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vivado_18392.backup.log
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#-----------------------------------------------------------
# Vivado v2019.2 (64-bit)
# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019
# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
# Start of session at: Thu Feb 2 13:54:37 2023
# Process ID: 18392
# Current directory: E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent6112 E:\files\A0_fpga_learn\ZYNQ_7010_FPGA\e203_7010\e203_7010.xpr
# Log file: E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/vivado.log
# Journal file: E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010\vivado.jou
#-----------------------------------------------------------
start_gui
open_project E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.xpr
INFO: [Project 1-313] Project file moved from 'E:/cache/ZYNQ_7010_FPGA/e203_7010' since last save.
CRITICAL WARNING: [Project 1-311] Could not find the file 'E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/hdl/mmcm_wrapper.v', nor could it be found using path 'E:/cache/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/hdl/mmcm_wrapper.v'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.2/data/ip'.
WARNING: [BD 41-1661] One or more IPs have been locked in the design 'ip_mmcm.bd'. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
ip_mmcm_clk_wiz_0_0
INFO: [Project 1-230] Project 'e203_7010.xpr' upgraded for this version of Vivado.
report_ip_status -name ip_status
update_compile_order -fileset sources_1
WARNING: [Vivado 12-4173] The following IPs are not generated and locked, no out-of-context (OOC) run will be created. Please select 'Report IP Status' from 'Tools/Report' or run Tcl command 'report_ip_status' for more information.
E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/ip_mmcm/ip_mmcm.bd
synth_design -rtl -name rtl_1
Command: synth_design -rtl -name rtl_1
Starting synth_design
Using part: xc7z010clg400-1
Top: system
INFO: [Device 21-403] Loading part xc7z010clg400-1
WARNING: [Synth 8-2507] parameter declaration becomes local in apb_uart_sv with formal parameter declaration list [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_uart/apb_uart.v:36]
WARNING: [Synth 8-2507] parameter declaration becomes local in apb_uart_sv with formal parameter declaration list [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_uart/apb_uart.v:38]
WARNING: [Synth 8-2507] parameter declaration becomes local in apb_uart_sv with formal parameter declaration list [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_uart/apb_uart.v:39]
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2359.594 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'system' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/zynq7010_e203/src/system.v:3]
INFO: [Synth 8-6157] synthesizing module 'ip_mmcm' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/ip_mmcm/synth/ip_mmcm.v:13]
INFO: [Synth 8-6157] synthesizing module 'ip_mmcm_clk_wiz_0_0' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/.Xil/Vivado-18392-DESKTOP-ELTC2F5/realtime/ip_mmcm_clk_wiz_0_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'ip_mmcm_clk_wiz_0_0' (1#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/.Xil/Vivado-18392-DESKTOP-ELTC2F5/realtime/ip_mmcm_clk_wiz_0_0_stub.v:5]
INFO: [Synth 8-6155] done synthesizing module 'ip_mmcm' (2#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/ip_mmcm/synth/ip_mmcm.v:13]
INFO: [Synth 8-6157] synthesizing module 'reset_sys' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/synth/reset_sys.v:13]
INFO: [Synth 8-638] synthesizing module 'reset_sys_proc_sys_reset_0_0' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ip/reset_sys_proc_sys_reset_0_0/synth/reset_sys_proc_sys_reset_0_0.vhd:74]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
Parameter C_EXT_RESET_HIGH bound to: 1'b0
Parameter C_AUX_RESET_HIGH bound to: 1'b0
Parameter C_NUM_BUS_RST bound to: 1 - type: integer
Parameter C_NUM_PERP_RST bound to: 1 - type: integer
Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer
Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer
INFO: [Synth 8-3491] module 'proc_sys_reset' declared at 'e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1264' bound to instance 'U0' of component 'proc_sys_reset' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ip/reset_sys_proc_sys_reset_0_0/synth/reset_sys_proc_sys_reset_0_0.vhd:129]
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
Parameter C_EXT_RESET_HIGH bound to: 1'b0
Parameter C_AUX_RESET_HIGH bound to: 1'b0
Parameter C_NUM_BUS_RST bound to: 1 - type: integer
Parameter C_NUM_PERP_RST bound to: 1 - type: integer
Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer
Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer
Parameter INIT bound to: 1'b1
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1392]
Parameter INIT bound to: 1'b1
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1408]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1434]
Parameter INIT bound to: 1'b1
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1457]
Parameter INIT bound to: 1'b0
Parameter IS_C_INVERTED bound to: 1'b0
Parameter IS_D_INVERTED bound to: 1'b0
Parameter IS_R_INVERTED bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1481]
INFO: [Synth 8-638] synthesizing module 'lpf' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
Parameter C_EXT_RESET_HIGH bound to: 1'b0
Parameter C_AUX_RESET_HIGH bound to: 1'b0
INFO: [Synth 8-3491] module 'SRL16' declared at 'D:/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:77949' bound to instance 'POR_SRL_I' of component 'SRL16' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:868]
INFO: [Synth 8-6157] synthesizing module 'SRL16' [D:/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:77949]
Parameter INIT bound to: 16'b0000000000000000
INFO: [Synth 8-6155] done synthesizing module 'SRL16' (3#1) [D:/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:77949]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter C_CDC_TYPE bound to: 1 - type: integer
Parameter C_RESET_STATE bound to: 0 - type: integer
Parameter C_SINGLE_BIT bound to: 1 - type: integer
Parameter C_FLOP_INPUT bound to: 0 - type: integer
Parameter C_VECTOR_WIDTH bound to: 2 - type: integer
Parameter C_MTBF_STAGES bound to: 4 - type: integer
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584]
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (4#1) [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-256] done synthesizing module 'lpf' (5#1) [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:816]
INFO: [Synth 8-638] synthesizing module 'sequence_psr' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301]
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125]
Parameter C_SIZE bound to: 6 - type: integer
INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (6#1) [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:125]
INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (7#1) [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:301]
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (8#1) [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1323]
INFO: [Synth 8-256] done synthesizing module 'reset_sys_proc_sys_reset_0_0' (9#1) [e:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/ip/reset_sys_proc_sys_reset_0_0/synth/reset_sys_proc_sys_reset_0_0.vhd:74]
INFO: [Synth 8-6155] done synthesizing module 'reset_sys' (10#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/bd/reset_sys/synth/reset_sys.v:13]
INFO: [Synth 8-6157] synthesizing module 'PULLUP' [D:/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:69974]
INFO: [Synth 8-6155] done synthesizing module 'PULLUP' (11#1) [D:/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:69974]
INFO: [Synth 8-6157] synthesizing module 'IOBUF' [D:/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:36196]
Parameter DRIVE bound to: 12 - type: integer
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter SLEW bound to: SLOW - type: string
INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (12#1) [D:/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:36196]
INFO: [Synth 8-6157] synthesizing module 'IOBUF__parameterized0' [D:/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:36196]
Parameter DRIVE bound to: 12 - type: integer
Parameter IBUF_LOW_PWR bound to: TRUE - type: string
Parameter IOSTANDARD bound to: DEFAULT - type: string
Parameter SLEW bound to: SLOW - type: string
INFO: [Synth 8-6155] done synthesizing module 'IOBUF__parameterized0' (12#1) [D:/Xilinx/Vivado/2019.2/scripts/rt/data/unisim_comp.v:36196]
INFO: [Synth 8-6157] synthesizing module 'e203_soc_top' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/soc/e203_soc_top.v:19]
INFO: [Synth 8-6157] synthesizing module 'e203_subsys_top' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/subsys/e203_subsys_top.v:31]
INFO: [Synth 8-6157] synthesizing module 'e203_subsys_main' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/subsys/e203_subsys_main.v:32]
INFO: [Synth 8-6157] synthesizing module 'sirv_ResetCatchAndSync_2' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/sirv_ResetCatchAndSync_2.v:19]
INFO: [Synth 8-6157] synthesizing module 'sirv_AsyncResetRegVec_129' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/sirv_AsyncResetRegVec_129.v:19]
INFO: [Synth 8-6157] synthesizing module 'sirv_AsyncResetReg' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/sirv_AsyncResetReg.v:19]
INFO: [Synth 8-6155] done synthesizing module 'sirv_AsyncResetReg' (13#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/sirv_AsyncResetReg.v:19]
INFO: [Synth 8-6155] done synthesizing module 'sirv_AsyncResetRegVec_129' (14#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/sirv_AsyncResetRegVec_129.v:19]
INFO: [Synth 8-6155] done synthesizing module 'sirv_ResetCatchAndSync_2' (15#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/sirv_ResetCatchAndSync_2.v:19]
INFO: [Synth 8-6157] synthesizing module 'e203_subsys_hclkgen' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/subsys/e203_subsys_hclkgen.v:31]
INFO: [Synth 8-6157] synthesizing module 'e203_subsys_pll' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/subsys/e203_subsys_pll.v:31]
INFO: [Synth 8-6155] done synthesizing module 'e203_subsys_pll' (16#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/subsys/e203_subsys_pll.v:31]
INFO: [Synth 8-6157] synthesizing module 'e203_subsys_hclkgen_rstsync' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/subsys/e203_subsys_hclkgen_rstsync.v:29]
Parameter RST_SYNC_LEVEL bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'e203_subsys_hclkgen_rstsync' (17#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/subsys/e203_subsys_hclkgen_rstsync.v:29]
INFO: [Synth 8-6157] synthesizing module 'e203_subsys_pllclkdiv' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/subsys/e203_subsys_pllclkdiv.v:31]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dfflr' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
Parameter DW bound to: 6 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dfflr' (18#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dfflr__parameterized0' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
Parameter DW bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dfflr__parameterized0' (18#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
INFO: [Synth 8-6157] synthesizing module 'e203_clkgate' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_clkgate.v:28]
INFO: [Synth 8-6155] done synthesizing module 'e203_clkgate' (19#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_clkgate.v:28]
INFO: [Synth 8-6155] done synthesizing module 'e203_subsys_pllclkdiv' (20#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/subsys/e203_subsys_pllclkdiv.v:31]
INFO: [Synth 8-6157] synthesizing module 'e203_subsys_gfcm' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/subsys/e203_subsys_gfcm.v:31]
Parameter SYNC_LEVEL bound to: 3 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'e203_subsys_gfcm' (21#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/subsys/e203_subsys_gfcm.v:31]
INFO: [Synth 8-6155] done synthesizing module 'e203_subsys_hclkgen' (22#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/subsys/e203_subsys_hclkgen.v:31]
INFO: [Synth 8-6157] synthesizing module 'e203_cpu_top' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_cpu_top.v:30]
INFO: [Synth 8-6157] synthesizing module 'e203_cpu' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_cpu.v:30]
Parameter MASTER bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'e203_reset_ctrl' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_reset_ctrl.v:29]
Parameter MASTER bound to: 1 - type: integer
Parameter RST_SYNC_LEVEL bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'e203_reset_ctrl' (23#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_reset_ctrl.v:29]
INFO: [Synth 8-6157] synthesizing module 'e203_clk_ctrl' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_clk_ctrl.v:30]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dffr' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:209]
Parameter DW bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dffr' (24#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:209]
INFO: [Synth 8-6155] done synthesizing module 'e203_clk_ctrl' (25#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_clk_ctrl.v:30]
INFO: [Synth 8-6157] synthesizing module 'e203_irq_sync' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_irq_sync.v:29]
Parameter MASTER bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_sync' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:99]
Parameter DP bound to: 2 - type: integer
Parameter DW bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_sync' (26#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:99]
INFO: [Synth 8-6155] done synthesizing module 'e203_irq_sync' (27#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_irq_sync.v:29]
INFO: [Synth 8-6157] synthesizing module 'e203_subsys_nice_core' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/subsys/e203_subsys_nice_core.v:28]
Parameter ROWBUF_DP bound to: 4 - type: integer
Parameter ROWBUF_IDX_W bound to: 2 - type: integer
Parameter ROW_IDX_W bound to: 2 - type: integer
Parameter COL_IDX_W bound to: 4 - type: integer
Parameter PIPE_NUM bound to: 3 - type: integer
Parameter NICE_FSM_WIDTH bound to: 2 - type: integer
Parameter IDLE bound to: 2'b00
Parameter LBUF bound to: 2'b01
Parameter SBUF bound to: 2'b10
Parameter ROWSUM bound to: 2'b11
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dfflr__parameterized1' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
Parameter DW bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dfflr__parameterized1' (27#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dfflr__parameterized2' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
Parameter DW bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dfflr__parameterized2' (27#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
INFO: [Synth 8-6155] done synthesizing module 'e203_subsys_nice_core' (28#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/subsys/e203_subsys_nice_core.v:28]
INFO: [Synth 8-6157] synthesizing module 'e203_core' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_core.v:30]
INFO: [Synth 8-6157] synthesizing module 'e203_ifu' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_ifu.v:29]
INFO: [Synth 8-6157] synthesizing module 'e203_ifu_ifetch' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_ifu_ifetch.v:29]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dffrs' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:177]
Parameter DW bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dffrs' (29#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:177]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dfflr__parameterized3' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
Parameter DW bound to: 16 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dfflr__parameterized3' (29#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dfflr__parameterized4' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
Parameter DW bound to: 5 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dfflr__parameterized4' (29#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
INFO: [Synth 8-6157] synthesizing module 'e203_ifu_minidec' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_ifu_minidec.v:28]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_decode' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_decode.v:29]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_decode' (30#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_decode.v:29]
INFO: [Synth 8-6155] done synthesizing module 'e203_ifu_minidec' (31#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_ifu_minidec.v:28]
INFO: [Synth 8-6157] synthesizing module 'e203_ifu_litebpu' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_ifu_litebpu.v:28]
INFO: [Synth 8-6155] done synthesizing module 'e203_ifu_litebpu' (32#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_ifu_litebpu.v:28]
INFO: [Synth 8-6155] done synthesizing module 'e203_ifu_ifetch' (33#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_ifu_ifetch.v:29]
INFO: [Synth 8-6157] synthesizing module 'e203_ifu_ift2icb' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_ifu_ift2icb.v:30]
Parameter ICB_STATE_WIDTH bound to: 2 - type: integer
Parameter ICB_STATE_IDLE bound to: 2'b00
Parameter ICB_STATE_1ST bound to: 2'b01
Parameter ICB_STATE_WAIT2ND bound to: 2'b10
Parameter ICB_STATE_2ND bound to: 2'b11
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_bypbuf' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:306]
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 33 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_fifo' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:381]
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 0 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 33 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dffl' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
Parameter DW bound to: 33 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dffl' (34#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dfflrs' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:40]
Parameter DW bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dfflrs' (35#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:40]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_fifo' (36#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:381]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_bypbuf' (37#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:306]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dffl__parameterized0' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
Parameter DW bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dffl__parameterized0' (37#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dffl__parameterized1' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
Parameter DW bound to: 16 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dffl__parameterized1' (37#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
INFO: [Synth 8-6155] done synthesizing module 'e203_ifu_ift2icb' (38#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_ifu_ift2icb.v:30]
INFO: [Synth 8-6155] done synthesizing module 'e203_ifu' (39#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_ifu.v:29]
INFO: [Synth 8-6157] synthesizing module 'e203_exu' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu.v:29]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_regfile' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_regfile.v:28]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dffl__parameterized2' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
Parameter DW bound to: 32 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dffl__parameterized2' (39#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_regfile' (40#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_regfile.v:28]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_disp' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_disp.v:29]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_disp' (41#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_disp.v:29]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_oitf' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_oitf.v:29]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dffl__parameterized3' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
Parameter DW bound to: 5 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dffl__parameterized3' (41#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dffl__parameterized4' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
Parameter DW bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dffl__parameterized4' (41#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_oitf' (42#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_oitf.v:29]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_alu' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_alu.v:32]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_nice' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_nice.v:30]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_fifo__parameterized0' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:381]
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 0 - type: integer
Parameter DP bound to: 4 - type: integer
Parameter DW bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dfflr__parameterized5' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
Parameter DW bound to: 3 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dfflr__parameterized5' (42#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dfflr__parameterized6' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
Parameter DW bound to: 4 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dfflr__parameterized6' (42#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:87]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_fifo__parameterized0' (42#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:381]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_nice' (43#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_nice.v:30]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_alu_csrctrl' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_alu_csrctrl.v:29]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_alu_csrctrl' (44#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_alu_csrctrl.v:29]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_alu_bjp' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_alu_bjp.v:32]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_alu_bjp' (45#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_alu_bjp.v:32]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_alu_lsuagu' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_alu_lsuagu.v:32]
Parameter ICB_STATE_WIDTH bound to: 4 - type: integer
Parameter ICB_STATE_IDLE bound to: 4'b0000
Parameter ICB_STATE_1ST bound to: 4'b0001
Parameter ICB_STATE_WAIT2ND bound to: 4'b0010
Parameter ICB_STATE_2ND bound to: 4'b0011
Parameter ICB_STATE_AMOALU bound to: 4'b0100
Parameter ICB_STATE_AMORDY bound to: 4'b0101
Parameter ICB_STATE_WBCK bound to: 4'b0110
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_alu_lsuagu' (46#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_alu_lsuagu.v:32]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_alu_rglr' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_alu_rglr.v:30]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_alu_rglr' (47#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_alu_rglr.v:30]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_alu_muldiv' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_alu_muldiv.v:32]
Parameter MULDIV_STATE_WIDTH bound to: 3 - type: integer
Parameter MULDIV_STATE_0TH bound to: 3'b000
Parameter MULDIV_STATE_EXEC bound to: 3'b001
Parameter MULDIV_STATE_REMD_CHCK bound to: 3'b010
Parameter MULDIV_STATE_QUOT_CORR bound to: 3'b011
Parameter MULDIV_STATE_REMD_CORR bound to: 3'b100
Parameter EXEC_CNT_W bound to: 6 - type: integer
Parameter EXEC_CNT_1 bound to: 6'b000001
Parameter EXEC_CNT_16 bound to: 6'b010000
Parameter EXEC_CNT_32 bound to: 6'b100000
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_alu_muldiv' (48#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_alu_muldiv.v:32]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_alu_dpath' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_alu_dpath.v:29]
Parameter DPATH_MUX_WIDTH bound to: 85 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_alu_dpath' (49#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_alu_dpath.v:29]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_alu' (50#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_alu.v:32]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_longpwbck' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_longpwbck.v:30]
WARNING: [Synth 8-693] zero replication count - replication ignored [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_longpwbck.v:141]
WARNING: [Synth 8-693] zero replication count - replication ignored [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_longpwbck.v:144]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_longpwbck' (51#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_longpwbck.v:30]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_wbck' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_wbck.v:30]
WARNING: [Synth 8-693] zero replication count - replication ignored [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_wbck.v:93]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_wbck' (52#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_wbck.v:30]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_commit' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_commit.v:31]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_branchslv' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_branchslv.v:30]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_branchslv' (53#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_branchslv.v:30]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_excp' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_excp.v:29]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_excp' (54#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_excp.v:29]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_commit' (55#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_commit.v:31]
INFO: [Synth 8-6157] synthesizing module 'e203_exu_csr' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_csr.v:29]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu_csr' (56#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu_csr.v:29]
INFO: [Synth 8-6155] done synthesizing module 'e203_exu' (57#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_exu.v:29]
INFO: [Synth 8-6157] synthesizing module 'e203_lsu' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_lsu.v:28]
INFO: [Synth 8-6157] synthesizing module 'e203_lsu_ctrl' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_lsu_ctrl.v:28]
Parameter LSU_ARBT_I_PTR_W bound to: 1 - type: integer
Parameter LSU_ARBT_I_NUM bound to: 2 - type: integer
Parameter USR_W bound to: 39 - type: integer
Parameter USR_PACK_EXCL bound to: 0 - type: integer
Parameter SPLT_FIFO_W bound to: 44 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_icb_arbt' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_icbs.v:37]
Parameter AW bound to: 32 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter USR_W bound to: 39 - type: integer
Parameter ARBT_SCHEME bound to: 0 - type: integer
Parameter FIFO_OUTS_NUM bound to: 1 - type: integer
Parameter FIFO_CUT_READY bound to: 0 - type: integer
Parameter ARBT_NUM bound to: 2 - type: integer
Parameter ALLOW_0CYCL_RSP bound to: 0 - type: integer
Parameter ARBT_PTR_W bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_pipe_stage' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:28]
Parameter CUT_READY bound to: 0 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_pipe_stage' (58#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:28]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_icb_arbt' (59#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_icbs.v:37]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_pipe_stage__parameterized0' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:28]
Parameter CUT_READY bound to: 0 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 44 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dffl__parameterized5' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
Parameter DW bound to: 44 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dffl__parameterized5' (59#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_pipe_stage__parameterized0' (59#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:28]
INFO: [Synth 8-6155] done synthesizing module 'e203_lsu_ctrl' (60#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_lsu_ctrl.v:28]
INFO: [Synth 8-6155] done synthesizing module 'e203_lsu' (61#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_lsu.v:28]
INFO: [Synth 8-6157] synthesizing module 'e203_biu' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_biu.v:29]
Parameter BIU_ARBT_I_NUM bound to: 2 - type: integer
Parameter BIU_ARBT_I_PTR_W bound to: 1 - type: integer
Parameter BIU_SPLT_I_NUM_0 bound to: 4 - type: integer
Parameter BIU_SPLT_I_NUM_1 bound to: 5 - type: integer
Parameter BIU_SPLT_I_NUM_2 bound to: 6 - type: integer
Parameter BIU_SPLT_I_NUM bound to: 6 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_icb_arbt__parameterized0' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_icbs.v:37]
Parameter AW bound to: 32 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter USR_W bound to: 1 - type: integer
Parameter ARBT_SCHEME bound to: 0 - type: integer
Parameter FIFO_OUTS_NUM bound to: 1 - type: integer
Parameter FIFO_CUT_READY bound to: 1 - type: integer
Parameter ARBT_NUM bound to: 2 - type: integer
Parameter ALLOW_0CYCL_RSP bound to: 0 - type: integer
Parameter ARBT_PTR_W bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_pipe_stage__parameterized1' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:28]
Parameter CUT_READY bound to: 1 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_pipe_stage__parameterized1' (61#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:28]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_icb_arbt__parameterized0' (61#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_icbs.v:37]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_icb_buffer' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_icbs.v:351]
Parameter OUTS_CNT_W bound to: 1 - type: integer
Parameter AW bound to: 32 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter CMD_CUT_READY bound to: 1 - type: integer
Parameter RSP_CUT_READY bound to: 1 - type: integer
Parameter CMD_DP bound to: 1 - type: integer
Parameter RSP_DP bound to: 1 - type: integer
Parameter USR_W bound to: 1 - type: integer
Parameter CMD_PACK_W bound to: 78 - type: integer
Parameter RSP_PACK_W bound to: 35 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_fifo__parameterized1' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:381]
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 0 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 78 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dffl__parameterized6' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
Parameter DW bound to: 78 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dffl__parameterized6' (61#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_fifo__parameterized1' (61#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:381]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_fifo__parameterized2' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:381]
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 0 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 35 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dffl__parameterized7' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
Parameter DW bound to: 35 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dffl__parameterized7' (61#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_fifo__parameterized2' (61#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:381]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_icb_buffer' (62#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_icbs.v:351]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_icb_splt' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_icbs.v:648]
Parameter AW bound to: 32 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter FIFO_OUTS_NUM bound to: 1 - type: integer
Parameter FIFO_CUT_READY bound to: 1 - type: integer
Parameter SPLT_NUM bound to: 6 - type: integer
Parameter SPLT_PTR_1HOT bound to: 1 - type: integer
Parameter SPLT_PTR_W bound to: 6 - type: integer
Parameter ALLOW_DIFF bound to: 0 - type: integer
Parameter ALLOW_0CYCL_RSP bound to: 1 - type: integer
Parameter VLD_MSK_PAYLOAD bound to: 0 - type: integer
Parameter USR_W bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_pipe_stage__parameterized2' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:28]
Parameter CUT_READY bound to: 1 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 6 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dffl__parameterized8' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
Parameter DW bound to: 6 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dffl__parameterized8' (62#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_pipe_stage__parameterized2' (62#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:28]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_icb_splt' (63#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_icbs.v:648]
INFO: [Synth 8-6155] done synthesizing module 'e203_biu' (64#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_biu.v:29]
INFO: [Synth 8-6155] done synthesizing module 'e203_core' (65#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_core.v:30]
INFO: [Synth 8-6157] synthesizing module 'e203_itcm_ctrl' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_itcm_ctrl.v:31]
Parameter ITCM_ARBT_I_NUM bound to: 2 - type: integer
Parameter ITCM_ARBT_I_PTR_W bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_icb_n2w' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_icbs.v:503]
Parameter AW bound to: 16 - type: integer
Parameter USR_W bound to: 1 - type: integer
Parameter FIFO_OUTS_NUM bound to: 1 - type: integer
Parameter FIFO_CUT_READY bound to: 0 - type: integer
Parameter X_W bound to: 32 - type: integer
Parameter Y_W bound to: 64 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_icb_n2w' (66#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_icbs.v:503]
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_icb_arbt__parameterized1' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_icbs.v:37]
Parameter AW bound to: 16 - type: integer
Parameter DW bound to: 64 - type: integer
Parameter USR_W bound to: 1 - type: integer
Parameter ARBT_SCHEME bound to: 0 - type: integer
Parameter FIFO_OUTS_NUM bound to: 1 - type: integer
Parameter FIFO_CUT_READY bound to: 0 - type: integer
Parameter ARBT_NUM bound to: 2 - type: integer
Parameter ALLOW_0CYCL_RSP bound to: 0 - type: integer
Parameter ARBT_PTR_W bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_icb_arbt__parameterized1' (66#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_icbs.v:37]
INFO: [Synth 8-6157] synthesizing module 'sirv_sram_icb_ctrl' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_sram_icb_ctrl.v:29]
Parameter DW bound to: 64 - type: integer
Parameter MW bound to: 8 - type: integer
Parameter AW bound to: 16 - type: integer
Parameter AW_LSB bound to: 3 - type: integer
Parameter USR_W bound to: 2 - type: integer
Parameter BUF_CMD_PACK_W bound to: 91 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_bypbuf__parameterized0' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:306]
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 91 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_fifo__parameterized3' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:381]
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 0 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 91 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_dffl__parameterized9' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
Parameter DW bound to: 91 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dffl__parameterized9' (66#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_fifo__parameterized3' (66#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:381]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_bypbuf__parameterized0' (66#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:306]
INFO: [Synth 8-6157] synthesizing module 'sirv_1cyc_sram_ctrl' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_1cyc_sram_ctrl.v:29]
Parameter DW bound to: 64 - type: integer
Parameter MW bound to: 8 - type: integer
Parameter AW bound to: 16 - type: integer
Parameter AW_LSB bound to: 3 - type: integer
Parameter USR_W bound to: 2 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_pipe_stage__parameterized3' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:28]
Parameter CUT_READY bound to: 0 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 2 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_pipe_stage__parameterized3' (66#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:28]
INFO: [Synth 8-6155] done synthesizing module 'sirv_1cyc_sram_ctrl' (67#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_1cyc_sram_ctrl.v:29]
INFO: [Synth 8-6155] done synthesizing module 'sirv_sram_icb_ctrl' (68#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_sram_icb_ctrl.v:29]
INFO: [Synth 8-6155] done synthesizing module 'e203_itcm_ctrl' (69#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_itcm_ctrl.v:31]
INFO: [Synth 8-6157] synthesizing module 'e203_dtcm_ctrl' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_dtcm_ctrl.v:31]
Parameter DTCM_ARBT_I_NUM bound to: 2 - type: integer
Parameter DTCM_ARBT_I_PTR_W bound to: 1 - type: integer
INFO: [Synth 8-6157] synthesizing module 'sirv_gnrl_icb_arbt__parameterized2' [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_icbs.v:37]
INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Parameter AW bound to: 16 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter USR_W bound to: 1 - type: integer
Parameter ARBT_SCHEME bound to: 0 - type: integer
Parameter FIFO_OUTS_NUM bound to: 1 - type: integer
Parameter FIFO_CUT_READY bound to: 0 - type: integer
Parameter ARBT_NUM bound to: 2 - type: integer
Parameter ALLOW_0CYCL_RSP bound to: 0 - type: integer
Parameter ARBT_PTR_W bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_icb_arbt__parameterized2' (69#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_icbs.v:37]
Parameter DW bound to: 32 - type: integer
Parameter MW bound to: 4 - type: integer
Parameter AW bound to: 16 - type: integer
Parameter AW_LSB bound to: 2 - type: integer
Parameter USR_W bound to: 1 - type: integer
Parameter BUF_CMD_PACK_W bound to: 54 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 54 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 0 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 54 - type: integer
Parameter DW bound to: 54 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_dffl__parameterized10' (69#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_dffs.v:133]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_fifo__parameterized4' (69#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:381]
INFO: [Synth 8-6155] done synthesizing module 'sirv_gnrl_bypbuf__parameterized1' (69#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_gnrl_bufs.v:306]
Parameter DW bound to: 32 - type: integer
Parameter MW bound to: 4 - type: integer
Parameter AW bound to: 16 - type: integer
Parameter AW_LSB bound to: 2 - type: integer
Parameter USR_W bound to: 1 - type: integer
INFO: [Synth 8-6155] done synthesizing module 'sirv_1cyc_sram_ctrl__parameterized0' (69#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_1cyc_sram_ctrl.v:29]
INFO: [Synth 8-6155] done synthesizing module 'sirv_sram_icb_ctrl__parameterized0' (69#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/general/sirv_sram_icb_ctrl.v:29]
INFO: [Synth 8-6155] done synthesizing module 'e203_dtcm_ctrl' (70#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_dtcm_ctrl.v:31]
INFO: [Synth 8-6155] done synthesizing module 'e203_cpu' (71#1) [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/core/e203_cpu.v:30]
INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Parameter DP bound to: 8192 - type: integer
Parameter DW bound to: 64 - type: integer
Parameter FORCE_X2ZERO bound to: 0 - type: integer
Parameter MW bound to: 8 - type: integer
Parameter AW bound to: 13 - type: integer
Parameter DP bound to: 8192 - type: integer
Parameter FORCE_X2ZERO bound to: 1'b0
Parameter DW bound to: 64 - type: integer
Parameter MW bound to: 8 - type: integer
Parameter AW bound to: 13 - type: integer
Parameter DP bound to: 16384 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter FORCE_X2ZERO bound to: 1 - type: integer
Parameter MW bound to: 4 - type: integer
Parameter AW bound to: 14 - type: integer
Parameter DP bound to: 16384 - type: integer
Parameter FORCE_X2ZERO bound to: 1'b0
Parameter DW bound to: 32 - type: integer
Parameter MW bound to: 4 - type: integer
Parameter AW bound to: 14 - type: integer
Parameter PLIC_IRQ_NUM bound to: 17 - type: integer
Parameter PLIC_PRIO_WIDTH bound to: 3 - type: integer
Parameter PLIC_IRQ_NUM bound to: 17 - type: integer
Parameter PLIC_IRQ_NUM_LOG2 bound to: 6 - type: integer
Parameter PLIC_ICB_RSP_FLOP bound to: 1 - type: integer
Parameter PLIC_IRQ_I_FLOP bound to: 1 - type: integer
Parameter PLIC_IRQ_O_FLOP bound to: 1 - type: integer
Parameter PLIC_PEND_ARRAY bound to: 1 - type: integer
Parameter DW bound to: 17 - type: integer
Parameter DW bound to: 6 - type: integer
Parameter DW bound to: 3 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter CMD_PACK_W bound to: 65 - type: integer
Parameter RSP_PACK_W bound to: 33 - type: integer
Parameter ICB_FIFO_DP bound to: 2 - type: integer
Parameter ICB_FIFO_CUT_READY bound to: 1 - type: integer
Parameter AW bound to: 32 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter SPLT_FIFO_OUTS_NUM bound to: 1 - type: integer
Parameter SPLT_FIFO_CUT_READY bound to: 1 - type: integer
Parameter O0_BASE_ADDR bound to: 268435456 - type: integer
Parameter O0_BASE_REGION_LSB bound to: 15 - type: integer
Parameter O1_BASE_ADDR bound to: 268468224 - type: integer
Parameter O1_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O2_BASE_ADDR bound to: 268509184 - type: integer
Parameter O2_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O3_BASE_ADDR bound to: 268513280 - type: integer
Parameter O3_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O4_BASE_ADDR bound to: 268517376 - type: integer
Parameter O4_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O5_BASE_ADDR bound to: 268521472 - type: integer
Parameter O5_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O6_BASE_ADDR bound to: 268578816 - type: integer
Parameter O6_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O7_BASE_ADDR bound to: 268582912 - type: integer
Parameter O7_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O8_BASE_ADDR bound to: 268587008 - type: integer
Parameter O8_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O9_BASE_ADDR bound to: 268644352 - type: integer
Parameter O9_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O10_BASE_ADDR bound to: 268648448 - type: integer
Parameter O10_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O11_BASE_ADDR bound to: 268652544 - type: integer
Parameter O11_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O12_BASE_ADDR bound to: 285212672 - type: integer
Parameter O12_BASE_REGION_LSB bound to: 24 - type: integer
Parameter O13_BASE_ADDR bound to: 268697600 - type: integer
Parameter O13_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O14_BASE_ADDR bound to: 268701696 - type: integer
Parameter O14_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O15_BASE_ADDR bound to: 268705792 - type: integer
Parameter O15_BASE_REGION_LSB bound to: 3 - type: integer
Parameter BASE_REGION_MSB bound to: 31 - type: integer
Parameter SPLT_I_NUM bound to: 17 - type: integer
Parameter OUTS_CNT_W bound to: 1 - type: integer
Parameter AW bound to: 32 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter CMD_CUT_READY bound to: 1 - type: integer
Parameter RSP_CUT_READY bound to: 1 - type: integer
Parameter CMD_DP bound to: 2 - type: integer
Parameter RSP_DP bound to: 2 - type: integer
Parameter USR_W bound to: 1 - type: integer
Parameter CMD_PACK_W bound to: 78 - type: integer
Parameter RSP_PACK_W bound to: 35 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 0 - type: integer
Parameter DP bound to: 2 - type: integer
Parameter DW bound to: 78 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 0 - type: integer
Parameter DP bound to: 2 - type: integer
Parameter DW bound to: 35 - type: integer
Parameter AW bound to: 32 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter FIFO_OUTS_NUM bound to: 1 - type: integer
Parameter FIFO_CUT_READY bound to: 1 - type: integer
Parameter SPLT_NUM bound to: 17 - type: integer
Parameter SPLT_PTR_1HOT bound to: 1 - type: integer
Parameter SPLT_PTR_W bound to: 17 - type: integer
Parameter ALLOW_DIFF bound to: 0 - type: integer
Parameter ALLOW_0CYCL_RSP bound to: 1 - type: integer
Parameter VLD_MSK_PAYLOAD bound to: 1 - type: integer
Parameter USR_W bound to: 1 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 17 - type: integer
Parameter DW bound to: 17 - type: integer
WARNING: [Synth 8-6014] Unused sequential element T_1514_reg was removed. [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/sirv_tlwidthwidget_qspi.v:386]
WARNING: [Synth 8-6014] Unused sequential element a_opcode_reg was removed. [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/sirv_flash_qspi.v:2220]
WARNING: [Synth 8-6014] Unused sequential element a_param_reg was removed. [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/sirv_flash_qspi.v:2221]
WARNING: [Synth 8-6014] Unused sequential element a_mask_reg was removed. [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/sirv_flash_qspi.v:2225]
WARNING: [Synth 8-6014] Unused sequential element a_data_reg was removed. [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/sirv_flash_qspi.v:2226]
Parameter DW bound to: 65 - type: integer
Parameter SYNC_DP bound to: 2 - type: integer
Parameter DW bound to: 65 - type: integer
Parameter DW bound to: 33 - type: integer
Parameter SYNC_DP bound to: 2 - type: integer
Parameter DW bound to: 33 - type: integer
Parameter AW bound to: 32 - type: integer
Parameter FIFO_OUTS_NUM bound to: 8 - type: integer
Parameter FIFO_CUT_READY bound to: 0 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 0 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter APB_ADDR_WIDTH bound to: 32 - type: integer
INFO: [Synth 8-155] case statement is not full and has no default [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_gpio/apb_gpio.v:132]
INFO: [Synth 8-226] default block is never used [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_gpio/apb_gpio.v:193]
Parameter APB_ADDR_WIDTH bound to: 32 - type: integer
Parameter RBR bound to: 3'b000
Parameter THR bound to: 3'b000
Parameter DLL bound to: 3'b000
Parameter IER bound to: 3'b001
Parameter DLM bound to: 3'b001
Parameter IIR bound to: 3'b010
Parameter FCR bound to: 3'b010
Parameter LCR bound to: 3'b011
Parameter MCR bound to: 3'b100
Parameter LSR bound to: 3'b101
Parameter MSR bound to: 3'b110
Parameter SCR bound to: 3'b111
Parameter TX_FIFO_DEPTH bound to: 16 - type: integer
Parameter RX_FIFO_DEPTH bound to: 16 - type: integer
Parameter IDLE bound to: 3'b000
Parameter START_BIT bound to: 3'b001
Parameter DATA bound to: 3'b010
Parameter SAVE_DATA bound to: 3'b011
Parameter PARITY bound to: 3'b100
Parameter STOP_BIT bound to: 3'b101
Parameter IDLE bound to: 3'b000
Parameter START_BIT bound to: 3'b001
Parameter DATA bound to: 3'b010
Parameter PARITY bound to: 3'b011
Parameter STOP_BIT_FIRST bound to: 3'b100
Parameter STOP_BIT_LAST bound to: 3'b101
Parameter DATA_WIDTH bound to: 9 - type: integer
Parameter BUFFER_DEPTH bound to: 16 - type: integer
Parameter LOG_BUFFER_DEPTH bound to: 4 - type: integer
Parameter DATA_WIDTH bound to: 8 - type: integer
Parameter BUFFER_DEPTH bound to: 16 - type: integer
Parameter LOG_BUFFER_DEPTH bound to: 4 - type: integer
Parameter TX_FIFO_DEPTH bound to: 16 - type: integer
Parameter RX_FIFO_DEPTH bound to: 16 - type: integer
INFO: [Synth 8-155] case statement is not full and has no default [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_uart/apb_uart.v:181]
Parameter BUFFER_DEPTH bound to: 10 - type: integer
Parameter APB_ADDR_WIDTH bound to: 32 - type: integer
Parameter LOG_BUFFER_DEPTH bound to: 4 - type: integer
Parameter FILL_BITS bound to: 3 - type: integer
INFO: [Synth 8-155] case statement is not full and has no default [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_spi_master/apb_spi_master.v:124]
Parameter BUFFER_DEPTH bound to: 10 - type: integer
Parameter APB_ADDR_WIDTH bound to: 32 - type: integer
Parameter LOG_BUFFER_DEPTH bound to: 4 - type: integer
INFO: [Synth 8-155] case statement is not full and has no default [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_spi_master/spi_master_apb_if.v:109]
Parameter DATA_WIDTH bound to: 32 - type: integer
Parameter BUFFER_DEPTH bound to: 10 - type: integer
Parameter LOG_BUFFER_DEPTH bound to: 4 - type: integer
Parameter DATA_NULL bound to: 3'b000
Parameter DATA_EMPTY bound to: 3'b001
Parameter DATA_CMD bound to: 3'b010
Parameter DATA_ADDR bound to: 3'b011
Parameter DATA_FIFO bound to: 3'b100
Parameter IDLE bound to: 5'b00000
Parameter CMD bound to: 5'b00001
Parameter ADDR bound to: 5'b00010
Parameter MODE bound to: 5'b00011
Parameter DUMMY bound to: 5'b00100
Parameter DATA_TX bound to: 5'b00101
Parameter DATA_RX bound to: 5'b00110
Parameter WAIT_EDGE bound to: 5'b00111
Parameter IDLE bound to: 1'b0
Parameter TRANSMIT bound to: 1'b1
Parameter IDLE bound to: 2'b00
Parameter RECEIVE bound to: 2'b01
Parameter WAIT_FIFO bound to: 2'b10
Parameter WAIT_FIFO_DONE bound to: 2'b11
INFO: [Synth 8-155] case statement is not full and has no default [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_spi_master/spi_master_controller.v:172]
INFO: [Synth 8-155] case statement is not full and has no default [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_spi_master/spi_master_controller.v:215]
WARNING: [Synth 8-6014] Unused sequential element do_tx_reg was removed. [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_spi_master/spi_master_controller.v:468]
Parameter APB_ADDR_WIDTH bound to: 32 - type: integer
INFO: [Synth 8-155] case statement is not full and has no default [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_i2c/apb_i2c.v:96]
Parameter ST_IDLE bound to: 5'b00000
Parameter ST_START bound to: 5'b00001
Parameter ST_READ bound to: 5'b00010
Parameter ST_WRITE bound to: 5'b00100
Parameter ST_ACK bound to: 5'b01000
Parameter ST_STOP bound to: 5'b10000
Parameter idle bound to: 18'b000000000000000000
Parameter start_a bound to: 18'b000000000000000001
Parameter start_b bound to: 18'b000000000000000010
Parameter start_c bound to: 18'b000000000000000100
Parameter start_d bound to: 18'b000000000000001000
Parameter start_e bound to: 18'b000000000000010000
Parameter stop_a bound to: 18'b000000000000100000
Parameter stop_b bound to: 18'b000000000001000000
Parameter stop_c bound to: 18'b000000000010000000
Parameter stop_d bound to: 18'b000000000100000000
Parameter rd_a bound to: 18'b000000001000000000
Parameter rd_b bound to: 18'b000000010000000000
Parameter rd_c bound to: 18'b000000100000000000
Parameter rd_d bound to: 18'b000001000000000000
Parameter wr_a bound to: 18'b000010000000000000
Parameter wr_b bound to: 18'b000100000000000000
Parameter wr_c bound to: 18'b001000000000000000
Parameter wr_d bound to: 18'b010000000000000000
INFO: [Synth 8-3536] HDL ADVISOR - Pragma parallel_case detected. Simulation mismatch may occur [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_i2c/i2c_master_bit_ctrl.v:374]
INFO: [Synth 8-3536] HDL ADVISOR - Pragma full_case detected. Simulation mismatch may occur [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_i2c/i2c_master_bit_ctrl.v:374]
INFO: [Synth 8-3536] HDL ADVISOR - Pragma parallel_case detected. Simulation mismatch may occur [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_i2c/i2c_master_bit_ctrl.v:378]
INFO: [Synth 8-3536] HDL ADVISOR - Pragma full_case detected. Simulation mismatch may occur [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_i2c/i2c_master_bit_ctrl.v:378]
INFO: [Synth 8-3536] HDL ADVISOR - Pragma parallel_case detected. Simulation mismatch may occur [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_i2c/i2c_master_byte_ctrl.v:220]
INFO: [Synth 8-3536] HDL ADVISOR - Pragma full_case detected. Simulation mismatch may occur [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_i2c/i2c_master_byte_ctrl.v:220]
Parameter APB_ADDR_WIDTH bound to: 32 - type: integer
Parameter EXTSIG_NUM bound to: 32 - type: integer
Parameter TIMER_NBITS bound to: 16 - type: integer
Parameter N_TIMEREXTSIG bound to: 48 - type: integer
Parameter APB_ADDR_WIDTH bound to: 32 - type: integer
INFO: [Synth 8-155] case statement is not full and has no default [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/perips/apb_adv_timer/adv_timer_apb_if.v:626]
Parameter NUM_BITS bound to: 16 - type: integer
Parameter N_EXTSIG bound to: 48 - type: integer
Parameter EXTSIG_NUM bound to: 48 - type: integer
Parameter NUM_BITS bound to: 16 - type: integer
Parameter NUM_BITS bound to: 16 - type: integer
Parameter AXI_FIFO_DP bound to: 2 - type: integer
Parameter AXI_FIFO_CUT_READY bound to: 1 - type: integer
Parameter AW bound to: 32 - type: integer
Parameter FIFO_OUTS_NUM bound to: 1 - type: integer
Parameter FIFO_CUT_READY bound to: 1 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 1 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 1 - type: integer
Parameter CHNL_FIFO_DP bound to: 2 - type: integer
Parameter CHNL_FIFO_CUT_READY bound to: 1 - type: integer
Parameter AW bound to: 32 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter AR_CHNL_W bound to: 50 - type: integer
Parameter AW_CHNL_W bound to: 50 - type: integer
Parameter W_CHNL_W bound to: 37 - type: integer
Parameter R_CHNL_W bound to: 35 - type: integer
Parameter B_CHNL_W bound to: 2 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 0 - type: integer
Parameter DP bound to: 2 - type: integer
Parameter DW bound to: 50 - type: integer
Parameter DW bound to: 50 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 0 - type: integer
Parameter DP bound to: 2 - type: integer
Parameter DW bound to: 37 - type: integer
Parameter DW bound to: 37 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 0 - type: integer
Parameter DP bound to: 2 - type: integer
Parameter DW bound to: 2 - type: integer
Parameter AW bound to: 32 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter MROM_AW bound to: 12 - type: integer
Parameter MROM_DP bound to: 1024 - type: integer
Parameter ICB_FIFO_DP bound to: 2 - type: integer
Parameter ICB_FIFO_CUT_READY bound to: 1 - type: integer
Parameter AW bound to: 32 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter SPLT_FIFO_OUTS_NUM bound to: 1 - type: integer
Parameter SPLT_FIFO_CUT_READY bound to: 1 - type: integer
Parameter O0_BASE_ADDR bound to: 0 - type: integer
Parameter O0_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O1_BASE_ADDR bound to: 4096 - type: integer
Parameter O1_BASE_REGION_LSB bound to: 12 - type: integer
Parameter O2_BASE_ADDR bound to: 131072 - type: integer
Parameter O2_BASE_REGION_LSB bound to: 17 - type: integer
Parameter O3_BASE_ADDR bound to: 536870912 - type: integer
Parameter O3_BASE_REGION_LSB bound to: 29 - type: integer
Parameter O4_BASE_ADDR bound to: -2147483648 - type: integer
Parameter O4_BASE_REGION_LSB bound to: 31 - type: integer
Parameter O5_BASE_ADDR bound to: 1073741824 - type: integer
Parameter O5_BASE_REGION_LSB bound to: 28 - type: integer
Parameter O6_BASE_ADDR bound to: 0 - type: integer
Parameter O6_BASE_REGION_LSB bound to: 0 - type: integer
Parameter O7_BASE_ADDR bound to: 0 - type: integer
Parameter O7_BASE_REGION_LSB bound to: 0 - type: integer
Parameter BASE_REGION_MSB bound to: 31 - type: integer
Parameter SPLT_I_NUM bound to: 9 - type: integer
Parameter AW bound to: 32 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter FIFO_OUTS_NUM bound to: 1 - type: integer
Parameter FIFO_CUT_READY bound to: 1 - type: integer
Parameter SPLT_NUM bound to: 9 - type: integer
Parameter SPLT_PTR_1HOT bound to: 1 - type: integer
Parameter SPLT_PTR_W bound to: 9 - type: integer
Parameter ALLOW_DIFF bound to: 0 - type: integer
Parameter ALLOW_0CYCL_RSP bound to: 1 - type: integer
Parameter VLD_MSK_PAYLOAD bound to: 1 - type: integer
Parameter USR_W bound to: 1 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 9 - type: integer
Parameter DW bound to: 9 - type: integer
Parameter AW bound to: 12 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter DP bound to: 1024 - type: integer
Parameter AW bound to: 12 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter DP bound to: 1024 - type: integer
Parameter AXI_FIFO_DP bound to: 2 - type: integer
Parameter AXI_FIFO_CUT_READY bound to: 1 - type: integer
Parameter AW bound to: 32 - type: integer
Parameter FIFO_OUTS_NUM bound to: 4 - type: integer
Parameter FIFO_CUT_READY bound to: 1 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 1 - type: integer
Parameter DP bound to: 4 - type: integer
Parameter DW bound to: 1 - type: integer
Parameter SUPPORT_JTAG_DTM bound to: 1 - type: integer
Parameter ASYNC_FF_LEVELS bound to: 2 - type: integer
Parameter PC_SIZE bound to: 32 - type: integer
Parameter HART_NUM bound to: 1 - type: integer
Parameter HART_ID_W bound to: 1 - type: integer
Parameter ASYNC_FF_LEVELS bound to: 2 - type: integer
Parameter DEBUG_DATA_BITS bound to: 34 - type: integer
Parameter DEBUG_ADDR_BITS bound to: 5 - type: integer
Parameter DEBUG_OP_BITS bound to: 2 - type: integer
Parameter JTAG_VERSION bound to: 4'b0001
Parameter DBUS_IDLE_CYCLES bound to: 3'b101
Parameter IR_BITS bound to: 5 - type: integer
Parameter DEBUG_VERSION bound to: 0 - type: integer
Parameter TEST_LOGIC_RESET bound to: 4'b0000
Parameter RUN_TEST_IDLE bound to: 4'b0001
Parameter SELECT_DR bound to: 4'b0010
Parameter CAPTURE_DR bound to: 4'b0011
Parameter SHIFT_DR bound to: 4'b0100
Parameter EXIT1_DR bound to: 4'b0101
Parameter PAUSE_DR bound to: 4'b0110
Parameter EXIT2_DR bound to: 4'b0111
Parameter UPDATE_DR bound to: 4'b1000
Parameter SELECT_IR bound to: 4'b1001
Parameter CAPTURE_IR bound to: 4'b1010
Parameter SHIFT_IR bound to: 4'b1011
Parameter EXIT1_IR bound to: 4'b1100
Parameter PAUSE_IR bound to: 4'b1101
Parameter EXIT2_IR bound to: 4'b1110
Parameter UPDATE_IR bound to: 4'b1111
Parameter REG_BYPASS bound to: 5'b11111
Parameter REG_IDCODE bound to: 5'b00001
Parameter REG_DEBUG_ACCESS bound to: 5'b10001
Parameter REG_DTM_INFO bound to: 5'b10000
Parameter DBUS_REG_BITS bound to: 41 - type: integer
Parameter DBUS_REQ_BITS bound to: 41 - type: integer
Parameter DBUS_RESP_BITS bound to: 36 - type: integer
Parameter SHIFT_REG_BITS bound to: 41 - type: integer
INFO: [Synth 8-155] case statement is not full and has no default [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/debug/sirv_jtag_dtm.v:237]
INFO: [Synth 8-155] case statement is not full and has no default [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/debug/sirv_jtag_dtm.v:295]
INFO: [Synth 8-155] case statement is not full and has no default [E:/files/A0_fpga_learn/ZYNQ_7010_FPGA/e203_7010/e203_7010.srcs/sources_1/imports/fpga/install/rtl/debug/sirv_jtag_dtm.v:308]
Parameter DW bound to: 41 - type: integer
Parameter SYNC_DP bound to: 2 - type: integer
Parameter DW bound to: 41 - type: integer
Parameter DW bound to: 36 - type: integer
Parameter SYNC_DP bound to: 2 - type: integer
Parameter DW bound to: 36 - type: integer
Parameter PC_SIZE bound to: 32 - type: integer
Parameter DW bound to: 36 - type: integer
Parameter SYNC_DP bound to: 2 - type: integer
Parameter DW bound to: 41 - type: integer
Parameter SYNC_DP bound to: 2 - type: integer
Parameter ASYNC_FF_LEVELS bound to: 2 - type: integer
Parameter CMD_PACK_W bound to: 65 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter SYNC_DP bound to: 2 - type: integer
Parameter DW bound to: 65 - type: integer
Parameter SYNC_DP bound to: 2 - type: integer
Parameter ICB_FIFO_DP bound to: 0 - type: integer
Parameter ICB_FIFO_CUT_READY bound to: 1 - type: integer
Parameter AW bound to: 15 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter SPLT_FIFO_OUTS_NUM bound to: 1 - type: integer
Parameter SPLT_FIFO_CUT_READY bound to: 1 - type: integer
Parameter O0_BASE_ADDR bound to: 15'b000001000000000
Parameter O0_BASE_REGION_LSB bound to: 8 - type: integer
Parameter BASE_REGION_MSB bound to: 14 - type: integer
Parameter SPLT_I_NUM bound to: 2 - type: integer
Parameter OUTS_CNT_W bound to: 1 - type: integer
Parameter AW bound to: 15 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter CMD_CUT_READY bound to: 1 - type: integer
Parameter RSP_CUT_READY bound to: 1 - type: integer
Parameter CMD_DP bound to: 0 - type: integer
Parameter RSP_DP bound to: 0 - type: integer
Parameter USR_W bound to: 1 - type: integer
Parameter CMD_PACK_W bound to: 61 - type: integer
Parameter RSP_PACK_W bound to: 35 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 0 - type: integer
Parameter DP bound to: 0 - type: integer
Parameter DW bound to: 61 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter MSKO bound to: 0 - type: integer
Parameter DP bound to: 0 - type: integer
Parameter DW bound to: 35 - type: integer
Parameter AW bound to: 15 - type: integer
Parameter DW bound to: 32 - type: integer
Parameter FIFO_OUTS_NUM bound to: 1 - type: integer
Parameter FIFO_CUT_READY bound to: 1 - type: integer
Parameter SPLT_NUM bound to: 2 - type: integer
Parameter SPLT_PTR_1HOT bound to: 1 - type: integer
Parameter SPLT_PTR_W bound to: 2 - type: integer
Parameter ALLOW_DIFF bound to: 0 - type: integer
Parameter ALLOW_0CYCL_RSP bound to: 1 - type: integer
Parameter VLD_MSK_PAYLOAD bound to: 1 - type: integer
Parameter USR_W bound to: 1 - type: integer
Parameter CUT_READY bound to: 1 - type: integer
Parameter DP bound to: 1 - type: integer
Parameter DW bound to: 2 - type: integer
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_read_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
RAM "ram_read_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_index_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
RAM "ram_index_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_data_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM
RAM "ram_data_reg" dissolved into registers
WARNING: [Synth 8-4767] Trying to implement RAM 'ram_mask_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.