KitchenTimer.twr

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Release 14.2 Trace  (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

C:\Xilinx\14.2\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
-n 3 -fastpaths -xml KitchenTimer.twx KitchenTimer.ncd -o KitchenTimer.twr
KitchenTimer.pcf -ucf KitchenTimer.ucf

Design file:              KitchenTimer.ncd
Physical constraint file: KitchenTimer.pcf
Device,package,speed:     xc6slx16,csg324,C,-3 (PRODUCTION 1.22 2012-07-09)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
-------------+------------+------------+------------+------------+------------------+--------+
             |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
Source       | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
-------------+------------+------------+------------+------------+------------------+--------+
count_up     |    7.033(R)|      SLOW  |   -1.447(R)|      FAST  |clk_BUFGP         |   0.000|
minbtn       |    1.664(R)|      SLOW  |   -1.061(R)|      FAST  |clk_BUFGP         |   0.000|
pause        |    1.281(R)|      SLOW  |   -0.785(R)|      SLOW  |clk_BUFGP         |   0.000|
reset        |    0.943(R)|      SLOW  |   -0.443(R)|      SLOW  |clk_BUFGP         |   0.000|
secbtn       |    0.969(R)|      FAST  |   -0.444(R)|      SLOW  |clk_BUFGP         |   0.000|
start        |    0.752(R)|      FAST  |   -0.175(R)|      SLOW  |clk_BUFGP         |   0.000|
timesetter<0>|    5.319(R)|      SLOW  |   -1.574(R)|      FAST  |clk_BUFGP         |   0.000|
timesetter<1>|    5.081(R)|      SLOW  |   -0.976(R)|      FAST  |clk_BUFGP         |   0.000|
timesetter<2>|    5.646(R)|      SLOW  |   -1.265(R)|      FAST  |clk_BUFGP         |   0.000|
timesetter<3>|    5.013(R)|      SLOW  |   -1.484(R)|      FAST  |clk_BUFGP         |   0.000|
timesetter<4>|    4.713(R)|      SLOW  |   -1.283(R)|      FAST  |clk_BUFGP         |   0.000|
timesetter<5>|    4.676(R)|      SLOW  |   -1.413(R)|      FAST  |clk_BUFGP         |   0.000|
zippy        |    7.116(R)|      SLOW  |   -2.079(R)|      FAST  |clk_BUFGP         |   0.000|
-------------+------------+------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+-----------------+------------+-----------------+------------+------------------+--------+
            |Max (slowest) clk|  Process   |Min (fastest) clk|  Process   |                  | Clock  |
Destination |  (edge) to PAD  |   Corner   |  (edge) to PAD  |   Corner   |Internal Clock(s) | Phase  |
------------+-----------------+------------+-----------------+------------+------------------+--------+
seven<0>    |        20.077(R)|      SLOW  |         5.643(R)|      FAST  |clk_BUFGP         |   0.000|
seven<1>    |        20.514(R)|      SLOW  |         5.796(R)|      FAST  |clk_BUFGP         |   0.000|
seven<2>    |        19.977(R)|      SLOW  |         5.570(R)|      FAST  |clk_BUFGP         |   0.000|
seven<3>    |        20.699(R)|      SLOW  |         5.924(R)|      FAST  |clk_BUFGP         |   0.000|
seven<4>    |        20.687(R)|      SLOW  |         5.939(R)|      FAST  |clk_BUFGP         |   0.000|
seven<5>    |        20.131(R)|      SLOW  |         5.658(R)|      FAST  |clk_BUFGP         |   0.000|
seven<6>    |        20.450(R)|      SLOW  |         5.776(R)|      FAST  |clk_BUFGP         |   0.000|
zled        |         8.440(R)|      SLOW  |         4.556(R)|      FAST  |clk_BUFGP         |   0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |   12.675|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Tue Apr 26 15:44:12 2016 
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 226 MB