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KitchenTimer_map.map
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KitchenTimer_map.map
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Release 14.2 Map P.28xd (nt64)
Xilinx Map Application Log File for Design 'KitchenTimer'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o KitchenTimer_map.ncd KitchenTimer.ngd
KitchenTimer.pcf
Target Device : xc6slx16
Target Package : csg324
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Apr 26 15:42:31 2016
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 6 secs
Total CPU time at the beginning of Placer: 3 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:37bad433) REAL time: 6 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:37bad433) REAL time: 6 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:37bad433) REAL time: 6 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:16da56a7) REAL time: 7 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:16da56a7) REAL time: 7 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:16da56a7) REAL time: 7 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:16da56a7) REAL time: 7 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:16da56a7) REAL time: 7 secs
Phase 9.8 Global Placement
..................................
.....................................................................................................................
.................................................................................................................................................................................................
....................................
Phase 9.8 Global Placement (Checksum:34b1d03a) REAL time: 10 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:34b1d03a) REAL time: 10 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:1492c76a) REAL time: 12 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:1492c76a) REAL time: 12 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:1492c76a) REAL time: 12 secs
Total REAL time to Placer completion: 12 secs
Total CPU time to Placer completion: 8 secs
Running post-placement packing...
Writing output files...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 170 out of 18,224 1%
Number used as Flip Flops: 166
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 4
Number of Slice LUTs: 534 out of 9,112 5%
Number used as logic: 519 out of 9,112 5%
Number using O6 output only: 291
Number using O5 output only: 146
Number using O5 and O6: 82
Number used as ROM: 0
Number used as Memory: 4 out of 2,176 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 4
Number using O6 output only: 3
Number using O5 output only: 0
Number using O5 and O6: 1
Number used exclusively as route-thrus: 11
Number with same-slice register load: 0
Number with same-slice carry load: 11
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 187 out of 2,278 8%
Nummber of MUXCYs used: 304 out of 4,556 6%
Number of LUT Flip Flop pairs used: 537
Number with an unused Flip Flop: 368 out of 537 68%
Number with an unused LUT: 3 out of 537 1%
Number of fully used LUT-FF pairs: 166 out of 537 30%
Number of unique control sets: 18
Number of slice register sites lost
to control set restrictions: 101 out of 18,224 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 26 out of 232 11%
Number of LOCed IOBs: 26 out of 26 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 0 out of 64 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 248 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
Number of OLOGIC2/OSERDES2s: 0 out of 248 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 32 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.37
Peak Memory Usage: 369 MB
Total REAL time to MAP completion: 13 secs
Total CPU time to MAP completion: 8 secs
Mapping completed.
See MAP report file "KitchenTimer_map.mrp" for details.