How does the compiler work?
I have a day job - message me for details please. Happy to talk your ears off. I will update this when not implementing new features, making improvements, and the like...
- Path from C syntax tree function definitions
- Tracking local variable define-use/assign chains
- Forming directed acyclic graph from inputs to return
- Dataflow ~netlist of assignments+operations
- Some kind ~front end language handling layer?
- Intermediate C-like, single assignment per variable form, highly optimized
- Pipeline scheduling / ‘comb. logic tetris’
- Given delays of operations which areas of DAG need registers where
- Seems tightly coupled with ~netlist comb. logic representation
- Needs to know latency of modules when assembling larger modules, keeping data aligned
- Rendering HDL (VHDL currently, and preferred, but SystemVerilog is fine)
- Pipelined primitives, ex. ~2 cycle latency 64b adder, as two 32b cycles w/ carry
- ~Netlist VHDL + lots of custom arbitrary stuff
- Internal C code gen for built in complex functions:
- ex. PipelineC FP operators are written in PipelineC
- Support for running PNR tools, parsing timing report/measuring delays
- How to make iterative pipelining changes if didnt meet timing
- Running simulation tools
- Experimental derived finite state machines
- Generating helper C code for users