2019 02 01

SPICE writer

The Netlist object got a method to write SPICE files. SPICE files use a specific format but for customization, a delegate can be registered to handle device output. Without a delegate, the SPICE writer will use the built-in device types (R, L, C, D and M).

Here is some code for writing a SPICE netlist with a delegate:

class MySPICEWriterDelegate < RBA::NetlistSpiceWriterDelegate

  def write_header
    # this line will appear at the beginning of the file
    emit_line("*** My special header")
  end

  def write_device_intro(cls)
    # this method will be called for every device class
    if cls.name == "NMOS" || cls.name == "PMOS"
      emit_line(".SUBCKT " + cls.name)
      # ... provide definitions for equivalent circuit 
      emit_line(".ENDS")
      emit_line("*** Put any model declarations here ***")
    end
  end

  def write_device(dev)
    # this method will be called for every device
    if dev.device_class.name == "NMOS" || dev.device_class.name == "PMOS"
      source = net_to_string(dev.net_for_terminal(0))
      gate = net_to_string(dev.net_for_terminal(1))
      drain = net_to_string(dev.net_for_terminal(2))
      bulk = net_to_string(dev.net_for_terminal(3))
      emit_line("X" + dev.id.to_s + " " + source + " " + gate + " " + drain + " " + bulkd + " " + dev.device_class.name)
    else
      super(dev)
    end
  end

end

# how to use it:

netlist = ... some RBA::Netlist object ...

writer = RBA::NetlistSpiceWriter::new(new MySPICEWriterDelegate::new)
netlist.write(path, writer, "Written by KLayout with MySPICEWriterDelegate")

Boolean core for hierarchical operations

The basic idea of hierarchical layout operations is to run computations on a cell with different environments and then determine the common part (the "core"). This is the part that can be put into every cell instance. Previously this part was computed based on a polygon decomposition. However, this lead to insufficient hierarchy utilization because the decomposition may be dependent on the environment. Hence, the scheme was changed to a boolean core: the computation of the common part now is done with real booleans. The effect is a somewhat more fractured result but a better hierarchy utilization.

Perimeter parameters for MOS transistors

Beside the AS/AD (area of source and drain regions), the perimeter of the source and drain regions has been added. If multiple gates attach to a single source or drain area, the perimeter of a single source/drain region is distributed on all attached transistors.