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CSR.sv
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// Generated by CIRCT firtool-1.56.1
// Standard header to adapt well known macros to our needs.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CSR( // <stdin>:3:3
input clock, // <stdin>:4:11
reset, // <stdin>:5:11
io_instret, // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:8:14
input [4:0] io_rs1, // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:8:14
input [11:0] io_csrReg, // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:8:14
input [4:0] io_rd, // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:8:14
input [1:0] io_op, // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:8:14
input [31:0] io_imm, // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:8:14
output [31:0] io_csrRead, // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:8:14
output [4:0] io_rdOut // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:8:14
);
wire _csrRdata_T_6 = io_csrReg == 12'hC02; // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:59:24
reg [31:0] instret; // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:70:24
reg [7:0] fcsrReg; // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:82:24
wire [31:0] csrRdata =
_csrRdata_T_6
? instret
: io_csrReg == 12'h3
? {24'h0, fcsrReg}
: io_csrReg == 12'h2 ? {29'h0, fcsrReg[7:5]} : {27'h0, fcsrReg[4:0]}; // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:59:24, :70:24, :82:24, :83:35, :84:{39,49}, :85:{36,46}, :97:43
wire [3:0][31:0] _GEN =
{{csrRdata & ~io_imm}, {csrRdata | io_imm}, {io_imm}, {csrRdata}}; // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:97:43, :105:41, :107:30, :108:{32,35}
always @(posedge clock) begin // <stdin>:4:11
if (reset) begin // <stdin>:4:11
instret <= 32'h0; // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:70:24
fcsrReg <= 8'h0; // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:82:24
end
else begin // <stdin>:4:11
automatic logic _doCsrRead_T_2; // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:46:42
_doCsrRead_T_2 = io_op == 2'h1 & io_rd == 5'h0; // <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:46:{27,42,51}
if (_csrRdata_T_6 & ~_doCsrRead_T_2) // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:46:{19,42}, :59:{24,38}
instret <= _GEN[io_op]; // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:70:24, :105:41
else if (io_instret) // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:8:14
instret <= instret + 32'h1; // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:70:24, :73:26
if (io_csrReg == 12'h3 & ~_doCsrRead_T_2) // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:46:{19,42}, :59:{24,38}
fcsrReg <= _GEN[io_op][7:0]; // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:82:24, :88:34, :105:41
else if (io_csrReg == 12'h1 & ~_doCsrRead_T_2) // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:46:{19,42}, :59:{24,38}
fcsrReg <= {fcsrReg[7:5], _GEN[io_op][4:0]}; // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:82:24, :85:46, :89:{41,52}, :105:41
else if (io_csrReg == 12'h2 & ~_doCsrRead_T_2) // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:46:{19,42}, :59:{24,38}
fcsrReg <= {_GEN[io_op][2:0], fcsrReg[4:0]}; // C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:82:24, :84:49, :90:{33,39}, :105:41
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // <stdin>:3:3
`ifdef FIRRTL_BEFORE_INITIAL // <stdin>:3:3
`FIRRTL_BEFORE_INITIAL // <stdin>:3:3
`endif // FIRRTL_BEFORE_INITIAL
initial begin // <stdin>:3:3
automatic logic [31:0] _RANDOM[0:2]; // <stdin>:3:3
`ifdef INIT_RANDOM_PROLOG_ // <stdin>:3:3
`INIT_RANDOM_PROLOG_ // <stdin>:3:3
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // <stdin>:3:3
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM; // <stdin>:3:3
end // <stdin>:3:3
instret = _RANDOM[2'h0]; // <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:70:24
fcsrReg = _RANDOM[2'h2][7:0]; // <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:82:24
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // <stdin>:3:3
`FIRRTL_AFTER_INITIAL // <stdin>:3:3
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_csrRead = csrRdata; // <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\CSR.scala:97:43
assign io_rdOut = io_rd; // <stdin>:3:3
endmodule