CoreWrapper.sv

// Generated by CIRCT firtool-1.56.1
// Standard header to adapt well known macros to our needs.
`ifndef RANDOMIZE
  `ifdef RANDOMIZE_REG_INIT
    `define RANDOMIZE
  `endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
  `ifdef RANDOMIZE_MEM_INIT
    `define RANDOMIZE
  `endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE

// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
  `define RANDOM $random
`endif // not def RANDOM

// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
  `define INIT_RANDOM
`endif // not def INIT_RANDOM

// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
  `define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY

// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
  `ifdef RANDOMIZE
    `ifdef VERILATOR
      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
    `else  // VERILATOR
      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
    `endif // VERILATOR
  `else  // RANDOMIZE
    `define INIT_RANDOM_PROLOG_
  `endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_

// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
  `ifndef ENABLE_INITIAL_REG_
    `define ENABLE_INITIAL_REG_
  `endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS

// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
  `ifndef ENABLE_INITIAL_MEM_
    `define ENABLE_INITIAL_MEM_
  `endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS

module Fetch(	// <stdin>:3:3
  input         clock,	// <stdin>:4:11
                reset,	// <stdin>:5:11
                io_mem_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:10:14
  input  [31:0] io_mem_resp_rdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:10:14
  input         io_ctrl_loadPC,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:10:14
  input  [31:0] io_ctrl_newPC,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:10:14
  input         io_hzd_flush,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:10:14
                io_hzd_stall,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:10:14
  output [31:0] io_mem_req_addr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:10:14
                io_id_instr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:10:14
                io_id_pc,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:10:14
  output        io_id_valid	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:10:14
);

  reg  [31:0] PC;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:24:21
  reg         delayedLoadPC;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:30:30
  reg  [31:0] delayedNewPC;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:31:29
  reg  [31:0] sampledInstr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:41:25
  reg         hasSampledInstr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:42:32
  reg         REG;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\utils\\package.scala:25:48
  wire [31:0] _PCnext_T = PC + 32'h4;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:24:21, :51:24
  wire        _PCnext_T_2 = io_ctrl_loadPC & io_mem_resp_ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:52:21
  wire        _PCnext_T_3 = delayedLoadPC & io_mem_resp_ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:30:30, :53:20
  wire        _io_id_valid_T_3 = io_mem_resp_ack | hasSampledInstr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:42:32, :59:34
  wire        _io_id_valid_output =
    ~(io_hzd_flush | io_hzd_stall | delayedLoadPC) & _io_id_valid_T_3;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:30:30, :59:34, :65:{18,49,67}
  reg  [31:0] io_id_pc_REG;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:70:22
  always @(posedge clock) begin	// <stdin>:4:11
    automatic logic _GEN = io_hzd_stall & io_mem_resp_ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:43:32
    automatic logic _GEN_0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:43:52
    _GEN_0 = _GEN & ~REG & ~hasSampledInstr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:42:32, :43:{32,52,55}, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\utils\\package.scala:25:{40,48}
    if (reset) begin	// <stdin>:4:11
      PC <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:24:21
      delayedLoadPC <= 1'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:30:30
      delayedNewPC <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:24:21, :31:29
      hasSampledInstr <= 1'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:30:30, :42:32
    end
    else begin	// <stdin>:4:11
      automatic logic _GEN_1 = io_ctrl_loadPC & ~io_mem_resp_ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:32:{23,26}
      if (~io_hzd_stall & _io_id_valid_T_3) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:59:34, :64:{15,31}
        if (_PCnext_T_2)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:52:21
          PC <= io_ctrl_newPC;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:24:21
        else if (_PCnext_T_3)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:53:20
          PC <= delayedNewPC;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:24:21, :31:29
        else	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:53:20
          PC <= _PCnext_T;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:24:21, :51:24
      end
      delayedLoadPC <= _GEN_1 | ~(delayedLoadPC & io_mem_resp_ack) & delayedLoadPC;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:30:30, :32:{23,44}, :33:19, :35:{29,49}, :36:19
      if (_GEN_1)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:32:23
        delayedNewPC <= io_ctrl_newPC;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:31:29
      hasSampledInstr <=
        _GEN_0 | ~(hasSampledInstr & _io_id_valid_output) & hasSampledInstr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:42:32, :43:{52,73}, :44:21, :46:{31,47}, :47:21, :65:67
    end
    if (_GEN_0)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:43:52
      sampledInstr <= io_mem_resp_rdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:41:25
    REG <= _GEN;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:43:32, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\utils\\package.scala:25:48
    if (io_hzd_stall | ~_io_id_valid_T_3)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:59:34, :70:26
      io_id_pc_REG <= PC;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:24:21, :70:22
    else if (_PCnext_T_2)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:52:21
      io_id_pc_REG <= io_ctrl_newPC;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:70:22
    else if (_PCnext_T_3)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:53:20
      io_id_pc_REG <= delayedNewPC;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:31:29, :70:22
    else	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:53:20
      io_id_pc_REG <= _PCnext_T;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:51:24, :70:22
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:3:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:3:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:3:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:3:3
      automatic logic [31:0] _RANDOM[0:4];	// <stdin>:3:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:3:3
        `INIT_RANDOM_PROLOG_	// <stdin>:3:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:3:3
        for (logic [2:0] i = 3'h0; i < 3'h5; i += 3'h1) begin
          _RANDOM[i] = `RANDOM;	// <stdin>:3:3
        end	// <stdin>:3:3
        PC = _RANDOM[3'h0];	// <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:24:21
        delayedLoadPC = _RANDOM[3'h1][0];	// <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:30:30
        delayedNewPC = {_RANDOM[3'h1][31:1], _RANDOM[3'h2][0]};	// <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:30:30, :31:29
        sampledInstr = {_RANDOM[3'h2][31:1], _RANDOM[3'h3][0]};	// <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:31:29, :41:25
        hasSampledInstr = _RANDOM[3'h3][1];	// <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:41:25, :42:32
        REG = _RANDOM[3'h3][2];	// <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:41:25, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\utils\\package.scala:25:48
        io_id_pc_REG = {_RANDOM[3'h3][31:3], _RANDOM[3'h4][2:0]};	// <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:41:25, :70:22
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:3:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:3:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  assign io_mem_req_addr =
    _io_id_valid_T_3
      ? (_PCnext_T_2 ? io_ctrl_newPC : _PCnext_T_3 ? delayedNewPC : _PCnext_T)
      : PC;	// <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:24:21, :31:29, :51:24, :52:21, :53:20, :59:{17,34}, src/main/scala/chisel3/util/Mux.scala:141:16
  assign io_id_instr = hasSampledInstr ? sampledInstr : io_mem_resp_rdata;	// <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:41:25, :42:32, :60:21
  assign io_id_pc = io_id_pc_REG;	// <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:70:22
  assign io_id_valid = _io_id_valid_output;	// <stdin>:3:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Fetch.scala:65:67
endmodule

module ImmediateGenerator(	// <stdin>:80:3
  input  [31:0] io_instr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:111:14
  output [31:0] io_imm	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:111:14
);

  assign io_imm =
    io_instr[6:0] == 7'h23
      ? {{20{io_instr[31]}}, io_instr[31:25], io_instr[11:7]}
      : io_instr[6:0] == 7'h63
          ? {{20{io_instr[31]}}, io_instr[7], io_instr[30:25], io_instr[11:8], 1'h0}
          : io_instr[6:0] == 7'h37 | io_instr[6:0] == 7'h17
              ? {io_instr[31:12], 12'h0}
              : {{12{io_instr[31]}},
                 io_instr[6:0] == 7'h6F
                   ? {io_instr[19:12], io_instr[20], io_instr[30:21], 1'h0}
                   : {{8{io_instr[31]}}, io_instr[31:20]}};	// <stdin>:80:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:116:{53,60}, :117:{17,38}, :118:{17,38,55}, :119:{17,52,65,82}, :120:{17,52,69,83}, :121:{17,26}, :123:24, :124:{28,37}, :125:14, :127:11, :130:11, :133:11, :136:11
endmodule

module Decode(	// <stdin>:232:3
  input         clock,	// <stdin>:233:11
                reset,	// <stdin>:234:11
  input  [31:0] io_fetch_instr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
                io_fetch_pc,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
  input         io_fetch_valid,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
  input  [4:0]  io_wb_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
  input  [31:0] io_wb_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
  input         io_wb_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
                io_hzd_flush,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
                io_hzd_stall,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
  output        io_ex_valid,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
  output [31:0] io_ex_imm,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
                io_ex_v1,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
                io_ex_v2,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
  output [4:0]  io_ex_rs1,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
                io_ex_rs2,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
  output [31:0] io_ex_pc,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
  output [4:0]  io_ex_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
  output [3:0]  io_ex_aluOp,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
  output        io_ex_pcNextSrc,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
                io_ex_ctrl_op2src,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
                io_ex_ctrl_branch,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
                io_ex_ctrl_jump,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
                io_ex_ctrl_memRead,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
                io_ex_ctrl_memWrite,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
  output [2:0]  io_ex_ctrl_memOp,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
  output        io_ex_ctrl_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
  output [4:0]  io_hzd_rs1,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
                io_hzd_rs2	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
);

  reg  [31:0]       fetch_instr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24
  reg  [31:0]       fetch_pc;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24
  reg               fetch_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24
  reg  [31:0]       reg_0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_3;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_4;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_5;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_6;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_7;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_8;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_9;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_10;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_11;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_12;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_13;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_14;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_15;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_16;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_17;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_18;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_19;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_20;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_21;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_22;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_23;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_24;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_25;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_26;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_27;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_28;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_29;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_30;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  reg  [31:0]       reg_31;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
  wire              _io_ex_aluOp_T_1 = fetch_instr[6:0] == 7'h13;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :34:{27,33}
  wire              _io_ex_v1_T_1 = fetch_instr[6:0] == 7'h17;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :34:{27,33}
  wire              _io_ex_ctrl_op2src_T = fetch_instr[6:0] == 7'h33;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :34:{27,33}
  wire              _io_ex_v1_T = fetch_instr[6:0] == 7'h37;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :34:{27,33}
  wire              _io_ex_ctrl_branch_T = fetch_instr[6:0] == 7'h63;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :34:{27,33}
  wire              _io_ex_ctrl_jump_T_1 = fetch_instr[6:0] == 7'h67;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :34:{27,33}
  wire              _io_ex_ctrl_jump_T = fetch_instr[6:0] == 7'h6F;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :34:{27,33}
  wire [31:0][31:0] _GEN =
    {{reg_31},
     {reg_30},
     {reg_29},
     {reg_28},
     {reg_27},
     {reg_26},
     {reg_25},
     {reg_24},
     {reg_23},
     {reg_22},
     {reg_21},
     {reg_20},
     {reg_19},
     {reg_18},
     {reg_17},
     {reg_16},
     {reg_15},
     {reg_14},
     {reg_13},
     {reg_12},
     {reg_11},
     {reg_10},
     {reg_9},
     {reg_8},
     {reg_7},
     {reg_6},
     {reg_5},
     {reg_4},
     {reg_3},
     {reg_2},
     {reg_1},
     {reg_0}};	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :58:15
  wire              _msb_T_6 = fetch_instr[14:12] == 3'h5;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :39:21, :74:43
  wire              valid = fetch_valid & ~io_hzd_flush & ~io_hzd_stall;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:{24,80}, :81:{30,44}
  always @(posedge clock) begin	// <stdin>:233:11
    if (reset) begin	// <stdin>:233:11
      fetch_instr <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:{24,68}
      fetch_pc <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:{24,68}
      fetch_valid <= 1'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:{24,68}
      reg_0 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_1 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_2 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_3 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_4 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_5 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_6 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_7 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_8 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_9 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_10 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_11 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_12 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_13 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_14 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_15 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_16 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_17 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_18 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_19 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_20 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_21 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_22 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_23 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_24 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_25 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_26 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_27 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_28 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_29 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_30 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
      reg_31 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:68, :31:20
    end
    else begin	// <stdin>:233:11
      automatic logic _GEN_0 = io_wb_we & (|io_wb_rd);	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:50:{17,29}
      if (io_hzd_stall) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
      end
      else begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:15:14
        fetch_instr <= io_fetch_instr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24
        fetch_pc <= io_fetch_pc;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24
        fetch_valid <= io_fetch_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24
      end
      if (_GEN_0 & io_wb_rd == 5'h0)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19, :63:19
        reg_0 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h1)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_1 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h2)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_2 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h3)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_3 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h4)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_4 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h5)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_5 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h6)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_6 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h7)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_7 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h8)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_8 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h9)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_9 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'hA)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_10 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'hB)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_11 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'hC)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_12 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'hD)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_13 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'hE)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_14 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'hF)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_15 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h10)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_16 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h11)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_17 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h12)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_18 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h13)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :34:27, :50:{17,38}, :51:19
        reg_19 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h14)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_20 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h15)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_21 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h16)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_22 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h17)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :34:27, :50:{17,38}, :51:19
        reg_23 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h18)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_24 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h19)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_25 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h1A)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_26 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h1B)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_27 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h1C)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_28 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h1D)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_29 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & io_wb_rd == 5'h1E)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_30 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      if (_GEN_0 & (&io_wb_rd))	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20, :50:{17,38}, :51:19
        reg_31 <= io_wb_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
    end
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:232:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:232:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:232:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:232:3
      automatic logic [31:0] _RANDOM[0:34];	// <stdin>:232:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:232:3
        `INIT_RANDOM_PROLOG_	// <stdin>:232:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:232:3
        for (logic [5:0] i = 6'h0; i < 6'h23; i += 6'h1) begin
          _RANDOM[i] = `RANDOM;	// <stdin>:232:3
        end	// <stdin>:232:3
        fetch_instr = _RANDOM[6'h0];	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24
        fetch_pc = _RANDOM[6'h1];	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24
        fetch_valid = _RANDOM[6'h2][0];	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24
        reg_0 = {_RANDOM[6'h2][31:1], _RANDOM[6'h3][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :31:20
        reg_1 = {_RANDOM[6'h3][31:1], _RANDOM[6'h4][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_2 = {_RANDOM[6'h4][31:1], _RANDOM[6'h5][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_3 = {_RANDOM[6'h5][31:1], _RANDOM[6'h6][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_4 = {_RANDOM[6'h6][31:1], _RANDOM[6'h7][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_5 = {_RANDOM[6'h7][31:1], _RANDOM[6'h8][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_6 = {_RANDOM[6'h8][31:1], _RANDOM[6'h9][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_7 = {_RANDOM[6'h9][31:1], _RANDOM[6'hA][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_8 = {_RANDOM[6'hA][31:1], _RANDOM[6'hB][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_9 = {_RANDOM[6'hB][31:1], _RANDOM[6'hC][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_10 = {_RANDOM[6'hC][31:1], _RANDOM[6'hD][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_11 = {_RANDOM[6'hD][31:1], _RANDOM[6'hE][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_12 = {_RANDOM[6'hE][31:1], _RANDOM[6'hF][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_13 = {_RANDOM[6'hF][31:1], _RANDOM[6'h10][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_14 = {_RANDOM[6'h10][31:1], _RANDOM[6'h11][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_15 = {_RANDOM[6'h11][31:1], _RANDOM[6'h12][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_16 = {_RANDOM[6'h12][31:1], _RANDOM[6'h13][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_17 = {_RANDOM[6'h13][31:1], _RANDOM[6'h14][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_18 = {_RANDOM[6'h14][31:1], _RANDOM[6'h15][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_19 = {_RANDOM[6'h15][31:1], _RANDOM[6'h16][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_20 = {_RANDOM[6'h16][31:1], _RANDOM[6'h17][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_21 = {_RANDOM[6'h17][31:1], _RANDOM[6'h18][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_22 = {_RANDOM[6'h18][31:1], _RANDOM[6'h19][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_23 = {_RANDOM[6'h19][31:1], _RANDOM[6'h1A][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_24 = {_RANDOM[6'h1A][31:1], _RANDOM[6'h1B][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_25 = {_RANDOM[6'h1B][31:1], _RANDOM[6'h1C][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_26 = {_RANDOM[6'h1C][31:1], _RANDOM[6'h1D][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_27 = {_RANDOM[6'h1D][31:1], _RANDOM[6'h1E][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_28 = {_RANDOM[6'h1E][31:1], _RANDOM[6'h1F][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_29 = {_RANDOM[6'h1F][31:1], _RANDOM[6'h20][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_30 = {_RANDOM[6'h20][31:1], _RANDOM[6'h21][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
        reg_31 = {_RANDOM[6'h21][31:1], _RANDOM[6'h22][0]};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:31:20
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:232:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:232:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  ImmediateGenerator immGen (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:42:22
    .io_instr (fetch_instr),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24
    .io_imm   (io_ex_imm)
  );
  assign io_ex_valid = valid;	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:81:44
  assign io_ex_v1 =
    _io_ex_v1_T
      ? 32'h0
      : _io_ex_v1_T_1
          ? fetch_pc
          : io_wb_we & io_wb_rd == fetch_instr[19:15] & (|io_wb_rd)
              ? io_wb_wdata
              : _GEN[fetch_instr[19:15]];	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:{24,68}, :34:27, :35:21, :50:29, :58:{15,37,45}, :67:{18,46}
  assign io_ex_v2 =
    io_wb_we & io_wb_rd == fetch_instr[24:20] & (|io_wb_rd)
      ? io_wb_wdata
      : _GEN[fetch_instr[24:20]];	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :36:21, :50:29, :58:15, :59:{15,37,45}
  assign io_ex_rs1 =
    _io_ex_v1_T | _io_ex_v1_T_1 | _io_ex_ctrl_jump_T ? 5'h0 : fetch_instr[19:15];	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :34:27, :35:21, :63:{19,61}
  assign io_ex_rs2 =
    _io_ex_v1_T | _io_ex_v1_T_1 | _io_ex_ctrl_jump_T ? 5'h0 : fetch_instr[24:20];	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :34:27, :36:21, :63:19, :64:{19,61}
  assign io_ex_pc = fetch_pc;	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24
  assign io_ex_rd = fetch_instr[11:7];	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :37:21
  assign io_ex_aluOp =
    _io_ex_ctrl_op2src_T | _io_ex_aluOp_T_1 | _io_ex_ctrl_branch_T
      ? {(_io_ex_ctrl_op2src_T & (_msb_T_6 | fetch_instr[14:12] == 3'h0)
          | _io_ex_aluOp_T_1 & _msb_T_6) & fetch_instr[30],
         fetch_instr[14:12]}
      : 4'h0;	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :34:27, :38:21, :39:21, :74:{32,43,60,70,89}, :75:{27,57,66}, :77:{21,63,97}, :92:36
  assign io_ex_pcNextSrc = _io_ex_ctrl_jump_T_1;	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:34:27
  assign io_ex_ctrl_op2src = _io_ex_ctrl_op2src_T & valid;	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:34:27, :81:44, :85:41
  assign io_ex_ctrl_branch = _io_ex_ctrl_branch_T & valid;	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:34:27, :81:44, :86:45
  assign io_ex_ctrl_jump = (_io_ex_ctrl_jump_T | _io_ex_ctrl_jump_T_1) & valid;	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:34:27, :81:44, :87:{41,64}
  assign io_ex_ctrl_memRead = fetch_instr[6:0] == 7'h3 & valid;	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :34:{27,33}, :81:44, :91:44
  assign io_ex_ctrl_memWrite = fetch_instr[6:0] == 7'h23 & valid;	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :34:{27,33}, :81:44, :90:46
  assign io_ex_ctrl_memOp = fetch_instr[14:12] & {3{valid}};	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :39:21, :81:44, :92:{30,36}
  assign io_ex_ctrl_we =
    fetch_instr[6:0] != 7'h63 & fetch_instr[6:0] != 7'h73 & fetch_instr[6:0] != 7'hF
    & fetch_instr[6:0] != 7'h23 & valid;	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :34:{27,33}, :55:{15,39,63,89}, :81:44, :95:23
  assign io_hzd_rs1 = fetch_instr[19:15];	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :35:21
  assign io_hzd_rs2 = fetch_instr[24:20];	// <stdin>:232:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Decode.scala:26:24, :36:21
endmodule

module Shifter(	// <stdin>:418:3
  input  [31:0] io_in,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:14:14
  input  [3:0]  io_mode,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:14:14
  input  [4:0]  io_shamt,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:14:14
  output [31:0] io_out	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:14:14
);

  wire        signed_0 = io_mode == 4'hD;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:25:24
  wire        rev = io_mode == 4'h1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:26:21
  wire [7:0]  _GEN =
    {{io_in[11:8], io_in[15:14]} & 6'h33, 2'h0} | {io_in[15:12], io_in[19:16]} & 8'h33;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:28:31
  wire [18:0] _GEN_0 =
    {io_in[5:4], io_in[7:6], io_in[9:8], _GEN, io_in[19:18], io_in[21:20], io_in[23]}
    & 19'h55555;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:28:31
  wire [31:0] input_0 =
    rev
      ? {io_in[0],
         io_in[1],
         io_in[2],
         io_in[3],
         io_in[4],
         _GEN_0[18:15] | {io_in[7:6], io_in[9:8]} & 4'h5,
         _GEN_0[14:7] | _GEN & 8'h55,
         _GEN[1],
         _GEN_0[5] | io_in[18],
         io_in[19],
         io_in[20],
         {_GEN_0[2:0], 1'h0} | {io_in[23:22], io_in[25:24]} & 4'h5,
         io_in[25],
         io_in[26],
         io_in[27],
         io_in[28],
         io_in[29],
         io_in[30],
         io_in[31]}
      : io_in;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:26:21, :28:{18,31}
  wire [31:0] shift_0 = io_shamt[0] ? {signed_0 & input_0[31], input_0[31:1]} : input_0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:25:24, :28:18, :35:{18,40}, :37:{20,29}, :39:8, :43:44
  wire [31:0] shift_1 =
    io_shamt[1] ? {{2{signed_0 & shift_0[31]}}, shift_0[31:2]} : shift_0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:25:24, :35:{18,31,40}, :37:{20,29}, :39:8, :45:69
  wire [31:0] shift_2 =
    io_shamt[2] ? {{4{signed_0 & shift_1[31]}}, shift_1[31:4]} : shift_1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:25:24, :35:{18,31,40}, :37:{20,29}, :39:8, :45:69
  wire [31:0] shift_3 =
    io_shamt[3] ? {{8{signed_0 & shift_2[31]}}, shift_2[31:8]} : shift_2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:25:24, :35:{18,31,40}, :37:{20,29}, :39:8, :45:69
  wire [31:0] shift_4 =
    io_shamt[4] ? {{16{signed_0 & shift_3[31]}}, shift_3[31:16]} : shift_3;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:25:24, :35:{18,31,40}, :37:{20,29}, :39:8, :45:69
  wire [7:0]  _GEN_1 =
    {{shift_4[11:8], shift_4[15:14]} & 6'h33, 2'h0} | {shift_4[15:12], shift_4[19:16]}
    & 8'h33;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:28:31, :39:8, :47:29
  wire [18:0] _GEN_2 =
    {shift_4[5:4],
     shift_4[7:6],
     shift_4[9:8],
     _GEN_1,
     shift_4[19:18],
     shift_4[21:20],
     shift_4[23]} & 19'h55555;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:28:31, :39:8, :47:29
  assign io_out =
    rev
      ? {shift_4[0],
         shift_4[1],
         shift_4[2],
         shift_4[3],
         shift_4[4],
         _GEN_2[18:15] | {shift_4[7:6], shift_4[9:8]} & 4'h5,
         _GEN_2[14:7] | _GEN_1 & 8'h55,
         _GEN_1[1],
         _GEN_2[5] | shift_4[18],
         shift_4[19],
         shift_4[20],
         {_GEN_2[2:0], 1'h0} | {shift_4[23:22], shift_4[25:24]} & 4'h5,
         shift_4[25],
         shift_4[26],
         shift_4[27],
         shift_4[28],
         shift_4[29],
         shift_4[30],
         shift_4[31]}
      : shift_4;	// <stdin>:418:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\Shifter.scala:26:21, :28:31, :39:8, :47:{16,29}
endmodule

module ALU(	// <stdin>:571:3
  input  [31:0] io_v1,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ALU.scala:14:14
                io_v2,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ALU.scala:14:14
  input  [3:0]  io_op,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ALU.scala:14:14
  output [31:0] io_res	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ALU.scala:14:14
);

  wire [31:0] _shifter_io_out;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ALU.scala:22:23
  wire        carry = io_op == 4'h8;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ALU.scala:18:21
  wire [32:0] _arith_T_4 = {io_v1, 1'h1} + {{32{carry}} ^ io_v2, carry};	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ALU.scala:18:21, :19:{23,36,42}
  Shifter shifter (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ALU.scala:22:23
    .io_in    (io_v1),
    .io_mode  (io_op),
    .io_shamt (io_v2[4:0]),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ALU.scala:24:28
    .io_out   (_shifter_io_out)
  );
  assign io_res =
    io_op == 4'h1 | io_op == 4'h5 | io_op == 4'hD
      ? _shifter_io_out
      : io_op == 4'h2 | io_op == 4'h3
          ? {31'h0,
             io_v1[31] == io_v2[31]
               ? io_v1[30:0] < io_v2[30:0]
               : io_op == 4'h2 ? io_v1[31] & ~(io_v2[31]) : ~(io_v1[31]) & io_v2[31]}
          : io_op == 4'h7 | io_op == 4'h6 | io_op == 4'h4
              ? (io_op == 4'h7
                   ? io_v1 & io_v2
                   : io_op == 4'h6 ? io_v1 | io_v2 : io_v1 ^ io_v2)
              : _arith_T_4[32:1];	// <stdin>:571:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ALU.scala:19:{36,84}, :22:23, :31:19, :32:19, :33:{19,35,42}, :34:{16,22}, :35:{8,15,35,37,44,50}, :38:{18,25,46,58,65,85,100}, :40:10, :41:17, :42:50, :43:50, :44:50
endmodule

module ForwardingUnit(	// <stdin>:651:3
  input  [4:0]  io_IDrs1,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ForwardingUnit.scala:7:14
                io_IDrs2,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ForwardingUnit.scala:7:14
  input  [31:0] io_IDv1,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ForwardingUnit.scala:7:14
                io_IDv2,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ForwardingUnit.scala:7:14
  input  [4:0]  io_mem_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ForwardingUnit.scala:7:14
  input  [31:0] io_mem_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ForwardingUnit.scala:7:14
  input         io_mem_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ForwardingUnit.scala:7:14
  input  [4:0]  io_wb_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ForwardingUnit.scala:7:14
  input  [31:0] io_wb_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ForwardingUnit.scala:7:14
  input         io_wb_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ForwardingUnit.scala:7:14
  output [31:0] io_v1,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ForwardingUnit.scala:7:14
                io_v2	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ForwardingUnit.scala:7:14
);

  assign io_v1 =
    io_IDrs1 == io_mem_rd & io_mem_we & (|io_IDrs1)
      ? io_mem_wdata
      : io_IDrs1 == io_wb_rd & io_wb_we & (|io_IDrs1) ? io_wb_wdata : io_IDv1;	// <stdin>:651:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ForwardingUnit.scala:30:{42,69,81}, :31:{41,66}, :32:19, :33:11, :34:25, :35:11, :37:11
  assign io_v2 =
    io_IDrs2 == io_mem_rd & io_mem_we & (|io_IDrs2)
      ? io_mem_wdata
      : io_IDrs2 == io_wb_rd & io_wb_we & (|io_IDrs2) ? io_wb_wdata : io_IDv2;	// <stdin>:651:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\ForwardingUnit.scala:40:{42,69,81}, :41:{41,66}, :42:19, :43:11, :44:25, :45:11, :47:11
endmodule

module Execute(	// <stdin>:688:3
  input         clock,	// <stdin>:689:11
                reset,	// <stdin>:690:11
                io_id_valid,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  input  [31:0] io_id_imm,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
                io_id_v1,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
                io_id_v2,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  input  [4:0]  io_id_rs1,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
                io_id_rs2,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  input  [31:0] io_id_pc,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  input  [4:0]  io_id_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  input  [3:0]  io_id_aluOp,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  input         io_id_pcNextSrc,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
                io_id_ctrl_op2src,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
                io_id_ctrl_branch,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
                io_id_ctrl_jump,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
                io_id_ctrl_memRead,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
                io_id_ctrl_memWrite,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  input  [2:0]  io_id_ctrl_memOp,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  input         io_id_ctrl_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  input  [4:0]  io_memFwd_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  input  [31:0] io_memFwd_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  input         io_memFwd_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  input  [4:0]  io_wbFwd_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  input  [31:0] io_wbFwd_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  input         io_wbFwd_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
                io_hzd_stall,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  output        io_memstage_valid,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  output [31:0] io_memstage_res,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  output [4:0]  io_memstage_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  output        io_memstage_ctrl_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
                io_memstage_ctrl_memRead,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
                io_memstage_ctrl_memWrite,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  output [2:0]  io_memstage_ctrl_memOp,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  output        io_mem_req,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  output [31:0] io_mem_addr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
                io_mem_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  output        io_mem_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  output [3:0]  io_mem_wmask,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  output        io_fetch_loadPC,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  output [31:0] io_fetch_newPC,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  output        io_hzd_memRead,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  output [4:0]  io_hzd_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
  output        io_hzd_loadPC	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
);

  wire [31:0] _fwd_io_v1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19
  wire [31:0] _fwd_io_v2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19
  wire [31:0] _alu_io_res;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:30:19
  reg         id_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg  [31:0] id_imm;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg  [31:0] id_v1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg  [31:0] id_v2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg  [4:0]  id_rs1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg  [4:0]  id_rs2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg  [31:0] id_pc;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg  [4:0]  id_rd;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg  [3:0]  id_aluOp;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg         id_pcNextSrc;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg         id_ctrl_op2src;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg         id_ctrl_branch;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg         id_ctrl_jump;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg         id_ctrl_memRead;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg         id_ctrl_memWrite;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg  [2:0]  id_ctrl_memOp;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  reg         id_ctrl_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  wire        eq = _fwd_io_v1 == _fwd_io_v2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19, :54:15
  wire        lt = $signed(_fwd_io_v1) < $signed(_fwd_io_v2);	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19, :55:22
  wire        ltu = _fwd_io_v1 < _fwd_io_v2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19, :56:16
  wire        loadPC =
    id_ctrl_branch
    & (eq & id_aluOp[2:0] == 3'h0 | ~eq & id_aluOp[2:0] == 3'h1 | lt
       & id_aluOp[2:0] == 3'h4 | ~lt & id_aluOp[2:0] == 3'h5 | ltu & id_aluOp[2:0] == 3'h6
       | ~ltu & (&(id_aluOp[2:0]))) | id_ctrl_jump;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19, :54:15, :55:22, :56:16, :58:{16,35,41}, :59:{13,17,36,42}, :60:{16,35,41}, :61:{13,17,36,42}, :62:{17,36,42}, :63:{14,19,38,44}, :65:{32,65,74}
  wire [31:0] _newPC_T_1 = (id_pcNextSrc ? _fwd_io_v1 : id_pc) + id_imm;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19, :34:19, :67:{23,49}
  wire        _GEN = id_ctrl_memOp == 3'h0;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19, :81:22
  wire [31:0] _wdata_T_4 = {4{_fwd_io_v2[7:0]}};	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19, :83:{48,56}
  wire        _GEN_0 = id_ctrl_memOp == 3'h1;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19, :84:29
  wire [31:0] _wdata_T_7 = {2{_fwd_io_v2[15:0]}};	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19, :86:{50,59}
  wire [31:0] req_addr = {_alu_io_res[31:2], 2'h0};	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:30:19, :97:{21,37}
  wire        req_req = (id_ctrl_memWrite | id_ctrl_memRead) & id_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19, :98:{32,51}
  wire [3:0]  req_wmask =
    (_GEN ? 4'h1 << _alu_io_res[1:0] : _GEN_0 ? (_alu_io_res[1] ? 4'hC : 4'h3) : 4'hF)
    & {4{id_ctrl_memWrite}};	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:30:19, :34:19, :81:{22,39}, :82:{10,28}, :84:{29,46}, :85:{10,16,23}, :88:10, :100:{21,27}, src/main/scala/chisel3/util/OneHot.scala:58:35
  reg         oldReq_req;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:104:23
  reg  [31:0] oldReq_addr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:104:23
  reg  [31:0] oldReq_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:104:23
  reg         oldReq_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:104:23
  reg  [3:0]  oldReq_wmask;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:104:23
  always @(posedge clock) begin	// <stdin>:689:11
    if (reset) begin	// <stdin>:689:11
      id_valid <= 1'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
      id_imm <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
      id_v1 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
      id_v2 <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
      id_rs1 <= 5'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
      id_rs2 <= 5'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
      id_pc <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
      id_rd <= 5'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
      id_aluOp <= 4'h0;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_pcNextSrc <= 1'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
      id_ctrl_op2src <= 1'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
      id_ctrl_branch <= 1'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
      id_ctrl_jump <= 1'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
      id_ctrl_memRead <= 1'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
      id_ctrl_memWrite <= 1'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
      id_ctrl_memOp <= 3'h0;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_ctrl_we <= 1'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:{19,50}
    end
    else if (io_hzd_stall) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
      id_v1 <= _fwd_io_v1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19, :34:19
      id_v2 <= _fwd_io_v2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19, :34:19
    end
    else begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
      id_valid <= io_id_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_imm <= io_id_imm;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_v1 <= io_id_v1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_v2 <= io_id_v2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_rs1 <= io_id_rs1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_rs2 <= io_id_rs2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_pc <= io_id_pc;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_rd <= io_id_rd;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_aluOp <= io_id_aluOp;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_pcNextSrc <= io_id_pcNextSrc;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_ctrl_op2src <= io_id_ctrl_op2src;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_ctrl_branch <= io_id_ctrl_branch;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_ctrl_jump <= io_id_ctrl_jump;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_ctrl_memRead <= io_id_ctrl_memRead;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_ctrl_memWrite <= io_id_ctrl_memWrite;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_ctrl_memOp <= io_id_ctrl_memOp;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
      id_ctrl_we <= io_id_ctrl_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
    end
    if (io_hzd_stall) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
    end
    else begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:9:14
      oldReq_req <= req_req;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:98:51, :104:23
      oldReq_addr <= req_addr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:97:37, :104:23
      if (_GEN)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:81:22
        oldReq_wdata <= _wdata_T_4;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:83:56, :104:23
      else if (_GEN_0)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:84:29
        oldReq_wdata <= _wdata_T_7;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:86:59, :104:23
      else	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:84:29
        oldReq_wdata <= _fwd_io_v2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19, :104:23
      oldReq_we <= id_ctrl_memWrite;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19, :104:23
      oldReq_wmask <= req_wmask;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:100:21, :104:23
    end
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:688:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:688:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:688:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:688:3
      automatic logic [31:0] _RANDOM[0:7];	// <stdin>:688:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:688:3
        `INIT_RANDOM_PROLOG_	// <stdin>:688:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:688:3
        for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin
          _RANDOM[i[2:0]] = `RANDOM;	// <stdin>:688:3
        end	// <stdin>:688:3
        id_valid = _RANDOM[3'h0][0];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_imm = {_RANDOM[3'h0][31:1], _RANDOM[3'h1][0]};	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_v1 = {_RANDOM[3'h1][31:1], _RANDOM[3'h2][0]};	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_v2 = {_RANDOM[3'h2][31:1], _RANDOM[3'h3][0]};	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_rs1 = _RANDOM[3'h3][5:1];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_rs2 = _RANDOM[3'h3][10:6];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_pc = {_RANDOM[3'h3][31:11], _RANDOM[3'h4][10:0]};	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_rd = _RANDOM[3'h4][15:11];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_aluOp = _RANDOM[3'h4][19:16];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_pcNextSrc = _RANDOM[3'h4][20];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_ctrl_op2src = _RANDOM[3'h4][21];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_ctrl_branch = _RANDOM[3'h4][22];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_ctrl_jump = _RANDOM[3'h4][23];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_ctrl_memRead = _RANDOM[3'h4][24];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_ctrl_memWrite = _RANDOM[3'h4][25];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_ctrl_memOp = _RANDOM[3'h4][28:26];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        id_ctrl_we = _RANDOM[3'h4][29];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
        oldReq_req = _RANDOM[3'h4][30];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19, :104:23
        oldReq_addr = {_RANDOM[3'h4][31], _RANDOM[3'h5][30:0]};	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19, :104:23
        oldReq_wdata = {_RANDOM[3'h5][31], _RANDOM[3'h6][30:0]};	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:104:23
        oldReq_we = _RANDOM[3'h6][31];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:104:23
        oldReq_wmask = _RANDOM[3'h7][3:0];	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:104:23
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:688:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:688:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  ALU alu (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:30:19
    .io_v1  (_fwd_io_v1),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19
    .io_v2  (id_ctrl_op2src ? _fwd_io_v2 : id_imm),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19, :34:19, :74:19
    .io_op  (id_aluOp),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
    .io_res (_alu_io_res)
  );
  ForwardingUnit fwd (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19
    .io_IDrs1     (id_rs1),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
    .io_IDrs2     (id_rs2),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
    .io_IDv1      (id_v1),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
    .io_IDv2      (id_v2),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
    .io_mem_rd    (io_memFwd_rd),
    .io_mem_wdata (io_memFwd_wdata),
    .io_mem_we    (io_memFwd_we),
    .io_wb_rd     (io_wbFwd_rd),
    .io_wb_wdata  (io_wbFwd_wdata),
    .io_wb_we     (io_wbFwd_we),
    .io_v1        (_fwd_io_v1),
    .io_v2        (_fwd_io_v2)
  );
  assign io_memstage_valid = id_valid & ~io_hzd_stall;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19, :35:9, :114:33
  assign io_memstage_res = id_ctrl_jump ? id_pc + 32'h4 : _alu_io_res;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:30:19, :34:19, :112:{25,46}
  assign io_memstage_rd = id_rd;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  assign io_memstage_ctrl_we = id_ctrl_we;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  assign io_memstage_ctrl_memRead = id_ctrl_memRead;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  assign io_memstage_ctrl_memWrite = id_ctrl_memWrite;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  assign io_memstage_ctrl_memOp = id_ctrl_memOp;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  assign io_mem_req = io_hzd_stall ? oldReq_req : req_req;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:98:51, :104:23, :105:16
  assign io_mem_addr = io_hzd_stall ? oldReq_addr : req_addr;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:97:37, :104:23, :105:16
  assign io_mem_wdata =
    io_hzd_stall ? oldReq_wdata : _GEN ? _wdata_T_4 : _GEN_0 ? _wdata_T_7 : _fwd_io_v2;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:31:19, :81:{22,39}, :83:{11,56}, :84:{29,46}, :86:{11,59}, :89:11, :104:23, :105:16
  assign io_mem_we = io_hzd_stall ? oldReq_we : id_ctrl_memWrite;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19, :104:23, :105:16
  assign io_mem_wmask = io_hzd_stall ? oldReq_wmask : req_wmask;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:100:21, :104:23, :105:16
  assign io_fetch_loadPC = loadPC;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:65:74
  assign io_fetch_newPC = {_newPC_T_1[31:1], 1'h0};	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:50, :67:{18,49,58}
  assign io_hzd_memRead = id_ctrl_memRead;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  assign io_hzd_rd = id_rd;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:34:19
  assign io_hzd_loadPC = loadPC;	// <stdin>:688:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Execute.scala:65:74
endmodule

module Memory(	// <stdin>:875:3
  input         clock,	// <stdin>:876:11
                reset,	// <stdin>:877:11
                io_ex_valid,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
  input  [31:0] io_ex_res,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
  input  [4:0]  io_ex_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
  input         io_ex_ctrl_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
                io_ex_ctrl_memRead,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
                io_ex_ctrl_memWrite,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
  input  [2:0]  io_ex_ctrl_memOp,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
  input         io_mem_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
  input  [31:0] io_mem_rdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
  input         io_hzd_stall,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
  output        io_wb_valid,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
  output [31:0] io_wb_res,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
  output [4:0]  io_wb_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
  output        io_wb_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
  output [4:0]  io_fwd_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
  output [31:0] io_fwd_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
  output        io_fwd_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
                io_hzd_memOp,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
                io_hzd_ack	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
);

  reg              ex_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
  reg  [31:0]      ex_res;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
  reg  [4:0]       ex_rd;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
  reg              ex_ctrl_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
  reg              ex_ctrl_memRead;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
  reg              ex_ctrl_memWrite;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
  reg  [2:0]       ex_ctrl_memOp;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
  wire             sext = ex_ctrl_memOp == 3'h1 | ~(|ex_ctrl_memOp);	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21, :28:{29,46,64}
  wire [3:0][31:0] _GEN =
    {{{{24{io_mem_rdata[31] & sext}}, io_mem_rdata[31:24]}},
     {{{24{io_mem_rdata[23] & sext}}, io_mem_rdata[23:16]}},
     {{{24{io_mem_rdata[15] & sext}}, io_mem_rdata[15:8]}},
     {{{24{io_mem_rdata[7] & sext}}, io_mem_rdata[7:0]}}};	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:28:46, :41:{14,23}, :42:{15,22,48,52,60,75}, :43:{21,30}, :44:{15,22,48,53,61,76}, :45:{21,30}, :46:{15,22,48,53,61,76}, :48:{15,22,48,53,61,76}
  always @(posedge clock) begin	// <stdin>:876:11
    if (reset) begin	// <stdin>:876:11
      ex_valid <= 1'h0;	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
      ex_res <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:{21,59}
      ex_rd <= 5'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:{21,59}
      ex_ctrl_we <= 1'h0;	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
      ex_ctrl_memRead <= 1'h0;	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
      ex_ctrl_memWrite <= 1'h0;	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
      ex_ctrl_memOp <= 3'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:{21,59}
    end
    else if (io_hzd_stall) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
    end
    else begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:9:14
      ex_valid <= io_ex_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
      ex_res <= io_ex_res;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
      ex_rd <= io_ex_rd;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
      ex_ctrl_we <= io_ex_ctrl_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
      ex_ctrl_memRead <= io_ex_ctrl_memRead;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
      ex_ctrl_memWrite <= io_ex_ctrl_memWrite;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
      ex_ctrl_memOp <= io_ex_ctrl_memOp;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
    end
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:875:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:875:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:875:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:875:3
      automatic logic [31:0] _RANDOM[0:1];	// <stdin>:875:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:875:3
        `INIT_RANDOM_PROLOG_	// <stdin>:875:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:875:3
        for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
          _RANDOM[i[0]] = `RANDOM;	// <stdin>:875:3
        end	// <stdin>:875:3
        ex_valid = _RANDOM[1'h0][0];	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
        ex_res = {_RANDOM[1'h0][31:1], _RANDOM[1'h1][0]};	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
        ex_rd = _RANDOM[1'h1][5:1];	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
        ex_ctrl_we = _RANDOM[1'h1][6];	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
        ex_ctrl_memRead = _RANDOM[1'h1][7];	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
        ex_ctrl_memWrite = _RANDOM[1'h1][8];	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
        ex_ctrl_memOp = _RANDOM[1'h1][11:9];	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:875:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:875:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  assign io_wb_valid = ex_valid & ~io_hzd_stall;	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:{21,68}, :58:27
  assign io_wb_res =
    ex_ctrl_memRead
      ? (ex_ctrl_memOp == 3'h1 | ex_ctrl_memOp == 3'h5
           ? {{16{(ex_res[1] ? io_mem_rdata[31] : io_mem_rdata[15]) & sext}},
              ex_res[1] ? io_mem_rdata[31:16] : io_mem_rdata[15:0]}
           : ~(|ex_ctrl_memOp) | ex_ctrl_memOp == 3'h4 ? _GEN[ex_res[1:0]] : io_mem_rdata)
      : ex_res;	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21, :27:26, :28:{29,46,64}, :31:25, :33:21, :34:{22,42,58,76,82}, :35:{21,37,59}, :36:{13,21}, :39:21, :41:{14,23}, :42:15, :43:{21,30}, :44:15, :45:{21,30}, :46:15, :48:15, :55:19
  assign io_wb_rd = ex_rd;	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
  assign io_wb_we = ex_ctrl_we;	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
  assign io_fwd_rd = ex_rd;	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
  assign io_fwd_wdata = ex_res;	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
  assign io_fwd_we = ex_ctrl_we;	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21
  assign io_hzd_memOp = (ex_ctrl_memWrite | ex_ctrl_memRead) & ex_valid;	// <stdin>:875:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Memory.scala:23:21, :66:{37,57}
  assign io_hzd_ack = io_mem_ack;	// <stdin>:875:3
endmodule

module Writeback(	// <stdin>:978:3
  input         clock,	// <stdin>:979:11
                reset,	// <stdin>:980:11
                io_mem_valid,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:8:14
  input  [31:0] io_mem_res,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:8:14
  input  [4:0]  io_mem_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:8:14
  input         io_mem_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:8:14
  output [4:0]  io_out_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:8:14
  output [31:0] io_out_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:8:14
  output        io_out_we	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:8:14
);

  reg        mem_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
  reg [31:0] mem_res;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
  reg [4:0]  mem_rd;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
  reg        mem_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
  always @(posedge clock) begin	// <stdin>:979:11
    if (reset) begin	// <stdin>:979:11
      mem_valid <= 1'h0;	// <stdin>:978:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
      mem_res <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:{22,62}
      mem_rd <= 5'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:{22,62}
      mem_we <= 1'h0;	// <stdin>:978:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
    end
    else begin	// <stdin>:979:11
      mem_valid <= io_mem_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
      mem_res <= io_mem_res;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
      mem_rd <= io_mem_rd;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
      mem_we <= io_mem_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
    end
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:978:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:978:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:978:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:978:3
      automatic logic [31:0] _RANDOM[0:1];	// <stdin>:978:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:978:3
        `INIT_RANDOM_PROLOG_	// <stdin>:978:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:978:3
        for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
          _RANDOM[i[0]] = `RANDOM;	// <stdin>:978:3
        end	// <stdin>:978:3
        mem_valid = _RANDOM[1'h0][0];	// <stdin>:978:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
        mem_res = {_RANDOM[1'h0][31:1], _RANDOM[1'h1][0]};	// <stdin>:978:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
        mem_rd = _RANDOM[1'h1][5:1];	// <stdin>:978:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
        mem_we = _RANDOM[1'h1][6];	// <stdin>:978:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:978:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:978:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  assign io_out_rd = mem_rd;	// <stdin>:978:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
  assign io_out_wdata = mem_res;	// <stdin>:978:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22
  assign io_out_we = mem_we & mem_valid;	// <stdin>:978:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\stages\\Writeback.scala:13:22, :14:23
endmodule

module HazardDetection(	// <stdin>:1000:3
  input  [4:0] io_ID_rs1,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:33:14
               io_ID_rs2,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:33:14
  input        io_EX_memRead,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:33:14
  input  [4:0] io_EX_rd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:33:14
  input        io_EX_loadPC,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:33:14
               io_MEM_memOp,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:33:14
               io_MEM_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:33:14
  output       io_IF_flush,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:33:14
               io_IF_stall,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:33:14
               io_ID_flush,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:33:14
               io_ID_stall,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:33:14
               io_EX_stall,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:33:14
               io_MEM_stall	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:33:14
);

  wire _GEN = io_MEM_memOp & ~io_MEM_ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:51:{22,25}
  wire _GEN_0 =
    io_EX_memRead & (|io_EX_rd) & (io_ID_rs1 == io_EX_rd | io_ID_rs2 == io_EX_rd) | _GEN;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:51:{22,38}, :63:{34,42,56,69,82,97}, :64:17
  assign io_IF_flush = io_EX_loadPC;	// <stdin>:1000:3
  assign io_IF_stall = _GEN_0;	// <stdin>:1000:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:51:38, :63:97, :64:17
  assign io_ID_flush = io_EX_loadPC;	// <stdin>:1000:3
  assign io_ID_stall = _GEN_0;	// <stdin>:1000:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:51:38, :63:97, :64:17
  assign io_EX_stall = _GEN;	// <stdin>:1000:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:51:22
  assign io_MEM_stall = _GEN;	// <stdin>:1000:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\modules\\HazardDetection.scala:51:22
endmodule

module Core(	// <stdin>:1032:3
  input         clock,	// <stdin>:1033:11
                reset,	// <stdin>:1034:11
                io_imem_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:8:14
  input  [31:0] io_imem_resp_rdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:8:14
  input         io_dmem_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:8:14
  input  [31:0] io_dmem_resp_rdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:8:14
  output [31:0] io_imem_req_addr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:8:14
  output        io_dmem_req_req,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:8:14
  output [31:0] io_dmem_req_addr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:8:14
                io_dmem_req_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:8:14
  output        io_dmem_req_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:8:14
  output [3:0]  io_dmem_req_wmask	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:8:14
);

  wire        _hazard_io_IF_flush;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:21:22
  wire        _hazard_io_IF_stall;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:21:22
  wire        _hazard_io_ID_flush;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:21:22
  wire        _hazard_io_ID_stall;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:21:22
  wire        _hazard_io_EX_stall;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:21:22
  wire        _hazard_io_MEM_stall;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:21:22
  wire [4:0]  _writeback_io_out_rd;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:20:25
  wire [31:0] _writeback_io_out_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:20:25
  wire        _writeback_io_out_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:20:25
  wire        _memory_io_wb_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
  wire [31:0] _memory_io_wb_res;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
  wire [4:0]  _memory_io_wb_rd;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
  wire        _memory_io_wb_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
  wire [4:0]  _memory_io_fwd_rd;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
  wire [31:0] _memory_io_fwd_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
  wire        _memory_io_fwd_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
  wire        _memory_io_hzd_memOp;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
  wire        _memory_io_hzd_ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
  wire        _execute_io_memstage_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
  wire [31:0] _execute_io_memstage_res;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
  wire [4:0]  _execute_io_memstage_rd;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
  wire        _execute_io_memstage_ctrl_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
  wire        _execute_io_memstage_ctrl_memRead;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
  wire        _execute_io_memstage_ctrl_memWrite;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
  wire [2:0]  _execute_io_memstage_ctrl_memOp;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
  wire        _execute_io_fetch_loadPC;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
  wire [31:0] _execute_io_fetch_newPC;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
  wire        _execute_io_hzd_memRead;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
  wire [4:0]  _execute_io_hzd_rd;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
  wire        _execute_io_hzd_loadPC;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
  wire        _decode_io_ex_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire [31:0] _decode_io_ex_imm;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire [31:0] _decode_io_ex_v1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire [31:0] _decode_io_ex_v2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire [4:0]  _decode_io_ex_rs1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire [4:0]  _decode_io_ex_rs2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire [31:0] _decode_io_ex_pc;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire [4:0]  _decode_io_ex_rd;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire [3:0]  _decode_io_ex_aluOp;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire        _decode_io_ex_pcNextSrc;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire        _decode_io_ex_ctrl_op2src;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire        _decode_io_ex_ctrl_branch;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire        _decode_io_ex_ctrl_jump;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire        _decode_io_ex_ctrl_memRead;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire        _decode_io_ex_ctrl_memWrite;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire [2:0]  _decode_io_ex_ctrl_memOp;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire        _decode_io_ex_ctrl_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire [4:0]  _decode_io_hzd_rs1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire [4:0]  _decode_io_hzd_rs2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
  wire [31:0] _fetch_io_id_instr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:16:21
  wire [31:0] _fetch_io_id_pc;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:16:21
  wire        _fetch_io_id_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:16:21
  Fetch fetch (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:16:21
    .clock             (clock),
    .reset             (reset),
    .io_mem_resp_ack   (io_imem_resp_ack),
    .io_mem_resp_rdata (io_imem_resp_rdata),
    .io_ctrl_loadPC    (_execute_io_fetch_loadPC),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
    .io_ctrl_newPC     (_execute_io_fetch_newPC),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
    .io_hzd_flush      (_hazard_io_IF_flush),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:21:22
    .io_hzd_stall      (_hazard_io_IF_stall),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:21:22
    .io_mem_req_addr   (io_imem_req_addr),
    .io_id_instr       (_fetch_io_id_instr),
    .io_id_pc          (_fetch_io_id_pc),
    .io_id_valid       (_fetch_io_id_valid)
  );
  Decode decode (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .clock               (clock),
    .reset               (reset),
    .io_fetch_instr      (_fetch_io_id_instr),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:16:21
    .io_fetch_pc         (_fetch_io_id_pc),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:16:21
    .io_fetch_valid      (_fetch_io_id_valid),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:16:21
    .io_wb_rd            (_writeback_io_out_rd),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:20:25
    .io_wb_wdata         (_writeback_io_out_wdata),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:20:25
    .io_wb_we            (_writeback_io_out_we),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:20:25
    .io_hzd_flush        (_hazard_io_ID_flush),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:21:22
    .io_hzd_stall        (_hazard_io_ID_stall),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:21:22
    .io_ex_valid         (_decode_io_ex_valid),
    .io_ex_imm           (_decode_io_ex_imm),
    .io_ex_v1            (_decode_io_ex_v1),
    .io_ex_v2            (_decode_io_ex_v2),
    .io_ex_rs1           (_decode_io_ex_rs1),
    .io_ex_rs2           (_decode_io_ex_rs2),
    .io_ex_pc            (_decode_io_ex_pc),
    .io_ex_rd            (_decode_io_ex_rd),
    .io_ex_aluOp         (_decode_io_ex_aluOp),
    .io_ex_pcNextSrc     (_decode_io_ex_pcNextSrc),
    .io_ex_ctrl_op2src   (_decode_io_ex_ctrl_op2src),
    .io_ex_ctrl_branch   (_decode_io_ex_ctrl_branch),
    .io_ex_ctrl_jump     (_decode_io_ex_ctrl_jump),
    .io_ex_ctrl_memRead  (_decode_io_ex_ctrl_memRead),
    .io_ex_ctrl_memWrite (_decode_io_ex_ctrl_memWrite),
    .io_ex_ctrl_memOp    (_decode_io_ex_ctrl_memOp),
    .io_ex_ctrl_we       (_decode_io_ex_ctrl_we),
    .io_hzd_rs1          (_decode_io_hzd_rs1),
    .io_hzd_rs2          (_decode_io_hzd_rs2)
  );
  Execute execute (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
    .clock                     (clock),
    .reset                     (reset),
    .io_id_valid               (_decode_io_ex_valid),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_imm                 (_decode_io_ex_imm),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_v1                  (_decode_io_ex_v1),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_v2                  (_decode_io_ex_v2),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_rs1                 (_decode_io_ex_rs1),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_rs2                 (_decode_io_ex_rs2),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_pc                  (_decode_io_ex_pc),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_rd                  (_decode_io_ex_rd),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_aluOp               (_decode_io_ex_aluOp),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_pcNextSrc           (_decode_io_ex_pcNextSrc),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_ctrl_op2src         (_decode_io_ex_ctrl_op2src),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_ctrl_branch         (_decode_io_ex_ctrl_branch),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_ctrl_jump           (_decode_io_ex_ctrl_jump),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_ctrl_memRead        (_decode_io_ex_ctrl_memRead),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_ctrl_memWrite       (_decode_io_ex_ctrl_memWrite),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_ctrl_memOp          (_decode_io_ex_ctrl_memOp),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_id_ctrl_we             (_decode_io_ex_ctrl_we),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_memFwd_rd              (_memory_io_fwd_rd),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
    .io_memFwd_wdata           (_memory_io_fwd_wdata),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
    .io_memFwd_we              (_memory_io_fwd_we),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
    .io_wbFwd_rd               (_writeback_io_out_rd),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:20:25
    .io_wbFwd_wdata            (_writeback_io_out_wdata),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:20:25
    .io_wbFwd_we               (_writeback_io_out_we),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:20:25
    .io_hzd_stall              (_hazard_io_EX_stall),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:21:22
    .io_memstage_valid         (_execute_io_memstage_valid),
    .io_memstage_res           (_execute_io_memstage_res),
    .io_memstage_rd            (_execute_io_memstage_rd),
    .io_memstage_ctrl_we       (_execute_io_memstage_ctrl_we),
    .io_memstage_ctrl_memRead  (_execute_io_memstage_ctrl_memRead),
    .io_memstage_ctrl_memWrite (_execute_io_memstage_ctrl_memWrite),
    .io_memstage_ctrl_memOp    (_execute_io_memstage_ctrl_memOp),
    .io_mem_req                (io_dmem_req_req),
    .io_mem_addr               (io_dmem_req_addr),
    .io_mem_wdata              (io_dmem_req_wdata),
    .io_mem_we                 (io_dmem_req_we),
    .io_mem_wmask              (io_dmem_req_wmask),
    .io_fetch_loadPC           (_execute_io_fetch_loadPC),
    .io_fetch_newPC            (_execute_io_fetch_newPC),
    .io_hzd_memRead            (_execute_io_hzd_memRead),
    .io_hzd_rd                 (_execute_io_hzd_rd),
    .io_hzd_loadPC             (_execute_io_hzd_loadPC)
  );
  Memory memory (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
    .clock               (clock),
    .reset               (reset),
    .io_ex_valid         (_execute_io_memstage_valid),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
    .io_ex_res           (_execute_io_memstage_res),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
    .io_ex_rd            (_execute_io_memstage_rd),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
    .io_ex_ctrl_we       (_execute_io_memstage_ctrl_we),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
    .io_ex_ctrl_memRead  (_execute_io_memstage_ctrl_memRead),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
    .io_ex_ctrl_memWrite (_execute_io_memstage_ctrl_memWrite),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
    .io_ex_ctrl_memOp    (_execute_io_memstage_ctrl_memOp),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
    .io_mem_ack          (io_dmem_resp_ack),
    .io_mem_rdata        (io_dmem_resp_rdata),
    .io_hzd_stall        (_hazard_io_MEM_stall),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:21:22
    .io_wb_valid         (_memory_io_wb_valid),
    .io_wb_res           (_memory_io_wb_res),
    .io_wb_rd            (_memory_io_wb_rd),
    .io_wb_we            (_memory_io_wb_we),
    .io_fwd_rd           (_memory_io_fwd_rd),
    .io_fwd_wdata        (_memory_io_fwd_wdata),
    .io_fwd_we           (_memory_io_fwd_we),
    .io_hzd_memOp        (_memory_io_hzd_memOp),
    .io_hzd_ack          (_memory_io_hzd_ack)
  );
  Writeback writeback (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:20:25
    .clock        (clock),
    .reset        (reset),
    .io_mem_valid (_memory_io_wb_valid),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
    .io_mem_res   (_memory_io_wb_res),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
    .io_mem_rd    (_memory_io_wb_rd),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
    .io_mem_we    (_memory_io_wb_we),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
    .io_out_rd    (_writeback_io_out_rd),
    .io_out_wdata (_writeback_io_out_wdata),
    .io_out_we    (_writeback_io_out_we)
  );
  HazardDetection hazard (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:21:22
    .io_ID_rs1     (_decode_io_hzd_rs1),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_ID_rs2     (_decode_io_hzd_rs2),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:17:22
    .io_EX_memRead (_execute_io_hzd_memRead),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
    .io_EX_rd      (_execute_io_hzd_rd),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
    .io_EX_loadPC  (_execute_io_hzd_loadPC),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:18:23
    .io_MEM_memOp  (_memory_io_hzd_memOp),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
    .io_MEM_ack    (_memory_io_hzd_ack),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\Core.scala:19:22
    .io_IF_flush   (_hazard_io_IF_flush),
    .io_IF_stall   (_hazard_io_IF_stall),
    .io_ID_flush   (_hazard_io_ID_flush),
    .io_ID_stall   (_hazard_io_ID_stall),
    .io_EX_stall   (_hazard_io_EX_stall),
    .io_MEM_stall  (_hazard_io_MEM_stall)
  );
endmodule

// VCS coverage exclude_file
module mem_2048x32(	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
  input  [10:0] R0_addr,
  input         R0_en,
                R0_clk,
  input  [10:0] W0_addr,
  input         W0_en,
                W0_clk,
  input  [31:0] W0_data,
  input  [3:0]  W0_mask,
  output [31:0] R0_data
);

  reg [31:0] Memory[0:2047];	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
  reg        _R0_en_d0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
  reg [10:0] _R0_addr_d0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
  always @(posedge R0_clk) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
    _R0_en_d0 <= R0_en;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
    _R0_addr_d0 <= R0_addr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
  end // always @(posedge)
  always @(posedge W0_clk) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
    if (W0_en & W0_mask[0])	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
      Memory[W0_addr][32'h0 +: 8] <= W0_data[7:0];	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
    if (W0_en & W0_mask[1])	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
      Memory[W0_addr][32'h8 +: 8] <= W0_data[15:8];	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
    if (W0_en & W0_mask[2])	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
      Memory[W0_addr][32'h10 +: 8] <= W0_data[23:16];	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
    if (W0_en & W0_mask[3])	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
      Memory[W0_addr][32'h18 +: 8] <= W0_data[31:24];	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_MEM_	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
    `ifdef RANDOMIZE_REG_INIT	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
      reg [31:0] _RANDOM;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
    `endif // RANDOMIZE_REG_INIT
    reg [31:0] _RANDOM_MEM;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
    initial begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
      `INIT_RANDOM_PROLOG_	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
      `ifdef RANDOMIZE_MEM_INIT	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
        for (logic [11:0] i = 12'h0; i < 12'h800; i += 12'h1) begin
          _RANDOM_MEM = `RANDOM;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
          Memory[i[10:0]] = _RANDOM_MEM;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
        end	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
      `endif // RANDOMIZE_MEM_INIT
      `ifdef RANDOMIZE_REG_INIT	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
        _RANDOM = {`RANDOM};	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
        _R0_en_d0 = _RANDOM[0];	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
        _R0_addr_d0 = _RANDOM[11:1];	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
      `endif // RANDOMIZE_REG_INIT
    end // initial
  `endif // ENABLE_INITIAL_MEM_
  assign R0_data = _R0_en_d0 ? Memory[_R0_addr_d0] : 32'bx;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
endmodule

module MemBlock(	// <stdin>:1078:3
  input         clock,	// <stdin>:1079:11
                io_req_req,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:13:14
  input  [31:0] io_req_addr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:13:14
                io_req_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:13:14
  input         io_req_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:13:14
  input  [3:0]  io_req_wmask,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:13:14
  output        io_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:13:14
  output [31:0] io_resp_rdata	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:13:14
);

  reg io_resp_ack_REG;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:26:25
  always @(posedge clock)	// <stdin>:1079:11
    io_resp_ack_REG <= io_req_req;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:26:25
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:1078:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:1078:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:1078:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:1078:3
      automatic logic [31:0] _RANDOM[0:0];	// <stdin>:1078:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:1078:3
        `INIT_RANDOM_PROLOG_	// <stdin>:1078:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:1078:3
        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;	// <stdin>:1078:3
        io_resp_ack_REG = _RANDOM[/*Zero width*/ 1'b0][0];	// <stdin>:1078:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:26:25
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:1078:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:1078:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  mem_2048x32 mem_ext (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:16:24
    .R0_addr (io_req_addr[12:2]),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:21:25
    .R0_en   (1'h1),	// <stdin>:1078:3
    .R0_clk  (clock),
    .W0_addr (io_req_addr[12:2]),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:21:25
    .W0_en   (io_req_req & io_req_we),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:22:19
    .W0_clk  (clock),
    .W0_data (io_req_wdata),
    .W0_mask (io_req_wmask),
    .R0_data (io_resp_rdata)
  );
  assign io_resp_ack = io_resp_ack_REG;	// <stdin>:1078:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemBlock.scala:26:25
endmodule

module Rx(	// <stdin>:1215:3, :1657:3
  input        clock,	// <stdin>:1216:11, :1658:11
               reset,	// <stdin>:1217:11, :1659:11
               io_rxd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:83:14
               io_channel_ready,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:83:14
  output       io_channel_valid,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:83:14
  output [7:0] io_channel_bits	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:83:14
);

  reg        rxReg_REG;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:93:30
  reg        rxReg;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:93:22
  reg [7:0]  shiftReg;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:95:25
  reg [19:0] cntReg;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:96:23
  reg [3:0]  bitsReg;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:97:24
  reg        valReg;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:98:23
  always @(posedge clock) begin	// <stdin>:1216:11, :1658:11
    if (reset) begin	// <stdin>:1216:11, :1658:11
      rxReg_REG <= 1'h1;	// <stdin>:1215:3, :1657:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:93:30
      rxReg <= 1'h1;	// <stdin>:1215:3, :1657:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:93:22
      shiftReg <= 8'h41;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:95:25
      cntReg <= 20'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:96:23
      bitsReg <= 4'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:97:24
      valReg <= 1'h0;	// <stdin>:1215:3, :1657:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:98:23
    end
    else begin	// <stdin>:1216:11, :1658:11
      rxReg_REG <= io_rxd;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:93:30
      rxReg <= rxReg_REG;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:93:{22,30}
      if ((|cntReg) | ~(|bitsReg)) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:95:25, :96:23, :97:24, :100:{15,24}, :102:{22,31}
      end
      else	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:95:25, :100:24, :102:31
        shiftReg <= {rxReg, shiftReg[7:1]};	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:93:22, :95:25, :104:{20,37}
      if (|cntReg)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:96:23, :100:15
        cntReg <= cntReg - 20'h1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:96:23, :101:22
      else if (|bitsReg) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:97:24, :102:22
        cntReg <= 20'h2B5;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:96:23, :103:12
        bitsReg <= bitsReg - 4'h1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:97:24, :105:24
      end
      else if (rxReg) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:93:22
      end
      else begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:93:22
        cntReg <= 20'h411;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:96:23, :112:12
        bitsReg <= 4'h8;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:97:24, :113:13
      end
      valReg <=
        ~(valReg & io_channel_ready)
        & (~(|cntReg) & (|bitsReg) & bitsReg == 4'h1 | valReg);	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:96:23, :97:24, :98:23, :100:{15,24}, :102:{22,31}, :107:18, :116:{15,36}, :117:12
    end
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:1215:3, :1657:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:1215:3, :1657:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:1215:3, :1657:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:1215:3, :1657:3
      automatic logic [31:0] _RANDOM[0:1];	// <stdin>:1215:3, :1657:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:1215:3, :1657:3
        `INIT_RANDOM_PROLOG_	// <stdin>:1215:3, :1657:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:1215:3, :1657:3
        for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
          _RANDOM[i[0]] = `RANDOM;	// <stdin>:1215:3, :1657:3
        end	// <stdin>:1215:3, :1657:3
        rxReg_REG = _RANDOM[1'h0][0];	// <stdin>:1215:3, :1657:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:93:30
        rxReg = _RANDOM[1'h0][1];	// <stdin>:1215:3, :1657:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:93:{22,30}
        shiftReg = _RANDOM[1'h0][9:2];	// <stdin>:1215:3, :1657:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:93:30, :95:25
        cntReg = _RANDOM[1'h0][29:10];	// <stdin>:1215:3, :1657:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:93:30, :96:23
        bitsReg = {_RANDOM[1'h0][31:30], _RANDOM[1'h1][1:0]};	// <stdin>:1215:3, :1657:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:93:30, :97:24
        valReg = _RANDOM[1'h1][2];	// <stdin>:1215:3, :1657:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:97:24, :98:23
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:1215:3, :1657:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:1215:3, :1657:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  assign io_channel_valid = valReg;	// <stdin>:1215:3, :1657:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:98:23
  assign io_channel_bits = shiftReg;	// <stdin>:1215:3, :1657:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:95:25
endmodule

module Tx(	// <stdin>:1263:3, :1705:3
  input        clock,	// <stdin>:1264:11, :1706:11
               reset,	// <stdin>:1265:11, :1707:11
               io_channel_valid,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:36:14
  input  [7:0] io_channel_bits,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:36:14
  output       io_txd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:36:14
               io_channel_ready	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:36:14
);

  reg  [10:0] shiftReg;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:43:25
  reg  [19:0] cntReg;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:44:23
  reg  [3:0]  bitsReg;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:45:24
  wire        _io_channel_ready_T = cntReg == 20'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:44:23, :47:31
  always @(posedge clock) begin	// <stdin>:1264:11, :1706:11
    if (reset) begin	// <stdin>:1264:11, :1706:11
      shiftReg <= 11'h7FF;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:43:25
      cntReg <= 20'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:44:23
      bitsReg <= 4'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:45:24
    end
    else if (_io_channel_ready_T) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:47:31
      if (|bitsReg) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:45:24, :47:52
        shiftReg <= {1'h1, shiftReg[10:1]};	// <stdin>:1263:3, :1705:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:43:25, :54:28, :55:22
        bitsReg <= bitsReg - 4'h1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:45:24, :56:26
      end
      else if (io_channel_valid) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:36:14
        shiftReg <= {2'h3, io_channel_bits, 1'h0};	// <stdin>:1263:3, :1705:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:43:25, :60:{24,28}
        bitsReg <= 4'hB;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:45:24, :61:17
      end
      else	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:36:14
        shiftReg <= 11'h7FF;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:43:25
      cntReg <= 20'h2B5;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:44:23, :52:12
    end
    else	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:47:31
      cntReg <= cntReg - 20'h1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:44:23, :68:22
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:1263:3, :1705:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:1263:3, :1705:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:1263:3, :1705:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:1263:3, :1705:3
      automatic logic [31:0] _RANDOM[0:1];	// <stdin>:1263:3, :1705:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:1263:3, :1705:3
        `INIT_RANDOM_PROLOG_	// <stdin>:1263:3, :1705:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:1263:3, :1705:3
        for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
          _RANDOM[i[0]] = `RANDOM;	// <stdin>:1263:3, :1705:3
        end	// <stdin>:1263:3, :1705:3
        shiftReg = _RANDOM[1'h0][10:0];	// <stdin>:1263:3, :1705:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:43:25
        cntReg = _RANDOM[1'h0][30:11];	// <stdin>:1263:3, :1705:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:43:25, :44:23
        bitsReg = {_RANDOM[1'h0][31], _RANDOM[1'h1][2:0]};	// <stdin>:1263:3, :1705:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:43:25, :45:24
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:1263:3, :1705:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:1263:3, :1705:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  assign io_txd = shiftReg[0];	// <stdin>:1263:3, :1705:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:43:25, :48:21
  assign io_channel_ready = _io_channel_ready_T & ~(|bitsReg);	// <stdin>:1263:3, :1705:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:45:24, :47:{31,40,52}
endmodule

// VCS coverage exclude_file
module ram_2x8(	// src/main/scala/chisel3/util/Decoupled.scala:257:91
  input        R0_addr,
               R0_en,
               R0_clk,
               W0_addr,
               W0_en,
               W0_clk,
  input  [7:0] W0_data,
  output [7:0] R0_data
);

  reg [7:0] Memory[0:1];	// src/main/scala/chisel3/util/Decoupled.scala:257:91
  always @(posedge W0_clk) begin	// src/main/scala/chisel3/util/Decoupled.scala:257:91
    if (W0_en)	// src/main/scala/chisel3/util/Decoupled.scala:257:91
      Memory[W0_addr] <= W0_data;	// src/main/scala/chisel3/util/Decoupled.scala:257:91
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_MEM_	// src/main/scala/chisel3/util/Decoupled.scala:257:91
    reg [31:0] _RANDOM_MEM;	// src/main/scala/chisel3/util/Decoupled.scala:257:91
    initial begin	// src/main/scala/chisel3/util/Decoupled.scala:257:91
      `INIT_RANDOM_PROLOG_	// src/main/scala/chisel3/util/Decoupled.scala:257:91
      `ifdef RANDOMIZE_MEM_INIT	// src/main/scala/chisel3/util/Decoupled.scala:257:91
        for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
          _RANDOM_MEM = `RANDOM;	// src/main/scala/chisel3/util/Decoupled.scala:257:91
          Memory[i[0]] = _RANDOM_MEM[7:0];	// src/main/scala/chisel3/util/Decoupled.scala:257:91
        end	// src/main/scala/chisel3/util/Decoupled.scala:257:91
      `endif // RANDOMIZE_MEM_INIT
    end // initial
  `endif // ENABLE_INITIAL_MEM_
  assign R0_data = R0_en ? Memory[R0_addr] : 8'bx;	// src/main/scala/chisel3/util/Decoupled.scala:257:91
endmodule

module Queue2_UInt8(	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3
  input        clock,	// <stdin>:1307:11, :1361:11, :1749:11, :1803:11
               reset,	// <stdin>:1308:11, :1362:11, :1750:11, :1804:11
               io_enq_valid,	// src/main/scala/chisel3/util/Decoupled.scala:256:14
  input  [7:0] io_enq_bits,	// src/main/scala/chisel3/util/Decoupled.scala:256:14
  input        io_deq_ready,	// src/main/scala/chisel3/util/Decoupled.scala:256:14
  output       io_enq_ready,	// src/main/scala/chisel3/util/Decoupled.scala:256:14
               io_deq_valid,	// src/main/scala/chisel3/util/Decoupled.scala:256:14
  output [7:0] io_deq_bits,	// src/main/scala/chisel3/util/Decoupled.scala:256:14
  output [1:0] io_count	// src/main/scala/chisel3/util/Decoupled.scala:256:14
);

  reg  wrap;	// src/main/scala/chisel3/util/Counter.scala:61:40
  reg  wrap_1;	// src/main/scala/chisel3/util/Counter.scala:61:40
  reg  maybe_full;	// src/main/scala/chisel3/util/Decoupled.scala:260:27
  wire ptr_match = wrap == wrap_1;	// src/main/scala/chisel3/util/Counter.scala:61:40, src/main/scala/chisel3/util/Decoupled.scala:261:33
  wire empty = ptr_match & ~maybe_full;	// src/main/scala/chisel3/util/Decoupled.scala:260:27, :261:33, :262:{25,28}
  wire full = ptr_match & maybe_full;	// src/main/scala/chisel3/util/Decoupled.scala:260:27, :261:33, :263:24
  wire do_enq = ~full & io_enq_valid;	// src/main/scala/chisel3/util/Decoupled.scala:52:35, :263:24, :287:19
  always @(posedge clock) begin	// <stdin>:1307:11, :1361:11, :1749:11, :1803:11
    if (reset) begin	// <stdin>:1307:11, :1361:11, :1749:11, :1803:11
      wrap <= 1'h0;	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3, src/main/scala/chisel3/util/Counter.scala:61:40
      wrap_1 <= 1'h0;	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3, src/main/scala/chisel3/util/Counter.scala:61:40
      maybe_full <= 1'h0;	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3, src/main/scala/chisel3/util/Decoupled.scala:260:27
    end
    else begin	// <stdin>:1307:11, :1361:11, :1749:11, :1803:11
      automatic logic do_deq = io_deq_ready & ~empty;	// src/main/scala/chisel3/util/Decoupled.scala:52:35, :262:25, :286:19
      if (do_enq)	// src/main/scala/chisel3/util/Decoupled.scala:52:35
        wrap <= wrap - 1'h1;	// src/main/scala/chisel3/util/Counter.scala:61:40, :77:24
      if (do_deq)	// src/main/scala/chisel3/util/Decoupled.scala:52:35
        wrap_1 <= wrap_1 - 1'h1;	// src/main/scala/chisel3/util/Counter.scala:61:40, :77:24
      if (do_deq != do_enq)	// src/main/scala/chisel3/util/Decoupled.scala:52:35, :277:15
        maybe_full <= do_enq;	// src/main/scala/chisel3/util/Decoupled.scala:52:35, :260:27
    end
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3
      automatic logic [31:0] _RANDOM[0:0];	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3
        `INIT_RANDOM_PROLOG_	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3
        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3
        wrap = _RANDOM[/*Zero width*/ 1'b0][0];	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3, src/main/scala/chisel3/util/Counter.scala:61:40
        wrap_1 = _RANDOM[/*Zero width*/ 1'b0][1];	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3, src/main/scala/chisel3/util/Counter.scala:61:40
        maybe_full = _RANDOM[/*Zero width*/ 1'b0][2];	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3, src/main/scala/chisel3/util/Counter.scala:61:40, src/main/scala/chisel3/util/Decoupled.scala:260:27
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  ram_2x8 ram_ext (	// src/main/scala/chisel3/util/Decoupled.scala:257:91
    .R0_addr (wrap_1),	// src/main/scala/chisel3/util/Counter.scala:61:40
    .R0_en   (1'h1),	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3
    .R0_clk  (clock),
    .W0_addr (wrap),	// src/main/scala/chisel3/util/Counter.scala:61:40
    .W0_en   (do_enq),	// src/main/scala/chisel3/util/Decoupled.scala:52:35
    .W0_clk  (clock),
    .W0_data (io_enq_bits),
    .R0_data (io_deq_bits)
  );
  assign io_enq_ready = ~full;	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3, src/main/scala/chisel3/util/Decoupled.scala:263:24, :287:19
  assign io_deq_valid = ~empty;	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3, src/main/scala/chisel3/util/Decoupled.scala:262:25, :286:19
  assign io_count = {maybe_full & ptr_match, wrap - wrap_1};	// <stdin>:1306:3, :1360:3, :1748:3, :1802:3, src/main/scala/chisel3/util/Counter.scala:61:40, src/main/scala/chisel3/util/Decoupled.scala:260:27, :261:33, :310:32, :313:{32,62}
endmodule

module Uart(	// <stdin>:1414:3, :1856:3
  input        clock,	// <stdin>:1415:11, :1857:11
               reset,	// <stdin>:1416:11, :1858:11
               io_rxd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:129:14
               io_rdData_ready,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:129:14
               io_txData_valid,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:129:14
  input  [7:0] io_txData_bits,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:129:14
  output       io_txd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:129:14
  output [7:0] io_rdData_bits,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:129:14
  output [1:0] io_rxCnt,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:129:14
  output       io_rxFull,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:129:14
               io_rxAvail,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:129:14
  output [1:0] io_txCnt,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:129:14
  output       io_txFull	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:129:14
);

  wire       _txBuf_io_deq_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:156:21
  wire [7:0] _txBuf_io_deq_bits;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:156:21
  wire [1:0] _txBuf_io_count;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:156:21
  wire       _rxBuf_io_enq_ready;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:155:21
  wire [1:0] _rxBuf_io_count;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:155:21
  wire       _tx_io_channel_ready;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:154:18
  wire       _rx_io_channel_valid;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:153:18
  wire [7:0] _rx_io_channel_bits;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:153:18
  Rx rx (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:153:18
    .clock            (clock),
    .reset            (reset),
    .io_rxd           (io_rxd),
    .io_channel_ready (_rxBuf_io_enq_ready),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:155:21
    .io_channel_valid (_rx_io_channel_valid),
    .io_channel_bits  (_rx_io_channel_bits)
  );
  Tx tx (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:154:18
    .clock            (clock),
    .reset            (reset),
    .io_channel_valid (_txBuf_io_deq_valid),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:156:21
    .io_channel_bits  (_txBuf_io_deq_bits),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:156:21
    .io_txd           (io_txd),
    .io_channel_ready (_tx_io_channel_ready)
  );
  Queue2_UInt8 rxBuf (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:155:21
    .clock        (clock),
    .reset        (reset),
    .io_enq_valid (_rx_io_channel_valid),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:153:18
    .io_enq_bits  (_rx_io_channel_bits),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:153:18
    .io_deq_ready (io_rdData_ready),
    .io_enq_ready (_rxBuf_io_enq_ready),
    .io_deq_valid (io_rxAvail),
    .io_deq_bits  (io_rdData_bits),
    .io_count     (_rxBuf_io_count)
  );
  Queue2_UInt8 txBuf (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:156:21
    .clock        (clock),
    .reset        (reset),
    .io_enq_valid (io_txData_valid),
    .io_enq_bits  (io_txData_bits),
    .io_deq_ready (_tx_io_channel_ready),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:154:18
    .io_enq_ready (/* unused */),
    .io_deq_valid (_txBuf_io_deq_valid),
    .io_deq_bits  (_txBuf_io_deq_bits),
    .io_count     (_txBuf_io_count)
  );
  assign io_rxCnt = _rxBuf_io_count;	// <stdin>:1414:3, :1856:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:155:21
  assign io_rxFull = _rxBuf_io_count == 2'h2;	// <stdin>:1414:3, :1856:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:155:21, :166:31
  assign io_txCnt = _txBuf_io_count;	// <stdin>:1414:3, :1856:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:156:21
  assign io_txFull = _txBuf_io_count == 2'h2;	// <stdin>:1414:3, :1856:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:156:21, :166:31, :168:31
endmodule

module UartWrapper(	// <stdin>:1447:3
  input         clock,	// <stdin>:1448:11
                reset,	// <stdin>:1449:11
                io_mem_req_req,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:192:14
  input  [31:0] io_mem_req_addr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:192:14
                io_mem_req_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:192:14
  input         io_mem_req_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:192:14
  input  [3:0]  io_mem_req_wmask,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:192:14
  input         io_rxd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:192:14
  output        io_mem_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:192:14
  output [31:0] io_mem_resp_rdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:192:14
  output        io_txd	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:192:14
);

  wire [7:0] _uart_io_rdData_bits;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:199:20
  wire [1:0] _uart_io_rxCnt;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:199:20
  wire       _uart_io_rxFull;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:199:20
  wire       _uart_io_rxAvail;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:199:20
  wire [1:0] _uart_io_txCnt;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:199:20
  wire       _uart_io_txFull;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:199:20
  reg  [7:0] rdData;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:204:23
  reg        ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:205:20
  wire       _GEN = io_mem_req_req & ~io_mem_req_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:213:{23,26}
  always @(posedge clock) begin	// <stdin>:1448:11
    if (reset)	// <stdin>:1448:11
      rdData <= 8'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:204:23
    else if (_GEN) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:213:23
      automatic logic [7:0][7:0] _GEN_0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:204:23, :215:34, :218:16, :221:16, :224:16, :227:16, :231:16, :234:16
      _GEN_0 =
        {{rdData},
         {{6'h0, _uart_io_txCnt}},
         {{7'h0, _uart_io_txFull}},
         {rdData},
         {{7'h0, _uart_io_rxAvail}},
         {{6'h0, _uart_io_rxCnt}},
         {{7'h0, _uart_io_rxFull}},
         {_uart_io_rdData_bits}};	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:199:20, :204:23, :215:34, :218:16, :221:16, :224:16, :227:16, :231:16, :234:16
      rdData <= _GEN_0[io_mem_req_addr[4:2]];	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:204:23, :215:{27,34}, :218:16, :221:16, :224:16, :227:16, :231:16, :234:16
    end
    ack <= io_mem_req_req;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:205:20
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:1447:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:1447:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:1447:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:1447:3
      automatic logic [31:0] _RANDOM[0:0];	// <stdin>:1447:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:1447:3
        `INIT_RANDOM_PROLOG_	// <stdin>:1447:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:1447:3
        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;	// <stdin>:1447:3
        rdData = _RANDOM[/*Zero width*/ 1'b0][7:0];	// <stdin>:1447:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:204:23
        ack = _RANDOM[/*Zero width*/ 1'b0][8];	// <stdin>:1447:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:204:23, :205:20
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:1447:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:1447:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  Uart uart (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:199:20
    .clock           (clock),
    .reset           (reset),
    .io_rxd          (io_rxd),
    .io_rdData_ready (_GEN & io_mem_req_addr[4:2] == 3'h0),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:208:24, :213:{23,42}, :215:{27,34}
    .io_txData_valid (io_mem_req_req & io_mem_req_we & io_mem_req_wmask[0]),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:241:{59,78}
    .io_txData_bits  (io_mem_req_wdata[7:0]),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:210:42
    .io_txd          (io_txd),
    .io_rdData_bits  (_uart_io_rdData_bits),
    .io_rxCnt        (_uart_io_rxCnt),
    .io_rxFull       (_uart_io_rxFull),
    .io_rxAvail      (_uart_io_rxAvail),
    .io_txCnt        (_uart_io_txCnt),
    .io_txFull       (_uart_io_txFull)
  );
  assign io_mem_resp_ack = ack;	// <stdin>:1447:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:205:20
  assign io_mem_resp_rdata = {24'h0, rdData};	// <stdin>:1447:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Uart.scala:204:23, :218:40, :245:21
endmodule

module Keys(	// <stdin>:1504:3
  input         clock,	// <stdin>:1505:11
                io_mem_req_req,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:7:14
  input  [11:0] io_keys,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:7:14
  output        io_mem_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:7:14
  output [31:0] io_mem_resp_rdata	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:7:14
);

  reg [11:0] io_mem_resp_rdata_REG;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:12:39
  reg [11:0] io_mem_resp_rdata_REG_1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:12:31
  reg        io_mem_resp_ack_REG;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:13:29
  always @(posedge clock) begin	// <stdin>:1505:11
    io_mem_resp_rdata_REG <= io_keys;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:12:39
    io_mem_resp_rdata_REG_1 <= io_mem_resp_rdata_REG;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:12:{31,39}
    io_mem_resp_ack_REG <= io_mem_req_req;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:13:29
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:1504:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:1504:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:1504:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:1504:3
      automatic logic [31:0] _RANDOM[0:0];	// <stdin>:1504:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:1504:3
        `INIT_RANDOM_PROLOG_	// <stdin>:1504:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:1504:3
        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;	// <stdin>:1504:3
        io_mem_resp_rdata_REG = _RANDOM[/*Zero width*/ 1'b0][11:0];	// <stdin>:1504:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:12:39
        io_mem_resp_rdata_REG_1 = _RANDOM[/*Zero width*/ 1'b0][23:12];	// <stdin>:1504:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:12:{31,39}
        io_mem_resp_ack_REG = _RANDOM[/*Zero width*/ 1'b0][24];	// <stdin>:1504:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:12:39, :13:29
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:1504:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:1504:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  assign io_mem_resp_ack = io_mem_resp_ack_REG;	// <stdin>:1504:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:13:29
  assign io_mem_resp_rdata = {20'h0, io_mem_resp_rdata_REG_1};	// <stdin>:1504:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Keys.scala:12:{21,31}
endmodule

module Leds(	// <stdin>:1521:3
  input         clock,	// <stdin>:1522:11
                reset,	// <stdin>:1523:11
                io_mem_req_req,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:7:14
  input  [31:0] io_mem_req_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:7:14
  input         io_mem_req_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:7:14
  output        io_mem_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:7:14
  output [31:0] io_mem_resp_rdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:7:14
  output [11:0] io_leds	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:7:14
);

  reg [11:0] leds;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:13:21
  reg [31:0] rdData;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:14:23
  reg        ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:15:20
  always @(posedge clock) begin	// <stdin>:1522:11
    if (reset) begin	// <stdin>:1522:11
      leds <= 12'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:13:21
      rdData <= 32'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:14:23
    end
    else begin	// <stdin>:1522:11
      if (io_mem_req_req & io_mem_req_we)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:22:23
        leds <= io_mem_req_wdata[11:0];	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:13:21, :23:29
      if (io_mem_req_req & ~io_mem_req_we)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:19:{23,26}
        rdData <= {20'h0, leds};	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:13:21, :14:23, :20:12
    end
    ack <= io_mem_req_req;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:15:20
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:1521:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:1521:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:1521:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:1521:3
      automatic logic [31:0] _RANDOM[0:1];	// <stdin>:1521:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:1521:3
        `INIT_RANDOM_PROLOG_	// <stdin>:1521:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:1521:3
        for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
          _RANDOM[i[0]] = `RANDOM;	// <stdin>:1521:3
        end	// <stdin>:1521:3
        leds = _RANDOM[1'h0][11:0];	// <stdin>:1521:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:13:21
        rdData = {_RANDOM[1'h0][31:12], _RANDOM[1'h1][11:0]};	// <stdin>:1521:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:13:21, :14:23
        ack = _RANDOM[1'h1][12];	// <stdin>:1521:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:14:23, :15:20
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:1521:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:1521:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  assign io_mem_resp_ack = ack;	// <stdin>:1521:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:15:20
  assign io_mem_resp_rdata = rdData;	// <stdin>:1521:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:14:23
  assign io_leds = leds;	// <stdin>:1521:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\Leds.scala:13:21
endmodule

module MemArbiter(	// <stdin>:1545:3
  input         clock,	// <stdin>:1546:11
                io_master_req_req,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  input  [31:0] io_master_req_addr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
                io_master_req_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  input         io_master_req_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  input  [3:0]  io_master_req_wmask,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  input         io_periph_0_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  input  [31:0] io_periph_0_resp_rdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  input         io_periph_1_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  input  [31:0] io_periph_1_resp_rdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  input         io_periph_2_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  input  [31:0] io_periph_2_resp_rdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  input         io_periph_3_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  input  [31:0] io_periph_3_resp_rdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  output        io_master_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  output [31:0] io_master_resp_rdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  output        io_periph_0_req_req,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  output [31:0] io_periph_0_req_addr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
                io_periph_0_req_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  output        io_periph_0_req_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  output [3:0]  io_periph_0_req_wmask,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  output        io_periph_1_req_req,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  output [31:0] io_periph_1_req_addr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
                io_periph_1_req_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  output        io_periph_1_req_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  output [3:0]  io_periph_1_req_wmask,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  output        io_periph_2_req_req,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
                io_periph_3_req_req,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  output [31:0] io_periph_3_req_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
  output        io_periph_3_req_we	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:14:14
);

  wire periphActivated = io_master_req_req & io_master_req_addr[31:24] == 8'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:{45,66,75}
  reg  REG;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:44:17
  wire periphActivated_1 = io_master_req_req & io_master_req_addr[31:24] == 8'h1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:{45,66,75}
  reg  REG_1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:44:17
  wire periphActivated_2 = io_master_req_req & io_master_req_addr[31:24] == 8'h3;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:{45,66,75}
  reg  REG_2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:44:17
  wire periphActivated_3 = io_master_req_req & io_master_req_addr[31:24] == 8'h2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:{45,66,75}
  reg  REG_3;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:44:17
  always @(posedge clock) begin	// <stdin>:1546:11
    REG <= periphActivated;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:45, :44:17
    REG_1 <= periphActivated_1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:45, :44:17
    REG_2 <= periphActivated_2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:45, :44:17
    REG_3 <= periphActivated_3;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:45, :44:17
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:1545:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:1545:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:1545:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:1545:3
      automatic logic [31:0] _RANDOM[0:0];	// <stdin>:1545:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:1545:3
        `INIT_RANDOM_PROLOG_	// <stdin>:1545:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:1545:3
        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;	// <stdin>:1545:3
        REG = _RANDOM[/*Zero width*/ 1'b0][0];	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:44:17
        REG_1 = _RANDOM[/*Zero width*/ 1'b0][1];	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:44:17
        REG_2 = _RANDOM[/*Zero width*/ 1'b0][2];	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:44:17
        REG_3 = _RANDOM[/*Zero width*/ 1'b0][3];	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:44:17
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:1545:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:1545:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  assign io_master_resp_ack =
    REG_3
      ? io_periph_3_resp_ack
      : REG_2
          ? io_periph_2_resp_ack
          : REG_1 ? io_periph_1_resp_ack : REG & io_periph_0_resp_ack;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:28:40, :44:{17,36}, :45:22
  assign io_master_resp_rdata =
    REG_3
      ? io_periph_3_resp_rdata
      : REG_2
          ? io_periph_2_resp_rdata
          : REG_1 ? io_periph_1_resp_rdata : REG ? io_periph_0_resp_rdata : 32'h0;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:28:40, :44:{17,36}, :45:22
  assign io_periph_0_req_req = periphActivated & io_master_req_req;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:45, :32:27, :33:18, :35:40
  assign io_periph_0_req_addr = periphActivated ? io_master_req_addr : 32'h0;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:28:40, :31:45, :32:27, :33:18, :35:40
  assign io_periph_0_req_wdata = periphActivated ? io_master_req_wdata : 32'h0;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:28:40, :31:45, :32:27, :33:18, :35:40
  assign io_periph_0_req_we = periphActivated & io_master_req_we;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:45, :32:27, :33:18, :35:40
  assign io_periph_0_req_wmask = periphActivated ? io_master_req_wmask : 4'h0;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:45, :32:27, :33:18, :35:40
  assign io_periph_1_req_req = periphActivated_1 & io_master_req_req;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:45, :32:27, :33:18, :35:40
  assign io_periph_1_req_addr = periphActivated_1 ? io_master_req_addr : 32'h0;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:28:40, :31:45, :32:27, :33:18, :35:40
  assign io_periph_1_req_wdata = periphActivated_1 ? io_master_req_wdata : 32'h0;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:28:40, :31:45, :32:27, :33:18, :35:40
  assign io_periph_1_req_we = periphActivated_1 & io_master_req_we;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:45, :32:27, :33:18, :35:40
  assign io_periph_1_req_wmask = periphActivated_1 ? io_master_req_wmask : 4'h0;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:45, :32:27, :33:18, :35:40
  assign io_periph_2_req_req = periphActivated_2 & io_master_req_req;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:45, :32:27, :33:18, :35:40
  assign io_periph_3_req_req = periphActivated_3 & io_master_req_req;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:45, :32:27, :33:18, :35:40
  assign io_periph_3_req_wdata = periphActivated_3 ? io_master_req_wdata : 32'h0;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:28:40, :31:45, :32:27, :33:18, :35:40
  assign io_periph_3_req_we = periphActivated_3 & io_master_req_we;	// <stdin>:1545:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemArbiter.scala:31:45, :32:27, :33:18, :35:40
endmodule

module MemMux(	// <stdin>:1618:3
  input         clock,	// <stdin>:1619:11
                reset,	// <stdin>:1620:11
  input  [31:0] io_imem_req_addr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
  input         io_dmem_req_req,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
  input  [31:0] io_dmem_req_addr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
                io_dmem_req_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
  input         io_dmem_req_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
  input  [3:0]  io_dmem_req_wmask,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
  input         io_mem_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
  input  [31:0] io_mem_resp_rdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
  output        io_imem_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
  output [31:0] io_imem_resp_rdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
  output        io_dmem_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
  output [31:0] io_dmem_resp_rdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
  output        io_mem_req_req,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
  output [31:0] io_mem_req_addr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
                io_mem_req_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
  output        io_mem_req_we,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
  output [3:0]  io_mem_req_wmask	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14
);

  reg  state;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:19:22
  wire _io_imem_resp_ack_output = state & io_mem_resp_ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:19:22, :24:17, :33:17
  wire _GEN = io_dmem_req_req & _io_imem_resp_ack_output;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:24:17, :33:17, :45:28
  wire _GEN_0 = (~state | _io_imem_resp_ack_output) & io_dmem_req_req;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:19:22, :24:17, :33:17, :35:18, :37:49, :38:20, :43:18, :45:71, :46:20
  always @(posedge clock) begin	// <stdin>:1619:11
    if (reset)	// <stdin>:1619:11
      state <= 1'h0;	// <stdin>:1618:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:19:22
    else if (state)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:19:22
      state <= ~(state & _GEN) & state;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:19:22, :33:17, :45:{28,71}, :47:15
    else	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:19:22
      state <= ~io_dmem_req_req | state;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:19:22, :37:{31,49}, :39:15
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:1618:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:1618:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:1618:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:1618:3
      automatic logic [31:0] _RANDOM[0:0];	// <stdin>:1618:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:1618:3
        `INIT_RANDOM_PROLOG_	// <stdin>:1618:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:1618:3
        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;	// <stdin>:1618:3
        state = _RANDOM[/*Zero width*/ 1'b0][0];	// <stdin>:1618:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:19:22
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:1618:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:1618:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  assign io_imem_resp_ack = _io_imem_resp_ack_output;	// <stdin>:1618:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:24:17, :33:17
  assign io_imem_resp_rdata = io_mem_resp_rdata;	// <stdin>:1618:3
  assign io_dmem_resp_ack = ~state & io_mem_resp_ack;	// <stdin>:1618:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:19:22, :24:17, :33:17, :36:20
  assign io_dmem_resp_rdata = io_mem_resp_rdata;	// <stdin>:1618:3
  assign io_mem_req_req = ~state | state & (~_GEN | io_dmem_req_req);	// <stdin>:1618:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:19:22, :27:18, :33:17, :37:49, :43:18, :45:{28,71}, :46:20
  assign io_mem_req_addr = _GEN_0 ? io_dmem_req_addr : io_imem_req_addr;	// <stdin>:1618:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:33:17, :35:18, :37:49, :38:20, :43:18, :45:71, :46:20
  assign io_mem_req_wdata = _GEN_0 ? io_dmem_req_wdata : 32'h0;	// <stdin>:1618:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14, :33:17, :35:18, :37:49, :38:20, :43:18, :45:71, :46:20
  assign io_mem_req_we = state ? _GEN & io_dmem_req_we : io_dmem_req_req & io_dmem_req_we;	// <stdin>:1618:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:19:22, :33:17, :35:18, :37:49, :38:20, :43:18, :45:{28,71}, :46:20
  assign io_mem_req_wmask = _GEN_0 ? io_dmem_req_wmask : 4'h0;	// <stdin>:1618:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\MemMux.scala:13:14, :33:17, :35:18, :37:49, :38:20, :43:18, :45:71, :46:20
endmodule

module HWBootloader(	// <stdin>:1889:3
  input         clock,	// <stdin>:1890:11
                reset,	// <stdin>:1891:11
                io_mem_resp_ack,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:12:14
                io_rxd,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:12:14
  output        io_mem_req_req,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:12:14
  output [31:0] io_mem_req_addr,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:12:14
                io_mem_req_wdata,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:12:14
  output [3:0]  io_mem_req_wmask,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:12:14
  output        io_go	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:12:14
);

  wire [7:0]  _uart_io_rdData_bits;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:20:20
  wire        _uart_io_rxAvail;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:20:20
  reg  [2:0]  state;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22
  reg  [7:0]  cnt;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:25:20
  reg  [7:0]  numBytesInTx;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:26:29
  reg  [3:0]  wmask;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:27:22
  reg  [13:0] addr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:28:21
  reg  [7:0]  byte_0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:29:21
  wire        _GEN = state == 3'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :37:17, :50:15
  wire        _GEN_0 = state == 3'h1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :37:17, :40:15
  wire        _GEN_1 = cnt == numBytesInTx;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:25:20, :26:29, :47:16
  wire        _GEN_2 = _GEN_1 & ~(&numBytesInTx);	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:26:29, :32:{22,36}, :47:{16,33}
  wire        _GEN_3 = _GEN_1 & (&numBytesInTx);	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:26:29, :32:36, :47:16, :49:40
  wire        _GEN_4 = _GEN_2 | _GEN_3;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:29:21, :47:{33,50}, :49:{40,58}, :51:36
  always @(posedge clock) begin	// <stdin>:1890:11
    if (reset) begin	// <stdin>:1890:11
      state <= 3'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :50:15
      cnt <= 8'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:25:20
      numBytesInTx <= 8'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:25:20, :26:29
      wmask <= 4'h1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:27:22
      addr <= 14'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:28:21
      byte_0 <= 8'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:25:20, :29:21
    end
    else begin	// <stdin>:1890:11
      automatic logic _GEN_5;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:37:17
      automatic logic _GEN_6;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:37:17
      automatic logic _GEN_7;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:28:21, :37:17
      automatic logic _GEN_8;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:28:21, :37:17
      _GEN_5 = state == 3'h2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :37:17, :52:15
      _GEN_6 = state == 3'h3;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :37:17, :59:15
      _GEN_7 = _GEN_0 | _GEN_5;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:28:21, :37:17
      _GEN_8 = _GEN | _GEN_7;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:28:21, :37:17
      if (_GEN) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:37:17
        if (_uart_io_rxAvail) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:20:20
          state <= 3'h1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :40:15
          cnt <= 8'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:25:20
        end
      end
      else begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:37:17
        if (_GEN_0) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:37:17
          if (_GEN_2)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:47:33
            state <= 3'h4;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :48:15
          else if (_GEN_3)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:49:40
            state <= 3'h0;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :50:15
          else if (_uart_io_rxAvail)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:20:20
            state <= 3'h2;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :52:15
        end
        else if (_GEN_5) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:37:17
          if (io_mem_resp_ack)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:12:14
            state <= 3'h3;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :59:15
        end
        else if (_GEN_6)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:37:17
          state <= 3'h1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :40:15
        if (_GEN_7 | ~_GEN_6) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:25:20, :27:22, :28:21, :37:17
        end
        else	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:25:20, :37:17
          cnt <= cnt + 8'h1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:25:20, :66:18
      end
      if (_GEN & _uart_io_rxAvail)	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:20:20, :26:29, :37:17, :39:29, :42:22
        numBytesInTx <= _uart_io_rdData_bits;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:20:20, :26:29
      if (_GEN_8 | ~_GEN_6) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:27:22, :28:21, :37:17
      end
      else	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:27:22, :37:17
        wmask <= {wmask[2:0], wmask[3]};	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:27:22, :64:24, :65:{21,27}
      if (_GEN_8 | ~(_GEN_6 & wmask[3])) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:27:22, :28:21, :37:17, :64:{12,18,24}
      end
      else	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:28:21, :37:17
        addr <= addr + 14'h1;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:28:21, :64:34
      if (_GEN | ~_GEN_0 | _GEN_4 | ~_uart_io_rxAvail) begin	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:20:20, :29:21, :37:17, :47:50, :49:58, :51:36
      end
      else	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:29:21, :37:17
        byte_0 <= _uart_io_rdData_bits;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:20:20, :29:21
    end
  end // always @(posedge)
  `ifdef ENABLE_INITIAL_REG_	// <stdin>:1889:3
    `ifdef FIRRTL_BEFORE_INITIAL	// <stdin>:1889:3
      `FIRRTL_BEFORE_INITIAL	// <stdin>:1889:3
    `endif // FIRRTL_BEFORE_INITIAL
    initial begin	// <stdin>:1889:3
      automatic logic [31:0] _RANDOM[0:1];	// <stdin>:1889:3
      `ifdef INIT_RANDOM_PROLOG_	// <stdin>:1889:3
        `INIT_RANDOM_PROLOG_	// <stdin>:1889:3
      `endif // INIT_RANDOM_PROLOG_
      `ifdef RANDOMIZE_REG_INIT	// <stdin>:1889:3
        for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
          _RANDOM[i[0]] = `RANDOM;	// <stdin>:1889:3
        end	// <stdin>:1889:3
        state = _RANDOM[1'h0][3:1];	// <stdin>:1889:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22
        cnt = _RANDOM[1'h0][11:4];	// <stdin>:1889:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :25:20
        numBytesInTx = _RANDOM[1'h0][19:12];	// <stdin>:1889:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :26:29
        wmask = _RANDOM[1'h0][23:20];	// <stdin>:1889:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :27:22
        addr = {_RANDOM[1'h0][31:24], _RANDOM[1'h1][5:0]};	// <stdin>:1889:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :28:21
        byte_0 = _RANDOM[1'h1][13:6];	// <stdin>:1889:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:28:21, :29:21
      `endif // RANDOMIZE_REG_INIT
    end // initial
    `ifdef FIRRTL_AFTER_INITIAL	// <stdin>:1889:3
      `FIRRTL_AFTER_INITIAL	// <stdin>:1889:3
    `endif // FIRRTL_AFTER_INITIAL
  `endif // ENABLE_INITIAL_REG_
  Uart uart (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:20:20
    .clock           (clock),
    .reset           (reset),
    .io_rxd          (io_rxd),
    .io_rdData_ready ((_GEN | _GEN_0 & ~_GEN_4) & _uart_io_rxAvail),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:20:20, :29:21, :33:24, :37:17, :39:29, :47:50, :49:58, :51:36
    .io_txData_valid (1'h0),	// <stdin>:1889:3
    .io_txData_bits  (8'h0),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:25:20
    .io_txd          (/* unused */),
    .io_rdData_bits  (_uart_io_rdData_bits),
    .io_rxCnt        (/* unused */),
    .io_rxFull       (/* unused */),
    .io_rxAvail      (_uart_io_rxAvail),
    .io_txCnt        (/* unused */),
    .io_txFull       (/* unused */)
  );
  assign io_mem_req_req = state == 3'h2 & ~io_mem_resp_ack;	// <stdin>:1889:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :52:15, :74:{27,37,40}
  assign io_mem_req_addr = {16'h0, addr, 2'h0};	// <stdin>:1889:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:28:21, :71:{32,40}
  assign io_mem_req_wdata = {2{{2{byte_0}}}};	// <stdin>:1889:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:29:21, :72:27
  assign io_mem_req_wmask = wmask;	// <stdin>:1889:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:27:22
  assign io_go = state == 3'h4;	// <stdin>:1889:3, C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\peripherals\\HWBootloader.scala:24:22, :48:15, :75:18
endmodule

module CoreWrapper(	// <stdin>:1986:3
  input         clock,	// <stdin>:1987:11
                reset,	// <stdin>:1988:11
                io_uart_rx,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:12:14
  input  [11:0] io_keys,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:12:14
  output        io_uart_tx,	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:12:14
  output [11:0] io_leds	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:12:14
);

  wire        _bootloader_io_mem_req_req;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:35:26
  wire [31:0] _bootloader_io_mem_req_addr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:35:26
  wire [31:0] _bootloader_io_mem_req_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:35:26
  wire [3:0]  _bootloader_io_mem_req_wmask;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:35:26
  wire        _bootloader_io_go;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:35:26
  wire        _memMux_io_imem_resp_ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22
  wire [31:0] _memMux_io_imem_resp_rdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22
  wire        _memMux_io_dmem_resp_ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22
  wire [31:0] _memMux_io_dmem_resp_rdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22
  wire        _memMux_io_mem_req_req;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22
  wire [31:0] _memMux_io_mem_req_addr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22
  wire [31:0] _memMux_io_mem_req_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22
  wire        _memMux_io_mem_req_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22
  wire [3:0]  _memMux_io_mem_req_wmask;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22
  wire        _memArb_io_master_resp_ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire [31:0] _memArb_io_master_resp_rdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire        _memArb_io_periph_0_req_req;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire [31:0] _memArb_io_periph_0_req_addr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire [31:0] _memArb_io_periph_0_req_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire        _memArb_io_periph_0_req_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire [3:0]  _memArb_io_periph_0_req_wmask;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire        _memArb_io_periph_1_req_req;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire [31:0] _memArb_io_periph_1_req_addr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire [31:0] _memArb_io_periph_1_req_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire        _memArb_io_periph_1_req_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire [3:0]  _memArb_io_periph_1_req_wmask;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire        _memArb_io_periph_2_req_req;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire        _memArb_io_periph_3_req_req;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire [31:0] _memArb_io_periph_3_req_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire        _memArb_io_periph_3_req_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
  wire        _leds_io_mem_resp_ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:31:20
  wire [31:0] _leds_io_mem_resp_rdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:31:20
  wire        _keys_io_mem_resp_ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:30:20
  wire [31:0] _keys_io_mem_resp_rdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:30:20
  wire        _uart_io_mem_resp_ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:24:20
  wire [31:0] _uart_io_mem_resp_rdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:24:20
  wire        _memblock_io_resp_ack;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:23:24
  wire [31:0] _memblock_io_resp_rdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:23:24
  wire [31:0] _core_io_imem_req_addr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:22:20
  wire        _core_io_dmem_req_req;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:22:20
  wire [31:0] _core_io_dmem_req_addr;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:22:20
  wire [31:0] _core_io_dmem_req_wdata;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:22:20
  wire        _core_io_dmem_req_we;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:22:20
  wire [3:0]  _core_io_dmem_req_wmask;	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:22:20
  Core core (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:22:20
    .clock              (clock),
    .reset              (reset),
    .io_imem_resp_ack   (_memMux_io_imem_resp_ack),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22
    .io_imem_resp_rdata (_memMux_io_imem_resp_rdata),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22
    .io_dmem_resp_ack   (_memArb_io_master_resp_ack),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_dmem_resp_rdata (_memArb_io_master_resp_rdata),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_imem_req_addr   (_core_io_imem_req_addr),
    .io_dmem_req_req    (_core_io_dmem_req_req),
    .io_dmem_req_addr   (_core_io_dmem_req_addr),
    .io_dmem_req_wdata  (_core_io_dmem_req_wdata),
    .io_dmem_req_we     (_core_io_dmem_req_we),
    .io_dmem_req_wmask  (_core_io_dmem_req_wmask)
  );
  MemBlock memblock (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:23:24
    .clock         (clock),
    .io_req_req
      (_bootloader_io_go ? _memMux_io_mem_req_req : _bootloader_io_mem_req_req),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22, :35:26, :43:27, :44:17, :48:17
    .io_req_addr
      (_bootloader_io_go ? _memMux_io_mem_req_addr : _bootloader_io_mem_req_addr),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22, :35:26, :43:27, :44:17, :48:17
    .io_req_wdata
      (_bootloader_io_go ? _memMux_io_mem_req_wdata : _bootloader_io_mem_req_wdata),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22, :35:26, :43:27, :44:17, :48:17
    .io_req_we     (~_bootloader_io_go | _memMux_io_mem_req_we),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22, :35:26, :43:{8,27}, :44:17, :48:17
    .io_req_wmask
      (_bootloader_io_go ? _memMux_io_mem_req_wmask : _bootloader_io_mem_req_wmask),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22, :35:26, :43:27, :44:17, :48:17
    .io_resp_ack   (_memblock_io_resp_ack),
    .io_resp_rdata (_memblock_io_resp_rdata)
  );
  UartWrapper uart (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:24:20
    .clock             (clock),
    .reset             (reset),
    .io_mem_req_req    (_memArb_io_periph_1_req_req),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_mem_req_addr   (_memArb_io_periph_1_req_addr),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_mem_req_wdata  (_memArb_io_periph_1_req_wdata),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_mem_req_we     (_memArb_io_periph_1_req_we),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_mem_req_wmask  (_memArb_io_periph_1_req_wmask),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_rxd            (io_uart_rx),
    .io_mem_resp_ack   (_uart_io_mem_resp_ack),
    .io_mem_resp_rdata (_uart_io_mem_resp_rdata),
    .io_txd            (io_uart_tx)
  );
  Keys keys (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:30:20
    .clock             (clock),
    .io_mem_req_req    (_memArb_io_periph_2_req_req),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_keys           (io_keys),
    .io_mem_resp_ack   (_keys_io_mem_resp_ack),
    .io_mem_resp_rdata (_keys_io_mem_resp_rdata)
  );
  Leds leds (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:31:20
    .clock             (clock),
    .reset             (reset),
    .io_mem_req_req    (_memArb_io_periph_3_req_req),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_mem_req_wdata  (_memArb_io_periph_3_req_wdata),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_mem_req_we     (_memArb_io_periph_3_req_we),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_mem_resp_ack   (_leds_io_mem_resp_ack),
    .io_mem_resp_rdata (_leds_io_mem_resp_rdata),
    .io_leds           (io_leds)
  );
  MemArbiter memArb (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .clock                  (clock),
    .io_master_req_req      (_core_io_dmem_req_req),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:22:20
    .io_master_req_addr     (_core_io_dmem_req_addr),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:22:20
    .io_master_req_wdata    (_core_io_dmem_req_wdata),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:22:20
    .io_master_req_we       (_core_io_dmem_req_we),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:22:20
    .io_master_req_wmask    (_core_io_dmem_req_wmask),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:22:20
    .io_periph_0_resp_ack   (_memMux_io_dmem_resp_ack),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22
    .io_periph_0_resp_rdata (_memMux_io_dmem_resp_rdata),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22
    .io_periph_1_resp_ack   (_uart_io_mem_resp_ack),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:24:20
    .io_periph_1_resp_rdata (_uart_io_mem_resp_rdata),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:24:20
    .io_periph_2_resp_ack   (_keys_io_mem_resp_ack),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:30:20
    .io_periph_2_resp_rdata (_keys_io_mem_resp_rdata),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:30:20
    .io_periph_3_resp_ack   (_leds_io_mem_resp_ack),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:31:20
    .io_periph_3_resp_rdata (_leds_io_mem_resp_rdata),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:31:20
    .io_master_resp_ack     (_memArb_io_master_resp_ack),
    .io_master_resp_rdata   (_memArb_io_master_resp_rdata),
    .io_periph_0_req_req    (_memArb_io_periph_0_req_req),
    .io_periph_0_req_addr   (_memArb_io_periph_0_req_addr),
    .io_periph_0_req_wdata  (_memArb_io_periph_0_req_wdata),
    .io_periph_0_req_we     (_memArb_io_periph_0_req_we),
    .io_periph_0_req_wmask  (_memArb_io_periph_0_req_wmask),
    .io_periph_1_req_req    (_memArb_io_periph_1_req_req),
    .io_periph_1_req_addr   (_memArb_io_periph_1_req_addr),
    .io_periph_1_req_wdata  (_memArb_io_periph_1_req_wdata),
    .io_periph_1_req_we     (_memArb_io_periph_1_req_we),
    .io_periph_1_req_wmask  (_memArb_io_periph_1_req_wmask),
    .io_periph_2_req_req    (_memArb_io_periph_2_req_req),
    .io_periph_3_req_req    (_memArb_io_periph_3_req_req),
    .io_periph_3_req_wdata  (_memArb_io_periph_3_req_wdata),
    .io_periph_3_req_we     (_memArb_io_periph_3_req_we)
  );
  MemMux memMux (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:33:22
    .clock              (clock),
    .reset              (reset),
    .io_imem_req_addr   (_core_io_imem_req_addr),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:22:20
    .io_dmem_req_req    (_memArb_io_periph_0_req_req),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_dmem_req_addr   (_memArb_io_periph_0_req_addr),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_dmem_req_wdata  (_memArb_io_periph_0_req_wdata),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_dmem_req_we     (_memArb_io_periph_0_req_we),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_dmem_req_wmask  (_memArb_io_periph_0_req_wmask),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:32:22
    .io_mem_resp_ack    (_bootloader_io_go & _memblock_io_resp_ack),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:23:24, :35:26, :43:27, :45:28, :48:17
    .io_mem_resp_rdata  (_bootloader_io_go ? _memblock_io_resp_rdata : 32'h0),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:22:20, :23:24, :33:22, :35:26, :43:27, :46:30, :48:17
    .io_imem_resp_ack   (_memMux_io_imem_resp_ack),
    .io_imem_resp_rdata (_memMux_io_imem_resp_rdata),
    .io_dmem_resp_ack   (_memMux_io_dmem_resp_ack),
    .io_dmem_resp_rdata (_memMux_io_dmem_resp_rdata),
    .io_mem_req_req     (_memMux_io_mem_req_req),
    .io_mem_req_addr    (_memMux_io_mem_req_addr),
    .io_mem_req_wdata   (_memMux_io_mem_req_wdata),
    .io_mem_req_we      (_memMux_io_mem_req_we),
    .io_mem_req_wmask   (_memMux_io_mem_req_wmask)
  );
  HWBootloader bootloader (	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:35:26
    .clock            (clock),
    .reset            (reset),
    .io_mem_resp_ack  (~_bootloader_io_go & _memblock_io_resp_ack),	// C:\\Users\\kaspe\\git\\riscv-core\\src\\main\\scala\\core\\CoreWrapper.scala:23:24, :35:26, :43:{8,27}, :44:17, :49:32
    .io_rxd           (io_uart_rx),
    .io_mem_req_req   (_bootloader_io_mem_req_req),
    .io_mem_req_addr  (_bootloader_io_mem_req_addr),
    .io_mem_req_wdata (_bootloader_io_mem_req_wdata),
    .io_mem_req_wmask (_bootloader_io_mem_req_wmask),
    .io_go            (_bootloader_io_go)
  );
endmodule