diff --git a/config/generic-bigtreetech-skr-mini-e3-v3.0.cfg b/config/generic-bigtreetech-skr-mini-e3-v3.0.cfg index 2ea064b09416..b6a98bb0224b 100644 --- a/config/generic-bigtreetech-skr-mini-e3-v3.0.cfg +++ b/config/generic-bigtreetech-skr-mini-e3-v3.0.cfg @@ -85,11 +85,10 @@ uart_pin: PC11 tx_pin: PC10 uart_address: 3 run_current: 0.650 -stealthchop_threshold: 999999 [heater_bed] heater_pin: PC9 -sensor_type: ATC Semitec 104GT-2 +sensor_type: EPCOS 100K B57560G104F sensor_pin: PC4 control: pid pid_Kp: 54.027 diff --git a/config/generic-mellow-fly-e3-v2.cfg b/config/generic-mellow-fly-e3-v2.cfg new file mode 100644 index 000000000000..6836ea328a0a --- /dev/null +++ b/config/generic-mellow-fly-e3-v2.cfg @@ -0,0 +1,232 @@ +# This file contains common pin mappings for the Mellow Fly-E3-v2. +# To use this config, the firmware should be compiled for the +# STM32F407 with a "32KiB bootloader". + +# The "make flash" command does not work on the Fly-E3-v2. Instead, +# after running "make", copy the generated "out/klipper.bin" file to a +# file named "firmware.bin" or "klipper.bin" on an SD card and then restart the Fly-E3-v2 +# with that SD card. + +# See docs/Config_Reference.md for a description of parameters. + +[mcu] +serial: /dev/serial/by-id/usb-Klipper_stm32f407xx_27004A001851323333353137-if00 + +[stepper_x] +step_pin: PE5 +dir_pin: PC0 +enable_pin: !PC1 +microsteps: 16 +rotation_distance: 30 +full_steps_per_rotation: 200 +endstop_pin: PE7 #X-STOP +position_endstop: 0 +position_max: 200 +homing_speed: 50 +second_homing_speed: 10 +homing_retract_dist: 5.0 +homing_positive_dir: false +step_pulse_duration: 0.000004 + +[stepper_y] +step_pin: PE4 +dir_pin: !PC13 +enable_pin: !PC14 +microsteps: 16 +rotation_distance: 30 +full_steps_per_rotation: 200 +endstop_pin: PE8 #Y-STOP +position_endstop: 0 +position_max: 200 +homing_speed: 50 +second_homing_speed: 10 +homing_retract_dist: 5.0 +homing_positive_dir: false +step_pulse_duration: 0.000004 + +[stepper_z] +step_pin: PE1 +dir_pin: !PB7 +enable_pin: !PE3 +microsteps: 16 +rotation_distance: 30 +full_steps_per_rotation: 200 +endstop_pin: PE9 #Z-STOP +position_min: 0 +position_endstop: 0 +position_max: 200 +homing_speed: 5 +second_homing_speed: 3 +homing_retract_dist: 5.0 +homing_positive_dir: false +step_pulse_duration: 0.000004 + +[extruder] +step_pin: PE2 +dir_pin: PD5 +enable_pin: !PD6 +microsteps: 16 +rotation_distance: 33.500 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PC6 #E0 + +######################################## +# Extruder 100K thermistor configuration +######################################## +sensor_type: ATC Semitec 104GT-2 +sensor_pin: PC4 #T0 TEMP +control: pid +pid_Kp: 22.2 +pid_Ki: 1.08 +pid_Kd: 114 +min_temp: 0 +max_temp: 275 +######################################## +# Extruder MAX31865 PT100 2 wire config +######################################## +# sensor_type: MAX31865 +# sensor_pin: PD15 #PT-100 +# spi_speed: 4000000 +# spi_software_sclk_pin: PD12 +# spi_software_mosi_pin: PD11 +# spi_software_miso_pin: PD13 +# rtd_nominal_r: 100 +# rtd_reference_r: 430 +# rtd_num_of_wires: 2 +# rtd_use_50Hz_filter: True +min_temp: 0 +max_temp: 300 + +#[extruder1] +#step_pin: PE0 +#dir_pin: PD1 +#enable_pin: !PD3 +#microsteps: 16 +#heater_pin: PC7 #E1 +#sensor_pin: PC5 #T1 TEMP + +######################################## +# TMC2209 configuration +######################################## + +[tmc2209 stepper_x] +uart_pin: PC15 +interpolate: False +run_current: 0.3 +sense_resistor: 0.110 +stealthchop_threshold: 999999 + +[tmc2209 stepper_y] +uart_pin: PB6 +interpolate: False +run_current: 0.3 +sense_resistor: 0.110 +stealthchop_threshold: 999999 + +[tmc2209 stepper_z] +uart_pin: PD7 +interpolate: False +run_current: 0.4 +sense_resistor: 0.110 +stealthchop_threshold: 999999 + +[tmc2209 extruder] +uart_pin: PD4 +interpolate: False +run_current: 0.27 +sense_resistor: 0.075 +stealthchop_threshold: 999999 + +#[tmc2209 extruder1] +#uart_pin: PD0 +#interpolate: False +#run_current: 0.27 +#sense_resistor: 0.075 +#stealthchop_threshold: 999999 + + +####################################### +# Heated Bed +####################################### + +[heater_bed] +heater_pin: PB0 #BED +sensor_type: Generic 3950 +sensor_pin: PB1 #B-TEMP +max_power: 1.0 +min_temp: 0 +max_temp: 120 +control: pid +pid_kp: 58.437 +pid_ki: 2.347 +pid_kd: 363.769 + +####################################### +# LIGHTING +####################################### + +#[led Toolhead] +#white_pin: PA2 #FAN2 +#cycle_time: 0.010 +#initial_white: 0 + +####################################### +# COOLING +####################################### + +[heater_fan hotend_fan] +pin: PA1 #FAN1 +max_power: 1.0 +kick_start_time: 0.5 +heater: extruder +heater_temp: 50 +fan_speed: 1.0 + +[controller_fan controller_fan] +pin: PA0 #FAN0 +max_power: 1.0 +kick_start_time: 0.5 +heater: extruder +stepper: stepper_x, stepper_y, stepper_z +fan_speed: 1.0 +idle_timeout: 60 + +[fan] +pin: PA3 #FAN3 +max_power: 1.0 +off_below: 0.2 + +[temperature_sensor Mellow_Fly_E3_V2] +sensor_type: temperature_mcu +min_temp: 5 +max_temp: 80 + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 3000 +max_z_velocity: 50 +max_z_accel: 100 + +######################################## +# EXP1 / EXP2 (display) pins +######################################## +[board_pins] +aliases: + EXP1_1=PD10, EXP1_3=PA8, EXP1_5=PE15, EXP1_7=PA14, EXP1_9=, + EXP1_2=PA9, EXP1_4=PA10, EXP1_6=PE14, EXP1_8=PA13, EXP1_10=<5V>, + # EXP2 header + EXP2_1=PA6, EXP2_3=PB11, EXP2_5=PB10, EXP2_7=PE13, EXP2_9=, + EXP2_2=PA5, EXP2_4=PA4, EXP2_6=PA7, EXP2_8=, EXP2_10=, + +# See the sample-lcd.cfg file for definitions of common LCD displays. + +####################################### +# BL-Touch +####################################### + +#[bltouch] +#sensor_pin: PC2 +#control_pin: PE6 +#z_offset: 0 diff --git a/config/sample-duet3-1lc.cfg b/config/sample-duet3-1lc.cfg index 298c6fafb98d..ef7e404280e4 100644 --- a/config/sample-duet3-1lc.cfg +++ b/config/sample-duet3-1lc.cfg @@ -77,5 +77,14 @@ heater_temp: 50.0 pin: toolboard:PA9 z_offset: 20 +[samd_sercom sercom_i2c] +sercom: sercom1 +tx_pin: toolboard:PA16 +clk_pin: toolboard:PA17 + +[lis3dh] +i2c_mcu: toolboard +i2c_bus: sercom1 + [mcu toolboard] canbus_uuid: 4b194673554e diff --git a/docs/API_Server.md b/docs/API_Server.md index cc0922e3ca81..3837f737ed99 100644 --- a/docs/API_Server.md +++ b/docs/API_Server.md @@ -364,6 +364,38 @@ and might later produce asynchronous messages such as: The "header" field in the initial query response is used to describe the fields found in later "data" responses. +### hx71x/dump_hx71x + +This endpoint is used to subscribe to raw HX711 and HX717 ADC data. +Obtaining these low-level ADC updates may be useful for diagnostic +and debugging purposes. Using this endpoint may increase Klipper's +system load. + +A request may look like: +`{"id": 123, "method":"hx71x/dump_hx71x", +"params": {"sensor": "load_cell", "response_template": {}}}` +and might return: +`{"id": 123,"result":{"header":["time","counts","value"]}}` +and might later produce asynchronous messages such as: +`{"params":{"data":[[3292.432935, 562534, 0.067059278], +[3292.4394937, 5625322, 0.670590639]]}}` + +### ads1220/dump_ads1220 + +This endpoint is used to subscribe to raw ADS1220 ADC data. +Obtaining these low-level ADC updates may be useful for diagnostic +and debugging purposes. Using this endpoint may increase Klipper's +system load. + +A request may look like: +`{"id": 123, "method":"ads1220/dump_ads1220", +"params": {"sensor": "load_cell", "response_template": {}}}` +and might return: +`{"id": 123,"result":{"header":["time","counts","value"]}}` +and might later produce asynchronous messages such as: +`{"params":{"data":[[3292.432935, 562534, 0.067059278], +[3292.4394937, 5625322, 0.670590639]]}}` + ### pause_resume/cancel This endpoint is similar to running the "PRINT_CANCEL" G-Code command. diff --git a/docs/Axis_Twist_Compensation.md b/docs/Axis_Twist_Compensation.md index 0017a2279de7..b0c80b1864b8 100644 --- a/docs/Axis_Twist_Compensation.md +++ b/docs/Axis_Twist_Compensation.md @@ -24,19 +24,51 @@ try to probe the bed without attaching the probe if you use it. > **Tip:** Make sure the [probe X and Y offsets](Config_Reference.md#probe) are > correctly set as they greatly influence calibration. -1. After setting up the [axis_twist_compensation] module, -perform `AXIS_TWIST_COMPENSATION_CALIBRATE` -* The calibration wizard will prompt you to measure the probe Z offset at a few -points along the bed -* The calibration defaults to 3 points but you can use the option -`SAMPLE_COUNT=` to use a different number. -2. [Adjust your Z offset](Probe_Calibrate.md#calibrating-probe-z-offset) -3. Perform automatic/probe-based bed tramming operations, such as -[Screws Tilt Adjust](G-Codes.md#screws_tilt_adjust), -[Z Tilt Adjust](G-Codes.md#z_tilt_adjust) etc -4. Home all axis, then perform a [Bed Mesh](Bed_Mesh.md) if required -5. Perform a test print, followed by any -[fine-tuning](Axis_Twist_Compensation.md#fine-tuning) as desired +### Basic Usage: X-Axis Calibration +1. After setting up the ```[axis_twist_compensation]``` module, run: +``` +AXIS_TWIST_COMPENSATION_CALIBRATE +``` +This command will calibrate the X-axis by default. + - The calibration wizard will prompt you to measure the probe Z offset at + several points along the bed. + - By default, the calibration uses 3 points, but you can specify a different + number with the option: +`` +SAMPLE_COUNT= +`` + +2. **Adjust Your Z Offset:** +After completing the calibration, be sure to [adjust your Z offset] +(Probe_Calibrate.md#calibrating-probe-z-offset). + +3. **Perform Bed Leveling Operations:** +Use probe-based operations as needed, such as: + - [Screws Tilt Adjust](G-Codes.md#screws_tilt_adjust) + - [Z Tilt Adjust](G-Codes.md#z_tilt_adjust) + +4. **Finalize the Setup:** + - Home all axes, and perform a [Bed Mesh](Bed_Mesh.md) if necessary. + - Run a test print, followed by any + [fine-tuning](Axis_Twist_Compensation.md#fine-tuning) + if needed. + +### For Y-Axis Calibration +The calibration process for the Y-axis is similar to the X-axis. To calibrate +the Y-axis, use: +``` +AXIS_TWIST_COMPENSATION_CALIBRATE AXIS=Y +``` +This will guide you through the same measuring process as for the X-axis. + +### Automatic Calibration for Both Axes +To perform automatic calibration for both the X and Y axes without manual +intervention, use: +``` +AXIS_TWIST_COMPENSATION_CALIBRATE AUTO=True +``` +In this mode, the calibration process will run for both axes automatically. + > **Tip:** Bed temperature and nozzle temperature and size do not seem to have > an influence to the calibration process. diff --git a/docs/Bed_Mesh.md b/docs/Bed_Mesh.md index 62f1dee84ed7..c8d744fecfe8 100644 --- a/docs/Bed_Mesh.md +++ b/docs/Bed_Mesh.md @@ -269,7 +269,7 @@ printers use an endstop for homing the Z axis and a probe for calibrating the mesh. In this configuration it is possible offset the mesh so that the (X, Y) `reference position` applies zero adjustment. The `reference postion` should be the location on the bed where a -[Z_ENDSTOP_CALIBRATE](./Manual_Level#calibrating-a-z-endstop) +[Z_ENDSTOP_CALIBRATE](./Manual_Level.md#calibrating-a-z-endstop) paper test is performed. The bed_mesh module provides the `zero_reference_position` option for specifying this coordinate: diff --git a/docs/Benchmarks.md b/docs/Benchmarks.md index 1256c580119a..47ee77d43259 100644 --- a/docs/Benchmarks.md +++ b/docs/Benchmarks.md @@ -354,6 +354,26 @@ micro-controller. | 1 stepper (200Mhz) | 39 | | 3 stepper (200Mhz) | 181 | +### SAME70 step rate benchmark + +The following configuration sequence is used on the SAME70: +``` +allocate_oids count=3 +config_stepper oid=0 step_pin=PC18 dir_pin=PB5 invert_step=-1 step_pulse_ticks=0 +config_stepper oid=1 step_pin=PC16 dir_pin=PD10 invert_step=-1 step_pulse_ticks=0 +config_stepper oid=2 step_pin=PC28 dir_pin=PA4 invert_step=-1 step_pulse_ticks=0 +finalize_config crc=0 +``` + +The test was last run on commit `34e9ea55` with gcc version +`arm-none-eabi-gcc (NixOS 10.3-2021.10) 10.3.1` on a SAME70Q20B +micro-controller. + +| same70 | ticks | +| -------------------- | ----- | +| 1 stepper | 45 | +| 3 stepper | 190 | + ### AR100 step rate benchmark ### The following configuration sequence is used on AR100 CPU (Allwinner A64): @@ -366,7 +386,7 @@ finalize_config crc=0 ``` -The test was last run on commit `08d037c6` with gcc version +The test was last run on commit `b7978d37` with gcc version `or1k-linux-musl-gcc (GCC) 9.2.0` on an Allwinner A64-H micro-controller. @@ -375,9 +395,9 @@ micro-controller. | 1 stepper | 85 | | 3 stepper | 359 | -### RP2040 step rate benchmark +### RPxxxx step rate benchmark -The following configuration sequence is used on the RP2040: +The following configuration sequence is used on the RP2040 and RP2350: ``` allocate_oids count=3 @@ -387,15 +407,26 @@ config_stepper oid=2 step_pin=gpio27 dir_pin=gpio5 invert_step=-1 step_pulse_tic finalize_config crc=0 ``` -The test was last run on commit `59314d99` with gcc version -`arm-none-eabi-gcc (Fedora 10.2.0-4.fc34) 10.2.0` on a Raspberry Pi -Pico board. +The test was last run on commit `f6718291` with gcc version +`arm-none-eabi-gcc (Fedora 14.1.0-1.fc40) 14.1.0` on Raspberry Pi +Pico and Pico 2 boards. -| rp2040 | ticks | +| rp2040 (*) | ticks | | -------------------- | ----- | | 1 stepper | 5 | | 3 stepper | 22 | +| rp2350 | ticks | +| -------------------- | ----- | +| 1 stepper | 36 | +| 3 stepper | 169 | + +(*) Note that the reported rp2040 ticks are relative to a 12Mhz +scheduling timer and do not correspond to its 125Mhz internal ARM +processing rate. It is expected that 5 scheduling ticks corresponds to +~47 ARM core cycles and 22 scheduling ticks corresponds to ~224 ARM +core cycles. + ### Linux MCU step rate benchmark The following configuration sequence is used on a Raspberry Pi: @@ -456,7 +487,8 @@ hub. | sam4s8c (USB) | 650K | 8d4a5c16 | arm-none-eabi-gcc (Fedora 7.4.0-1.fc30) 7.4.0 | | samd51 (USB) | 864K | 01d2183f | arm-none-eabi-gcc (Fedora 7.4.0-1.fc30) 7.4.0 | | stm32f446 (USB) | 870K | 01d2183f | arm-none-eabi-gcc (Fedora 7.4.0-1.fc30) 7.4.0 | -| rp2040 (USB) | 873K | c5667193 | arm-none-eabi-gcc (Fedora 10.2.0-4.fc34) 10.2.0 | +| rp2040 (USB) | 885K | f6718291 | arm-none-eabi-gcc (Fedora 14.1.0-1.fc40) 14.1.0 | +| rp2350 (USB) | 885K | f6718291 | arm-none-eabi-gcc (Fedora 14.1.0-1.fc40) 14.1.0 | ## Host Benchmarks diff --git a/docs/Config_Changes.md b/docs/Config_Changes.md index b5212ce19930..5535dc85a195 100644 --- a/docs/Config_Changes.md +++ b/docs/Config_Changes.md @@ -8,6 +8,23 @@ All dates in this document are approximate. ## Changes +20241112: Option `CHIPS=` in `TEST_RESONANCES` and +`SHAPER_CALIBRATE` requires specifying the full name(s) of the accel +chip(s). For example, `adxl345 rpi` instead of short name - `rpi`. + +20240912: `SET_PIN`, `SET_SERVO`, `SET_FAN_SPEED`, `M106`, and `M107` +commands are now collated. Previously, if many updates to the same +object were issued faster than the minimum scheduling time (typically +100ms) then actual updates could be queued far into the future. Now if +many updates are issued in rapid succession then it is possible that +only the latest request will be applied. If the previous behavior is +requried then consider adding explicit `G4` delay commands between +updates. + +20240912: Support for `maximum_mcu_duration` and `static_value` +parameters in `[output_pin]` config sections have been removed. These +options have been deprecated since 20240123. + 20240415: The `on_error_gcode` parameter in the `[virtual_sdcard]` config section now has a default. If this parameter is not specified it now defaults to `TURN_OFF_HEATERS`. If the previous behavior is diff --git a/docs/Config_Reference.md b/docs/Config_Reference.md index b192e7362c76..d73a3a643860 100644 --- a/docs/Config_Reference.md +++ b/docs/Config_Reference.md @@ -1675,8 +1675,9 @@ Support for LIS2DW accelerometers. ``` [lis2dw] -cs_pin: -# The SPI enable pin for the sensor. This parameter must be provided. +#cs_pin: +# The SPI enable pin for the sensor. This parameter must be provided +# if using SPI. #spi_speed: 5000000 # The SPI speed (in hz) to use when communicating with the chip. # The default is 5000000. @@ -1686,6 +1687,46 @@ cs_pin: #spi_software_miso_pin: # See the "common SPI settings" section for a description of the # above parameters. +#i2c_address: +# Default is 25 (0x19). If SA0 is high, it would be 24 (0x18) instead. +#i2c_mcu: +#i2c_bus: +#i2c_software_scl_pin: +#i2c_software_sda_pin: +#i2c_speed: 400000 +# See the "common I2C settings" section for a description of the +# above parameters. The default "i2c_speed" is 400000. +#axes_map: x, y, z +# See the "adxl345" section for information on this parameter. +``` + +### [lis3dh] + +Support for LIS3DH accelerometers. + +``` +[lis3dh] +#cs_pin: +# The SPI enable pin for the sensor. This parameter must be provided +# if using SPI. +#spi_speed: 5000000 +# The SPI speed (in hz) to use when communicating with the chip. +# The default is 5000000. +#spi_bus: +#spi_software_sclk_pin: +#spi_software_mosi_pin: +#spi_software_miso_pin: +# See the "common SPI settings" section for a description of the +# above parameters. +#i2c_address: +# Default is 25 (0x19). If SA0 is high, it would be 24 (0x18) instead. +#i2c_mcu: +#i2c_bus: +#i2c_software_scl_pin: +#i2c_software_sda_pin: +#i2c_speed: 400000 +# See the "common I2C settings" section for a description of the +# above parameters. The default "i2c_speed" is 400000. #axes_map: x, y, z # See the "adxl345" section for information on this parameter. ``` @@ -2042,9 +2083,9 @@ sensor_type: ldc1612 ### [axis_twist_compensation] -A tool to compensate for inaccurate probe readings due to twist in X gantry. See -the [Axis Twist Compensation Guide](Axis_Twist_Compensation.md) for more -detailed information regarding symptoms, configuration and setup. +A tool to compensate for inaccurate probe readings due to twist in X or Y +gantry. See the [Axis Twist Compensation Guide](Axis_Twist_Compensation.md) +for more detailed information regarding symptoms, configuration and setup. ``` [axis_twist_compensation] @@ -2057,16 +2098,33 @@ detailed information regarding symptoms, configuration and setup. calibrate_start_x: 20 # Defines the minimum X coordinate of the calibration # This should be the X coordinate that positions the nozzle at the starting -# calibration position. This parameter must be provided. +# calibration position. calibrate_end_x: 200 # Defines the maximum X coordinate of the calibration # This should be the X coordinate that positions the nozzle at the ending -# calibration position. This parameter must be provided. +# calibration position. calibrate_y: 112.5 # Defines the Y coordinate of the calibration # This should be the Y coordinate that positions the nozzle during the -# calibration process. This parameter must be provided and is recommended to +# calibration process. This parameter is recommended to # be near the center of the bed + +# For Y-axis twist compensation, specify the following parameters: +calibrate_start_y: ... +# Defines the minimum Y coordinate of the calibration +# This should be the Y coordinate that positions the nozzle at the starting +# calibration position for the Y axis. This parameter must be provided if +# compensating for Y axis twist. +calibrate_end_y: ... +# Defines the maximum Y coordinate of the calibration +# This should be the Y coordinate that positions the nozzle at the ending +# calibration position for the Y axis. This parameter must be provided if +# compensating for Y axis twist. +calibrate_x: ... +# Defines the X coordinate of the calibration for Y axis twist compensation +# This should be the X coordinate that positions the nozzle during the +# calibration process for Y axis twist compensation. This parameter must be +# provided and is recommended to be near the center of the bed. ``` ## Additional stepper motors and extruders @@ -2401,6 +2459,69 @@ temperature sensors that are reported via the M105 command. # parameter. ``` +### [temperature_probe] + +Reports probe coil temperature. Includes optional thermal drift +calibration for eddy current based probes. A `[temperature_probe]` +section may be linked to a `[probe_eddy_current]` by using the same +postfix for both sections. + +``` +[temperature_probe my_probe] +#sensor_type: +#sensor_pin: +#min_temp: +#max_temp: +# Temperature sensor configuration. +# See the "extruder" section for the definition of the above +# parameters. +#smooth_time: +# A time value (in seconds) over which temperature measurements will +# be smoothed to reduce the impact of measurement noise. The default +# is 2.0 seconds. +#gcode_id: +# See the "heater_generic" section for the definition of this +# parameter. +#speed: +# The travel speed [mm/s] for xy moves during calibration. Default +# is the speed defined by the probe. +#horizontal_move_z: +# The z distance [mm] from the bed at which xy moves will occur +# during calibration. Default is 2mm. +#resting_z: +# The z distance [mm] from the bed at which the tool will rest +# to heat the probe coil during calibration. Default is .4mm +#calibration_position: +# The X, Y, Z position where the tool should be moved when +# probe drift calibration initializes. This is the location +# where the first manual probe will occur. If omitted, the +# default behavior is not to move the tool prior to the first +# manual probe. +#calibration_bed_temp: +# The maximum safe bed temperature (in C) used to heat the probe +# during probe drift calibration. When set, the calibration +# procedure will turn on the bed after the first sample is +# taken. When the calibration procedure is complete the bed +# temperature will be set to zero. When omitted the default +# behavior is not to set the bed temperature. +#calibration_extruder_temp: +# The extruder temperature (in C) set probe during drift calibration. +# When this option is supplied the procedure will wait for until the +# specified temperature is reached before requesting the first manual +# probe. When the calibration procedure is complete the extruder +# temperature will be set to 0. When omitted the default behavior is +# not to set the extruder temperature. +#extruder_heating_z: 50. +# The Z location where extruder heating will occur if the +# "calibration_extruder_temp" option is set. Its recommended to heat +# the extruder some distance from the bed to minimize its impact on +# the probe coil temperature. The default is 50. +#max_validation_temp: 60. +# The maximum temperature used to validate the calibration. It is +# recommended to set this to a value between 100 and 120 for enclosed +# printers. The default is 60. +``` + ## Temperature sensors Klipper includes definitions for many types of temperature sensors. @@ -4586,6 +4707,112 @@ adc2: # above parameters. ``` +## Load Cells + +### [load_cell] +Load Cell. Uses an ADC sensor attached to a load cell to create a digital +scale. + +``` +[load_cell] +sensor_type: +# This must be one of the supported sensor types, see below. +``` + +#### HX711 +This is a 24 bit low sample rate chip using "bit-bang" communications. It is +suitable for filament scales. +``` +[load_cell] +sensor_type: hx711 +sclk_pin: +# The pin connected to the HX711 clock line. This parameter must be provided. +dout_pin: +# The pin connected to the HX711 data output line. This parameter must be +# provided. +#gain: A-128 +# Valid values for gain are: A-128, A-64, B-32. The default is A-128. +# 'A' denotes the input channel and the number denotes the gain. Only the 3 +# listed combinations are supported by the chip. Note that changing the gain +# setting also selects the channel being read. +#sample_rate: 80 +# Valid values for sample_rate are 80 or 10. The default value is 80. +# This must match the wiring of the chip. The sample rate cannot be changed +# in software. +``` + +#### HX717 +This is the 4x higher sample rate version of the HX711, suitable for probing. +``` +[load_cell] +sensor_type: hx717 +sclk_pin: +# The pin connected to the HX717 clock line. This parameter must be provided. +dout_pin: +# The pin connected to the HX717 data output line. This parameter must be +# provided. +#gain: A-128 +# Valid values for gain are A-128, B-64, A-64, B-8. +# 'A' denotes the input channel and the number denotes the gain setting. +# Only the 4 listed combinations are supported by the chip. Note that +# changing the gain setting also selects the channel being read. +#sample_rate: 320 +# Valid values for sample_rate are: 10, 20, 80, 320. The default is 320. +# This must match the wiring of the chip. The sample rate cannot be changed +# in software. +``` + +#### ADS1220 +The ADS1220 is a 24 bit ADC supporting up to a 2Khz sample rate configurable in +software. +``` +[load_cell] +sensor_type: ads1220 +cs_pin: +# The pin connected to the ADS1220 chip select line. This parameter must +# be provided. +#spi_speed: 512000 +# This chip supports 2 speeds: 256000 or 512000. The faster speed is only +# enabled when one of the Turbo sample rates is used. The correct spi_speed +# is selected based on the sample rate. +#spi_bus: +#spi_software_sclk_pin: +#spi_software_mosi_pin: +#spi_software_miso_pin: +# See the "common SPI settings" section for a description of the +# above parameters. +data_ready_pin: +# Pin connected to the ADS1220 data ready line. This parameter must be +# provided. +#gain: 128 +# Valid gain values are 128, 64, 32, 16, 8, 4, 2, 1 +# The default is 128 +#pga_bypass: False +# Disable the internal Programmable Gain Amplifier. If +# True the PGA will be disabled for gains 1, 2, and 4. The PGA is always +# enabled for gain settings 8 to 128, regardless of the pga_bypass setting. +# If AVSS is used as an input pga_bypass is forced to True. +# The default is False. +#sample_rate: 660 +# This chip supports two ranges of sample rates, Normal and Turbo. In turbo +# mode the chip's internal clock runs twice as fast and the SPI communication +# speed is also doubled. +# Normal sample rates: 20, 45, 90, 175, 330, 600, 1000 +# Turbo sample rates: 40, 90, 180, 350, 660, 1200, 2000 +# The default is 660 +#input_mux: +# Input multiplexer configuration, select a pair of pins to use. The first pin +# is the positive, AINP, and the second pin is the negative, AINN. Valid +# values are: 'AIN0_AIN1', 'AIN0_AIN2', 'AIN0_AIN3', 'AIN1_AIN2', 'AIN1_AIN3', +# 'AIN2_AIN3', 'AIN1_AIN0', 'AIN3_AIN2', 'AIN0_AVSS', 'AIN1_AVSS', 'AIN2_AVSS' +# and 'AIN3_AVSS'. If AVSS is used the PGA is bypassed and the pga_bypass +# setting will be forced to True. +# The default is AIN0_AIN1. +#vref: +# The selected voltage reference. Valid values are: 'internal', 'REF0', 'REF1' +# and 'analog_supply'. Default is 'internal'. +``` + ## Board specific hardware support ### [sx1509] @@ -4849,8 +5076,9 @@ Most Klipper micro-controller implementations only support an micro-controller supports a 400000 speed (*fast mode*, 400kbit/s), but it must be [set in the operating system](RPi_microcontroller.md#optional-enabling-i2c) and the `i2c_speed` parameter is otherwise ignored. The Klipper -"RP2040" micro-controller and ATmega AVR family support a rate of 400000 -via the `i2c_speed` parameter. All other Klipper micro-controllers use a +"RP2040" micro-controller and ATmega AVR family and some STM32 +(F0, G0, G4, L4, F7, H7) support a rate of 400000 via the `i2c_speed` parameter. +All other Klipper micro-controllers use a 100000 rate and ignore the `i2c_speed` parameter. ``` diff --git a/docs/Eddy_Probe.md b/docs/Eddy_Probe.md index 221c855b6d66..3c36a613c181 100644 --- a/docs/Eddy_Probe.md +++ b/docs/Eddy_Probe.md @@ -54,3 +54,93 @@ result in changes in reported Z height. Changes in either the bed surface temperature or sensor hardware temperature can skew the results. It is important that calibration and probing is only done when the printer is at a stable temperature. + +## Thermal Drift Calibration + +As with all inductive probes, eddy current probes are subject to +significant thermal drift. If the eddy probe has a temperature +sensor on the coil it is possible to configure a `[temperature_probe]` +to report coil temperature and enable software drift compensation. To +link a temperature probe to an eddy current probe the +`[temperature_probe]` section must share a name with the +`[probe_eddy_current]` section. For example: + +``` +[probe_eddy_current my_probe] +# eddy probe configuration... + +[temperature_probe my_probe] +# temperature probe configuration... +``` + +See the [configuration reference](Config_Reference.md#temperature_probe) +for further details on how to configure a `temperature_probe`. It is +advised to configure the `calibration_position`, +`calibration_extruder_temp`, `extruder_heating_z`, and +`calibration_bed_temp` options, as doing so will automate some of the +steps outlined below. If the printer to be calibrated is enclosed, it +is strongly recommended to set the `max_validation_temp` option to a value +between 100 and 120. + +Eddy probe manufacturers may offer a stock drift calibration that can be +manually added to `drift_calibration` option of the `[probe_eddy_current]` +section. If they do not, or if the stock calibration does not perform well on +your system, the `temperature_probe` module offers a manual calibration +procedure via the `TEMPERATURE_PROBE_CALIBRATE` gcode command. + +Prior to performing calibration the user should have an idea of what the +maximum attainable temperature probe coil temperature is. This temperature +should be used to set the `TARGET` parameter of the +`TEMPERATURE_PROBE_CALIBRATE` command. The goal is to calibrate across the +widest temperature range possible, thus its desirable to start with the printer +cold and finish with the coil at the maximum temperature it can reach. + +Once a `[temperature_probe]` is configured, the following steps may be taken +to perform thermal drift calibration: + +- The probe must be calibrated using `PROBE_EDDY_CURRENT_CALIBRATE` + when a `[temperature_probe]` is configured and linked. This captures + the temperature during calibration which is necessary to perform + thermal drift compensation. +- Make sure the nozzle is free of debris and filament. +- The bed, nozzle, and probe coil should be cold prior to calibration. +- The following steps are required if the `calibration_position`, + `calibration_extruder_temp`, and `extruder_heating_z` options in + `[temperature_probe]` are **NOT** configured: + - Move the tool to the center of the bed. Z should be 30mm+ above the bed. + - Heat the extruder to a temperature above the maximum safe bed temperature. + 150-170C should be sufficient for most configurations. The purpose of + heating the extruder is to avoid nozzle expansion during calibration. + - When the extruder temperature has settled, move the Z axis down to about 1mm + above the bed. +- Start drift calibration. If the probe's name is `my_probe` and the maximum + probe temperature we can achieve is 80C, the appropriate gcode command is + `TEMPERATURE_PROBE_CALIBRATE PROBE=my_probe TARGET=80`. If configured, the + tool will move to the X,Y coordinate specified by the `calibration_position` + and the Z value specified by `extruder_heating_z`. After heating the extruder + to the specified temperature the tool will move to the Z value specified + by the`calibration_position`. +- The procedure will request a manual probe. Perform the manual probe with + the paper test and `ACCEPT`. The calibration procedure will take the first + set of samples with the probe then park the probe in the heating position. +- If the `calibration_bed_temp` is **NOT** configured turn on the bed heat + to the maximum safe temperature. Otherwise this step will be performed + automatically. +- By default the calibration procedure will request a manual probe every + 2C between samples until the `TARGET` is reached. The temperature delta + between samples can be customized by setting the `STEP` parameter in + `TEMPERATURE_PROBE_CALIBRATE`. Care should be taken when setting a custom + `STEP` value, a value too high may request too few samples resulting in + a poor calibration. +- The following additional gcode commands are available during drift + calibration: + - `TEMPERATURE_PROBE_NEXT` may be used to force a new sample before the step + delta has been reached. + - `TEMPERATURE_PROBE_COMPLETE` may be used to complete calibration before the + `TARGET` has been reached. + - `ABORT` may be used to end calibration and discard results. +- When calibration is finished use `SAVE_CONFIG` to store the drift + calibration. + +As one may conclude, the calibration process outlined above is more challenging +and time consuming than most other procedures. It may require practice and several attempts to achieve an optimal calibration. diff --git a/docs/Features.md b/docs/Features.md index 9c61ccf72845..229cbef8e6cd 100644 --- a/docs/Features.md +++ b/docs/Features.md @@ -190,6 +190,8 @@ represent total number of steps per second on the micro-controller. | AR100 | 3529K | 2507K | | STM32F407 | 3652K | 2459K | | STM32F446 | 3913K | 2634K | +| RP2350 | 4167K | 2663K | +| SAME70 | 6667K | 4737K | | STM32H743 | 9091K | 6061K | If unsure of the micro-controller on a particular board, find the diff --git a/docs/G-Codes.md b/docs/G-Codes.md index e55fba35db80..7c90417cabbb 100644 --- a/docs/G-Codes.md +++ b/docs/G-Codes.md @@ -146,9 +146,19 @@ The following commands are available when the section](Config_Reference.md#axis_twist_compensation) is enabled. #### AXIS_TWIST_COMPENSATION_CALIBRATE -`AXIS_TWIST_COMPENSATION_CALIBRATE [SAMPLE_COUNT=]`: Initiates the X -twist calibration wizard. `SAMPLE_COUNT` specifies the number of points along -the X axis to calibrate at and defaults to 3. +`AXIS_TWIST_COMPENSATION_CALIBRATE [AXIS=] [AUTO=] +[SAMPLE_COUNT=]` + +Calibrates axis twist compensation by specifying the target axis or +enabling automatic calibration. + +- **AXIS:** Define the axis (`X` or `Y`) for which the twist compensation +will be calibrated. If not specified, the axis defaults to `'X'`. + +- **AUTO:** Enables automatic calibration mode. When `AUTO=True`, the +calibration will run for both the X and Y axes. In this mode, `AXIS` +cannot be specified. If both `AXIS` and `AUTO` are provided, an error +will be raised. ### [bed_mesh] @@ -476,6 +486,20 @@ enabled. `SET_FAN_SPEED FAN=config_name SPEED=` This command sets the speed of a fan. "speed" must be between 0.0 and 1.0. +`SET_FAN_SPEED PIN=config_name TEMPLATE= +[=]`: If `TEMPLATE` is specified then it assigns a +[display_template](Config_Reference.md#display_template) to the given +fan. For example, if one defined a `[display_template +my_fan_template]` config section then one could assign +`TEMPLATE=my_fan_template` here. The display_template should produce a +string containing a floating point number with the desired value. The +template will be continuously evaluated and the fan will be +automatically set to the resulting speed. One may set display_template +parameters to use during template evaluation (parameters will be +parsed as Python literals). If TEMPLATE is an empty string then this +command will clear any previous template assigned to the pin (one can +then use `SET_FAN_SPEED` commands to manage the values directly). + ### [filament_switch_sensor] The following command is available when a @@ -857,6 +881,20 @@ output `VALUE`. VALUE should be 0 or 1 for "digital" output pins. For PWM pins, set to a value between 0.0 and 1.0, or between 0.0 and `scale` if a scale is configured in the output_pin config section. +`SET_PIN PIN=config_name TEMPLATE= [=]`: +If `TEMPLATE` is specified then it assigns a +[display_template](Config_Reference.md#display_template) to the given +pin. For example, if one defined a `[display_template +my_pin_template]` config section then one could assign +`TEMPLATE=my_pin_template` here. The display_template should produce a +string containing a floating point number with the desired value. The +template will be continuously evaluated and the pin will be +automatically set to the resulting value. One may set display_template +parameters to use during template evaluation (parameters will be +parsed as Python literals). If TEMPLATE is an empty string then this +command will clear any previous template assigned to the pin (one can +then use `SET_PIN` commands to manage the values directly). + ### [palette2] The following commands are available when the @@ -1056,20 +1094,19 @@ is enabled (also see the all enabled accelerometer chips. #### TEST_RESONANCES -`TEST_RESONANCES AXIS= OUTPUT= +`TEST_RESONANCES AXIS= [OUTPUT=] [NAME=] [FREQ_START=] [FREQ_END=] -[HZ_PER_SEC=] [CHIPS=] -[POINT=x,y,z] [INPUT_SHAPING=[<0:1>]]`: Runs the resonance +[ACCEL_PER_HZ=] [HZ_PER_SEC=] [CHIPS=] +[POINT=x,y,z] [INPUT_SHAPING=<0:1>]`: Runs the resonance test in all configured probe points for the requested "axis" and measures the acceleration using the accelerometer chips configured for the respective axis. "axis" can either be X or Y, or specify an arbitrary direction as `AXIS=dx,dy`, where dx and dy are floating point numbers defining a direction vector (e.g. `AXIS=X`, `AXIS=Y`, or `AXIS=1,-1` to define a diagonal direction). Note that `AXIS=dx,dy` -and `AXIS=-dx,-dy` is equivalent. `adxl345_chip_name` can be one or -more configured adxl345 chip,delimited with comma, for example -`CHIPS="adxl345, adxl345 rpi"`. Note that `adxl345` can be omitted from -named adxl345 chips. If POINT is specified it will override the point(s) +and `AXIS=-dx,-dy` is equivalent. `chip_name` can be one or +more configured accel chips, delimited with comma, for example +`CHIPS="adxl345, adxl345 rpi"`. If POINT is specified it will override the point(s) configured in `[resonance_tester]`. If `INPUT_SHAPING=0` or not set(default), disables input shaping for the resonance testing, because it is not valid to run the resonance testing with the input shaper @@ -1086,8 +1123,9 @@ frequency response is calculated (across all probe points) and written into #### SHAPER_CALIBRATE `SHAPER_CALIBRATE [AXIS=] [NAME=] [FREQ_START=] -[FREQ_END=] [HZ_PER_SEC=] [CHIPS=] -[MAX_SMOOTHING=]`: Similarly to `TEST_RESONANCES`, runs +[FREQ_END=] [ACCEL_PER_HZ=][HZ_PER_SEC=] +[CHIPS=] [MAX_SMOOTHING=] [INPUT_SHAPING=<0:1>]`: +Similarly to `TEST_RESONANCES`, runs the resonance test as configured, and tries to find the optimal parameters for the input shaper for the requested axis (or both X and Y axes if `AXIS` parameter is unset). If `MAX_SMOOTHING` is unset, its @@ -1415,3 +1453,39 @@ command will probe the points specified in the config and then make independent adjustments to each Z stepper to compensate for tilt. See the PROBE command for details on the optional probe parameters. The optional `HORIZONTAL_MOVE_Z` value overrides the `horizontal_move_z` option specified in the config file. + +### [temperature_probe] + +The following commands are available when a +[temperature_probe config section](Config_Reference.md#temperature_probe) +is enabled. + +#### TEMPERATURE_PROBE_CALIBRATE +`TEMPERATURE_PROBE_CALIBRATE [PROBE=] [TARGET=] [STEP=]`: +Initiates probe drift calibration for eddy current based probes. The `TARGET` +is a target temperature for the last sample. When the temperature recorded +during a sample exceeds the `TARGET` calibration will complete. The `STEP` +parameter sets temperature delta (in C) between samples. After a sample has +been taken, this delta is used to schedule a call to `TEMPERATURE_PROBE_NEXT`. +The default `STEP` is 2. + +#### TEMPERATURE_PROBE_NEXT +`TEMPERATURE_PROBE_NEXT`: After calibration has started this command is run to +take the next sample. It is automatically scheduled to run when the delta +specified by `STEP` has been reached, however its also possible to manually run +this command to force a new sample. This command is only available during +calibration. + +#### TEMPERATURE_PROBE_COMPLETE: +`TEMPERATURE_PROBE_COMPLETE`: Can be used to end calibration and save the +current result before the `TARGET` temperature is reached. This command +is only available during calibration. + +#### ABORT +`ABORT`: Aborts the calibration process, discarding the current results. +This command is only available during drift calibration. + +### TEMPERATURE_PROBE_ENABLE +`TEMPERATURE_PROBE_ENABLE ENABLE=[0|1]`: Sets temperature drift +compensation on or off. If ENABLE is set to 0, drift compensation +will be disabled, if set to 1 it is enabled. diff --git a/docs/Installation.md b/docs/Installation.md index 004d963a0796..ca64259aa0bc 100644 --- a/docs/Installation.md +++ b/docs/Installation.md @@ -1,15 +1,20 @@ # Installation -These instructions assume the software will run on a Raspberry Pi -computer in conjunction with OctoPrint. It is recommended that a -Raspberry Pi 2 (or later) be used as the host machine (see the +These instructions assume the software will run on a linux based host +running a Klipper compatible front end. It is recommended that a +SBC(Small Board Computer) such as a Raspberry Pi or Debian based Linux +device be used as the host machine (see the [FAQ](FAQ.md#can-i-run-klipper-on-something-other-than-a-raspberry-pi-3) -for other machines). +for other options). + +For the purposes of these instructions host relates to the Linux device and +mcu relates to the printboard. SBC relates to the term Small Board Computer +such as the Raspberry Pi. ## Obtain a Klipper Configuration File Most Klipper settings are determined by a "printer configuration file" -that will be stored on the Raspberry Pi. An appropriate configuration +printer.cfg, that will be stored on the host. An appropriate configuration file can often be found by looking in the Klipper [config directory](../config/) for a file starting with a "printer-" prefix that corresponds to the target printer. The Klipper @@ -35,38 +40,51 @@ printer configuration file, then start with the closest example [config file](../config/) and use the Klipper [config reference](Config_Reference.md) for further information. -## Prepping an OS image +## Interacting with Klipper -Start by installing [OctoPi](https://github.com/guysoft/OctoPi) on the -Raspberry Pi computer. Use OctoPi v0.17.0 or later - see the -[OctoPi releases](https://github.com/guysoft/OctoPi/releases) for -release information. One should verify that OctoPi boots and that the -OctoPrint web server works. After connecting to the OctoPrint web -page, follow the prompt to upgrade OctoPrint to v1.4.2 or later. +Klipper is a 3d printer firmware, so it needs some way for the user to +interact with it. -After installing OctoPi and upgrading OctoPrint, it will be necessary -to ssh into the target machine to run a handful of system commands. If -using a Linux or MacOS desktop, then the "ssh" software should already -be installed on the desktop. There are free ssh clients available for -other desktops (eg, -[PuTTY](https://www.chiark.greenend.org.uk/~sgtatham/putty/)). Use the -ssh utility to connect to the Raspberry Pi (`ssh pi@octopi` -- password -is "raspberry") and run the following commands: +Currently the best choices are front ends that retrieve information through +the [Moonraker web API](https://moonraker.readthedocs.io/) and there is also +the option to use [Octoprint](https://octoprint.org/) to control Klipper. -``` -git clone https://github.com/Klipper3d/klipper -./klipper/scripts/install-octopi.sh -``` +The choice is up to the user on what to use, but the underlying Klipper is the +same in all cases. We encourage users to research the options available and +make an informed decision. + +## Obtaining an OS image for SBC's + +There are many ways to obtain an OS image for Klipper for SBC use, most depend on +what front end you wish to use. Some manafactures of these SBC boards also provide +their own Klipper-centric images. + +The two main Moonraker based front ends are [Fluidd](https://docs.fluidd.xyz/) +and [Mainsail](https://docs.mainsail.xyz/), the latter of which has a premade install +image ["MainsailOS"](http://docs.mainsailOS.xyz), this has the option for Raspberry Pi +and some OrangePi varianta. -The above will download Klipper, install some system dependencies, -setup Klipper to run at system startup, and start the Klipper host -software. It will require an internet connection and it may take a few -minutes to complete. +Fluidd can be installed via KIAUH(Klipper Install And Update Helper), which +is explained below and is a 3rd party installer for all things Klipper. + +OctoPrint can be installed via the popular OctoPi image or via KIAUH, this +process is explained in [OctoPrint.md](OctoPrint.md) + +## Installing via KIAUH + +Normally you would start with a base image for your SBC, RPiOS Lite for example, +or in the case of a x86 Linux device, Ubuntu Server. Please note that Desktop +variants are not recommended due to certain helper programs that can stop some +Klipper functions working and even mask access to some print boards. + +KIAUH can be used to install Klipper and its associated programs on a variety +of Linux based systems that run a form of Debian. More information can be found +at https://github.com/dw-0/kiauh ## Building and flashing the micro-controller To compile the micro-controller code, start by running these commands -on the Raspberry Pi: +on your host device: ``` cd ~/klipper/ @@ -108,10 +126,21 @@ It should report something similar to the following: It's common for each printer to have its own unique serial port name. This unique name will be used when flashing the micro-controller. It's possible there may be multiple lines in the above output - if so, -choose the line corresponding to the micro-controller (see the +choose the line corresponding to the micro-controller. If many +items are listed and the choice is ambiguous, unplug the board and +run the command again, the missing item will be your print board(see the [FAQ](FAQ.md#wheres-my-serial-port) for more information). -For common micro-controllers, the code can be flashed with something +For common micro-controllers with STM32 or clone chips, LPC chips and +others it is usual that these need an initial Klipper flash via SD card. + +When flashing with this method, it is important to make sure that the +print board is not connected with USB to the host, due to some boards +being able to feed power back to the board and stopping a flash from +occuring. + +For common micro-controllers using Atmega chips, for example the 2560, +the code can be flashed with something similar to: ``` @@ -123,53 +152,38 @@ sudo service klipper start Be sure to update the FLASH_DEVICE with the printer's unique serial port name. -When flashing for the first time, make sure that OctoPrint is not -connected directly to the printer (from the OctoPrint web page, under -the "Connection" section, click "Disconnect"). - -## Configuring OctoPrint to use Klipper - -The OctoPrint web server needs to be configured to communicate with -the Klipper host software. Using a web browser, login to the OctoPrint -web page and then configure the following items: - -Navigate to the Settings tab (the wrench icon at the top of the -page). Under "Serial Connection" in "Additional serial ports" add -`/tmp/printer`. Then click "Save". - -Enter the Settings tab again and under "Serial Connection" change the -"Serial Port" setting to `/tmp/printer`. +For common micro-controllers using RP2040 chips, the code can be flashed +with something similar to: -In the Settings tab, navigate to the "Behavior" sub-tab and select the -"Cancel any ongoing prints but stay connected to the printer" -option. Click "Save". +``` +sudo service klipper stop +make flash FLASH_DEVICE=first +sudo service klipper start +``` -From the main page, under the "Connection" section (at the top left of -the page) make sure the "Serial Port" is set to `/tmp/printer` and -click "Connect". (If `/tmp/printer` is not an available selection then -try reloading the page.) +It is important to note that RP2040 chips may need to be put into Boot mode +before this operation. -Once connected, navigate to the "Terminal" tab and type "status" -(without the quotes) into the command entry box and click "Send". The -terminal window will likely report there is an error opening the -config file - that means OctoPrint is successfully communicating with -Klipper. Proceed to the next section. ## Configuring Klipper The next step is to copy the [printer configuration file](#obtain-a-klipper-configuration-file) to -the Raspberry Pi. +the host. + +Arguably the easiest way to set the Klipper configuration file is using the +built in editors in Mainsail or Fluidd. These will allow the user to open +the configuration examples and save them to be printer.cfg. -Arguably the easiest way to set the Klipper configuration file is to -use a desktop editor that supports editing files over the "scp" and/or -"sftp" protocols. There are freely available tools that support this -(eg, Notepad++, WinSCP, and Cyberduck). Load the printer config file -in the editor and then save it as a file named `printer.cfg` in the -home directory of the pi user (ie, `/home/pi/printer.cfg`). +Another option is to use a desktop editor that supports editing files +over the "scp" and/or "sftp" protocols. There are freely available tools +that support this (eg, Notepad++, WinSCP, and Cyberduck). +Load the printer config file in the editor and then save it as a file +named "printer.cfg" in the home directory of the pi user +(ie, /home/pi/printer.cfg). Alternatively, one can also copy and edit the file directly on the -Raspberry Pi via ssh. That may look something like the following (be +host via ssh. That may look something like the following (be sure to update the command to use the appropriate printer config filename): @@ -201,7 +215,7 @@ serial: /dev/serial/by-id/usb-1a86_USB2.0-Serial-if00-port0 ``` After creating and editing the file it will be necessary to issue a -"restart" command in the OctoPrint web terminal to load the config. A +"restart" command in the command console to load the config. A "status" command will report the printer is ready if the Klipper config file is successfully read and the micro-controller is successfully found and configured. @@ -211,10 +225,10 @@ Klipper to report a configuration error. If an error occurs, make any necessary corrections to the printer config file and issue "restart" until "status" reports the printer is ready. -Klipper reports error messages via the OctoPrint terminal tab. The -"status" command can be used to re-report error messages. The default -Klipper startup script also places a log in **/tmp/klippy.log** which -provides more detailed information. +Klipper reports error messages via the command console and via pop up in +Fluidd and Mainsail. The "status" command can be used to re-report error +messages. A log is available and usually located in ~/printer_data/logs +this is named klippy.log After Klipper reports that the printer is ready, proceed to the [config check document](Config_checks.md) to perform some basic checks diff --git a/docs/Measuring_Resonances.md b/docs/Measuring_Resonances.md index d5f7f54cc537..81c2eb96d2ce 100644 --- a/docs/Measuring_Resonances.md +++ b/docs/Measuring_Resonances.md @@ -212,12 +212,20 @@ sudo apt install python3-numpy python3-matplotlib libatlas-base-dev libopenblas- Next, in order to install NumPy in the Klipper environment, run the command: ``` -~/klippy-env/bin/pip install -v numpy +~/klippy-env/bin/pip install -v "numpy<1.26" ``` Note that, depending on the performance of the CPU, it may take *a lot* of time, up to 10-20 minutes. Be patient and wait for the completion of the installation. On some occasions, if the board has too little RAM -the installation may fail and you will need to enable swap. +the installation may fail and you will need to enable swap. Also note +the forced version, due to newer versions of NumPY having requirements +that may not be satisfied in some klipper python environments. + +Once installed please check that no errors show from the command: +``` +~/klippy-env/bin/python -c 'import numpy;' +``` +The correct output should simply be a new line. #### Configure ADXL345 With RPi diff --git a/docs/OctoPrint.md b/docs/OctoPrint.md new file mode 100644 index 000000000000..20f9246af547 --- /dev/null +++ b/docs/OctoPrint.md @@ -0,0 +1,79 @@ +# OctoPrint for Klipper + +Klipper has a few options for its front ends, Octoprint was the first +and original front end for Klipper. This document will give +a brief overview of installing with this option. + +## Install with OctoPi + +Start by installing [OctoPi](https://github.com/guysoft/OctoPi) on the +Raspberry Pi computer. Use OctoPi v0.17.0 or later - see the +[OctoPi releases](https://github.com/guysoft/OctoPi/releases) for +release information. + +One should verify that OctoPi boots and that the +OctoPrint web server works. After connecting to the OctoPrint web +page, follow the prompt to upgrade OctoPrint if needed. + +After installing OctoPi and upgrading OctoPrint, it will be necessary +to ssh into the target machine to run a handful of system commands. + +Start by running these commands on your host device: + +__If you do not have git installed, please do so with:__ +``` +sudo apt install git +``` +then proceed: +``` +cd ~ +git clone https://github.com/Klipper3d/klipper +./klipper/scripts/install-octopi.sh +``` + +The above will download Klipper, install the needed system dependencies, +setup Klipper to run at system startup, and start the Klipper host +software. It will require an internet connection and it may take a few +minutes to complete. + +## Installing with KIAUH + +KIAUH can be used to install OctoPrint on a variety of Linux based systems +that run a form of Debian. More information can be found +at https://github.com/dw-0/kiauh + +## Configuring OctoPrint to use Klipper + +The OctoPrint web server needs to be configured to communicate with the Klipper +host software. Using a web browser, login to the OctoPrint web page and then +configure the following items: + +Navigate to the Settings tab (the wrench icon at the top of the page). +Under "Serial Connection" in "Additional serial ports" add: + +``` +~/printer_data/comms/klippy.serial +``` +Then click "Save". + +_In some older setups this address may be `/tmp/printer`_ + + +Enter the Settings tab again and under "Serial Connection" change the "Serial Port" +setting to the one added above. + +In the Settings tab, navigate to the "Behavior" sub-tab and select the +"Cancel any ongoing prints but stay connected to the printer" option. Click "Save". + +From the main page, under the "Connection" section (at the top left of the page) +make sure the "Serial Port" is set to the new additional one added +and click "Connect". (If it is not in the available selection then +try reloading the page.) + +Once connected, navigate to the "Terminal" tab and type "status" (without the quotes) +into the command entry box and click "Send". The terminal window will likely report +there is an error opening the config file - that means OctoPrint is successfully +communicating with Klipper. + +Please proceed to [Installation.md](Installation.md) and the +_Building and flashing the micro-controller_ section diff --git a/docs/Overview.md b/docs/Overview.md index 2b9253c26e67..1ab948910b49 100644 --- a/docs/Overview.md +++ b/docs/Overview.md @@ -17,6 +17,7 @@ communication with the Klipper developers. ## Installation and Configuration - [Installation](Installation.md): Guide to installing Klipper. + - [Octoprint](OctoPrint.md): Guide to installing Octoprint with Klipper. - [Config Reference](Config_Reference.md): Description of config parameters. - [Rotation Distance](Rotation_Distance.md): Calculating the diff --git a/docs/Sponsors.md b/docs/Sponsors.md index a226bb57bb5c..0d0d71dc9907 100644 --- a/docs/Sponsors.md +++ b/docs/Sponsors.md @@ -17,7 +17,6 @@ serve the 3D printing community better. Follow them on ## Sponsors [](https://obico.io/klipper.html?source=klipper_sponsor) -[](https://peopoly.net) ## Klipper Developers diff --git a/docs/_klipper3d/mkdocs.yml b/docs/_klipper3d/mkdocs.yml index 4bfdd169422a..02d32fadca66 100644 --- a/docs/_klipper3d/mkdocs.yml +++ b/docs/_klipper3d/mkdocs.yml @@ -88,7 +88,9 @@ nav: - Config_Changes.md - Contact.md - Installation and Configuration: - - Installation.md + - Installation: + - Installation.md + - OctoPrint.md - Configuration Reference: - Config_Reference.md - Rotation_Distance.md diff --git a/klippy/configfile.py b/klippy/configfile.py index a8a4a4ff76f3..8210de2ba696 100644 --- a/klippy/configfile.py +++ b/klippy/configfile.py @@ -1,12 +1,17 @@ # Code for reading and writing the Klipper config file # -# Copyright (C) 2016-2021 Kevin O'Connor +# Copyright (C) 2016-2024 Kevin O'Connor # # This file may be distributed under the terms of the GNU GPLv3 license. import sys, os, glob, re, time, logging, configparser, io error = configparser.Error + +###################################################################### +# Config section parsing helper +###################################################################### + class sentinel: pass @@ -134,39 +139,118 @@ def deprecate(self, option, value=None): pconfig = self.printer.lookup_object("configfile") pconfig.deprecate(self.section, option, value, msg) + +###################################################################### +# Config file parsing (with include file support) +###################################################################### + +class ConfigFileReader: + def read_config_file(self, filename): + try: + f = open(filename, 'r') + data = f.read() + f.close() + except: + msg = "Unable to open config file %s" % (filename,) + logging.exception(msg) + raise error(msg) + return data.replace('\r\n', '\n') + def build_config_string(self, fileconfig): + sfile = io.StringIO() + fileconfig.write(sfile) + return sfile.getvalue().strip() + def append_fileconfig(self, fileconfig, data, filename): + if not data: + return + # Strip trailing comments + lines = data.split('\n') + for i, line in enumerate(lines): + pos = line.find('#') + if pos >= 0: + lines[i] = line[:pos] + sbuffer = io.StringIO('\n'.join(lines)) + if sys.version_info.major >= 3: + fileconfig.read_file(sbuffer, filename) + else: + fileconfig.readfp(sbuffer, filename) + def _create_fileconfig(self): + if sys.version_info.major >= 3: + fileconfig = configparser.RawConfigParser( + strict=False, inline_comment_prefixes=(';', '#')) + else: + fileconfig = configparser.RawConfigParser() + return fileconfig + def build_fileconfig(self, data, filename): + fileconfig = self._create_fileconfig() + self.append_fileconfig(fileconfig, data, filename) + return fileconfig + def _resolve_include(self, source_filename, include_spec, fileconfig, + visited): + dirname = os.path.dirname(source_filename) + include_spec = include_spec.strip() + include_glob = os.path.join(dirname, include_spec) + include_filenames = glob.glob(include_glob) + if not include_filenames and not glob.has_magic(include_glob): + # Empty set is OK if wildcard but not for direct file reference + raise error("Include file '%s' does not exist" % (include_glob,)) + include_filenames.sort() + for include_filename in include_filenames: + include_data = self.read_config_file(include_filename) + self._parse_config(include_data, include_filename, fileconfig, + visited) + return include_filenames + def _parse_config(self, data, filename, fileconfig, visited): + path = os.path.abspath(filename) + if path in visited: + raise error("Recursive include of config file '%s'" % (filename)) + visited.add(path) + lines = data.split('\n') + # Buffer lines between includes and parse as a unit so that overrides + # in includes apply linearly as they do within a single file + buf = [] + for line in lines: + # Strip trailing comment + pos = line.find('#') + if pos >= 0: + line = line[:pos] + # Process include or buffer line + mo = configparser.RawConfigParser.SECTCRE.match(line) + header = mo and mo.group('header') + if header and header.startswith('include '): + self.append_fileconfig(fileconfig, '\n'.join(buf), filename) + del buf[:] + include_spec = header[8:].strip() + self._resolve_include(filename, include_spec, fileconfig, + visited) + else: + buf.append(line) + self.append_fileconfig(fileconfig, '\n'.join(buf), filename) + visited.remove(path) + def build_fileconfig_with_includes(self, data, filename): + fileconfig = self._create_fileconfig() + self._parse_config(data, filename, fileconfig, set()) + return fileconfig + + +###################################################################### +# Config auto save helper +###################################################################### + AUTOSAVE_HEADER = """ #*# <---------------------- SAVE_CONFIG ----------------------> #*# DO NOT EDIT THIS BLOCK OR BELOW. The contents are auto-generated. #*# """ -class PrinterConfig: +class ConfigAutoSave: def __init__(self, printer): self.printer = printer - self.autosave = None - self.deprecated = {} - self.runtime_warnings = [] - self.deprecate_warnings = [] - self.status_raw_config = {} + self.fileconfig = None self.status_save_pending = {} - self.status_settings = {} - self.status_warnings = [] self.save_config_pending = False gcode = self.printer.lookup_object('gcode') gcode.register_command("SAVE_CONFIG", self.cmd_SAVE_CONFIG, desc=self.cmd_SAVE_CONFIG_help) - def get_printer(self): - return self.printer - def _read_config_file(self, filename): - try: - f = open(filename, 'r') - data = f.read() - f.close() - except: - msg = "Unable to open config file %s" % (filename,) - logging.exception(msg) - raise error(msg) - return data.replace('\r\n', '\n') def _find_autosave_data(self, data): regular_data = data autosave_data = "" @@ -175,7 +259,7 @@ def _find_autosave_data(self, data): regular_data = data[:pos] autosave_data = data[pos + len(AUTOSAVE_HEADER):].strip() # Check for errors and strip line prefixes - if "\n#*# " in regular_data: + if "\n#*# " in regular_data or autosave_data.find(AUTOSAVE_HEADER) >= 0: logging.warning("Can't read autosave from config file" " - autosave state corrupted") return data, "" @@ -192,7 +276,7 @@ def _find_autosave_data(self, data): return regular_data, "\n".join(out) comment_r = re.compile('[#;].*$') value_r = re.compile('[^A-Za-z0-9_].*$') - def _strip_duplicates(self, data, config): + def _strip_duplicates(self, data, fileconfig): # Comment out fields in 'data' that are defined in 'config' lines = data.split('\n') section = None @@ -210,152 +294,31 @@ def _strip_duplicates(self, data, config): section = pruned_line[1:-1].strip() continue field = self.value_r.sub('', pruned_line) - if config.fileconfig.has_option(section, field): + if fileconfig.has_option(section, field): is_dup_field = True lines[lineno] = '#' + lines[lineno] return "\n".join(lines) - def _parse_config_buffer(self, buffer, filename, fileconfig): - if not buffer: - return - data = '\n'.join(buffer) - del buffer[:] - sbuffer = io.StringIO(data) - if sys.version_info.major >= 3: - fileconfig.read_file(sbuffer, filename) - else: - fileconfig.readfp(sbuffer, filename) - def _resolve_include(self, source_filename, include_spec, fileconfig, - visited): - dirname = os.path.dirname(source_filename) - include_spec = include_spec.strip() - include_glob = os.path.join(dirname, include_spec) - include_filenames = glob.glob(include_glob) - if not include_filenames and not glob.has_magic(include_glob): - # Empty set is OK if wildcard but not for direct file reference - raise error("Include file '%s' does not exist" % (include_glob,)) - include_filenames.sort() - for include_filename in include_filenames: - include_data = self._read_config_file(include_filename) - self._parse_config(include_data, include_filename, fileconfig, - visited) - return include_filenames - def _parse_config(self, data, filename, fileconfig, visited): - path = os.path.abspath(filename) - if path in visited: - raise error("Recursive include of config file '%s'" % (filename)) - visited.add(path) - lines = data.split('\n') - # Buffer lines between includes and parse as a unit so that overrides - # in includes apply linearly as they do within a single file - buffer = [] - for line in lines: - # Strip trailing comment - pos = line.find('#') - if pos >= 0: - line = line[:pos] - # Process include or buffer line - mo = configparser.RawConfigParser.SECTCRE.match(line) - header = mo and mo.group('header') - if header and header.startswith('include '): - self._parse_config_buffer(buffer, filename, fileconfig) - include_spec = header[8:].strip() - self._resolve_include(filename, include_spec, fileconfig, - visited) - else: - buffer.append(line) - self._parse_config_buffer(buffer, filename, fileconfig) - visited.remove(path) - def _build_config_wrapper(self, data, filename): - if sys.version_info.major >= 3: - fileconfig = configparser.RawConfigParser( - strict=False, inline_comment_prefixes=(';', '#')) - else: - fileconfig = configparser.RawConfigParser() - self._parse_config(data, filename, fileconfig, set()) - return ConfigWrapper(self.printer, fileconfig, {}, 'printer') - def _build_config_string(self, config): - sfile = io.StringIO() - config.fileconfig.write(sfile) - return sfile.getvalue().strip() - def read_config(self, filename): - return self._build_config_wrapper(self._read_config_file(filename), - filename) - def read_main_config(self): + def load_main_config(self): filename = self.printer.get_start_args()['config_file'] - data = self._read_config_file(filename) + cfgrdr = ConfigFileReader() + data = cfgrdr.read_config_file(filename) regular_data, autosave_data = self._find_autosave_data(data) - regular_config = self._build_config_wrapper(regular_data, filename) - autosave_data = self._strip_duplicates(autosave_data, regular_config) - self.autosave = self._build_config_wrapper(autosave_data, filename) - cfg = self._build_config_wrapper(regular_data + autosave_data, filename) - return cfg - def check_unused_options(self, config): - fileconfig = config.fileconfig - objects = dict(self.printer.lookup_objects()) - # Determine all the fields that have been accessed - access_tracking = dict(config.access_tracking) - for section in self.autosave.fileconfig.sections(): - for option in self.autosave.fileconfig.options(section): - access_tracking[(section.lower(), option.lower())] = 1 - # Validate that there are no undefined parameters in the config file - valid_sections = { s: 1 for s, o in access_tracking } - for section_name in fileconfig.sections(): - section = section_name.lower() - if section not in valid_sections and section not in objects: - raise error("Section '%s' is not a valid config section" - % (section,)) - for option in fileconfig.options(section_name): - option = option.lower() - if (section, option) not in access_tracking: - raise error("Option '%s' is not valid in section '%s'" - % (option, section)) - # Setup get_status() - self._build_status(config) - def log_config(self, config): - lines = ["===== Config file =====", - self._build_config_string(config), - "======================="] - self.printer.set_rollover_info("config", "\n".join(lines)) - # Status reporting - def runtime_warning(self, msg): - logging.warning(msg) - res = {'type': 'runtime_warning', 'message': msg} - self.runtime_warnings.append(res) - self.status_warnings = self.runtime_warnings + self.deprecate_warnings - def deprecate(self, section, option, value=None, msg=None): - self.deprecated[(section, option, value)] = msg - def _build_status(self, config): - self.status_raw_config.clear() - for section in config.get_prefix_sections(''): - self.status_raw_config[section.get_name()] = section_status = {} - for option in section.get_prefix_options(''): - section_status[option] = section.get(option, note_valid=False) - self.status_settings = {} - for (section, option), value in config.access_tracking.items(): - self.status_settings.setdefault(section, {})[option] = value - self.deprecate_warnings = [] - for (section, option, value), msg in self.deprecated.items(): - if value is None: - res = {'type': 'deprecated_option'} - else: - res = {'type': 'deprecated_value', 'value': value} - res['message'] = msg - res['section'] = section - res['option'] = option - self.deprecate_warnings.append(res) - self.status_warnings = self.runtime_warnings + self.deprecate_warnings + regular_fileconfig = cfgrdr.build_fileconfig_with_includes( + regular_data, filename) + autosave_data = self._strip_duplicates(autosave_data, + regular_fileconfig) + self.fileconfig = cfgrdr.build_fileconfig(autosave_data, filename) + cfgrdr.append_fileconfig(regular_fileconfig, + autosave_data, '*AUTOSAVE*') + return regular_fileconfig, self.fileconfig def get_status(self, eventtime): - return {'config': self.status_raw_config, - 'settings': self.status_settings, - 'warnings': self.status_warnings, - 'save_config_pending': self.save_config_pending, + return {'save_config_pending': self.save_config_pending, 'save_config_pending_items': self.status_save_pending} - # Autosave functions def set(self, section, option, value): - if not self.autosave.fileconfig.has_section(section): - self.autosave.fileconfig.add_section(section) + if not self.fileconfig.has_section(section): + self.fileconfig.add_section(section) svalue = str(value) - self.autosave.fileconfig.set(section, option, svalue) + self.fileconfig.set(section, option, svalue) pending = dict(self.status_save_pending) if not section in pending or pending[section] is None: pending[section] = {} @@ -366,8 +329,8 @@ def set(self, section, option, value): self.save_config_pending = True logging.info("save_config: set [%s] %s = %s", section, option, svalue) def remove_section(self, section): - if self.autosave.fileconfig.has_section(section): - self.autosave.fileconfig.remove_section(section) + if self.fileconfig.has_section(section): + self.fileconfig.remove_section(section) pending = dict(self.status_save_pending) pending[section] = None self.status_save_pending = pending @@ -378,21 +341,20 @@ def remove_section(self, section): del pending[section] self.status_save_pending = pending self.save_config_pending = True - def _disallow_include_conflicts(self, regular_data, cfgname, gcode): - config = self._build_config_wrapper(regular_data, cfgname) - for section in self.autosave.fileconfig.sections(): - for option in self.autosave.fileconfig.options(section): - if config.fileconfig.has_option(section, option): + def _disallow_include_conflicts(self, regular_fileconfig): + for section in self.fileconfig.sections(): + for option in self.fileconfig.options(section): + if regular_fileconfig.has_option(section, option): msg = ("SAVE_CONFIG section '%s' option '%s' conflicts " "with included value" % (section, option)) - raise gcode.error(msg) + raise self.printer.command_error(msg) cmd_SAVE_CONFIG_help = "Overwrite config file and restart" def cmd_SAVE_CONFIG(self, gcmd): - if not self.autosave.fileconfig.sections(): + if not self.fileconfig.sections(): return - gcode = self.printer.lookup_object('gcode') # Create string containing autosave data - autosave_data = self._build_config_string(self.autosave) + cfgrdr = ConfigFileReader() + autosave_data = cfgrdr.build_config_string(self.fileconfig) lines = [('#*# ' + l).strip() for l in autosave_data.split('\n')] lines.insert(0, "\n" + AUTOSAVE_HEADER.rstrip()) @@ -401,16 +363,27 @@ def cmd_SAVE_CONFIG(self, gcmd): # Read in and validate current config file cfgname = self.printer.get_start_args()['config_file'] try: - data = self._read_config_file(cfgname) - regular_data, old_autosave_data = self._find_autosave_data(data) - config = self._build_config_wrapper(regular_data, cfgname) + data = cfgrdr.read_config_file(cfgname) except error as e: - msg = "Unable to parse existing config on SAVE_CONFIG" + msg = "Unable to read existing config on SAVE_CONFIG" logging.exception(msg) - raise gcode.error(msg) - regular_data = self._strip_duplicates(regular_data, self.autosave) - self._disallow_include_conflicts(regular_data, cfgname, gcode) + raise gcmd.error(msg) + regular_data, old_autosave_data = self._find_autosave_data(data) + regular_data = self._strip_duplicates(regular_data, self.fileconfig) data = regular_data.rstrip() + autosave_data + new_regular_data, new_autosave_data = self._find_autosave_data(data) + if not new_autosave_data: + raise gcmd.error( + "Existing config autosave is corrupted." + " Can't complete SAVE_CONFIG") + try: + regular_fileconfig = cfgrdr.build_fileconfig_with_includes( + new_regular_data, cfgname) + except error as e: + msg = "Unable to parse existing config on SAVE_CONFIG" + logging.exception(msg) + raise gcmd.error(msg) + self._disallow_include_conflicts(regular_fileconfig) # Determine filenames datestr = time.strftime("-%Y%m%d_%H%M%S") backup_name = cfgname + datestr @@ -430,6 +403,135 @@ def cmd_SAVE_CONFIG(self, gcmd): except: msg = "Unable to write config file during SAVE_CONFIG" logging.exception(msg) - raise gcode.error(msg) + raise gcmd.error(msg) # Request a restart + gcode = self.printer.lookup_object('gcode') gcode.request_restart('restart') + + +###################################################################### +# Config validation (check for undefined options) +###################################################################### + +class ConfigValidate: + def __init__(self, printer): + self.printer = printer + self.status_settings = {} + self.access_tracking = {} + self.autosave_options = {} + def start_access_tracking(self, autosave_fileconfig): + # Note autosave options for use during undefined options check + self.autosave_options = {} + for section in autosave_fileconfig.sections(): + for option in autosave_fileconfig.options(section): + self.autosave_options[(section.lower(), option.lower())] = 1 + self.access_tracking = {} + return self.access_tracking + def check_unused(self, fileconfig): + # Don't warn on fields set in autosave segment + access_tracking = dict(self.access_tracking) + access_tracking.update(self.autosave_options) + # Note locally used sections + valid_sections = { s: 1 for s, o in self.printer.lookup_objects() } + valid_sections.update({ s: 1 for s, o in access_tracking }) + # Validate that there are no undefined parameters in the config file + for section_name in fileconfig.sections(): + section = section_name.lower() + if section not in valid_sections: + raise error("Section '%s' is not a valid config section" + % (section,)) + for option in fileconfig.options(section_name): + option = option.lower() + if (section, option) not in access_tracking: + raise error("Option '%s' is not valid in section '%s'" + % (option, section)) + # Setup get_status() + self._build_status_settings() + # Clear tracking state + self.access_tracking.clear() + self.autosave_options.clear() + def _build_status_settings(self): + self.status_settings = {} + for (section, option), value in self.access_tracking.items(): + self.status_settings.setdefault(section, {})[option] = value + def get_status(self, eventtime): + return {'settings': self.status_settings} + + +###################################################################### +# Main printer config tracking +###################################################################### + +class PrinterConfig: + def __init__(self, printer): + self.printer = printer + self.autosave = ConfigAutoSave(printer) + self.validate = ConfigValidate(printer) + self.deprecated = {} + self.runtime_warnings = [] + self.deprecate_warnings = [] + self.status_raw_config = {} + self.status_warnings = [] + def get_printer(self): + return self.printer + def read_config(self, filename): + cfgrdr = ConfigFileReader() + data = cfgrdr.read_config_file(filename) + fileconfig = cfgrdr.build_fileconfig(data, filename) + return ConfigWrapper(self.printer, fileconfig, {}, 'printer') + def read_main_config(self): + fileconfig, autosave_fileconfig = self.autosave.load_main_config() + access_tracking = self.validate.start_access_tracking( + autosave_fileconfig) + config = ConfigWrapper(self.printer, fileconfig, + access_tracking, 'printer') + self._build_status_config(config) + return config + def log_config(self, config): + cfgrdr = ConfigFileReader() + lines = ["===== Config file =====", + cfgrdr.build_config_string(config.fileconfig), + "======================="] + self.printer.set_rollover_info("config", "\n".join(lines)) + def check_unused_options(self, config): + self.validate.check_unused(config.fileconfig) + # Deprecation warnings + def runtime_warning(self, msg): + logging.warning(msg) + res = {'type': 'runtime_warning', 'message': msg} + self.runtime_warnings.append(res) + self.status_warnings = self.runtime_warnings + self.deprecate_warnings + def deprecate(self, section, option, value=None, msg=None): + key = (section, option, value) + if key in self.deprecated and self.deprecated[key] == msg: + return + self.deprecated[key] = msg + self.deprecate_warnings = [] + for (section, option, value), msg in self.deprecated.items(): + if value is None: + res = {'type': 'deprecated_option'} + else: + res = {'type': 'deprecated_value', 'value': value} + res['message'] = msg + res['section'] = section + res['option'] = option + self.deprecate_warnings.append(res) + self.status_warnings = self.runtime_warnings + self.deprecate_warnings + # Status reporting + def _build_status_config(self, config): + self.status_raw_config = {} + for section in config.get_prefix_sections(''): + self.status_raw_config[section.get_name()] = section_status = {} + for option in section.get_prefix_options(''): + section_status[option] = section.get(option, note_valid=False) + def get_status(self, eventtime): + status = {'config': self.status_raw_config, + 'warnings': self.status_warnings} + status.update(self.autosave.get_status(eventtime)) + status.update(self.validate.get_status(eventtime)) + return status + # Autosave functions + def set(self, section, option, value): + self.autosave.set(section, option, value) + def remove_section(self, section): + self.autosave.remove_section(section) diff --git a/klippy/extras/ads1220.py b/klippy/extras/ads1220.py new file mode 100644 index 000000000000..fcae78bca807 --- /dev/null +++ b/klippy/extras/ads1220.py @@ -0,0 +1,216 @@ +# ADS1220 Support +# +# Copyright (C) 2024 Gareth Farrington +# +# This file may be distributed under the terms of the GNU GPLv3 license. +import logging +from . import bulk_sensor, bus + +# +# Constants +# +BYTES_PER_SAMPLE = 4 # samples are 4 byte wide unsigned integers +MAX_SAMPLES_PER_MESSAGE = bulk_sensor.MAX_BULK_MSG_SIZE // BYTES_PER_SAMPLE +UPDATE_INTERVAL = 0.10 +RESET_CMD = 0x06 +START_SYNC_CMD = 0x08 +RREG_CMD = 0x20 +WREG_CMD = 0x40 +NOOP_CMD = 0x0 +RESET_STATE = bytearray([0x0, 0x0, 0x0, 0x0]) + +# turn bytearrays into pretty hex strings: [0xff, 0x1] +def hexify(byte_array): + return "[%s]" % (", ".join([hex(b) for b in byte_array])) + + +class ADS1220: + def __init__(self, config): + self.printer = printer = config.get_printer() + self.name = config.get_name().split()[-1] + self.last_error_count = 0 + self.consecutive_fails = 0 + # Chip options + # Gain + self.gain_options = {'1': 0x0, '2': 0x1, '4': 0x2, '8': 0x3, '16': 0x4, + '32': 0x5, '64': 0x6, '128': 0x7} + self.gain = config.getchoice('gain', self.gain_options, default='128') + # Sample rate + self.sps_normal = {'20': 20, '45': 45, '90': 90, '175': 175, + '330': 330, '600': 600, '1000': 1000} + self.sps_turbo = {'40': 40, '90': 90, '180': 180, '350': 350, + '660': 660, '1200': 1200, '2000': 2000} + self.sps_options = self.sps_normal.copy() + self.sps_options.update(self.sps_turbo) + self.sps = config.getchoice('sample_rate', self.sps_options, + default='660') + self.is_turbo = str(self.sps) in self.sps_turbo + # Input multiplexer: AINP and AINN + mux_options = {'AIN0_AIN1': 0b0000, 'AIN0_AIN2': 0b0001, + 'AIN0_AIN3': 0b0010, 'AIN1_AIN2': 0b0011, + 'AIN1_AIN3': 0b0100, 'AIN2_AIN3': 0b0101, + 'AIN1_AIN0': 0b0110, 'AIN3_AIN2': 0b0111, + 'AIN0_AVSS': 0b1000, 'AIN1_AVSS': 0b1001, + 'AIN2_AVSS': 0b1010, 'AIN3_AVSS': 0b1011} + self.mux = config.getchoice('input_mux', mux_options, + default='AIN0_AIN1') + # PGA Bypass + self.pga_bypass = config.getboolean('pga_bypass', default=False) + # bypass PGA when AVSS is the negative input + force_pga_bypass = self.mux >= 0b1000 + self.pga_bypass = force_pga_bypass or self.pga_bypass + # Voltage Reference + self.vref_options = {'internal': 0b0, 'REF0': 0b01, 'REF1': 0b10, + 'analog_supply': 0b11} + self.vref = config.getchoice('vref', self.vref_options, + default='internal') + # check for conflict between REF1 and AIN0/AIN3 + mux_conflict = [0b0000, 0b0001, 0b0010, 0b0100, 0b0101, 0b0110, 0b0111, + 0b1000, 0b1011] + if self.vref == 0b10 and self.mux in mux_conflict: + raise config.error("ADS1220 config error: AIN0/REFP1 and AIN3/REFN1" + " cant be used as a voltage reference and" + " an input at the same time") + # SPI Setup + spi_speed = 512000 if self.is_turbo else 256000 + self.spi = bus.MCU_SPI_from_config(config, 1, default_speed=spi_speed) + self.mcu = mcu = self.spi.get_mcu() + self.oid = mcu.create_oid() + # Data Ready (DRDY) Pin + drdy_pin = config.get('data_ready_pin') + ppins = printer.lookup_object('pins') + drdy_ppin = ppins.lookup_pin(drdy_pin) + self.data_ready_pin = drdy_ppin['pin'] + drdy_pin_mcu = drdy_ppin['chip'] + if drdy_pin_mcu != self.mcu: + raise config.error("ADS1220 config error: SPI communication and" + " data_ready_pin must be on the same MCU") + # Bulk Sensor Setup + self.bulk_queue = bulk_sensor.BulkDataQueue(self.mcu, oid=self.oid) + # Clock tracking + chip_smooth = self.sps * UPDATE_INTERVAL * 2 + # Measurement conversion + self.ffreader = bulk_sensor.FixedFreqReader(mcu, chip_smooth, " 1: + t_sb = 5 + elif max_standby_time > 0.5: + t_sb = 4 + elif max_standby_time > 0.25: + t_sb = 3 + elif max_standby_time > 0.125: + t_sb = 2 + elif max_standby_time > 0.0625: + t_sb = 1 + elif max_standby_time > 0.020: + t_sb = 7 + elif max_standby_time > 0.010: + t_sb = 6 + else: + if max_standby_time > 4: + t_sb = 7 + elif max_standby_time > 2: + t_sb = 6 + elif max_standby_time > 1: + t_sb = 5 + elif max_standby_time > 0.5: + t_sb = 4 + elif max_standby_time > 0.25: + t_sb = 3 + elif max_standby_time > 0.125: + t_sb = 2 + elif max_standby_time > 0.0625: + t_sb = 1 + + cfg = t_sb << 5 | self.iir_filter << 2 + self.write_register('CONFIG', cfg) + if self.chip_type == 'BME280': + self.write_register('CTRL_HUM', self.os_hum) + # Enter normal (periodic) mode + meas = self.os_temp << 5 | self.os_pres << 2 | MODE_PERIODIC + self.write_register('CTRL_MEAS', meas, wait=True) - try: - # wait until results are ready - status = self.read_register('STATUS', 1)[0] - while status & STATUS_MEASURING: - self.reactor.pause( - self.reactor.monotonic() + self.max_sample_time) - status = self.read_register('STATUS', 1)[0] + if self.chip_type == 'BME680': + self.write_register('CONFIG', self.iir_filter << 2) + # Should be set once and reused on every mode register write + self.write_register('CTRL_HUM', self.os_hum & 0x07) + gas_wait_0 = self._calc_gas_heater_duration(self.gas_heat_duration) + self.write_register('GAS_WAIT_0', [gas_wait_0]) + res_heat_0 = self._calc_gas_heater_resistance(self.gas_heat_temp) + self.write_register('RES_HEAT_0', [res_heat_0]) + # Set initial heater current to reach Gas heater target on start + self.write_register('IDAC_HEAT_0', 96) + def _sample_bme280(self, eventtime): + # In normal mode data shadowing is performed + # So reading can be done while measurements are in process + try: if self.chip_type == 'BME280': data = self.read_register('PRESSURE_MSB', 8) elif self.chip_type == 'BMP280': @@ -462,36 +511,40 @@ def _sample_bmp388_press(self): return comp_press def _sample_bme680(self, eventtime): - self.write_register('CTRL_HUM', self.os_hum & 0x07) - meas = self.os_temp << 5 | self.os_pres << 2 - self.write_register('CTRL_MEAS', [meas]) - - gas_wait_0 = self._calculate_gas_heater_duration(self.gas_heat_duration) - self.write_register('GAS_WAIT_0', [gas_wait_0]) - res_heat_0 = self._calculate_gas_heater_resistance(self.gas_heat_temp) - self.write_register('RES_HEAT_0', [res_heat_0]) - gas_config = RUN_GAS | NB_CONV_0 - self.write_register('CTRL_GAS_1', [gas_config]) - - def data_ready(stat): + def data_ready(stat, run_gas): new_data = (stat & EAS_NEW_DATA) gas_done = not (stat & GAS_DONE) meas_done = not (stat & MEASURE_DONE) + if not run_gas: + gas_done = True return new_data and gas_done and meas_done + run_gas = False + # Check VOC once a while + if self.reactor.monotonic() - self.last_gas_time > 3: + gas_config = RUN_GAS | NB_CONV_0 + self.write_register('CTRL_GAS_1', [gas_config]) + run_gas = True + # Enter forced mode - meas = meas | MODE - self.write_register('CTRL_MEAS', meas) + meas = self.os_temp << 5 | self.os_pres << 2 | MODE + self.write_register('CTRL_MEAS', meas, wait=True) + max_sample_time = self.max_sample_time + if run_gas: + max_sample_time += self.gas_heat_duration / 1000 + self.reactor.pause(self.reactor.monotonic() + max_sample_time) try: # wait until results are ready status = self.read_register('EAS_STATUS_0', 1)[0] - while not data_ready(status): + while not data_ready(status, run_gas): self.reactor.pause( self.reactor.monotonic() + self.max_sample_time) status = self.read_register('EAS_STATUS_0', 1)[0] data = self.read_register('PRESSURE_MSB', 8) - gas_data = self.read_register('GAS_R_MSB', 2) + gas_data = [0, 0] + if run_gas: + gas_data = self.read_register('GAS_R_MSB', 2) except Exception: logging.exception("BME680: Error reading data") self.temp = self.pressure = self.humidity = self.gas = .0 @@ -515,6 +568,10 @@ def data_ready(stat): gas_raw = (gas_data[0] << 2) | ((gas_data[1] & 0xC0) >> 6) gas_range = (gas_data[1] & 0x0F) self.gas = self._compensate_gas(gas_raw, gas_range) + # Disable gas measurement on success + gas_config = NB_CONV_0 + self.write_register('CTRL_GAS_1', [gas_config]) + self.last_gas_time = self.reactor.monotonic() if self.temp < self.min_temp or self.temp > self.max_temp: self.printer.invoke_shutdown( @@ -643,7 +700,7 @@ def _compensate_gas(self, gas_raw, gas_range): gas_raw - 512. + var1) return gas - def _calculate_gas_heater_resistance(self, target_temp): + def _calc_gas_heater_resistance(self, target_temp): amb_temp = self.temp heater_data = self.read_register('RES_HEAT_VAL', 3) res_heat_val = get_signed_byte(heater_data[0]) @@ -658,7 +715,7 @@ def _calculate_gas_heater_resistance(self, target_temp): * (1. / (1. + (res_heat_val * 0.002)))) - 25)) return int(res_heat) - def _calculate_gas_heater_duration(self, duration_ms): + def _calc_gas_heater_duration(self, duration_ms): if duration_ms >= 4032: duration_reg = 0xff else: @@ -719,12 +776,15 @@ def read_register(self, reg_name, read_len): params = self.i2c.i2c_read(regs, read_len) return bytearray(params['response']) - def write_register(self, reg_name, data): + def write_register(self, reg_name, data, wait = False): if type(data) is not list: data = [data] reg = self.chip_registers[reg_name] data.insert(0, reg) - self.i2c.i2c_write(data) + if not wait: + self.i2c.i2c_write(data) + else: + self.i2c.i2c_write_wait_ack(data) def get_status(self, eventtime): data = { diff --git a/klippy/extras/bus.py b/klippy/extras/bus.py index 28bfcdf0d15d..b8236dc7c042 100644 --- a/klippy/extras/bus.py +++ b/klippy/extras/bus.py @@ -160,7 +160,7 @@ def __init__(self, mcu, bus, addr, speed, sw_pins=None): % (self.oid, speed, addr)) self.cmd_queue = self.mcu.alloc_command_queue() self.mcu.register_config_callback(self.build_config) - self.i2c_write_cmd = self.i2c_read_cmd = self.i2c_modify_bits_cmd = None + self.i2c_write_cmd = self.i2c_read_cmd = None def get_oid(self): return self.oid def get_mcu(self): @@ -180,9 +180,6 @@ def build_config(self): "i2c_read oid=%c reg=%*s read_len=%u", "i2c_read_response oid=%c response=%*s", oid=self.oid, cq=self.cmd_queue) - self.i2c_modify_bits_cmd = self.mcu.lookup_command( - "i2c_modify_bits oid=%c reg=%*s clear_set_bits=%*s", - cq=self.cmd_queue) def i2c_write(self, data, minclock=0, reqclock=0): if self.i2c_write_cmd is None: # Send setup message via mcu initialization @@ -197,19 +194,6 @@ def i2c_write_wait_ack(self, data, minclock=0, reqclock=0): minclock=minclock, reqclock=reqclock) def i2c_read(self, write, read_len): return self.i2c_read_cmd.send([self.oid, write, read_len]) - def i2c_modify_bits(self, reg, clear_bits, set_bits, - minclock=0, reqclock=0): - clearset = clear_bits + set_bits - if self.i2c_modify_bits_cmd is None: - # Send setup message via mcu initialization - reg_msg = "".join(["%02x" % (x,) for x in reg]) - clearset_msg = "".join(["%02x" % (x,) for x in clearset]) - self.mcu.add_config_cmd( - "i2c_modify_bits oid=%d reg=%s clear_set_bits=%s" % ( - self.oid, reg_msg, clearset_msg), is_init=True) - return - self.i2c_modify_bits_cmd.send([self.oid, reg, clearset], - minclock=minclock, reqclock=reqclock) def MCU_I2C_from_config(config, default_addr=None, default_speed=100000): # Load bus parameters diff --git a/klippy/extras/controller_fan.py b/klippy/extras/controller_fan.py index df141e7eb7d1..b1286b59712a 100644 --- a/klippy/extras/controller_fan.py +++ b/klippy/extras/controller_fan.py @@ -62,9 +62,7 @@ def callback(self, eventtime): self.last_on += 1 if speed != self.last_speed: self.last_speed = speed - curtime = self.printer.get_reactor().monotonic() - print_time = self.fan.get_mcu().estimated_print_time(curtime) - self.fan.set_speed(print_time + PIN_MIN_TIME, speed) + self.fan.set_speed(speed) return eventtime + 1. def load_config_prefix(config): diff --git a/klippy/extras/dotstar.py b/klippy/extras/dotstar.py index 4186534fead6..0262c13d0ade 100644 --- a/klippy/extras/dotstar.py +++ b/klippy/extras/dotstar.py @@ -1,9 +1,9 @@ # Support for "dotstar" leds # -# Copyright (C) 2019-2022 Kevin O'Connor +# Copyright (C) 2019-2024 Kevin O'Connor # # This file may be distributed under the terms of the GNU GPLv3 license. -from . import bus +from . import bus, led BACKGROUND_PRIORITY_CLOCK = 0x7fffffff00000000 @@ -22,9 +22,8 @@ def __init__(self, config): self.spi = bus.MCU_SPI(mcu, None, None, 0, 500000, sw_spi_pins) # Initialize color data self.chain_count = config.getint('chain_count', 1, minval=1) - pled = printer.load_object(config, "led") - self.led_helper = pled.setup_helper(config, self.update_leds, - self.chain_count) + self.led_helper = led.LEDHelper(config, self.update_leds, + self.chain_count) self.prev_data = None # Register commands printer.register_event_handler("klippy:connect", self.handle_connect) diff --git a/klippy/extras/fan.py b/klippy/extras/fan.py index d6e687218c5e..c5677ba068a3 100644 --- a/klippy/extras/fan.py +++ b/klippy/extras/fan.py @@ -1,17 +1,14 @@ # Printer cooling fan # -# Copyright (C) 2016-2020 Kevin O'Connor +# Copyright (C) 2016-2024 Kevin O'Connor # # This file may be distributed under the terms of the GNU GPLv3 license. -from . import pulse_counter - -FAN_MIN_TIME = 0.100 +from . import pulse_counter, output_pin class Fan: def __init__(self, config, default_shutdown_speed=0.): self.printer = config.get_printer() - self.last_fan_value = 0. - self.last_fan_time = 0. + self.last_fan_value = self.last_req_value = 0. # Read config self.max_power = config.getfloat('max_power', 1., above=0., maxval=1.) self.kick_start_time = config.getfloat('kick_start_time', 0.1, @@ -36,6 +33,10 @@ def __init__(self, config, default_shutdown_speed=0.): self.enable_pin = ppins.setup_pin('digital_out', enable_pin) self.enable_pin.setup_max_duration(0.) + # Create gcode request queue + self.gcrq = output_pin.GCodeRequestQueue(config, self.mcu_fan.get_mcu(), + self._apply_speed) + # Setup tachometer self.tachometer = FanTachometer(config) @@ -45,37 +46,37 @@ def __init__(self, config, default_shutdown_speed=0.): def get_mcu(self): return self.mcu_fan.get_mcu() - def set_speed(self, print_time, value): + def _apply_speed(self, print_time, value): if value < self.off_below: value = 0. value = max(0., min(self.max_power, value * self.max_power)) if value == self.last_fan_value: - return - print_time = max(self.last_fan_time + FAN_MIN_TIME, print_time) + return "discard", 0. if self.enable_pin: if value > 0 and self.last_fan_value == 0: self.enable_pin.set_digital(print_time, 1) elif value == 0 and self.last_fan_value > 0: self.enable_pin.set_digital(print_time, 0) - if (value and value < self.max_power and self.kick_start_time + if (value and self.kick_start_time and (not self.last_fan_value or value - self.last_fan_value > .5)): # Run fan at full speed for specified kick_start_time + self.last_req_value = value + self.last_fan_value = self.max_power self.mcu_fan.set_pwm(print_time, self.max_power) - print_time += self.kick_start_time + return "delay", self.kick_start_time + self.last_fan_value = self.last_req_value = value self.mcu_fan.set_pwm(print_time, value) - self.last_fan_time = print_time - self.last_fan_value = value + def set_speed(self, value, print_time=None): + self.gcrq.send_async_request(value, print_time) def set_speed_from_command(self, value): - toolhead = self.printer.lookup_object('toolhead') - toolhead.register_lookahead_callback((lambda pt: - self.set_speed(pt, value))) + self.gcrq.queue_gcode_request(value) def _handle_request_restart(self, print_time): - self.set_speed(print_time, 0.) + self.set_speed(0., print_time) def get_status(self, eventtime): tachometer_status = self.tachometer.get_status(eventtime) return { - 'speed': self.last_fan_value, + 'speed': self.last_req_value, 'rpm': tachometer_status['rpm'], } diff --git a/klippy/extras/fan_generic.py b/klippy/extras/fan_generic.py index def9a77e146b..20bd57e70fd0 100644 --- a/klippy/extras/fan_generic.py +++ b/klippy/extras/fan_generic.py @@ -1,9 +1,10 @@ # Support fans that are controlled by gcode # -# Copyright (C) 2016-2020 Kevin O'Connor +# Copyright (C) 2016-2024 Kevin O'Connor # # This file may be distributed under the terms of the GNU GPLv3 license. -from . import fan +import logging +from . import fan, output_pin class PrinterFanGeneric: cmd_SET_FAN_SPEED_help = "Sets the speed of a fan" @@ -12,6 +13,9 @@ def __init__(self, config): self.fan = fan.Fan(config, default_shutdown_speed=0.) self.fan_name = config.get_name().split()[-1] + # Template handling + self.template_eval = output_pin.lookup_template_eval(config) + gcode = self.printer.lookup_object("gcode") gcode.register_mux_command("SET_FAN_SPEED", "FAN", self.fan_name, @@ -20,8 +24,21 @@ def __init__(self, config): def get_status(self, eventtime): return self.fan.get_status(eventtime) + def _template_update(self, text): + try: + value = float(text) + except ValueError as e: + logging.exception("fan_generic template render error") + self.fan.set_speed(value) def cmd_SET_FAN_SPEED(self, gcmd): - speed = gcmd.get_float('SPEED', 0.) + speed = gcmd.get_float('SPEED', None, 0.) + template = gcmd.get('TEMPLATE', None) + if (speed is None) == (template is None): + raise gcmd.error("SET_FAN_SPEED must specify SPEED or TEMPLATE") + # Check for template setting + if template is not None: + self.template_eval.set_template(gcmd, self._template_update) + return self.fan.set_speed_from_command(speed) def load_config_prefix(config): diff --git a/klippy/extras/gcode_arcs.py b/klippy/extras/gcode_arcs.py index 76c165dd5bca..3917dac30bf2 100644 --- a/klippy/extras/gcode_arcs.py +++ b/klippy/extras/gcode_arcs.py @@ -39,8 +39,6 @@ def __init__(self, config): self.gcode.register_command("G18", self.cmd_G18) self.gcode.register_command("G19", self.cmd_G19) - self.Coord = self.gcode.Coord - # backwards compatibility, prior implementation only supported XY self.plane = ARC_PLANE_X_Y @@ -64,52 +62,36 @@ def _cmd_inner(self, gcmd, clockwise): if not gcodestatus['absolute_coordinates']: raise gcmd.error("G2/G3 does not support relative move mode") currentPos = gcodestatus['gcode_position'] + absolut_extrude = gcodestatus['absolute_extrude'] # Parse parameters - asTarget = self.Coord(x=gcmd.get_float("X", currentPos[0]), - y=gcmd.get_float("Y", currentPos[1]), - z=gcmd.get_float("Z", currentPos[2]), - e=None) + asTarget = [gcmd.get_float("X", currentPos[0]), + gcmd.get_float("Y", currentPos[1]), + gcmd.get_float("Z", currentPos[2])] if gcmd.get_float("R", None) is not None: raise gcmd.error("G2/G3 does not support R moves") # determine the plane coordinates and the helical axis - asPlanar = [ gcmd.get_float(a, 0.) for i,a in enumerate('IJ') ] + I = gcmd.get_float('I', 0.) + J = gcmd.get_float('J', 0.) + asPlanar = (I, J) axes = (X_AXIS, Y_AXIS, Z_AXIS) if self.plane == ARC_PLANE_X_Z: - asPlanar = [ gcmd.get_float(a, 0.) for i,a in enumerate('IK') ] + K = gcmd.get_float('K', 0.) + asPlanar = (I, K) axes = (X_AXIS, Z_AXIS, Y_AXIS) elif self.plane == ARC_PLANE_Y_Z: - asPlanar = [ gcmd.get_float(a, 0.) for i,a in enumerate('JK') ] + K = gcmd.get_float('K', 0.) + asPlanar = (J, K) axes = (Y_AXIS, Z_AXIS, X_AXIS) if not (asPlanar[0] or asPlanar[1]): raise gcmd.error("G2/G3 requires IJ, IK or JK parameters") - asE = gcmd.get_float("E", None) - asF = gcmd.get_float("F", None) - - # Build list of linear coordinates to move - coords = self.planArc(currentPos, asTarget, asPlanar, - clockwise, *axes) - e_per_move = e_base = 0. - if asE is not None: - if gcodestatus['absolute_extrude']: - e_base = currentPos[3] - e_per_move = (asE - e_base) / len(coords) - - # Convert coords into G1 commands - for coord in coords: - g1_params = {'X': coord[0], 'Y': coord[1], 'Z': coord[2]} - if e_per_move: - g1_params['E'] = e_base + e_per_move - if gcodestatus['absolute_extrude']: - e_base += e_per_move - if asF is not None: - g1_params['F'] = asF - g1_gcmd = self.gcode.create_gcode_command("G1", "G1", g1_params) - self.gcode_move.cmd_G1(g1_gcmd) + # Build linear coordinates to move + self.planArc(currentPos, asTarget, asPlanar, clockwise, + gcmd, absolut_extrude, *axes) # function planArc() originates from marlin plan_arc() # https://github.com/MarlinFirmware/Marlin @@ -120,6 +102,7 @@ def _cmd_inner(self, gcmd, clockwise): # # alpha and beta axes are the current plane, helical axis is linear travel def planArc(self, currentPos, targetPos, offset, clockwise, + gcmd, absolut_extrude, alpha_axis, beta_axis, helical_axis): # todo: sometimes produces full circles @@ -159,23 +142,42 @@ def planArc(self, currentPos, targetPos, offset, clockwise, # Generate coordinates theta_per_segment = angular_travel / segments linear_per_segment = linear_travel / segments - coords = [] - for i in range(1, int(segments)): + + asE = gcmd.get_float("E", None) + asF = gcmd.get_float("F", None) + + e_per_move = e_base = 0. + if asE is not None: + if absolut_extrude: + e_base = currentPos[3] + e_per_move = (asE - e_base) / segments + + for i in range(1, int(segments) + 1): dist_Helical = i * linear_per_segment - cos_Ti = math.cos(i * theta_per_segment) - sin_Ti = math.sin(i * theta_per_segment) + c_theta = i * theta_per_segment + cos_Ti = math.cos(c_theta) + sin_Ti = math.sin(c_theta) r_P = -offset[0] * cos_Ti + offset[1] * sin_Ti r_Q = -offset[0] * sin_Ti - offset[1] * cos_Ti - # Coord doesn't support index assignment, create list - c = [None, None, None, None] + c = [None, None, None] c[alpha_axis] = center_P + r_P c[beta_axis] = center_Q + r_Q c[helical_axis] = currentPos[helical_axis] + dist_Helical - coords.append(self.Coord(*c)) - coords.append(targetPos) - return coords + + if i == segments: + c = targetPos + # Convert coords into G1 commands + g1_params = {'X': c[0], 'Y': c[1], 'Z': c[2]} + if e_per_move: + g1_params['E'] = e_base + e_per_move + if absolut_extrude: + e_base += e_per_move + if asF is not None: + g1_params['F'] = asF + g1_gcmd = self.gcode.create_gcode_command("G1", "G1", g1_params) + self.gcode_move.cmd_G1(g1_gcmd) def load_config(config): return ArcSupport(config) diff --git a/klippy/extras/heater_fan.py b/klippy/extras/heater_fan.py index ab4c8a81e7f6..3630366e915f 100644 --- a/klippy/extras/heater_fan.py +++ b/klippy/extras/heater_fan.py @@ -33,9 +33,7 @@ def callback(self, eventtime): speed = self.fan_speed if speed != self.last_speed: self.last_speed = speed - curtime = self.printer.get_reactor().monotonic() - print_time = self.fan.get_mcu().estimated_print_time(curtime) - self.fan.set_speed(print_time + PIN_MIN_TIME, speed) + self.fan.set_speed(speed) return eventtime + 1. def load_config_prefix(config): diff --git a/klippy/extras/heaters.py b/klippy/extras/heaters.py index 5480501326b4..7cb663a4a279 100644 --- a/klippy/extras/heaters.py +++ b/klippy/extras/heaters.py @@ -259,7 +259,8 @@ def load_config(self, config): try: dconfig = pconfig.read_config(filename) except Exception: - raise config.config_error("Cannot load config '%s'" % (filename,)) + logging.exception("Unable to load temperature_sensors.cfg") + raise config.error("Cannot load config '%s'" % (filename,)) for c in dconfig.get_prefix_sections(''): self.printer.load_object(dconfig, c.get_name()) def add_sensor_factory(self, sensor_type, sensor_factory): diff --git a/klippy/extras/homing.py b/klippy/extras/homing.py index 06b52f1ec56e..bbad53371594 100644 --- a/klippy/extras/homing.py +++ b/klippy/extras/homing.py @@ -1,6 +1,6 @@ # Helper code for implementing homing operations # -# Copyright (C) 2016-2021 Kevin O'Connor +# Copyright (C) 2016-2024 Kevin O'Connor # # This file may be distributed under the terms of the GNU GPLv3 license. import logging, math @@ -29,10 +29,17 @@ def __init__(self, stepper, endstop_name): self.endstop_name = endstop_name self.stepper_name = stepper.get_name() self.start_pos = stepper.get_mcu_position() + self.start_cmd_pos = stepper.mcu_to_commanded_position(self.start_pos) self.halt_pos = self.trig_pos = None def note_home_end(self, trigger_time): self.halt_pos = self.stepper.get_mcu_position() self.trig_pos = self.stepper.get_past_mcu_position(trigger_time) + def verify_no_probe_skew(self, haltpos): + new_start_pos = self.stepper.get_mcu_position(self.start_cmd_pos) + if new_start_pos != self.start_pos: + logging.warning( + "Stepper '%s' position skew after probe: pos %d now %d", + self.stepper.get_name(), self.start_pos, new_start_pos) # Implementation of homing/probing moves class HomingMove: @@ -121,6 +128,9 @@ def homing_move(self, movepos, speed, probe_pos=False, haltpos = trigpos = self.calc_toolhead_pos(kin_spos, trig_steps) if trig_steps != halt_steps: haltpos = self.calc_toolhead_pos(kin_spos, halt_steps) + self.toolhead.set_position(haltpos) + for sp in self.stepper_positions: + sp.verify_no_probe_skew(haltpos) else: haltpos = trigpos = movepos over_steps = {sp.stepper_name: sp.halt_pos - sp.trig_pos @@ -130,7 +140,7 @@ def homing_move(self, movepos, speed, probe_pos=False, halt_kin_spos = {s.get_name(): s.get_commanded_position() for s in kin.get_steppers()} haltpos = self.calc_toolhead_pos(halt_kin_spos, over_steps) - self.toolhead.set_position(haltpos) + self.toolhead.set_position(haltpos) # Signal homing/probing move complete try: self.printer.send_event("homing:homing_move_end", self) diff --git a/klippy/extras/hx71x.py b/klippy/extras/hx71x.py new file mode 100644 index 000000000000..5c59ed0b4fdc --- /dev/null +++ b/klippy/extras/hx71x.py @@ -0,0 +1,168 @@ +# HX711/HX717 Support +# +# Copyright (C) 2024 Gareth Farrington +# +# This file may be distributed under the terms of the GNU GPLv3 license. +import logging +from . import bulk_sensor + +# +# Constants +# +UPDATE_INTERVAL = 0.10 +SAMPLE_ERROR_DESYNC = -0x80000000 +SAMPLE_ERROR_LONG_READ = 0x40000000 + +# Implementation of HX711 and HX717 +class HX71xBase: + def __init__(self, config, sensor_type, + sample_rate_options, default_sample_rate, + gain_options, default_gain): + self.printer = printer = config.get_printer() + self.name = config.get_name().split()[-1] + self.last_error_count = 0 + self.consecutive_fails = 0 + self.sensor_type = sensor_type + # Chip options + dout_pin_name = config.get('dout_pin') + sclk_pin_name = config.get('sclk_pin') + ppins = printer.lookup_object('pins') + dout_ppin = ppins.lookup_pin(dout_pin_name) + sclk_ppin = ppins.lookup_pin(sclk_pin_name) + self.mcu = mcu = dout_ppin['chip'] + self.oid = mcu.create_oid() + if sclk_ppin['chip'] is not mcu: + raise config.error("%s config error: All pins must be " + "connected to the same MCU" % (self.name,)) + self.dout_pin = dout_ppin['pin'] + self.sclk_pin = sclk_ppin['pin'] + # Samples per second choices + self.sps = config.getchoice('sample_rate', sample_rate_options, + default=default_sample_rate) + # gain/channel choices + self.gain_channel = int(config.getchoice('gain', gain_options, + default=default_gain)) + ## Bulk Sensor Setup + self.bulk_queue = bulk_sensor.BulkDataQueue(mcu, oid=self.oid) + # Clock tracking + chip_smooth = self.sps * UPDATE_INTERVAL * 2 + self.ffreader = bulk_sensor.FixedFreqReader(mcu, chip_smooth, " 0: + logging.error("%s: Forced sensor restart due to error", self.name) + self._finish_measurements() + self._start_measurements() + elif overflows > 0: + self.consecutive_fails += 1 + if self.consecutive_fails > 4: + logging.error("%s: Forced sensor restart due to overflows", + self.name) + self._finish_measurements() + self._start_measurements() + else: + self.consecutive_fails = 0 + return {'data': samples, 'errors': self.last_error_count, + 'overflows': self.ffreader.get_last_overflows()} + + +def HX711(config): + return HX71xBase(config, "hx711", + # HX711 sps options + {80: 80, 10: 10}, 80, + # HX711 gain/channel options + {'A-128': 1, 'B-32': 2, 'A-64': 3}, 'A-128') + + +def HX717(config): + return HX71xBase(config, "hx717", + # HX717 sps options + {320: 320, 80: 80, 20: 20, 10: 10}, 320, + # HX717 gain/channel options + {'A-128': 1, 'B-64': 2, 'A-64': 3, + 'B-8': 4}, 'A-128') + + +HX71X_SENSOR_TYPES = { + "hx711": HX711, + "hx717": HX717 +} diff --git a/klippy/extras/led.py b/klippy/extras/led.py index 2396a79e7d06..22b51e8e6117 100644 --- a/klippy/extras/led.py +++ b/klippy/extras/led.py @@ -1,13 +1,10 @@ # Support for PWM driven LEDs # -# Copyright (C) 2019-2022 Kevin O'Connor +# Copyright (C) 2019-2024 Kevin O'Connor # # This file may be distributed under the terms of the GNU GPLv3 license. -import logging, ast -from .display import display - -# Time between each led template update -RENDER_TIME = 0.500 +import logging +from . import output_pin # Helper code for common LED initialization and control class LEDHelper: @@ -22,14 +19,22 @@ def __init__(self, config, update_func, led_count=1): blue = config.getfloat('initial_BLUE', 0., minval=0., maxval=1.) white = config.getfloat('initial_WHITE', 0., minval=0., maxval=1.) self.led_state = [(red, green, blue, white)] * led_count + # Support setting an led template + self.template_eval = output_pin.lookup_template_eval(config) + self.tcallbacks = [(lambda text, s=self, index=i: + s._template_update(index, text)) + for i in range(led_count)] # Register commands name = config.get_name().split()[-1] gcode = self.printer.lookup_object('gcode') gcode.register_mux_command("SET_LED", "LED", name, self.cmd_SET_LED, desc=self.cmd_SET_LED_help) - def get_led_count(self): - return self.led_count - def set_color(self, index, color): + gcode.register_mux_command("SET_LED_TEMPLATE", "LED", name, + self.cmd_SET_LED_TEMPLATE, + desc=self.cmd_SET_LED_TEMPLATE_help) + def get_status(self, eventtime=None): + return {'color_data': self.led_state} + def _set_color(self, index, color): if index is None: new_led_state = [color] * self.led_count if self.led_state == new_led_state: @@ -41,7 +46,17 @@ def set_color(self, index, color): new_led_state[index - 1] = color self.led_state = new_led_state self.need_transmit = True - def check_transmit(self, print_time): + def _template_update(self, index, text): + try: + parts = [max(0., min(1., float(f))) + for f in text.split(',', 4)] + except ValueError as e: + logging.exception("led template render error") + parts = [] + if len(parts) < 4: + parts += [0.] * (4 - len(parts)) + self._set_color(index, tuple(parts)) + def _check_transmit(self, print_time=None): if not self.need_transmit: return self.need_transmit = False @@ -62,9 +77,9 @@ def cmd_SET_LED(self, gcmd): color = (red, green, blue, white) # Update and transmit data def lookahead_bgfunc(print_time): - self.set_color(index, color) + self._set_color(index, color) if transmit: - self.check_transmit(print_time) + self._check_transmit(print_time) if sync: #Sync LED Update with print time and send toolhead = self.printer.lookup_object('toolhead') @@ -72,112 +87,15 @@ def lookahead_bgfunc(print_time): else: #Send update now (so as not to wake toolhead and reset idle_timeout) lookahead_bgfunc(None) - def get_status(self, eventtime=None): - return {'color_data': self.led_state} - -# Main LED tracking code -class PrinterLED: - def __init__(self, config): - self.printer = config.get_printer() - self.led_helpers = {} - self.active_templates = {} - self.render_timer = None - # Load templates - dtemplates = display.lookup_display_templates(config) - self.templates = dtemplates.get_display_templates() - gcode_macro = self.printer.lookup_object("gcode_macro") - self.create_template_context = gcode_macro.create_template_context - # Register handlers - gcode = self.printer.lookup_object('gcode') - gcode.register_command("SET_LED_TEMPLATE", self.cmd_SET_LED_TEMPLATE, - desc=self.cmd_SET_LED_TEMPLATE_help) - def setup_helper(self, config, update_func, led_count=1): - led_helper = LEDHelper(config, update_func, led_count) - name = config.get_name().split()[-1] - self.led_helpers[name] = led_helper - return led_helper - def _activate_timer(self): - if self.render_timer is not None or not self.active_templates: - return - reactor = self.printer.get_reactor() - self.render_timer = reactor.register_timer(self._render, reactor.NOW) - def _activate_template(self, led_helper, index, template, lparams): - key = (led_helper, index) - if template is not None: - uid = (template,) + tuple(sorted(lparams.items())) - self.active_templates[key] = (uid, template, lparams) - return - if key in self.active_templates: - del self.active_templates[key] - def _render(self, eventtime): - if not self.active_templates: - # Nothing to do - unregister timer - reactor = self.printer.get_reactor() - reactor.register_timer(self.render_timer) - self.render_timer = None - return reactor.NEVER - # Setup gcode_macro template context - context = self.create_template_context(eventtime) - def render(name, **kwargs): - return self.templates[name].render(context, **kwargs) - context['render'] = render - # Render all templates - need_transmit = {} - rendered = {} - template_info = self.active_templates.items() - for (led_helper, index), (uid, template, lparams) in template_info: - color = rendered.get(uid) - if color is None: - try: - text = template.render(context, **lparams) - parts = [max(0., min(1., float(f))) - for f in text.split(',', 4)] - except Exception as e: - logging.exception("led template render error") - parts = [] - if len(parts) < 4: - parts += [0.] * (4 - len(parts)) - rendered[uid] = color = tuple(parts) - need_transmit[led_helper] = 1 - led_helper.set_color(index, color) - context.clear() # Remove circular references for better gc - # Transmit pending changes - for led_helper in need_transmit.keys(): - led_helper.check_transmit(None) - return eventtime + RENDER_TIME cmd_SET_LED_TEMPLATE_help = "Assign a display_template to an LED" def cmd_SET_LED_TEMPLATE(self, gcmd): - led_name = gcmd.get("LED") - led_helper = self.led_helpers.get(led_name) - if led_helper is None: - raise gcmd.error("Unknown LED '%s'" % (led_name,)) - led_count = led_helper.get_led_count() - index = gcmd.get_int("INDEX", None, minval=1, maxval=led_count) - template = None - lparams = {} - tpl_name = gcmd.get("TEMPLATE") - if tpl_name: - template = self.templates.get(tpl_name) - if template is None: - raise gcmd.error("Unknown display_template '%s'" % (tpl_name,)) - tparams = template.get_params() - for p, v in gcmd.get_command_parameters().items(): - if not p.startswith("PARAM_"): - continue - p = p.lower() - if p not in tparams: - raise gcmd.error("Invalid display_template parameter: %s" - % (p,)) - try: - lparams[p] = ast.literal_eval(v) - except ValueError as e: - raise gcmd.error("Unable to parse '%s' as a literal" % (v,)) + index = gcmd.get_int("INDEX", None, minval=1, maxval=self.led_count) + set_template = self.template_eval.set_template if index is not None: - self._activate_template(led_helper, index, template, lparams) + set_template(gcmd, self.tcallbacks[index-1], self._check_transmit) else: - for i in range(led_count): - self._activate_template(led_helper, i+1, template, lparams) - self._activate_timer() + for i in range(self.led_count): + set_template(gcmd, self.tcallbacks[i], self._check_transmit) PIN_MIN_TIME = 0.100 MAX_SCHEDULE_TIME = 5.0 @@ -205,8 +123,7 @@ def __init__(self, config): % (config.get_name(),)) self.last_print_time = 0. # Initialize color data - pled = printer.load_object(config, "led") - self.led_helper = pled.setup_helper(config, self.update_leds, 1) + self.led_helper = LEDHelper(config, self.update_leds, 1) self.prev_color = color = self.led_helper.get_status()['color_data'][0] for idx, mcu_pin in self.pins: mcu_pin.setup_start_value(color[idx], 0.) @@ -225,8 +142,5 @@ def update_leds(self, led_state, print_time): def get_status(self, eventtime=None): return self.led_helper.get_status(eventtime) -def load_config(config): - return PrinterLED(config) - def load_config_prefix(config): return PrinterPWMLED(config) diff --git a/klippy/extras/lis2dw.py b/klippy/extras/lis2dw.py index 45c12ea1aba1..e71f99f89353 100644 --- a/klippy/extras/lis2dw.py +++ b/klippy/extras/lis2dw.py @@ -12,6 +12,8 @@ REG_LIS2DW_CTRL_REG1_ADDR = 0x20 REG_LIS2DW_CTRL_REG2_ADDR = 0x21 REG_LIS2DW_CTRL_REG3_ADDR = 0x22 +REG_LIS2DW_CTRL_REG4_ADDR = 0x23 +REG_LIS2DW_CTRL_REG5_ADDR = 0x24 REG_LIS2DW_CTRL_REG6_ADDR = 0x25 REG_LIS2DW_STATUS_REG_ADDR = 0x27 REG_LIS2DW_OUT_XL_ADDR = 0x28 @@ -26,26 +28,57 @@ # REG_MOD_MULTI = 0x40 LIS2DW_DEV_ID = 0x44 +LIS3DH_DEV_ID = 0x33 +LIS_I2C_ADDR = 0x19 + +# Right shift for left justified registers. FREEFALL_ACCEL = 9.80665 -SCALE = FREEFALL_ACCEL * 1.952 / 4 +LIS2DW_SCALE = FREEFALL_ACCEL * 1.952 / 4 +LIS3DH_SCALE = FREEFALL_ACCEL * 3.906 / 16 BATCH_UPDATES = 0.100 +# "Enums" that should be compatible with all python versions + +LIS2DW_TYPE = 'LIS2DW' +LIS3DH_TYPE = 'LIS3DH' + +SPI_SERIAL_TYPE = 'spi' +I2C_SERIAL_TYPE = 'i2c' + # Printer class that controls LIS2DW chip class LIS2DW: - def __init__(self, config): + def __init__(self, config, lis_type): self.printer = config.get_printer() adxl345.AccelCommandHelper(config, self) - self.axes_map = adxl345.read_axes_map(config, SCALE, SCALE, SCALE) - self.data_rate = 1600 + self.lis_type = lis_type + if self.lis_type == LIS2DW_TYPE: + self.axes_map = adxl345.read_axes_map(config, LIS2DW_SCALE, + LIS2DW_SCALE, LIS2DW_SCALE) + self.data_rate = 1600 + else: + self.axes_map = adxl345.read_axes_map(config, LIS3DH_SCALE, + LIS3DH_SCALE, LIS3DH_SCALE) + self.data_rate = 1344 + # Check for spi or i2c + if config.get('cs_pin', None) is not None: + self.bus_type = SPI_SERIAL_TYPE + else: + self.bus_type = I2C_SERIAL_TYPE # Setup mcu sensor_lis2dw bulk query code - self.spi = bus.MCU_SPI_from_config(config, 3, default_speed=5000000) - self.mcu = mcu = self.spi.get_mcu() + if self.bus_type == SPI_SERIAL_TYPE: + self.bus = bus.MCU_SPI_from_config(config, + 3, default_speed=5000000) + else: + self.bus = bus.MCU_I2C_from_config(config, + default_addr=LIS_I2C_ADDR, default_speed=400000) + self.mcu = mcu = self.bus.get_mcu() self.oid = oid = mcu.create_oid() self.query_lis2dw_cmd = None - mcu.add_config_cmd("config_lis2dw oid=%d spi_oid=%d" - % (oid, self.spi.get_oid())) + mcu.add_config_cmd("config_lis2dw oid=%d bus_oid=%d bus_oid_type=%s " + "lis_chip_type=%s" % (oid, self.bus.get_oid(), + self.bus_type, self.lis_type)) mcu.add_config_cmd("query_lis2dw oid=%d rest_ticks=0" % (oid,), on_restart=True) mcu.register_config_callback(self._build_config) @@ -63,17 +96,23 @@ def __init__(self, config): self.name, {'header': hdr}) def _build_config(self): - cmdqueue = self.spi.get_command_queue() + cmdqueue = self.bus.get_command_queue() self.query_lis2dw_cmd = self.mcu.lookup_command( "query_lis2dw oid=%c rest_ticks=%u", cq=cmdqueue) self.ffreader.setup_query_command("query_lis2dw_status oid=%c", oid=self.oid, cq=cmdqueue) def read_reg(self, reg): - params = self.spi.spi_transfer([reg | REG_MOD_READ, 0x00]) - response = bytearray(params['response']) - return response[1] + if self.bus_type == SPI_SERIAL_TYPE: + params = self.bus.spi_transfer([reg | REG_MOD_READ, 0x00]) + response = bytearray(params['response']) + return response[1] + params = self.bus.i2c_read([reg], 1) + return bytearray(params['response'])[0] def set_reg(self, reg, val, minclock=0): - self.spi.spi_send([reg, val & 0xFF], minclock=minclock) + if self.bus_type == SPI_SERIAL_TYPE: + self.bus.spi_send([reg, val & 0xFF], minclock=minclock) + else: + self.bus.i2c_write([reg, val & 0xFF], minclock=minclock) stored_val = self.read_reg(reg) if stored_val != val: raise self.printer.command_error( @@ -102,26 +141,48 @@ def _start_measurements(self): # noise or wrong signal as a correctly initialized device dev_id = self.read_reg(REG_LIS2DW_WHO_AM_I_ADDR) logging.info("lis2dw_dev_id: %x", dev_id) - if dev_id != LIS2DW_DEV_ID: - raise self.printer.command_error( - "Invalid lis2dw id (got %x vs %x).\n" - "This is generally indicative of connection problems\n" - "(e.g. faulty wiring) or a faulty lis2dw chip." - % (dev_id, LIS2DW_DEV_ID)) - # Setup chip in requested query rate - # ODR/2, +-16g, low-pass filter, Low-noise abled - self.set_reg(REG_LIS2DW_CTRL_REG6_ADDR, 0x34) - # Continuous mode: If the FIFO is full - # the new sample overwrites the older sample. - self.set_reg(REG_LIS2DW_FIFO_CTRL, 0xC0) - # High-Performance / Low-Power mode 1600/200 Hz - # High-Performance Mode (14-bit resolution) - self.set_reg(REG_LIS2DW_CTRL_REG1_ADDR, 0x94) - + if self.lis_type == LIS2DW_TYPE: + if dev_id != LIS2DW_DEV_ID: + raise self.printer.command_error( + "Invalid lis2dw id (got %x vs %x).\n" + "This is generally indicative of connection problems\n" + "(e.g. faulty wiring) or a faulty lis2dw chip." + % (dev_id, LIS2DW_DEV_ID)) + # Setup chip in requested query rate + # ODR/2, +-16g, low-pass filter, Low-noise abled + self.set_reg(REG_LIS2DW_CTRL_REG6_ADDR, 0x34) + # Continuous mode: If the FIFO is full + # the new sample overwrites the older sample. + self.set_reg(REG_LIS2DW_FIFO_CTRL, 0xC0) + # High-Performance / Low-Power mode 1600/200 Hz + # High-Performance Mode (14-bit resolution) + self.set_reg(REG_LIS2DW_CTRL_REG1_ADDR, 0x94) + else: + if dev_id != LIS3DH_DEV_ID: + raise self.printer.command_error( + "Invalid lis3dh id (got %x vs %x).\n" + "This is generally indicative of connection problems\n" + "(e.g. faulty wiring) or a faulty lis3dh chip." + % (dev_id, LIS3DH_DEV_ID)) + # High Resolution / Low Power mode 1344/5376 Hz + # High Resolution mode (12-bit resolution) + # Enable X Y Z axes + self.set_reg(REG_LIS2DW_CTRL_REG1_ADDR, 0x97) + # Disable all filtering + self.set_reg(REG_LIS2DW_CTRL_REG2_ADDR, 0) + # Set +-8g, High Resolution mode + self.set_reg(REG_LIS2DW_CTRL_REG4_ADDR, 0x28) + # Enable FIFO + self.set_reg(REG_LIS2DW_CTRL_REG5_ADDR, 0x40) + # Stream mode + self.set_reg(REG_LIS2DW_FIFO_CTRL, 0x80) # Start bulk reading rest_ticks = self.mcu.seconds_to_clock(4. / self.data_rate) self.query_lis2dw_cmd.send([self.oid, rest_ticks]) - self.set_reg(REG_LIS2DW_FIFO_CTRL, 0xC0) + if self.lis_type == LIS2DW_TYPE: + self.set_reg(REG_LIS2DW_FIFO_CTRL, 0xC0) + else: + self.set_reg(REG_LIS2DW_FIFO_CTRL, 0x80) logging.info("LIS2DW starting '%s' measurements", self.name) # Initialize clock tracking self.ffreader.note_start() @@ -142,7 +203,7 @@ def _process_batch(self, eventtime): 'overflows': self.ffreader.get_last_overflows()} def load_config(config): - return LIS2DW(config) + return LIS2DW(config, LIS2DW_TYPE) def load_config_prefix(config): - return LIS2DW(config) + return LIS2DW(config, LIS2DW_TYPE) diff --git a/klippy/extras/lis3dh.py b/klippy/extras/lis3dh.py new file mode 100644 index 000000000000..b7e35186ad58 --- /dev/null +++ b/klippy/extras/lis3dh.py @@ -0,0 +1,12 @@ +# Support for reading acceleration data from an LIS3DH chip +# +# Copyright (C) 2024 Luke Vuksta +# +# This file may be distributed under the terms of the GNU GPLv3 license. +from . import lis2dw + +def load_config(config): + return lis2dw.LIS2DW(config, lis2dw.LIS3DH_TYPE) + +def load_config_prefix(config): + return lis2dw.LIS2DW(config, lis2dw.LIS3DH_TYPE) diff --git a/klippy/extras/load_cell.py b/klippy/extras/load_cell.py new file mode 100644 index 000000000000..14f3c2983f99 --- /dev/null +++ b/klippy/extras/load_cell.py @@ -0,0 +1,30 @@ +# Load Cell Implementation +# +# Copyright (C) 2024 Gareth Farrington +# +# This file may be distributed under the terms of the GNU GPLv3 license. +from . import hx71x +from . import ads1220 + +# Printer class that controls a load cell +class LoadCell: + def __init__(self, config, sensor): + self.printer = printer = config.get_printer() + self.sensor = sensor # must implement BulkAdcSensor + + def _on_sample(self, msg): + return True + + def get_sensor(self): + return self.sensor + +def load_config(config): + # Sensor types + sensors = {} + sensors.update(hx71x.HX71X_SENSOR_TYPES) + sensors.update(ads1220.ADS1220_SENSOR_TYPE) + sensor_class = config.getchoice('sensor_type', sensors) + return LoadCell(config, sensor_class(config)) + +def load_config_prefix(config): + return load_config(config) diff --git a/klippy/extras/neopixel.py b/klippy/extras/neopixel.py index b6daeb4d29e3..e72b8a91a188 100644 --- a/klippy/extras/neopixel.py +++ b/klippy/extras/neopixel.py @@ -4,6 +4,7 @@ # # This file may be distributed under the terms of the GNU GPLv3 license. import logging +from . import led BACKGROUND_PRIORITY_CLOCK = 0x7fffffff00000000 @@ -40,9 +41,7 @@ def __init__(self, config): if len(self.color_map) > MAX_MCU_SIZE: raise config.error("neopixel chain too long") # Initialize color data - pled = printer.load_object(config, "led") - self.led_helper = pled.setup_helper(config, self.update_leds, - chain_count) + self.led_helper = led.LEDHelper(config, self.update_leds, chain_count) self.color_data = bytearray(len(self.color_map)) self.update_color_data(self.led_helper.get_status()['color_data']) self.old_color_data = bytearray([d ^ 1 for d in self.color_data]) diff --git a/klippy/extras/output_pin.py b/klippy/extras/output_pin.py index ef094674c1c1..24d27a62de4d 100644 --- a/klippy/extras/output_pin.py +++ b/klippy/extras/output_pin.py @@ -3,9 +3,180 @@ # Copyright (C) 2017-2024 Kevin O'Connor # # This file may be distributed under the terms of the GNU GPLv3 license. +import logging, ast +from .display import display + + +###################################################################### +# G-Code request queuing helper +###################################################################### PIN_MIN_TIME = 0.100 -RESEND_HOST_TIME = 0.300 + PIN_MIN_TIME + +# Helper code to queue g-code requests +class GCodeRequestQueue: + def __init__(self, config, mcu, callback): + self.printer = printer = config.get_printer() + self.mcu = mcu + self.callback = callback + self.rqueue = [] + self.next_min_flush_time = 0. + self.toolhead = None + mcu.register_flush_callback(self._flush_notification) + printer.register_event_handler("klippy:connect", self._handle_connect) + def _handle_connect(self): + self.toolhead = self.printer.lookup_object('toolhead') + def _flush_notification(self, print_time, clock): + rqueue = self.rqueue + while rqueue: + next_time = max(rqueue[0][0], self.next_min_flush_time) + if next_time > print_time: + return + # Skip requests that have been overridden with a following request + pos = 0 + while pos + 1 < len(rqueue) and rqueue[pos + 1][0] <= next_time: + pos += 1 + req_pt, req_val = rqueue[pos] + # Invoke callback for the request + min_wait = 0. + ret = self.callback(next_time, req_val) + if ret is not None: + # Handle special cases + action, min_wait = ret + if action == "discard": + del rqueue[:pos+1] + continue + if action == "delay": + pos -= 1 + del rqueue[:pos+1] + self.next_min_flush_time = next_time + max(min_wait, PIN_MIN_TIME) + # Ensure following queue items are flushed + self.toolhead.note_mcu_movequeue_activity(self.next_min_flush_time) + def _queue_request(self, print_time, value): + self.rqueue.append((print_time, value)) + self.toolhead.note_mcu_movequeue_activity(print_time) + def queue_gcode_request(self, value): + self.toolhead.register_lookahead_callback( + (lambda pt: self._queue_request(pt, value))) + def send_async_request(self, value, print_time=None): + if print_time is None: + systime = self.printer.get_reactor().monotonic() + print_time = self.mcu.estimated_print_time(systime + PIN_MIN_TIME) + while 1: + next_time = max(print_time, self.next_min_flush_time) + # Invoke callback for the request + action, min_wait = "normal", 0. + ret = self.callback(next_time, value) + if ret is not None: + # Handle special cases + action, min_wait = ret + if action == "discard": + break + self.next_min_flush_time = next_time + max(min_wait, PIN_MIN_TIME) + if action != "delay": + break + + +###################################################################### +# Template evaluation helper +###################################################################### + +# Time between each template update +RENDER_TIME = 0.500 + +# Main template evaluation code +class PrinterTemplateEvaluator: + def __init__(self, config): + self.printer = config.get_printer() + self.active_templates = {} + self.render_timer = None + # Load templates + dtemplates = display.lookup_display_templates(config) + self.templates = dtemplates.get_display_templates() + gcode_macro = self.printer.load_object(config, "gcode_macro") + self.create_template_context = gcode_macro.create_template_context + def _activate_timer(self): + if self.render_timer is not None or not self.active_templates: + return + reactor = self.printer.get_reactor() + self.render_timer = reactor.register_timer(self._render, reactor.NOW) + def _activate_template(self, callback, template, lparams, flush_callback): + if template is not None: + uid = (template,) + tuple(sorted(lparams.items())) + self.active_templates[callback] = ( + uid, template, lparams, flush_callback) + return + if callback in self.active_templates: + del self.active_templates[callback] + def _render(self, eventtime): + if not self.active_templates: + # Nothing to do - unregister timer + reactor = self.printer.get_reactor() + reactor.unregister_timer(self.render_timer) + self.render_timer = None + return reactor.NEVER + # Setup gcode_macro template context + context = self.create_template_context(eventtime) + def render(name, **kwargs): + return self.templates[name].render(context, **kwargs) + context['render'] = render + # Render all templates + flush_callbacks = {} + rendered = {} + template_info = self.active_templates.items() + for callback, (uid, template, lparams, flush_callback) in template_info: + text = rendered.get(uid) + if text is None: + try: + text = template.render(context, **lparams) + except Exception as e: + logging.exception("display template render error") + text = "" + rendered[uid] = text + if flush_callback is not None: + flush_callbacks[flush_callback] = 1 + callback(text) + context.clear() # Remove circular references for better gc + # Invoke optional flush callbacks + for flush_callback in flush_callbacks.keys(): + flush_callback() + return eventtime + RENDER_TIME + def set_template(self, gcmd, callback, flush_callback=None): + template = None + lparams = {} + tpl_name = gcmd.get("TEMPLATE") + if tpl_name: + template = self.templates.get(tpl_name) + if template is None: + raise gcmd.error("Unknown display_template '%s'" % (tpl_name,)) + tparams = template.get_params() + for p, v in gcmd.get_command_parameters().items(): + if not p.startswith("PARAM_"): + continue + p = p.lower() + if p not in tparams: + raise gcmd.error("Invalid display_template parameter: %s" + % (p,)) + try: + lparams[p] = ast.literal_eval(v) + except ValueError as e: + raise gcmd.error("Unable to parse '%s' as a literal" % (v,)) + self._activate_template(callback, template, lparams, flush_callback) + self._activate_timer() + +def lookup_template_eval(config): + printer = config.get_printer() + te = printer.lookup_object("template_evaluator", None) + if te is None: + te = PrinterTemplateEvaluator(config) + printer.add_object("template_evaluator", te) + return te + + +###################################################################### +# Main output pin handling +###################################################################### + MAX_SCHEDULE_TIME = 5.0 class PrinterOutputPin: @@ -24,30 +195,18 @@ def __init__(self, config): else: self.mcu_pin = ppins.setup_pin('digital_out', config.get('pin')) self.scale = 1. - self.last_print_time = 0. - # Support mcu checking for maximum duration - self.reactor = self.printer.get_reactor() - self.resend_timer = None - self.resend_interval = 0. - max_mcu_duration = config.getfloat('maximum_mcu_duration', 0., - minval=0.500, - maxval=MAX_SCHEDULE_TIME) - self.mcu_pin.setup_max_duration(max_mcu_duration) - if max_mcu_duration: - config.deprecate('maximum_mcu_duration') - self.resend_interval = max_mcu_duration - RESEND_HOST_TIME + self.mcu_pin.setup_max_duration(0.) # Determine start and shutdown values - static_value = config.getfloat('static_value', None, - minval=0., maxval=self.scale) - if static_value is not None: - config.deprecate('static_value') - self.last_value = self.shutdown_value = static_value / self.scale - else: - self.last_value = config.getfloat( - 'value', 0., minval=0., maxval=self.scale) / self.scale - self.shutdown_value = config.getfloat( - 'shutdown_value', 0., minval=0., maxval=self.scale) / self.scale + self.last_value = config.getfloat( + 'value', 0., minval=0., maxval=self.scale) / self.scale + self.shutdown_value = config.getfloat( + 'shutdown_value', 0., minval=0., maxval=self.scale) / self.scale self.mcu_pin.setup_start_value(self.last_value, self.shutdown_value) + # Create gcode request queue + self.gcrq = GCodeRequestQueue(config, self.mcu_pin.get_mcu(), + self._set_pin) + # Template handling + self.template_eval = lookup_template_eval(config) # Register commands pin_name = config.get_name().split()[1] gcode = self.printer.lookup_object('gcode') @@ -56,45 +215,36 @@ def __init__(self, config): desc=self.cmd_SET_PIN_help) def get_status(self, eventtime): return {'value': self.last_value} - def _set_pin(self, print_time, value, is_resend=False): - if value == self.last_value and not is_resend: - return - print_time = max(print_time, self.last_print_time + PIN_MIN_TIME) + def _set_pin(self, print_time, value): + if value == self.last_value: + return "discard", 0. + self.last_value = value if self.is_pwm: self.mcu_pin.set_pwm(print_time, value) else: self.mcu_pin.set_digital(print_time, value) - self.last_value = value - self.last_print_time = print_time - if self.resend_interval and self.resend_timer is None: - self.resend_timer = self.reactor.register_timer( - self._resend_current_val, self.reactor.NOW) + def _template_update(self, text): + try: + value = float(text) + except ValueError as e: + logging.exception("output_pin template render error") + self.gcrq.send_async_request(value) cmd_SET_PIN_help = "Set the value of an output pin" def cmd_SET_PIN(self, gcmd): + value = gcmd.get_float('VALUE', None, minval=0., maxval=self.scale) + template = gcmd.get('TEMPLATE', None) + if (value is None) == (template is None): + raise gcmd.error("SET_PIN command must specify VALUE or TEMPLATE") + # Check for template setting + if template is not None: + self.template_eval.set_template(gcmd, self._template_update) + return # Read requested value - value = gcmd.get_float('VALUE', minval=0., maxval=self.scale) value /= self.scale if not self.is_pwm and value not in [0., 1.]: raise gcmd.error("Invalid pin value") - # Obtain print_time and apply requested settings - toolhead = self.printer.lookup_object('toolhead') - toolhead.register_lookahead_callback( - lambda print_time: self._set_pin(print_time, value)) - - def _resend_current_val(self, eventtime): - if self.last_value == self.shutdown_value: - self.reactor.unregister_timer(self.resend_timer) - self.resend_timer = None - return self.reactor.NEVER - - systime = self.reactor.monotonic() - print_time = self.mcu_pin.get_mcu().estimated_print_time(systime) - time_diff = (self.last_print_time + self.resend_interval) - print_time - if time_diff > 0.: - # Reschedule for resend time - return systime + time_diff - self._set_pin(print_time + PIN_MIN_TIME, self.last_value, True) - return systime + self.resend_interval + # Queue requested value + self.gcrq.queue_gcode_request(value) def load_config_prefix(config): return PrinterOutputPin(config) diff --git a/klippy/extras/pca9533.py b/klippy/extras/pca9533.py index f84f9a65ad37..a94e1334e056 100644 --- a/klippy/extras/pca9533.py +++ b/klippy/extras/pca9533.py @@ -4,7 +4,7 @@ # # This file may be distributed under the terms of the GNU GPLv3 license. import logging -from . import bus +from . import bus, led BACKGROUND_PRIORITY_CLOCK = 0x7fffffff00000000 @@ -16,8 +16,7 @@ class PCA9533: def __init__(self, config): self.printer = config.get_printer() self.i2c = bus.MCU_I2C_from_config(config, default_addr=98) - pled = self.printer.load_object(config, "led") - self.led_helper = pled.setup_helper(config, self.update_leds, 1) + self.led_helper = led.LEDHelper(config, self.update_leds, 1) self.i2c.i2c_write([PCA9533_PWM0, 85]) self.i2c.i2c_write([PCA9533_PWM1, 170]) self.update_leds(self.led_helper.get_status()['color_data'], None) diff --git a/klippy/extras/pca9632.py b/klippy/extras/pca9632.py index 00876dc18aca..8a3551cf242a 100644 --- a/klippy/extras/pca9632.py +++ b/klippy/extras/pca9632.py @@ -3,7 +3,7 @@ # Copyright (C) 2022 Ricardo Alcantara # # This file may be distributed under the terms of the GNU GPLv3 license. -from . import bus, mcp4018 +from . import bus, led, mcp4018 BACKGROUND_PRIORITY_CLOCK = 0x7fffffff00000000 @@ -34,8 +34,7 @@ def __init__(self, config): raise config.error("Invalid color_order '%s'" % (color_order,)) self.color_map = ["RGBW".index(c) for c in color_order] self.prev_regs = {} - pled = printer.load_object(config, "led") - self.led_helper = pled.setup_helper(config, self.update_leds, 1) + self.led_helper = led.LEDHelper(config, self.update_leds, 1) printer.register_event_handler("klippy:connect", self.handle_connect) def reg_write(self, reg, val, minclock=0): if self.prev_regs.get(reg) == val: diff --git a/klippy/extras/probe_eddy_current.py b/klippy/extras/probe_eddy_current.py index 345096e60b44..932d1bfa3fed 100644 --- a/klippy/extras/probe_eddy_current.py +++ b/klippy/extras/probe_eddy_current.py @@ -14,6 +14,7 @@ class EddyCalibration: def __init__(self, config): self.printer = config.get_printer() self.name = config.get_name() + self.drift_comp = DummyDriftCompensation() # Current calibration data self.cal_freqs = [] self.cal_zpos = [] @@ -37,8 +38,10 @@ def load_calibration(self, cal): self.cal_freqs = [c[0] for c in cal] self.cal_zpos = [c[1] for c in cal] def apply_calibration(self, samples): + cur_temp = self.drift_comp.get_temperature() for i, (samp_time, freq, dummy_z) in enumerate(samples): - pos = bisect.bisect(self.cal_freqs, freq) + adj_freq = self.drift_comp.adjust_freq(freq, cur_temp) + pos = bisect.bisect(self.cal_freqs, adj_freq) if pos >= len(self.cal_zpos): zpos = -OUT_OF_RANGE elif pos == 0: @@ -51,7 +54,7 @@ def apply_calibration(self, samples): prev_zpos = self.cal_zpos[pos - 1] gain = (this_zpos - prev_zpos) / (this_freq - prev_freq) offset = prev_zpos - prev_freq * gain - zpos = freq * gain + offset + zpos = adj_freq * gain + offset samples[i] = (samp_time, freq, round(zpos, 6)) def freq_to_height(self, freq): dummy_sample = [(0., freq, 0.)] @@ -71,7 +74,8 @@ def height_to_freq(self, height): prev_zpos = rev_zpos[pos - 1] gain = (this_freq - prev_freq) / (this_zpos - prev_zpos) offset = prev_freq - prev_zpos * gain - return height * gain + offset + freq = height * gain + offset + return self.drift_comp.unadjust_freq(freq) def do_calibration_moves(self, move_speed): toolhead = self.printer.lookup_object('toolhead') kin = toolhead.get_kinematics() @@ -86,6 +90,7 @@ def handle_batch(msg): return True self.printer.lookup_object(self.name).add_client(handle_batch) toolhead.dwell(1.) + self.drift_comp.note_z_calibration_start() # Move to each 40um position max_z = 4.0 samp_dist = 0.040 @@ -112,6 +117,7 @@ def handle_batch(msg): times.append((start_query_time, end_query_time, kin_pos[2])) toolhead.dwell(1.0) toolhead.wait_moves() + self.drift_comp.note_z_calibration_finish() # Finish data collection is_finished = True # Correlate query responses @@ -188,6 +194,8 @@ def cmd_EDDY_CALIBRATE(self, gcmd): # Start manual probe manual_probe.ManualProbeHelper(self.printer, gcmd, self.post_manual_probe) + def register_drift_compensation(self, comp): + self.drift_comp = comp # Tool to gather samples and convert them to probe positions class EddyGatherSamples: @@ -265,16 +273,18 @@ def _check_samples(self): freq = self._pull_freq(start_time, end_time) if pos_time is not None: toolhead_pos = self._lookup_toolhead_pos(pos_time) - self._probe_results.append((freq, toolhead_pos)) + sensor_z = None + if freq: + sensor_z = self._calibration.freq_to_height(freq) + self._probe_results.append((sensor_z, toolhead_pos)) self._probe_times.pop(0) def pull_probed(self): self._await_samples() results = [] - for freq, toolhead_pos in self._probe_results: - if not freq: + for sensor_z, toolhead_pos in self._probe_results: + if sensor_z is None: raise self._printer.command_error( "Unable to obtain probe_eddy_current sensor readings") - sensor_z = self._calibration.freq_to_height(freq) if sensor_z <= -OUT_OF_RANGE or sensor_z >= OUT_OF_RANGE: raise self._printer.command_error( "probe_eddy_current sensor not in valid range") @@ -435,6 +445,20 @@ def start_probe_session(self, gcmd): return EddyScanningProbe(self.printer, self.sensor_helper, self.calibration, z_offset, gcmd) return self.probe_session.start_probe_session(gcmd) + def register_drift_compensation(self, comp): + self.calibration.register_drift_compensation(comp) + +class DummyDriftCompensation: + def get_temperature(self): + return 0. + def note_z_calibration_start(self): + pass + def note_z_calibration_finish(self): + pass + def adjust_freq(self, freq, temp=None): + return freq + def unadjust_freq(self, freq, temp=None): + return freq def load_config_prefix(config): return PrinterEddyProbe(config) diff --git a/klippy/extras/resonance_tester.py b/klippy/extras/resonance_tester.py index fe8717d58545..e9d4e9d92c53 100644 --- a/klippy/extras/resonance_tester.py +++ b/klippy/extras/resonance_tester.py @@ -65,6 +65,8 @@ def prepare_test(self, gcmd): self.freq_start = gcmd.get_float("FREQ_START", self.min_freq, minval=1.) self.freq_end = gcmd.get_float("FREQ_END", self.max_freq, minval=self.freq_start, maxval=300.) + self.accel_per_hz = gcmd.get_float("ACCEL_PER_HZ", + self.accel_per_hz, above=0.) self.hz_per_sec = gcmd.get_float("HZ_PER_SEC", self.hz_per_sec, above=0., maxval=2.) def run_test(self, axis, gcmd): @@ -212,11 +214,7 @@ def _run_test(self, gcmd, axes, helper, raw_name_suffix=None, def _parse_chips(self, accel_chips): parsed_chips = [] for chip_name in accel_chips.split(','): - if "adxl345" in chip_name: - chip_lookup_name = chip_name.strip() - else: - chip_lookup_name = "adxl345 " + chip_name.strip(); - chip = self.printer.lookup_object(chip_lookup_name) + chip = self.printer.lookup_object(chip_name.strip()) parsed_chips.append(chip) return parsed_chips def _get_max_calibration_freq(self): diff --git a/klippy/extras/servo.py b/klippy/extras/servo.py index c05c9f819353..f1ce997638f5 100644 --- a/klippy/extras/servo.py +++ b/klippy/extras/servo.py @@ -1,11 +1,11 @@ # Support for servos # -# Copyright (C) 2017-2020 Kevin O'Connor +# Copyright (C) 2017-2024 Kevin O'Connor # # This file may be distributed under the terms of the GNU GPLv3 license. +from . import output_pin SERVO_SIGNAL_PERIOD = 0.020 -PIN_MIN_TIME = 0.100 class PrinterServo: def __init__(self, config): @@ -18,7 +18,7 @@ def __init__(self, config): self.max_angle = config.getfloat('maximum_servo_angle', 180.) self.angle_to_width = (self.max_width - self.min_width) / self.max_angle self.width_to_value = 1. / SERVO_SIGNAL_PERIOD - self.last_value = self.last_value_time = 0. + self.last_value = 0. initial_pwm = 0. iangle = config.getfloat('initial_angle', None, minval=0., maxval=360.) if iangle is not None: @@ -33,6 +33,9 @@ def __init__(self, config): self.mcu_servo.setup_max_duration(0.) self.mcu_servo.setup_cycle_time(SERVO_SIGNAL_PERIOD) self.mcu_servo.setup_start_value(initial_pwm, 0.) + # Create gcode request queue + self.gcrq = output_pin.GCodeRequestQueue( + config, self.mcu_servo.get_mcu(), self._set_pwm) # Register commands servo_name = config.get_name().split()[1] gcode = self.printer.lookup_object('gcode') @@ -43,11 +46,9 @@ def get_status(self, eventtime): return {'value': self.last_value} def _set_pwm(self, print_time, value): if value == self.last_value: - return - print_time = max(print_time, self.last_value_time + PIN_MIN_TIME) - self.mcu_servo.set_pwm(print_time, value) + return "discard", 0. self.last_value = value - self.last_value_time = print_time + self.mcu_servo.set_pwm(print_time, value) def _get_pwm_from_angle(self, angle): angle = max(0., min(self.max_angle, angle)) width = self.min_width + angle * self.angle_to_width @@ -58,13 +59,13 @@ def _get_pwm_from_pulse_width(self, width): return width * self.width_to_value cmd_SET_SERVO_help = "Set servo angle" def cmd_SET_SERVO(self, gcmd): - print_time = self.printer.lookup_object('toolhead').get_last_move_time() width = gcmd.get_float('WIDTH', None) if width is not None: - self._set_pwm(print_time, self._get_pwm_from_pulse_width(width)) + value = self._get_pwm_from_pulse_width(width) else: angle = gcmd.get_float('ANGLE') - self._set_pwm(print_time, self._get_pwm_from_angle(angle)) + value = self._get_pwm_from_angle(angle) + self.gcrq.queue_gcode_request(value) def load_config_prefix(config): return PrinterServo(config) diff --git a/klippy/extras/sx1509.py b/klippy/extras/sx1509.py index 3bfecb7831c3..070b913353d6 100644 --- a/klippy/extras/sx1509.py +++ b/klippy/extras/sx1509.py @@ -38,19 +38,17 @@ def __init__(self, config): REG_INPUT_DISABLE : 0, REG_ANALOG_DRIVER_ENABLE : 0} self.reg_i_on_dict = {reg : 0 for reg in REG_I_ON} def _build_config(self): - # Reset the chip + # Reset the chip, Default RegClock/RegMisc 0x0 self._mcu.add_config_cmd("i2c_write oid=%d data=%02x%02x" % ( self._oid, REG_RESET, 0x12)) self._mcu.add_config_cmd("i2c_write oid=%d data=%02x%02x" % ( self._oid, REG_RESET, 0x34)) # Enable Oscillator - self._mcu.add_config_cmd("i2c_modify_bits oid=%d reg=%02x" - " clear_set_bits=%02x%02x" % ( - self._oid, REG_CLOCK, 0, (1 << 6))) + self._mcu.add_config_cmd("i2c_write oid=%d data=%02x%02x" % ( + self._oid, REG_CLOCK, (1 << 6))) # Setup Clock Divider - self._mcu.add_config_cmd("i2c_modify_bits oid=%d reg=%02x" - " clear_set_bits=%02x%02x" % ( - self._oid, REG_MISC, 0, (1 << 4))) + self._mcu.add_config_cmd("i2c_write oid=%d data=%02x%02x" % ( + self._oid, REG_MISC, (1 << 4))) # Transfer all regs with their initial cached state for _reg, _data in self.reg_dict.items(): self._mcu.add_config_cmd("i2c_write oid=%d data=%02x%04x" % ( diff --git a/klippy/extras/temperature_fan.py b/klippy/extras/temperature_fan.py index aee94f281594..a9aa4d0bab52 100644 --- a/klippy/extras/temperature_fan.py +++ b/klippy/extras/temperature_fan.py @@ -46,7 +46,7 @@ def __init__(self, config): self.cmd_SET_TEMPERATURE_FAN_TARGET, desc=self.cmd_SET_TEMPERATURE_FAN_TARGET_help) - def set_speed(self, read_time, value): + def set_tf_speed(self, read_time, value): if value <= 0.: value = 0. elif value < self.min_speed: @@ -60,7 +60,7 @@ def set_speed(self, read_time, value): speed_time = read_time + self.speed_delay self.next_speed_time = speed_time + 0.75 * MAX_FAN_TIME self.last_speed_value = value - self.fan.set_speed(speed_time, value) + self.fan.set_speed(value, speed_time) def temperature_callback(self, read_time, temp): self.last_temp = temp self.control.temperature_callback(read_time, temp) @@ -128,10 +128,10 @@ def temperature_callback(self, read_time, temp): and temp <= target_temp-self.max_delta): self.heating = True if self.heating: - self.temperature_fan.set_speed(read_time, 0.) + self.temperature_fan.set_tf_speed(read_time, 0.) else: - self.temperature_fan.set_speed(read_time, - self.temperature_fan.get_max_speed()) + self.temperature_fan.set_tf_speed( + read_time, self.temperature_fan.get_max_speed()) ###################################################################### # Proportional Integral Derivative (PID) control algo @@ -171,7 +171,7 @@ def temperature_callback(self, read_time, temp): # Calculate output co = self.Kp*temp_err + self.Ki*temp_integ - self.Kd*temp_deriv bounded_co = max(0., min(self.temperature_fan.get_max_speed(), co)) - self.temperature_fan.set_speed( + self.temperature_fan.set_tf_speed( read_time, max(self.temperature_fan.get_min_speed(), self.temperature_fan.get_max_speed() - bounded_co)) # Store state for next measurement diff --git a/klippy/extras/temperature_mcu.py b/klippy/extras/temperature_mcu.py index be2cd145c455..6f3386a4ba74 100644 --- a/klippy/extras/temperature_mcu.py +++ b/klippy/extras/temperature_mcu.py @@ -66,7 +66,7 @@ def handle_mcu_identify(self): self.mcu_type = mcu.get_constants().get("MCU", "") # Run MCU specific configuration cfg_funcs = [ - ('rp2040', self.config_rp2040), + ('rp2', self.config_rp2040), ('sam3', self.config_sam3), ('sam4', self.config_sam4), ('same70', self.config_same70), ('samd21', self.config_samd21), ('samd51', self.config_samd51), ('same5', self.config_samd51), diff --git a/klippy/extras/temperature_probe.py b/klippy/extras/temperature_probe.py new file mode 100644 index 000000000000..05eac34ef984 --- /dev/null +++ b/klippy/extras/temperature_probe.py @@ -0,0 +1,721 @@ +# Probe temperature sensor and drift calibration +# +# Copyright (C) 2024 Eric Callahan +# +# This file may be distributed under the terms of the GNU GPLv3 license. +import logging +from . import manual_probe + +KELVIN_TO_CELSIUS = -273.15 + +###################################################################### +# Polynomial Helper Classes and Functions +###################################################################### + +def calc_determinant(matrix): + m = matrix + aei = m[0][0] * m[1][1] * m[2][2] + bfg = m[1][0] * m[2][1] * m[0][2] + cdh = m[2][0] * m[0][1] * m[1][2] + ceg = m[2][0] * m[1][1] * m[0][2] + bdi = m[1][0] * m[0][1] * m[2][2] + afh = m[0][0] * m[2][1] * m[1][2] + return aei + bfg + cdh - ceg - bdi - afh + +class Polynomial2d: + def __init__(self, a, b, c): + self.a = a + self.b = b + self.c = c + + def __call__(self, xval): + return self.c * xval * xval + self.b * xval + self.a + + def get_coefs(self): + return (self.a, self.b, self.c) + + def __str__(self): + return "%f, %f, %f" % (self.a, self.b, self.c) + + def __repr__(self): + parts = ["y(x) ="] + deg = 2 + for i, coef in enumerate((self.c, self.b, self.a)): + if round(coef, 8) == int(coef): + coef = int(coef) + if abs(coef) < 1e-10: + continue + cur_deg = deg - i + x_str = "x^%d" % (cur_deg,) if cur_deg > 1 else "x" * cur_deg + if len(parts) == 1: + parts.append("%f%s" % (coef, x_str)) + else: + sym = "-" if coef < 0 else "+" + parts.append("%s %f%s" % (sym, abs(coef), x_str)) + return " ".join(parts) + + @classmethod + def fit(cls, coords): + xlist = [c[0] for c in coords] + ylist = [c[1] for c in coords] + count = len(coords) + sum_x = sum(xlist) + sum_y = sum(ylist) + sum_x2 = sum([x**2 for x in xlist]) + sum_x3 = sum([x**3 for x in xlist]) + sum_x4 = sum([x**4 for x in xlist]) + sum_xy = sum([x * y for x, y in coords]) + sum_x2y = sum([y*x**2 for x, y in coords]) + vector_b = [sum_y, sum_xy, sum_x2y] + m = [ + [count, sum_x, sum_x2], + [sum_x, sum_x2, sum_x3], + [sum_x2, sum_x3, sum_x4] + ] + m0 = [vector_b, m[1], m[2]] + m1 = [m[0], vector_b, m[2]] + m2 = [m[0], m[1], vector_b] + det_m = calc_determinant(m) + a0 = calc_determinant(m0) / det_m + a1 = calc_determinant(m1) / det_m + a2 = calc_determinant(m2) / det_m + return cls(a0, a1, a2) + +class TemperatureProbe: + def __init__(self, config): + self.name = config.get_name() + self.printer = config.get_printer() + self.gcode = self.printer.lookup_object("gcode") + self.speed = config.getfloat("speed", None, above=0.) + self.horizontal_move_z = config.getfloat( + "horizontal_move_z", 2., above=0. + ) + self.resting_z = config.getfloat("resting_z", .4, above=0.) + self.cal_pos = config.getfloatlist( + "calibration_position", None, count=3 + ) + self.cal_bed_temp = config.getfloat( + "calibration_bed_temp", None, above=50. + ) + self.cal_extruder_temp = config.getfloat( + "calibration_extruder_temp", None, above=50. + ) + self.cal_extruder_z = config.getfloat( + "extruder_heating_z", 50., above=0. + ) + # Setup temperature sensor + smooth_time = config.getfloat("smooth_time", 2., above=0.) + self.inv_smooth_time = 1. / smooth_time + self.min_temp = config.getfloat( + "min_temp", KELVIN_TO_CELSIUS, minval=KELVIN_TO_CELSIUS + ) + self.max_temp = config.getfloat( + "max_temp", 99999999.9, above=self.min_temp + ) + pheaters = self.printer.load_object(config, "heaters") + self.sensor = pheaters.setup_sensor(config) + self.sensor.setup_minmax(self.min_temp, self.max_temp) + self.sensor.setup_callback(self._temp_callback) + pheaters.register_sensor(config, self) + self.last_temp_read_time = 0. + self.last_measurement = (0., 99999999., 0.,) + # Calibration State + self.cal_helper = None + self.next_auto_temp = 99999999. + self.target_temp = 0 + self.expected_count = 0 + self.sample_count = 0 + self.in_calibration = False + self.step = 2. + self.last_zero_pos = None + self.total_expansion = 0 + self.start_pos = [] + + # Register GCode Commands + pname = self.name.split(maxsplit=1)[-1] + self.gcode.register_mux_command( + "TEMPERATURE_PROBE_CALIBRATE", "PROBE", pname, + self.cmd_TEMPERATURE_PROBE_CALIBRATE, + desc=self.cmd_TEMPERATURE_PROBE_CALIBRATE_help + ) + + self.gcode.register_mux_command( + "TEMPERATURE_PROBE_ENABLE", "PROBE", pname, + self.cmd_TEMPERATURE_PROBE_ENABLE, + desc=self.cmd_TEMPERATURE_PROBE_ENABLE_help + ) + + # Register Drift Compensation Helper with probe + full_probe_name = "probe_eddy_current %s" % (pname,) + if config.has_section(full_probe_name): + pprobe = self.printer.load_object(config, full_probe_name) + self.cal_helper = EddyDriftCompensation(config, self) + pprobe.register_drift_compensation(self.cal_helper) + logging.info( + "%s: registered drift compensation with probe [%s]" + % (self.name, full_probe_name) + ) + else: + logging.info( + "%s: No probe named %s configured, thermal drift compensation " + "disabled." % (self.name, pname) + ) + + def _temp_callback(self, read_time, temp): + smoothed_temp, measured_min, measured_max = self.last_measurement + time_diff = read_time - self.last_temp_read_time + self.last_temp_read_time = read_time + temp_diff = temp - smoothed_temp + adj_time = min(time_diff * self.inv_smooth_time, 1.) + smoothed_temp += temp_diff * adj_time + measured_min = min(measured_min, smoothed_temp) + measured_max = max(measured_max, smoothed_temp) + self.last_measurement = (smoothed_temp, measured_min, measured_max) + if self.in_calibration and smoothed_temp >= self.next_auto_temp: + self.printer.get_reactor().register_async_callback( + self._check_kick_next + ) + + def _check_kick_next(self, eventtime): + smoothed_temp = self.last_measurement[0] + if self.in_calibration and smoothed_temp >= self.next_auto_temp: + self.next_auto_temp = 99999999. + self.gcode.run_script("TEMPERATURE_PROBE_NEXT") + + def get_temp(self, eventtime=None): + return self.last_measurement[0], self.target_temp + + def _collect_sample(self, kin_pos, tool_zero_z): + probe = self._get_probe() + x_offset, y_offset, _ = probe.get_offsets() + speeds = self._get_speeds() + lift_speed, _, move_speed = speeds + toolhead = self.printer.lookup_object("toolhead") + cur_pos = toolhead.get_position() + # Move to probe to sample collection position + cur_pos[2] += self.horizontal_move_z + toolhead.manual_move(cur_pos, lift_speed) + cur_pos[0] -= x_offset + cur_pos[1] -= y_offset + toolhead.manual_move(cur_pos, move_speed) + return self.cal_helper.collect_sample(kin_pos, tool_zero_z, speeds) + + def _prepare_next_sample(self, last_temp, tool_zero_z): + # Register our own abort command now that the manual + # probe has finished and unregistered + self.gcode.register_command( + "ABORT", self.cmd_TEMPERATURE_PROBE_ABORT, + desc=self.cmd_TEMPERATURE_PROBE_ABORT_help + ) + probe_speed = self._get_speeds()[1] + # Move tool down to the resting position + toolhead = self.printer.lookup_object("toolhead") + cur_pos = toolhead.get_position() + cur_pos[2] = tool_zero_z + self.resting_z + toolhead.manual_move(cur_pos, probe_speed) + cnt, exp_cnt = self.sample_count, self.expected_count + self.next_auto_temp = last_temp + self.step + self.gcode.respond_info( + "%s: collected sample %d/%d at temp %.2fC, next sample scheduled " + "at temp %.2fC" + % (self.name, cnt, exp_cnt, last_temp, self.next_auto_temp) + ) + + def _manual_probe_finalize(self, kin_pos): + if kin_pos is None: + # Calibration aborted + self._finalize_drift_cal(False) + return + if self.last_zero_pos is not None: + z_diff = self.last_zero_pos[2] - kin_pos[2] + self.total_expansion += z_diff + logging.info( + "Estimated Total Thermal Expansion: %.6f" + % (self.total_expansion,) + ) + self.last_zero_pos = kin_pos + toolhead = self.printer.lookup_object("toolhead") + tool_zero_z = toolhead.get_position()[2] + try: + last_temp = self._collect_sample(kin_pos, tool_zero_z) + except Exception: + self._finalize_drift_cal(False) + raise + self.sample_count += 1 + if last_temp >= self.target_temp: + # Calibration Done + self._finalize_drift_cal(True) + else: + try: + self._prepare_next_sample(last_temp, tool_zero_z) + if self.sample_count == 1: + self._set_bed_temp(self.cal_bed_temp) + except Exception: + self._finalize_drift_cal(False) + raise + + def _finalize_drift_cal(self, success, msg=None): + self.next_auto_temp = 99999999. + self.target_temp = 0 + self.expected_count = 0 + self.sample_count = 0 + self.step = 2. + self.in_calibration = False + self.last_zero_pos = None + self.total_expansion = 0 + self.start_pos = [] + # Unregister Temporary Commands + self.gcode.register_command("ABORT", None) + self.gcode.register_command("TEMPERATURE_PROBE_NEXT", None) + self.gcode.register_command("TEMPERATURE_PROBE_COMPLETE", None) + # Turn off heaters + self._set_extruder_temp(0) + self._set_bed_temp(0) + try: + self.cal_helper.finish_calibration(success) + except self.gcode.error as e: + success = False + msg = str(e) + if not success: + msg = msg or "%s: calibration aborted" % (self.name,) + self.gcode.respond_info(msg) + + def _get_probe(self): + probe = self.printer.lookup_object("probe") + if probe is None: + raise self.gcode.error("No probe configured") + return probe + + def _set_extruder_temp(self, temp, wait=False): + if self.cal_extruder_temp is None: + # Extruder temperature not configured + return + toolhead = self.printer.lookup_object("toolhead") + extr_name = toolhead.get_extruder().get_name() + self.gcode.run_script_from_command( + "SET_HEATER_TEMPERATURE HEATER=%s TARGET=%f" + % (extr_name, temp) + ) + if wait: + self.gcode.run_script_from_command( + "TEMPERATURE_WAIT SENSOR=%s MINIMUM=%f" + % (extr_name, temp) + ) + def _set_bed_temp(self, temp): + if self.cal_bed_temp is None: + # Bed temperature not configured + return + self.gcode.run_script_from_command( + "SET_HEATER_TEMPERATURE HEATER=heater_bed TARGET=%f" + % (temp,) + ) + + def _check_homed(self): + toolhead = self.printer.lookup_object("toolhead") + reactor = self.printer.get_reactor() + status = toolhead.get_status(reactor.monotonic()) + h_axes = status["homed_axes"] + for axis in "xyz": + if axis not in h_axes: + raise self.gcode.error( + "Printer must be homed before calibration" + ) + + def _move_to_start(self): + toolhead = self.printer.lookup_object("toolhead") + cur_pos = toolhead.get_position() + move_speed = self._get_speeds()[2] + if self.cal_pos is not None: + if self.cal_extruder_temp is not None: + # Move to extruder heating z position + cur_pos[2] = self.cal_extruder_z + toolhead.manual_move(cur_pos, move_speed) + toolhead.manual_move(self.cal_pos[:2], move_speed) + self._set_extruder_temp(self.cal_extruder_temp, True) + toolhead.manual_move(self.cal_pos, move_speed) + elif self.cal_extruder_temp is not None: + cur_pos[2] = self.cal_extruder_z + toolhead.manual_move(cur_pos, move_speed) + self._set_extruder_temp(self.cal_extruder_temp, True) + + def _get_speeds(self): + pparams = self._get_probe().get_probe_params() + probe_speed = pparams["probe_speed"] + lift_speed = pparams["lift_speed"] + move_speed = self.speed or max(probe_speed, lift_speed) + return lift_speed, probe_speed, move_speed + + cmd_TEMPERATURE_PROBE_CALIBRATE_help = ( + "Calibrate probe temperature drift compensation" + ) + def cmd_TEMPERATURE_PROBE_CALIBRATE(self, gcmd): + if self.cal_helper is None: + raise gcmd.error( + "No calibration helper registered for [%s]" + % (self.name,) + ) + self._check_homed() + probe = self._get_probe() + probe_name = probe.get_status(None)["name"] + short_name = probe_name.split(maxsplit=1)[-1] + if short_name != self.name.split(maxsplit=1)[-1]: + raise self.gcode.error( + "[%s] not linked to registered probe [%s]." + % (self.name, probe_name) + ) + manual_probe.verify_no_manual_probe(self.printer) + if self.in_calibration: + raise gcmd.error( + "Already in probe drift calibration. Use " + "TEMPERATURE_PROBE_COMPLETE or ABORT to exit." + ) + cur_temp = self.last_measurement[0] + target_temp = gcmd.get_float("TARGET", above=cur_temp) + step = gcmd.get_float("STEP", 2., minval=1.0) + expected_count = int( + (target_temp - cur_temp) / step + .5 + ) + if expected_count < 3: + raise gcmd.error( + "Invalid STEP and/or TARGET parameters resulted " + "in too few expected samples: %d" + % (expected_count,) + ) + try: + self.gcode.register_command( + "TEMPERATURE_PROBE_NEXT", self.cmd_TEMPERATURE_PROBE_NEXT, + desc=self.cmd_TEMPERATURE_PROBE_NEXT_help + ) + self.gcode.register_command( + "TEMPERATURE_PROBE_COMPLETE", + self.cmd_TEMPERATURE_PROBE_COMPLETE, + desc=self.cmd_TEMPERATURE_PROBE_NEXT_help + ) + except self.printer.config_error: + raise gcmd.error( + "Auxiliary Probe Drift Commands already registered. Use " + "TEMPERATURE_PROBE_COMPLETE or ABORT to exit." + ) + self.in_calibration = True + self.cal_helper.start_calibration() + self.target_temp = target_temp + self.step = step + self.sample_count = 0 + self.expected_count = expected_count + # If configured move to heating position and turn on extruder + try: + self._move_to_start() + except self.printer.command_error: + self._finalize_drift_cal(False, "Error during initial move") + raise + # Caputure start position and begin initial probe + toolhead = self.printer.lookup_object("toolhead") + self.start_pos = toolhead.get_position()[:2] + manual_probe.ManualProbeHelper( + self.printer, gcmd, self._manual_probe_finalize + ) + + cmd_TEMPERATURE_PROBE_NEXT_help = "Sample next probe drift temperature" + def cmd_TEMPERATURE_PROBE_NEXT(self, gcmd): + manual_probe.verify_no_manual_probe(self.printer) + self.next_auto_temp = 99999999. + toolhead = self.printer.lookup_object("toolhead") + # Lift and Move to nozzle back to start position + curpos = toolhead.get_position() + start_z = curpos[2] + lift_speed, probe_speed, move_speed = self._get_speeds() + # Move nozzle to the manual probing position + curpos[2] += self.horizontal_move_z + toolhead.manual_move(curpos, lift_speed) + curpos[0] = self.start_pos[0] + curpos[1] = self.start_pos[1] + toolhead.manual_move(curpos, move_speed) + curpos[2] = start_z + toolhead.manual_move(curpos, probe_speed) + self.gcode.register_command("ABORT", None) + manual_probe.ManualProbeHelper( + self.printer, gcmd, self._manual_probe_finalize + ) + + cmd_TEMPERATURE_PROBE_COMPLETE_help = "Finish Probe Drift Calibration" + def cmd_TEMPERATURE_PROBE_COMPLETE(self, gcmd): + manual_probe.verify_no_manual_probe(self.printer) + self._finalize_drift_cal(self.sample_count >= 3) + + cmd_TEMPERATURE_PROBE_ABORT_help = "Abort Probe Drift Calibration" + def cmd_TEMPERATURE_PROBE_ABORT(self, gcmd): + self._finalize_drift_cal(False) + + cmd_TEMPERATURE_PROBE_ENABLE_help = ( + "Set adjustment factor applied to drift correction" + ) + def cmd_TEMPERATURE_PROBE_ENABLE(self, gcmd): + if self.cal_helper is not None: + self.cal_helper.set_enabled(gcmd) + + def is_in_calibration(self): + return self.in_calibration + + def get_status(self, eventtime=None): + smoothed_temp, measured_min, measured_max = self.last_measurement + dcomp_enabled = False + if self.cal_helper is not None: + dcomp_enabled = self.cal_helper.is_enabled() + return { + "temperature": smoothed_temp, + "measured_min_temp": round(measured_min, 2), + "measured_max_temp": round(measured_max, 2), + "in_calibration": self.in_calibration, + "estimated_expansion": self.total_expansion, + "compensation_enabled": dcomp_enabled + } + + def stats(self, eventtime): + return False, '%s: temp=%.1f' % (self.name, self.last_measurement[0]) + + +##################################################################### +# +# Eddy Current Probe Drift Compensation Helper +# +##################################################################### + +DRIFT_SAMPLE_COUNT = 9 + +class EddyDriftCompensation: + def __init__(self, config, sensor): + self.printer = config.get_printer() + self.temp_sensor = sensor + self.name = config.get_name() + self.cal_temp = config.getfloat("calibration_temp", 0.) + self.drift_calibration = None + self.calibration_samples = None + self.max_valid_temp = config.getfloat("max_validation_temp", 60.) + self.dc_min_temp = config.getfloat("drift_calibration_min_temp", 0.) + dc = config.getlists( + "drift_calibration", None, seps=(',', '\n'), parser=float + ) + self.min_freq = 999999999999. + if dc is not None: + for coefs in dc: + if len(coefs) != 3: + raise config.error( + "Invalid polynomial in drift calibration" + ) + self.drift_calibration = [Polynomial2d(*coefs) for coefs in dc] + cal = self.drift_calibration + start_temp, end_temp = self.dc_min_temp, self.max_valid_temp + self._check_calibration(cal, start_temp, end_temp, config.error) + low_poly = self.drift_calibration[-1] + self.min_freq = min([low_poly(temp) for temp in range(121)]) + cal_str = "\n".join([repr(p) for p in cal]) + logging.info( + "%s: loaded temperature drift calibration. Min Temp: %.2f," + " Min Freq: %.6f\n%s" + % (self.name, self.dc_min_temp, self.min_freq, cal_str) + ) + else: + logging.info( + "%s: No drift calibration configured, disabling temperature " + "drift compensation" + % (self.name,) + ) + self.enabled = has_dc = self.drift_calibration is not None + if self.cal_temp < 1e-6 and has_dc: + self.enabled = False + logging.info( + "%s: No temperature saved for eddy probe calibration, " + "disabling temperature drift compensation." + % (self.name,) + ) + + def is_enabled(self): + return self.enabled + + def set_enabled(self, gcmd): + enabled = gcmd.get_int("ENABLE") + if enabled: + if self.drift_calibration is None: + raise gcmd.error( + "No drift calibration configured, cannot enable " + "temperature drift compensation" + ) + if self.cal_temp < 1e-6: + raise gcmd.error( + "Z Calibration temperature not configured, cannot enable " + "temperature drift compensation" + ) + self.enabled = enabled + + def note_z_calibration_start(self): + self.cal_temp = self.get_temperature() + + def note_z_calibration_finish(self): + self.cal_temp = (self.cal_temp + self.get_temperature()) / 2.0 + configfile = self.printer.lookup_object('configfile') + configfile.set(self.name, "calibration_temp", "%.6f " % (self.cal_temp)) + gcode = self.printer.lookup_object("gcode") + gcode.respond_info( + "%s: Z Calibration Temperature set to %.2f. " + "The SAVE_CONFIG command will update the printer config " + "file and restart the printer." + % (self.name, self.cal_temp) + ) + + def collect_sample(self, kin_pos, tool_zero_z, speeds): + if self.calibration_samples is None: + self.calibration_samples = [[] for _ in range(DRIFT_SAMPLE_COUNT)] + move_times = [] + temps = [0. for _ in range(DRIFT_SAMPLE_COUNT)] + probe_samples = [[] for _ in range(DRIFT_SAMPLE_COUNT)] + toolhead = self.printer.lookup_object("toolhead") + cur_pos = toolhead.get_position() + lift_speed, probe_speed, _ = speeds + + def _on_bulk_data_recd(msg): + if move_times: + idx, start_time, end_time = move_times[0] + cur_temp = self.get_temperature() + for sample in msg["data"]: + ptime = sample[0] + while ptime > end_time: + move_times.pop(0) + if not move_times: + return idx >= DRIFT_SAMPLE_COUNT - 1 + idx, start_time, end_time = move_times[0] + if ptime < start_time: + continue + temps[idx] = cur_temp + probe_samples[idx].append(sample) + return True + sect_name = "probe_eddy_current " + self.name.split(maxsplit=1)[-1] + self.printer.lookup_object(sect_name).add_client(_on_bulk_data_recd) + for i in range(DRIFT_SAMPLE_COUNT): + if i == 0: + # Move down to first sample location + cur_pos[2] = tool_zero_z + .05 + else: + # Sample each .5mm in z + cur_pos[2] += 1. + toolhead.manual_move(cur_pos, lift_speed) + cur_pos[2] -= .5 + toolhead.manual_move(cur_pos, probe_speed) + start = toolhead.get_last_move_time() + .05 + end = start + .1 + move_times.append((i, start, end)) + toolhead.dwell(.2) + toolhead.wait_moves() + # Wait for sample collection to finish + reactor = self.printer.get_reactor() + evttime = reactor.monotonic() + while move_times: + evttime = reactor.pause(evttime + .1) + sample_temp = sum(temps) / len(temps) + for i, data in enumerate(probe_samples): + freqs = [d[1] for d in data] + zvals = [d[2] for d in data] + avg_freq = sum(freqs) / len(freqs) + avg_z = sum(zvals) / len(zvals) + kin_z = i * .5 + .05 + kin_pos[2] + logging.info( + "Probe Values at Temp %.2fC, Z %.4fmm: Avg Freq = %.6f, " + "Avg Measured Z = %.6f" + % (sample_temp, kin_z, avg_freq, avg_z) + ) + self.calibration_samples[i].append((sample_temp, avg_freq)) + return sample_temp + + def start_calibration(self): + self.enabled = False + self.calibration_samples = [[] for _ in range(DRIFT_SAMPLE_COUNT)] + + def finish_calibration(self, success): + cal_samples = self.calibration_samples + self.calibration_samples = None + if not success: + return + gcode = self.printer.lookup_object("gcode") + if len(cal_samples) < 3: + raise gcode.error( + "calbration error, not enough samples" + ) + min_temp, _ = cal_samples[0][0] + max_temp, _ = cal_samples[-1][0] + polynomials = [] + for i, coords in enumerate(cal_samples): + height = .05 + i * .5 + poly = Polynomial2d.fit(coords) + polynomials.append(poly) + logging.info("Polynomial at Z=%.2f: %s" % (height, repr(poly))) + end_vld_temp = max(self.max_valid_temp, max_temp) + self._check_calibration(polynomials, min_temp, end_vld_temp) + coef_cfg = "\n" + "\n".join([str(p) for p in polynomials]) + configfile = self.printer.lookup_object('configfile') + configfile.set(self.name, "drift_calibration", coef_cfg) + configfile.set(self.name, "drift_calibration_min_temp", min_temp) + gcode.respond_info( + "%s: generated %d 2D polynomials\n" + "The SAVE_CONFIG command will update the printer config " + "file and restart the printer." + % (self.name, len(polynomials)) + ) + + def _check_calibration(self, calibration, start_temp, end_temp, error=None): + error = error or self.printer.command_error + start = int(start_temp) + end = int(end_temp) + 1 + for temp in range(start, end, 1): + last_freq = calibration[0](temp) + for i, poly in enumerate(calibration[1:]): + next_freq = poly(temp) + if next_freq >= last_freq: + # invalid polynomial + raise error( + "%s: invalid calibration detected, curve at index " + "%d overlaps previous curve at temp %dC." + % (self.name, i + 1, temp) + ) + last_freq = next_freq + + def adjust_freq(self, freq, origin_temp=None): + # Adjusts frequency from current temperature toward + # destination temperature + if not self.enabled or freq < self.min_freq: + return freq + if origin_temp is None: + origin_temp = self.get_temperature() + return self._calc_freq(freq, origin_temp, self.cal_temp) + + def unadjust_freq(self, freq, dest_temp=None): + # Given a frequency and its orignal sampled temp, find the + # offset frequency based on the current temp + if not self.enabled or freq < self.min_freq: + return freq + if dest_temp is None: + dest_temp = self.get_temperature() + return self._calc_freq(freq, self.cal_temp, dest_temp) + + def _calc_freq(self, freq, origin_temp, dest_temp): + high_freq = low_freq = None + dc = self.drift_calibration + for pos, poly in enumerate(dc): + high_freq = low_freq + low_freq = poly(origin_temp) + if freq >= low_freq: + if high_freq is None: + # Freqency above max calibration value + err = poly(dest_temp) - low_freq + return freq + err + t = min(1., max(0., (freq - low_freq) / (high_freq - low_freq))) + low_tgt_freq = poly(dest_temp) + high_tgt_freq = dc[pos-1](dest_temp) + return (1 - t) * low_tgt_freq + t * high_tgt_freq + # Frequency below minimum, no correction + return freq + + def get_temperature(self): + return self.temp_sensor.get_temp()[0] + + +def load_config_prefix(config): + return TemperatureProbe(config) diff --git a/klippy/kinematics/idex_modes.py b/klippy/kinematics/idex_modes.py index f2618d0805a7..2f2da4168358 100644 --- a/klippy/kinematics/idex_modes.py +++ b/klippy/kinematics/idex_modes.py @@ -4,7 +4,7 @@ # Copyright (C) 2023 Dmitry Butyugin # # This file may be distributed under the terms of the GNU GPLv3 license. -import math +import logging, math import chelper INACTIVE = 'INACTIVE' @@ -202,14 +202,31 @@ def cmd_RESTORE_DUAL_CARRIAGE_STATE(self, gcmd): move_speed = gcmd.get_float('MOVE_SPEED', 0., above=0.) toolhead = self.printer.lookup_object('toolhead') toolhead.flush_step_generation() - pos = toolhead.get_position() if gcmd.get_int('MOVE', 1): + homing_speed = 99999999. + cur_pos = [] for i, dc in enumerate(self.dc): self.toggle_active_dc_rail(i) - saved_pos = saved_state['axes_positions'][i] - toolhead.manual_move( - pos[:self.axis] + [saved_pos] + pos[self.axis+1:], - move_speed or dc.get_rail().homing_speed) + homing_speed = min(homing_speed, dc.get_rail().homing_speed) + cur_pos.append(toolhead.get_position()) + move_pos = list(cur_pos[0]) + dl = [saved_state['axes_positions'][i] - cur_pos[i][self.axis] + for i in range(2)] + primary_ind = 0 if abs(dl[0]) >= abs(dl[1]) else 1 + self.toggle_active_dc_rail(primary_ind) + move_pos[self.axis] = saved_state['axes_positions'][primary_ind] + dc_mode = INACTIVE if min(abs(dl[0]), abs(dl[1])) < 0.000000001 \ + else COPY if dl[0] * dl[1] > 0 else MIRROR + if dc_mode != INACTIVE: + self.dc[1-primary_ind].activate(dc_mode, cur_pos[primary_ind]) + self.dc[1-primary_ind].override_axis_scaling( + abs(dl[1-primary_ind] / dl[primary_ind]), + cur_pos[primary_ind]) + toolhead.manual_move(move_pos, move_speed or homing_speed) + toolhead.flush_step_generation() + # Make sure the scaling coefficients are restored with the mode + self.dc[0].inactivate(move_pos) + self.dc[1].inactivate(move_pos) for i, dc in enumerate(self.dc): saved_mode = saved_state['carriage_modes'][i] self.activate_dc_mode(i, saved_mode) @@ -257,3 +274,8 @@ def inactivate(self, position): self.scale = 0. self.apply_transform() self.mode = INACTIVE + def override_axis_scaling(self, new_scale, position): + old_axis_position = self.get_axis_position(position) + self.scale = math.copysign(new_scale, self.scale) + self.offset = old_axis_position - position[self.axis] * self.scale + self.apply_transform() diff --git a/klippy/mcu.py b/klippy/mcu.py index 1122ff865845..eb71e6bc2a97 100644 --- a/klippy/mcu.py +++ b/klippy/mcu.py @@ -832,9 +832,10 @@ def _ready(self): systime = self._reactor.monotonic() get_clock = self._clocksync.get_clock calc_freq = get_clock(systime + 1) - get_clock(systime) + freq_diff = abs(mcu_freq - calc_freq) mcu_freq_mhz = int(mcu_freq / 1000000. + 0.5) calc_freq_mhz = int(calc_freq / 1000000. + 0.5) - if mcu_freq_mhz != calc_freq_mhz: + if freq_diff > mcu_freq*0.01 and mcu_freq_mhz != calc_freq_mhz: pconfig = self._printer.lookup_object('configfile') msg = ("MCU '%s' configured for %dMhz but running at %dMhz!" % (self._name, mcu_freq_mhz, calc_freq_mhz)) diff --git a/klippy/msgproto.py b/klippy/msgproto.py index 0fe765934590..25701df36c86 100644 --- a/klippy/msgproto.py +++ b/klippy/msgproto.py @@ -324,7 +324,7 @@ def lookup_msgid(self, msgformat): def create_command(self, msg): parts = msg.strip().split() if not parts: - return "" + return [] msgname = parts[0] mp = self.messages_by_name.get(msgname) if mp is None: diff --git a/klippy/stepper.py b/klippy/stepper.py index 9b692904dcf9..05e56cca4327 100644 --- a/klippy/stepper.py +++ b/klippy/stepper.py @@ -138,8 +138,10 @@ def set_position(self, coord): def get_commanded_position(self): ffi_main, ffi_lib = chelper.get_ffi() return ffi_lib.itersolve_get_commanded_pos(self._stepper_kinematics) - def get_mcu_position(self): - mcu_pos_dist = self.get_commanded_position() + self._mcu_position_offset + def get_mcu_position(self, cmd_pos=None): + if cmd_pos is None: + cmd_pos = self.get_commanded_position() + mcu_pos_dist = cmd_pos + self._mcu_position_offset mcu_pos = mcu_pos_dist / self._step_dist if mcu_pos >= 0.: return int(mcu_pos + 0.5) diff --git a/lib/README b/lib/README index 106b2cfc35fa..367e07659d4a 100644 --- a/lib/README +++ b/lib/README @@ -105,16 +105,23 @@ The stm32h7 directory contains code from: version v1.9.0 (ccb11556044540590ca6e45056e6b65cdca2deb2). Contents taken from the Drivers/CMSIS/Device/ST/STM32H7xx/ directory. -The rp2040 directory contains code from the pico sdk: +The pico-sdk directory contains code from the pico sdk: https://github.com/raspberrypi/pico-sdk.git -version 1.2.0 (bfcbefafc5d2a210551a4d9d80b4303d4ae0adf7). It has been +version 2.0.0 (efe2103f9b28458a1615ff096054479743ade236). It has been modified so that it can build outside of the pico sdk. See -rp2040.patch for the modifications. +pico-sdk.patch for the modifications. + +The elf2uf2 directory contains code from the pico sdk: + https://github.com/raspberrypi/pico-sdk.git +version 1.2.0 (bfcbefafc5d2a210551a4d9d80b4303d4ae0adf7). Contents +taken from the tools/elf2uf2/ directory. The rp2040_flash directory contains a light-weight bootsel flash tool. It uses C part of the the `picoboot_connection` directory found in: https://github.com/raspberrypi/picotool.git -version v1.1.0 (55fd880c3dc029b961fc1a0967a6cfdc0af02721). +version 2.0.0 (8a9af99ab10b20b1c6afb30cd9384e562a6647f9). Note that +Makefile and main.c are locally developed files (the remaining files +are from the picotool repo). The hub-ctrl directory contains code from: https://github.com/codazoda/hub-ctrl.c/ @@ -167,7 +174,7 @@ used to upload firmware to devices flashed with the CanBoot bootloader. The can2040 directory contains code from: https://github.com/KevinOConnor/can2040 -version v1.6.0 (af3d21e5d61b8408c63fbdfb0aceb21d69d91693) +commit 13321ce2bc046e059a47def70f977a579a984462. The Huada HC32F460 directory contains code from: https://www.hdsc.com.cn/Category83-1490 diff --git a/lib/can2040/can2040.c b/lib/can2040/can2040.c index c2bd0061a57c..4e5108ca22f5 100644 --- a/lib/can2040/can2040.c +++ b/lib/can2040/can2040.c @@ -6,8 +6,8 @@ #include // uint32_t #include // memset -#include "RP2040.h" // hw_set_bits #include "can2040.h" // can2040_setup +#include "cmsis_gcc.h" // __DMB #include "hardware/regs/dreq.h" // DREQ_PIO0_RX1 #include "hardware/structs/dma.h" // dma_hw #include "hardware/structs/iobank0.h" // iobank0_hw @@ -128,7 +128,7 @@ static void pio_sync_setup(struct can2040 *cd) { pio_hw_t *pio_hw = cd->pio_hw; - struct pio_sm_hw *sm = &pio_hw->sm[0]; + pio_sm_hw_t *sm = &pio_hw->sm[0]; sm->execctrl = ( cd->gpio_rx << PIO_SM0_EXECCTRL_JMP_PIN_LSB | (can2040_offset_sync_end - 1) << PIO_SM0_EXECCTRL_WRAP_TOP_LSB @@ -148,7 +148,7 @@ static void pio_rx_setup(struct can2040 *cd) { pio_hw_t *pio_hw = cd->pio_hw; - struct pio_sm_hw *sm = &pio_hw->sm[1]; + pio_sm_hw_t *sm = &pio_hw->sm[1]; sm->execctrl = ( (can2040_offset_shared_rx_end - 1) << PIO_SM0_EXECCTRL_WRAP_TOP_LSB | can2040_offset_shared_rx_read << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB); @@ -165,7 +165,7 @@ static void pio_match_setup(struct can2040 *cd) { pio_hw_t *pio_hw = cd->pio_hw; - struct pio_sm_hw *sm = &pio_hw->sm[2]; + pio_sm_hw_t *sm = &pio_hw->sm[2]; sm->execctrl = ( (can2040_offset_match_end - 1) << PIO_SM0_EXECCTRL_WRAP_TOP_LSB | can2040_offset_shared_rx_read << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB); @@ -173,7 +173,7 @@ pio_match_setup(struct can2040 *cd) sm->shiftctrl = 0; sm->instr = 0xe040; // set y, 0 sm->instr = 0xa0e2; // mov osr, y - sm->instr = 0xa02a, // mov x, !y + sm->instr = 0xa02a; // mov x, !y sm->instr = can2040_offset_match_load_next; // jmp match_load_next } @@ -182,7 +182,7 @@ static void pio_tx_setup(struct can2040 *cd) { pio_hw_t *pio_hw = cd->pio_hw; - struct pio_sm_hw *sm = &pio_hw->sm[3]; + pio_sm_hw_t *sm = &pio_hw->sm[3]; sm->execctrl = ( cd->gpio_rx << PIO_SM0_EXECCTRL_JMP_PIN_LSB | can2040_offset_tx_conflict << PIO_SM0_EXECCTRL_WRAP_TOP_LSB @@ -255,7 +255,7 @@ pio_tx_reset(struct can2040 *cd) | (0x08 << PIO_CTRL_SM_RESTART_LSB)); pio_hw->irq = (SI_MATCHED | SI_ACKDONE) >> 8; // clear PIO irq flags // Clear tx fifo - struct pio_sm_hw *sm = &pio_hw->sm[3]; + pio_sm_hw_t *sm = &pio_hw->sm[3]; sm->shiftctrl = 0; sm->shiftctrl = (PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_AUTOPULL_BITS); @@ -271,7 +271,7 @@ pio_tx_send(struct can2040 *cd, uint32_t *data, uint32_t count) uint32_t i; for (i=0; itxf[3] = data[i]; - struct pio_sm_hw *sm = &pio_hw->sm[3]; + pio_sm_hw_t *sm = &pio_hw->sm[3]; sm->instr = 0xe001; // set pins, 1 sm->instr = 0x6021; // out x, 1 sm->instr = can2040_offset_tx_write_pin; // jmp tx_write_pin @@ -287,7 +287,7 @@ pio_tx_inject_ack(struct can2040 *cd, uint32_t match_key) pio_tx_reset(cd); pio_hw->instr_mem[can2040_offset_tx_got_recessive] = 0xc023; // irq wait 3 pio_hw->txf[3] = 0x7fffffff; - struct pio_sm_hw *sm = &pio_hw->sm[3]; + pio_sm_hw_t *sm = &pio_hw->sm[3]; sm->instr = 0xe001; // set pins, 1 sm->instr = 0x6021; // out x, 1 sm->instr = can2040_offset_tx_write_pin; // jmp tx_write_pin diff --git a/lib/cmsis-core/core_cm33.h b/lib/cmsis-core/core_cm33.h new file mode 100644 index 000000000000..13359be3ed04 --- /dev/null +++ b/lib/cmsis-core/core_cm33.h @@ -0,0 +1,3264 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/lib/cmsis-core/mpu_armv8.h b/lib/cmsis-core/mpu_armv8.h new file mode 100644 index 000000000000..ef44ad01df0c --- /dev/null +++ b/lib/cmsis-core/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.2 + * @date 10. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/lib/rp2040/elf2uf2/elf.h b/lib/elf2uf2/elf.h similarity index 100% rename from lib/rp2040/elf2uf2/elf.h rename to lib/elf2uf2/elf.h diff --git a/lib/rp2040/elf2uf2/main.cpp b/lib/elf2uf2/main.cpp similarity index 100% rename from lib/rp2040/elf2uf2/main.cpp rename to lib/elf2uf2/main.cpp diff --git a/lib/rp2040/boot/picoboot.h b/lib/pico-sdk/boot/picoboot.h similarity index 63% rename from lib/rp2040/boot/picoboot.h rename to lib/pico-sdk/boot/picoboot.h index ddfa0aaad450..8645d52d738d 100644 --- a/lib/rp2040/boot/picoboot.h +++ b/lib/pico-sdk/boot/picoboot.h @@ -16,18 +16,20 @@ #endif /** \file picoboot.h -* \defgroup boot_picoboot boot_picoboot +* \defgroup boot_picoboot_headers boot_picoboot_headers * -* Header file for the PICOBOOT USB interface exposed by an RP2040 in BOOTSEL mode. +* \brief Header file for the PICOBOOT USB interface exposed by an RP2xxx chip in BOOTSEL mode */ +#include "picoboot_constants.h" + #define PICOBOOT_MAGIC 0x431fd10bu // -------------------------------------------- // CONTROL REQUESTS FOR THE PICOBOOT INTERFACE // -------------------------------------------- -// size 0 OUT - unstall EPs and reset +// size 0 OUT - un-stall EPs and reset #define PICOBOOT_IF_RESET 0x41 // size 16 IN - return the status of the last command @@ -47,11 +49,17 @@ enum picoboot_cmd_id { PC_REBOOT = 0x2, PC_FLASH_ERASE = 0x3, PC_READ = 0x84, // either RAM or FLASH - PC_WRITE = 5, // either RAM or FLASH (does no erase) + PC_WRITE = 0x5, // either RAM or FLASH (does no erase) PC_EXIT_XIP = 0x6, PC_ENTER_CMD_XIP = 0x7, PC_EXEC = 0x8, - PC_VECTORIZE_FLASH = 0x9 + PC_VECTORIZE_FLASH = 0x9, + // RP2350 only below here + PC_REBOOT2 = 0xa, + PC_GET_INFO = 0x8b, + PC_OTP_READ = 0x8c, + PC_OTP_WRITE = 0xd, + //PC_EXEC2 = 0xe, // currently unused }; enum picoboot_status { @@ -64,14 +72,32 @@ enum picoboot_status { PICOBOOT_INTERLEAVED_WRITE = 6, PICOBOOT_REBOOTING = 7, PICOBOOT_UNKNOWN_ERROR = 8, + PICOBOOT_INVALID_STATE = 9, + PICOBOOT_NOT_PERMITTED = 10, + PICOBOOT_INVALID_ARG = 11, + PICOBOOT_BUFFER_TOO_SMALL = 12, + PICOBOOT_PRECONDITION_NOT_MET = 13, + PICOBOOT_MODIFIED_DATA = 14, + PICOBOOT_INVALID_DATA = 15, + PICOBOOT_NOT_FOUND = 16, + PICOBOOT_UNSUPPORTED_MODIFICATION = 17, }; struct __packed picoboot_reboot_cmd { - uint32_t dPC; // 0 means reset into bootrom + uint32_t dPC; // 0 means reset into regular boot path uint32_t dSP; uint32_t dDelayMS; }; + +// note this (with pc_sp) union member has the same layout as picoboot_reboot_cmd except with extra dFlags +struct __packed picoboot_reboot2_cmd { + uint32_t dFlags; + uint32_t dDelayMS; + uint32_t dParam0; + uint32_t dParam1; +}; + // used for EXEC, VECTORIZE_FLASH struct __packed picoboot_address_only_cmd { uint32_t dAddr; @@ -83,6 +109,13 @@ struct __packed picoboot_range_cmd { uint32_t dSize; }; +struct __packed picoboot_exec2_cmd { + uint32_t image_base; + uint32_t image_size; + uint32_t workarea_base; + uint32_t workarea_size; +}; + enum picoboot_exclusive_type { NOT_EXCLUSIVE = 0, EXCLUSIVE, @@ -93,6 +126,20 @@ struct __packed picoboot_exclusive_cmd { uint8_t bExclusive; }; +struct __packed picoboot_otp_cmd { + uint16_t wRow; // OTP row + uint16_t wRowCount; // number of rows to transfer + uint8_t bEcc; // use error correction (16 bit per register vs 24 (stored as 32) bit raw) +}; + + +struct __packed picoboot_get_info_cmd { + uint8_t bType; + uint8_t bParam; + uint16_t wParam; + uint32_t dParams[3]; +}; + // little endian struct __packed __aligned(4) picoboot_cmd { uint32_t dMagic; @@ -107,9 +154,12 @@ struct __packed __aligned(4) picoboot_cmd { struct picoboot_range_cmd range_cmd; struct picoboot_address_only_cmd address_only_cmd; struct picoboot_exclusive_cmd exclusive_cmd; + struct picoboot_reboot2_cmd reboot2_cmd; + struct picoboot_otp_cmd otp_cmd; + struct picoboot_get_info_cmd get_info_cmd; + struct picoboot_exec2_cmd exec2_cmd; }; }; - static_assert(32 == sizeof(struct picoboot_cmd), "picoboot_cmd must be 32 bytes big"); struct __packed __aligned(4) picoboot_cmd_status { @@ -121,4 +171,5 @@ struct __packed __aligned(4) picoboot_cmd_status { }; static_assert(16 == sizeof(struct picoboot_cmd_status), "picoboot_cmd_status must be 16 bytes big"); + #endif diff --git a/lib/pico-sdk/boot/picoboot_constants.h b/lib/pico-sdk/boot/picoboot_constants.h new file mode 100644 index 000000000000..ac78ea21351d --- /dev/null +++ b/lib/pico-sdk/boot/picoboot_constants.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOOT_PICOBOOT_CONSTANTS_H +#define _BOOT_PICOBOOT_CONSTANTS_H + +#define REBOOT2_TYPE_MASK 0x0f + +// note these match REBOOT_TYPE in pico/bootrom_constants.h (also 0 is used for PC_SP for backwards compatibility with RP2040) +// values 0-7 are secure/non-secure +#define REBOOT2_FLAG_REBOOT_TYPE_NORMAL 0x0 // param0 = diagnostic partition +#define REBOOT2_FLAG_REBOOT_TYPE_BOOTSEL 0x2 // param0 = bootsel_flags, param1 = gpio_config +#define REBOOT2_FLAG_REBOOT_TYPE_RAM_IMAGE 0x3 // param0 = image_base, param1 = image_end +#define REBOOT2_FLAG_REBOOT_TYPE_FLASH_UPDATE 0x4 // param0 = update_base + +// values 8-15 are secure only +#define REBOOT2_FLAG_REBOOT_TYPE_PC_SP 0xd + +#define REBOOT2_FLAG_REBOOT_TO_ARM 0x10 +#define REBOOT2_FLAG_REBOOT_TO_RISCV 0x20 + +#define REBOOT2_FLAG_NO_RETURN_ON_SUCCESS 0x100 + +#define BOOTSEL_FLAG_DISABLE_MSD_INTERFACE 0x01 +#define BOOTSEL_FLAG_DISABLE_PICOBOOT_INTERFACE 0x02 +#define BOOTSEL_FLAG_GPIO_PIN_ACTIVE_LOW 0x10 +#define BOOTSEL_FLAG_GPIO_PIN_SPECIFIED 0x20 + +#define PICOBOOT_GET_INFO_SYS 1 +#define PICOBOOT_GET_INFO_PARTTION_TABLE 2 +#define PICOBOOT_GET_INFO_UF2_TARGET_PARTITION 3 +#define PICOBOOT_GET_INFO_UF2_STATUS 4 + +#define UF2_STATUS_IGNORED_FAMILY 0x01 +#define UF2_STATUS_ABORT_EXCLUSIVELY_LOCKED 0x10 +#define UF2_STATUS_ABORT_BAD_ADDRESS 0x20 +#define UF2_STATUS_ABORT_WRITE_ERROR 0x40 +#define UF2_STATUS_ABORT_REBOOT_FAILED 0x80 +#endif \ No newline at end of file diff --git a/lib/rp2040/boot/uf2.h b/lib/pico-sdk/boot/uf2.h similarity index 65% rename from lib/rp2040/boot/uf2.h rename to lib/pico-sdk/boot/uf2.h index a040242bd9a9..271540a205fa 100644 --- a/lib/rp2040/boot/uf2.h +++ b/lib/pico-sdk/boot/uf2.h @@ -11,9 +11,9 @@ #include /** \file uf2.h -* \defgroup boot_uf2 boot_uf2 +* \defgroup boot_uf2_headers boot_uf2_headers * -* Header file for the UF2 format supported by an RP2040 in BOOTSEL mode. +* \brief Header file for the UF2 format supported by a RP2xxx chip in BOOTSEL mode */ #define UF2_MAGIC_START0 0x0A324655u @@ -25,7 +25,14 @@ #define UF2_FLAG_FAMILY_ID_PRESENT 0x00002000u #define UF2_FLAG_MD5_PRESENT 0x00004000u -#define RP2040_FAMILY_ID 0xe48bff56 +#define RP2040_FAMILY_ID 0xe48bff56u +#define ABSOLUTE_FAMILY_ID 0xe48bff57u +#define DATA_FAMILY_ID 0xe48bff58u +#define RP2350_ARM_S_FAMILY_ID 0xe48bff59u +#define RP2350_RISCV_FAMILY_ID 0xe48bff5au +#define RP2350_ARM_NS_FAMILY_ID 0xe48bff5bu +#define FAMILY_ID_MAX 0xe48bff5bu + struct uf2_block { // 32 byte header diff --git a/lib/rp2040/hardware/address_mapped.h b/lib/pico-sdk/hardware/address_mapped.h similarity index 63% rename from lib/rp2040/hardware/address_mapped.h rename to lib/pico-sdk/hardware/address_mapped.h index d651f5985f1d..635a275b5e89 100644 --- a/lib/rp2040/hardware/address_mapped.h +++ b/lib/pico-sdk/hardware/address_mapped.h @@ -10,12 +10,13 @@ //#include "pico.h" #define __force_inline inline #define static_assert(a,b) +#define valid_params_if(a,b) #include "hardware/regs/addressmap.h" /** \file address_mapped.h * \defgroup hardware_base hardware_base * - * Low-level types and (atomic) accessors for memory-mapped hardware registers + * \brief Low-level types and (atomic) accessors for memory-mapped hardware registers * * `hardware_base` defines the low level types and access functions for memory mapped hardware registers. It is included * by default by all other hardware libraries. @@ -36,7 +37,7 @@ * When dealing with these types, you will always use a pointer, i.e. `io_rw_32 *some_reg` is a pointer to a read/write * 32 bit register that you can write with `*some_reg = value`, or read with `value = *some_reg`. * - * RP2040 hardware is also aliased to provide atomic setting, clear or flipping of a subset of the bits within + * RP-series hardware is also aliased to provide atomic setting, clear or flipping of a subset of the bits within * a hardware register so that concurrent access by two cores is always consistent with one atomic operation * being performed first, followed by the second. * @@ -57,6 +58,14 @@ extern "C" { #define check_hw_layout(type, member, offset) static_assert(offsetof(type, member) == (offset), "hw offset mismatch") #define check_hw_size(type, size) static_assert(sizeof(type) == (size), "hw size mismatch") +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS, Enable/disable assertions in memory address aliasing macros, type=bool, default=0, group=hardware_base +#ifndef PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS +#define PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS 0 +#endif + +typedef volatile uint64_t io_rw_64; +typedef const volatile uint64_t io_ro_64; +typedef volatile uint64_t io_wo_64; typedef volatile uint32_t io_rw_32; typedef const volatile uint32_t io_ro_32; typedef volatile uint32_t io_wo_32; @@ -70,15 +79,55 @@ typedef volatile uint8_t io_wo_8; typedef volatile uint8_t *const ioptr; typedef ioptr const const_ioptr; +// A non-functional (empty) helper macro to help IDEs follow links from the autogenerated +// hardware struct headers in hardware/structs/xxx.h to the raw register definitions +// in hardware/regs/xxx.h. A preprocessor define such as TIMER_TIMEHW_OFFSET (a timer register offset) +// is not generally clickable (in an IDE) if placed in a C comment, so _REG_(TIMER_TIMEHW_OFFSET) is +// included outside of a comment instead +#define _REG_(x) + +// Helper method used by hw_alias macros to optionally check input validity +#define hw_alias_check_addr(addr) ((uintptr_t)(addr)) +// can't use the following impl as it breaks existing static declarations using hw_alias, so would be a backwards incompatibility +//static __force_inline uint32_t hw_alias_check_addr(volatile void *addr) { +// uint32_t rc = (uintptr_t)addr; +// invalid_params_if(ADDRESS_ALIAS, rc < 0x40000000); // catch likely non HW pointer types +// return rc; +//} + +#if PICO_RP2040 +// Helper method used by xip_alias macros to optionally check input validity +__force_inline static uint32_t xip_alias_check_addr(const void *addr) { + uint32_t rc = (uintptr_t)addr; + valid_params_if(ADDRESS_ALIAS, rc >= XIP_MAIN_BASE && rc < XIP_NOALLOC_BASE); + return rc; +} +#else +//static __force_inline uint32_t xip_alias_check_addr(const void *addr) { +// uint32_t rc = (uintptr_t)addr; +// valid_params_if(ADDRESS_ALIAS, rc >= XIP_BASE && rc < XIP_END); +// return rc; +//} +#endif + // Untyped conversion alias pointer generation macros -#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | (uintptr_t)(addr))) -#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | (uintptr_t)(addr))) -#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | (uintptr_t)(addr))) +#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS + hw_alias_check_addr(addr))) +#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS + hw_alias_check_addr(addr))) +#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS + hw_alias_check_addr(addr))) + +#if PICO_RP2040 +#define xip_noalloc_alias_untyped(addr) ((void *)(XIP_NOALLOC_BASE | xip_alias_check_addr(addr))) +#define xip_nocache_alias_untyped(addr) ((void *)(XIP_NOCACHE_BASE | xip_alias_check_addr(addr))) +#define xip_nocache_noalloc_alias_untyped(addr) ((void *)(XIP_NOCACHE_NOALLOC_BASE | xip_alias_check_addr(addr))) +#endif // Typed conversion alias pointer generation macros #define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p)) #define hw_clear_alias(p) ((typeof(p))hw_clear_alias_untyped(p)) #define hw_xor_alias(p) ((typeof(p))hw_xor_alias_untyped(p)) +#define xip_noalloc_alias(p) ((typeof(p))xip_noalloc_alias_untyped(p)) +#define xip_nocache_alias(p) ((typeof(p))xip_nocache_alias_untyped(p)) +#define xip_nocache_noalloc_alias(p) ((typeof(p))xip_nocache_noalloc_alias_untyped(p)) /*! \brief Atomically set the specified bits to 1 in a HW register * \ingroup hardware_base @@ -126,6 +175,11 @@ __force_inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint hw_xor_bits(addr, (*addr ^ values) & write_mask); } +#if !PICO_RP2040 +// include this here to avoid the check in every other hardware/structs header that needs it +#include "hardware/structs/accessctrl.h" +#endif + #ifdef __cplusplus } #endif diff --git a/lib/pico-sdk/hardware/platform_defs.h b/lib/pico-sdk/hardware/platform_defs.h new file mode 100644 index 000000000000..924336a9240f --- /dev/null +++ b/lib/pico-sdk/hardware/platform_defs.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_PLATFORM_DEFS_H +#define _HARDWARE_PLATFORM_DEFS_H + +#define NUM_CORES 2u + +#define NUM_DMA_CHANNELS 12u + +#define NUM_GENERIC_TIMERS 1u +#define NUM_ALARMS 4u + +#define NUM_IRQS 32u + +#define NUM_SPIN_LOCKS 32u + +#define XOSC_HZ 12000000u + +#define NUM_SPIN_LOCKS 32u + +#define NUM_BANK0_GPIOS 30 + +#ifndef _u +#define _u(x) x ## u +#endif + +#endif diff --git a/lib/pico-sdk/pico-sdk.patch b/lib/pico-sdk/pico-sdk.patch new file mode 100644 index 000000000000..0a27b4605bff --- /dev/null +++ b/lib/pico-sdk/pico-sdk.patch @@ -0,0 +1,69 @@ +diff --git a/lib/pico-sdk/hardware/address_mapped.h b/lib/pico-sdk/hardware/address_mapped.h +index b384f5572..635a275b5 100644 +--- a/lib/pico-sdk/hardware/address_mapped.h ++++ b/lib/pico-sdk/hardware/address_mapped.h +@@ -7,7 +7,10 @@ + #ifndef _HARDWARE_ADDRESS_MAPPED_H + #define _HARDWARE_ADDRESS_MAPPED_H + +-#include "pico.h" ++//#include "pico.h" ++#define __force_inline inline ++#define static_assert(a,b) ++#define valid_params_if(a,b) + #include "hardware/regs/addressmap.h" + + /** \file address_mapped.h +diff --git a/lib/pico-sdk/rp2040/cmsis_include/RP2040.h b/lib/pico-sdk/rp2040/cmsis_include/RP2040.h +index 8da431fae..be661392c 100644 +--- a/lib/pico-sdk/rp2040/cmsis_include/RP2040.h ++++ b/lib/pico-sdk/rp2040/cmsis_include/RP2040.h +@@ -2572,6 +2572,7 @@ typedef struct { /*!< RTC Structure + * @{ + */ + ++#if 0 + #define RESETS_BASE 0x4000C000UL + #define PSM_BASE 0x40010000UL + #define CLOCKS_BASE 0x40008000UL +@@ -2608,6 +2609,7 @@ typedef struct { /*!< RTC Structure + #define TBMAN_BASE 0x4006C000UL + #define VREG_AND_CHIP_RESET_BASE 0x40064000UL + #define RTC_BASE 0x4005C000UL ++#endif + + /** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +diff --git a/lib/pico-sdk/rp2040/pico/asm_helper.S b/lib/pico-sdk/rp2040/pico/asm_helper.S +index aff1fc9ae..59c67db19 100644 +--- a/lib/pico-sdk/rp2040/pico/asm_helper.S ++++ b/lib/pico-sdk/rp2040/pico/asm_helper.S +@@ -4,7 +4,7 @@ + * SPDX-License-Identifier: BSD-3-Clause + */ + +-#include "pico.h" ++//#include "pico.h" + + # note we don't do this by default in this file for backwards comaptibility with user code + # that may include this file, but not use unified syntax. Note that this macro does equivalent +diff --git a/lib/pico-sdk/rp2350/cmsis_include/RP2350.h b/lib/pico-sdk/rp2350/cmsis_include/RP2350.h +index 8ae014e04..94d0f178c 100644 +--- a/lib/pico-sdk/rp2350/cmsis_include/RP2350.h ++++ b/lib/pico-sdk/rp2350/cmsis_include/RP2350.h +@@ -5933,6 +5933,7 @@ typedef struct { /*!< USB_DPRAM Structure + * @{ + */ + ++#if 0 + #define RESETS_BASE 0x40020000UL + #define PSM_BASE 0x40018000UL + #define CLOCKS_BASE 0x40010000UL +@@ -5986,6 +5987,7 @@ typedef struct { /*!< USB_DPRAM Structure + #define OTP_DATA_RAW_BASE 0x40134000UL + #define TBMAN_BASE 0x40160000UL + #define USB_DPRAM_BASE 0x50100000UL ++#endif + + /** @} */ /* End of group Device_Peripheral_peripheralAddr */ + diff --git a/lib/pico-sdk/pico/bootrom_constants.h b/lib/pico-sdk/pico/bootrom_constants.h new file mode 100644 index 000000000000..924487f8c95a --- /dev/null +++ b/lib/pico-sdk/pico/bootrom_constants.h @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PICO_BOOTROM_CONSTANTS_H +#define _PICO_BOOTROM_CONSTANTS_H + +#ifndef NO_PICO_PLATFORM +#include "pico/platform.h" +#endif + +// ROOT ADDRESSES +#define BOOTROM_MAGIC_OFFSET 0x10 +#define BOOTROM_FUNC_TABLE_OFFSET 0x14 +#if PICO_RP2040 +#define BOOTROM_DATA_TABLE_OFFSET 0x16 +#endif + +#if PICO_RP2040 +#define BOOTROM_VTABLE_OFFSET 0x00 +#define BOOTROM_TABLE_LOOKUP_OFFSET 0x18 +#else +// todo remove this (or #ifdef it for A1/A2) +#define BOOTROM_IS_A2() ((*(volatile uint8_t *)0x13) == 2) +#define BOOTROM_WELL_KNOWN_PTR_SIZE (BOOTROM_IS_A2() ? 2 : 4) +#if defined(__riscv) +#define BOOTROM_ENTRY_OFFSET 0x7dfc +#define BOOTROM_TABLE_LOOKUP_ENTRY_OFFSET (BOOTROM_ENTRY_OFFSET - BOOTROM_WELL_KNOWN_PTR_SIZE) +#define BOOTROM_TABLE_LOOKUP_OFFSET (BOOTROM_ENTRY_OFFSET - BOOTROM_WELL_KNOWN_PTR_SIZE*2) +#else +#define BOOTROM_VTABLE_OFFSET 0x00 +#define BOOTROM_TABLE_LOOKUP_OFFSET (BOOTROM_FUNC_TABLE_OFFSET + BOOTROM_WELL_KNOWN_PTR_SIZE) +#endif +#endif + +#if !PICO_RP2040 || PICO_COMBINED_DOCS + +#define BOOTROM_OK 0 +//#define BOOTROM_ERROR_TIMEOUT (-1) +//#define BOOTROM_ERROR_GENERIC (-2) +//#define BOOTROM_ERROR_NO_DATA (-3) // E.g. read from an empty buffer/FIFO +#define BOOTROM_ERROR_NOT_PERMITTED (-4) // Permission violation e.g. write to read-only flash partition +#define BOOTROM_ERROR_INVALID_ARG (-5) // Argument is outside of range of supported values` +//#define BOOTROM_ERROR_IO (-6) +//#define BOOTROM_ERROR_BADAUTH (-7) +//#define BOOTROM_ERROR_CONNECT_FAILED (-8) +//#define BOOTROM_ERROR_INSUFFICIENT_RESOURCES (-9) // Dynamic allocation of resources failed +#define BOOTROM_ERROR_INVALID_ADDRESS (-10) // Address argument was out-of-bounds or was determined to be an address that the caller may not access +#define BOOTROM_ERROR_BAD_ALIGNMENT (-11) // Address modulo transfer chunk size was nonzero (e.g. word-aligned transfer with address % 4 != 0) +#define BOOTROM_ERROR_INVALID_STATE (-12) // Something happened or failed to happen in the past, and consequently we (currently) can't service the request +#define BOOTROM_ERROR_BUFFER_TOO_SMALL (-13) // A user-allocated buffer was too small to hold the result or working state of this function +#define BOOTROM_ERROR_PRECONDITION_NOT_MET (-14) // This call failed because another ROM function must be called first +#define BOOTROM_ERROR_MODIFIED_DATA (-15) // Cached data was determined to be inconsistent with the full version of the data it was calculated from +#define BOOTROM_ERROR_INVALID_DATA (-16) // A data structure failed to validate +#define BOOTROM_ERROR_NOT_FOUND (-17) // Attempted to access something that does not exist; or, a search failed +#define BOOTROM_ERROR_UNSUPPORTED_MODIFICATION (-18) // Write is impossible based on previous writes; e.g. attempted to clear an OTP bit +#define BOOTROM_ERROR_LOCK_REQUIRED (-19) // A required lock is not owned +#define BOOTROM_ERROR_LAST (-19) + +#define RT_FLAG_FUNC_RISCV 0x0001 +#define RT_FLAG_FUNC_RISCV_FAR 0x0003 +#define RT_FLAG_FUNC_ARM_SEC 0x0004 +// reserved for 32-bit pointer: 0x0008 +#define RT_FLAG_FUNC_ARM_NONSEC 0x0010 +// reserved for 32-bit pointer: 0x0020 +#define RT_FLAG_DATA 0x0040 +// reserved for 32-bit pointer: 0x0080 + +#define PARTITION_TABLE_MAX_PARTITIONS 16 +// note this is deliberately > MAX_PARTITIONs is likely to be, and also -1 as a signed byte +#define PARTITION_TABLE_NO_PARTITION_INDEX 0xff + +// todo these are duplicated in picoboot_constants.h +// values 0-7 are secure/non-secure +#define BOOT_TYPE_NORMAL 0 +#define BOOT_TYPE_BOOTSEL 2 +#define BOOT_TYPE_RAM_IMAGE 3 +#define BOOT_TYPE_FLASH_UPDATE 4 + +// values 8-15 are secure only +#define BOOT_TYPE_PC_SP 0xd + +// ORed in if a bootloader chained into the image +#define BOOT_TYPE_CHAINED_FLAG 0x80 + +// call from NS to S +#ifndef __riscv +#define BOOTROM_API_CALLBACK_secure_call 0 +#endif +#define BOOTROM_API_CALLBACK_COUNT 1 + +#define BOOTROM_LOCK_SHA_256 0 +#define BOOTROM_LOCK_FLASH_OP 1 +#define BOOTROM_LOCK_OTP 2 +#define BOOTROM_LOCK_MAX 2 + +#define BOOTROM_LOCK_ENABLE 7 + +#define BOOT_PARTITION_NONE (-1) +#define BOOT_PARTITION_SLOT0 (-2) +#define BOOT_PARTITION_SLOT1 (-3) +#define BOOT_PARTITION_WINDOW (-4) + +#define BOOT_DIAGNOSTIC_WINDOW_SEARCHED 0x01 +// note if both BOOT_DIAGNOSTIC_INVALID_BLOCK_LOOP and BOOT_DIAGNOSTIC_VALID_BLOCK_LOOP then the block loop was valid +// but it has a PARTITION_TABLE which while it passed the initial verification (and hash/sig) had invalid contents +// (discovered when it was later loaded) +#define BOOT_DIAGNOSTIC_INVALID_BLOCK_LOOP 0x02 +#define BOOT_DIAGNOSTIC_VALID_BLOCK_LOOP 0x04 +#define BOOT_DIAGNOSTIC_VALID_IMAGE_DEF 0x08 +#define BOOT_DIAGNOSTIC_HAS_PARTITION_TABLE 0x10 +#define BOOT_DIAGNOSTIC_CONSIDERED 0x20 +#define BOOT_DIAGNOSTIC_CHOSEN 0x40 +#define BOOT_DIAGNOSTIC_PARTITION_TABLE_LSB 7 +#define BOOT_DIAGNOSTIC_PARTITION_TABLE_MATCHING_KEY_FOR_VERIFY 0x80 +#define BOOT_DIAGNOSTIC_PARTITION_TABLE_HASH_FOR_VERIFY 0x100 +#define BOOT_DIAGNOSTIC_PARTITION_TABLE_VERIFIED_OK 0x200 +#define BOOT_DIAGNOSTIC_IMAGE_DEF_LSB 10 +#define BOOT_DIAGNOSTIC_IMAGE_DEF_MATCHING_KEY_FOR_VERIFY 0x400 +#define BOOT_DIAGNOSTIC_IMAGE_DEF_HASH_FOR_VERIFY 0x800 +#define BOOT_DIAGNOSTIC_IMAGE_DEF_VERIFIED_OK 0x1000 + +#define BOOT_DIAGNOSTIC_LOAD_MAP_ENTRIES_LOADED 0x2000 +#define BOOT_DIAGNOSTIC_IMAGE_LAUNCHED 0x4000 +#define BOOT_DIAGNOSTIC_IMAGE_CONDITION_FAILURE 0x8000 + +#define BOOT_PARSED_BLOCK_DIAGNOSTIC_MATCHING_KEY_FOR_VERIFY 0x1 // if this is present and VERIFIED_OK isn't the sig check failed +#define BOOT_PARSED_BLOCK_DIAGNOSTIC_HASH_FOR_VERIFY 0x2 // if this is present and VERIFIED_OL isn't then hash check failed +#define BOOT_PARSED_BLOCK_DIAGNOSTIC_VERIFIED_OK 0x4 + +#define BOOT_TBYB_AND_UPDATE_FLAG_BUY_PENDING 0x1 +#define BOOT_TBYB_AND_UPDATE_FLAG_OTP_VERSION_APPLIED 0x2 +#define BOOT_TBYB_AND_UPDATE_FLAG_OTHER_ERASED 0x4 + +#ifndef __ASSEMBLER__ +// Limited to 3 arguments in case of varm multiplex hint (trashes Arm r3) +typedef int (*bootrom_api_callback_generic_t)(uint32_t r0, uint32_t r1, uint32_t r2); +// Return negative for error, else number of bytes transferred: +//typedef int (*bootrom_api_callback_stdout_put_blocking_t)(const uint8_t *buffer, uint32_t size); +//typedef int (*bootrom_api_callback_stdin_get_t)(uint8_t *buffer, uint32_t size); +//typedef void (*bootrom_api_callback_core1_security_setup_t)(void); +#endif + +#endif + +/*! \brief Return a bootrom lookup code based on two ASCII characters + * \ingroup pico_bootrom + * + * These codes are uses to lookup data or function addresses in the bootrom + * + * \param c1 the first character + * \param c2 the second character + * \return the 'code' to use in rom_func_lookup() or rom_data_lookup() + */ +#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8)) + +// ROM FUNCTIONS + +// RP2040 & RP2350 +#define ROM_DATA_SOFTWARE_GIT_REVISION ROM_TABLE_CODE('G', 'R') +#define ROM_FUNC_FLASH_ENTER_CMD_XIP ROM_TABLE_CODE('C', 'X') +#define ROM_FUNC_FLASH_EXIT_XIP ROM_TABLE_CODE('E', 'X') +#define ROM_FUNC_FLASH_FLUSH_CACHE ROM_TABLE_CODE('F', 'C') +#define ROM_FUNC_CONNECT_INTERNAL_FLASH ROM_TABLE_CODE('I', 'F') +#define ROM_FUNC_FLASH_RANGE_ERASE ROM_TABLE_CODE('R', 'E') +#define ROM_FUNC_FLASH_RANGE_PROGRAM ROM_TABLE_CODE('R', 'P') + + +#if PICO_RP2040 +// RP2040 only +#define ROM_FUNC_MEMCPY44 ROM_TABLE_CODE('C', '4') +#define ROM_DATA_COPYRIGHT ROM_TABLE_CODE('C', 'R') +#define ROM_FUNC_CLZ32 ROM_TABLE_CODE('L', '3') +#define ROM_FUNC_MEMCPY ROM_TABLE_CODE('M', 'C') +#define ROM_FUNC_MEMSET ROM_TABLE_CODE('M', 'S') +#define ROM_FUNC_POPCOUNT32 ROM_TABLE_CODE('P', '3') +#define ROM_FUNC_REVERSE32 ROM_TABLE_CODE('R', '3') +#define ROM_FUNC_MEMSET4 ROM_TABLE_CODE('S', '4') +#define ROM_FUNC_CTZ32 ROM_TABLE_CODE('T', '3') +#define ROM_FUNC_RESET_USB_BOOT ROM_TABLE_CODE('U', 'B') +#endif + +#if !PICO_RP2040 || PICO_COMBINED_DOCS +// RP2350 only +#define ROM_FUNC_PICK_AB_PARTITION ROM_TABLE_CODE('A', 'B') +#define ROM_FUNC_CHAIN_IMAGE ROM_TABLE_CODE('C', 'I') +#define ROM_FUNC_EXPLICIT_BUY ROM_TABLE_CODE('E', 'B') +#define ROM_FUNC_FLASH_RUNTIME_TO_STORAGE_ADDR ROM_TABLE_CODE('F', 'A') +#define ROM_DATA_FLASH_DEVINFO16_PTR ROM_TABLE_CODE('F', 'D') +#define ROM_FUNC_FLASH_OP ROM_TABLE_CODE('F', 'O') +#define ROM_FUNC_GET_B_PARTITION ROM_TABLE_CODE('G', 'B') +#define ROM_FUNC_GET_PARTITION_TABLE_INFO ROM_TABLE_CODE('G', 'P') +#define ROM_FUNC_GET_SYS_INFO ROM_TABLE_CODE('G', 'S') +#define ROM_FUNC_GET_UF2_TARGET_PARTITION ROM_TABLE_CODE('G', 'U') +#define ROM_FUNC_LOAD_PARTITION_TABLE ROM_TABLE_CODE('L', 'P') +#define ROM_FUNC_OTP_ACCESS ROM_TABLE_CODE('O', 'A') +#define ROM_DATA_PARTITION_TABLE_PTR ROM_TABLE_CODE('P', 'T') +#define ROM_FUNC_FLASH_RESET_ADDRESS_TRANS ROM_TABLE_CODE('R', 'A') +#define ROM_FUNC_REBOOT ROM_TABLE_CODE('R', 'B') +#define ROM_FUNC_SET_ROM_CALLBACK ROM_TABLE_CODE('R', 'C') +#define ROM_FUNC_SECURE_CALL ROM_TABLE_CODE('S', 'C') +#define ROM_FUNC_SET_NS_API_PERMISSION ROM_TABLE_CODE('S', 'P') +#define ROM_FUNC_BOOTROM_STATE_RESET ROM_TABLE_CODE('S', 'R') +#define ROM_FUNC_SET_BOOTROM_STACK ROM_TABLE_CODE('S', 'S') +#define ROM_DATA_SAVED_XIP_SETUP_FUNC_PTR ROM_TABLE_CODE('X', 'F') +#define ROM_FUNC_FLASH_SELECT_XIP_READ_MODE ROM_TABLE_CODE('X', 'M') +#define ROM_FUNC_VALIDATE_NS_BUFFER ROM_TABLE_CODE('V', 'B') +#endif + +// these form a bit set +#define BOOTROM_STATE_RESET_CURRENT_CORE 0x01 +#define BOOTROM_STATE_RESET_OTHER_CORE 0x02 +#define BOOTROM_STATE_RESET_GLOBAL_STATE 0x04 // reset any global state (e.g. permissions) + +// partition level stuff is returned first (note PT_INFO flags is only 16 bits) + +// 3 words: pt_count, unpartitioned_perm_loc, unpartioned_perm_flags +#define PT_INFO_PT_INFO 0x0001 +#define PT_INFO_SINGLE_PARTITION 0x8000 // marker to just include a single partition in the results) + +// then in order per partition selected + +// 2 words: unpartitioned_perm_loc, unpartioned_perm_flags +#define PT_INFO_PARTITION_LOCATION_AND_FLAGS 0x0010 +// 2 words: id lsb first +#define PT_INFO_PARTITION_ID 0x0020 +// n+1 words: n, family_id... +#define PT_INFO_PARTITION_FAMILY_IDS 0x0040 +// (n+3)/4 words... bytes are: n (len), c0, c1, ... cn-1 padded to word boundary with zeroes +#define PT_INFO_PARTITION_NAME 0x0080 + +// items are returned in order +// 3 words package_id, device_id, wafer_id +#define SYS_INFO_CHIP_INFO 0x0001 +// 1 word: chip specific critical bits +#define SYS_INFO_CRITICAL 0x0002 +// 1 word: bytes: cpu_type, supported_cpu_type_bitfield +#define SYS_INFO_CPU_INFO 0x0004 +// 1 word: same as FLASH_DEVINFO row in OTP +#define SYS_INFO_FLASH_DEV_INFO 0x0008 +// 4 words +#define SYS_INFO_BOOT_RANDOM 0x0010 +// 2 words lsb first +#define SYS_INFO_NONCE 0x0020 +// 4 words boot_info, boot_diagnostic, boot_param0, boot_param1 +#define SYS_INFO_BOOT_INFO 0x0040 + +#define BOOTROM_NS_API_get_sys_info 0 +#define BOOTROM_NS_API_checked_flash_op 1 +#define BOOTROM_NS_API_flash_runtime_to_storage_addr 2 +#define BOOTROM_NS_API_get_partition_table_info 3 +#define BOOTROM_NS_API_secure_call 4 +#define BOOTROM_NS_API_otp_access 5 +#define BOOTROM_NS_API_reboot 6 +#define BOOTROM_NS_API_get_b_partition 7 +#define BOOTROM_NS_API_COUNT 8 + +#ifndef __ASSEMBLER__ + +typedef struct { + uint32_t permissions_and_location; + uint32_t permissions_and_flags; +} resident_partition_t; +static_assert(sizeof(resident_partition_t) == 8, ""); + +#define OTP_CMD_ROW_BITS 0x0000ffffu +#define OTP_CMD_ROW_LSB 0u +#define OTP_CMD_WRITE_BITS 0x00010000u +#define OTP_CMD_ECC_BITS 0x00020000u + +typedef struct otp_cmd { + uint32_t flags; +} otp_cmd_t; + +typedef enum { + BOOTROM_XIP_MODE_03H_SERIAL = 0, + BOOTROM_XIP_MODE_0BH_SERIAL, + BOOTROM_XIP_MODE_BBH_DUAL, + BOOTROM_XIP_MODE_EBH_QUAD, + BOOTROM_XIP_MODE_N_MODES +} bootrom_xip_mode_t; + +// The checked flash API wraps the low-level flash routines from generic_flash, adding bounds +// checking, permission checking against the resident partition table, and simple address +// translation. The low-level API deals with flash offsets (i.e. distance from the start of the +// first flash device, measured in bytes) but the checked flash API accepts one of two types of +// address: +// +// - Flash runtime addresses: the address of some flash-resident data or code in the currently +// running image. The flash addresses your binary is "linked at" by the linker. +// - Flash storage addresses: a flash offset, plus the address base where QSPI hardware is first +// mapped on the system bus (XIP_BASE constant from addressmap.h) +// +// These addresses are one and the same *if* the currently running program is stored at the +// beginning of flash. They are different if the start of your image has been "rolled" by the flash +// boot path to make it appear at the address it was linked at even though it is stored at a +// different location in flash, which is necessary when you have A/B images for example. +// +// The address translation between flash runtime and flash storage addresses is configured in +// hardware by the QMI_ATRANSx registers, and this API assumes those registers contain a valid +// address mapping which it can use to translate runtime to storage addresses. + +typedef struct cflash_flags { + uint32_t flags; +} cflash_flags_t; + +// Bits which are permitted to be set in a flags variable -- any other bits being set is an error +#define CFLASH_FLAGS_BITS 0x00070301u + +// Used to tell checked flash API which space a given address belongs to +#define CFLASH_ASPACE_BITS 0x00000001u +#define CFLASH_ASPACE_LSB 0u +#define CFLASH_ASPACE_VALUE_STORAGE 0u +#define CFLASH_ASPACE_VALUE_RUNTIME 1u + +// Used to tell checked flash APIs the effective security level of a flash access (may be forced to +// one of these values for the NonSecure-exported version of this API) +#define CFLASH_SECLEVEL_BITS 0x00000300u +#define CFLASH_SECLEVEL_LSB 8u +// Zero is not a valid security level: +#define CFLASH_SECLEVEL_VALUE_SECURE 1u +#define CFLASH_SECLEVEL_VALUE_NONSECURE 2u +#define CFLASH_SECLEVEL_VALUE_BOOTLOADER 3u + +#define CFLASH_OP_BITS 0x00070000u +#define CFLASH_OP_LSB 16u +// Erase size_bytes bytes of flash, starting at address addr. Both addr and size_bytes must be a +// multiple of 4096 bytes (one flash sector). +#define CFLASH_OP_VALUE_ERASE 0u +// Program size_bytes bytes of flash, starting at address addr. Both addr and size_bytes must be a +// multiple of 256 bytes (one flash page). +#define CFLASH_OP_VALUE_PROGRAM 1u +// Read size_bytes bytes of flash, starting at address addr. There are no alignment restrictions on +// addr or size_bytes. +#define CFLASH_OP_VALUE_READ 2u +#define CFLASH_OP_MAX 2u + +#endif + +#endif diff --git a/lib/rp2040/pico/platform.h b/lib/pico-sdk/pico/platform.h similarity index 84% rename from lib/rp2040/pico/platform.h rename to lib/pico-sdk/pico/platform.h index 499bdf648de6..dca69f265242 100644 --- a/lib/rp2040/pico/platform.h +++ b/lib/pico-sdk/pico/platform.h @@ -4,10 +4,11 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _PICO_PLATFORM_H_ -#define _PICO_PLATFORM_H_ +#ifndef _PICO_PLATFORM_H +#define _PICO_PLATFORM_H #include "hardware/platform_defs.h" +#include #include #ifdef __unix__ @@ -20,15 +21,21 @@ extern "C" { #endif -#define __not_in_flash(grup) +#define __not_in_flash(group) #define __not_in_flash_func(func) func -#define __no_inline_not_in_flash_func(func) +#define __no_inline_not_in_flash_func(func) func #define __in_flash(group) #define __scratch_x(group) #define __scratch_y(group) -#define __packed_aligned +#ifndef _MSC_VER +#define __packed __attribute__((packed)) +#define __packed_aligned __packed __attribute((aligned)) +#else +// MSVC requires #pragma pack which isn't compatible with a single attribute style define #define __packed +#define __packed_aligned +#endif #define __time_critical_func(x) x #define __after_data(group) @@ -60,6 +67,9 @@ extern void tight_loop_contents(); #define PICO_WEAK_FUNCTION_DEF(x) _Pragma(__STRING(weak x)) #define PICO_WEAK_FUNCTION_IMPL_NAME(x) x +#ifndef __weak +#define __weak __attribute__((weak)) +#endif #else #ifndef __noreturn #define __noreturn __declspec(noreturn) @@ -133,6 +143,12 @@ static inline int32_t __mul_instruction(int32_t a,int32_t b) static inline void __compiler_memory_barrier(void) { } + +uint get_core_num(); + +static inline uint __get_current_exception(void) { + return 0; +} #ifdef __cplusplus } #endif diff --git a/lib/pico-sdk/rp2040/boot_stage2/BUILD.bazel b/lib/pico-sdk/rp2040/boot_stage2/BUILD.bazel new file mode 100644 index 000000000000..65c9e76b2733 --- /dev/null +++ b/lib/pico-sdk/rp2040/boot_stage2/BUILD.bazel @@ -0,0 +1,146 @@ +# Always include these libraries through //src/rp2_common:*! +# This ensures that you'll get the right headers for the MCU you're targeting. + +load("@bazel_skylib//rules:copy_file.bzl", "copy_file") +load("@bazel_skylib//rules:run_binary.bzl", "run_binary") +load("@rules_python//python:defs.bzl", "py_binary") +load("//bazel/toolchain:objcopy.bzl", "objcopy_to_bin") +load("//bazel/util:multiple_choice_flag.bzl", "declare_flag_choices", "flag_choice") +load("//bazel/util:transition.bzl", "rp2040_bootloader_binary") + +# There's a lot of implementation details in here that shouldn't be considered +# stable, so allowlist visibility to just the public-facing pieces. +package(default_visibility = ["//visibility:private"]) + +# Known choices for boot2: +BOOT2_CHOICES = [ + "boot2_at25sf128a", + "boot2_generic_03h", + "boot2_is25lp080", + "boot2_usb_blinky", + "boot2_w25q080", + "boot2_w25x10cl", + "compile_time_choice", +] + +BOOT2_CHOICE_FILES = [c + ".S" for c in BOOT2_CHOICES] + +BOOT2_CHOICE_FILE_MAP = {c: [c + ".S"] for c in BOOT2_CHOICES} + +BOOT2_CHOICE_DEFINE_MAP = {c: ['PICO_BUILD_BOOT_STAGE2_NAME=\\"{}\\"'.format(c)] for c in BOOT2_CHOICES} + +# Define shouldn't be set for compile_time_choice. +BOOT2_CHOICE_DEFINE_MAP["compile_time_choice"] = [] + +cc_library( + name = "config", + hdrs = [ + "asminclude/boot2_helpers/exit_from_boot2.S", + "asminclude/boot2_helpers/read_flash_sreg.S", + "asminclude/boot2_helpers/wait_ssi_ready.S", + "include/boot_stage2/config.h", + ] + BOOT2_CHOICE_FILES, + defines = select(flag_choice( + "//bazel/config:PICO_DEFAULT_BOOT_STAGE2", + ":__pkg__", + BOOT2_CHOICE_DEFINE_MAP, + )), + includes = [ + "asminclude", + "include", + ], + target_compatible_with = ["//bazel/constraint:rp2040"], + visibility = ["//visibility:public"], +) + +# Creates a config_setting for each known boot2 option with the name: +# PICO_DEFAULT_BOOT_STAGE2_[choice] +declare_flag_choices( + "//bazel/config:PICO_DEFAULT_BOOT_STAGE2", + BOOT2_CHOICES, +) + +filegroup( + name = "build_selected_boot2", + srcs = select(flag_choice( + "//bazel/config:PICO_DEFAULT_BOOT_STAGE2", + ":__pkg__", + BOOT2_CHOICE_FILE_MAP, + )), + visibility = ["//src/rp2_common:__pkg__"], +) + +cc_binary( + name = "boot_stage2_elf_actual", + srcs = ["//bazel/config:PICO_DEFAULT_BOOT_STAGE2_FILE"], + copts = ["-fPIC"], + # Incompatible with section garbage collection. + features = ["-gc_sections"], + linkopts = [ + "-Wl,--no-gc-sections", + "-nostartfiles", + "-Wl,--entry=_stage2_boot", + "-T$(location boot_stage2.ld)", + ], + # this does nothing if someone passes --custom_malloc, so the + # rp2040_bootloader_binary transition forcibly clobbers --custom_malloc. + malloc = "//bazel:empty_cc_lib", + tags = ["manual"], # Only build as an explicit dependency. + target_compatible_with = ["//bazel/constraint:rp2040"], + deps = [ + "boot_stage2.ld", + ":config", + "//src/common/pico_base_headers", + "//src/rp2_common:pico_platform_internal", + ], +) + +# Always build the bootloader with the bootloader-specific platform. +rp2040_bootloader_binary( + name = "boot_stage2_elf", + src = "boot_stage2_elf_actual", +) + +objcopy_to_bin( + name = "boot_stage2_bin", + src = ":boot_stage2_elf", + out = "boot_stage2.bin", + target_compatible_with = ["//bazel/constraint:rp2040"], +) + +# WORKAROUND: Python rules always require a .py extension. +copy_file( + name = "copy_tool_to_py", + src = "pad_checksum", + out = "pad_checksum_tool.py", + target_compatible_with = ["//bazel/constraint:host"], +) + +py_binary( + name = "pad_checksum_tool", + srcs = ["pad_checksum_tool.py"], + target_compatible_with = ["//bazel/constraint:host"], +) + +run_binary( + name = "boot_stage2_padded", + srcs = [":boot_stage2_bin"], + outs = ["boot_stage2.S"], + args = [ + "-s 0xffffffff", + "$(location boot_stage2_bin)", + "$(location boot_stage2.S)", + ], + target_compatible_with = ["//bazel/constraint:rp2040"], + tool = ":pad_checksum_tool", +) + +cc_library( + name = "boot_stage2", + srcs = [":boot_stage2_padded"], + target_compatible_with = ["//bazel/constraint:rp2040"], + visibility = ["//src/rp2_common:__pkg__"], + # This isn't referenced as a symbol, so alwayslink is required to ensure + # it doesn't get dropped before the linker script can find it. + alwayslink = True, +) diff --git a/lib/rp2040/boot_stage2/CMakeLists.txt b/lib/pico-sdk/rp2040/boot_stage2/CMakeLists.txt similarity index 84% rename from lib/rp2040/boot_stage2/CMakeLists.txt rename to lib/pico-sdk/rp2040/boot_stage2/CMakeLists.txt index 73c3e3e94220..c5768785b543 100644 --- a/lib/rp2040/boot_stage2/CMakeLists.txt +++ b/lib/pico-sdk/rp2040/boot_stage2/CMakeLists.txt @@ -1,10 +1,10 @@ -# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2_FILE, Default boot stage 2 file to use unless overridden by pico_set_boot_stage2 on the TARGET; this setting is useful when explicitly setting the default build from a per board CMake file, group=build -# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2, Simpler alternative to specifying PICO_DEFAULT_BOOT_STAGE2_FILE where the file is src/rp2_common/boot_stage2/{PICO_DEFAULT_BOOT_STAGE2}.S, default=compile_time_choice, group=build +# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2_FILE, Default boot stage 2 file to use unless overridden by pico_set_boot_stage2 on the TARGET; this setting is useful when explicitly setting the default build from a per board CMake file, type=string, group=build +# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2, Simpler alternative to specifying PICO_DEFAULT_BOOT_STAGE2_FILE where the latter is set to src/rp2_common/boot_stage2/{PICO_DEFAULT_BOOT_STAGE2}.S, type=string, default=compile_time_choice, group=build if (DEFINED ENV{PICO_DEFAULT_BOOT_STAGE2_FILE}) set(PICO_DEFAULT_BOOT_STAGE2_FILE $ENV{PICO_DEFAULT_BOOT_STAGE2_FILE}) message("Using PICO_DEFAULT_BOOT_STAGE2_FILE from environment ('${PICO_DEFAULT_BOOT_STAGE2_FILE}')") -elif (PICO_DEFAULT_BOOT_STAGE2_FILE) +elseif (PICO_DEFAULT_BOOT_STAGE2_FILE) # explicitly set, so cache it set(PICO_DEFAULT_BOOT_STAGE2_FILE "${PICO_DEFAULT_BOOT_STAGE2_FILE}" CACHE STRING "boot stage 2 source file" FORCE) endif() @@ -25,12 +25,13 @@ endif() if (NOT EXISTS ${PICO_DEFAULT_BOOT_STAGE2_FILE}) message(FATAL_ERROR "Specified boot stage 2 source '${PICO_DEFAULT_BOOT_STAGE2_FILE}' does not exist.") endif() +pico_register_common_scope_var(PICO_DEFAULT_BOOT_STAGE2_FILE) # needed by function below set(PICO_BOOT_STAGE2_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "") add_library(boot_stage2_headers INTERFACE) -target_include_directories(boot_stage2_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) +target_include_directories(boot_stage2_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include) # by convention the first source file name without extension is used for the binary info name function(pico_define_boot_stage2 NAME SOURCES) @@ -39,9 +40,9 @@ function(pico_define_boot_stage2 NAME SOURCES) ) # todo bit of an abstraction failure - revisit for Clang support anyway - if (CMAKE_C_COMPILER_ID STREQUAL "Clang") + if (PICO_C_COMPILER_IS_CLANG) target_link_options(${NAME} PRIVATE "-nostdlib") - else () + elseif (PICO_C_COMPILER_IS_GNU) target_link_options(${NAME} PRIVATE "--specs=nosys.specs") target_link_options(${NAME} PRIVATE "-nostartfiles") endif () @@ -62,12 +63,13 @@ function(pico_define_boot_stage2 NAME SOURCES) find_package (Python3 REQUIRED COMPONENTS Interpreter) add_custom_target(${NAME}_bin DEPENDS ${ORIGINAL_BIN}) - add_custom_command(OUTPUT ${ORIGINAL_BIN} DEPENDS ${NAME} COMMAND ${CMAKE_OBJCOPY} -Obinary $ ${ORIGINAL_BIN}) + add_custom_command(OUTPUT ${ORIGINAL_BIN} DEPENDS ${NAME} COMMAND ${CMAKE_OBJCOPY} -Obinary $ ${ORIGINAL_BIN} + VERBATIM) add_custom_target(${NAME}_padded_checksummed_asm DEPENDS ${PADDED_CHECKSUMMED_ASM}) add_custom_command(OUTPUT ${PADDED_CHECKSUMMED_ASM} DEPENDS ${ORIGINAL_BIN} COMMAND ${Python3_EXECUTABLE} ${PICO_BOOT_STAGE2_DIR}/pad_checksum -s 0xffffffff ${ORIGINAL_BIN} ${PADDED_CHECKSUMMED_ASM} - ) + VERBATIM) add_library(${NAME}_library INTERFACE) add_dependencies(${NAME}_library ${NAME}_padded_checksummed_asm) @@ -98,3 +100,9 @@ endmacro() pico_define_boot_stage2(bs2_default ${PICO_DEFAULT_BOOT_STAGE2_FILE}) +# Create a new boot stage 2 target using the default implementation for the current build (PICO_BOARD derived) +function(pico_clone_default_boot_stage2 NAME) + pico_define_boot_stage2(${NAME} ${PICO_DEFAULT_BOOT_STAGE2_FILE}) +endfunction() + +pico_promote_common_scope_vars() diff --git a/lib/rp2040/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S b/lib/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S similarity index 100% rename from lib/rp2040/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S rename to lib/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S diff --git a/lib/rp2040/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S b/lib/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S similarity index 100% rename from lib/rp2040/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S rename to lib/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S diff --git a/lib/rp2040/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S b/lib/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S similarity index 100% rename from lib/rp2040/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S rename to lib/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S diff --git a/lib/rp2040/boot_stage2/boot2_at25sf128a.S b/lib/pico-sdk/rp2040/boot_stage2/boot2_at25sf128a.S similarity index 95% rename from lib/rp2040/boot_stage2/boot2_at25sf128a.S rename to lib/pico-sdk/rp2040/boot_stage2/boot2_at25sf128a.S index be232ff11231..72f751ed9875 100644 --- a/lib/rp2040/boot_stage2/boot2_at25sf128a.S +++ b/lib/pico-sdk/rp2040/boot_stage2/boot2_at25sf128a.S @@ -86,21 +86,18 @@ // Start of 2nd Stage Boot Code // ---------------------------------------------------------------------------- -.syntax unified -.cpu cortex-m0plus -.thumb +pico_default_asm_setup .section .text -// The exit point is passed in lr. If entered from bootrom, this will be the -// flash address immediately following this second stage (0x10000100). -// Otherwise it will be a return address -- second stage being called as a -// function by user code, after copying out of XIP region. r3 holds SSI base, -// r0...2 used as temporaries. Other GPRs not used. -.global _stage2_boot -.type _stage2_boot,%function -.thumb_func -_stage2_boot: +// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected +// to continue into the binary via the vector table at 0x10000100. +// +// lr will be non-zero on entry if this code has been copied into RAM by user code and called +// from there, and the boot_stage2 should just return normally. +// +// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. +regular_func _stage2_boot push {lr} // Set pad configuration: diff --git a/lib/rp2040/boot_stage2/boot2_generic_03h.S b/lib/pico-sdk/rp2040/boot_stage2/boot2_generic_03h.S similarity index 86% rename from lib/rp2040/boot_stage2/boot2_generic_03h.S rename to lib/pico-sdk/rp2040/boot_stage2/boot2_generic_03h.S index cc7e4fbc7e4e..effef930b129 100644 --- a/lib/rp2040/boot_stage2/boot2_generic_03h.S +++ b/lib/pico-sdk/rp2040/boot_stage2/boot2_generic_03h.S @@ -16,10 +16,12 @@ // 4-byte checksum. Therefore code size cannot exceed 252 bytes. // ---------------------------------------------------------------------------- -//#include "pico/asm_helper.S" +#include "pico/asm_helper.S" #include "hardware/regs/addressmap.h" #include "hardware/regs/ssi.h" +pico_default_asm_setup + // ---------------------------------------------------------------------------- // Config section // ---------------------------------------------------------------------------- @@ -53,25 +55,26 @@ // Start of 2nd Stage Boot Code // ---------------------------------------------------------------------------- -.cpu cortex-m0 -.thumb - .section .text -.global _stage2_boot -.type _stage2_boot,%function -.thumb_func -_stage2_boot: +// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected +// to continue into the binary via the vector table at 0x10000100. +// +// lr will be non-zero on entry if this code has been copied into RAM by user code and called +// from there, and the boot_stage2 should just return normally. +// +// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. +regular_func _stage2_boot push {lr} ldr r3, =XIP_SSI_BASE // Use as base address where possible // Disable SSI to allow further config - mov r1, #0 + movs r1, #0 str r1, [r3, #SSI_SSIENR_OFFSET] // Set baud rate - mov r1, #PICO_FLASH_SPI_CLKDIV + movs r1, #PICO_FLASH_SPI_CLKDIV str r1, [r3, #SSI_BAUDR_OFFSET] ldr r1, =(CTRLR0_XIP) @@ -82,11 +85,11 @@ _stage2_boot: str r1, [r0] // NDF=0 (single 32b read) - mov r1, #0x0 + movs r1, #0x0 str r1, [r3, #SSI_CTRLR1_OFFSET] // Re-enable SSI - mov r1, #1 + movs r1, #1 str r1, [r3, #SSI_SSIENR_OFFSET] // We are now in XIP mode. Any bus accesses to the XIP address window will be diff --git a/lib/rp2040/boot_stage2/boot2_is25lp080.S b/lib/pico-sdk/rp2040/boot_stage2/boot2_is25lp080.S similarity index 91% rename from lib/rp2040/boot_stage2/boot2_is25lp080.S rename to lib/pico-sdk/rp2040/boot_stage2/boot2_is25lp080.S index 80bf9d1100d8..fda0f992f850 100644 --- a/lib/rp2040/boot_stage2/boot2_is25lp080.S +++ b/lib/pico-sdk/rp2040/boot_stage2/boot2_is25lp080.S @@ -80,25 +80,27 @@ // Start of 2nd Stage Boot Code // ---------------------------------------------------------------------------- -.cpu cortex-m0 -.thumb +pico_default_asm_setup .section .text - -.global _stage2_boot -.type _stage2_boot,%function -.thumb_func -_stage2_boot: +// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected +// to continue into the binary via the vector table at 0x10000100. +// +// lr will be non-zero on entry if this code has been copied into RAM by user code and called +// from there, and the boot_stage2 should just return normally. +// +// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. +regular_func _stage2_boot push {lr} ldr r3, =XIP_SSI_BASE // Use as base address where possible // Disable SSI to allow further config - mov r1, #0 + movs r1, #0 str r1, [r3, #SSI_SSIENR_OFFSET] // Set baud rate - mov r1, #PICO_FLASH_SPI_CLKDIV + movs r1, #PICO_FLASH_SPI_CLKDIV str r1, [r3, #SSI_BAUDR_OFFSET] // On QSPI parts we usually need a 01h SR-write command to enable QSPI mode @@ -113,7 +115,7 @@ program_sregs: str r1, [r3, #SSI_CTRLR0_OFFSET] // Enable SSI and select slave 0 - mov r1, #1 + movs r1, #1 str r1, [r3, #SSI_SSIENR_OFFSET] // Check whether SR needs updating @@ -124,7 +126,7 @@ program_sregs: beq skip_sreg_programming // Send write enable command - mov r1, #CMD_WRITE_ENABLE + movs r1, #CMD_WRITE_ENABLE str r1, [r3, #SSI_DR0_OFFSET] // Poll for completion and discard RX @@ -132,9 +134,9 @@ program_sregs: ldr r1, [r3, #SSI_DR0_OFFSET] // Send status write command followed by data bytes - mov r1, #CMD_WRITE_STATUS + movs r1, #CMD_WRITE_STATUS str r1, [r3, #SSI_DR0_OFFSET] - mov r0, #0 + movs r0, #0 str r2, [r3, #SSI_DR0_OFFSET] bl wait_ssi_ready @@ -145,7 +147,7 @@ program_sregs: 1: ldr r0, =CMD_READ_STATUS bl read_flash_sreg - mov r1, #1 + movs r1, #1 tst r0, r1 bne 1b @@ -157,7 +159,7 @@ skip_sreg_programming: // bl wait_ssi_ready // Disable SSI again so that it can be reconfigured - mov r1, #0 + movs r1, #0 str r1, [r3, #SSI_SSIENR_OFFSET] #endif @@ -182,7 +184,7 @@ dummy_read: ldr r1, =(CTRLR0_ENTER_XIP) str r1, [r3, #SSI_CTRLR0_OFFSET] - mov r1, #0x0 // NDF=0 (single 32b read) + movs r1, #0x0 // NDF=0 (single 32b read) str r1, [r3, #SSI_CTRLR1_OFFSET] #define SPI_CTRLR0_ENTER_XIP \ @@ -197,12 +199,12 @@ dummy_read: ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register str r1, [r0] - mov r1, #1 // Re-enable SSI + movs r1, #1 // Re-enable SSI str r1, [r3, #SSI_SSIENR_OFFSET] - mov r1, #CMD_READ + movs r1, #CMD_READ str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO - mov r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010 + movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction // Poll for completion @@ -218,7 +220,7 @@ dummy_read: // to APM mode and generate a 28-bit address phase with the extra nibble set // to 4'b0000). - mov r1, #0 + movs r1, #0 str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config // Note that the INST_L field is used to select what XIP data gets pushed into @@ -240,7 +242,7 @@ configure_ssi: ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) str r1, [r0] - mov r1, #1 + movs r1, #1 str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI // We are now in XIP mode, with all transactions using Dual I/O and only diff --git a/lib/rp2040/boot_stage2/boot2_usb_blinky.S b/lib/pico-sdk/rp2040/boot_stage2/boot2_usb_blinky.S similarity index 84% rename from lib/rp2040/boot_stage2/boot2_usb_blinky.S rename to lib/pico-sdk/rp2040/boot_stage2/boot2_usb_blinky.S index 74c47a3ec128..0249a455a566 100644 --- a/lib/rp2040/boot_stage2/boot2_usb_blinky.S +++ b/lib/pico-sdk/rp2040/boot_stage2/boot2_usb_blinky.S @@ -4,6 +4,8 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include "pico/asm_helper.S" + // Stub second stage which calls into USB bootcode, with parameters. // USB boot takes two parameters: // - A GPIO mask for activity LED -- if mask is 0, don't touch GPIOs at all @@ -19,17 +21,12 @@ #define ACTIVITY_LED 0 #define BOOT_MODE USB_BOOT_MSD_AND_PICOBOOT -.cpu cortex-m0 -.thumb +pico_default_asm_setup .section .text -.global _stage2_boot -.type _stage2_boot,%function - -.thumb_func -_stage2_boot: - mov r7, #0x14 // Pointer to _well_known pointer table in ROM +regular_func _stage2_boot + movs r7, #0x14 // Pointer to _well_known pointer table in ROM ldrh r0, [r7, #0] // Offset 0 is 16 bit pointer to function table ldrh r7, [r7, #4] // Offset 4 is 16 bit pointer to table lookup routine ldr r1, =('U' | ('B' << 8)) // Symbol for USB Boot @@ -39,7 +36,7 @@ _stage2_boot: mov r7, r0 ldr r0, =(1u << ACTIVITY_LED) // Mask of which GPIO (or GPIOs) to use - mov r1, #BOOT_MODE + movs r1, #BOOT_MODE blx r7 dead: diff --git a/lib/rp2040/boot_stage2/boot2_w25q080.S b/lib/pico-sdk/rp2040/boot_stage2/boot2_w25q080.S similarity index 95% rename from lib/rp2040/boot_stage2/boot2_w25q080.S rename to lib/pico-sdk/rp2040/boot_stage2/boot2_w25q080.S index 8fb3def4c426..c35fb81fa33e 100644 --- a/lib/rp2040/boot_stage2/boot2_w25q080.S +++ b/lib/pico-sdk/rp2040/boot_stage2/boot2_w25q080.S @@ -26,7 +26,7 @@ // 4-byte checksum. Therefore code size cannot exceed 252 bytes. // ---------------------------------------------------------------------------- -//#include "pico/asm_helper.S" +#include "pico/asm_helper.S" #include "hardware/regs/addressmap.h" #include "hardware/regs/ssi.h" #include "hardware/regs/pads_qspi.h" @@ -86,21 +86,18 @@ // Start of 2nd Stage Boot Code // ---------------------------------------------------------------------------- -.syntax unified -.cpu cortex-m0plus -.thumb +pico_default_asm_setup .section .text -// The exit point is passed in lr. If entered from bootrom, this will be the -// flash address immediately following this second stage (0x10000100). -// Otherwise it will be a return address -- second stage being called as a -// function by user code, after copying out of XIP region. r3 holds SSI base, -// r0...2 used as temporaries. Other GPRs not used. -.global _stage2_boot -.type _stage2_boot,%function -.thumb_func -_stage2_boot: +// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected +// to continue into the binary via the vector table at 0x10000100. +// +// lr will be non-zero on entry if this code has been copied into RAM by user code and called +// from there, and the boot_stage2 should just return normally. +// +// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. +regular_func _stage2_boot push {lr} // Set pad configuration: diff --git a/lib/rp2040/boot_stage2/boot2_w25x10cl.S b/lib/pico-sdk/rp2040/boot_stage2/boot2_w25x10cl.S similarity index 91% rename from lib/rp2040/boot_stage2/boot2_w25x10cl.S rename to lib/pico-sdk/rp2040/boot_stage2/boot2_w25x10cl.S index 02628d4eb5dd..9aa51ac576bf 100644 --- a/lib/rp2040/boot_stage2/boot2_w25x10cl.S +++ b/lib/pico-sdk/rp2040/boot_stage2/boot2_w25x10cl.S @@ -40,6 +40,8 @@ #define PICO_FLASH_SPI_CLKDIV 4 #endif +pico_default_asm_setup + // ---------------------------------------------------------------------------- // The "System Control Block" is a set of internal Cortex-M0+ control registers // that are memory mapped and accessed like any other H/W register. They have @@ -69,31 +71,30 @@ // Start of 2nd Stage Boot Code // ---------------------------------------------------------------------------- -.cpu cortex-m0 -.thumb - .org 0 .section .text -// This code will get copied to 0x20000000 and then executed - -.global _stage2_boot -.type _stage2_boot,%function -.thumb_func -_stage2_boot: +// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected +// to continue into the binary via the vector table at 0x10000100. +// +// lr will be non-zero on entry if this code has been copied into RAM by user code and called +// from there, and the boot_stage2 should just return normally. +// +// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used. +regular_func _stage2_boot push {lr} ldr r3, =XIP_SSI_BASE // Use as base address where possible // We are primarily interested in setting up Flash for DSPI XIP w/ continuous read - mov r1, #0 + movs r1, #0 str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI to allow further config // The Boot ROM sets a very conservative SPI clock frequency to be sure it can // read the initial 256 bytes from any device. Here we can be more aggressive. - mov r1, #PICO_FLASH_SPI_CLKDIV + movs r1, #PICO_FLASH_SPI_CLKDIV str r1, [r3, #SSI_BAUDR_OFFSET] // Set SSI Clock // First we need to send the initial command to get us in to Fast Read Dual I/O @@ -116,7 +117,7 @@ _stage2_boot: ldr r1, =(CTRLR0_ENTER_XIP) str r1, [r3, #SSI_CTRLR0_OFFSET] - mov r1, #0x0 // NDF=0 (single 32b read) + movs r1, #0x0 // NDF=0 (single 32b read) str r1, [r3, #SSI_CTRLR1_OFFSET] #define SPI_CTRLR0_ENTER_XIP \ @@ -131,18 +132,18 @@ _stage2_boot: ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register str r1, [r0] - mov r1, #1 // Re-enable SSI + movs r1, #1 // Re-enable SSI str r1, [r3, #SSI_SSIENR_OFFSET] - mov r1, #W25X10CL_CMD_READ_DATA_FAST_DUAL_IO // 8b command = 0xBB + movs r1, #W25X10CL_CMD_READ_DATA_FAST_DUAL_IO // 8b command = 0xBB str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO - mov r1, #0x0000002 // 28-bit Address for dummy read = 0x000000 + 0x2 Mode bits to set M[5:4]=10 + movs r1, #0x0000002 // 28-bit Address for dummy read = 0x000000 + 0x2 Mode bits to set M[5:4]=10 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction // Now we wait for the read transaction to complete by monitoring the SSI // status register and checking for the "RX FIFO Not Empty" flag to assert. - mov r1, #SSI_SR_RFNE_BITS + movs r1, #SSI_SR_RFNE_BITS 00: ldr r0, [r3, #SSI_SR_OFFSET] // Read status register tst r0, r1 // RFNE status flag set? @@ -158,7 +159,7 @@ _stage2_boot: // to APM mode and generate a 28-bit address phase with the extra nibble set // to 4'b0000). - mov r1, #0 + movs r1, #0 str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config // Note that the INST_L field is used to select what XIP data gets pushed into @@ -180,7 +181,7 @@ _stage2_boot: ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) str r1, [r0] - mov r1, #1 + movs r1, #1 str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI // We are now in XIP mode, with all transactions using Dual I/O and only diff --git a/lib/rp2040/boot_stage2/boot_stage2.ld b/lib/pico-sdk/rp2040/boot_stage2/boot_stage2.ld similarity index 100% rename from lib/rp2040/boot_stage2/boot_stage2.ld rename to lib/pico-sdk/rp2040/boot_stage2/boot_stage2.ld diff --git a/lib/rp2040/boot_stage2/compile_time_choice.S b/lib/pico-sdk/rp2040/boot_stage2/compile_time_choice.S similarity index 100% rename from lib/rp2040/boot_stage2/compile_time_choice.S rename to lib/pico-sdk/rp2040/boot_stage2/compile_time_choice.S diff --git a/lib/rp2040/boot_stage2/doc.h b/lib/pico-sdk/rp2040/boot_stage2/doc.h similarity index 100% rename from lib/rp2040/boot_stage2/doc.h rename to lib/pico-sdk/rp2040/boot_stage2/doc.h diff --git a/lib/rp2040/boot_stage2/include/boot_stage2/config.h b/lib/pico-sdk/rp2040/boot_stage2/include/boot_stage2/config.h similarity index 91% rename from lib/rp2040/boot_stage2/include/boot_stage2/config.h rename to lib/pico-sdk/rp2040/boot_stage2/include/boot_stage2/config.h index 5e57f953d48d..e4d32628cec8 100644 --- a/lib/rp2040/boot_stage2/include/boot_stage2/config.h +++ b/lib/pico-sdk/rp2040/boot_stage2/include/boot_stage2/config.h @@ -4,12 +4,12 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _BOOT_STAGE2_CONFIG_H_ -#define _BOOT_STAGE2_CONFIG_H_ +#ifndef _BOOT_STAGE2_CONFIG_H +#define _BOOT_STAGE2_CONFIG_H // NOTE THIS HEADER IS INCLUDED FROM ASSEMBLY -#include "pico/config.h" +#include "pico.h" // PICO_CONFIG: PICO_BUILD_BOOT_STAGE2_NAME, The name of the boot stage 2 if selected by the build, group=boot_stage2 #ifdef PICO_BUILD_BOOT_STAGE2_NAME @@ -85,10 +85,7 @@ #error no boot stage 2 is defined by PICO_BOOT_STAGE2_CHOOSE_ macro #endif // we can't include cdefs in assembly, so define our own, but avoid conflict with real ones for c inclusion - #define _PICO__STRING(x) #x - #define _PICO__XSTRING(x) _PICO__STRING(x) - #define _PICO__CONCAT1(x, y) x ## y - #define PICO_BOOT_STAGE2_NAME _PICO__XSTRING(_BOOT_STAGE2) - #define PICO_BOOT_STAGE2_ASM _PICO__XSTRING(_PICO__CONCAT1(_BOOT_STAGE2,.S)) + #define PICO_BOOT_STAGE2_NAME __PICO_XSTRING(_BOOT_STAGE2) + #define PICO_BOOT_STAGE2_ASM __PICO_XSTRING(__PICO_CONCAT1(_BOOT_STAGE2,.S)) #endif #endif diff --git a/lib/rp2040/boot_stage2/pad_checksum b/lib/pico-sdk/rp2040/boot_stage2/pad_checksum similarity index 98% rename from lib/rp2040/boot_stage2/pad_checksum rename to lib/pico-sdk/rp2040/boot_stage2/pad_checksum index 356227d589f9..d3017568264c 100755 --- a/lib/rp2040/boot_stage2/pad_checksum +++ b/lib/pico-sdk/rp2040/boot_stage2/pad_checksum @@ -31,7 +31,7 @@ try: except: sys.exit("Could not open input file '{}'".format(args.ifile)) -if len(idata) >= args.pad - 4: +if len(idata) > args.pad - 4: sys.exit("Input file size ({} bytes) too large for final size ({} bytes)".format(len(idata), args.pad)) idata_padded = idata + bytes(args.pad - 4 - len(idata)) diff --git a/lib/pico-sdk/rp2040/cmsis_include/RP2040.h b/lib/pico-sdk/rp2040/cmsis_include/RP2040.h new file mode 100644 index 000000000000..be661392c0f7 --- /dev/null +++ b/lib/pico-sdk/rp2040/cmsis_include/RP2040.h @@ -0,0 +1,2675 @@ +/* + * Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + * + * @file src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/RP2040.h + * @brief CMSIS HeaderFile + * @version 0.1 + * @date Tue Aug 6 18:22:05 2024 + * @note Generated by SVDConv V3.3.47 + * from File 'src/rp2_common/cmsis/../../rp2040/hardware_regs/RP2040.svd', + * last modified on Tue Aug 6 17:58:50 2024 + */ + + +/** @addtogroup Raspberry Pi + * @{ + */ + + +/** @addtogroup RP2040 + * @{ + */ + + +#ifndef RP2040_H +#define RP2040_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* =========================================== RP2040 Specific Interrupt Numbers =========================================== */ + TIMER_IRQ_0_IRQn = 0, /*!< 0 TIMER_IRQ_0 */ + TIMER_IRQ_1_IRQn = 1, /*!< 1 TIMER_IRQ_1 */ + TIMER_IRQ_2_IRQn = 2, /*!< 2 TIMER_IRQ_2 */ + TIMER_IRQ_3_IRQn = 3, /*!< 3 TIMER_IRQ_3 */ + PWM_IRQ_WRAP_IRQn = 4, /*!< 4 PWM_IRQ_WRAP */ + USBCTRL_IRQ_IRQn = 5, /*!< 5 USBCTRL_IRQ */ + XIP_IRQ_IRQn = 6, /*!< 6 XIP_IRQ */ + PIO0_IRQ_0_IRQn = 7, /*!< 7 PIO0_IRQ_0 */ + PIO0_IRQ_1_IRQn = 8, /*!< 8 PIO0_IRQ_1 */ + PIO1_IRQ_0_IRQn = 9, /*!< 9 PIO1_IRQ_0 */ + PIO1_IRQ_1_IRQn = 10, /*!< 10 PIO1_IRQ_1 */ + DMA_IRQ_0_IRQn = 11, /*!< 11 DMA_IRQ_0 */ + DMA_IRQ_1_IRQn = 12, /*!< 12 DMA_IRQ_1 */ + IO_IRQ_BANK0_IRQn = 13, /*!< 13 IO_IRQ_BANK0 */ + IO_IRQ_QSPI_IRQn = 14, /*!< 14 IO_IRQ_QSPI */ + SIO_IRQ_PROC0_IRQn = 15, /*!< 15 SIO_IRQ_PROC0 */ + SIO_IRQ_PROC1_IRQn = 16, /*!< 16 SIO_IRQ_PROC1 */ + CLOCKS_IRQ_IRQn = 17, /*!< 17 CLOCKS_IRQ */ + SPI0_IRQ_IRQn = 18, /*!< 18 SPI0_IRQ */ + SPI1_IRQ_IRQn = 19, /*!< 19 SPI1_IRQ */ + UART0_IRQ_IRQn = 20, /*!< 20 UART0_IRQ */ + UART1_IRQ_IRQn = 21, /*!< 21 UART1_IRQ */ + ADC_IRQ_FIFO_IRQn = 22, /*!< 22 ADC_IRQ_FIFO */ + I2C0_IRQ_IRQn = 23, /*!< 23 I2C0_IRQ */ + I2C1_IRQ_IRQn = 24, /*!< 24 I2C1_IRQ */ + RTC_IRQ_IRQn = 25 /*!< 25 RTC_IRQ */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 0 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ +#include "system_RP2040.h" /*!< RP2040 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ RESETS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief RESETS (RESETS) + */ + +typedef struct { /*!< RESETS Structure */ + __IOM uint32_t RESET; /*!< Reset control. If a bit is set it means the peripheral is in + reset. 0 means the peripheral's reset is deasserted. */ + __IOM uint32_t WDSEL; /*!< Watchdog select. If a bit is set then the watchdog will reset + this peripheral when the watchdog fires. */ + __IOM uint32_t RESET_DONE; /*!< Reset done. If a bit is set then a reset done signal has been + returned by the peripheral. This indicates that the peripheral's + registers are ready to be accessed. */ +} RESETS_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ PSM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PSM (PSM) + */ + +typedef struct { /*!< PSM Structure */ + __IOM uint32_t FRCE_ON; /*!< Force block out of reset (i.e. power it on) */ + __IOM uint32_t FRCE_OFF; /*!< Force into reset (i.e. power it off) */ + __IOM uint32_t WDSEL; /*!< Set to 1 if this peripheral should be reset when the watchdog + fires. */ + __IOM uint32_t DONE; /*!< Indicates the peripheral's registers are ready to access. */ +} PSM_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCKS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CLOCKS (CLOCKS) + */ + +typedef struct { /*!< CLOCKS Structure */ + __IOM uint32_t CLK_GPOUT0_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT0_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_GPOUT0_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_GPOUT1_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT1_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_GPOUT1_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_GPOUT2_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT2_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_GPOUT2_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_GPOUT3_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT3_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_GPOUT3_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_REF_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_REF_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_REF_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_SYS_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_SYS_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_SYS_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_PERI_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_PERI_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_PERI_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_USB_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_USB_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_USB_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_ADC_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_ADC_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_ADC_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_RTC_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_RTC_DIV; /*!< Clock divisor, can be changed on-the-fly */ + __IOM uint32_t CLK_RTC_SELECTED; /*!< Indicates which SRC is currently selected by the glitchless + mux (one-hot). */ + __IOM uint32_t CLK_SYS_RESUS_CTRL; /*!< CLK_SYS_RESUS_CTRL */ + __IOM uint32_t CLK_SYS_RESUS_STATUS; /*!< CLK_SYS_RESUS_STATUS */ + __IOM uint32_t FC0_REF_KHZ; /*!< Reference clock frequency in kHz */ + __IOM uint32_t FC0_MIN_KHZ; /*!< Minimum pass frequency in kHz. This is optional. Set to 0 if + you are not using the pass/fail flags */ + __IOM uint32_t FC0_MAX_KHZ; /*!< Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff + if you are not using the pass/fail flags */ + __IOM uint32_t FC0_DELAY; /*!< Delays the start of frequency counting to allow the mux to settle + Delay is measured in multiples of the reference clock period */ + __IOM uint32_t FC0_INTERVAL; /*!< The test interval is 0.98us * 2**interval, but let's call it + 1us * 2**interval The default gives a test interval of + 250us */ + __IOM uint32_t FC0_SRC; /*!< Clock sent to frequency counter, set to 0 when not required + Writing to this register initiates the frequency count */ + __IOM uint32_t FC0_STATUS; /*!< Frequency counter status */ + __IOM uint32_t FC0_RESULT; /*!< Result of frequency measurement, only valid when status_done=1 */ + __IOM uint32_t WAKE_EN0; /*!< enable clock in wake mode */ + __IOM uint32_t WAKE_EN1; /*!< enable clock in wake mode */ + __IOM uint32_t SLEEP_EN0; /*!< enable clock in sleep mode */ + __IOM uint32_t SLEEP_EN1; /*!< enable clock in sleep mode */ + __IOM uint32_t ENABLED0; /*!< indicates the state of the clock enable */ + __IOM uint32_t ENABLED1; /*!< indicates the state of the clock enable */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} CLOCKS_Type; /*!< Size = 200 (0xc8) */ + + + +/* =========================================================================================================================== */ +/* ================ PADS_BANK0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PADS_BANK0 (PADS_BANK0) + */ + +typedef struct { /*!< PADS_BANK0 Structure */ + __IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */ + __IOM uint32_t GPIO0; /*!< Pad control register */ + __IOM uint32_t GPIO1; /*!< Pad control register */ + __IOM uint32_t GPIO2; /*!< Pad control register */ + __IOM uint32_t GPIO3; /*!< Pad control register */ + __IOM uint32_t GPIO4; /*!< Pad control register */ + __IOM uint32_t GPIO5; /*!< Pad control register */ + __IOM uint32_t GPIO6; /*!< Pad control register */ + __IOM uint32_t GPIO7; /*!< Pad control register */ + __IOM uint32_t GPIO8; /*!< Pad control register */ + __IOM uint32_t GPIO9; /*!< Pad control register */ + __IOM uint32_t GPIO10; /*!< Pad control register */ + __IOM uint32_t GPIO11; /*!< Pad control register */ + __IOM uint32_t GPIO12; /*!< Pad control register */ + __IOM uint32_t GPIO13; /*!< Pad control register */ + __IOM uint32_t GPIO14; /*!< Pad control register */ + __IOM uint32_t GPIO15; /*!< Pad control register */ + __IOM uint32_t GPIO16; /*!< Pad control register */ + __IOM uint32_t GPIO17; /*!< Pad control register */ + __IOM uint32_t GPIO18; /*!< Pad control register */ + __IOM uint32_t GPIO19; /*!< Pad control register */ + __IOM uint32_t GPIO20; /*!< Pad control register */ + __IOM uint32_t GPIO21; /*!< Pad control register */ + __IOM uint32_t GPIO22; /*!< Pad control register */ + __IOM uint32_t GPIO23; /*!< Pad control register */ + __IOM uint32_t GPIO24; /*!< Pad control register */ + __IOM uint32_t GPIO25; /*!< Pad control register */ + __IOM uint32_t GPIO26; /*!< Pad control register */ + __IOM uint32_t GPIO27; /*!< Pad control register */ + __IOM uint32_t GPIO28; /*!< Pad control register */ + __IOM uint32_t GPIO29; /*!< Pad control register */ + __IOM uint32_t SWCLK; /*!< Pad control register */ + __IOM uint32_t SWD; /*!< Pad control register */ +} PADS_BANK0_Type; /*!< Size = 132 (0x84) */ + + + +/* =========================================================================================================================== */ +/* ================ PADS_QSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PADS_QSPI (PADS_QSPI) + */ + +typedef struct { /*!< PADS_QSPI Structure */ + __IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */ + __IOM uint32_t GPIO_QSPI_SCLK; /*!< Pad control register */ + __IOM uint32_t GPIO_QSPI_SD0; /*!< Pad control register */ + __IOM uint32_t GPIO_QSPI_SD1; /*!< Pad control register */ + __IOM uint32_t GPIO_QSPI_SD2; /*!< Pad control register */ + __IOM uint32_t GPIO_QSPI_SD3; /*!< Pad control register */ + __IOM uint32_t GPIO_QSPI_SS; /*!< Pad control register */ +} PADS_QSPI_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ IO_QSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief IO_QSPI (IO_QSPI) + */ + +typedef struct { /*!< IO_QSPI Structure */ + __IOM uint32_t GPIO_QSPI_SCLK_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO_QSPI_SCLK_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SS_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO_QSPI_SS_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD0_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO_QSPI_SD0_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD1_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO_QSPI_SD1_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD2_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO_QSPI_SD2_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD3_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO_QSPI_SD3_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t PROC0_INTE; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTF; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTS; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC1_INTE; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTF; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTS; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t DORMANT_WAKE_INTE; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS; /*!< Interrupt status after masking & forcing for dormant_wake */ +} IO_QSPI_Type; /*!< Size = 88 (0x58) */ + + + +/* =========================================================================================================================== */ +/* ================ IO_BANK0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief IO_BANK0 (IO_BANK0) + */ + +typedef struct { /*!< IO_BANK0 Structure */ + __IOM uint32_t GPIO0_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO0_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO1_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO1_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO2_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO2_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO3_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO3_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO4_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO4_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO5_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO5_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO6_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO6_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO7_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO7_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO8_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO8_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO9_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO9_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO10_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO10_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO11_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO11_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO12_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO12_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO13_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO13_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO14_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO14_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO15_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO15_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO16_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO16_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO17_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO17_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO18_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO18_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO19_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO19_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO20_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO20_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO21_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO21_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO22_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO22_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO23_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO23_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO24_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO24_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO25_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO25_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO26_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO26_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO27_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO27_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO28_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO28_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t GPIO29_STATUS; /*!< GPIO status */ + __IOM uint32_t GPIO29_CTRL; /*!< GPIO control including function select and overrides. */ + __IOM uint32_t INTR0; /*!< Raw Interrupts */ + __IOM uint32_t INTR1; /*!< Raw Interrupts */ + __IOM uint32_t INTR2; /*!< Raw Interrupts */ + __IOM uint32_t INTR3; /*!< Raw Interrupts */ + __IOM uint32_t PROC0_INTE0; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE1; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE2; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE3; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTF0; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF1; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF2; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF3; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTS0; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS1; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS2; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS3; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC1_INTE0; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE1; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE2; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE3; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTF0; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF1; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF2; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF3; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTS0; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS1; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS2; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS3; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t DORMANT_WAKE_INTE0; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE1; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE2; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE3; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF0; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF1; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF2; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF3; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS0; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS1; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS2; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS3; /*!< Interrupt status after masking & forcing for dormant_wake */ +} IO_BANK0_Type; /*!< Size = 400 (0x190) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSINFO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SYSINFO (SYSINFO) + */ + +typedef struct { /*!< SYSINFO Structure */ + __IOM uint32_t CHIP_ID; /*!< JEDEC JEP-106 compliant chip identifier. */ + __IOM uint32_t PLATFORM; /*!< Platform register. Allows software to know what environment + it is running in. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t GITREF_RP2040; /*!< Git hash of the chip source. Used to identify chip version. */ +} SYSINFO_Type; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ PPB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PPB (PPB) + */ + +typedef struct { /*!< PPB Structure */ + __IM uint32_t RESERVED[14340]; + __IOM uint32_t SYST_CSR; /*!< Use the SysTick Control and Status Register to enable the SysTick + features. */ + __IOM uint32_t SYST_RVR; /*!< Use the SysTick Reload Value Register to specify the start value + to load into the current value register when the counter + reaches 0. It can be any value between 0 and 0x00FFFFFF. + A start value of 0 is possible, but has no effect because + the SysTick interrupt and COUNTFLAG are activated when + counting from 1 to 0. The reset value of this register + is UNKNOWN. To generate a multi-shot timer with a period + of N processor clock cycles, use a RELOAD value of N-1. + For example, if the SysTick interrupt is required every + 100 clock pulses, set RELOAD to 99. */ + __IOM uint32_t SYST_CVR; /*!< Use the SysTick Current Value Register to find the current value + in the register. The reset value of this register is UNKNOWN. */ + __IOM uint32_t SYST_CALIB; /*!< Use the SysTick Calibration Value Register to enable software + to scale to any required speed using divide and multiply. */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t NVIC_ISER; /*!< Use the Interrupt Set-Enable Register to enable interrupts and + determine which interrupts are currently enabled. If a + pending interrupt is enabled, the NVIC activates the interrupt + based on its priority. If an interrupt is not enabled, + asserting its interrupt signal changes the interrupt state + to pending, but the NVIC never activates the interrupt, + regardless of its priority. */ + __IM uint32_t RESERVED2[31]; + __IOM uint32_t NVIC_ICER; /*!< Use the Interrupt Clear-Enable Registers to disable interrupts + and determine which interrupts are currently enabled. */ + __IM uint32_t RESERVED3[31]; + __IOM uint32_t NVIC_ISPR; /*!< The NVIC_ISPR forces interrupts into the pending state, and + shows which interrupts are pending. */ + __IM uint32_t RESERVED4[31]; + __IOM uint32_t NVIC_ICPR; /*!< Use the Interrupt Clear-Pending Register to clear pending interrupts + and determine which interrupts are currently pending. */ + __IM uint32_t RESERVED5[95]; + __IOM uint32_t NVIC_IPR0; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. Note: Writing 1 to an NVIC_ICPR + bit does not affect the active state of the corresponding + interrupt. These registers are only word-accessible */ + __IOM uint32_t NVIC_IPR1; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. */ + __IOM uint32_t NVIC_IPR2; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. */ + __IOM uint32_t NVIC_IPR3; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. */ + __IOM uint32_t NVIC_IPR4; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. */ + __IOM uint32_t NVIC_IPR5; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. */ + __IOM uint32_t NVIC_IPR6; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. */ + __IOM uint32_t NVIC_IPR7; /*!< Use the Interrupt Priority Registers to assign a priority from + 0 to 3 to each of the available interrupts. 0 is the highest + priority, and 3 is the lowest. */ + __IM uint32_t RESERVED6[568]; + __IOM uint32_t CPUID; /*!< Read the CPU ID Base Register to determine: the ID number of + the processor core, the version number of the processor + core, the implementation details of the processor core. */ + __IOM uint32_t ICSR; /*!< Use the Interrupt Control State Register to set a pending Non-Maskable + Interrupt (NMI), set or clear a pending PendSV, set or + clear a pending SysTick, check for pending exceptions, + check the vector number of the highest priority pended + exception, check the vector number of the active exception. */ + __IOM uint32_t VTOR; /*!< The VTOR holds the vector table offset address. */ + __IOM uint32_t AIRCR; /*!< Use the Application Interrupt and Reset Control Register to: + determine data endianness, clear all active state information + from debug halt mode, request a system reset. */ + __IOM uint32_t SCR; /*!< System Control Register. Use the System Control Register for + power-management functions: signal to the system when the + processor can enter a low power state, control how the + processor enters and exits low power states. */ + __IOM uint32_t CCR; /*!< The Configuration and Control Register permanently enables stack + alignment and causes unaligned accesses to result in a + Hard Fault. */ + __IM uint32_t RESERVED7; + __IOM uint32_t SHPR2; /*!< System handlers are a special class of exception handler that + can have their priority set to any of the priority levels. + Use the System Handler Priority Register 2 to set the priority + of SVCall. */ + __IOM uint32_t SHPR3; /*!< System handlers are a special class of exception handler that + can have their priority set to any of the priority levels. + Use the System Handler Priority Register 3 to set the priority + of PendSV and SysTick. */ + __IOM uint32_t SHCSR; /*!< Use the System Handler Control and State Register to determine + or clear the pending status of SVCall. */ + __IM uint32_t RESERVED8[26]; + __IOM uint32_t MPU_TYPE; /*!< Read the MPU Type Register to determine if the processor implements + an MPU, and how many regions the MPU supports. */ + __IOM uint32_t MPU_CTRL; /*!< Use the MPU Control Register to enable and disable the MPU, + and to control whether the default memory map is enabled + as a background region for privileged accesses, and whether + the MPU is enabled for HardFaults and NMIs. */ + __IOM uint32_t MPU_RNR; /*!< Use the MPU Region Number Register to select the region currently + accessed by MPU_RBAR and MPU_RASR. */ + __IOM uint32_t MPU_RBAR; /*!< Read the MPU Region Base Address Register to determine the base + address of the region identified by MPU_RNR. Write to update + the base address of said region or that of a specified + region, with whose number MPU_RNR will also be updated. */ + __IOM uint32_t MPU_RASR; /*!< Use the MPU Region Attribute and Size Register to define the + size, access behaviour and memory type of the region identified + by MPU_RNR, and enable that region. */ +} PPB_Type; /*!< Size = 60836 (0xeda4) */ + + + +/* =========================================================================================================================== */ +/* ================ SSI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DW_apb_ssi has the following features: + * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. + * APB3 and APB4 protocol support. + * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. + * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. + * Programmable Dual/Quad/Octal SPI support in Master Mode. + * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. + * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. + * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. + * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. + * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. + * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. + * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. + * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. + * Programmable features: + - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. + - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. + - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. + * Configured features: + - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. + - 1 slave select output. + - Hardware slave-select – Dedicated hardware slave-select line. + - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. + - Interrupt polarity – active high interrupt lines. + - Serial clock polarity – low serial-clock polarity directly after reset. + - Serial clock phase – capture on first edge of serial-clock directly after reset. (SSI) + */ + +typedef struct { /*!< SSI Structure */ + __IOM uint32_t CTRLR0; /*!< Control register 0 */ + __IOM uint32_t CTRLR1; /*!< Master Control register 1 */ + __IOM uint32_t SSIENR; /*!< SSI Enable */ + __IOM uint32_t MWCR; /*!< Microwire Control */ + __IOM uint32_t SER; /*!< Slave enable */ + __IOM uint32_t BAUDR; /*!< Baud rate */ + __IOM uint32_t TXFTLR; /*!< TX FIFO threshold level */ + __IOM uint32_t RXFTLR; /*!< RX FIFO threshold level */ + __IOM uint32_t TXFLR; /*!< TX FIFO level */ + __IOM uint32_t RXFLR; /*!< RX FIFO level */ + __IOM uint32_t SR; /*!< Status register */ + __IOM uint32_t IMR; /*!< Interrupt mask */ + __IOM uint32_t ISR; /*!< Interrupt status */ + __IOM uint32_t RISR; /*!< Raw interrupt status */ + __IOM uint32_t TXOICR; /*!< TX FIFO overflow interrupt clear */ + __IOM uint32_t RXOICR; /*!< RX FIFO overflow interrupt clear */ + __IOM uint32_t RXUICR; /*!< RX FIFO underflow interrupt clear */ + __IOM uint32_t MSTICR; /*!< Multi-master interrupt clear */ + __IOM uint32_t ICR; /*!< Interrupt clear */ + __IOM uint32_t DMACR; /*!< DMA control */ + __IOM uint32_t DMATDLR; /*!< DMA TX data level */ + __IOM uint32_t DMARDLR; /*!< DMA RX data level */ + __IOM uint32_t IDR; /*!< Identification register */ + __IOM uint32_t SSI_VERSION_ID; /*!< Version ID */ + __IOM uint32_t DR0; /*!< Data Register 0 (of 36) */ + __IM uint32_t RESERVED[35]; + __IOM uint32_t RX_SAMPLE_DLY; /*!< RX sample delay */ + __IOM uint32_t SPI_CTRLR0; /*!< SPI control */ + __IOM uint32_t TXD_DRIVE_EDGE; /*!< TX drive edge */ +} SSI_Type; /*!< Size = 252 (0xfc) */ + + + +/* =========================================================================================================================== */ +/* ================ XIP_CTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief QSPI flash execute-in-place block (XIP_CTRL) + */ + +typedef struct { /*!< XIP_CTRL Structure */ + __IOM uint32_t CTRL; /*!< Cache control */ + __IOM uint32_t FLUSH; /*!< Cache Flush control */ + __IOM uint32_t STAT; /*!< Cache Status */ + __IOM uint32_t CTR_HIT; /*!< Cache Hit counter */ + __IOM uint32_t CTR_ACC; /*!< Cache Access counter */ + __IOM uint32_t STREAM_ADDR; /*!< FIFO stream address */ + __IOM uint32_t STREAM_CTR; /*!< FIFO stream control */ + __IOM uint32_t STREAM_FIFO; /*!< FIFO stream data */ +} XIP_CTRL_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSCFG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Register block for various chip control signals (SYSCFG) + */ + +typedef struct { /*!< SYSCFG Structure */ + __IOM uint32_t PROC0_NMI_MASK; /*!< Processor core 0 NMI source mask */ + __IOM uint32_t PROC1_NMI_MASK; /*!< Processor core 1 NMI source mask */ + __IOM uint32_t PROC_CONFIG; /*!< Configuration for processors */ + __IOM uint32_t PROC_IN_SYNC_BYPASS; /*!< For each bit, if 1, bypass the input synchronizer between that + GPIO and the GPIO input register in the SIO. The input + synchronizers should generally be unbypassed, to avoid + injecting metastabilities into processors. If you're feeling + brave, you can bypass to save two cycles of input latency. + This register applies to GPIO 0...29. */ + __IOM uint32_t PROC_IN_SYNC_BYPASS_HI; /*!< For each bit, if 1, bypass the input synchronizer between that + GPIO and the GPIO input register in the SIO. The input + synchronizers should generally be unbypassed, to avoid + injecting metastabilities into processors. If you're feeling + brave, you can bypass to save two cycles of input latency. + This register applies to GPIO 30...35 (the QSPI IOs). */ + __IOM uint32_t DBGFORCE; /*!< Directly control the SWD debug port of either processor */ + __IOM uint32_t MEMPOWERDOWN; /*!< Control power downs to memories. Set high to power down memories. + Use with extreme caution */ +} SYSCFG_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ XOSC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controls the crystal oscillator (XOSC) + */ + +typedef struct { /*!< XOSC Structure */ + __IOM uint32_t CTRL; /*!< Crystal Oscillator Control */ + __IOM uint32_t STATUS; /*!< Crystal Oscillator Status */ + __IOM uint32_t DORMANT; /*!< Crystal Oscillator pause control */ + __IOM uint32_t STARTUP; /*!< Controls the startup delay */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t COUNT; /*!< A down counter running at the xosc frequency which counts to + zero and stops. To start the counter write a non-zero value. + Can be used for short software pauses when setting up time + sensitive hardware. */ +} XOSC_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ PLL_SYS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PLL_SYS (PLL_SYS) + */ + +typedef struct { /*!< PLL_SYS Structure */ + __IOM uint32_t CS; /*!< Control and Status GENERAL CONSTRAINTS: Reference clock frequency + min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO + frequency min=750MHz, max=1600MHz */ + __IOM uint32_t PWR; /*!< Controls the PLL power modes. */ + __IOM uint32_t FBDIV_INT; /*!< Feedback divisor (note: this PLL does not support fractional + division) */ + __IOM uint32_t PRIM; /*!< Controls the PLL post dividers for the primary output (note: + this PLL does not have a secondary output) the primary + output is driven from VCO divided by postdiv1*postdiv2 */ +} PLL_SYS_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART0 (UART0) + */ + +typedef struct { /*!< UART0 Structure */ + __IOM uint32_t UARTDR; /*!< Data Register, UARTDR */ + __IOM uint32_t UARTRSR; /*!< Receive Status Register/Error Clear Register, UARTRSR/UARTECR */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t UARTFR; /*!< Flag Register, UARTFR */ + __IM uint32_t RESERVED1; + __IOM uint32_t UARTILPR; /*!< IrDA Low-Power Counter Register, UARTILPR */ + __IOM uint32_t UARTIBRD; /*!< Integer Baud Rate Register, UARTIBRD */ + __IOM uint32_t UARTFBRD; /*!< Fractional Baud Rate Register, UARTFBRD */ + __IOM uint32_t UARTLCR_H; /*!< Line Control Register, UARTLCR_H */ + __IOM uint32_t UARTCR; /*!< Control Register, UARTCR */ + __IOM uint32_t UARTIFLS; /*!< Interrupt FIFO Level Select Register, UARTIFLS */ + __IOM uint32_t UARTIMSC; /*!< Interrupt Mask Set/Clear Register, UARTIMSC */ + __IOM uint32_t UARTRIS; /*!< Raw Interrupt Status Register, UARTRIS */ + __IOM uint32_t UARTMIS; /*!< Masked Interrupt Status Register, UARTMIS */ + __IOM uint32_t UARTICR; /*!< Interrupt Clear Register, UARTICR */ + __IOM uint32_t UARTDMACR; /*!< DMA Control Register, UARTDMACR */ + __IM uint32_t RESERVED2[997]; + __IOM uint32_t UARTPERIPHID0; /*!< UARTPeriphID0 Register */ + __IOM uint32_t UARTPERIPHID1; /*!< UARTPeriphID1 Register */ + __IOM uint32_t UARTPERIPHID2; /*!< UARTPeriphID2 Register */ + __IOM uint32_t UARTPERIPHID3; /*!< UARTPeriphID3 Register */ + __IOM uint32_t UARTPCELLID0; /*!< UARTPCellID0 Register */ + __IOM uint32_t UARTPCELLID1; /*!< UARTPCellID1 Register */ + __IOM uint32_t UARTPCELLID2; /*!< UARTPCellID2 Register */ + __IOM uint32_t UARTPCELLID3; /*!< UARTPCellID3 Register */ +} UART0_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ ROSC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ROSC (ROSC) + */ + +typedef struct { /*!< ROSC Structure */ + __IOM uint32_t CTRL; /*!< Ring Oscillator control */ + __IOM uint32_t FREQA; /*!< The FREQA & FREQB registers control the frequency by controlling + the drive strength of each stage The drive strength has + 4 levels determined by the number of bits set Increasing + the number of bits set increases the drive strength and + increases the oscillation frequency 0 bits set is the default + drive strength 1 bit set doubles the drive strength 2 bits + set triples drive strength 3 bits set quadruples drive + strength */ + __IOM uint32_t FREQB; /*!< For a detailed description see freqa register */ + __IOM uint32_t DORMANT; /*!< Ring Oscillator pause control */ + __IOM uint32_t DIV; /*!< Controls the output divider */ + __IOM uint32_t PHASE; /*!< Controls the phase shifted output */ + __IOM uint32_t STATUS; /*!< Ring Oscillator Status */ + __IOM uint32_t RANDOMBIT; /*!< This just reads the state of the oscillator output so randomness + is compromised if the ring oscillator is stopped or run + at a harmonic of the bus frequency */ + __IOM uint32_t COUNT; /*!< A down counter running at the ROSC frequency which counts to + zero and stops. To start the counter write a non-zero value. + Can be used for short software pauses when setting up time + sensitive hardware. */ +} ROSC_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ WATCHDOG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief WATCHDOG (WATCHDOG) + */ + +typedef struct { /*!< WATCHDOG Structure */ + __IOM uint32_t CTRL; /*!< Watchdog control The rst_wdsel register determines which subsystems + are reset when the watchdog is triggered. The watchdog + can be triggered in software. */ + __IOM uint32_t LOAD; /*!< Load the watchdog timer. The maximum setting is 0xffffff which + corresponds to 0xffffff / 2 ticks before triggering a watchdog + reset (see errata RP2040-E1). */ + __IOM uint32_t REASON; /*!< Logs the reason for the last reset. Both bits are zero for the + case of a hardware reset. */ + __IOM uint32_t SCRATCH0; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH1; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH2; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH3; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH4; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH5; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH6; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH7; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t TICK; /*!< Controls the tick generator */ +} WATCHDOG_Type; /*!< Size = 48 (0x30) */ + + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DMA with separate read and write masters (DMA) + */ + +typedef struct { /*!< DMA Structure */ + __IOM uint32_t CH0_READ_ADDR; /*!< DMA Channel 0 Read Address pointer */ + __IOM uint32_t CH0_WRITE_ADDR; /*!< DMA Channel 0 Write Address pointer */ + __IOM uint32_t CH0_TRANS_COUNT; /*!< DMA Channel 0 Transfer Count */ + __IOM uint32_t CH0_CTRL_TRIG; /*!< DMA Channel 0 Control and Status */ + __IOM uint32_t CH0_AL1_CTRL; /*!< Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL1_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */ + __IOM uint32_t CH0_AL1_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */ + __IOM uint32_t CH0_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 0 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH0_AL2_CTRL; /*!< Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL2_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */ + __IOM uint32_t CH0_AL2_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */ + __IOM uint32_t CH0_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 0 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH0_AL3_CTRL; /*!< Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL3_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */ + __IOM uint32_t CH0_AL3_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */ + __IOM uint32_t CH0_AL3_READ_ADDR_TRIG; /*!< Alias for channel 0 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH1_READ_ADDR; /*!< DMA Channel 1 Read Address pointer */ + __IOM uint32_t CH1_WRITE_ADDR; /*!< DMA Channel 1 Write Address pointer */ + __IOM uint32_t CH1_TRANS_COUNT; /*!< DMA Channel 1 Transfer Count */ + __IOM uint32_t CH1_CTRL_TRIG; /*!< DMA Channel 1 Control and Status */ + __IOM uint32_t CH1_AL1_CTRL; /*!< Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL1_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */ + __IOM uint32_t CH1_AL1_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */ + __IOM uint32_t CH1_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 1 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH1_AL2_CTRL; /*!< Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL2_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */ + __IOM uint32_t CH1_AL2_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */ + __IOM uint32_t CH1_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 1 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH1_AL3_CTRL; /*!< Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL3_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */ + __IOM uint32_t CH1_AL3_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */ + __IOM uint32_t CH1_AL3_READ_ADDR_TRIG; /*!< Alias for channel 1 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH2_READ_ADDR; /*!< DMA Channel 2 Read Address pointer */ + __IOM uint32_t CH2_WRITE_ADDR; /*!< DMA Channel 2 Write Address pointer */ + __IOM uint32_t CH2_TRANS_COUNT; /*!< DMA Channel 2 Transfer Count */ + __IOM uint32_t CH2_CTRL_TRIG; /*!< DMA Channel 2 Control and Status */ + __IOM uint32_t CH2_AL1_CTRL; /*!< Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL1_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */ + __IOM uint32_t CH2_AL1_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */ + __IOM uint32_t CH2_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 2 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH2_AL2_CTRL; /*!< Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL2_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */ + __IOM uint32_t CH2_AL2_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */ + __IOM uint32_t CH2_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 2 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH2_AL3_CTRL; /*!< Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL3_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */ + __IOM uint32_t CH2_AL3_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */ + __IOM uint32_t CH2_AL3_READ_ADDR_TRIG; /*!< Alias for channel 2 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH3_READ_ADDR; /*!< DMA Channel 3 Read Address pointer */ + __IOM uint32_t CH3_WRITE_ADDR; /*!< DMA Channel 3 Write Address pointer */ + __IOM uint32_t CH3_TRANS_COUNT; /*!< DMA Channel 3 Transfer Count */ + __IOM uint32_t CH3_CTRL_TRIG; /*!< DMA Channel 3 Control and Status */ + __IOM uint32_t CH3_AL1_CTRL; /*!< Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL1_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */ + __IOM uint32_t CH3_AL1_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */ + __IOM uint32_t CH3_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 3 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH3_AL2_CTRL; /*!< Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL2_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */ + __IOM uint32_t CH3_AL2_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */ + __IOM uint32_t CH3_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 3 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH3_AL3_CTRL; /*!< Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL3_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */ + __IOM uint32_t CH3_AL3_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */ + __IOM uint32_t CH3_AL3_READ_ADDR_TRIG; /*!< Alias for channel 3 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH4_READ_ADDR; /*!< DMA Channel 4 Read Address pointer */ + __IOM uint32_t CH4_WRITE_ADDR; /*!< DMA Channel 4 Write Address pointer */ + __IOM uint32_t CH4_TRANS_COUNT; /*!< DMA Channel 4 Transfer Count */ + __IOM uint32_t CH4_CTRL_TRIG; /*!< DMA Channel 4 Control and Status */ + __IOM uint32_t CH4_AL1_CTRL; /*!< Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL1_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */ + __IOM uint32_t CH4_AL1_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */ + __IOM uint32_t CH4_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 4 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH4_AL2_CTRL; /*!< Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL2_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */ + __IOM uint32_t CH4_AL2_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */ + __IOM uint32_t CH4_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 4 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH4_AL3_CTRL; /*!< Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL3_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */ + __IOM uint32_t CH4_AL3_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */ + __IOM uint32_t CH4_AL3_READ_ADDR_TRIG; /*!< Alias for channel 4 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH5_READ_ADDR; /*!< DMA Channel 5 Read Address pointer */ + __IOM uint32_t CH5_WRITE_ADDR; /*!< DMA Channel 5 Write Address pointer */ + __IOM uint32_t CH5_TRANS_COUNT; /*!< DMA Channel 5 Transfer Count */ + __IOM uint32_t CH5_CTRL_TRIG; /*!< DMA Channel 5 Control and Status */ + __IOM uint32_t CH5_AL1_CTRL; /*!< Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL1_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */ + __IOM uint32_t CH5_AL1_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */ + __IOM uint32_t CH5_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 5 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH5_AL2_CTRL; /*!< Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL2_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */ + __IOM uint32_t CH5_AL2_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */ + __IOM uint32_t CH5_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 5 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH5_AL3_CTRL; /*!< Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL3_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */ + __IOM uint32_t CH5_AL3_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */ + __IOM uint32_t CH5_AL3_READ_ADDR_TRIG; /*!< Alias for channel 5 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH6_READ_ADDR; /*!< DMA Channel 6 Read Address pointer */ + __IOM uint32_t CH6_WRITE_ADDR; /*!< DMA Channel 6 Write Address pointer */ + __IOM uint32_t CH6_TRANS_COUNT; /*!< DMA Channel 6 Transfer Count */ + __IOM uint32_t CH6_CTRL_TRIG; /*!< DMA Channel 6 Control and Status */ + __IOM uint32_t CH6_AL1_CTRL; /*!< Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL1_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */ + __IOM uint32_t CH6_AL1_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */ + __IOM uint32_t CH6_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 6 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH6_AL2_CTRL; /*!< Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL2_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */ + __IOM uint32_t CH6_AL2_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */ + __IOM uint32_t CH6_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 6 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH6_AL3_CTRL; /*!< Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL3_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */ + __IOM uint32_t CH6_AL3_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */ + __IOM uint32_t CH6_AL3_READ_ADDR_TRIG; /*!< Alias for channel 6 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH7_READ_ADDR; /*!< DMA Channel 7 Read Address pointer */ + __IOM uint32_t CH7_WRITE_ADDR; /*!< DMA Channel 7 Write Address pointer */ + __IOM uint32_t CH7_TRANS_COUNT; /*!< DMA Channel 7 Transfer Count */ + __IOM uint32_t CH7_CTRL_TRIG; /*!< DMA Channel 7 Control and Status */ + __IOM uint32_t CH7_AL1_CTRL; /*!< Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL1_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */ + __IOM uint32_t CH7_AL1_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */ + __IOM uint32_t CH7_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 7 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH7_AL2_CTRL; /*!< Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL2_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */ + __IOM uint32_t CH7_AL2_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */ + __IOM uint32_t CH7_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 7 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH7_AL3_CTRL; /*!< Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL3_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */ + __IOM uint32_t CH7_AL3_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */ + __IOM uint32_t CH7_AL3_READ_ADDR_TRIG; /*!< Alias for channel 7 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH8_READ_ADDR; /*!< DMA Channel 8 Read Address pointer */ + __IOM uint32_t CH8_WRITE_ADDR; /*!< DMA Channel 8 Write Address pointer */ + __IOM uint32_t CH8_TRANS_COUNT; /*!< DMA Channel 8 Transfer Count */ + __IOM uint32_t CH8_CTRL_TRIG; /*!< DMA Channel 8 Control and Status */ + __IOM uint32_t CH8_AL1_CTRL; /*!< Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL1_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */ + __IOM uint32_t CH8_AL1_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */ + __IOM uint32_t CH8_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 8 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH8_AL2_CTRL; /*!< Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL2_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */ + __IOM uint32_t CH8_AL2_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */ + __IOM uint32_t CH8_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 8 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH8_AL3_CTRL; /*!< Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL3_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */ + __IOM uint32_t CH8_AL3_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */ + __IOM uint32_t CH8_AL3_READ_ADDR_TRIG; /*!< Alias for channel 8 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH9_READ_ADDR; /*!< DMA Channel 9 Read Address pointer */ + __IOM uint32_t CH9_WRITE_ADDR; /*!< DMA Channel 9 Write Address pointer */ + __IOM uint32_t CH9_TRANS_COUNT; /*!< DMA Channel 9 Transfer Count */ + __IOM uint32_t CH9_CTRL_TRIG; /*!< DMA Channel 9 Control and Status */ + __IOM uint32_t CH9_AL1_CTRL; /*!< Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL1_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */ + __IOM uint32_t CH9_AL1_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */ + __IOM uint32_t CH9_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 9 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH9_AL2_CTRL; /*!< Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL2_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */ + __IOM uint32_t CH9_AL2_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */ + __IOM uint32_t CH9_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 9 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH9_AL3_CTRL; /*!< Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL3_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */ + __IOM uint32_t CH9_AL3_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */ + __IOM uint32_t CH9_AL3_READ_ADDR_TRIG; /*!< Alias for channel 9 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH10_READ_ADDR; /*!< DMA Channel 10 Read Address pointer */ + __IOM uint32_t CH10_WRITE_ADDR; /*!< DMA Channel 10 Write Address pointer */ + __IOM uint32_t CH10_TRANS_COUNT; /*!< DMA Channel 10 Transfer Count */ + __IOM uint32_t CH10_CTRL_TRIG; /*!< DMA Channel 10 Control and Status */ + __IOM uint32_t CH10_AL1_CTRL; /*!< Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL1_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */ + __IOM uint32_t CH10_AL1_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */ + __IOM uint32_t CH10_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 10 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH10_AL2_CTRL; /*!< Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL2_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */ + __IOM uint32_t CH10_AL2_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */ + __IOM uint32_t CH10_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 10 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH10_AL3_CTRL; /*!< Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL3_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */ + __IOM uint32_t CH10_AL3_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */ + __IOM uint32_t CH10_AL3_READ_ADDR_TRIG; /*!< Alias for channel 10 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH11_READ_ADDR; /*!< DMA Channel 11 Read Address pointer */ + __IOM uint32_t CH11_WRITE_ADDR; /*!< DMA Channel 11 Write Address pointer */ + __IOM uint32_t CH11_TRANS_COUNT; /*!< DMA Channel 11 Transfer Count */ + __IOM uint32_t CH11_CTRL_TRIG; /*!< DMA Channel 11 Control and Status */ + __IOM uint32_t CH11_AL1_CTRL; /*!< Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL1_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */ + __IOM uint32_t CH11_AL1_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */ + __IOM uint32_t CH11_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 11 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH11_AL2_CTRL; /*!< Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL2_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */ + __IOM uint32_t CH11_AL2_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */ + __IOM uint32_t CH11_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 11 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH11_AL3_CTRL; /*!< Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL3_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */ + __IOM uint32_t CH11_AL3_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */ + __IOM uint32_t CH11_AL3_READ_ADDR_TRIG; /*!< Alias for channel 11 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t INTR; /*!< Interrupt Status (raw) */ + __IOM uint32_t INTE0; /*!< Interrupt Enables for IRQ 0 */ + __IOM uint32_t INTF0; /*!< Force Interrupts */ + __IOM uint32_t INTS0; /*!< Interrupt Status for IRQ 0 */ + __IOM uint32_t INTR1; /*!< Interrupt Status (raw) */ + __IOM uint32_t INTE1; /*!< Interrupt Enables for IRQ 1 */ + __IOM uint32_t INTF1; /*!< Force Interrupts for IRQ 1 */ + __IOM uint32_t INTS1; /*!< Interrupt Status (masked) for IRQ 1 */ + __IOM uint32_t TIMER0; /*!< Pacing (X/Y) Fractional Timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t TIMER1; /*!< Pacing (X/Y) Fractional Timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t TIMER2; /*!< Pacing (X/Y) Fractional Timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t TIMER3; /*!< Pacing (X/Y) Fractional Timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t MULTI_CHAN_TRIGGER; /*!< Trigger one or more channels simultaneously */ + __IOM uint32_t SNIFF_CTRL; /*!< Sniffer Control */ + __IOM uint32_t SNIFF_DATA; /*!< Data accumulator for sniff hardware */ + __IM uint32_t RESERVED1; + __IOM uint32_t FIFO_LEVELS; /*!< Debug RAF, WAF, TDF levels */ + __IOM uint32_t CHAN_ABORT; /*!< Abort an in-progress transfer sequence on one or more channels */ + __IOM uint32_t N_CHANNELS; /*!< The number of channels this DMA instance is equipped with. This + DMA supports up to 16 hardware channels, but can be configured + with as few as one, to minimise silicon area. */ + __IM uint32_t RESERVED2[237]; + __IOM uint32_t CH0_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH0_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED3[14]; + __IOM uint32_t CH1_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH1_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED4[14]; + __IOM uint32_t CH2_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH2_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED5[14]; + __IOM uint32_t CH3_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH3_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED6[14]; + __IOM uint32_t CH4_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH4_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED7[14]; + __IOM uint32_t CH5_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH5_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED8[14]; + __IOM uint32_t CH6_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH6_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED9[14]; + __IOM uint32_t CH7_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH7_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED10[14]; + __IOM uint32_t CH8_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH8_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t CH9_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH9_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED12[14]; + __IOM uint32_t CH10_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH10_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED13[14]; + __IOM uint32_t CH11_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH11_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ +} DMA_Type; /*!< Size = 2760 (0xac8) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controls time and alarms + time is a 64 bit value indicating the time in usec since power-on + timeh is the top 32 bits of time & timel is the bottom 32 bits + to change time write to timelw before timehw + to read time read from timelr before timehr + An alarm is set by setting alarm_enable and writing to the corresponding alarm register + When an alarm is pending, the corresponding alarm_running signal will be high + An alarm can be cancelled before it has finished by clearing the alarm_enable + When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared + To clear the interrupt write a 1 to the corresponding alarm_irq (TIMER) + */ + +typedef struct { /*!< TIMER Structure */ + __IOM uint32_t TIMEHW; /*!< Write to bits 63:32 of time always write timelw before timehw */ + __IOM uint32_t TIMELW; /*!< Write to bits 31:0 of time writes do not get copied to time + until timehw is written */ + __IOM uint32_t TIMEHR; /*!< Read from bits 63:32 of time always read timelr before timehr */ + __IOM uint32_t TIMELR; /*!< Read from bits 31:0 of time */ + __IOM uint32_t ALARM0; /*!< Arm alarm 0, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM0 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ALARM1; /*!< Arm alarm 1, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM1 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ALARM2; /*!< Arm alarm 2, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM2 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ALARM3; /*!< Arm alarm 3, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM3 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ARMED; /*!< Indicates the armed/disarmed status of each alarm. A write to + the corresponding ALARMx register arms the alarm. Alarms + automatically disarm upon firing, but writing ones here + will disarm immediately without waiting to fire. */ + __IOM uint32_t TIMERAWH; /*!< Raw read from bits 63:32 of time (no side effects) */ + __IOM uint32_t TIMERAWL; /*!< Raw read from bits 31:0 of time (no side effects) */ + __IOM uint32_t DBGPAUSE; /*!< Set bits high to enable pause when the corresponding debug ports + are active */ + __IOM uint32_t PAUSE; /*!< Set high to pause the timer */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} TIMER_Type; /*!< Size = 68 (0x44) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Simple PWM (PWM) + */ + +typedef struct { /*!< PWM Structure */ + __IOM uint32_t CH0_CSR; /*!< Control and status register */ + __IOM uint32_t CH0_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH0_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH0_CC; /*!< Counter compare values */ + __IOM uint32_t CH0_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH1_CSR; /*!< Control and status register */ + __IOM uint32_t CH1_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH1_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH1_CC; /*!< Counter compare values */ + __IOM uint32_t CH1_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH2_CSR; /*!< Control and status register */ + __IOM uint32_t CH2_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH2_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH2_CC; /*!< Counter compare values */ + __IOM uint32_t CH2_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH3_CSR; /*!< Control and status register */ + __IOM uint32_t CH3_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH3_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH3_CC; /*!< Counter compare values */ + __IOM uint32_t CH3_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH4_CSR; /*!< Control and status register */ + __IOM uint32_t CH4_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH4_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH4_CC; /*!< Counter compare values */ + __IOM uint32_t CH4_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH5_CSR; /*!< Control and status register */ + __IOM uint32_t CH5_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH5_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH5_CC; /*!< Counter compare values */ + __IOM uint32_t CH5_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH6_CSR; /*!< Control and status register */ + __IOM uint32_t CH6_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH6_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH6_CC; /*!< Counter compare values */ + __IOM uint32_t CH6_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH7_CSR; /*!< Control and status register */ + __IOM uint32_t CH7_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH7_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH7_CC; /*!< Counter compare values */ + __IOM uint32_t CH7_TOP; /*!< Counter wrap value */ + __IOM uint32_t EN; /*!< This register aliases the CSR_EN bits for all channels. Writing + to this register allows multiple channels to be enabled + or disabled simultaneously, so they can run in perfect + sync. For each channel, there is only one physical EN register + bit, which can be accessed through here or CHx_CSR. */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} PWM_Type; /*!< Size = 180 (0xb4) */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Control and data interface to SAR ADC (ADC) + */ + +typedef struct { /*!< ADC Structure */ + __IOM uint32_t CS; /*!< ADC Control and Status */ + __IOM uint32_t RESULT; /*!< Result of most recent ADC conversion */ + __IOM uint32_t FCS; /*!< FIFO control and status */ + __IOM uint32_t FIFO; /*!< Conversion result FIFO */ + __IOM uint32_t DIV; /*!< Clock divider. If non-zero, CS_START_MANY will start conversions + at regular intervals rather than back-to-back. The divider + is reset when either of these fields are written. Total + period is 1 + INT + FRAC / 256 */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} ADC_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DW_apb_i2c address block + + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): + + IC_ULTRA_FAST_MODE ................ 0x0 + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 + IC_UFM_SCL_LOW_COUNT .............. 0x0008 + IC_UFM_SCL_HIGH_COUNT ............. 0x0006 + IC_TX_TL .......................... 0x0 + IC_TX_CMD_BLOCK ................... 0x1 + IC_HAS_DMA ........................ 0x1 + IC_HAS_ASYNC_FIFO ................. 0x0 + IC_SMBUS_ARP ...................... 0x0 + IC_FIRST_DATA_BYTE_STATUS ......... 0x1 + IC_INTR_IO ........................ 0x1 + IC_MASTER_MODE .................... 0x1 + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 + IC_INTR_POL ....................... 0x1 + IC_OPTIONAL_SAR ................... 0x0 + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 + IC_DEFAULT_SLAVE_ADDR ............. 0x055 + IC_DEFAULT_HS_SPKLEN .............. 0x1 + IC_FS_SCL_HIGH_COUNT .............. 0x0006 + IC_HS_SCL_LOW_COUNT ............... 0x0008 + IC_DEVICE_ID_VALUE ................ 0x0 + IC_10BITADDR_MASTER ............... 0x0 + IC_CLK_FREQ_OPTIMIZATION .......... 0x0 + IC_DEFAULT_FS_SPKLEN .............. 0x7 + IC_ADD_ENCODED_PARAMS ............. 0x0 + IC_DEFAULT_SDA_HOLD ............... 0x000001 + IC_DEFAULT_SDA_SETUP .............. 0x64 + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 + IC_CLOCK_PERIOD ................... 100 + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 + IC_RESTART_EN ..................... 0x1 + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 + IC_BUS_CLEAR_FEATURE .............. 0x0 + IC_CAP_LOADING .................... 100 + IC_FS_SCL_LOW_COUNT ............... 0x000d + APB_DATA_WIDTH .................... 32 + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_SLV_DATA_NACK_ONLY ............. 0x1 + IC_10BITADDR_SLAVE ................ 0x0 + IC_CLK_TYPE ....................... 0x0 + IC_SMBUS_UDID_MSB ................. 0x0 + IC_SMBUS_SUSPEND_ALERT ............ 0x0 + IC_HS_SCL_HIGH_COUNT .............. 0x0006 + IC_SLV_RESTART_DET_EN ............. 0x1 + IC_SMBUS .......................... 0x0 + IC_OPTIONAL_SAR_DEFAULT ........... 0x0 + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 + IC_USE_COUNTS ..................... 0x0 + IC_RX_BUFFER_DEPTH ................ 16 + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_RX_FULL_HLD_BUS_EN ............. 0x1 + IC_SLAVE_DISABLE .................. 0x1 + IC_RX_TL .......................... 0x0 + IC_DEVICE_ID ...................... 0x0 + IC_HC_COUNT_VALUES ................ 0x0 + I2C_DYNAMIC_TAR_UPDATE ............ 0 + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff + IC_HS_MASTER_CODE ................. 0x1 + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff + IC_SS_SCL_HIGH_COUNT .............. 0x0028 + IC_SS_SCL_LOW_COUNT ............... 0x002f + IC_MAX_SPEED_MODE ................. 0x2 + IC_STAT_FOR_CLK_STRETCH ........... 0x0 + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 + IC_DEFAULT_UFM_SPKLEN ............. 0x1 + IC_TX_BUFFER_DEPTH ................ 16 (I2C0) + */ + +typedef struct { /*!< I2C0 Structure */ + __IOM uint32_t IC_CON; /*!< I2C Control Register. This register can be written only when + the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] + register being set to 0. Writes at other times have no + effect. Read/Write Access: - bit 10 is read only. - bit + 11 is read only - bit 16 is read only - bit 17 is read + only - bits 18 and 19 are read only. */ + __IOM uint32_t IC_TAR; /*!< I2C Target Address Register This register is 12 bits wide, and + bits 31:12 are reserved. This register can be written to + only when IC_ENABLE[0] is set to 0. Note: If the software + or application is aware that the DW_apb_i2c is not using + the TAR address for the pending commands in the Tx FIFO, + then it is possible to update the TAR address even while + the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not + necessary to perform any write to this register if DW_apb_i2c + is enabled as an I2C slave only. */ + __IOM uint32_t IC_SAR; /*!< I2C Slave Address Register */ + __IM uint32_t RESERVED; + __IOM uint32_t IC_DATA_CMD; /*!< I2C Rx/Tx Data Buffer and Command Register; this is the register + the CPU writes to when filling the TX FIFO and the CPU + reads from when retrieving bytes from RX FIFO. The size + of the register changes as follows: Write: - 11 bits when + IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 + Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 + bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order + for the DW_apb_i2c to continue acknowledging reads, a read + command should be written for every byte that is to be + received; otherwise the DW_apb_i2c will stop acknowledging. */ + __IOM uint32_t IC_SS_SCL_HCNT; /*!< Standard Speed I2C Clock SCL High Count Register */ + __IOM uint32_t IC_SS_SCL_LCNT; /*!< Standard Speed I2C Clock SCL Low Count Register */ + __IOM uint32_t IC_FS_SCL_HCNT; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register */ + __IOM uint32_t IC_FS_SCL_LCNT; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t IC_INTR_STAT; /*!< I2C Interrupt Status Register Each bit in this register has + a corresponding mask bit in the IC_INTR_MASK register. + These bits are cleared by reading the matching interrupt + clear register. The unmasked raw versions of these bits + are available in the IC_RAW_INTR_STAT register. */ + __IOM uint32_t IC_INTR_MASK; /*!< I2C Interrupt Mask Register. These bits mask their corresponding + interrupt status bits. This register is active low; a value + of 0 masks the interrupt, whereas a value of 1 unmasks + the interrupt. */ + __IOM uint32_t IC_RAW_INTR_STAT; /*!< I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, + these bits are not masked so they always show the true + status of the DW_apb_i2c. */ + __IOM uint32_t IC_RX_TL; /*!< I2C Receive FIFO Threshold Register */ + __IOM uint32_t IC_TX_TL; /*!< I2C Transmit FIFO Threshold Register */ + __IOM uint32_t IC_CLR_INTR; /*!< Clear Combined and Individual Interrupt Register */ + __IOM uint32_t IC_CLR_RX_UNDER; /*!< Clear RX_UNDER Interrupt Register */ + __IOM uint32_t IC_CLR_RX_OVER; /*!< Clear RX_OVER Interrupt Register */ + __IOM uint32_t IC_CLR_TX_OVER; /*!< Clear TX_OVER Interrupt Register */ + __IOM uint32_t IC_CLR_RD_REQ; /*!< Clear RD_REQ Interrupt Register */ + __IOM uint32_t IC_CLR_TX_ABRT; /*!< Clear TX_ABRT Interrupt Register */ + __IOM uint32_t IC_CLR_RX_DONE; /*!< Clear RX_DONE Interrupt Register */ + __IOM uint32_t IC_CLR_ACTIVITY; /*!< Clear ACTIVITY Interrupt Register */ + __IOM uint32_t IC_CLR_STOP_DET; /*!< Clear STOP_DET Interrupt Register */ + __IOM uint32_t IC_CLR_START_DET; /*!< Clear START_DET Interrupt Register */ + __IOM uint32_t IC_CLR_GEN_CALL; /*!< Clear GEN_CALL Interrupt Register */ + __IOM uint32_t IC_ENABLE; /*!< I2C Enable Register */ + __IOM uint32_t IC_STATUS; /*!< I2C Status Register This is a read-only register used to indicate + the current transfer status and FIFO status. The status + register may be read at any time. None of the bits in this + register request an interrupt. When the I2C is disabled + by writing 0 in bit 0 of the IC_ENABLE register: - Bits + 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When + the master or slave state machines goes to idle and ic_en=0: + - Bits 5 and 6 are set to 0 */ + __IOM uint32_t IC_TXFLR; /*!< I2C Transmit FIFO Level Register This register contains the + number of valid data entries in the transmit FIFO buffer. + It is cleared whenever: - The I2C is disabled - There is + a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT + register - The slave bulk transmit mode is aborted The + register increments whenever data is placed into the transmit + FIFO and decrements when data is taken from the transmit + FIFO. */ + __IOM uint32_t IC_RXFLR; /*!< I2C Receive FIFO Level Register This register contains the number + of valid data entries in the receive FIFO buffer. It is + cleared whenever: - The I2C is disabled - Whenever there + is a transmit abort caused by any of the events tracked + in IC_TX_ABRT_SOURCE The register increments whenever data + is placed into the receive FIFO and decrements when data + is taken from the receive FIFO. */ + __IOM uint32_t IC_SDA_HOLD; /*!< I2C SDA Hold Time Length Register The bits [15:0] of this register + are used to control the hold time of SDA during transmit + in both slave and master mode (after SCL goes from HIGH + to LOW). The bits [23:16] of this register are used to + extend the SDA transition (if any) whenever SCL is HIGH + in the receiver in either master or slave mode. Writes + to this register succeed only when IC_ENABLE[0]=0. The + values in this register are in units of ic_clk period. + The value programmed in IC_SDA_TX_HOLD must be greater + than the minimum hold time in each mode (one cycle in master + mode, seven cycles in slave mode) for the value to be implemented. + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) + cannot exceed at any time the duration of the low part + of scl. Therefore the programmed value cannot be larger + than N_SCL_LOW-2, where N_SCL_LOW is the duration of the + low part of the scl period measured in ic_clk cycles. */ + __IOM uint32_t IC_TX_ABRT_SOURCE; /*!< I2C Transmit Abort Source Register This register has 32 bits + that indicate the source of the TX_ABRT bit. Except for + Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT + register or the IC_CLR_INTR register is read. To clear + Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed + first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL + bit must be cleared (IC_TAR[11]), or the GC_OR_START bit + must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT + is fixed, then this bit can be cleared in the same manner + as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT + is not fixed before attempting to clear this bit, Bit 9 + clears for one cycle and is then re-asserted. */ + __IOM uint32_t IC_SLV_DATA_NACK_ONLY; /*!< Generate Slave Data NACK Register The register is used to generate + a NACK for the data part of a transfer when DW_apb_i2c + is acting as a slave-receiver. This register only exists + when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When + this parameter disabled, this register does not exist and + writing to the register's address has no effect. A write + can occur on this register if both of the following conditions + are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - + Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] + is a register read-back location for the internal slv_activity + signal; the user should poll this before writing the ic_slv_data_nack_onl + bit. */ + __IOM uint32_t IC_DMA_CR; /*!< DMA Control Register The register is used to enable the DMA + Controller interface operation. There is a separate bit + for transmit and receive. This can be programmed regardless + of the state of IC_ENABLE. */ + __IOM uint32_t IC_DMA_TDLR; /*!< DMA Transmit Data Level Register */ + __IOM uint32_t IC_DMA_RDLR; /*!< I2C Receive Data Level Register */ + __IOM uint32_t IC_SDA_SETUP; /*!< I2C SDA Setup Register This register controls the amount of + time delay (in terms of number of ic_clk clock periods) + introduced in the rising edge of SCL - relative to SDA + changing - when DW_apb_i2c services a read request in a + slave-transmitter operation. The relevant I2C requirement + is tSU:DAT (note 4) as detailed in the I2C Bus Specification. + This register must be programmed with a value equal to + or greater than 2. Writes to this register succeed only + when IC_ENABLE[0] = 0. Note: The length of setup time is + calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], + so if the user requires 10 ic_clk periods of setup time, + they should program a value of 11. The IC_SDA_SETUP register + is only used by the DW_apb_i2c when operating as a slave + transmitter. */ + __IOM uint32_t IC_ACK_GENERAL_CALL; /*!< I2C ACK General Call Register The register controls whether + DW_apb_i2c responds with a ACK or NACK when it receives + an I2C General Call address. This register is applicable + only when the DW_apb_i2c is in slave mode. */ + __IOM uint32_t IC_ENABLE_STATUS; /*!< I2C Enable Status Register The register is used to report the + DW_apb_i2c hardware status when the IC_ENABLE[0] register + is set from 1 to 0; that is, when DW_apb_i2c is disabled. + If IC_ENABLE[0] has been set to 1, bits 2:1 are forced + to 0, and bit 0 is forced to 1. If IC_ENABLE[0] has been + set to 0, bits 2:1 is only be valid as soon as bit 0 is + read as '0'. Note: When IC_ENABLE[0] has been set to 0, + a delay occurs for bit 0 to be read as 0 because disabling + the DW_apb_i2c depends on I2C bus activities. */ + __IOM uint32_t IC_FS_SPKLEN; /*!< I2C SS, FS or FM+ spike suppression limit This register is used + to store the duration, measured in ic_clk cycles, of the + longest spike that is filtered out by the spike suppression + logic when the component is operating in SS, FS or FM+ + modes. The relevant I2C requirement is tSP (table 4) as + detailed in the I2C Bus Specification. This register must + be programmed with a minimum value of 1. */ + __IM uint32_t RESERVED2; + __IOM uint32_t IC_CLR_RESTART_DET; /*!< Clear RESTART_DET Interrupt Register */ + __IM uint32_t RESERVED3[18]; + __IOM uint32_t IC_COMP_PARAM_1; /*!< Component Parameter Register 1 Note This register is not implemented + and therefore reads as 0. If it was implemented it would + be a constant read-only register that contains encoded + information about the component's parameter settings. Fields + shown below are the settings for those parameters */ + __IOM uint32_t IC_COMP_VERSION; /*!< I2C Component Version Register */ + __IOM uint32_t IC_COMP_TYPE; /*!< I2C Component Type Register */ +} I2C0_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI0 (SPI0) + */ + +typedef struct { /*!< SPI0 Structure */ + __IOM uint32_t SSPCR0; /*!< Control register 0, SSPCR0 on page 3-4 */ + __IOM uint32_t SSPCR1; /*!< Control register 1, SSPCR1 on page 3-5 */ + __IOM uint32_t SSPDR; /*!< Data register, SSPDR on page 3-6 */ + __IOM uint32_t SSPSR; /*!< Status register, SSPSR on page 3-7 */ + __IOM uint32_t SSPCPSR; /*!< Clock prescale register, SSPCPSR on page 3-8 */ + __IOM uint32_t SSPIMSC; /*!< Interrupt mask set or clear register, SSPIMSC on page 3-9 */ + __IOM uint32_t SSPRIS; /*!< Raw interrupt status register, SSPRIS on page 3-10 */ + __IOM uint32_t SSPMIS; /*!< Masked interrupt status register, SSPMIS on page 3-11 */ + __IOM uint32_t SSPICR; /*!< Interrupt clear register, SSPICR on page 3-11 */ + __IOM uint32_t SSPDMACR; /*!< DMA control register, SSPDMACR on page 3-12 */ + __IM uint32_t RESERVED[1006]; + __IOM uint32_t SSPPERIPHID0; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPERIPHID1; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPERIPHID2; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPERIPHID3; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPCELLID0; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + __IOM uint32_t SSPPCELLID1; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + __IOM uint32_t SSPPCELLID2; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + __IOM uint32_t SSPPCELLID3; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ +} SPI0_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ PIO0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable IO block (PIO0) + */ + +typedef struct { /*!< PIO0 Structure */ + __IOM uint32_t CTRL; /*!< PIO control register */ + __IOM uint32_t FSTAT; /*!< FIFO status register */ + __IOM uint32_t FDEBUG; /*!< FIFO debug register */ + __IOM uint32_t FLEVEL; /*!< FIFO levels */ + __IOM uint32_t TXF0; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t TXF1; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t TXF2; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t TXF3; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t RXF0; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t RXF1; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t RXF2; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t RXF3; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t IRQ; /*!< State machine IRQ flags register. Write 1 to clear. There are + 8 state machine IRQ flags, which can be set, cleared, and + waited on by the state machines. There's no fixed association + between flags and state machines -- any state machine can + use any flag. Any of the 8 flags can be used for timing + synchronisation between state machines, using IRQ and WAIT + instructions. The lower four of these flags are also routed + out to system-level interrupt requests, alongside FIFO + status interrupts -- see e.g. IRQ0_INTE. */ + __IOM uint32_t IRQ_FORCE; /*!< Writing a 1 to each of these bits will forcibly assert the corresponding + IRQ. Note this is different to the INTF register: writing + here affects PIO internal state. INTF just asserts the + processor-facing IRQ signal for testing ISRs, and is not + visible to the state machines. */ + __IOM uint32_t INPUT_SYNC_BYPASS; /*!< There is a 2-flipflop synchronizer on each GPIO input, which + protects PIO logic from metastabilities. This increases + input delay, and for fast synchronous IO (e.g. SPI) these + synchronizers may need to be bypassed. Each bit in this + register corresponds to one GPIO. 0 -> input is synchronized + (default) 1 -> synchronizer is bypassed If in doubt, leave + this register as all zeroes. */ + __IOM uint32_t DBG_PADOUT; /*!< Read to sample the pad output values PIO is currently driving + to the GPIOs. On RP2040 there are 30 GPIOs, so the two + most significant bits are hardwired to 0. */ + __IOM uint32_t DBG_PADOE; /*!< Read to sample the pad output enables (direction) PIO is currently + driving to the GPIOs. On RP2040 there are 30 GPIOs, so + the two most significant bits are hardwired to 0. */ + __IOM uint32_t DBG_CFGINFO; /*!< The PIO hardware has some free parameters that may vary between + chip products. These should be provided in the chip datasheet, + but are also exposed here. */ + __IOM uint32_t INSTR_MEM0; /*!< Write-only access to instruction memory location 0 */ + __IOM uint32_t INSTR_MEM1; /*!< Write-only access to instruction memory location 1 */ + __IOM uint32_t INSTR_MEM2; /*!< Write-only access to instruction memory location 2 */ + __IOM uint32_t INSTR_MEM3; /*!< Write-only access to instruction memory location 3 */ + __IOM uint32_t INSTR_MEM4; /*!< Write-only access to instruction memory location 4 */ + __IOM uint32_t INSTR_MEM5; /*!< Write-only access to instruction memory location 5 */ + __IOM uint32_t INSTR_MEM6; /*!< Write-only access to instruction memory location 6 */ + __IOM uint32_t INSTR_MEM7; /*!< Write-only access to instruction memory location 7 */ + __IOM uint32_t INSTR_MEM8; /*!< Write-only access to instruction memory location 8 */ + __IOM uint32_t INSTR_MEM9; /*!< Write-only access to instruction memory location 9 */ + __IOM uint32_t INSTR_MEM10; /*!< Write-only access to instruction memory location 10 */ + __IOM uint32_t INSTR_MEM11; /*!< Write-only access to instruction memory location 11 */ + __IOM uint32_t INSTR_MEM12; /*!< Write-only access to instruction memory location 12 */ + __IOM uint32_t INSTR_MEM13; /*!< Write-only access to instruction memory location 13 */ + __IOM uint32_t INSTR_MEM14; /*!< Write-only access to instruction memory location 14 */ + __IOM uint32_t INSTR_MEM15; /*!< Write-only access to instruction memory location 15 */ + __IOM uint32_t INSTR_MEM16; /*!< Write-only access to instruction memory location 16 */ + __IOM uint32_t INSTR_MEM17; /*!< Write-only access to instruction memory location 17 */ + __IOM uint32_t INSTR_MEM18; /*!< Write-only access to instruction memory location 18 */ + __IOM uint32_t INSTR_MEM19; /*!< Write-only access to instruction memory location 19 */ + __IOM uint32_t INSTR_MEM20; /*!< Write-only access to instruction memory location 20 */ + __IOM uint32_t INSTR_MEM21; /*!< Write-only access to instruction memory location 21 */ + __IOM uint32_t INSTR_MEM22; /*!< Write-only access to instruction memory location 22 */ + __IOM uint32_t INSTR_MEM23; /*!< Write-only access to instruction memory location 23 */ + __IOM uint32_t INSTR_MEM24; /*!< Write-only access to instruction memory location 24 */ + __IOM uint32_t INSTR_MEM25; /*!< Write-only access to instruction memory location 25 */ + __IOM uint32_t INSTR_MEM26; /*!< Write-only access to instruction memory location 26 */ + __IOM uint32_t INSTR_MEM27; /*!< Write-only access to instruction memory location 27 */ + __IOM uint32_t INSTR_MEM28; /*!< Write-only access to instruction memory location 28 */ + __IOM uint32_t INSTR_MEM29; /*!< Write-only access to instruction memory location 29 */ + __IOM uint32_t INSTR_MEM30; /*!< Write-only access to instruction memory location 30 */ + __IOM uint32_t INSTR_MEM31; /*!< Write-only access to instruction memory location 31 */ + __IOM uint32_t SM0_CLKDIV; /*!< Clock divisor register for state machine 0 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM0_EXECCTRL; /*!< Execution/behavioural settings for state machine 0 */ + __IOM uint32_t SM0_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 0 */ + __IOM uint32_t SM0_ADDR; /*!< Current instruction address of state machine 0 */ + __IOM uint32_t SM0_INSTR; /*!< Read to see the instruction currently addressed by state machine + 0's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM0_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t SM1_CLKDIV; /*!< Clock divisor register for state machine 1 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM1_EXECCTRL; /*!< Execution/behavioural settings for state machine 1 */ + __IOM uint32_t SM1_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 1 */ + __IOM uint32_t SM1_ADDR; /*!< Current instruction address of state machine 1 */ + __IOM uint32_t SM1_INSTR; /*!< Read to see the instruction currently addressed by state machine + 1's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM1_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t SM2_CLKDIV; /*!< Clock divisor register for state machine 2 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM2_EXECCTRL; /*!< Execution/behavioural settings for state machine 2 */ + __IOM uint32_t SM2_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 2 */ + __IOM uint32_t SM2_ADDR; /*!< Current instruction address of state machine 2 */ + __IOM uint32_t SM2_INSTR; /*!< Read to see the instruction currently addressed by state machine + 2's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM2_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t SM3_CLKDIV; /*!< Clock divisor register for state machine 3 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM3_EXECCTRL; /*!< Execution/behavioural settings for state machine 3 */ + __IOM uint32_t SM3_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 3 */ + __IOM uint32_t SM3_ADDR; /*!< Current instruction address of state machine 3 */ + __IOM uint32_t SM3_INSTR; /*!< Read to see the instruction currently addressed by state machine + 3's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM3_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t IRQ0_INTE; /*!< Interrupt Enable for irq0 */ + __IOM uint32_t IRQ0_INTF; /*!< Interrupt Force for irq0 */ + __IOM uint32_t IRQ0_INTS; /*!< Interrupt status after masking & forcing for irq0 */ + __IOM uint32_t IRQ1_INTE; /*!< Interrupt Enable for irq1 */ + __IOM uint32_t IRQ1_INTF; /*!< Interrupt Force for irq1 */ + __IOM uint32_t IRQ1_INTS; /*!< Interrupt status after masking & forcing for irq1 */ +} PIO0_Type; /*!< Size = 324 (0x144) */ + + + +/* =========================================================================================================================== */ +/* ================ BUSCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Register block for busfabric control signals and performance counters (BUSCTRL) + */ + +typedef struct { /*!< BUSCTRL Structure */ + __IOM uint32_t BUS_PRIORITY; /*!< Set the priority of each master for bus arbitration. */ + __IOM uint32_t BUS_PRIORITY_ACK; /*!< Bus priority acknowledge */ + __IOM uint32_t PERFCTR0; /*!< Bus fabric performance counter 0 */ + __IOM uint32_t PERFSEL0; /*!< Bus fabric performance event select for PERFCTR0 */ + __IOM uint32_t PERFCTR1; /*!< Bus fabric performance counter 1 */ + __IOM uint32_t PERFSEL1; /*!< Bus fabric performance event select for PERFCTR1 */ + __IOM uint32_t PERFCTR2; /*!< Bus fabric performance counter 2 */ + __IOM uint32_t PERFSEL2; /*!< Bus fabric performance event select for PERFCTR2 */ + __IOM uint32_t PERFCTR3; /*!< Bus fabric performance counter 3 */ + __IOM uint32_t PERFSEL3; /*!< Bus fabric performance event select for PERFCTR3 */ +} BUSCTRL_Type; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ SIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Single-cycle IO block + Provides core-local and inter-core hardware for the two processors, with single-cycle access. (SIO) + */ + +typedef struct { /*!< SIO Structure */ + __IOM uint32_t CPUID; /*!< Processor core identifier */ + __IOM uint32_t GPIO_IN; /*!< Input value for GPIO pins */ + __IOM uint32_t GPIO_HI_IN; /*!< Input value for QSPI pins */ + __IM uint32_t RESERVED; + __IOM uint32_t GPIO_OUT; /*!< GPIO output value */ + __IOM uint32_t GPIO_OUT_SET; /*!< GPIO output value set */ + __IOM uint32_t GPIO_OUT_CLR; /*!< GPIO output value clear */ + __IOM uint32_t GPIO_OUT_XOR; /*!< GPIO output value XOR */ + __IOM uint32_t GPIO_OE; /*!< GPIO output enable */ + __IOM uint32_t GPIO_OE_SET; /*!< GPIO output enable set */ + __IOM uint32_t GPIO_OE_CLR; /*!< GPIO output enable clear */ + __IOM uint32_t GPIO_OE_XOR; /*!< GPIO output enable XOR */ + __IOM uint32_t GPIO_HI_OUT; /*!< QSPI output value */ + __IOM uint32_t GPIO_HI_OUT_SET; /*!< QSPI output value set */ + __IOM uint32_t GPIO_HI_OUT_CLR; /*!< QSPI output value clear */ + __IOM uint32_t GPIO_HI_OUT_XOR; /*!< QSPI output value XOR */ + __IOM uint32_t GPIO_HI_OE; /*!< QSPI output enable */ + __IOM uint32_t GPIO_HI_OE_SET; /*!< QSPI output enable set */ + __IOM uint32_t GPIO_HI_OE_CLR; /*!< QSPI output enable clear */ + __IOM uint32_t GPIO_HI_OE_XOR; /*!< QSPI output enable XOR */ + __IOM uint32_t FIFO_ST; /*!< Status register for inter-core FIFOs (mailboxes). There is one + FIFO in the core 0 -> core 1 direction, and one core 1 + -> core 0. Both are 32 bits wide and 8 words deep. Core + 0 can see the read side of the 1->0 FIFO (RX), and the + write side of 0->1 FIFO (TX). Core 1 can see the read side + of the 0->1 FIFO (RX), and the write side of 1->0 FIFO + (TX). The SIO IRQ for each core is the logical OR of the + VLD, WOF and ROE fields of its FIFO_ST register. */ + __IOM uint32_t FIFO_WR; /*!< Write access to this core's TX FIFO */ + __IOM uint32_t FIFO_RD; /*!< Read access to this core's RX FIFO */ + __IOM uint32_t SPINLOCK_ST; /*!< Spinlock state A bitmap containing the state of all 32 spinlocks + (1=locked). Mainly intended for debugging. */ + __IOM uint32_t DIV_UDIVIDEND; /*!< Divider unsigned dividend Write to the DIVIDEND operand of the + divider, i.e. the p in `p / q`. Any operand write starts + a new calculation. The results appear in QUOTIENT, REMAINDER. + UDIVIDEND/SDIVIDEND are aliases of the same internal register. + The U alias starts an unsigned calculation, and the S alias + starts a signed calculation. */ + __IOM uint32_t DIV_UDIVISOR; /*!< Divider unsigned divisor Write to the DIVISOR operand of the + divider, i.e. the q in `p / q`. Any operand write starts + a new calculation. The results appear in QUOTIENT, REMAINDER. + UDIVISOR/SDIVISOR are aliases of the same internal register. + The U alias starts an unsigned calculation, and the S alias + starts a signed calculation. */ + __IOM uint32_t DIV_SDIVIDEND; /*!< Divider signed dividend The same as UDIVIDEND, but starts a + signed calculation, rather than unsigned. */ + __IOM uint32_t DIV_SDIVISOR; /*!< Divider signed divisor The same as UDIVISOR, but starts a signed + calculation, rather than unsigned. */ + __IOM uint32_t DIV_QUOTIENT; /*!< Divider result quotient The result of `DIVIDEND / DIVISOR` (division). + Contents undefined while CSR_READY is low. For signed calculations, + QUOTIENT is negative when the signs of DIVIDEND and DIVISOR + differ. This register can be written to directly, for context + save/restore purposes. This halts any in-progress calculation + and sets the CSR_READY and CSR_DIRTY flags. Reading from + QUOTIENT clears the CSR_DIRTY flag, so should read results + in the order REMAINDER, QUOTIENT if CSR_DIRTY is used. */ + __IOM uint32_t DIV_REMAINDER; /*!< Divider result remainder The result of `DIVIDEND % DIVISOR` + (modulo). Contents undefined while CSR_READY is low. For + signed calculations, REMAINDER is negative only when DIVIDEND + is negative. This register can be written to directly, + for context save/restore purposes. This halts any in-progress + calculation and sets the CSR_READY and CSR_DIRTY flags. */ + __IOM uint32_t DIV_CSR; /*!< Control and status register for divider. */ + __IM uint32_t RESERVED1; + __IOM uint32_t INTERP0_ACCUM0; /*!< Read/write access to accumulator 0 */ + __IOM uint32_t INTERP0_ACCUM1; /*!< Read/write access to accumulator 1 */ + __IOM uint32_t INTERP0_BASE0; /*!< Read/write access to BASE0 register. */ + __IOM uint32_t INTERP0_BASE1; /*!< Read/write access to BASE1 register. */ + __IOM uint32_t INTERP0_BASE2; /*!< Read/write access to BASE2 register. */ + __IOM uint32_t INTERP0_POP_LANE0; /*!< Read LANE0 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP0_POP_LANE1; /*!< Read LANE1 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP0_POP_FULL; /*!< Read FULL result, and simultaneously write lane results to both + accumulators (POP). */ + __IOM uint32_t INTERP0_PEEK_LANE0; /*!< Read LANE0 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP0_PEEK_LANE1; /*!< Read LANE1 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP0_PEEK_FULL; /*!< Read FULL result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP0_CTRL_LANE0; /*!< Control register for lane 0 */ + __IOM uint32_t INTERP0_CTRL_LANE1; /*!< Control register for lane 1 */ + __IOM uint32_t INTERP0_ACCUM0_ADD; /*!< Values written here are atomically added to ACCUM0 Reading yields + lane 0's raw shift and mask value (BASE0 not added). */ + __IOM uint32_t INTERP0_ACCUM1_ADD; /*!< Values written here are atomically added to ACCUM1 Reading yields + lane 1's raw shift and mask value (BASE1 not added). */ + __IOM uint32_t INTERP0_BASE_1AND0; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 + simultaneously. Each half is sign-extended to 32 bits if + that lane's SIGNED flag is set. */ + __IOM uint32_t INTERP1_ACCUM0; /*!< Read/write access to accumulator 0 */ + __IOM uint32_t INTERP1_ACCUM1; /*!< Read/write access to accumulator 1 */ + __IOM uint32_t INTERP1_BASE0; /*!< Read/write access to BASE0 register. */ + __IOM uint32_t INTERP1_BASE1; /*!< Read/write access to BASE1 register. */ + __IOM uint32_t INTERP1_BASE2; /*!< Read/write access to BASE2 register. */ + __IOM uint32_t INTERP1_POP_LANE0; /*!< Read LANE0 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP1_POP_LANE1; /*!< Read LANE1 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP1_POP_FULL; /*!< Read FULL result, and simultaneously write lane results to both + accumulators (POP). */ + __IOM uint32_t INTERP1_PEEK_LANE0; /*!< Read LANE0 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP1_PEEK_LANE1; /*!< Read LANE1 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP1_PEEK_FULL; /*!< Read FULL result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP1_CTRL_LANE0; /*!< Control register for lane 0 */ + __IOM uint32_t INTERP1_CTRL_LANE1; /*!< Control register for lane 1 */ + __IOM uint32_t INTERP1_ACCUM0_ADD; /*!< Values written here are atomically added to ACCUM0 Reading yields + lane 0's raw shift and mask value (BASE0 not added). */ + __IOM uint32_t INTERP1_ACCUM1_ADD; /*!< Values written here are atomically added to ACCUM1 Reading yields + lane 1's raw shift and mask value (BASE1 not added). */ + __IOM uint32_t INTERP1_BASE_1AND0; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 + simultaneously. Each half is sign-extended to 32 bits if + that lane's SIGNED flag is set. */ + __IOM uint32_t SPINLOCK0; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK1; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK2; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK3; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK4; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK5; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK6; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK7; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK8; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK9; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK10; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK11; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK12; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK13; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK14; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK15; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK16; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK17; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK18; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK19; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK20; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK21; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK22; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK23; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK24; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK25; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK26; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK27; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK28; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK29; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK30; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK31; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ +} SIO_Type; /*!< Size = 384 (0x180) */ + + + +/* =========================================================================================================================== */ +/* ================ USB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief USB FS/LS controller device registers (USB) + */ + +typedef struct { /*!< USB Structure */ + __IOM uint32_t ADDR_ENDP; /*!< Device address and endpoint control */ + __IOM uint32_t ADDR_ENDP1; /*!< Interrupt endpoint 1. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP2; /*!< Interrupt endpoint 2. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP3; /*!< Interrupt endpoint 3. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP4; /*!< Interrupt endpoint 4. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP5; /*!< Interrupt endpoint 5. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP6; /*!< Interrupt endpoint 6. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP7; /*!< Interrupt endpoint 7. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP8; /*!< Interrupt endpoint 8. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP9; /*!< Interrupt endpoint 9. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP10; /*!< Interrupt endpoint 10. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP11; /*!< Interrupt endpoint 11. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP12; /*!< Interrupt endpoint 12. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP13; /*!< Interrupt endpoint 13. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP14; /*!< Interrupt endpoint 14. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP15; /*!< Interrupt endpoint 15. Only valid for HOST mode. */ + __IOM uint32_t MAIN_CTRL; /*!< Main control register */ + __IOM uint32_t SOF_WR; /*!< Set the SOF (Start of Frame) frame number in the host controller. + The SOF packet is sent every 1ms and the host will increment + the frame number by 1 each time. */ + __IOM uint32_t SOF_RD; /*!< Read the last SOF (Start of Frame) frame number seen. In device + mode the last SOF received from the host. In host mode + the last SOF sent by the host. */ + __IOM uint32_t SIE_CTRL; /*!< SIE control register */ + __IOM uint32_t SIE_STATUS; /*!< SIE status register */ + __IOM uint32_t INT_EP_CTRL; /*!< interrupt endpoint control register */ + __IOM uint32_t BUFF_STATUS; /*!< Buffer status register. A bit set here indicates that a buffer + has completed on the endpoint (if the buffer interrupt + is enabled). It is possible for 2 buffers to be completed, + so clearing the buffer status bit may instantly re set + it on the next clock cycle. */ + __IOM uint32_t BUFF_CPU_SHOULD_HANDLE; /*!< Which of the double buffers should be handled. Only valid if + using an interrupt per buffer (i.e. not per 2 buffers). + Not valid for host interrupt endpoint polling because they + are only single buffered. */ + __IOM uint32_t EP_ABORT; /*!< Device only: Can be set to ignore the buffer control register + for this endpoint in case you would like to revoke a buffer. + A NAK will be sent for every access to the endpoint until + this bit is cleared. A corresponding bit in `EP_ABORT_DONE` + is set when it is safe to modify the buffer control register. */ + __IOM uint32_t EP_ABORT_DONE; /*!< Device only: Used in conjunction with `EP_ABORT`. Set once an + endpoint is idle so the programmer knows it is safe to + modify the buffer control register. */ + __IOM uint32_t EP_STALL_ARM; /*!< Device: this bit must be set in conjunction with the `STALL` + bit in the buffer control register to send a STALL on EP0. + The device controller clears these bits when a SETUP packet + is received because the USB spec requires that a STALL + condition is cleared when a SETUP packet is received. */ + __IOM uint32_t NAK_POLL; /*!< Used by the host controller. Sets the wait time in microseconds + before trying again if the device replies with a NAK. */ + __IOM uint32_t EP_STATUS_STALL_NAK; /*!< Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` + bits are set. For EP0 this comes from `SIE_CTRL`. For all + other endpoints it comes from the endpoint control register. */ + __IOM uint32_t USB_MUXING; /*!< Where to connect the USB controller. Should be to_phy by default. */ + __IOM uint32_t USB_PWR; /*!< Overrides for the power signals in the event that the VBUS signals + are not hooked up to GPIO. Set the value of the override + and then the override enable so switch over to the override + value. */ + __IOM uint32_t USBPHY_DIRECT; /*!< Note that most functions are driven directly from usb_fsls controller. + This register allows more detailed control/status from + the USB PHY. Useful for debug but not expected to be used + in normal operation Use in conjunction with usbphy_direct_override + register */ + __IOM uint32_t USBPHY_DIRECT_OVERRIDE; /*!< USBPHY_DIRECT_OVERRIDE */ + __IOM uint32_t USBPHY_TRIM; /*!< Note that most functions are driven directly from usb_fsls controller. + This register allows more detailed control/status from + the USB PHY. Useful for debug but not expected to be used + in normal operation */ + __IM uint32_t RESERVED; + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} USB_Type; /*!< Size = 156 (0x9c) */ + + + +/* =========================================================================================================================== */ +/* ================ USB_DPRAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DPRAM layout for USB device. (USB_DPRAM) + */ + +typedef struct { /*!< USB_DPRAM Structure */ + __IOM uint32_t SETUP_PACKET_LOW; /*!< Bytes 0-3 of the SETUP packet from the host. */ + __IOM uint32_t SETUP_PACKET_HIGH; /*!< Bytes 4-7 of the setup packet from the host. */ + __IOM uint32_t EP1_IN_CONTROL; /*!< EP1_IN_CONTROL */ + __IOM uint32_t EP1_OUT_CONTROL; /*!< EP1_OUT_CONTROL */ + __IOM uint32_t EP2_IN_CONTROL; /*!< EP2_IN_CONTROL */ + __IOM uint32_t EP2_OUT_CONTROL; /*!< EP2_OUT_CONTROL */ + __IOM uint32_t EP3_IN_CONTROL; /*!< EP3_IN_CONTROL */ + __IOM uint32_t EP3_OUT_CONTROL; /*!< EP3_OUT_CONTROL */ + __IOM uint32_t EP4_IN_CONTROL; /*!< EP4_IN_CONTROL */ + __IOM uint32_t EP4_OUT_CONTROL; /*!< EP4_OUT_CONTROL */ + __IOM uint32_t EP5_IN_CONTROL; /*!< EP5_IN_CONTROL */ + __IOM uint32_t EP5_OUT_CONTROL; /*!< EP5_OUT_CONTROL */ + __IOM uint32_t EP6_IN_CONTROL; /*!< EP6_IN_CONTROL */ + __IOM uint32_t EP6_OUT_CONTROL; /*!< EP6_OUT_CONTROL */ + __IOM uint32_t EP7_IN_CONTROL; /*!< EP7_IN_CONTROL */ + __IOM uint32_t EP7_OUT_CONTROL; /*!< EP7_OUT_CONTROL */ + __IOM uint32_t EP8_IN_CONTROL; /*!< EP8_IN_CONTROL */ + __IOM uint32_t EP8_OUT_CONTROL; /*!< EP8_OUT_CONTROL */ + __IOM uint32_t EP9_IN_CONTROL; /*!< EP9_IN_CONTROL */ + __IOM uint32_t EP9_OUT_CONTROL; /*!< EP9_OUT_CONTROL */ + __IOM uint32_t EP10_IN_CONTROL; /*!< EP10_IN_CONTROL */ + __IOM uint32_t EP10_OUT_CONTROL; /*!< EP10_OUT_CONTROL */ + __IOM uint32_t EP11_IN_CONTROL; /*!< EP11_IN_CONTROL */ + __IOM uint32_t EP11_OUT_CONTROL; /*!< EP11_OUT_CONTROL */ + __IOM uint32_t EP12_IN_CONTROL; /*!< EP12_IN_CONTROL */ + __IOM uint32_t EP12_OUT_CONTROL; /*!< EP12_OUT_CONTROL */ + __IOM uint32_t EP13_IN_CONTROL; /*!< EP13_IN_CONTROL */ + __IOM uint32_t EP13_OUT_CONTROL; /*!< EP13_OUT_CONTROL */ + __IOM uint32_t EP14_IN_CONTROL; /*!< EP14_IN_CONTROL */ + __IOM uint32_t EP14_OUT_CONTROL; /*!< EP14_OUT_CONTROL */ + __IOM uint32_t EP15_IN_CONTROL; /*!< EP15_IN_CONTROL */ + __IOM uint32_t EP15_OUT_CONTROL; /*!< EP15_OUT_CONTROL */ + __IOM uint32_t EP0_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP0_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP1_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP1_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP2_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP2_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP3_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP3_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP4_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP4_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP5_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP5_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP6_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP6_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP7_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP7_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP8_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP8_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP9_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP9_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP10_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP10_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP11_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP11_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP12_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP12_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP13_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP13_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP14_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP14_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP15_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP15_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ +} USB_DPRAM_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ TBMAN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Testbench manager. Allows the programmer to know what platform their software is running on. (TBMAN) + */ + +typedef struct { /*!< TBMAN Structure */ + __IOM uint32_t PLATFORM; /*!< Indicates the type of platform in use */ +} TBMAN_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ VREG_AND_CHIP_RESET ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief control and status for on-chip voltage regulator and chip level reset subsystem (VREG_AND_CHIP_RESET) + */ + +typedef struct { /*!< VREG_AND_CHIP_RESET Structure */ + __IOM uint32_t VREG; /*!< Voltage regulator control and status */ + __IOM uint32_t BOD; /*!< brown-out detection control */ + __IOM uint32_t CHIP_RESET; /*!< Chip reset control and status */ +} VREG_AND_CHIP_RESET_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Register block to control RTC (RTC) + */ + +typedef struct { /*!< RTC Structure */ + __IOM uint32_t CLKDIV_M1; /*!< Divider minus 1 for the 1 second counter. Safe to change the + value when RTC is not enabled. */ + __IOM uint32_t SETUP_0; /*!< RTC setup register 0 */ + __IOM uint32_t SETUP_1; /*!< RTC setup register 1 */ + __IOM uint32_t CTRL; /*!< RTC Control and status */ + __IOM uint32_t IRQ_SETUP_0; /*!< Interrupt setup register 0 */ + __IOM uint32_t IRQ_SETUP_1; /*!< Interrupt setup register 1 */ + __IOM uint32_t RTC_1; /*!< RTC register 1. */ + __IOM uint32_t RTC_0; /*!< RTC register 0 Read this before RTC 1! */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} RTC_Type; /*!< Size = 48 (0x30) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#if 0 +#define RESETS_BASE 0x4000C000UL +#define PSM_BASE 0x40010000UL +#define CLOCKS_BASE 0x40008000UL +#define PADS_BANK0_BASE 0x4001C000UL +#define PADS_QSPI_BASE 0x40020000UL +#define IO_QSPI_BASE 0x40018000UL +#define IO_BANK0_BASE 0x40014000UL +#define SYSINFO_BASE 0x40000000UL +#define PPB_BASE 0xE0000000UL +#define SSI_BASE 0x18000000UL +#define XIP_CTRL_BASE 0x14000000UL +#define SYSCFG_BASE 0x40004000UL +#define XOSC_BASE 0x40024000UL +#define PLL_SYS_BASE 0x40028000UL +#define PLL_USB_BASE 0x4002C000UL +#define UART0_BASE 0x40034000UL +#define UART1_BASE 0x40038000UL +#define ROSC_BASE 0x40060000UL +#define WATCHDOG_BASE 0x40058000UL +#define DMA_BASE 0x50000000UL +#define TIMER_BASE 0x40054000UL +#define PWM_BASE 0x40050000UL +#define ADC_BASE 0x4004C000UL +#define I2C0_BASE 0x40044000UL +#define I2C1_BASE 0x40048000UL +#define SPI0_BASE 0x4003C000UL +#define SPI1_BASE 0x40040000UL +#define PIO0_BASE 0x50200000UL +#define PIO1_BASE 0x50300000UL +#define BUSCTRL_BASE 0x40030000UL +#define SIO_BASE 0xD0000000UL +#define USB_BASE 0x50110000UL +#define USB_DPRAM_BASE 0x50100000UL +#define TBMAN_BASE 0x4006C000UL +#define VREG_AND_CHIP_RESET_BASE 0x40064000UL +#define RTC_BASE 0x4005C000UL +#endif + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define RESETS ((RESETS_Type*) RESETS_BASE) +#define PSM ((PSM_Type*) PSM_BASE) +#define CLOCKS ((CLOCKS_Type*) CLOCKS_BASE) +#define PADS_BANK0 ((PADS_BANK0_Type*) PADS_BANK0_BASE) +#define PADS_QSPI ((PADS_QSPI_Type*) PADS_QSPI_BASE) +#define IO_QSPI ((IO_QSPI_Type*) IO_QSPI_BASE) +#define IO_BANK0 ((IO_BANK0_Type*) IO_BANK0_BASE) +#define SYSINFO ((SYSINFO_Type*) SYSINFO_BASE) +#define PPB ((PPB_Type*) PPB_BASE) +#define SSI ((SSI_Type*) SSI_BASE) +#define XIP_CTRL ((XIP_CTRL_Type*) XIP_CTRL_BASE) +#define SYSCFG ((SYSCFG_Type*) SYSCFG_BASE) +#define XOSC ((XOSC_Type*) XOSC_BASE) +#define PLL_SYS ((PLL_SYS_Type*) PLL_SYS_BASE) +#define PLL_USB ((PLL_SYS_Type*) PLL_USB_BASE) +#define UART0 ((UART0_Type*) UART0_BASE) +#define UART1 ((UART0_Type*) UART1_BASE) +#define ROSC ((ROSC_Type*) ROSC_BASE) +#define WATCHDOG ((WATCHDOG_Type*) WATCHDOG_BASE) +#define DMA ((DMA_Type*) DMA_BASE) +#define TIMER ((TIMER_Type*) TIMER_BASE) +#define PWM ((PWM_Type*) PWM_BASE) +#define ADC ((ADC_Type*) ADC_BASE) +#define I2C0 ((I2C0_Type*) I2C0_BASE) +#define I2C1 ((I2C0_Type*) I2C1_BASE) +#define SPI0 ((SPI0_Type*) SPI0_BASE) +#define SPI1 ((SPI0_Type*) SPI1_BASE) +#define PIO0 ((PIO0_Type*) PIO0_BASE) +#define PIO1 ((PIO0_Type*) PIO1_BASE) +#define BUSCTRL ((BUSCTRL_Type*) BUSCTRL_BASE) +#define SIO ((SIO_Type*) SIO_BASE) +#define USB ((USB_Type*) USB_BASE) +#define USB_DPRAM ((USB_DPRAM_Type*) USB_DPRAM_BASE) +#define TBMAN ((TBMAN_Type*) TBMAN_BASE) +#define VREG_AND_CHIP_RESET ((VREG_AND_CHIP_RESET_Type*) VREG_AND_CHIP_RESET_BASE) +#define RTC ((RTC_Type*) RTC_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +#ifdef __cplusplus +} +#endif + +#endif /* RP2040_H */ + + +/** @} */ /* End of group RP2040 */ + +/** @} */ /* End of group Raspberry Pi */ diff --git a/lib/rp2040/cmsis_include/system_RP2040.h b/lib/pico-sdk/rp2040/cmsis_include/system_RP2040.h similarity index 100% rename from lib/rp2040/cmsis_include/system_RP2040.h rename to lib/pico-sdk/rp2040/cmsis_include/system_RP2040.h diff --git a/lib/pico-sdk/rp2040/hardware/platform_defs.h b/lib/pico-sdk/rp2040/hardware/platform_defs.h new file mode 100644 index 000000000000..54d9344c8cb1 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/platform_defs.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_PLATFORM_DEFS_H +#define _HARDWARE_PLATFORM_DEFS_H + +// This header is included from C and assembler - intended mostly for #defines; guard other stuff with #ifdef __ASSEMBLER__ + +#ifndef _u +#ifdef __ASSEMBLER__ +#define _u(x) x +#else +#define _u(x) x ## u +#endif +#endif + +#define NUM_CORES _u(2) +#define NUM_DMA_CHANNELS _u(12) +#define NUM_DMA_TIMERS _u(4) +#define NUM_DMA_IRQS _u(2) +#define NUM_IRQS _u(32) +#define NUM_USER_IRQS _u(6) +#define NUM_PIOS _u(2) +#define NUM_PIO_STATE_MACHINES _u(4) +#define NUM_PIO_IRQS _u(2) +#define NUM_PWM_SLICES _u(8) +#define NUM_PWM_IRQS _u(1) +#define NUM_SPIN_LOCKS _u(32) +#define NUM_UARTS _u(2) +#define NUM_I2CS _u(2) +#define NUM_SPIS _u(2) +#define NUM_GENERIC_TIMERS _u(1) +#define NUM_ALARMS _u(4) +#define ADC_BASE_PIN _u(26) +#define NUM_ADC_CHANNELS _u(5) +#define NUM_RESETS _u(24) +#define NUM_BANK0_GPIOS _u(30) +#define NUM_QSPI_GPIOS _u(6) + +#define PIO_INSTRUCTION_COUNT _u(32) + +#define USBCTRL_DPRAM_SIZE _u(4096) + +#define HAS_SIO_DIVIDER 1 +#define HAS_RP2040_RTC 1 +// PICO_CONFIG: XOSC_HZ, Crystal oscillator frequency in Hz, type=int, default=12000000, advanced=true, group=hardware_base +// NOTE: The system and USB clocks are generated from the frequency using two PLLs. +// If you override this define, or SYS_CLK_HZ/USB_CLK_HZ below, you will *also* need to add your own adjusted PLL set-up defines to +// override the defaults which live in src/rp2_common/hardware_clocks/include/hardware/clocks.h +// Please see the comments there about calculating the new PLL setting values. +#ifndef XOSC_HZ +#ifdef XOSC_KHZ +#define XOSC_HZ ((XOSC_KHZ) * _u(1000)) +#elif defined(XOSC_MHZ) +#define XOSC_HZ ((XOSC_MHZ) * _u(1000000)) +#else +#define XOSC_HZ _u(12000000) +#endif +#endif + +// PICO_CONFIG: SYS_CLK_HZ, System operating frequency in Hz, type=int, default=125000000, advanced=true, group=hardware_base +#ifndef SYS_CLK_HZ +#ifdef SYS_CLK_KHZ +#define SYS_CLK_HZ ((SYS_CLK_KHZ) * _u(1000)) +#elif defined(SYS_CLK_MHZ) +#define SYS_CLK_HZ ((SYS_CLK_MHZ) * _u(1000000)) +#else +#define SYS_CLK_HZ _u(125000000) +#endif +#endif + +// PICO_CONFIG: USB_CLK_HZ, USB clock frequency. Must be 48MHz for the USB interface to operate correctly, type=int, default=48000000, advanced=true, group=hardware_base +#ifndef USB_CLK_HZ +#ifdef USB_CLK_KHZ +#define USB_CLK_HZ ((USB_CLK_KHZ) * _u(1000)) +#elif defined(USB_CLK_MHZ) +#define USB_CLK_HZ ((USB_CLK_MHZ) * _u(1000000)) +#else +#define USB_CLK_HZ _u(48000000) +#endif +#endif + +// For backwards compatibility define XOSC_KHZ if the frequency is indeed an integer number of Khz. +#if defined(XOSC_HZ) && !defined(XOSC_KHZ) && (XOSC_HZ % 1000 == 0) +#define XOSC_KHZ (XOSC_HZ / 1000) +#endif + +// For backwards compatibility define XOSC_MHZ if the frequency is indeed an integer number of Mhz. +#if defined(XOSC_KHZ) && !defined(XOSC_MHZ) && (XOSC_KHZ % 1000 == 0) +#define XOSC_MHZ (XOSC_KHZ / 1000) +#endif + +// For backwards compatibility define SYS_CLK_KHZ if the frequency is indeed an integer number of Khz. +#if defined(SYS_CLK_HZ) && !defined(SYS_CLK_KHZ) && (SYS_CLK_HZ % 1000 == 0) +#define SYS_CLK_KHZ (SYS_CLK_HZ / 1000) +#endif + +// For backwards compatibility define SYS_CLK_MHZ if the frequency is indeed an integer number of Mhz. +#if defined(SYS_CLK_KHZ) && !defined(SYS_CLK_MHZ) && (SYS_CLK_KHZ % 1000 == 0) +#define SYS_CLK_MHZ (SYS_CLK_KHZ / 1000) +#endif + +// For backwards compatibility define USB_CLK_KHZ if the frequency is indeed an integer number of Khz. +#if defined(USB_CLK_HZ) && !defined(USB_CLK_KHZ) && (USB_CLK_HZ % 1000 == 0) +#define USB_CLK_KHZ (USB_CLK_HZ / 1000) +#endif + +// For backwards compatibility define USB_CLK_MHZ if the frequency is indeed an integer number of Mhz. +#if defined(USB_CLK_KHZ) && !defined(USB_CLK_MHZ) && (USB_CLK_KHZ % 1000 == 0) +#define USB_CLK_MHZ (USB_CLK_KHZ / 1000) +#endif + +#define FIRST_USER_IRQ (NUM_IRQS - NUM_USER_IRQS) +#define VTABLE_FIRST_IRQ 16 + +#endif diff --git a/lib/rp2040/hardware/regs/adc.h b/lib/pico-sdk/rp2040/hardware/regs/adc.h similarity index 98% rename from lib/rp2040/hardware/regs/adc.h rename to lib/pico-sdk/rp2040/hardware/regs/adc.h index 47510be51e0b..3077f1624c94 100644 --- a/lib/rp2040/hardware/regs/adc.h +++ b/lib/pico-sdk/rp2040/hardware/regs/adc.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : apb // Description : Control and data interface to SAR ADC // ============================================================================= -#ifndef HARDWARE_REGS_ADC_DEFINED -#define HARDWARE_REGS_ADC_DEFINED +#ifndef _HARDWARE_REGS_ADC_H +#define _HARDWARE_REGS_ADC_H // ============================================================================= // Register : ADC_CS // Description : ADC Control and Status @@ -25,8 +27,8 @@ // round-robin fashion. // The first channel to be sampled will be the one currently // indicated by AINSEL. -// AINSEL will be updated after each conversion with the -// newly-selected channel. +// AINSEL will be updated after each conversion with the newly- +// selected channel. #define ADC_CS_RROBIN_RESET _u(0x00) #define ADC_CS_RROBIN_BITS _u(0x001f0000) #define ADC_CS_RROBIN_MSB _u(20) @@ -153,7 +155,6 @@ #define ADC_FCS_UNDER_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : ADC_FCS_FULL -// Description : None #define ADC_FCS_FULL_RESET _u(0x0) #define ADC_FCS_FULL_BITS _u(0x00000200) #define ADC_FCS_FULL_MSB _u(9) @@ -161,7 +162,6 @@ #define ADC_FCS_FULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : ADC_FCS_EMPTY -// Description : None #define ADC_FCS_EMPTY_RESET _u(0x0) #define ADC_FCS_EMPTY_BITS _u(0x00000100) #define ADC_FCS_EMPTY_MSB _u(8) @@ -218,7 +218,6 @@ #define ADC_FIFO_ERR_ACCESS "RF" // ----------------------------------------------------------------------------- // Field : ADC_FIFO_VAL -// Description : None #define ADC_FIFO_VAL_RESET "-" #define ADC_FIFO_VAL_BITS _u(0x00000fff) #define ADC_FIFO_VAL_MSB _u(11) @@ -311,4 +310,5 @@ #define ADC_INTS_FIFO_LSB _u(0) #define ADC_INTS_FIFO_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_ADC_DEFINED +#endif // _HARDWARE_REGS_ADC_H + diff --git a/lib/rp2040/hardware/regs/addressmap.h b/lib/pico-sdk/rp2040/hardware/regs/addressmap.h similarity index 84% rename from lib/rp2040/hardware/regs/addressmap.h rename to lib/pico-sdk/rp2040/hardware/regs/addressmap.h index b39ab45fdcf4..61da68c5be40 100644 --- a/lib/rp2040/hardware/regs/addressmap.h +++ b/lib/pico-sdk/rp2040/hardware/regs/addressmap.h @@ -1,18 +1,24 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _ADDRESSMAP_H_ -#define _ADDRESSMAP_H_ +#ifndef _ADDRESSMAP_H +#define _ADDRESSMAP_H + +/** + * \file rp2040/addressmap.h + */ #include "hardware/platform_defs.h" // Register address offsets for atomic RMW aliases -#define REG_ALIAS_RW_BITS (0x0u << 12u) -#define REG_ALIAS_XOR_BITS (0x1u << 12u) -#define REG_ALIAS_SET_BITS (0x2u << 12u) -#define REG_ALIAS_CLR_BITS (0x3u << 12u) +#define REG_ALIAS_RW_BITS (_u(0x0) << _u(12)) +#define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12)) +#define REG_ALIAS_SET_BITS (_u(0x2) << _u(12)) +#define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12)) #define ROM_BASE _u(0x00000000) #define XIP_BASE _u(0x10000000) @@ -71,4 +77,5 @@ #define SIO_BASE _u(0xd0000000) #define PPB_BASE _u(0xe0000000) -#endif // _ADDRESSMAP_H_ +#endif // _ADDRESSMAP_H + diff --git a/lib/rp2040/hardware/regs/busctrl.h b/lib/pico-sdk/rp2040/hardware/regs/busctrl.h similarity index 64% rename from lib/rp2040/hardware/regs/busctrl.h rename to lib/pico-sdk/rp2040/hardware/regs/busctrl.h index 8be0d8666a85..ee5f153e24df 100644 --- a/lib/rp2040/hardware/regs/busctrl.h +++ b/lib/pico-sdk/rp2040/hardware/regs/busctrl.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,8 +12,8 @@ // Description : Register block for busfabric control signals and performance // counters // ============================================================================= -#ifndef HARDWARE_REGS_BUSCTRL_DEFINED -#define HARDWARE_REGS_BUSCTRL_DEFINED +#ifndef _HARDWARE_REGS_BUSCTRL_H +#define _HARDWARE_REGS_BUSCTRL_H // ============================================================================= // Register : BUSCTRL_BUS_PRIORITY // Description : Set the priority of each master for bus arbitration. @@ -102,32 +104,32 @@ // 0x11 -> xip_main // 0x12 -> rom_contested // 0x13 -> rom -#define BUSCTRL_PERFSEL0_OFFSET _u(0x0000000c) -#define BUSCTRL_PERFSEL0_BITS _u(0x0000001f) -#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL0_MSB _u(4) -#define BUSCTRL_PERFSEL0_LSB _u(0) -#define BUSCTRL_PERFSEL0_ACCESS "RW" -#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED _u(0x00) -#define BUSCTRL_PERFSEL0_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL0_OFFSET _u(0x0000000c) +#define BUSCTRL_PERFSEL0_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL0_MSB _u(4) +#define BUSCTRL_PERFSEL0_LSB _u(0) +#define BUSCTRL_PERFSEL0_ACCESS "RW" +#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL0_VALUE_APB _u(0x01) #define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL0_VALUE_FASTPERI _u(0x03) -#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED _u(0x04) -#define BUSCTRL_PERFSEL0_VALUE_SRAM5 _u(0x05) -#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL0_VALUE_SRAM4 _u(0x07) -#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED _u(0x08) -#define BUSCTRL_PERFSEL0_VALUE_SRAM3 _u(0x09) -#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL0_VALUE_SRAM2 _u(0x0b) -#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED _u(0x0c) -#define BUSCTRL_PERFSEL0_VALUE_SRAM1 _u(0x0d) -#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL0_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL0_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0 _u(0x0f) #define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED _u(0x10) -#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN _u(0x11) -#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL0_VALUE_ROM _u(0x13) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL0_VALUE_ROM _u(0x13) // ============================================================================= // Register : BUSCTRL_PERFCTR1 // Description : Bus fabric performance counter 1 @@ -166,32 +168,32 @@ // 0x11 -> xip_main // 0x12 -> rom_contested // 0x13 -> rom -#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000014) -#define BUSCTRL_PERFSEL1_BITS _u(0x0000001f) -#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL1_MSB _u(4) -#define BUSCTRL_PERFSEL1_LSB _u(0) -#define BUSCTRL_PERFSEL1_ACCESS "RW" -#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED _u(0x00) -#define BUSCTRL_PERFSEL1_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000014) +#define BUSCTRL_PERFSEL1_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL1_MSB _u(4) +#define BUSCTRL_PERFSEL1_LSB _u(0) +#define BUSCTRL_PERFSEL1_ACCESS "RW" +#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL1_VALUE_APB _u(0x01) #define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL1_VALUE_FASTPERI _u(0x03) -#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED _u(0x04) -#define BUSCTRL_PERFSEL1_VALUE_SRAM5 _u(0x05) -#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL1_VALUE_SRAM4 _u(0x07) -#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED _u(0x08) -#define BUSCTRL_PERFSEL1_VALUE_SRAM3 _u(0x09) -#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL1_VALUE_SRAM2 _u(0x0b) -#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED _u(0x0c) -#define BUSCTRL_PERFSEL1_VALUE_SRAM1 _u(0x0d) -#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL1_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL1_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0 _u(0x0f) #define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED _u(0x10) -#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN _u(0x11) -#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL1_VALUE_ROM _u(0x13) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL1_VALUE_ROM _u(0x13) // ============================================================================= // Register : BUSCTRL_PERFCTR2 // Description : Bus fabric performance counter 2 @@ -230,32 +232,32 @@ // 0x11 -> xip_main // 0x12 -> rom_contested // 0x13 -> rom -#define BUSCTRL_PERFSEL2_OFFSET _u(0x0000001c) -#define BUSCTRL_PERFSEL2_BITS _u(0x0000001f) -#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL2_MSB _u(4) -#define BUSCTRL_PERFSEL2_LSB _u(0) -#define BUSCTRL_PERFSEL2_ACCESS "RW" -#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED _u(0x00) -#define BUSCTRL_PERFSEL2_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL2_OFFSET _u(0x0000001c) +#define BUSCTRL_PERFSEL2_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL2_MSB _u(4) +#define BUSCTRL_PERFSEL2_LSB _u(0) +#define BUSCTRL_PERFSEL2_ACCESS "RW" +#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL2_VALUE_APB _u(0x01) #define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL2_VALUE_FASTPERI _u(0x03) -#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED _u(0x04) -#define BUSCTRL_PERFSEL2_VALUE_SRAM5 _u(0x05) -#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL2_VALUE_SRAM4 _u(0x07) -#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED _u(0x08) -#define BUSCTRL_PERFSEL2_VALUE_SRAM3 _u(0x09) -#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL2_VALUE_SRAM2 _u(0x0b) -#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED _u(0x0c) -#define BUSCTRL_PERFSEL2_VALUE_SRAM1 _u(0x0d) -#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL2_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL2_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0 _u(0x0f) #define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED _u(0x10) -#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN _u(0x11) -#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL2_VALUE_ROM _u(0x13) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL2_VALUE_ROM _u(0x13) // ============================================================================= // Register : BUSCTRL_PERFCTR3 // Description : Bus fabric performance counter 3 @@ -294,31 +296,32 @@ // 0x11 -> xip_main // 0x12 -> rom_contested // 0x13 -> rom -#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000024) -#define BUSCTRL_PERFSEL3_BITS _u(0x0000001f) -#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f) -#define BUSCTRL_PERFSEL3_MSB _u(4) -#define BUSCTRL_PERFSEL3_LSB _u(0) -#define BUSCTRL_PERFSEL3_ACCESS "RW" -#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED _u(0x00) -#define BUSCTRL_PERFSEL3_VALUE_APB _u(0x01) +#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000024) +#define BUSCTRL_PERFSEL3_BITS _u(0x0000001f) +#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL3_MSB _u(4) +#define BUSCTRL_PERFSEL3_LSB _u(0) +#define BUSCTRL_PERFSEL3_ACCESS "RW" +#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED _u(0x00) +#define BUSCTRL_PERFSEL3_VALUE_APB _u(0x01) #define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED _u(0x02) -#define BUSCTRL_PERFSEL3_VALUE_FASTPERI _u(0x03) -#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED _u(0x04) -#define BUSCTRL_PERFSEL3_VALUE_SRAM5 _u(0x05) -#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED _u(0x06) -#define BUSCTRL_PERFSEL3_VALUE_SRAM4 _u(0x07) -#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED _u(0x08) -#define BUSCTRL_PERFSEL3_VALUE_SRAM3 _u(0x09) -#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED _u(0x0a) -#define BUSCTRL_PERFSEL3_VALUE_SRAM2 _u(0x0b) -#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED _u(0x0c) -#define BUSCTRL_PERFSEL3_VALUE_SRAM1 _u(0x0d) -#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED _u(0x0e) -#define BUSCTRL_PERFSEL3_VALUE_SRAM0 _u(0x0f) +#define BUSCTRL_PERFSEL3_VALUE_FASTPERI _u(0x03) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED _u(0x04) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5 _u(0x05) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4 _u(0x07) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED _u(0x08) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3 _u(0x09) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2 _u(0x0b) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED _u(0x0c) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1 _u(0x0d) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0 _u(0x0f) #define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED _u(0x10) -#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN _u(0x11) -#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _u(0x12) -#define BUSCTRL_PERFSEL3_VALUE_ROM _u(0x13) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN _u(0x11) +#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL3_VALUE_ROM _u(0x13) // ============================================================================= -#endif // HARDWARE_REGS_BUSCTRL_DEFINED +#endif // _HARDWARE_REGS_BUSCTRL_H + diff --git a/lib/rp2040/hardware/regs/clocks.h b/lib/pico-sdk/rp2040/hardware/regs/clocks.h similarity index 90% rename from lib/rp2040/hardware/regs/clocks.h rename to lib/pico-sdk/rp2040/hardware/regs/clocks.h index c0d2eaba4dc1..7c604b9b6370 100644 --- a/lib/rp2040/hardware/regs/clocks.h +++ b/lib/pico-sdk/rp2040/hardware/regs/clocks.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : CLOCKS // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_CLOCKS_DEFINED -#define HARDWARE_REGS_CLOCKS_DEFINED +#ifndef _HARDWARE_REGS_CLOCKS_H +#define _HARDWARE_REGS_CLOCKS_H // ============================================================================= // Register : CLOCKS_CLK_GPOUT0_CTRL // Description : Clock control, can be changed on-the-fly (except for auxsrc) @@ -75,22 +76,22 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) #define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) -#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT0_DIV // Description : Clock divisor, can be changed on-the-fly @@ -190,22 +191,22 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) #define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) -#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT1_DIV // Description : Clock divisor, can be changed on-the-fly @@ -305,22 +306,22 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) #define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) -#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT2_DIV // Description : Clock divisor, can be changed on-the-fly @@ -420,22 +421,22 @@ // 0x8 -> clk_adc // 0x9 -> clk_rtc // 0xa -> clk_ref -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS _u(0x000001e0) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB _u(8) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) #define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) -#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa) // ============================================================================= // Register : CLOCKS_CLK_GPOUT3_DIV // Description : Clock divisor, can be changed on-the-fly @@ -483,29 +484,29 @@ // 0x0 -> clksrc_pll_usb // 0x1 -> clksrc_gpin0 // 0x2 -> clksrc_gpin1 -#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS _u(0x00000060) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB _u(6) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS _u(0x00000060) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB _u(6) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) -#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_REF_CTRL_SRC -// Description : Selects the clock source glitchlessly, can be changed -// on-the-fly +// Description : Selects the clock source glitchlessly, can be changed on-the- +// fly // 0x0 -> rosc_clksrc_ph // 0x1 -> clksrc_clk_ref_aux // 0x2 -> xosc_clksrc -#define CLOCKS_CLK_REF_CTRL_SRC_RESET "-" -#define CLOCKS_CLK_REF_CTRL_SRC_BITS _u(0x00000003) -#define CLOCKS_CLK_REF_CTRL_SRC_MSB _u(1) -#define CLOCKS_CLK_REF_CTRL_SRC_LSB _u(0) -#define CLOCKS_CLK_REF_CTRL_SRC_ACCESS "RW" -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH _u(0x0) +#define CLOCKS_CLK_REF_CTRL_SRC_RESET "-" +#define CLOCKS_CLK_REF_CTRL_SRC_BITS _u(0x00000003) +#define CLOCKS_CLK_REF_CTRL_SRC_MSB _u(1) +#define CLOCKS_CLK_REF_CTRL_SRC_LSB _u(0) +#define CLOCKS_CLK_REF_CTRL_SRC_ACCESS "RW" +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH _u(0x0) #define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX _u(0x1) -#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC _u(0x2) +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC _u(0x2) // ============================================================================= // Register : CLOCKS_CLK_REF_DIV // Description : Clock divisor, can be changed on-the-fly @@ -553,29 +554,29 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) #define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x1) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x2) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x2) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ----------------------------------------------------------------------------- // Field : CLOCKS_CLK_SYS_CTRL_SRC -// Description : Selects the clock source glitchlessly, can be changed -// on-the-fly +// Description : Selects the clock source glitchlessly, can be changed on-the- +// fly // 0x0 -> clk_ref // 0x1 -> clksrc_clk_sys_aux -#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x0) -#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _u(0x00000001) -#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _u(0) -#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _u(0) -#define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS "RW" -#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _u(0x00000001) +#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _u(0) +#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _u(0) +#define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS "RW" +#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF _u(0x0) #define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX _u(0x1) // ============================================================================= // Register : CLOCKS_CLK_SYS_DIV @@ -649,18 +650,18 @@ // 0x4 -> xosc_clksrc // 0x5 -> clksrc_gpin0 // 0x6 -> clksrc_gpin1 -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS "RW" -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0) #define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) #define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2) #define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x3) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x4) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x5) -#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x6) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x4) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x5) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x6) // ============================================================================= // Register : CLOCKS_CLK_PERI_SELECTED // Description : Indicates which SRC is currently selected by the glitchless mux @@ -725,17 +726,17 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) #define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) #define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ============================================================================= // Register : CLOCKS_CLK_USB_DIV // Description : Clock divisor, can be changed on-the-fly @@ -814,17 +815,17 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) #define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) #define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ============================================================================= // Register : CLOCKS_CLK_ADC_DIV // Description : Clock divisor, can be changed on-the-fly @@ -903,17 +904,17 @@ // 0x3 -> xosc_clksrc // 0x4 -> clksrc_gpin0 // 0x5 -> clksrc_gpin1 -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET _u(0x0) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS _u(0x000000e0) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB _u(7) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB _u(5) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_ACCESS "RW" #define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) #define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) #define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) -#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) // ============================================================================= // Register : CLOCKS_CLK_RTC_DIV // Description : Clock divisor, can be changed on-the-fly @@ -951,7 +952,6 @@ #define CLOCKS_CLK_RTC_SELECTED_ACCESS "RO" // ============================================================================= // Register : CLOCKS_CLK_SYS_RESUS_CTRL -// Description : None #define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET _u(0x00000078) #define CLOCKS_CLK_SYS_RESUS_CTRL_BITS _u(0x000111ff) #define CLOCKS_CLK_SYS_RESUS_CTRL_RESET _u(0x000000ff) @@ -991,7 +991,6 @@ #define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_ACCESS "RW" // ============================================================================= // Register : CLOCKS_CLK_SYS_RESUS_STATUS -// Description : None #define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET _u(0x0000007c) #define CLOCKS_CLK_SYS_RESUS_STATUS_BITS _u(0x00000001) #define CLOCKS_CLK_SYS_RESUS_STATUS_RESET _u(0x00000000) @@ -1073,26 +1072,26 @@ // 0x0b -> clk_usb // 0x0c -> clk_adc // 0x0d -> clk_rtc -#define CLOCKS_FC0_SRC_OFFSET _u(0x00000094) -#define CLOCKS_FC0_SRC_BITS _u(0x000000ff) -#define CLOCKS_FC0_SRC_RESET _u(0x00000000) -#define CLOCKS_FC0_SRC_MSB _u(7) -#define CLOCKS_FC0_SRC_LSB _u(0) -#define CLOCKS_FC0_SRC_ACCESS "RW" -#define CLOCKS_FC0_SRC_VALUE_NULL _u(0x00) +#define CLOCKS_FC0_SRC_OFFSET _u(0x00000094) +#define CLOCKS_FC0_SRC_BITS _u(0x000000ff) +#define CLOCKS_FC0_SRC_RESET _u(0x00000000) +#define CLOCKS_FC0_SRC_MSB _u(7) +#define CLOCKS_FC0_SRC_LSB _u(0) +#define CLOCKS_FC0_SRC_ACCESS "RW" +#define CLOCKS_FC0_SRC_VALUE_NULL _u(0x00) #define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY _u(0x01) #define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY _u(0x02) -#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC _u(0x03) -#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH _u(0x04) -#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC _u(0x05) -#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 _u(0x06) -#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 _u(0x07) -#define CLOCKS_FC0_SRC_VALUE_CLK_REF _u(0x08) -#define CLOCKS_FC0_SRC_VALUE_CLK_SYS _u(0x09) -#define CLOCKS_FC0_SRC_VALUE_CLK_PERI _u(0x0a) -#define CLOCKS_FC0_SRC_VALUE_CLK_USB _u(0x0b) -#define CLOCKS_FC0_SRC_VALUE_CLK_ADC _u(0x0c) -#define CLOCKS_FC0_SRC_VALUE_CLK_RTC _u(0x0d) +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC _u(0x03) +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH _u(0x04) +#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC _u(0x05) +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 _u(0x06) +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 _u(0x07) +#define CLOCKS_FC0_SRC_VALUE_CLK_REF _u(0x08) +#define CLOCKS_FC0_SRC_VALUE_CLK_SYS _u(0x09) +#define CLOCKS_FC0_SRC_VALUE_CLK_PERI _u(0x0a) +#define CLOCKS_FC0_SRC_VALUE_CLK_USB _u(0x0b) +#define CLOCKS_FC0_SRC_VALUE_CLK_ADC _u(0x0c) +#define CLOCKS_FC0_SRC_VALUE_CLK_RTC _u(0x0d) // ============================================================================= // Register : CLOCKS_FC0_STATUS // Description : Frequency counter status @@ -1171,7 +1170,6 @@ #define CLOCKS_FC0_RESULT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_RESULT_KHZ -// Description : None #define CLOCKS_FC0_RESULT_KHZ_RESET _u(0x0000000) #define CLOCKS_FC0_RESULT_KHZ_BITS _u(0x3fffffe0) #define CLOCKS_FC0_RESULT_KHZ_MSB _u(29) @@ -1179,7 +1177,6 @@ #define CLOCKS_FC0_RESULT_KHZ_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_FC0_RESULT_FRAC -// Description : None #define CLOCKS_FC0_RESULT_FRAC_RESET _u(0x00) #define CLOCKS_FC0_RESULT_FRAC_BITS _u(0x0000001f) #define CLOCKS_FC0_RESULT_FRAC_MSB _u(4) @@ -1193,7 +1190,6 @@ #define CLOCKS_WAKE_EN0_RESET _u(0xffffffff) // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM3 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS _u(0x80000000) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_MSB _u(31) @@ -1201,7 +1197,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM2 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS _u(0x40000000) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_MSB _u(30) @@ -1209,7 +1204,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM1 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS _u(0x20000000) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_MSB _u(29) @@ -1217,7 +1211,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM0 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS _u(0x10000000) #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_MSB _u(28) @@ -1225,7 +1218,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI1 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS _u(0x08000000) #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_MSB _u(27) @@ -1233,7 +1225,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI1 -// Description : None #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS _u(0x04000000) #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_MSB _u(26) @@ -1241,7 +1232,6 @@ #define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI0 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS _u(0x02000000) #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_MSB _u(25) @@ -1249,7 +1239,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI0 -// Description : None #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS _u(0x01000000) #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_MSB _u(24) @@ -1257,7 +1246,6 @@ #define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_SIO -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS _u(0x00800000) #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB _u(23) @@ -1265,7 +1253,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_RTC -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_BITS _u(0x00400000) #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_MSB _u(22) @@ -1273,7 +1260,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_RTC_RTC -// Description : None #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_BITS _u(0x00200000) #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_MSB _u(21) @@ -1281,7 +1267,6 @@ #define CLOCKS_WAKE_EN0_CLK_RTC_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_ROSC -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS _u(0x00100000) #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB _u(20) @@ -1289,7 +1274,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_ROM -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS _u(0x00080000) #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB _u(19) @@ -1297,7 +1281,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_RESETS -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS _u(0x00040000) #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB _u(18) @@ -1305,7 +1288,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PWM -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS _u(0x00020000) #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB _u(17) @@ -1313,7 +1295,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PSM -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS _u(0x00010000) #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB _u(16) @@ -1321,7 +1302,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_PSM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS _u(0x00008000) #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB _u(15) @@ -1329,7 +1309,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB _u(14) @@ -1337,7 +1316,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO1 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS _u(0x00002000) #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB _u(13) @@ -1345,7 +1323,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO0 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS _u(0x00001000) #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB _u(12) @@ -1353,7 +1330,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_PADS -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS _u(0x00000800) #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB _u(11) @@ -1361,7 +1337,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_PADS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) @@ -1369,7 +1344,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_JTAG -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS _u(0x00000200) #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB _u(9) @@ -1377,7 +1351,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_IO -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS _u(0x00000100) #define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB _u(8) @@ -1385,7 +1358,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_IO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C1 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS _u(0x00000080) #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB _u(7) @@ -1393,7 +1365,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C0 -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS _u(0x00000040) #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB _u(6) @@ -1401,7 +1372,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_DMA -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS _u(0x00000020) #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB _u(5) @@ -1409,7 +1379,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB _u(4) @@ -1417,7 +1386,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB _u(3) @@ -1425,7 +1393,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_ADC -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS _u(0x00000004) #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB _u(2) @@ -1433,7 +1400,6 @@ #define CLOCKS_WAKE_EN0_CLK_SYS_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_ADC_ADC -// Description : None #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_BITS _u(0x00000002) #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_MSB _u(1) @@ -1441,7 +1407,6 @@ #define CLOCKS_WAKE_EN0_CLK_ADC_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS -// Description : None #define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) #define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) #define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB _u(0) @@ -1455,7 +1420,6 @@ #define CLOCKS_WAKE_EN1_RESET _u(0x00007fff) // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_XOSC -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS _u(0x00004000) #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB _u(14) @@ -1463,7 +1427,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_XIP -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS _u(0x00002000) #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB _u(13) @@ -1471,7 +1434,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB _u(12) @@ -1479,7 +1441,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_USB_USBCTRL -// Description : None #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_BITS _u(0x00000800) #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_MSB _u(11) @@ -1487,7 +1448,6 @@ #define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS _u(0x00000400) #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB _u(10) @@ -1495,7 +1455,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_UART1 -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS _u(0x00000200) #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB _u(9) @@ -1503,7 +1462,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_PERI_UART1 -// Description : None #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS _u(0x00000100) #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB _u(8) @@ -1511,7 +1469,6 @@ #define CLOCKS_WAKE_EN1_CLK_PERI_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_UART0 -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS _u(0x00000080) #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB _u(7) @@ -1519,7 +1476,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_PERI_UART0 -// Description : None #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS _u(0x00000040) #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB _u(6) @@ -1527,7 +1483,6 @@ #define CLOCKS_WAKE_EN1_CLK_PERI_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS _u(0x00000020) #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_MSB _u(5) @@ -1535,7 +1490,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_TBMAN -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS _u(0x00000010) #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB _u(4) @@ -1543,7 +1497,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS _u(0x00000008) #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB _u(3) @@ -1551,7 +1504,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS _u(0x00000004) #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB _u(2) @@ -1559,7 +1511,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM5 -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS _u(0x00000002) #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB _u(1) @@ -1567,7 +1518,6 @@ #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM4 -// Description : None #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET _u(0x1) #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS _u(0x00000001) #define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB _u(0) @@ -1581,7 +1531,6 @@ #define CLOCKS_SLEEP_EN0_RESET _u(0xffffffff) // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_BITS _u(0x80000000) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_MSB _u(31) @@ -1589,7 +1538,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_BITS _u(0x40000000) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_MSB _u(30) @@ -1597,7 +1545,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_BITS _u(0x20000000) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_MSB _u(29) @@ -1605,7 +1552,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_BITS _u(0x10000000) #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_MSB _u(28) @@ -1613,7 +1559,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI1 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS _u(0x08000000) #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_MSB _u(27) @@ -1621,7 +1566,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI1 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS _u(0x04000000) #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_MSB _u(26) @@ -1629,7 +1573,6 @@ #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI0 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS _u(0x02000000) #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_MSB _u(25) @@ -1637,7 +1580,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI0 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS _u(0x01000000) #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_MSB _u(24) @@ -1645,7 +1587,6 @@ #define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_SIO -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS _u(0x00800000) #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB _u(23) @@ -1653,7 +1594,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_RTC -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_BITS _u(0x00400000) #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_MSB _u(22) @@ -1661,7 +1601,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_RTC_RTC -// Description : None #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS _u(0x00200000) #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_MSB _u(21) @@ -1669,7 +1608,6 @@ #define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROSC -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS _u(0x00100000) #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB _u(20) @@ -1677,7 +1615,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROM -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS _u(0x00080000) #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB _u(19) @@ -1685,7 +1622,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_RESETS -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS _u(0x00040000) #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB _u(18) @@ -1693,7 +1629,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PWM -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS _u(0x00020000) #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB _u(17) @@ -1701,7 +1636,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PSM -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS _u(0x00010000) #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB _u(16) @@ -1709,7 +1643,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS _u(0x00008000) #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB _u(15) @@ -1717,7 +1650,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB _u(14) @@ -1725,7 +1657,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO1 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS _u(0x00002000) #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB _u(13) @@ -1733,7 +1664,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO0 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS _u(0x00001000) #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB _u(12) @@ -1741,7 +1671,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_PADS -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS _u(0x00000800) #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB _u(11) @@ -1749,7 +1678,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) @@ -1757,7 +1685,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_JTAG -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS _u(0x00000200) #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB _u(9) @@ -1765,7 +1692,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_IO -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS _u(0x00000100) #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB _u(8) @@ -1773,7 +1699,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_IO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C1 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS _u(0x00000080) #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB _u(7) @@ -1781,7 +1706,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C0 -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS _u(0x00000040) #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB _u(6) @@ -1789,7 +1713,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_DMA -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS _u(0x00000020) #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB _u(5) @@ -1797,7 +1720,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB _u(4) @@ -1805,7 +1727,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB _u(3) @@ -1813,7 +1734,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_ADC -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS _u(0x00000004) #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB _u(2) @@ -1821,7 +1741,6 @@ #define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_ADC_ADC -// Description : None #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_BITS _u(0x00000002) #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_MSB _u(1) @@ -1829,7 +1748,6 @@ #define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS -// Description : None #define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) #define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) #define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB _u(0) @@ -1843,7 +1761,6 @@ #define CLOCKS_SLEEP_EN1_RESET _u(0x00007fff) // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_XOSC -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS _u(0x00004000) #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB _u(14) @@ -1851,7 +1768,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_XIP -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS _u(0x00002000) #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB _u(13) @@ -1859,7 +1775,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB _u(12) @@ -1867,7 +1782,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL -// Description : None #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_BITS _u(0x00000800) #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_MSB _u(11) @@ -1875,7 +1789,6 @@ #define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS _u(0x00000400) #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB _u(10) @@ -1883,7 +1796,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART1 -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS _u(0x00000200) #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB _u(9) @@ -1891,7 +1803,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART1 -// Description : None #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS _u(0x00000100) #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB _u(8) @@ -1899,7 +1810,6 @@ #define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART0 -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS _u(0x00000080) #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB _u(7) @@ -1907,7 +1817,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART0 -// Description : None #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS _u(0x00000040) #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB _u(6) @@ -1915,7 +1824,6 @@ #define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS _u(0x00000020) #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_MSB _u(5) @@ -1923,7 +1831,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS _u(0x00000010) #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB _u(4) @@ -1931,7 +1838,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS _u(0x00000008) #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB _u(3) @@ -1939,7 +1845,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS _u(0x00000004) #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB _u(2) @@ -1947,7 +1852,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5 -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS _u(0x00000002) #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB _u(1) @@ -1955,7 +1859,6 @@ #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4 -// Description : None #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET _u(0x1) #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS _u(0x00000001) #define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB _u(0) @@ -1969,7 +1872,6 @@ #define CLOCKS_ENABLED0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM3 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_BITS _u(0x80000000) #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_MSB _u(31) @@ -1977,7 +1879,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_SRAM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM2 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_BITS _u(0x40000000) #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_MSB _u(30) @@ -1985,7 +1886,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_SRAM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM1 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_BITS _u(0x20000000) #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_MSB _u(29) @@ -1993,7 +1893,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_SRAM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SRAM0 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_BITS _u(0x10000000) #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_MSB _u(28) @@ -2001,7 +1900,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_SRAM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SPI1 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_SPI1_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_SPI1_BITS _u(0x08000000) #define CLOCKS_ENABLED0_CLK_SYS_SPI1_MSB _u(27) @@ -2009,7 +1907,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_SPI1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_PERI_SPI1 -// Description : None #define CLOCKS_ENABLED0_CLK_PERI_SPI1_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_PERI_SPI1_BITS _u(0x04000000) #define CLOCKS_ENABLED0_CLK_PERI_SPI1_MSB _u(26) @@ -2017,7 +1914,6 @@ #define CLOCKS_ENABLED0_CLK_PERI_SPI1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SPI0 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_SPI0_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_SPI0_BITS _u(0x02000000) #define CLOCKS_ENABLED0_CLK_SYS_SPI0_MSB _u(25) @@ -2025,7 +1921,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_SPI0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_PERI_SPI0 -// Description : None #define CLOCKS_ENABLED0_CLK_PERI_SPI0_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_PERI_SPI0_BITS _u(0x01000000) #define CLOCKS_ENABLED0_CLK_PERI_SPI0_MSB _u(24) @@ -2033,7 +1928,6 @@ #define CLOCKS_ENABLED0_CLK_PERI_SPI0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_SIO -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS _u(0x00800000) #define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB _u(23) @@ -2041,7 +1935,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_SIO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_RTC -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_RTC_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_RTC_BITS _u(0x00400000) #define CLOCKS_ENABLED0_CLK_SYS_RTC_MSB _u(22) @@ -2049,7 +1942,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_RTC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_RTC_RTC -// Description : None #define CLOCKS_ENABLED0_CLK_RTC_RTC_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_RTC_RTC_BITS _u(0x00200000) #define CLOCKS_ENABLED0_CLK_RTC_RTC_MSB _u(21) @@ -2057,7 +1949,6 @@ #define CLOCKS_ENABLED0_CLK_RTC_RTC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_ROSC -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS _u(0x00100000) #define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB _u(20) @@ -2065,7 +1956,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_ROSC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_ROM -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS _u(0x00080000) #define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB _u(19) @@ -2073,7 +1963,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_ROM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_RESETS -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS _u(0x00040000) #define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB _u(18) @@ -2081,7 +1970,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_RESETS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PWM -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS _u(0x00020000) #define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB _u(17) @@ -2089,7 +1977,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_PWM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PSM -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS _u(0x00010000) #define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB _u(16) @@ -2097,7 +1984,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_PSM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PLL_USB -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS _u(0x00008000) #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB _u(15) @@ -2105,7 +1991,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PLL_SYS -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS _u(0x00004000) #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB _u(14) @@ -2113,7 +1998,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PIO1 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS _u(0x00002000) #define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB _u(13) @@ -2121,7 +2005,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_PIO1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PIO0 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS _u(0x00001000) #define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB _u(12) @@ -2129,7 +2012,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_PIO0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_PADS -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS _u(0x00000800) #define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB _u(11) @@ -2137,7 +2019,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_PADS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400) #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10) @@ -2145,7 +2026,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_JTAG -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS _u(0x00000200) #define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB _u(9) @@ -2153,7 +2033,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_JTAG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_IO -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_IO_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_IO_BITS _u(0x00000100) #define CLOCKS_ENABLED0_CLK_SYS_IO_MSB _u(8) @@ -2161,7 +2040,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_IO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_I2C1 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS _u(0x00000080) #define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB _u(7) @@ -2169,7 +2047,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_I2C1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_I2C0 -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS _u(0x00000040) #define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB _u(6) @@ -2177,7 +2054,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_I2C0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_DMA -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS _u(0x00000020) #define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB _u(5) @@ -2185,7 +2061,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_DMA_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010) #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB _u(4) @@ -2193,7 +2068,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_BUSCTRL -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS _u(0x00000008) #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB _u(3) @@ -2201,7 +2075,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_ADC -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS _u(0x00000004) #define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB _u(2) @@ -2209,7 +2082,6 @@ #define CLOCKS_ENABLED0_CLK_SYS_ADC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_ADC_ADC -// Description : None #define CLOCKS_ENABLED0_CLK_ADC_ADC_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_ADC_ADC_BITS _u(0x00000002) #define CLOCKS_ENABLED0_CLK_ADC_ADC_MSB _u(1) @@ -2217,7 +2089,6 @@ #define CLOCKS_ENABLED0_CLK_ADC_ADC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED0_CLK_SYS_CLOCKS -// Description : None #define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET _u(0x0) #define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS _u(0x00000001) #define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB _u(0) @@ -2231,7 +2102,6 @@ #define CLOCKS_ENABLED1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_XOSC -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS _u(0x00004000) #define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB _u(14) @@ -2239,7 +2109,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_XOSC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_XIP -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS _u(0x00002000) #define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB _u(13) @@ -2247,7 +2116,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_XIP_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_WATCHDOG -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS _u(0x00001000) #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB _u(12) @@ -2255,7 +2123,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_USB_USBCTRL -// Description : None #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_BITS _u(0x00000800) #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_MSB _u(11) @@ -2263,7 +2130,6 @@ #define CLOCKS_ENABLED1_CLK_USB_USBCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_USBCTRL -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS _u(0x00000400) #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB _u(10) @@ -2271,7 +2137,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_UART1 -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS _u(0x00000200) #define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB _u(9) @@ -2279,7 +2144,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_UART1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_PERI_UART1 -// Description : None #define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS _u(0x00000100) #define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB _u(8) @@ -2287,7 +2151,6 @@ #define CLOCKS_ENABLED1_CLK_PERI_UART1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_UART0 -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS _u(0x00000080) #define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB _u(7) @@ -2295,7 +2158,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_UART0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_PERI_UART0 -// Description : None #define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS _u(0x00000040) #define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB _u(6) @@ -2303,7 +2165,6 @@ #define CLOCKS_ENABLED1_CLK_PERI_UART0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_TIMER -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_TIMER_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_TIMER_BITS _u(0x00000020) #define CLOCKS_ENABLED1_CLK_SYS_TIMER_MSB _u(5) @@ -2311,7 +2172,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_TIMER_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_TBMAN -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS _u(0x00000010) #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB _u(4) @@ -2319,7 +2179,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_TBMAN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SYSINFO -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS _u(0x00000008) #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB _u(3) @@ -2327,7 +2186,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SYSCFG -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS _u(0x00000004) #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB _u(2) @@ -2335,7 +2193,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SRAM5 -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS _u(0x00000002) #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB _u(1) @@ -2343,7 +2200,6 @@ #define CLOCKS_ENABLED1_CLK_SYS_SRAM5_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : CLOCKS_ENABLED1_CLK_SYS_SRAM4 -// Description : None #define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET _u(0x0) #define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS _u(0x00000001) #define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB _u(0) @@ -2357,7 +2213,6 @@ #define CLOCKS_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTR_CLK_SYS_RESUS -// Description : None #define CLOCKS_INTR_CLK_SYS_RESUS_RESET _u(0x0) #define CLOCKS_INTR_CLK_SYS_RESUS_BITS _u(0x00000001) #define CLOCKS_INTR_CLK_SYS_RESUS_MSB _u(0) @@ -2371,7 +2226,6 @@ #define CLOCKS_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTE_CLK_SYS_RESUS -// Description : None #define CLOCKS_INTE_CLK_SYS_RESUS_RESET _u(0x0) #define CLOCKS_INTE_CLK_SYS_RESUS_BITS _u(0x00000001) #define CLOCKS_INTE_CLK_SYS_RESUS_MSB _u(0) @@ -2385,7 +2239,6 @@ #define CLOCKS_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTF_CLK_SYS_RESUS -// Description : None #define CLOCKS_INTF_CLK_SYS_RESUS_RESET _u(0x0) #define CLOCKS_INTF_CLK_SYS_RESUS_BITS _u(0x00000001) #define CLOCKS_INTF_CLK_SYS_RESUS_MSB _u(0) @@ -2399,11 +2252,11 @@ #define CLOCKS_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : CLOCKS_INTS_CLK_SYS_RESUS -// Description : None #define CLOCKS_INTS_CLK_SYS_RESUS_RESET _u(0x0) #define CLOCKS_INTS_CLK_SYS_RESUS_BITS _u(0x00000001) #define CLOCKS_INTS_CLK_SYS_RESUS_MSB _u(0) #define CLOCKS_INTS_CLK_SYS_RESUS_LSB _u(0) #define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_CLOCKS_DEFINED +#endif // _HARDWARE_REGS_CLOCKS_H + diff --git a/lib/rp2040/hardware/regs/dma.h b/lib/pico-sdk/rp2040/hardware/regs/dma.h similarity index 90% rename from lib/rp2040/hardware/regs/dma.h rename to lib/pico-sdk/rp2040/hardware/regs/dma.h index 49938ba92b98..62a37ec096de 100644 --- a/lib/rp2040/hardware/regs/dma.h +++ b/lib/pico-sdk/rp2040/hardware/regs/dma.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : apb // Description : DMA with separate read and write masters // ============================================================================= -#ifndef HARDWARE_REGS_DMA_DEFINED -#define HARDWARE_REGS_DMA_DEFINED +#ifndef _HARDWARE_REGS_DMA_H +#define _HARDWARE_REGS_DMA_H // ============================================================================= // Register : DMA_CH0_READ_ADDR // Description : DMA Channel 0 Read Address pointer @@ -84,7 +86,7 @@ // Description : If 1, the channel received a read bus error. Write one to // clear. // READ_ADDR shows the approximate address where the bus error was -// encountered (will not to be earlier, or more than 3 transfers +// encountered (will not be earlier, or more than 3 transfers // later) #define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _u(0x0) #define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) @@ -96,8 +98,8 @@ // Description : If 1, the channel received a write bus error. Write one to // clear. // WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not to be earlier, or more than 5 -// transfers later) +// was encountered (will not be earlier, or more than 5 transfers +// later) #define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) #define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) #define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _u(29) @@ -124,8 +126,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -168,22 +170,21 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. -// Reset value is equal to channel number (0). #define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) #define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _u(14) @@ -210,11 +211,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_INCR_WRITE @@ -248,14 +249,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -294,7 +295,7 @@ #define DMA_CH0_AL1_CTRL_RESET "-" #define DMA_CH0_AL1_CTRL_MSB _u(31) #define DMA_CH0_AL1_CTRL_LSB _u(0) -#define DMA_CH0_AL1_CTRL_ACCESS "RO" +#define DMA_CH0_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL1_READ_ADDR // Description : Alias for channel 0 READ_ADDR register @@ -303,7 +304,7 @@ #define DMA_CH0_AL1_READ_ADDR_RESET "-" #define DMA_CH0_AL1_READ_ADDR_MSB _u(31) #define DMA_CH0_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH0_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH0_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL1_WRITE_ADDR // Description : Alias for channel 0 WRITE_ADDR register @@ -312,7 +313,7 @@ #define DMA_CH0_AL1_WRITE_ADDR_RESET "-" #define DMA_CH0_AL1_WRITE_ADDR_MSB _u(31) #define DMA_CH0_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 0 TRANS_COUNT register @@ -323,7 +324,7 @@ #define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-" #define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB _u(31) #define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL2_CTRL // Description : Alias for channel 0 CTRL register @@ -332,7 +333,7 @@ #define DMA_CH0_AL2_CTRL_RESET "-" #define DMA_CH0_AL2_CTRL_MSB _u(31) #define DMA_CH0_AL2_CTRL_LSB _u(0) -#define DMA_CH0_AL2_CTRL_ACCESS "RO" +#define DMA_CH0_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL2_TRANS_COUNT // Description : Alias for channel 0 TRANS_COUNT register @@ -341,7 +342,7 @@ #define DMA_CH0_AL2_TRANS_COUNT_RESET "-" #define DMA_CH0_AL2_TRANS_COUNT_MSB _u(31) #define DMA_CH0_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL2_READ_ADDR // Description : Alias for channel 0 READ_ADDR register @@ -350,7 +351,7 @@ #define DMA_CH0_AL2_READ_ADDR_RESET "-" #define DMA_CH0_AL2_READ_ADDR_MSB _u(31) #define DMA_CH0_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH0_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH0_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 0 WRITE_ADDR register @@ -361,7 +362,7 @@ #define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-" #define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB _u(31) #define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL3_CTRL // Description : Alias for channel 0 CTRL register @@ -370,7 +371,7 @@ #define DMA_CH0_AL3_CTRL_RESET "-" #define DMA_CH0_AL3_CTRL_MSB _u(31) #define DMA_CH0_AL3_CTRL_LSB _u(0) -#define DMA_CH0_AL3_CTRL_ACCESS "RO" +#define DMA_CH0_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL3_WRITE_ADDR // Description : Alias for channel 0 WRITE_ADDR register @@ -379,7 +380,7 @@ #define DMA_CH0_AL3_WRITE_ADDR_RESET "-" #define DMA_CH0_AL3_WRITE_ADDR_MSB _u(31) #define DMA_CH0_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL3_TRANS_COUNT // Description : Alias for channel 0 TRANS_COUNT register @@ -388,7 +389,7 @@ #define DMA_CH0_AL3_TRANS_COUNT_RESET "-" #define DMA_CH0_AL3_TRANS_COUNT_MSB _u(31) #define DMA_CH0_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH0_AL3_READ_ADDR_TRIG // Description : Alias for channel 0 READ_ADDR register @@ -399,7 +400,7 @@ #define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-" #define DMA_CH0_AL3_READ_ADDR_TRIG_MSB _u(31) #define DMA_CH0_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_READ_ADDR // Description : DMA Channel 1 Read Address pointer @@ -457,7 +458,7 @@ // Description : DMA Channel 1 Control and Status #define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c) #define DMA_CH1_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH1_CTRL_TRIG_RESET _u(0x00000800) +#define DMA_CH1_CTRL_TRIG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel @@ -473,7 +474,7 @@ // Description : If 1, the channel received a read bus error. Write one to // clear. // READ_ADDR shows the approximate address where the bus error was -// encountered (will not to be earlier, or more than 3 transfers +// encountered (will not be earlier, or more than 3 transfers // later) #define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _u(0x0) #define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) @@ -485,8 +486,8 @@ // Description : If 1, the channel received a write bus error. Write one to // clear. // WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not to be earlier, or more than 5 -// transfers later) +// was encountered (will not be earlier, or more than 5 transfers +// later) #define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) #define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) #define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _u(29) @@ -513,8 +514,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -557,23 +558,22 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. -// Reset value is equal to channel number (1). -#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x1) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) #define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _u(11) @@ -599,11 +599,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_INCR_WRITE @@ -637,14 +637,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -683,7 +683,7 @@ #define DMA_CH1_AL1_CTRL_RESET "-" #define DMA_CH1_AL1_CTRL_MSB _u(31) #define DMA_CH1_AL1_CTRL_LSB _u(0) -#define DMA_CH1_AL1_CTRL_ACCESS "RO" +#define DMA_CH1_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL1_READ_ADDR // Description : Alias for channel 1 READ_ADDR register @@ -692,7 +692,7 @@ #define DMA_CH1_AL1_READ_ADDR_RESET "-" #define DMA_CH1_AL1_READ_ADDR_MSB _u(31) #define DMA_CH1_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH1_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH1_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL1_WRITE_ADDR // Description : Alias for channel 1 WRITE_ADDR register @@ -701,7 +701,7 @@ #define DMA_CH1_AL1_WRITE_ADDR_RESET "-" #define DMA_CH1_AL1_WRITE_ADDR_MSB _u(31) #define DMA_CH1_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 1 TRANS_COUNT register @@ -712,7 +712,7 @@ #define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-" #define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB _u(31) #define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL2_CTRL // Description : Alias for channel 1 CTRL register @@ -721,7 +721,7 @@ #define DMA_CH1_AL2_CTRL_RESET "-" #define DMA_CH1_AL2_CTRL_MSB _u(31) #define DMA_CH1_AL2_CTRL_LSB _u(0) -#define DMA_CH1_AL2_CTRL_ACCESS "RO" +#define DMA_CH1_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL2_TRANS_COUNT // Description : Alias for channel 1 TRANS_COUNT register @@ -730,7 +730,7 @@ #define DMA_CH1_AL2_TRANS_COUNT_RESET "-" #define DMA_CH1_AL2_TRANS_COUNT_MSB _u(31) #define DMA_CH1_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL2_READ_ADDR // Description : Alias for channel 1 READ_ADDR register @@ -739,7 +739,7 @@ #define DMA_CH1_AL2_READ_ADDR_RESET "-" #define DMA_CH1_AL2_READ_ADDR_MSB _u(31) #define DMA_CH1_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH1_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH1_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 1 WRITE_ADDR register @@ -750,7 +750,7 @@ #define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-" #define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB _u(31) #define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL3_CTRL // Description : Alias for channel 1 CTRL register @@ -759,7 +759,7 @@ #define DMA_CH1_AL3_CTRL_RESET "-" #define DMA_CH1_AL3_CTRL_MSB _u(31) #define DMA_CH1_AL3_CTRL_LSB _u(0) -#define DMA_CH1_AL3_CTRL_ACCESS "RO" +#define DMA_CH1_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL3_WRITE_ADDR // Description : Alias for channel 1 WRITE_ADDR register @@ -768,7 +768,7 @@ #define DMA_CH1_AL3_WRITE_ADDR_RESET "-" #define DMA_CH1_AL3_WRITE_ADDR_MSB _u(31) #define DMA_CH1_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL3_TRANS_COUNT // Description : Alias for channel 1 TRANS_COUNT register @@ -777,7 +777,7 @@ #define DMA_CH1_AL3_TRANS_COUNT_RESET "-" #define DMA_CH1_AL3_TRANS_COUNT_MSB _u(31) #define DMA_CH1_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH1_AL3_READ_ADDR_TRIG // Description : Alias for channel 1 READ_ADDR register @@ -788,7 +788,7 @@ #define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-" #define DMA_CH1_AL3_READ_ADDR_TRIG_MSB _u(31) #define DMA_CH1_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_READ_ADDR // Description : DMA Channel 2 Read Address pointer @@ -846,7 +846,7 @@ // Description : DMA Channel 2 Control and Status #define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c) #define DMA_CH2_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH2_CTRL_TRIG_RESET _u(0x00001000) +#define DMA_CH2_CTRL_TRIG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel @@ -862,7 +862,7 @@ // Description : If 1, the channel received a read bus error. Write one to // clear. // READ_ADDR shows the approximate address where the bus error was -// encountered (will not to be earlier, or more than 3 transfers +// encountered (will not be earlier, or more than 3 transfers // later) #define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _u(0x0) #define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) @@ -874,8 +874,8 @@ // Description : If 1, the channel received a write bus error. Write one to // clear. // WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not to be earlier, or more than 5 -// transfers later) +// was encountered (will not be earlier, or more than 5 transfers +// later) #define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) #define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) #define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _u(29) @@ -902,8 +902,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -946,23 +946,22 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. -// Reset value is equal to channel number (2). -#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x2) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) #define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _u(11) @@ -988,11 +987,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_INCR_WRITE @@ -1026,14 +1025,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -1072,7 +1071,7 @@ #define DMA_CH2_AL1_CTRL_RESET "-" #define DMA_CH2_AL1_CTRL_MSB _u(31) #define DMA_CH2_AL1_CTRL_LSB _u(0) -#define DMA_CH2_AL1_CTRL_ACCESS "RO" +#define DMA_CH2_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL1_READ_ADDR // Description : Alias for channel 2 READ_ADDR register @@ -1081,7 +1080,7 @@ #define DMA_CH2_AL1_READ_ADDR_RESET "-" #define DMA_CH2_AL1_READ_ADDR_MSB _u(31) #define DMA_CH2_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH2_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH2_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL1_WRITE_ADDR // Description : Alias for channel 2 WRITE_ADDR register @@ -1090,7 +1089,7 @@ #define DMA_CH2_AL1_WRITE_ADDR_RESET "-" #define DMA_CH2_AL1_WRITE_ADDR_MSB _u(31) #define DMA_CH2_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 2 TRANS_COUNT register @@ -1101,7 +1100,7 @@ #define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-" #define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB _u(31) #define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL2_CTRL // Description : Alias for channel 2 CTRL register @@ -1110,7 +1109,7 @@ #define DMA_CH2_AL2_CTRL_RESET "-" #define DMA_CH2_AL2_CTRL_MSB _u(31) #define DMA_CH2_AL2_CTRL_LSB _u(0) -#define DMA_CH2_AL2_CTRL_ACCESS "RO" +#define DMA_CH2_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL2_TRANS_COUNT // Description : Alias for channel 2 TRANS_COUNT register @@ -1119,7 +1118,7 @@ #define DMA_CH2_AL2_TRANS_COUNT_RESET "-" #define DMA_CH2_AL2_TRANS_COUNT_MSB _u(31) #define DMA_CH2_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL2_READ_ADDR // Description : Alias for channel 2 READ_ADDR register @@ -1128,7 +1127,7 @@ #define DMA_CH2_AL2_READ_ADDR_RESET "-" #define DMA_CH2_AL2_READ_ADDR_MSB _u(31) #define DMA_CH2_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH2_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH2_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 2 WRITE_ADDR register @@ -1139,7 +1138,7 @@ #define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-" #define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB _u(31) #define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL3_CTRL // Description : Alias for channel 2 CTRL register @@ -1148,7 +1147,7 @@ #define DMA_CH2_AL3_CTRL_RESET "-" #define DMA_CH2_AL3_CTRL_MSB _u(31) #define DMA_CH2_AL3_CTRL_LSB _u(0) -#define DMA_CH2_AL3_CTRL_ACCESS "RO" +#define DMA_CH2_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL3_WRITE_ADDR // Description : Alias for channel 2 WRITE_ADDR register @@ -1157,7 +1156,7 @@ #define DMA_CH2_AL3_WRITE_ADDR_RESET "-" #define DMA_CH2_AL3_WRITE_ADDR_MSB _u(31) #define DMA_CH2_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL3_TRANS_COUNT // Description : Alias for channel 2 TRANS_COUNT register @@ -1166,7 +1165,7 @@ #define DMA_CH2_AL3_TRANS_COUNT_RESET "-" #define DMA_CH2_AL3_TRANS_COUNT_MSB _u(31) #define DMA_CH2_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH2_AL3_READ_ADDR_TRIG // Description : Alias for channel 2 READ_ADDR register @@ -1177,7 +1176,7 @@ #define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-" #define DMA_CH2_AL3_READ_ADDR_TRIG_MSB _u(31) #define DMA_CH2_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_READ_ADDR // Description : DMA Channel 3 Read Address pointer @@ -1235,7 +1234,7 @@ // Description : DMA Channel 3 Control and Status #define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc) #define DMA_CH3_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH3_CTRL_TRIG_RESET _u(0x00001800) +#define DMA_CH3_CTRL_TRIG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel @@ -1251,7 +1250,7 @@ // Description : If 1, the channel received a read bus error. Write one to // clear. // READ_ADDR shows the approximate address where the bus error was -// encountered (will not to be earlier, or more than 3 transfers +// encountered (will not be earlier, or more than 3 transfers // later) #define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _u(0x0) #define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) @@ -1263,8 +1262,8 @@ // Description : If 1, the channel received a write bus error. Write one to // clear. // WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not to be earlier, or more than 5 -// transfers later) +// was encountered (will not be earlier, or more than 5 transfers +// later) #define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) #define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) #define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _u(29) @@ -1291,8 +1290,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -1335,23 +1334,22 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. -// Reset value is equal to channel number (3). -#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x3) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) #define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _u(11) @@ -1377,11 +1375,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_INCR_WRITE @@ -1415,14 +1413,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -1461,7 +1459,7 @@ #define DMA_CH3_AL1_CTRL_RESET "-" #define DMA_CH3_AL1_CTRL_MSB _u(31) #define DMA_CH3_AL1_CTRL_LSB _u(0) -#define DMA_CH3_AL1_CTRL_ACCESS "RO" +#define DMA_CH3_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL1_READ_ADDR // Description : Alias for channel 3 READ_ADDR register @@ -1470,7 +1468,7 @@ #define DMA_CH3_AL1_READ_ADDR_RESET "-" #define DMA_CH3_AL1_READ_ADDR_MSB _u(31) #define DMA_CH3_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH3_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH3_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL1_WRITE_ADDR // Description : Alias for channel 3 WRITE_ADDR register @@ -1479,7 +1477,7 @@ #define DMA_CH3_AL1_WRITE_ADDR_RESET "-" #define DMA_CH3_AL1_WRITE_ADDR_MSB _u(31) #define DMA_CH3_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 3 TRANS_COUNT register @@ -1490,7 +1488,7 @@ #define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-" #define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB _u(31) #define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL2_CTRL // Description : Alias for channel 3 CTRL register @@ -1499,7 +1497,7 @@ #define DMA_CH3_AL2_CTRL_RESET "-" #define DMA_CH3_AL2_CTRL_MSB _u(31) #define DMA_CH3_AL2_CTRL_LSB _u(0) -#define DMA_CH3_AL2_CTRL_ACCESS "RO" +#define DMA_CH3_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL2_TRANS_COUNT // Description : Alias for channel 3 TRANS_COUNT register @@ -1508,7 +1506,7 @@ #define DMA_CH3_AL2_TRANS_COUNT_RESET "-" #define DMA_CH3_AL2_TRANS_COUNT_MSB _u(31) #define DMA_CH3_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL2_READ_ADDR // Description : Alias for channel 3 READ_ADDR register @@ -1517,7 +1515,7 @@ #define DMA_CH3_AL2_READ_ADDR_RESET "-" #define DMA_CH3_AL2_READ_ADDR_MSB _u(31) #define DMA_CH3_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH3_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH3_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 3 WRITE_ADDR register @@ -1528,7 +1526,7 @@ #define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-" #define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB _u(31) #define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL3_CTRL // Description : Alias for channel 3 CTRL register @@ -1537,7 +1535,7 @@ #define DMA_CH3_AL3_CTRL_RESET "-" #define DMA_CH3_AL3_CTRL_MSB _u(31) #define DMA_CH3_AL3_CTRL_LSB _u(0) -#define DMA_CH3_AL3_CTRL_ACCESS "RO" +#define DMA_CH3_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL3_WRITE_ADDR // Description : Alias for channel 3 WRITE_ADDR register @@ -1546,7 +1544,7 @@ #define DMA_CH3_AL3_WRITE_ADDR_RESET "-" #define DMA_CH3_AL3_WRITE_ADDR_MSB _u(31) #define DMA_CH3_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL3_TRANS_COUNT // Description : Alias for channel 3 TRANS_COUNT register @@ -1555,7 +1553,7 @@ #define DMA_CH3_AL3_TRANS_COUNT_RESET "-" #define DMA_CH3_AL3_TRANS_COUNT_MSB _u(31) #define DMA_CH3_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH3_AL3_READ_ADDR_TRIG // Description : Alias for channel 3 READ_ADDR register @@ -1566,7 +1564,7 @@ #define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-" #define DMA_CH3_AL3_READ_ADDR_TRIG_MSB _u(31) #define DMA_CH3_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_READ_ADDR // Description : DMA Channel 4 Read Address pointer @@ -1624,7 +1622,7 @@ // Description : DMA Channel 4 Control and Status #define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c) #define DMA_CH4_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH4_CTRL_TRIG_RESET _u(0x00002000) +#define DMA_CH4_CTRL_TRIG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel @@ -1640,7 +1638,7 @@ // Description : If 1, the channel received a read bus error. Write one to // clear. // READ_ADDR shows the approximate address where the bus error was -// encountered (will not to be earlier, or more than 3 transfers +// encountered (will not be earlier, or more than 3 transfers // later) #define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _u(0x0) #define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) @@ -1652,8 +1650,8 @@ // Description : If 1, the channel received a write bus error. Write one to // clear. // WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not to be earlier, or more than 5 -// transfers later) +// was encountered (will not be earlier, or more than 5 transfers +// later) #define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) #define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) #define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _u(29) @@ -1680,8 +1678,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -1724,23 +1722,22 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. -// Reset value is equal to channel number (4). -#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x4) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) #define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _u(11) @@ -1766,11 +1763,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_INCR_WRITE @@ -1804,14 +1801,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -1850,7 +1847,7 @@ #define DMA_CH4_AL1_CTRL_RESET "-" #define DMA_CH4_AL1_CTRL_MSB _u(31) #define DMA_CH4_AL1_CTRL_LSB _u(0) -#define DMA_CH4_AL1_CTRL_ACCESS "RO" +#define DMA_CH4_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL1_READ_ADDR // Description : Alias for channel 4 READ_ADDR register @@ -1859,7 +1856,7 @@ #define DMA_CH4_AL1_READ_ADDR_RESET "-" #define DMA_CH4_AL1_READ_ADDR_MSB _u(31) #define DMA_CH4_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH4_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH4_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL1_WRITE_ADDR // Description : Alias for channel 4 WRITE_ADDR register @@ -1868,7 +1865,7 @@ #define DMA_CH4_AL1_WRITE_ADDR_RESET "-" #define DMA_CH4_AL1_WRITE_ADDR_MSB _u(31) #define DMA_CH4_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 4 TRANS_COUNT register @@ -1879,7 +1876,7 @@ #define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-" #define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB _u(31) #define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL2_CTRL // Description : Alias for channel 4 CTRL register @@ -1888,7 +1885,7 @@ #define DMA_CH4_AL2_CTRL_RESET "-" #define DMA_CH4_AL2_CTRL_MSB _u(31) #define DMA_CH4_AL2_CTRL_LSB _u(0) -#define DMA_CH4_AL2_CTRL_ACCESS "RO" +#define DMA_CH4_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL2_TRANS_COUNT // Description : Alias for channel 4 TRANS_COUNT register @@ -1897,7 +1894,7 @@ #define DMA_CH4_AL2_TRANS_COUNT_RESET "-" #define DMA_CH4_AL2_TRANS_COUNT_MSB _u(31) #define DMA_CH4_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL2_READ_ADDR // Description : Alias for channel 4 READ_ADDR register @@ -1906,7 +1903,7 @@ #define DMA_CH4_AL2_READ_ADDR_RESET "-" #define DMA_CH4_AL2_READ_ADDR_MSB _u(31) #define DMA_CH4_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH4_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH4_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 4 WRITE_ADDR register @@ -1917,7 +1914,7 @@ #define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-" #define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB _u(31) #define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL3_CTRL // Description : Alias for channel 4 CTRL register @@ -1926,7 +1923,7 @@ #define DMA_CH4_AL3_CTRL_RESET "-" #define DMA_CH4_AL3_CTRL_MSB _u(31) #define DMA_CH4_AL3_CTRL_LSB _u(0) -#define DMA_CH4_AL3_CTRL_ACCESS "RO" +#define DMA_CH4_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL3_WRITE_ADDR // Description : Alias for channel 4 WRITE_ADDR register @@ -1935,7 +1932,7 @@ #define DMA_CH4_AL3_WRITE_ADDR_RESET "-" #define DMA_CH4_AL3_WRITE_ADDR_MSB _u(31) #define DMA_CH4_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL3_TRANS_COUNT // Description : Alias for channel 4 TRANS_COUNT register @@ -1944,7 +1941,7 @@ #define DMA_CH4_AL3_TRANS_COUNT_RESET "-" #define DMA_CH4_AL3_TRANS_COUNT_MSB _u(31) #define DMA_CH4_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH4_AL3_READ_ADDR_TRIG // Description : Alias for channel 4 READ_ADDR register @@ -1955,7 +1952,7 @@ #define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-" #define DMA_CH4_AL3_READ_ADDR_TRIG_MSB _u(31) #define DMA_CH4_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_READ_ADDR // Description : DMA Channel 5 Read Address pointer @@ -2013,7 +2010,7 @@ // Description : DMA Channel 5 Control and Status #define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c) #define DMA_CH5_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH5_CTRL_TRIG_RESET _u(0x00002800) +#define DMA_CH5_CTRL_TRIG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel @@ -2029,7 +2026,7 @@ // Description : If 1, the channel received a read bus error. Write one to // clear. // READ_ADDR shows the approximate address where the bus error was -// encountered (will not to be earlier, or more than 3 transfers +// encountered (will not be earlier, or more than 3 transfers // later) #define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _u(0x0) #define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) @@ -2041,8 +2038,8 @@ // Description : If 1, the channel received a write bus error. Write one to // clear. // WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not to be earlier, or more than 5 -// transfers later) +// was encountered (will not be earlier, or more than 5 transfers +// later) #define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) #define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) #define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _u(29) @@ -2069,8 +2066,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -2113,23 +2110,22 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. -// Reset value is equal to channel number (5). -#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x5) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) #define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _u(11) @@ -2155,11 +2151,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_INCR_WRITE @@ -2193,14 +2189,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -2239,7 +2235,7 @@ #define DMA_CH5_AL1_CTRL_RESET "-" #define DMA_CH5_AL1_CTRL_MSB _u(31) #define DMA_CH5_AL1_CTRL_LSB _u(0) -#define DMA_CH5_AL1_CTRL_ACCESS "RO" +#define DMA_CH5_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL1_READ_ADDR // Description : Alias for channel 5 READ_ADDR register @@ -2248,7 +2244,7 @@ #define DMA_CH5_AL1_READ_ADDR_RESET "-" #define DMA_CH5_AL1_READ_ADDR_MSB _u(31) #define DMA_CH5_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH5_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH5_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL1_WRITE_ADDR // Description : Alias for channel 5 WRITE_ADDR register @@ -2257,7 +2253,7 @@ #define DMA_CH5_AL1_WRITE_ADDR_RESET "-" #define DMA_CH5_AL1_WRITE_ADDR_MSB _u(31) #define DMA_CH5_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 5 TRANS_COUNT register @@ -2268,7 +2264,7 @@ #define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-" #define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB _u(31) #define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL2_CTRL // Description : Alias for channel 5 CTRL register @@ -2277,7 +2273,7 @@ #define DMA_CH5_AL2_CTRL_RESET "-" #define DMA_CH5_AL2_CTRL_MSB _u(31) #define DMA_CH5_AL2_CTRL_LSB _u(0) -#define DMA_CH5_AL2_CTRL_ACCESS "RO" +#define DMA_CH5_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL2_TRANS_COUNT // Description : Alias for channel 5 TRANS_COUNT register @@ -2286,7 +2282,7 @@ #define DMA_CH5_AL2_TRANS_COUNT_RESET "-" #define DMA_CH5_AL2_TRANS_COUNT_MSB _u(31) #define DMA_CH5_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL2_READ_ADDR // Description : Alias for channel 5 READ_ADDR register @@ -2295,7 +2291,7 @@ #define DMA_CH5_AL2_READ_ADDR_RESET "-" #define DMA_CH5_AL2_READ_ADDR_MSB _u(31) #define DMA_CH5_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH5_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH5_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 5 WRITE_ADDR register @@ -2306,7 +2302,7 @@ #define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-" #define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB _u(31) #define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL3_CTRL // Description : Alias for channel 5 CTRL register @@ -2315,7 +2311,7 @@ #define DMA_CH5_AL3_CTRL_RESET "-" #define DMA_CH5_AL3_CTRL_MSB _u(31) #define DMA_CH5_AL3_CTRL_LSB _u(0) -#define DMA_CH5_AL3_CTRL_ACCESS "RO" +#define DMA_CH5_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL3_WRITE_ADDR // Description : Alias for channel 5 WRITE_ADDR register @@ -2324,7 +2320,7 @@ #define DMA_CH5_AL3_WRITE_ADDR_RESET "-" #define DMA_CH5_AL3_WRITE_ADDR_MSB _u(31) #define DMA_CH5_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL3_TRANS_COUNT // Description : Alias for channel 5 TRANS_COUNT register @@ -2333,7 +2329,7 @@ #define DMA_CH5_AL3_TRANS_COUNT_RESET "-" #define DMA_CH5_AL3_TRANS_COUNT_MSB _u(31) #define DMA_CH5_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH5_AL3_READ_ADDR_TRIG // Description : Alias for channel 5 READ_ADDR register @@ -2344,7 +2340,7 @@ #define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-" #define DMA_CH5_AL3_READ_ADDR_TRIG_MSB _u(31) #define DMA_CH5_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_READ_ADDR // Description : DMA Channel 6 Read Address pointer @@ -2402,7 +2398,7 @@ // Description : DMA Channel 6 Control and Status #define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c) #define DMA_CH6_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH6_CTRL_TRIG_RESET _u(0x00003000) +#define DMA_CH6_CTRL_TRIG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel @@ -2418,7 +2414,7 @@ // Description : If 1, the channel received a read bus error. Write one to // clear. // READ_ADDR shows the approximate address where the bus error was -// encountered (will not to be earlier, or more than 3 transfers +// encountered (will not be earlier, or more than 3 transfers // later) #define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _u(0x0) #define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) @@ -2430,8 +2426,8 @@ // Description : If 1, the channel received a write bus error. Write one to // clear. // WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not to be earlier, or more than 5 -// transfers later) +// was encountered (will not be earlier, or more than 5 transfers +// later) #define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) #define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) #define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _u(29) @@ -2458,8 +2454,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -2502,23 +2498,22 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. -// Reset value is equal to channel number (6). -#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x6) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) #define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _u(11) @@ -2544,11 +2539,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_INCR_WRITE @@ -2582,14 +2577,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -2628,7 +2623,7 @@ #define DMA_CH6_AL1_CTRL_RESET "-" #define DMA_CH6_AL1_CTRL_MSB _u(31) #define DMA_CH6_AL1_CTRL_LSB _u(0) -#define DMA_CH6_AL1_CTRL_ACCESS "RO" +#define DMA_CH6_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL1_READ_ADDR // Description : Alias for channel 6 READ_ADDR register @@ -2637,7 +2632,7 @@ #define DMA_CH6_AL1_READ_ADDR_RESET "-" #define DMA_CH6_AL1_READ_ADDR_MSB _u(31) #define DMA_CH6_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH6_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH6_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL1_WRITE_ADDR // Description : Alias for channel 6 WRITE_ADDR register @@ -2646,7 +2641,7 @@ #define DMA_CH6_AL1_WRITE_ADDR_RESET "-" #define DMA_CH6_AL1_WRITE_ADDR_MSB _u(31) #define DMA_CH6_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 6 TRANS_COUNT register @@ -2657,7 +2652,7 @@ #define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-" #define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB _u(31) #define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL2_CTRL // Description : Alias for channel 6 CTRL register @@ -2666,7 +2661,7 @@ #define DMA_CH6_AL2_CTRL_RESET "-" #define DMA_CH6_AL2_CTRL_MSB _u(31) #define DMA_CH6_AL2_CTRL_LSB _u(0) -#define DMA_CH6_AL2_CTRL_ACCESS "RO" +#define DMA_CH6_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL2_TRANS_COUNT // Description : Alias for channel 6 TRANS_COUNT register @@ -2675,7 +2670,7 @@ #define DMA_CH6_AL2_TRANS_COUNT_RESET "-" #define DMA_CH6_AL2_TRANS_COUNT_MSB _u(31) #define DMA_CH6_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL2_READ_ADDR // Description : Alias for channel 6 READ_ADDR register @@ -2684,7 +2679,7 @@ #define DMA_CH6_AL2_READ_ADDR_RESET "-" #define DMA_CH6_AL2_READ_ADDR_MSB _u(31) #define DMA_CH6_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH6_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH6_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 6 WRITE_ADDR register @@ -2695,7 +2690,7 @@ #define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-" #define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB _u(31) #define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL3_CTRL // Description : Alias for channel 6 CTRL register @@ -2704,7 +2699,7 @@ #define DMA_CH6_AL3_CTRL_RESET "-" #define DMA_CH6_AL3_CTRL_MSB _u(31) #define DMA_CH6_AL3_CTRL_LSB _u(0) -#define DMA_CH6_AL3_CTRL_ACCESS "RO" +#define DMA_CH6_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL3_WRITE_ADDR // Description : Alias for channel 6 WRITE_ADDR register @@ -2713,7 +2708,7 @@ #define DMA_CH6_AL3_WRITE_ADDR_RESET "-" #define DMA_CH6_AL3_WRITE_ADDR_MSB _u(31) #define DMA_CH6_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL3_TRANS_COUNT // Description : Alias for channel 6 TRANS_COUNT register @@ -2722,7 +2717,7 @@ #define DMA_CH6_AL3_TRANS_COUNT_RESET "-" #define DMA_CH6_AL3_TRANS_COUNT_MSB _u(31) #define DMA_CH6_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH6_AL3_READ_ADDR_TRIG // Description : Alias for channel 6 READ_ADDR register @@ -2733,7 +2728,7 @@ #define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-" #define DMA_CH6_AL3_READ_ADDR_TRIG_MSB _u(31) #define DMA_CH6_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_READ_ADDR // Description : DMA Channel 7 Read Address pointer @@ -2791,7 +2786,7 @@ // Description : DMA Channel 7 Control and Status #define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc) #define DMA_CH7_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH7_CTRL_TRIG_RESET _u(0x00003800) +#define DMA_CH7_CTRL_TRIG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel @@ -2807,7 +2802,7 @@ // Description : If 1, the channel received a read bus error. Write one to // clear. // READ_ADDR shows the approximate address where the bus error was -// encountered (will not to be earlier, or more than 3 transfers +// encountered (will not be earlier, or more than 3 transfers // later) #define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _u(0x0) #define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) @@ -2819,8 +2814,8 @@ // Description : If 1, the channel received a write bus error. Write one to // clear. // WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not to be earlier, or more than 5 -// transfers later) +// was encountered (will not be earlier, or more than 5 transfers +// later) #define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) #define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) #define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _u(29) @@ -2847,8 +2842,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -2891,23 +2886,22 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. -// Reset value is equal to channel number (7). -#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x7) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) #define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _u(11) @@ -2933,11 +2927,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_INCR_WRITE @@ -2971,14 +2965,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH7_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -3017,7 +3011,7 @@ #define DMA_CH7_AL1_CTRL_RESET "-" #define DMA_CH7_AL1_CTRL_MSB _u(31) #define DMA_CH7_AL1_CTRL_LSB _u(0) -#define DMA_CH7_AL1_CTRL_ACCESS "RO" +#define DMA_CH7_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL1_READ_ADDR // Description : Alias for channel 7 READ_ADDR register @@ -3026,7 +3020,7 @@ #define DMA_CH7_AL1_READ_ADDR_RESET "-" #define DMA_CH7_AL1_READ_ADDR_MSB _u(31) #define DMA_CH7_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH7_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH7_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL1_WRITE_ADDR // Description : Alias for channel 7 WRITE_ADDR register @@ -3035,7 +3029,7 @@ #define DMA_CH7_AL1_WRITE_ADDR_RESET "-" #define DMA_CH7_AL1_WRITE_ADDR_MSB _u(31) #define DMA_CH7_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 7 TRANS_COUNT register @@ -3046,7 +3040,7 @@ #define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-" #define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB _u(31) #define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL2_CTRL // Description : Alias for channel 7 CTRL register @@ -3055,7 +3049,7 @@ #define DMA_CH7_AL2_CTRL_RESET "-" #define DMA_CH7_AL2_CTRL_MSB _u(31) #define DMA_CH7_AL2_CTRL_LSB _u(0) -#define DMA_CH7_AL2_CTRL_ACCESS "RO" +#define DMA_CH7_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL2_TRANS_COUNT // Description : Alias for channel 7 TRANS_COUNT register @@ -3064,7 +3058,7 @@ #define DMA_CH7_AL2_TRANS_COUNT_RESET "-" #define DMA_CH7_AL2_TRANS_COUNT_MSB _u(31) #define DMA_CH7_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL2_READ_ADDR // Description : Alias for channel 7 READ_ADDR register @@ -3073,7 +3067,7 @@ #define DMA_CH7_AL2_READ_ADDR_RESET "-" #define DMA_CH7_AL2_READ_ADDR_MSB _u(31) #define DMA_CH7_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH7_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH7_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 7 WRITE_ADDR register @@ -3084,7 +3078,7 @@ #define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-" #define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB _u(31) #define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL3_CTRL // Description : Alias for channel 7 CTRL register @@ -3093,7 +3087,7 @@ #define DMA_CH7_AL3_CTRL_RESET "-" #define DMA_CH7_AL3_CTRL_MSB _u(31) #define DMA_CH7_AL3_CTRL_LSB _u(0) -#define DMA_CH7_AL3_CTRL_ACCESS "RO" +#define DMA_CH7_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL3_WRITE_ADDR // Description : Alias for channel 7 WRITE_ADDR register @@ -3102,7 +3096,7 @@ #define DMA_CH7_AL3_WRITE_ADDR_RESET "-" #define DMA_CH7_AL3_WRITE_ADDR_MSB _u(31) #define DMA_CH7_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL3_TRANS_COUNT // Description : Alias for channel 7 TRANS_COUNT register @@ -3111,7 +3105,7 @@ #define DMA_CH7_AL3_TRANS_COUNT_RESET "-" #define DMA_CH7_AL3_TRANS_COUNT_MSB _u(31) #define DMA_CH7_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH7_AL3_READ_ADDR_TRIG // Description : Alias for channel 7 READ_ADDR register @@ -3122,7 +3116,7 @@ #define DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-" #define DMA_CH7_AL3_READ_ADDR_TRIG_MSB _u(31) #define DMA_CH7_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_READ_ADDR // Description : DMA Channel 8 Read Address pointer @@ -3180,7 +3174,7 @@ // Description : DMA Channel 8 Control and Status #define DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c) #define DMA_CH8_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH8_CTRL_TRIG_RESET _u(0x00004000) +#define DMA_CH8_CTRL_TRIG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel @@ -3196,7 +3190,7 @@ // Description : If 1, the channel received a read bus error. Write one to // clear. // READ_ADDR shows the approximate address where the bus error was -// encountered (will not to be earlier, or more than 3 transfers +// encountered (will not be earlier, or more than 3 transfers // later) #define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET _u(0x0) #define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) @@ -3208,8 +3202,8 @@ // Description : If 1, the channel received a write bus error. Write one to // clear. // WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not to be earlier, or more than 5 -// transfers later) +// was encountered (will not be earlier, or more than 5 transfers +// later) #define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) #define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) #define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB _u(29) @@ -3236,8 +3230,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -3280,23 +3274,22 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. -// Reset value is equal to channel number (8). -#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _u(0x8) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) #define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB _u(11) @@ -3322,11 +3315,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_INCR_WRITE @@ -3360,14 +3353,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH8_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -3406,7 +3399,7 @@ #define DMA_CH8_AL1_CTRL_RESET "-" #define DMA_CH8_AL1_CTRL_MSB _u(31) #define DMA_CH8_AL1_CTRL_LSB _u(0) -#define DMA_CH8_AL1_CTRL_ACCESS "RO" +#define DMA_CH8_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL1_READ_ADDR // Description : Alias for channel 8 READ_ADDR register @@ -3415,7 +3408,7 @@ #define DMA_CH8_AL1_READ_ADDR_RESET "-" #define DMA_CH8_AL1_READ_ADDR_MSB _u(31) #define DMA_CH8_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH8_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH8_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL1_WRITE_ADDR // Description : Alias for channel 8 WRITE_ADDR register @@ -3424,7 +3417,7 @@ #define DMA_CH8_AL1_WRITE_ADDR_RESET "-" #define DMA_CH8_AL1_WRITE_ADDR_MSB _u(31) #define DMA_CH8_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 8 TRANS_COUNT register @@ -3435,7 +3428,7 @@ #define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-" #define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB _u(31) #define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL2_CTRL // Description : Alias for channel 8 CTRL register @@ -3444,7 +3437,7 @@ #define DMA_CH8_AL2_CTRL_RESET "-" #define DMA_CH8_AL2_CTRL_MSB _u(31) #define DMA_CH8_AL2_CTRL_LSB _u(0) -#define DMA_CH8_AL2_CTRL_ACCESS "RO" +#define DMA_CH8_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL2_TRANS_COUNT // Description : Alias for channel 8 TRANS_COUNT register @@ -3453,7 +3446,7 @@ #define DMA_CH8_AL2_TRANS_COUNT_RESET "-" #define DMA_CH8_AL2_TRANS_COUNT_MSB _u(31) #define DMA_CH8_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL2_READ_ADDR // Description : Alias for channel 8 READ_ADDR register @@ -3462,7 +3455,7 @@ #define DMA_CH8_AL2_READ_ADDR_RESET "-" #define DMA_CH8_AL2_READ_ADDR_MSB _u(31) #define DMA_CH8_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH8_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH8_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 8 WRITE_ADDR register @@ -3473,7 +3466,7 @@ #define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-" #define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB _u(31) #define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL3_CTRL // Description : Alias for channel 8 CTRL register @@ -3482,7 +3475,7 @@ #define DMA_CH8_AL3_CTRL_RESET "-" #define DMA_CH8_AL3_CTRL_MSB _u(31) #define DMA_CH8_AL3_CTRL_LSB _u(0) -#define DMA_CH8_AL3_CTRL_ACCESS "RO" +#define DMA_CH8_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL3_WRITE_ADDR // Description : Alias for channel 8 WRITE_ADDR register @@ -3491,7 +3484,7 @@ #define DMA_CH8_AL3_WRITE_ADDR_RESET "-" #define DMA_CH8_AL3_WRITE_ADDR_MSB _u(31) #define DMA_CH8_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL3_TRANS_COUNT // Description : Alias for channel 8 TRANS_COUNT register @@ -3500,7 +3493,7 @@ #define DMA_CH8_AL3_TRANS_COUNT_RESET "-" #define DMA_CH8_AL3_TRANS_COUNT_MSB _u(31) #define DMA_CH8_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH8_AL3_READ_ADDR_TRIG // Description : Alias for channel 8 READ_ADDR register @@ -3511,7 +3504,7 @@ #define DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-" #define DMA_CH8_AL3_READ_ADDR_TRIG_MSB _u(31) #define DMA_CH8_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_READ_ADDR // Description : DMA Channel 9 Read Address pointer @@ -3569,7 +3562,7 @@ // Description : DMA Channel 9 Control and Status #define DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c) #define DMA_CH9_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH9_CTRL_TRIG_RESET _u(0x00004800) +#define DMA_CH9_CTRL_TRIG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel @@ -3585,7 +3578,7 @@ // Description : If 1, the channel received a read bus error. Write one to // clear. // READ_ADDR shows the approximate address where the bus error was -// encountered (will not to be earlier, or more than 3 transfers +// encountered (will not be earlier, or more than 3 transfers // later) #define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET _u(0x0) #define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) @@ -3597,8 +3590,8 @@ // Description : If 1, the channel received a write bus error. Write one to // clear. // WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not to be earlier, or more than 5 -// transfers later) +// was encountered (will not be earlier, or more than 5 transfers +// later) #define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) #define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) #define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB _u(29) @@ -3625,8 +3618,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -3669,23 +3662,22 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. -// Reset value is equal to channel number (9). -#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _u(0x9) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) #define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB _u(11) @@ -3711,11 +3703,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_INCR_WRITE @@ -3749,14 +3741,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH9_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -3795,7 +3787,7 @@ #define DMA_CH9_AL1_CTRL_RESET "-" #define DMA_CH9_AL1_CTRL_MSB _u(31) #define DMA_CH9_AL1_CTRL_LSB _u(0) -#define DMA_CH9_AL1_CTRL_ACCESS "RO" +#define DMA_CH9_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL1_READ_ADDR // Description : Alias for channel 9 READ_ADDR register @@ -3804,7 +3796,7 @@ #define DMA_CH9_AL1_READ_ADDR_RESET "-" #define DMA_CH9_AL1_READ_ADDR_MSB _u(31) #define DMA_CH9_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH9_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH9_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL1_WRITE_ADDR // Description : Alias for channel 9 WRITE_ADDR register @@ -3813,7 +3805,7 @@ #define DMA_CH9_AL1_WRITE_ADDR_RESET "-" #define DMA_CH9_AL1_WRITE_ADDR_MSB _u(31) #define DMA_CH9_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 9 TRANS_COUNT register @@ -3824,7 +3816,7 @@ #define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-" #define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB _u(31) #define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL2_CTRL // Description : Alias for channel 9 CTRL register @@ -3833,7 +3825,7 @@ #define DMA_CH9_AL2_CTRL_RESET "-" #define DMA_CH9_AL2_CTRL_MSB _u(31) #define DMA_CH9_AL2_CTRL_LSB _u(0) -#define DMA_CH9_AL2_CTRL_ACCESS "RO" +#define DMA_CH9_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL2_TRANS_COUNT // Description : Alias for channel 9 TRANS_COUNT register @@ -3842,7 +3834,7 @@ #define DMA_CH9_AL2_TRANS_COUNT_RESET "-" #define DMA_CH9_AL2_TRANS_COUNT_MSB _u(31) #define DMA_CH9_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL2_READ_ADDR // Description : Alias for channel 9 READ_ADDR register @@ -3851,7 +3843,7 @@ #define DMA_CH9_AL2_READ_ADDR_RESET "-" #define DMA_CH9_AL2_READ_ADDR_MSB _u(31) #define DMA_CH9_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH9_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH9_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 9 WRITE_ADDR register @@ -3862,7 +3854,7 @@ #define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-" #define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB _u(31) #define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL3_CTRL // Description : Alias for channel 9 CTRL register @@ -3871,7 +3863,7 @@ #define DMA_CH9_AL3_CTRL_RESET "-" #define DMA_CH9_AL3_CTRL_MSB _u(31) #define DMA_CH9_AL3_CTRL_LSB _u(0) -#define DMA_CH9_AL3_CTRL_ACCESS "RO" +#define DMA_CH9_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL3_WRITE_ADDR // Description : Alias for channel 9 WRITE_ADDR register @@ -3880,7 +3872,7 @@ #define DMA_CH9_AL3_WRITE_ADDR_RESET "-" #define DMA_CH9_AL3_WRITE_ADDR_MSB _u(31) #define DMA_CH9_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL3_TRANS_COUNT // Description : Alias for channel 9 TRANS_COUNT register @@ -3889,7 +3881,7 @@ #define DMA_CH9_AL3_TRANS_COUNT_RESET "-" #define DMA_CH9_AL3_TRANS_COUNT_MSB _u(31) #define DMA_CH9_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH9_AL3_READ_ADDR_TRIG // Description : Alias for channel 9 READ_ADDR register @@ -3900,7 +3892,7 @@ #define DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-" #define DMA_CH9_AL3_READ_ADDR_TRIG_MSB _u(31) #define DMA_CH9_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_READ_ADDR // Description : DMA Channel 10 Read Address pointer @@ -3958,7 +3950,7 @@ // Description : DMA Channel 10 Control and Status #define DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c) #define DMA_CH10_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH10_CTRL_TRIG_RESET _u(0x00005000) +#define DMA_CH10_CTRL_TRIG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel @@ -3974,7 +3966,7 @@ // Description : If 1, the channel received a read bus error. Write one to // clear. // READ_ADDR shows the approximate address where the bus error was -// encountered (will not to be earlier, or more than 3 transfers +// encountered (will not be earlier, or more than 3 transfers // later) #define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET _u(0x0) #define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) @@ -3986,8 +3978,8 @@ // Description : If 1, the channel received a write bus error. Write one to // clear. // WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not to be earlier, or more than 5 -// transfers later) +// was encountered (will not be earlier, or more than 5 transfers +// later) #define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) #define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) #define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB _u(29) @@ -4014,8 +4006,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -4058,23 +4050,22 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. -// Reset value is equal to channel number (10). -#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _u(0xa) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) #define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB _u(11) @@ -4100,11 +4091,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_INCR_WRITE @@ -4138,14 +4129,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH10_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -4184,7 +4175,7 @@ #define DMA_CH10_AL1_CTRL_RESET "-" #define DMA_CH10_AL1_CTRL_MSB _u(31) #define DMA_CH10_AL1_CTRL_LSB _u(0) -#define DMA_CH10_AL1_CTRL_ACCESS "RO" +#define DMA_CH10_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL1_READ_ADDR // Description : Alias for channel 10 READ_ADDR register @@ -4193,7 +4184,7 @@ #define DMA_CH10_AL1_READ_ADDR_RESET "-" #define DMA_CH10_AL1_READ_ADDR_MSB _u(31) #define DMA_CH10_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH10_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH10_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL1_WRITE_ADDR // Description : Alias for channel 10 WRITE_ADDR register @@ -4202,7 +4193,7 @@ #define DMA_CH10_AL1_WRITE_ADDR_RESET "-" #define DMA_CH10_AL1_WRITE_ADDR_MSB _u(31) #define DMA_CH10_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 10 TRANS_COUNT register @@ -4213,7 +4204,7 @@ #define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-" #define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB _u(31) #define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL2_CTRL // Description : Alias for channel 10 CTRL register @@ -4222,7 +4213,7 @@ #define DMA_CH10_AL2_CTRL_RESET "-" #define DMA_CH10_AL2_CTRL_MSB _u(31) #define DMA_CH10_AL2_CTRL_LSB _u(0) -#define DMA_CH10_AL2_CTRL_ACCESS "RO" +#define DMA_CH10_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL2_TRANS_COUNT // Description : Alias for channel 10 TRANS_COUNT register @@ -4231,7 +4222,7 @@ #define DMA_CH10_AL2_TRANS_COUNT_RESET "-" #define DMA_CH10_AL2_TRANS_COUNT_MSB _u(31) #define DMA_CH10_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL2_READ_ADDR // Description : Alias for channel 10 READ_ADDR register @@ -4240,7 +4231,7 @@ #define DMA_CH10_AL2_READ_ADDR_RESET "-" #define DMA_CH10_AL2_READ_ADDR_MSB _u(31) #define DMA_CH10_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH10_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH10_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 10 WRITE_ADDR register @@ -4251,7 +4242,7 @@ #define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-" #define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB _u(31) #define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL3_CTRL // Description : Alias for channel 10 CTRL register @@ -4260,7 +4251,7 @@ #define DMA_CH10_AL3_CTRL_RESET "-" #define DMA_CH10_AL3_CTRL_MSB _u(31) #define DMA_CH10_AL3_CTRL_LSB _u(0) -#define DMA_CH10_AL3_CTRL_ACCESS "RO" +#define DMA_CH10_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL3_WRITE_ADDR // Description : Alias for channel 10 WRITE_ADDR register @@ -4269,7 +4260,7 @@ #define DMA_CH10_AL3_WRITE_ADDR_RESET "-" #define DMA_CH10_AL3_WRITE_ADDR_MSB _u(31) #define DMA_CH10_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL3_TRANS_COUNT // Description : Alias for channel 10 TRANS_COUNT register @@ -4278,7 +4269,7 @@ #define DMA_CH10_AL3_TRANS_COUNT_RESET "-" #define DMA_CH10_AL3_TRANS_COUNT_MSB _u(31) #define DMA_CH10_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH10_AL3_READ_ADDR_TRIG // Description : Alias for channel 10 READ_ADDR register @@ -4289,7 +4280,7 @@ #define DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-" #define DMA_CH10_AL3_READ_ADDR_TRIG_MSB _u(31) #define DMA_CH10_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_READ_ADDR // Description : DMA Channel 11 Read Address pointer @@ -4347,7 +4338,7 @@ // Description : DMA Channel 11 Control and Status #define DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc) #define DMA_CH11_CTRL_TRIG_BITS _u(0xe1ffffff) -#define DMA_CH11_CTRL_TRIG_RESET _u(0x00005800) +#define DMA_CH11_CTRL_TRIG_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_AHB_ERROR // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel @@ -4363,7 +4354,7 @@ // Description : If 1, the channel received a read bus error. Write one to // clear. // READ_ADDR shows the approximate address where the bus error was -// encountered (will not to be earlier, or more than 3 transfers +// encountered (will not be earlier, or more than 3 transfers // later) #define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET _u(0x0) #define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) @@ -4375,8 +4366,8 @@ // Description : If 1, the channel received a write bus error. Write one to // clear. // WRITE_ADDR shows the approximate address where the bus error -// was encountered (will not to be earlier, or more than 5 -// transfers later) +// was encountered (will not be earlier, or more than 5 transfers +// later) #define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) #define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) #define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB _u(29) @@ -4403,8 +4394,8 @@ // checksum. This only applies if the sniff hardware is enabled, // and has this channel selected. // -// This allows checksum to be enabled or disabled on a -// per-control- block basis. +// This allows checksum to be enabled or disabled on a per- +// control- block basis. #define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) #define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000) #define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB _u(23) @@ -4447,23 +4438,22 @@ // 0x3d -> Select Timer 2 as TREQ (Optional) // 0x3e -> Select Timer 3 as TREQ (Optional) // 0x3f -> Permanent request, for unpaced transfers. -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(20) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _u(15) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) -#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(20) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _u(15) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) #define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_CHAIN_TO // Description : When this channel completes, it will trigger the channel // indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this // channel)_. -// Reset value is equal to channel number (11). -#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _u(0xb) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) #define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800) #define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB _u(14) #define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB _u(11) @@ -4489,11 +4479,11 @@ // apply to either read or write addresses, based on value of // RING_SEL. // 0x0 -> RING_NONE -#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _u(9) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _u(6) -#define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _u(9) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _u(6) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW" #define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_INCR_WRITE @@ -4527,14 +4517,14 @@ // 0x0 -> SIZE_BYTE // 0x1 -> SIZE_HALFWORD // 0x2 -> SIZE_WORD -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _u(3) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _u(2) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW" -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) #define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) -#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) // ----------------------------------------------------------------------------- // Field : DMA_CH11_CTRL_TRIG_HIGH_PRIORITY // Description : HIGH_PRIORITY gives a channel preferential treatment in issue @@ -4573,7 +4563,7 @@ #define DMA_CH11_AL1_CTRL_RESET "-" #define DMA_CH11_AL1_CTRL_MSB _u(31) #define DMA_CH11_AL1_CTRL_LSB _u(0) -#define DMA_CH11_AL1_CTRL_ACCESS "RO" +#define DMA_CH11_AL1_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL1_READ_ADDR // Description : Alias for channel 11 READ_ADDR register @@ -4582,7 +4572,7 @@ #define DMA_CH11_AL1_READ_ADDR_RESET "-" #define DMA_CH11_AL1_READ_ADDR_MSB _u(31) #define DMA_CH11_AL1_READ_ADDR_LSB _u(0) -#define DMA_CH11_AL1_READ_ADDR_ACCESS "RO" +#define DMA_CH11_AL1_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL1_WRITE_ADDR // Description : Alias for channel 11 WRITE_ADDR register @@ -4591,7 +4581,7 @@ #define DMA_CH11_AL1_WRITE_ADDR_RESET "-" #define DMA_CH11_AL1_WRITE_ADDR_MSB _u(31) #define DMA_CH11_AL1_WRITE_ADDR_LSB _u(0) -#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RO" +#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL1_TRANS_COUNT_TRIG // Description : Alias for channel 11 TRANS_COUNT register @@ -4602,7 +4592,7 @@ #define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-" #define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB _u(31) #define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB _u(0) -#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RO" +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL2_CTRL // Description : Alias for channel 11 CTRL register @@ -4611,7 +4601,7 @@ #define DMA_CH11_AL2_CTRL_RESET "-" #define DMA_CH11_AL2_CTRL_MSB _u(31) #define DMA_CH11_AL2_CTRL_LSB _u(0) -#define DMA_CH11_AL2_CTRL_ACCESS "RO" +#define DMA_CH11_AL2_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL2_TRANS_COUNT // Description : Alias for channel 11 TRANS_COUNT register @@ -4620,7 +4610,7 @@ #define DMA_CH11_AL2_TRANS_COUNT_RESET "-" #define DMA_CH11_AL2_TRANS_COUNT_MSB _u(31) #define DMA_CH11_AL2_TRANS_COUNT_LSB _u(0) -#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RO" +#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL2_READ_ADDR // Description : Alias for channel 11 READ_ADDR register @@ -4629,7 +4619,7 @@ #define DMA_CH11_AL2_READ_ADDR_RESET "-" #define DMA_CH11_AL2_READ_ADDR_MSB _u(31) #define DMA_CH11_AL2_READ_ADDR_LSB _u(0) -#define DMA_CH11_AL2_READ_ADDR_ACCESS "RO" +#define DMA_CH11_AL2_READ_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL2_WRITE_ADDR_TRIG // Description : Alias for channel 11 WRITE_ADDR register @@ -4640,7 +4630,7 @@ #define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-" #define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB _u(31) #define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB _u(0) -#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RO" +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL3_CTRL // Description : Alias for channel 11 CTRL register @@ -4649,7 +4639,7 @@ #define DMA_CH11_AL3_CTRL_RESET "-" #define DMA_CH11_AL3_CTRL_MSB _u(31) #define DMA_CH11_AL3_CTRL_LSB _u(0) -#define DMA_CH11_AL3_CTRL_ACCESS "RO" +#define DMA_CH11_AL3_CTRL_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL3_WRITE_ADDR // Description : Alias for channel 11 WRITE_ADDR register @@ -4658,7 +4648,7 @@ #define DMA_CH11_AL3_WRITE_ADDR_RESET "-" #define DMA_CH11_AL3_WRITE_ADDR_MSB _u(31) #define DMA_CH11_AL3_WRITE_ADDR_LSB _u(0) -#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RO" +#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL3_TRANS_COUNT // Description : Alias for channel 11 TRANS_COUNT register @@ -4667,7 +4657,7 @@ #define DMA_CH11_AL3_TRANS_COUNT_RESET "-" #define DMA_CH11_AL3_TRANS_COUNT_MSB _u(31) #define DMA_CH11_AL3_TRANS_COUNT_LSB _u(0) -#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RO" +#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RW" // ============================================================================= // Register : DMA_CH11_AL3_READ_ADDR_TRIG // Description : Alias for channel 11 READ_ADDR register @@ -4678,7 +4668,7 @@ #define DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-" #define DMA_CH11_AL3_READ_ADDR_TRIG_MSB _u(31) #define DMA_CH11_AL3_READ_ADDR_TRIG_LSB _u(0) -#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RO" +#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RW" // ============================================================================= // Register : DMA_INTR // Description : Interrupt Status (raw) @@ -4702,7 +4692,7 @@ #define DMA_INTR_RESET _u(0x00000000) #define DMA_INTR_MSB _u(15) #define DMA_INTR_LSB _u(0) -#define DMA_INTR_ACCESS "RO" +#define DMA_INTR_ACCESS "WC" // ============================================================================= // Register : DMA_INTE0 // Description : Interrupt Enables for IRQ 0 @@ -4937,26 +4927,23 @@ #define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_CALC -// Description : 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial) -// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit -// reversed data +// 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial) +// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data // 0x2 -> Calculate a CRC-16-CCITT // 0x3 -> Calculate a CRC-16-CCITT with bit reversed data -// 0xe -> XOR reduction over all data. == 1 if the total 1 -// population count is odd. -// 0xf -> Calculate a simple 32-bit checksum (addition with a 32 -// bit accumulator) -#define DMA_SNIFF_CTRL_CALC_RESET _u(0x0) -#define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0) -#define DMA_SNIFF_CTRL_CALC_MSB _u(8) -#define DMA_SNIFF_CTRL_CALC_LSB _u(5) -#define DMA_SNIFF_CTRL_CALC_ACCESS "RW" -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _u(0x0) +// 0xe -> XOR reduction over all data. == 1 if the total 1 population count is odd. +// 0xf -> Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) +#define DMA_SNIFF_CTRL_CALC_RESET _u(0x0) +#define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0) +#define DMA_SNIFF_CTRL_CALC_MSB _u(8) +#define DMA_SNIFF_CTRL_CALC_LSB _u(5) +#define DMA_SNIFF_CTRL_CALC_ACCESS "RW" +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _u(0x0) #define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R _u(0x1) -#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _u(0x2) +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _u(0x2) #define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R _u(0x3) -#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN _u(0xe) -#define DMA_SNIFF_CTRL_CALC_VALUE_SUM _u(0xf) +#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN _u(0xe) +#define DMA_SNIFF_CTRL_CALC_VALUE_SUM _u(0xf) // ----------------------------------------------------------------------------- // Field : DMA_SNIFF_CTRL_DMACH // Description : DMA channel for Sniffer to observe @@ -5056,7 +5043,7 @@ #define DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH0_DBG_CTDREQ_MSB _u(5) #define DMA_CH0_DBG_CTDREQ_LSB _u(0) -#define DMA_CH0_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH0_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH0_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5078,7 +5065,7 @@ #define DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH1_DBG_CTDREQ_MSB _u(5) #define DMA_CH1_DBG_CTDREQ_LSB _u(0) -#define DMA_CH1_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH1_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH1_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5100,7 +5087,7 @@ #define DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH2_DBG_CTDREQ_MSB _u(5) #define DMA_CH2_DBG_CTDREQ_LSB _u(0) -#define DMA_CH2_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH2_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH2_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5122,7 +5109,7 @@ #define DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH3_DBG_CTDREQ_MSB _u(5) #define DMA_CH3_DBG_CTDREQ_LSB _u(0) -#define DMA_CH3_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH3_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH3_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5144,7 +5131,7 @@ #define DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH4_DBG_CTDREQ_MSB _u(5) #define DMA_CH4_DBG_CTDREQ_LSB _u(0) -#define DMA_CH4_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH4_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH4_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5166,7 +5153,7 @@ #define DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH5_DBG_CTDREQ_MSB _u(5) #define DMA_CH5_DBG_CTDREQ_LSB _u(0) -#define DMA_CH5_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH5_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH5_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5188,7 +5175,7 @@ #define DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH6_DBG_CTDREQ_MSB _u(5) #define DMA_CH6_DBG_CTDREQ_LSB _u(0) -#define DMA_CH6_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH6_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH6_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5210,7 +5197,7 @@ #define DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH7_DBG_CTDREQ_MSB _u(5) #define DMA_CH7_DBG_CTDREQ_LSB _u(0) -#define DMA_CH7_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH7_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH7_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5232,7 +5219,7 @@ #define DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH8_DBG_CTDREQ_MSB _u(5) #define DMA_CH8_DBG_CTDREQ_LSB _u(0) -#define DMA_CH8_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH8_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH8_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5254,7 +5241,7 @@ #define DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH9_DBG_CTDREQ_MSB _u(5) #define DMA_CH9_DBG_CTDREQ_LSB _u(0) -#define DMA_CH9_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH9_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH9_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5276,7 +5263,7 @@ #define DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH10_DBG_CTDREQ_MSB _u(5) #define DMA_CH10_DBG_CTDREQ_LSB _u(0) -#define DMA_CH10_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH10_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH10_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5298,7 +5285,7 @@ #define DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000) #define DMA_CH11_DBG_CTDREQ_MSB _u(5) #define DMA_CH11_DBG_CTDREQ_LSB _u(0) -#define DMA_CH11_DBG_CTDREQ_ACCESS "RO" +#define DMA_CH11_DBG_CTDREQ_ACCESS "WC" // ============================================================================= // Register : DMA_CH11_DBG_TCR // Description : Read to get channel TRANS_COUNT reload value, i.e. the length @@ -5310,4 +5297,5 @@ #define DMA_CH11_DBG_TCR_LSB _u(0) #define DMA_CH11_DBG_TCR_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_DMA_DEFINED +#endif // _HARDWARE_REGS_DMA_H + diff --git a/lib/pico-sdk/rp2040/hardware/regs/dreq.h b/lib/pico-sdk/rp2040/hardware/regs/dreq.h new file mode 100644 index 000000000000..d3359f846c71 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/regs/dreq.h @@ -0,0 +1,117 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _DREQ_H +#define _DREQ_H + +/** + * \file rp2040/dreq.h + */ + +#ifdef __ASSEMBLER__ +#define DREQ_PIO0_TX0 0 +#define DREQ_PIO0_TX1 1 +#define DREQ_PIO0_TX2 2 +#define DREQ_PIO0_TX3 3 +#define DREQ_PIO0_RX0 4 +#define DREQ_PIO0_RX1 5 +#define DREQ_PIO0_RX2 6 +#define DREQ_PIO0_RX3 7 +#define DREQ_PIO1_TX0 8 +#define DREQ_PIO1_TX1 9 +#define DREQ_PIO1_TX2 10 +#define DREQ_PIO1_TX3 11 +#define DREQ_PIO1_RX0 12 +#define DREQ_PIO1_RX1 13 +#define DREQ_PIO1_RX2 14 +#define DREQ_PIO1_RX3 15 +#define DREQ_SPI0_TX 16 +#define DREQ_SPI0_RX 17 +#define DREQ_SPI1_TX 18 +#define DREQ_SPI1_RX 19 +#define DREQ_UART0_TX 20 +#define DREQ_UART0_RX 21 +#define DREQ_UART1_TX 22 +#define DREQ_UART1_RX 23 +#define DREQ_PWM_WRAP0 24 +#define DREQ_PWM_WRAP1 25 +#define DREQ_PWM_WRAP2 26 +#define DREQ_PWM_WRAP3 27 +#define DREQ_PWM_WRAP4 28 +#define DREQ_PWM_WRAP5 29 +#define DREQ_PWM_WRAP6 30 +#define DREQ_PWM_WRAP7 31 +#define DREQ_I2C0_TX 32 +#define DREQ_I2C0_RX 33 +#define DREQ_I2C1_TX 34 +#define DREQ_I2C1_RX 35 +#define DREQ_ADC 36 +#define DREQ_XIP_STREAM 37 +#define DREQ_XIP_SSITX 38 +#define DREQ_XIP_SSIRX 39 +#define DREQ_DMA_TIMER0 59 +#define DREQ_DMA_TIMER1 60 +#define DREQ_DMA_TIMER2 61 +#define DREQ_DMA_TIMER3 62 +#define DREQ_FORCE 63 +#else +/** + * \brief DREQ numbers for DMA pacing on RP2040 (used as typedef \ref dreq_num_t) + * \ingroup hardware_dma + */ +typedef enum dreq_num_rp2040 { + DREQ_PIO0_TX0 = 0, ///< Select PIO0's TX FIFO 0 as DREQ + DREQ_PIO0_TX1 = 1, ///< Select PIO0's TX FIFO 1 as DREQ + DREQ_PIO0_TX2 = 2, ///< Select PIO0's TX FIFO 2 as DREQ + DREQ_PIO0_TX3 = 3, ///< Select PIO0's TX FIFO 3 as DREQ + DREQ_PIO0_RX0 = 4, ///< Select PIO0's RX FIFO 0 as DREQ + DREQ_PIO0_RX1 = 5, ///< Select PIO0's RX FIFO 1 as DREQ + DREQ_PIO0_RX2 = 6, ///< Select PIO0's RX FIFO 2 as DREQ + DREQ_PIO0_RX3 = 7, ///< Select PIO0's RX FIFO 3 as DREQ + DREQ_PIO1_TX0 = 8, ///< Select PIO1's TX FIFO 0 as DREQ + DREQ_PIO1_TX1 = 9, ///< Select PIO1's TX FIFO 1 as DREQ + DREQ_PIO1_TX2 = 10, ///< Select PIO1's TX FIFO 2 as DREQ + DREQ_PIO1_TX3 = 11, ///< Select PIO1's TX FIFO 3 as DREQ + DREQ_PIO1_RX0 = 12, ///< Select PIO1's RX FIFO 0 as DREQ + DREQ_PIO1_RX1 = 13, ///< Select PIO1's RX FIFO 1 as DREQ + DREQ_PIO1_RX2 = 14, ///< Select PIO1's RX FIFO 2 as DREQ + DREQ_PIO1_RX3 = 15, ///< Select PIO1's RX FIFO 3 as DREQ + DREQ_SPI0_TX = 16, ///< Select SPI0's TX FIFO as DREQ + DREQ_SPI0_RX = 17, ///< Select SPI0's RX FIFO as DREQ + DREQ_SPI1_TX = 18, ///< Select SPI1's TX FIFO as DREQ + DREQ_SPI1_RX = 19, ///< Select SPI1's RX FIFO as DREQ + DREQ_UART0_TX = 20, ///< Select UART0's TX FIFO as DREQ + DREQ_UART0_RX = 21, ///< Select UART0's RX FIFO as DREQ + DREQ_UART1_TX = 22, ///< Select UART1's TX FIFO as DREQ + DREQ_UART1_RX = 23, ///< Select UART1's RX FIFO as DREQ + DREQ_PWM_WRAP0 = 24, ///< Select PWM Counter 0's Wrap Value as DREQ + DREQ_PWM_WRAP1 = 25, ///< Select PWM Counter 1's Wrap Value as DREQ + DREQ_PWM_WRAP2 = 26, ///< Select PWM Counter 2's Wrap Value as DREQ + DREQ_PWM_WRAP3 = 27, ///< Select PWM Counter 3's Wrap Value as DREQ + DREQ_PWM_WRAP4 = 28, ///< Select PWM Counter 4's Wrap Value as DREQ + DREQ_PWM_WRAP5 = 29, ///< Select PWM Counter 5's Wrap Value as DREQ + DREQ_PWM_WRAP6 = 30, ///< Select PWM Counter 6's Wrap Value as DREQ + DREQ_PWM_WRAP7 = 31, ///< Select PWM Counter 7's Wrap Value as DREQ + DREQ_I2C0_TX = 32, ///< Select I2C0's TX FIFO as DREQ + DREQ_I2C0_RX = 33, ///< Select I2C0's RX FIFO as DREQ + DREQ_I2C1_TX = 34, ///< Select I2C1's TX FIFO as DREQ + DREQ_I2C1_RX = 35, ///< Select I2C1's RX FIFO as DREQ + DREQ_ADC = 36, ///< Select the ADC as DREQ + DREQ_XIP_STREAM = 37, ///< Select the XIP Streaming FIFO as DREQ + DREQ_XIP_SSITX = 38, ///< Select the XIP SSI TX FIFO as DREQ + DREQ_XIP_SSIRX = 39, ///< Select the XIP SSI RX FIFO as DREQ + DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ + DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ + DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ + DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ + DREQ_FORCE = 63, ///< Select FORCE as DREQ + DREQ_COUNT +} dreq_num_t; +#endif + +#endif // _DREQ_H + diff --git a/lib/rp2040/hardware/regs/i2c.h b/lib/pico-sdk/rp2040/hardware/regs/i2c.h similarity index 77% rename from lib/rp2040/hardware/regs/i2c.h rename to lib/pico-sdk/rp2040/hardware/regs/i2c.h index 9384bed05daf..f44ceb440272 100644 --- a/lib/rp2040/hardware/regs/i2c.h +++ b/lib/pico-sdk/rp2040/hardware/regs/i2c.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,9 +10,83 @@ // Version : 1 // Bus type : apb // Description : DW_apb_i2c address block +// +// List of configuration constants for the Synopsys I2C +// hardware (you may see references to these in I2C register +// header; these are *fixed* values, set at hardware design +// time): +// +// IC_ULTRA_FAST_MODE ................ 0x0 +// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 +// IC_UFM_SCL_LOW_COUNT .............. 0x0008 +// IC_UFM_SCL_HIGH_COUNT ............. 0x0006 +// IC_TX_TL .......................... 0x0 +// IC_TX_CMD_BLOCK ................... 0x1 +// IC_HAS_DMA ........................ 0x1 +// IC_HAS_ASYNC_FIFO ................. 0x0 +// IC_SMBUS_ARP ...................... 0x0 +// IC_FIRST_DATA_BYTE_STATUS ......... 0x1 +// IC_INTR_IO ........................ 0x1 +// IC_MASTER_MODE .................... 0x1 +// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 +// IC_INTR_POL ....................... 0x1 +// IC_OPTIONAL_SAR ................... 0x0 +// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 +// IC_DEFAULT_SLAVE_ADDR ............. 0x055 +// IC_DEFAULT_HS_SPKLEN .............. 0x1 +// IC_FS_SCL_HIGH_COUNT .............. 0x0006 +// IC_HS_SCL_LOW_COUNT ............... 0x0008 +// IC_DEVICE_ID_VALUE ................ 0x0 +// IC_10BITADDR_MASTER ............... 0x0 +// IC_CLK_FREQ_OPTIMIZATION .......... 0x0 +// IC_DEFAULT_FS_SPKLEN .............. 0x7 +// IC_ADD_ENCODED_PARAMS ............. 0x0 +// IC_DEFAULT_SDA_HOLD ............... 0x000001 +// IC_DEFAULT_SDA_SETUP .............. 0x64 +// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 +// IC_CLOCK_PERIOD ................... 100 +// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 +// IC_RESTART_EN ..................... 0x1 +// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 +// IC_BUS_CLEAR_FEATURE .............. 0x0 +// IC_CAP_LOADING .................... 100 +// IC_FS_SCL_LOW_COUNT ............... 0x000d +// APB_DATA_WIDTH .................... 32 +// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_SLV_DATA_NACK_ONLY ............. 0x1 +// IC_10BITADDR_SLAVE ................ 0x0 +// IC_CLK_TYPE ....................... 0x0 +// IC_SMBUS_UDID_MSB ................. 0x0 +// IC_SMBUS_SUSPEND_ALERT ............ 0x0 +// IC_HS_SCL_HIGH_COUNT .............. 0x0006 +// IC_SLV_RESTART_DET_EN ............. 0x1 +// IC_SMBUS .......................... 0x0 +// IC_OPTIONAL_SAR_DEFAULT ........... 0x0 +// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 +// IC_USE_COUNTS ..................... 0x0 +// IC_RX_BUFFER_DEPTH ................ 16 +// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_RX_FULL_HLD_BUS_EN ............. 0x1 +// IC_SLAVE_DISABLE .................. 0x1 +// IC_RX_TL .......................... 0x0 +// IC_DEVICE_ID ...................... 0x0 +// IC_HC_COUNT_VALUES ................ 0x0 +// I2C_DYNAMIC_TAR_UPDATE ............ 0 +// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff +// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff +// IC_HS_MASTER_CODE ................. 0x1 +// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff +// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff +// IC_SS_SCL_HIGH_COUNT .............. 0x0028 +// IC_SS_SCL_LOW_COUNT ............... 0x002f +// IC_MAX_SPEED_MODE ................. 0x2 +// IC_STAT_FOR_CLK_STRETCH ........... 0x0 +// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 +// IC_DEFAULT_UFM_SPKLEN ............. 0x1 +// IC_TX_BUFFER_DEPTH ................ 16 // ============================================================================= -#ifndef HARDWARE_REGS_I2C_DEFINED -#define HARDWARE_REGS_I2C_DEFINED +#ifndef _HARDWARE_REGS_I2C_H +#define _HARDWARE_REGS_I2C_H // ============================================================================= // Register : I2C_IC_CON // Description : I2C Control Register. This register can be written only when @@ -42,13 +118,13 @@ // Reset value: 0x0. // 0x0 -> Overflow when RX_FIFO is full // 0x1 -> Hold bus when RX_FIFO is full -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET _u(0x0) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS _u(0x00000200) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB _u(9) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB _u(9) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS "RW" +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET _u(0x0) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS _u(0x00000200) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB _u(9) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB _u(9) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS "RW" #define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED _u(0x1) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_TX_EMPTY_CTRL // Description : This bit controls the generation of the TX_EMPTY interrupt, as @@ -57,13 +133,13 @@ // Reset value: 0x0. // 0x0 -> Default behaviour of TX_EMPTY interrupt // 0x1 -> Controlled generation of TX_EMPTY interrupt -#define I2C_IC_CON_TX_EMPTY_CTRL_RESET _u(0x0) -#define I2C_IC_CON_TX_EMPTY_CTRL_BITS _u(0x00000100) -#define I2C_IC_CON_TX_EMPTY_CTRL_MSB _u(8) -#define I2C_IC_CON_TX_EMPTY_CTRL_LSB _u(8) -#define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS "RW" +#define I2C_IC_CON_TX_EMPTY_CTRL_RESET _u(0x0) +#define I2C_IC_CON_TX_EMPTY_CTRL_BITS _u(0x00000100) +#define I2C_IC_CON_TX_EMPTY_CTRL_MSB _u(8) +#define I2C_IC_CON_TX_EMPTY_CTRL_LSB _u(8) +#define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS "RW" #define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED _u(0x1) +#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_STOP_DET_IFADDRESSED // Description : In slave mode: - 1'b1: issues the STOP_DET interrupt only when @@ -77,13 +153,13 @@ // transmitted address matches the slave address (SAR). // 0x0 -> slave issues STOP_DET intr always // 0x1 -> slave issues STOP_DET intr only if addressed -#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET _u(0x0) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS _u(0x00000080) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB _u(7) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB _u(7) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS "RW" +#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET _u(0x0) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS _u(0x00000080) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB _u(7) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB _u(7) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS "RW" #define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED _u(0x1) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_SLAVE_DISABLE // Description : This bit controls whether I2C has its slave disabled, which @@ -98,12 +174,12 @@ // 0, then bit 0 should also be written with a 0. // 0x0 -> Slave mode is enabled // 0x1 -> Slave mode is disabled -#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET _u(0x1) -#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS _u(0x00000040) -#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB _u(6) -#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB _u(6) -#define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS "RW" -#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED _u(0x0) +#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET _u(0x1) +#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS _u(0x00000040) +#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB _u(6) +#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB _u(6) +#define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS "RW" +#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED _u(0x0) #define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_RESTART_EN @@ -112,25 +188,25 @@ // conditions; however, RESTART conditions are used in several // DW_apb_i2c operations. When RESTART is disabled, the master is // prohibited from performing the following functions: - Sending a -// START BYTE - Performing any high-speed mode operation - -// High-speed mode operation - Performing direction changes in -// combined format mode - Performing a read operation with a -// 10-bit address By replacing RESTART condition followed by a -// STOP and a subsequent START condition, split operations are -// broken down into multiple DW_apb_i2c transfers. If the above -// operations are performed, it will result in setting bit 6 -// (TX_ABRT) of the IC_RAW_INTR_STAT register. +// START BYTE - Performing any high-speed mode operation - High- +// speed mode operation - Performing direction changes in combined +// format mode - Performing a read operation with a 10-bit address +// By replacing RESTART condition followed by a STOP and a +// subsequent START condition, split operations are broken down +// into multiple DW_apb_i2c transfers. If the above operations are +// performed, it will result in setting bit 6 (TX_ABRT) of the +// IC_RAW_INTR_STAT register. // // Reset value: ENABLED // 0x0 -> Master restart disabled // 0x1 -> Master restart enabled -#define I2C_IC_CON_IC_RESTART_EN_RESET _u(0x1) -#define I2C_IC_CON_IC_RESTART_EN_BITS _u(0x00000020) -#define I2C_IC_CON_IC_RESTART_EN_MSB _u(5) -#define I2C_IC_CON_IC_RESTART_EN_LSB _u(5) -#define I2C_IC_CON_IC_RESTART_EN_ACCESS "RW" +#define I2C_IC_CON_IC_RESTART_EN_RESET _u(0x1) +#define I2C_IC_CON_IC_RESTART_EN_BITS _u(0x00000020) +#define I2C_IC_CON_IC_RESTART_EN_MSB _u(5) +#define I2C_IC_CON_IC_RESTART_EN_LSB _u(5) +#define I2C_IC_CON_IC_RESTART_EN_ACCESS "RW" #define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED _u(0x1) +#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_10BITADDR_MASTER // Description : Controls whether the DW_apb_i2c starts its transfers in 7- or @@ -138,12 +214,12 @@ // addressing - 1: 10-bit addressing // 0x0 -> Master 7Bit addressing mode // 0x1 -> Master 10Bit addressing mode -#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET _u(0x0) -#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS _u(0x00000010) -#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB _u(4) -#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB _u(4) -#define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS "RW" -#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS _u(0x00000010) +#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB _u(4) +#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB _u(4) +#define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS "RW" +#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS _u(0x0) #define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_IC_10BITADDR_SLAVE @@ -156,12 +232,12 @@ // that match the full 10 bits of the IC_SAR register. // 0x0 -> Slave 7Bit addressing // 0x1 -> Slave 10Bit addressing -#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET _u(0x0) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS _u(0x00000008) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB _u(3) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB _u(3) -#define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS "RW" -#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS _u(0x00000008) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB _u(3) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB _u(3) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS "RW" +#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS _u(0x0) #define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_SPEED @@ -186,14 +262,14 @@ // 0x1 -> Standard Speed mode of operation // 0x2 -> Fast or Fast Plus mode of operation // 0x3 -> High Speed mode of operation -#define I2C_IC_CON_SPEED_RESET _u(0x2) -#define I2C_IC_CON_SPEED_BITS _u(0x00000006) -#define I2C_IC_CON_SPEED_MSB _u(2) -#define I2C_IC_CON_SPEED_LSB _u(1) -#define I2C_IC_CON_SPEED_ACCESS "RW" +#define I2C_IC_CON_SPEED_RESET _u(0x2) +#define I2C_IC_CON_SPEED_BITS _u(0x00000006) +#define I2C_IC_CON_SPEED_MSB _u(2) +#define I2C_IC_CON_SPEED_LSB _u(1) +#define I2C_IC_CON_SPEED_ACCESS "RW" #define I2C_IC_CON_SPEED_VALUE_STANDARD _u(0x1) -#define I2C_IC_CON_SPEED_VALUE_FAST _u(0x2) -#define I2C_IC_CON_SPEED_VALUE_HIGH _u(0x3) +#define I2C_IC_CON_SPEED_VALUE_FAST _u(0x2) +#define I2C_IC_CON_SPEED_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : I2C_IC_CON_MASTER_MODE // Description : This bit controls whether the DW_apb_i2c master is enabled. @@ -202,13 +278,13 @@ // '1' then bit 6 should also be written with a '1'. // 0x0 -> Master mode is disabled // 0x1 -> Master mode is enabled -#define I2C_IC_CON_MASTER_MODE_RESET _u(0x1) -#define I2C_IC_CON_MASTER_MODE_BITS _u(0x00000001) -#define I2C_IC_CON_MASTER_MODE_MSB _u(0) -#define I2C_IC_CON_MASTER_MODE_LSB _u(0) -#define I2C_IC_CON_MASTER_MODE_ACCESS "RW" +#define I2C_IC_CON_MASTER_MODE_RESET _u(0x1) +#define I2C_IC_CON_MASTER_MODE_BITS _u(0x00000001) +#define I2C_IC_CON_MASTER_MODE_MSB _u(0) +#define I2C_IC_CON_MASTER_MODE_LSB _u(0) +#define I2C_IC_CON_MASTER_MODE_ACCESS "RW" #define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED _u(0x0) -#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED _u(0x1) +#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_TAR // Description : I2C Target Address Register @@ -233,17 +309,15 @@ // GC_OR_START and use IC_TAR normally - 1: perform special I2C // command as specified in Device_ID or GC_OR_START bit Reset // value: 0x0 -// 0x0 -> Disables programming of GENERAL_CALL or START_BYTE -// transmission -// 0x1 -> Enables programming of GENERAL_CALL or START_BYTE -// transmission -#define I2C_IC_TAR_SPECIAL_RESET _u(0x0) -#define I2C_IC_TAR_SPECIAL_BITS _u(0x00000800) -#define I2C_IC_TAR_SPECIAL_MSB _u(11) -#define I2C_IC_TAR_SPECIAL_LSB _u(11) -#define I2C_IC_TAR_SPECIAL_ACCESS "RW" +// 0x0 -> Disables programming of GENERAL_CALL or START_BYTE transmission +// 0x1 -> Enables programming of GENERAL_CALL or START_BYTE transmission +#define I2C_IC_TAR_SPECIAL_RESET _u(0x0) +#define I2C_IC_TAR_SPECIAL_BITS _u(0x00000800) +#define I2C_IC_TAR_SPECIAL_MSB _u(11) +#define I2C_IC_TAR_SPECIAL_LSB _u(11) +#define I2C_IC_TAR_SPECIAL_ACCESS "RW" #define I2C_IC_TAR_SPECIAL_VALUE_DISABLED _u(0x0) -#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED _u(0x1) +#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TAR_GC_OR_START // Description : If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to @@ -256,13 +330,13 @@ // value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 // 0x0 -> GENERAL_CALL byte transmission // 0x1 -> START byte transmission -#define I2C_IC_TAR_GC_OR_START_RESET _u(0x0) -#define I2C_IC_TAR_GC_OR_START_BITS _u(0x00000400) -#define I2C_IC_TAR_GC_OR_START_MSB _u(10) -#define I2C_IC_TAR_GC_OR_START_LSB _u(10) -#define I2C_IC_TAR_GC_OR_START_ACCESS "RW" +#define I2C_IC_TAR_GC_OR_START_RESET _u(0x0) +#define I2C_IC_TAR_GC_OR_START_BITS _u(0x00000400) +#define I2C_IC_TAR_GC_OR_START_MSB _u(10) +#define I2C_IC_TAR_GC_OR_START_LSB _u(10) +#define I2C_IC_TAR_GC_OR_START_ACCESS "RW" #define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL _u(0x0) -#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE _u(0x1) +#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TAR_IC_TAR // Description : This is the target address for any master transaction. When @@ -347,13 +421,13 @@ // FIRST_DATA_BYTE status. // 0x0 -> Sequential data byte received // 0x1 -> Non sequential data byte received -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET _u(0x0) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS _u(0x00000800) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB _u(11) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB _u(11) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS "RO" +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET _u(0x0) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS _u(0x00000800) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB _u(11) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB _u(11) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS "RO" #define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE _u(0x0) -#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE _u(0x1) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_RESTART // Description : This bit controls whether a RESTART is issued before the byte @@ -373,13 +447,13 @@ // Reset value: 0x0 // 0x0 -> Don't Issue RESTART before this command // 0x1 -> Issue RESTART before this command -#define I2C_IC_DATA_CMD_RESTART_RESET _u(0x0) -#define I2C_IC_DATA_CMD_RESTART_BITS _u(0x00000400) -#define I2C_IC_DATA_CMD_RESTART_MSB _u(10) -#define I2C_IC_DATA_CMD_RESTART_LSB _u(10) -#define I2C_IC_DATA_CMD_RESTART_ACCESS "SC" +#define I2C_IC_DATA_CMD_RESTART_RESET _u(0x0) +#define I2C_IC_DATA_CMD_RESTART_BITS _u(0x00000400) +#define I2C_IC_DATA_CMD_RESTART_MSB _u(10) +#define I2C_IC_DATA_CMD_RESTART_LSB _u(10) +#define I2C_IC_DATA_CMD_RESTART_ACCESS "SC" #define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE _u(0x0) -#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE _u(0x1) +#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_STOP // Description : This bit controls whether a STOP is issued after the byte is @@ -397,13 +471,13 @@ // is available in the Tx FIFO. Reset value: 0x0 // 0x0 -> Don't Issue STOP after this command // 0x1 -> Issue STOP after this command -#define I2C_IC_DATA_CMD_STOP_RESET _u(0x0) -#define I2C_IC_DATA_CMD_STOP_BITS _u(0x00000200) -#define I2C_IC_DATA_CMD_STOP_MSB _u(9) -#define I2C_IC_DATA_CMD_STOP_LSB _u(9) -#define I2C_IC_DATA_CMD_STOP_ACCESS "SC" +#define I2C_IC_DATA_CMD_STOP_RESET _u(0x0) +#define I2C_IC_DATA_CMD_STOP_BITS _u(0x00000200) +#define I2C_IC_DATA_CMD_STOP_MSB _u(9) +#define I2C_IC_DATA_CMD_STOP_LSB _u(9) +#define I2C_IC_DATA_CMD_STOP_ACCESS "SC" #define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE _u(0x0) -#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE _u(0x1) +#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_CMD // Description : This bit controls whether a read or a write is performed. This @@ -428,13 +502,13 @@ // Reset value: 0x0 // 0x0 -> Master Write Command // 0x1 -> Master Read Command -#define I2C_IC_DATA_CMD_CMD_RESET _u(0x0) -#define I2C_IC_DATA_CMD_CMD_BITS _u(0x00000100) -#define I2C_IC_DATA_CMD_CMD_MSB _u(8) -#define I2C_IC_DATA_CMD_CMD_LSB _u(8) -#define I2C_IC_DATA_CMD_CMD_ACCESS "SC" +#define I2C_IC_DATA_CMD_CMD_RESET _u(0x0) +#define I2C_IC_DATA_CMD_CMD_BITS _u(0x00000100) +#define I2C_IC_DATA_CMD_CMD_MSB _u(8) +#define I2C_IC_DATA_CMD_CMD_LSB _u(8) +#define I2C_IC_DATA_CMD_CMD_ACCESS "SC" #define I2C_IC_DATA_CMD_CMD_VALUE_WRITE _u(0x0) -#define I2C_IC_DATA_CMD_CMD_VALUE_READ _u(0x1) +#define I2C_IC_DATA_CMD_CMD_VALUE_READ _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DATA_CMD_DAT // Description : This register contains the data to be transmitted or received @@ -552,9 +626,9 @@ // Field : I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT // Description : This register must be set before any I2C bus transaction can // take place to ensure proper I/O timing. This register sets the -// SCL clock low period count for fast speed. It is used in -// high-speed mode to send the Master Code and START BYTE or -// General CALL. For more information, refer to 'IC_CLK Frequency +// SCL clock low period count for fast speed. It is used in high- +// speed mode to send the Master Code and START BYTE or General +// CALL. For more information, refer to 'IC_CLK Frequency // Configuration'. // // This register goes away and becomes read-only returning 0s if @@ -595,13 +669,13 @@ // Reset value: 0x0 // 0x0 -> R_RESTART_DET interrupt is inactive // 0x1 -> R_RESTART_DET interrupt is active -#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS _u(0x00001000) -#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB _u(12) -#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB _u(12) -#define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB _u(12) +#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB _u(12) +#define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS "RO" #define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_GEN_CALL // Description : See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL @@ -610,13 +684,13 @@ // Reset value: 0x0 // 0x0 -> R_GEN_CALL interrupt is inactive // 0x1 -> R_GEN_CALL interrupt is active -#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS _u(0x00000800) -#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB _u(11) -#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB _u(11) -#define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB _u(11) +#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB _u(11) +#define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS "RO" #define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_START_DET // Description : See IC_RAW_INTR_STAT for a detailed description of R_START_DET @@ -625,13 +699,13 @@ // Reset value: 0x0 // 0x0 -> R_START_DET interrupt is inactive // 0x1 -> R_START_DET interrupt is active -#define I2C_IC_INTR_STAT_R_START_DET_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_START_DET_BITS _u(0x00000400) -#define I2C_IC_INTR_STAT_R_START_DET_MSB _u(10) -#define I2C_IC_INTR_STAT_R_START_DET_LSB _u(10) -#define I2C_IC_INTR_STAT_R_START_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_START_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_START_DET_BITS _u(0x00000400) +#define I2C_IC_INTR_STAT_R_START_DET_MSB _u(10) +#define I2C_IC_INTR_STAT_R_START_DET_LSB _u(10) +#define I2C_IC_INTR_STAT_R_START_DET_ACCESS "RO" #define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_STOP_DET // Description : See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET @@ -640,13 +714,13 @@ // Reset value: 0x0 // 0x0 -> R_STOP_DET interrupt is inactive // 0x1 -> R_STOP_DET interrupt is active -#define I2C_IC_INTR_STAT_R_STOP_DET_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_STOP_DET_BITS _u(0x00000200) -#define I2C_IC_INTR_STAT_R_STOP_DET_MSB _u(9) -#define I2C_IC_INTR_STAT_R_STOP_DET_LSB _u(9) -#define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_STOP_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_INTR_STAT_R_STOP_DET_MSB _u(9) +#define I2C_IC_INTR_STAT_R_STOP_DET_LSB _u(9) +#define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS "RO" #define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_ACTIVITY // Description : See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY @@ -655,13 +729,13 @@ // Reset value: 0x0 // 0x0 -> R_ACTIVITY interrupt is inactive // 0x1 -> R_ACTIVITY interrupt is active -#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS _u(0x00000100) -#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB _u(8) -#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB _u(8) -#define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB _u(8) +#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB _u(8) +#define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS "RO" #define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_DONE // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE @@ -670,13 +744,13 @@ // Reset value: 0x0 // 0x0 -> R_RX_DONE interrupt is inactive // 0x1 -> R_RX_DONE interrupt is active -#define I2C_IC_INTR_STAT_R_RX_DONE_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_DONE_BITS _u(0x00000080) -#define I2C_IC_INTR_STAT_R_RX_DONE_MSB _u(7) -#define I2C_IC_INTR_STAT_R_RX_DONE_LSB _u(7) -#define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_DONE_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_INTR_STAT_R_RX_DONE_MSB _u(7) +#define I2C_IC_INTR_STAT_R_RX_DONE_LSB _u(7) +#define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS "RO" #define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_TX_ABRT // Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT @@ -685,13 +759,13 @@ // Reset value: 0x0 // 0x0 -> R_TX_ABRT interrupt is inactive // 0x1 -> R_TX_ABRT interrupt is active -#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS _u(0x00000040) -#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB _u(6) -#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB _u(6) -#define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB _u(6) +#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB _u(6) +#define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS "RO" #define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RD_REQ // Description : See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ @@ -700,13 +774,13 @@ // Reset value: 0x0 // 0x0 -> R_RD_REQ interrupt is inactive // 0x1 -> R_RD_REQ interrupt is active -#define I2C_IC_INTR_STAT_R_RD_REQ_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RD_REQ_BITS _u(0x00000020) -#define I2C_IC_INTR_STAT_R_RD_REQ_MSB _u(5) -#define I2C_IC_INTR_STAT_R_RD_REQ_LSB _u(5) -#define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RD_REQ_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_INTR_STAT_R_RD_REQ_MSB _u(5) +#define I2C_IC_INTR_STAT_R_RD_REQ_LSB _u(5) +#define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS "RO" #define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_TX_EMPTY // Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY @@ -715,13 +789,13 @@ // Reset value: 0x0 // 0x0 -> R_TX_EMPTY interrupt is inactive // 0x1 -> R_TX_EMPTY interrupt is active -#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS _u(0x00000010) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB _u(4) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB _u(4) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB _u(4) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB _u(4) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS "RO" #define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_TX_OVER // Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER @@ -730,13 +804,13 @@ // Reset value: 0x0 // 0x0 -> R_TX_OVER interrupt is inactive // 0x1 -> R_TX_OVER interrupt is active -#define I2C_IC_INTR_STAT_R_TX_OVER_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_OVER_BITS _u(0x00000008) -#define I2C_IC_INTR_STAT_R_TX_OVER_MSB _u(3) -#define I2C_IC_INTR_STAT_R_TX_OVER_LSB _u(3) -#define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_OVER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_INTR_STAT_R_TX_OVER_MSB _u(3) +#define I2C_IC_INTR_STAT_R_TX_OVER_LSB _u(3) +#define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS "RO" #define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_FULL // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL @@ -745,13 +819,13 @@ // Reset value: 0x0 // 0x0 -> R_RX_FULL interrupt is inactive // 0x1 -> R_RX_FULL interrupt is active -#define I2C_IC_INTR_STAT_R_RX_FULL_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_FULL_BITS _u(0x00000004) -#define I2C_IC_INTR_STAT_R_RX_FULL_MSB _u(2) -#define I2C_IC_INTR_STAT_R_RX_FULL_LSB _u(2) -#define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_FULL_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_INTR_STAT_R_RX_FULL_MSB _u(2) +#define I2C_IC_INTR_STAT_R_RX_FULL_LSB _u(2) +#define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS "RO" #define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_OVER // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER @@ -760,13 +834,13 @@ // Reset value: 0x0 // 0x0 -> R_RX_OVER interrupt is inactive // 0x1 -> R_RX_OVER interrupt is active -#define I2C_IC_INTR_STAT_R_RX_OVER_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_OVER_BITS _u(0x00000002) -#define I2C_IC_INTR_STAT_R_RX_OVER_MSB _u(1) -#define I2C_IC_INTR_STAT_R_RX_OVER_LSB _u(1) -#define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_OVER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_INTR_STAT_R_RX_OVER_MSB _u(1) +#define I2C_IC_INTR_STAT_R_RX_OVER_LSB _u(1) +#define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS "RO" #define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_STAT_R_RX_UNDER // Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER @@ -775,13 +849,13 @@ // Reset value: 0x0 // 0x0 -> RX_UNDER interrupt is inactive // 0x1 -> RX_UNDER interrupt is active -#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB _u(0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB _u(0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB _u(0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB _u(0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS "RO" #define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE _u(0x1) +#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_INTR_MASK // Description : I2C Interrupt Mask Register. @@ -800,12 +874,12 @@ // Reset value: 0x0 // 0x0 -> RESTART_DET interrupt is masked // 0x1 -> RESTART_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS _u(0x00001000) -#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB _u(12) -#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB _u(12) -#define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB _u(12) +#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB _u(12) +#define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_GEN_CALL @@ -815,12 +889,12 @@ // Reset value: 0x1 // 0x0 -> GEN_CALL interrupt is masked // 0x1 -> GEN_CALL interrupt is unmasked -#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS _u(0x00000800) -#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB _u(11) -#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB _u(11) -#define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB _u(11) +#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB _u(11) +#define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_START_DET @@ -830,12 +904,12 @@ // Reset value: 0x0 // 0x0 -> START_DET interrupt is masked // 0x1 -> START_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_START_DET_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_START_DET_BITS _u(0x00000400) -#define I2C_IC_INTR_MASK_M_START_DET_MSB _u(10) -#define I2C_IC_INTR_MASK_M_START_DET_LSB _u(10) -#define I2C_IC_INTR_MASK_M_START_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_START_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_START_DET_BITS _u(0x00000400) +#define I2C_IC_INTR_MASK_M_START_DET_MSB _u(10) +#define I2C_IC_INTR_MASK_M_START_DET_LSB _u(10) +#define I2C_IC_INTR_MASK_M_START_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_STOP_DET @@ -845,12 +919,12 @@ // Reset value: 0x0 // 0x0 -> STOP_DET interrupt is masked // 0x1 -> STOP_DET interrupt is unmasked -#define I2C_IC_INTR_MASK_M_STOP_DET_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_STOP_DET_BITS _u(0x00000200) -#define I2C_IC_INTR_MASK_M_STOP_DET_MSB _u(9) -#define I2C_IC_INTR_MASK_M_STOP_DET_LSB _u(9) -#define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_STOP_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_INTR_MASK_M_STOP_DET_MSB _u(9) +#define I2C_IC_INTR_MASK_M_STOP_DET_LSB _u(9) +#define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_ACTIVITY @@ -860,12 +934,12 @@ // Reset value: 0x0 // 0x0 -> ACTIVITY interrupt is masked // 0x1 -> ACTIVITY interrupt is unmasked -#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET _u(0x0) -#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS _u(0x00000100) -#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB _u(8) -#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB _u(8) -#define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB _u(8) +#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB _u(8) +#define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_DONE @@ -875,12 +949,12 @@ // Reset value: 0x1 // 0x0 -> RX_DONE interrupt is masked // 0x1 -> RX_DONE interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_DONE_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_DONE_BITS _u(0x00000080) -#define I2C_IC_INTR_MASK_M_RX_DONE_MSB _u(7) -#define I2C_IC_INTR_MASK_M_RX_DONE_LSB _u(7) -#define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_DONE_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_INTR_MASK_M_RX_DONE_MSB _u(7) +#define I2C_IC_INTR_MASK_M_RX_DONE_LSB _u(7) +#define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_TX_ABRT @@ -890,12 +964,12 @@ // Reset value: 0x1 // 0x0 -> TX_ABORT interrupt is masked // 0x1 -> TX_ABORT interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS _u(0x00000040) -#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB _u(6) -#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB _u(6) -#define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB _u(6) +#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB _u(6) +#define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RD_REQ @@ -904,12 +978,12 @@ // Reset value: 0x1 // 0x0 -> RD_REQ interrupt is masked // 0x1 -> RD_REQ interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RD_REQ_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RD_REQ_BITS _u(0x00000020) -#define I2C_IC_INTR_MASK_M_RD_REQ_MSB _u(5) -#define I2C_IC_INTR_MASK_M_RD_REQ_LSB _u(5) -#define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RD_REQ_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_INTR_MASK_M_RD_REQ_MSB _u(5) +#define I2C_IC_INTR_MASK_M_RD_REQ_LSB _u(5) +#define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_TX_EMPTY @@ -919,12 +993,12 @@ // Reset value: 0x1 // 0x0 -> TX_EMPTY interrupt is masked // 0x1 -> TX_EMPTY interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS _u(0x00000010) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB _u(4) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB _u(4) -#define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB _u(4) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB _u(4) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_TX_OVER @@ -934,12 +1008,12 @@ // Reset value: 0x1 // 0x0 -> TX_OVER interrupt is masked // 0x1 -> TX_OVER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_TX_OVER_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_TX_OVER_BITS _u(0x00000008) -#define I2C_IC_INTR_MASK_M_TX_OVER_MSB _u(3) -#define I2C_IC_INTR_MASK_M_TX_OVER_LSB _u(3) -#define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_OVER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_INTR_MASK_M_TX_OVER_MSB _u(3) +#define I2C_IC_INTR_MASK_M_TX_OVER_LSB _u(3) +#define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_FULL @@ -949,12 +1023,12 @@ // Reset value: 0x1 // 0x0 -> RX_FULL interrupt is masked // 0x1 -> RX_FULL interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_FULL_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_FULL_BITS _u(0x00000004) -#define I2C_IC_INTR_MASK_M_RX_FULL_MSB _u(2) -#define I2C_IC_INTR_MASK_M_RX_FULL_LSB _u(2) -#define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_FULL_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_INTR_MASK_M_RX_FULL_MSB _u(2) +#define I2C_IC_INTR_MASK_M_RX_FULL_LSB _u(2) +#define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_OVER @@ -964,12 +1038,12 @@ // Reset value: 0x1 // 0x0 -> RX_OVER interrupt is masked // 0x1 -> RX_OVER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_OVER_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_OVER_BITS _u(0x00000002) -#define I2C_IC_INTR_MASK_M_RX_OVER_MSB _u(1) -#define I2C_IC_INTR_MASK_M_RX_OVER_LSB _u(1) -#define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_OVER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_INTR_MASK_M_RX_OVER_MSB _u(1) +#define I2C_IC_INTR_MASK_M_RX_OVER_LSB _u(1) +#define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_INTR_MASK_M_RX_UNDER @@ -979,12 +1053,12 @@ // Reset value: 0x1 // 0x0 -> RX_UNDER interrupt is masked // 0x1 -> RX_UNDER interrupt is unmasked -#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET _u(0x1) -#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB _u(0) -#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB _u(0) -#define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS "RW" -#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB _u(0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB _u(0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED _u(0x0) #define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED _u(0x1) // ============================================================================= // Register : I2C_IC_RAW_INTR_STAT @@ -1011,13 +1085,13 @@ // Reset value: 0x0 // 0x0 -> RESTART_DET interrupt is inactive // 0x1 -> RESTART_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS _u(0x00001000) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB _u(12) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB _u(12) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB _u(12) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB _u(12) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_GEN_CALL // Description : Set only when a General Call address is received and it is @@ -1029,13 +1103,13 @@ // Reset value: 0x0 // 0x0 -> GEN_CALL interrupt is inactive // 0x1 -> GEN_CALL interrupt is active -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS _u(0x00000800) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB _u(11) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB _u(11) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB _u(11) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB _u(11) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_START_DET // Description : Indicates whether a START or RESTART condition has occurred on @@ -1045,13 +1119,13 @@ // Reset value: 0x0 // 0x0 -> START_DET interrupt is inactive // 0x1 -> START_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_START_DET_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_START_DET_BITS _u(0x00000400) -#define I2C_IC_RAW_INTR_STAT_START_DET_MSB _u(10) -#define I2C_IC_RAW_INTR_STAT_START_DET_LSB _u(10) -#define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_START_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_START_DET_BITS _u(0x00000400) +#define I2C_IC_RAW_INTR_STAT_START_DET_MSB _u(10) +#define I2C_IC_RAW_INTR_STAT_START_DET_LSB _u(10) +#define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_STOP_DET // Description : Indicates whether a STOP condition has occurred on the I2C @@ -1074,13 +1148,13 @@ // Reset value: 0x0 // 0x0 -> STOP_DET interrupt is inactive // 0x1 -> STOP_DET interrupt is active -#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS _u(0x00000200) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB _u(9) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB _u(9) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB _u(9) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB _u(9) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_ACTIVITY // Description : This bit captures DW_apb_i2c activity and stays set until it is @@ -1094,13 +1168,13 @@ // Reset value: 0x0 // 0x0 -> RAW_INTR_ACTIVITY interrupt is inactive // 0x1 -> RAW_INTR_ACTIVITY interrupt is active -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS _u(0x00000100) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB _u(8) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB _u(8) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB _u(8) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB _u(8) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_DONE // Description : When the DW_apb_i2c is acting as a slave-transmitter, this bit @@ -1111,13 +1185,13 @@ // Reset value: 0x0 // 0x0 -> RX_DONE interrupt is inactive // 0x1 -> RX_DONE interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS _u(0x00000080) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB _u(7) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB _u(7) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB _u(7) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB _u(7) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_TX_ABRT // Description : This bit indicates if DW_apb_i2c, as an I2C transmitter, is @@ -1137,13 +1211,13 @@ // Reset value: 0x0 // 0x0 -> TX_ABRT interrupt is inactive // 0x1 -> TX_ABRT interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS _u(0x00000040) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB _u(6) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB _u(6) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB _u(6) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB _u(6) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RD_REQ // Description : This bit is set to 1 when DW_apb_i2c is acting as a slave and @@ -1159,13 +1233,13 @@ // Reset value: 0x0 // 0x0 -> RD_REQ interrupt is inactive // 0x1 -> RD_REQ interrupt is active -#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS _u(0x00000020) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB _u(5) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB _u(5) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB _u(5) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB _u(5) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_TX_EMPTY // Description : The behavior of the TX_EMPTY interrupt status differs based on @@ -1187,13 +1261,13 @@ // Reset value: 0x0. // 0x0 -> TX_EMPTY interrupt is inactive // 0x1 -> TX_EMPTY interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS _u(0x00000010) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB _u(4) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB _u(4) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB _u(4) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB _u(4) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_TX_OVER // Description : Set during transmit if the transmit buffer is filled to @@ -1206,13 +1280,13 @@ // Reset value: 0x0 // 0x0 -> TX_OVER interrupt is inactive // 0x1 -> TX_OVER interrupt is active -#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS _u(0x00000008) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB _u(3) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB _u(3) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB _u(3) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB _u(3) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_FULL // Description : Set when the receive buffer reaches or goes above the RX_TL @@ -1226,13 +1300,13 @@ // Reset value: 0x0 // 0x0 -> RX_FULL interrupt is inactive // 0x1 -> RX_FULL interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS _u(0x00000004) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB _u(2) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB _u(2) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB _u(2) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB _u(2) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_OVER // Description : Set if the receive buffer is completely filled to @@ -1250,13 +1324,13 @@ // Reset value: 0x0 // 0x0 -> RX_OVER interrupt is inactive // 0x1 -> RX_OVER interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS _u(0x00000002) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB _u(1) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB _u(1) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB _u(1) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB _u(1) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_RAW_INTR_STAT_RX_UNDER // Description : Set if the processor attempts to read the receive buffer when @@ -1268,13 +1342,13 @@ // Reset value: 0x0 // 0x0 -> RX_UNDER interrupt is inactive // 0x1 -> RX_UNDER interrupt is active -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS _u(0x00000001) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB _u(0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB _u(0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB _u(0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB _u(0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS "RO" #define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE _u(0x0) -#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE _u(0x1) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_RX_TL // Description : I2C Receive FIFO Threshold Register @@ -1539,13 +1613,13 @@ // value: IC_TX_CMD_BLOCK_DEFAULT // 0x0 -> Tx Command execution not blocked // 0x1 -> Tx Command execution blocked -#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET _u(0x0) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS _u(0x00000004) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB _u(2) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB _u(2) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS "RW" +#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET _u(0x0) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS _u(0x00000004) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB _u(2) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB _u(2) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS "RW" #define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED _u(0x0) -#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED _u(0x1) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_ABORT // Description : When set, the controller initiates the transfer abort. - 0: @@ -1565,11 +1639,11 @@ // Reset value: 0x0 // 0x0 -> ABORT operation not in progress // 0x1 -> ABORT operation in progress -#define I2C_IC_ENABLE_ABORT_RESET _u(0x0) -#define I2C_IC_ENABLE_ABORT_BITS _u(0x00000002) -#define I2C_IC_ENABLE_ABORT_MSB _u(1) -#define I2C_IC_ENABLE_ABORT_LSB _u(1) -#define I2C_IC_ENABLE_ABORT_ACCESS "RW" +#define I2C_IC_ENABLE_ABORT_RESET _u(0x0) +#define I2C_IC_ENABLE_ABORT_BITS _u(0x00000002) +#define I2C_IC_ENABLE_ABORT_MSB _u(1) +#define I2C_IC_ENABLE_ABORT_LSB _u(1) +#define I2C_IC_ENABLE_ABORT_ACCESS "RW" #define I2C_IC_ENABLE_ABORT_VALUE_DISABLE _u(0x0) #define I2C_IC_ENABLE_ABORT_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- @@ -1599,13 +1673,13 @@ // Reset value: 0x0 // 0x0 -> I2C is disabled // 0x1 -> I2C is enabled -#define I2C_IC_ENABLE_ENABLE_RESET _u(0x0) -#define I2C_IC_ENABLE_ENABLE_BITS _u(0x00000001) -#define I2C_IC_ENABLE_ENABLE_MSB _u(0) -#define I2C_IC_ENABLE_ENABLE_LSB _u(0) -#define I2C_IC_ENABLE_ENABLE_ACCESS "RW" +#define I2C_IC_ENABLE_ENABLE_RESET _u(0x0) +#define I2C_IC_ENABLE_ENABLE_BITS _u(0x00000001) +#define I2C_IC_ENABLE_ENABLE_MSB _u(0) +#define I2C_IC_ENABLE_ENABLE_LSB _u(0) +#define I2C_IC_ENABLE_ENABLE_ACCESS "RW" #define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED _u(0x0) -#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED _u(0x1) +#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_STATUS // Description : I2C Status Register @@ -1631,12 +1705,12 @@ // DW_apb_i2c is Active Reset value: 0x0 // 0x0 -> Slave is idle // 0x1 -> Slave not idle -#define I2C_IC_STATUS_SLV_ACTIVITY_RESET _u(0x0) -#define I2C_IC_STATUS_SLV_ACTIVITY_BITS _u(0x00000040) -#define I2C_IC_STATUS_SLV_ACTIVITY_MSB _u(6) -#define I2C_IC_STATUS_SLV_ACTIVITY_LSB _u(6) -#define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE _u(0x0) +#define I2C_IC_STATUS_SLV_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_SLV_ACTIVITY_BITS _u(0x00000040) +#define I2C_IC_STATUS_SLV_ACTIVITY_MSB _u(6) +#define I2C_IC_STATUS_SLV_ACTIVITY_LSB _u(6) +#define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE _u(0x0) #define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_MST_ACTIVITY @@ -1650,12 +1724,12 @@ // Reset value: 0x0 // 0x0 -> Master is idle // 0x1 -> Master not idle -#define I2C_IC_STATUS_MST_ACTIVITY_RESET _u(0x0) -#define I2C_IC_STATUS_MST_ACTIVITY_BITS _u(0x00000020) -#define I2C_IC_STATUS_MST_ACTIVITY_MSB _u(5) -#define I2C_IC_STATUS_MST_ACTIVITY_LSB _u(5) -#define I2C_IC_STATUS_MST_ACTIVITY_ACCESS "RO" -#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE _u(0x0) +#define I2C_IC_STATUS_MST_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_MST_ACTIVITY_BITS _u(0x00000020) +#define I2C_IC_STATUS_MST_ACTIVITY_MSB _u(5) +#define I2C_IC_STATUS_MST_ACTIVITY_LSB _u(5) +#define I2C_IC_STATUS_MST_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE _u(0x0) #define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_RFF @@ -1666,13 +1740,13 @@ // 0x0 // 0x0 -> Rx FIFO not full // 0x1 -> Rx FIFO is full -#define I2C_IC_STATUS_RFF_RESET _u(0x0) -#define I2C_IC_STATUS_RFF_BITS _u(0x00000010) -#define I2C_IC_STATUS_RFF_MSB _u(4) -#define I2C_IC_STATUS_RFF_LSB _u(4) -#define I2C_IC_STATUS_RFF_ACCESS "RO" +#define I2C_IC_STATUS_RFF_RESET _u(0x0) +#define I2C_IC_STATUS_RFF_BITS _u(0x00000010) +#define I2C_IC_STATUS_RFF_MSB _u(4) +#define I2C_IC_STATUS_RFF_LSB _u(4) +#define I2C_IC_STATUS_RFF_ACCESS "RO" #define I2C_IC_STATUS_RFF_VALUE_NOT_FULL _u(0x0) -#define I2C_IC_STATUS_RFF_VALUE_FULL _u(0x1) +#define I2C_IC_STATUS_RFF_VALUE_FULL _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_RFNE // Description : Receive FIFO Not Empty. This bit is set when the receive FIFO @@ -1681,12 +1755,12 @@ // not empty Reset value: 0x0 // 0x0 -> Rx FIFO is empty // 0x1 -> Rx FIFO not empty -#define I2C_IC_STATUS_RFNE_RESET _u(0x0) -#define I2C_IC_STATUS_RFNE_BITS _u(0x00000008) -#define I2C_IC_STATUS_RFNE_MSB _u(3) -#define I2C_IC_STATUS_RFNE_LSB _u(3) -#define I2C_IC_STATUS_RFNE_ACCESS "RO" -#define I2C_IC_STATUS_RFNE_VALUE_EMPTY _u(0x0) +#define I2C_IC_STATUS_RFNE_RESET _u(0x0) +#define I2C_IC_STATUS_RFNE_BITS _u(0x00000008) +#define I2C_IC_STATUS_RFNE_MSB _u(3) +#define I2C_IC_STATUS_RFNE_LSB _u(3) +#define I2C_IC_STATUS_RFNE_ACCESS "RO" +#define I2C_IC_STATUS_RFNE_VALUE_EMPTY _u(0x0) #define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_TFE @@ -1697,13 +1771,13 @@ // Transmit FIFO is empty Reset value: 0x1 // 0x0 -> Tx FIFO not empty // 0x1 -> Tx FIFO is empty -#define I2C_IC_STATUS_TFE_RESET _u(0x1) -#define I2C_IC_STATUS_TFE_BITS _u(0x00000004) -#define I2C_IC_STATUS_TFE_MSB _u(2) -#define I2C_IC_STATUS_TFE_LSB _u(2) -#define I2C_IC_STATUS_TFE_ACCESS "RO" +#define I2C_IC_STATUS_TFE_RESET _u(0x1) +#define I2C_IC_STATUS_TFE_BITS _u(0x00000004) +#define I2C_IC_STATUS_TFE_MSB _u(2) +#define I2C_IC_STATUS_TFE_LSB _u(2) +#define I2C_IC_STATUS_TFE_ACCESS "RO" #define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY _u(0x0) -#define I2C_IC_STATUS_TFE_VALUE_EMPTY _u(0x1) +#define I2C_IC_STATUS_TFE_VALUE_EMPTY _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_TFNF // Description : Transmit FIFO Not Full. Set when the transmit FIFO contains one @@ -1712,25 +1786,25 @@ // value: 0x1 // 0x0 -> Tx FIFO is full // 0x1 -> Tx FIFO not full -#define I2C_IC_STATUS_TFNF_RESET _u(0x1) -#define I2C_IC_STATUS_TFNF_BITS _u(0x00000002) -#define I2C_IC_STATUS_TFNF_MSB _u(1) -#define I2C_IC_STATUS_TFNF_LSB _u(1) -#define I2C_IC_STATUS_TFNF_ACCESS "RO" -#define I2C_IC_STATUS_TFNF_VALUE_FULL _u(0x0) +#define I2C_IC_STATUS_TFNF_RESET _u(0x1) +#define I2C_IC_STATUS_TFNF_BITS _u(0x00000002) +#define I2C_IC_STATUS_TFNF_MSB _u(1) +#define I2C_IC_STATUS_TFNF_LSB _u(1) +#define I2C_IC_STATUS_TFNF_ACCESS "RO" +#define I2C_IC_STATUS_TFNF_VALUE_FULL _u(0x0) #define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_STATUS_ACTIVITY // Description : I2C Activity Status. Reset value: 0x0 // 0x0 -> I2C is idle // 0x1 -> I2C is active -#define I2C_IC_STATUS_ACTIVITY_RESET _u(0x0) -#define I2C_IC_STATUS_ACTIVITY_BITS _u(0x00000001) -#define I2C_IC_STATUS_ACTIVITY_MSB _u(0) -#define I2C_IC_STATUS_ACTIVITY_LSB _u(0) -#define I2C_IC_STATUS_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_ACTIVITY_BITS _u(0x00000001) +#define I2C_IC_STATUS_ACTIVITY_MSB _u(0) +#define I2C_IC_STATUS_ACTIVITY_LSB _u(0) +#define I2C_IC_STATUS_ACTIVITY_ACCESS "RO" #define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE _u(0x1) +#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_TXFLR // Description : I2C Transmit FIFO Level Register This register contains the @@ -1870,12 +1944,12 @@ // Role of DW_apb_i2c: Master-Transmitter // 0x0 -> Transfer abort detected by master- scenario not present // 0x1 -> Transfer abort detected by master -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS _u(0x00010000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB _u(16) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB _u(16) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS _u(0x00010000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB _u(16) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB _u(16) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX @@ -1886,15 +1960,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave trying to transmit to remote master in read mode- -// scenario not present +// 0x0 -> Slave trying to transmit to remote master in read mode- scenario not present // 0x1 -> Slave trying to transmit to remote master in read mode -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB _u(15) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB _u(15) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB _u(15) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB _u(15) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST @@ -1910,15 +1983,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave lost arbitration to remote master- scenario not -// present +// 0x0 -> Slave lost arbitration to remote master- scenario not present // 0x1 -> Slave lost arbitration to remote master -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS _u(0x00004000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB _u(14) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB _u(14) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS _u(0x00004000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB _u(14) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB _u(14) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO @@ -1929,16 +2001,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Slave-Transmitter -// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read -// command- scenario not present -// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read -// command -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB _u(13) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID _u(0x0) +// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read command- scenario not present +// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read command +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB _u(13) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ARB_LOST @@ -1949,15 +2019,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter -// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario -// not present +// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario not present // 0x1 -> Master or Slave-Transmitter lost arbitration -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB _u(12) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB _u(12) -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB _u(12) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB _u(12) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS @@ -1967,15 +2036,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> User initiating master operation when MASTER disabled- -// scenario not present +// 0x0 -> User initiating master operation when MASTER disabled- scenario not present // 0x1 -> User initiating master operation when MASTER disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB _u(11) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB _u(11) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB _u(11) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB _u(11) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT @@ -1986,16 +2054,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Receiver -// 0x0 -> Master not trying to read in 10Bit addressing mode when -// RESTART disabled -// 0x1 -> Master trying to read in 10Bit addressing mode when -// RESTART disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB _u(10) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID _u(0x0) +// 0x0 -> Master not trying to read in 10Bit addressing mode when RESTART disabled +// 0x1 -> Master trying to read in 10Bit addressing mode when RESTART disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB _u(10) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT @@ -2014,15 +2080,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master -// 0x0 -> User trying to send START byte when RESTART disabled- -// scenario not present +// 0x0 -> User trying to send START byte when RESTART disabled- scenario not present // 0x1 -> User trying to send START byte when RESTART disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB _u(9) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB _u(9) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB _u(9) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB _u(9) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT @@ -2033,16 +2098,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver -// 0x0 -> User trying to switch Master to HS mode when RESTART -// disabled- scenario not present -// 0x1 -> User trying to switch Master to HS mode when RESTART -// disabled -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB _u(8) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB _u(8) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID _u(0x0) +// 0x0 -> User trying to switch Master to HS mode when RESTART disabled- scenario not present +// 0x1 -> User trying to switch Master to HS mode when RESTART disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB _u(8) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB _u(8) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET @@ -2054,12 +2117,12 @@ // Role of DW_apb_i2c: Master // 0x0 -> ACK detected for START byte- scenario not present // 0x1 -> ACK detected for START byte -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS _u(0x00000080) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB _u(7) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB _u(7) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS _u(0x00000080) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB _u(7) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB _u(7) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET @@ -2071,12 +2134,12 @@ // Role of DW_apb_i2c: Master // 0x0 -> HS Master code ACKed in HS Mode- scenario not present // 0x1 -> HS Master code ACKed in HS Mode -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS _u(0x00000040) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB _u(6) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB _u(6) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS _u(0x00000040) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB _u(6) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB _u(6) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ @@ -2090,12 +2153,12 @@ // Role of DW_apb_i2c: Master-Transmitter // 0x0 -> GCALL is followed by read from bus-scenario not present // 0x1 -> GCALL is followed by read from bus -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS _u(0x00000020) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB _u(5) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB _u(5) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS _u(0x00000020) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB _u(5) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB _u(5) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK @@ -2108,12 +2171,12 @@ // Role of DW_apb_i2c: Master-Transmitter // 0x0 -> GCALL not ACKed by any slave-scenario not present // 0x1 -> GCALL not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS _u(0x00000010) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB _u(4) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB _u(4) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS _u(0x00000010) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB _u(4) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB _u(4) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK @@ -2125,15 +2188,14 @@ // Reset value: 0x0 // // Role of DW_apb_i2c: Master-Transmitter -// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario -// not present +// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario not present // 0x1 -> Transmitted data not ACKed by addressed slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB _u(3) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB _u(3) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS "RO" -#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB _u(3) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB _u(3) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID _u(0x0) #define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK @@ -2146,13 +2208,13 @@ // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver // 0x0 -> This abort is not generated // 0x1 -> Byte 2 of 10Bit Address not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS _u(0x00000004) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB _u(2) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB _u(2) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS _u(0x00000004) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB _u(2) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB _u(2) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS "RO" #define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE _u(0x1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK // Description : This field indicates that the Master is in 10-bit address mode @@ -2164,13 +2226,13 @@ // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver // 0x0 -> This abort is not generated // 0x1 -> Byte 1 of 10Bit Address not ACKed by any slave -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS _u(0x00000002) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB _u(1) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB _u(1) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS _u(0x00000002) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB _u(1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB _u(1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS "RO" #define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE _u(0x1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK // Description : This field indicates that the Master is in 7-bit addressing @@ -2180,15 +2242,14 @@ // // Role of DW_apb_i2c: Master-Transmitter or Master-Receiver // 0x0 -> This abort is not generated -// 0x1 -> This abort is generated because of NOACK for 7-bit -// address -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS _u(0x00000001) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB _u(0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB _u(0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS "RO" +// 0x1 -> This abort is generated because of NOACK for 7-bit address +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS _u(0x00000001) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB _u(0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB _u(0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS "RO" #define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE _u(0x0) -#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE _u(0x1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE _u(0x1) // ============================================================================= // Register : I2C_IC_SLV_DATA_NACK_ONLY // Description : Generate Slave Data NACK Register @@ -2222,13 +2283,13 @@ // value: 0x0 // 0x0 -> Slave receiver generates NACK normally // 0x1 -> Slave receiver generates NACK upon data reception only -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET _u(0x0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS _u(0x00000001) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB _u(0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB _u(0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS "RW" +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET _u(0x0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS _u(0x00000001) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB _u(0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB _u(0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS "RW" #define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED _u(0x0) -#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED _u(0x1) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_DMA_CR // Description : DMA Control Register @@ -2245,26 +2306,26 @@ // FIFO DMA channel. Reset value: 0x0 // 0x0 -> transmit FIFO DMA channel disabled // 0x1 -> Transmit FIFO DMA channel enabled -#define I2C_IC_DMA_CR_TDMAE_RESET _u(0x0) -#define I2C_IC_DMA_CR_TDMAE_BITS _u(0x00000002) -#define I2C_IC_DMA_CR_TDMAE_MSB _u(1) -#define I2C_IC_DMA_CR_TDMAE_LSB _u(1) -#define I2C_IC_DMA_CR_TDMAE_ACCESS "RW" +#define I2C_IC_DMA_CR_TDMAE_RESET _u(0x0) +#define I2C_IC_DMA_CR_TDMAE_BITS _u(0x00000002) +#define I2C_IC_DMA_CR_TDMAE_MSB _u(1) +#define I2C_IC_DMA_CR_TDMAE_LSB _u(1) +#define I2C_IC_DMA_CR_TDMAE_ACCESS "RW" #define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED _u(0x0) -#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED _u(0x1) +#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_DMA_CR_RDMAE // Description : Receive DMA Enable. This bit enables/disables the receive FIFO // DMA channel. Reset value: 0x0 // 0x0 -> Receive FIFO DMA channel disabled // 0x1 -> Receive FIFO DMA channel enabled -#define I2C_IC_DMA_CR_RDMAE_RESET _u(0x0) -#define I2C_IC_DMA_CR_RDMAE_BITS _u(0x00000001) -#define I2C_IC_DMA_CR_RDMAE_MSB _u(0) -#define I2C_IC_DMA_CR_RDMAE_LSB _u(0) -#define I2C_IC_DMA_CR_RDMAE_ACCESS "RW" +#define I2C_IC_DMA_CR_RDMAE_RESET _u(0x0) +#define I2C_IC_DMA_CR_RDMAE_BITS _u(0x00000001) +#define I2C_IC_DMA_CR_RDMAE_MSB _u(0) +#define I2C_IC_DMA_CR_RDMAE_LSB _u(0) +#define I2C_IC_DMA_CR_RDMAE_ACCESS "RW" #define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED _u(0x0) -#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED _u(0x1) +#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_DMA_TDLR // Description : DMA Transmit Data Level Register @@ -2360,13 +2421,13 @@ // ic_data_oe). // 0x0 -> Generate NACK for a General Call // 0x1 -> Generate ACK for a General Call -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET _u(0x1) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS _u(0x00000001) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB _u(0) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB _u(0) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS "RW" +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET _u(0x1) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS _u(0x00000001) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB _u(0) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB _u(0) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS "RW" #define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED _u(0x0) -#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED _u(0x1) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_ENABLE_STATUS // Description : I2C Enable Status Register @@ -2389,14 +2450,14 @@ #define I2C_IC_ENABLE_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST -// Description : Slave Received Data Lost. This bit indicates if a -// Slave-Receiver operation has been aborted with at least one -// data byte received from an I2C transfer due to the setting bit -// 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is -// deemed to have been actively engaged in an aborted I2C transfer -// (with matching address) and the data phase of the I2C transfer -// has been entered, even though a data byte has been responded -// with a NACK. +// Description : Slave Received Data Lost. This bit indicates if a Slave- +// Receiver operation has been aborted with at least one data byte +// received from an I2C transfer due to the setting bit 0 of +// IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to +// have been actively engaged in an aborted I2C transfer (with +// matching address) and the data phase of the I2C transfer has +// been entered, even though a data byte has been responded with a +// NACK. // // Note: If the remote I2C master terminates the transfer with a // STOP condition before the DW_apb_i2c has a chance to NACK a @@ -2404,8 +2465,8 @@ // also set to 1. // // When read as 0, DW_apb_i2c is deemed to have been disabled -// without being actively involved in the data phase of a -// Slave-Receiver transfer. +// without being actively involved in the data phase of a Slave- +// Receiver transfer. // // Note: The CPU can safely read this bit when IC_EN (bit 0) is // read as 0. @@ -2413,13 +2474,13 @@ // Reset value: 0x0 // 0x0 -> Slave RX Data is not lost // 0x1 -> Slave RX Data is lost -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS _u(0x00000004) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB _u(2) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB _u(2) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS _u(0x00000004) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB _u(2) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB _u(2) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS "RO" #define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE _u(0x1) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY // Description : Slave Disabled While Busy (Transmit, Receive). This bit @@ -2428,8 +2489,8 @@ // 1 to 0. This bit is set when the CPU writes a 0 to the // IC_ENABLE register while: // -// (a) DW_apb_i2c is receiving the address byte of the -// Slave-Transmitter operation from a remote master; +// (a) DW_apb_i2c is receiving the address byte of the Slave- +// Transmitter operation from a remote master; // // OR, // @@ -2456,13 +2517,13 @@ // Reset value: 0x0 // 0x0 -> Slave is disabled when it is idle // 0x1 -> Slave is disabled when it is active -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS _u(0x00000002) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB _u(1) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB _u(1) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS _u(0x00000002) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB _u(1) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB _u(1) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS "RO" #define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE _u(0x0) -#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE _u(0x1) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE _u(0x1) // ----------------------------------------------------------------------------- // Field : I2C_IC_ENABLE_STATUS_IC_EN // Description : ic_en Status. This bit always reflects the value driven on the @@ -2475,13 +2536,13 @@ // Reset value: 0x0 // 0x0 -> I2C disabled // 0x1 -> I2C enabled -#define I2C_IC_ENABLE_STATUS_IC_EN_RESET _u(0x0) -#define I2C_IC_ENABLE_STATUS_IC_EN_BITS _u(0x00000001) -#define I2C_IC_ENABLE_STATUS_IC_EN_MSB _u(0) -#define I2C_IC_ENABLE_STATUS_IC_EN_LSB _u(0) -#define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_IC_EN_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_IC_EN_BITS _u(0x00000001) +#define I2C_IC_ENABLE_STATUS_IC_EN_MSB _u(0) +#define I2C_IC_ENABLE_STATUS_IC_EN_LSB _u(0) +#define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS "RO" #define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED _u(0x0) -#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED _u(0x1) +#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED _u(0x1) // ============================================================================= // Register : I2C_IC_FS_SPKLEN // Description : I2C SS, FS or FM+ spike suppression limit @@ -2613,7 +2674,6 @@ #define I2C_IC_COMP_VERSION_RESET _u(0x3230312a) // ----------------------------------------------------------------------------- // Field : I2C_IC_COMP_VERSION_IC_COMP_VERSION -// Description : None #define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET _u(0x3230312a) #define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS _u(0xffffffff) #define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB _u(31) @@ -2636,4 +2696,5 @@ #define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB _u(0) #define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_I2C_DEFINED +#endif // _HARDWARE_REGS_I2C_H + diff --git a/lib/pico-sdk/rp2040/hardware/regs/intctrl.h b/lib/pico-sdk/rp2040/hardware/regs/intctrl.h new file mode 100644 index 000000000000..3190b413d0e0 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/regs/intctrl.h @@ -0,0 +1,106 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _INTCTRL_H +#define _INTCTRL_H + +/** + * \file rp2040/intctrl.h + */ + +#ifdef __ASSEMBLER__ +#define TIMER_IRQ_0 0 +#define TIMER_IRQ_1 1 +#define TIMER_IRQ_2 2 +#define TIMER_IRQ_3 3 +#define PWM_IRQ_WRAP 4 +#define USBCTRL_IRQ 5 +#define XIP_IRQ 6 +#define PIO0_IRQ_0 7 +#define PIO0_IRQ_1 8 +#define PIO1_IRQ_0 9 +#define PIO1_IRQ_1 10 +#define DMA_IRQ_0 11 +#define DMA_IRQ_1 12 +#define IO_IRQ_BANK0 13 +#define IO_IRQ_QSPI 14 +#define SIO_IRQ_PROC0 15 +#define SIO_IRQ_PROC1 16 +#define CLOCKS_IRQ 17 +#define SPI0_IRQ 18 +#define SPI1_IRQ 19 +#define UART0_IRQ 20 +#define UART1_IRQ 21 +#define ADC_IRQ_FIFO 22 +#define I2C0_IRQ 23 +#define I2C1_IRQ 24 +#define RTC_IRQ 25 +#else +/** + * \brief Interrupt numbers on RP2040 (used as typedef \ref irq_num_t) + * \ingroup hardware_irq + */ +typedef enum irq_num_rp2040 { + TIMER_IRQ_0 = 0, ///< Select TIMER's IRQ 0 output + TIMER_IRQ_1 = 1, ///< Select TIMER's IRQ 1 output + TIMER_IRQ_2 = 2, ///< Select TIMER's IRQ 2 output + TIMER_IRQ_3 = 3, ///< Select TIMER's IRQ 3 output + PWM_IRQ_WRAP = 4, ///< Select PWM's IRQ_WRAP output + USBCTRL_IRQ = 5, ///< Select USBCTRL's IRQ output + XIP_IRQ = 6, ///< Select XIP's IRQ output + PIO0_IRQ_0 = 7, ///< Select PIO0's IRQ 0 output + PIO0_IRQ_1 = 8, ///< Select PIO0's IRQ 1 output + PIO1_IRQ_0 = 9, ///< Select PIO1's IRQ 0 output + PIO1_IRQ_1 = 10, ///< Select PIO1's IRQ 1 output + DMA_IRQ_0 = 11, ///< Select DMA's IRQ 0 output + DMA_IRQ_1 = 12, ///< Select DMA's IRQ 1 output + IO_IRQ_BANK0 = 13, ///< Select IO_BANK0's IRQ output + IO_IRQ_QSPI = 14, ///< Select IO_QSPI's IRQ output + SIO_IRQ_PROC0 = 15, ///< Select SIO_PROC0's IRQ output + SIO_IRQ_PROC1 = 16, ///< Select SIO_PROC1's IRQ output + CLOCKS_IRQ = 17, ///< Select CLOCKS's IRQ output + SPI0_IRQ = 18, ///< Select SPI0's IRQ output + SPI1_IRQ = 19, ///< Select SPI1's IRQ output + UART0_IRQ = 20, ///< Select UART0's IRQ output + UART1_IRQ = 21, ///< Select UART1's IRQ output + ADC_IRQ_FIFO = 22, ///< Select ADC's IRQ_FIFO output + I2C0_IRQ = 23, ///< Select I2C0's IRQ output + I2C1_IRQ = 24, ///< Select I2C1's IRQ output + RTC_IRQ = 25, ///< Select RTC's IRQ output + IRQ_COUNT +} irq_num_t; +#endif + +#define isr_timer_0 isr_irq0 +#define isr_timer_1 isr_irq1 +#define isr_timer_2 isr_irq2 +#define isr_timer_3 isr_irq3 +#define isr_pwm_wrap isr_irq4 +#define isr_usbctrl isr_irq5 +#define isr_xip isr_irq6 +#define isr_pio0_0 isr_irq7 +#define isr_pio0_1 isr_irq8 +#define isr_pio1_0 isr_irq9 +#define isr_pio1_1 isr_irq10 +#define isr_dma_0 isr_irq11 +#define isr_dma_1 isr_irq12 +#define isr_io_bank0 isr_irq13 +#define isr_io_qspi isr_irq14 +#define isr_sio_proc0 isr_irq15 +#define isr_sio_proc1 isr_irq16 +#define isr_clocks isr_irq17 +#define isr_spi0 isr_irq18 +#define isr_spi1 isr_irq19 +#define isr_uart0 isr_irq20 +#define isr_uart1 isr_irq21 +#define isr_adc_fifo isr_irq22 +#define isr_i2c0 isr_irq23 +#define isr_i2c1 isr_irq24 +#define isr_rtc isr_irq25 + +#endif // _INTCTRL_H + diff --git a/lib/rp2040/hardware/regs/io_bank0.h b/lib/pico-sdk/rp2040/hardware/regs/io_bank0.h similarity index 86% rename from lib/rp2040/hardware/regs/io_bank0.h rename to lib/pico-sdk/rp2040/hardware/regs/io_bank0.h index 26f139e36b39..c0ebaf9f903b 100644 --- a/lib/rp2040/hardware/regs/io_bank0.h +++ b/lib/pico-sdk/rp2040/hardware/regs/io_bank0.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : IO_BANK0 // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_IO_BANK0_DEFINED -#define HARDWARE_REGS_IO_BANK0_DEFINED +#ifndef _HARDWARE_REGS_IO_BANK0_H +#define _HARDWARE_REGS_IO_BANK0_H // ============================================================================= // Register : IO_BANK0_GPIO0_STATUS // Description : GPIO status @@ -91,67 +92,64 @@ #define IO_BANK0_GPIO0_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO0_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -166,21 +164,21 @@ // 0x07 -> pio1_0 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 _u(0x05) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 _u(0x05) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07) #define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO1_STATUS // Description : GPIO status @@ -261,67 +259,64 @@ #define IO_BANK0_GPIO1_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO1_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -336,21 +331,21 @@ // 0x07 -> pio1_1 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 _u(0x05) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 _u(0x05) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07) #define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO2_STATUS // Description : GPIO status @@ -431,67 +426,64 @@ #define IO_BANK0_GPIO2_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO2_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -506,21 +498,21 @@ // 0x07 -> pio1_2 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 _u(0x05) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 _u(0x05) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07) #define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO3_STATUS // Description : GPIO status @@ -601,67 +593,64 @@ #define IO_BANK0_GPIO3_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO3_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -676,21 +665,21 @@ // 0x07 -> pio1_3 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 _u(0x05) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 _u(0x05) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07) #define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO4_STATUS // Description : GPIO status @@ -771,67 +760,64 @@ #define IO_BANK0_GPIO4_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO4_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -845,20 +831,20 @@ // 0x07 -> pio1_4 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 _u(0x05) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 _u(0x05) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07) #define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO5_STATUS // Description : GPIO status @@ -939,67 +925,64 @@ #define IO_BANK0_GPIO5_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO5_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1013,20 +996,20 @@ // 0x07 -> pio1_5 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 _u(0x05) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 _u(0x05) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07) #define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO6_STATUS // Description : GPIO status @@ -1107,67 +1090,64 @@ #define IO_BANK0_GPIO6_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO6_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1182,21 +1162,21 @@ // 0x08 -> usb_muxing_extphy_softcon // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 _u(0x05) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON _u(0x08) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 _u(0x05) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON _u(0x08) #define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO7_STATUS // Description : GPIO status @@ -1277,67 +1257,64 @@ #define IO_BANK0_GPIO7_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO7_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1352,21 +1329,21 @@ // 0x08 -> usb_muxing_extphy_oe_n // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 _u(0x05) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 _u(0x05) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07) #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N _u(0x08) #define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO8_STATUS // Description : GPIO status @@ -1447,67 +1424,64 @@ #define IO_BANK0_GPIO8_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO8_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1522,21 +1496,21 @@ // 0x08 -> usb_muxing_extphy_rcv // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 _u(0x05) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 _u(0x05) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07) #define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV _u(0x08) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO9_STATUS // Description : GPIO status @@ -1617,67 +1591,64 @@ #define IO_BANK0_GPIO9_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO9_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1692,21 +1663,21 @@ // 0x08 -> usb_muxing_extphy_vp // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 _u(0x05) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP _u(0x08) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 _u(0x05) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP _u(0x08) #define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO10_STATUS // Description : GPIO status @@ -1787,67 +1758,64 @@ #define IO_BANK0_GPIO10_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO10_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -1862,21 +1830,21 @@ // 0x08 -> usb_muxing_extphy_vm // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 _u(0x05) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM _u(0x08) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 _u(0x05) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM _u(0x08) #define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO11_STATUS // Description : GPIO status @@ -1957,67 +1925,64 @@ #define IO_BANK0_GPIO11_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO11_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2032,21 +1997,21 @@ // 0x08 -> usb_muxing_extphy_suspnd // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 _u(0x05) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 _u(0x05) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07) #define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND _u(0x08) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO12_STATUS // Description : GPIO status @@ -2127,67 +2092,64 @@ #define IO_BANK0_GPIO12_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO12_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2202,21 +2164,21 @@ // 0x08 -> usb_muxing_extphy_speed // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 _u(0x05) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED _u(0x08) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 _u(0x05) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED _u(0x08) #define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO13_STATUS // Description : GPIO status @@ -2297,67 +2259,64 @@ #define IO_BANK0_GPIO13_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO13_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2372,21 +2331,21 @@ // 0x08 -> usb_muxing_extphy_vpo // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 _u(0x05) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO _u(0x08) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 _u(0x05) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO _u(0x08) #define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO14_STATUS // Description : GPIO status @@ -2467,67 +2426,64 @@ #define IO_BANK0_GPIO14_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO14_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2542,21 +2498,21 @@ // 0x08 -> usb_muxing_extphy_vmo // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 _u(0x05) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 _u(0x05) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07) #define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO _u(0x08) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO15_STATUS // Description : GPIO status @@ -2637,67 +2593,64 @@ #define IO_BANK0_GPIO15_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO15_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2712,21 +2665,21 @@ // 0x08 -> usb_muxing_digital_dp // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 _u(0x05) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP _u(0x08) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 _u(0x05) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP _u(0x08) #define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO16_STATUS // Description : GPIO status @@ -2807,67 +2760,64 @@ #define IO_BANK0_GPIO16_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO16_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -2882,21 +2832,21 @@ // 0x08 -> usb_muxing_digital_dm // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 _u(0x05) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM _u(0x08) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 _u(0x05) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM _u(0x08) #define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO17_STATUS // Description : GPIO status @@ -2977,67 +2927,64 @@ #define IO_BANK0_GPIO17_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO17_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3051,20 +2998,20 @@ // 0x07 -> pio1_17 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 _u(0x05) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 _u(0x05) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07) #define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO18_STATUS // Description : GPIO status @@ -3145,67 +3092,64 @@ #define IO_BANK0_GPIO18_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO18_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3219,20 +3163,20 @@ // 0x07 -> pio1_18 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 _u(0x05) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 _u(0x05) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07) #define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO19_STATUS // Description : GPIO status @@ -3313,67 +3257,64 @@ #define IO_BANK0_GPIO19_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO19_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3387,20 +3328,20 @@ // 0x07 -> pio1_19 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 _u(0x05) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 _u(0x05) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07) #define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO20_STATUS // Description : GPIO status @@ -3481,67 +3422,64 @@ #define IO_BANK0_GPIO20_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO20_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3556,21 +3494,21 @@ // 0x08 -> clocks_gpin_0 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 _u(0x05) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x08) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 _u(0x05) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x08) #define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO21_STATUS // Description : GPIO status @@ -3651,67 +3589,64 @@ #define IO_BANK0_GPIO21_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO21_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3726,21 +3661,21 @@ // 0x08 -> clocks_gpout_0 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 _u(0x05) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x08) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 _u(0x05) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x08) #define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO22_STATUS // Description : GPIO status @@ -3821,67 +3756,64 @@ #define IO_BANK0_GPIO22_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO22_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -3896,21 +3828,21 @@ // 0x08 -> clocks_gpin_1 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 _u(0x05) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x08) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 _u(0x05) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x08) #define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO23_STATUS // Description : GPIO status @@ -3991,67 +3923,64 @@ #define IO_BANK0_GPIO23_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO23_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4066,21 +3995,21 @@ // 0x08 -> clocks_gpout_1 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 _u(0x05) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x08) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 _u(0x05) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x08) #define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO24_STATUS // Description : GPIO status @@ -4161,67 +4090,64 @@ #define IO_BANK0_GPIO24_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO24_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO24_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO24_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO24_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO24_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO24_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4236,21 +4162,21 @@ // 0x08 -> clocks_gpout_2 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 _u(0x05) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _u(0x08) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 _u(0x05) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _u(0x08) #define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO25_STATUS // Description : GPIO status @@ -4331,67 +4257,64 @@ #define IO_BANK0_GPIO25_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO25_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO25_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO25_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO25_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO25_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO25_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4406,21 +4329,21 @@ // 0x08 -> clocks_gpout_3 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 _u(0x05) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _u(0x08) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 _u(0x05) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _u(0x08) #define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO26_STATUS // Description : GPIO status @@ -4501,67 +4424,64 @@ #define IO_BANK0_GPIO26_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO26_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO26_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO26_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO26_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO26_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO26_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4575,20 +4495,20 @@ // 0x07 -> pio1_26 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 _u(0x05) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 _u(0x05) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07) #define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO27_STATUS // Description : GPIO status @@ -4669,67 +4589,64 @@ #define IO_BANK0_GPIO27_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO27_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO27_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO27_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO27_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO27_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO27_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4743,20 +4660,20 @@ // 0x07 -> pio1_27 // 0x09 -> usb_muxing_overcurr_detect // 0x1f -> null -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 _u(0x05) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 _u(0x05) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07) #define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09) -#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO28_STATUS // Description : GPIO status @@ -4837,67 +4754,64 @@ #define IO_BANK0_GPIO28_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO28_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO28_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO28_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO28_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO28_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO28_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -4911,20 +4825,20 @@ // 0x07 -> pio1_28 // 0x09 -> usb_muxing_vbus_detect // 0x1f -> null -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 _u(0x05) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 _u(0x05) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07) #define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09) -#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_GPIO29_STATUS // Description : GPIO status @@ -5005,67 +4919,64 @@ #define IO_BANK0_GPIO29_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _u(29) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _u(28) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW" #define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_BANK0_GPIO29_CTRL_INOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_INOVER_BITS _u(0x00030000) -#define IO_BANK0_GPIO29_CTRL_INOVER_MSB _u(17) -#define IO_BANK0_GPIO29_CTRL_INOVER_LSB _u(16) -#define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO29_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO29_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW" #define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _u(13) -#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _u(12) -#define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _u(13) +#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _u(12) +#define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _u(9) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _u(8) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _u(9) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _u(8) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW" #define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_BANK0_GPIO29_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -5079,20 +4990,20 @@ // 0x07 -> pio1_29 // 0x09 -> usb_muxing_vbus_en // 0x1f -> null -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _u(4) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _u(0) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW" -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 _u(0x05) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 _u(0x05) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07) #define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09) -#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_BANK0_INTR0 // Description : Raw Interrupts @@ -5101,7 +5012,6 @@ #define IO_BANK0_INTR0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -5109,7 +5019,6 @@ #define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB _u(30) @@ -5117,7 +5026,6 @@ #define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -5125,7 +5033,6 @@ #define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -5133,7 +5040,6 @@ #define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -5141,7 +5047,6 @@ #define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB _u(26) @@ -5149,7 +5054,6 @@ #define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -5157,7 +5061,6 @@ #define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -5165,7 +5068,6 @@ #define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -5173,7 +5075,6 @@ #define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB _u(22) @@ -5181,7 +5082,6 @@ #define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -5189,7 +5089,6 @@ #define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -5197,7 +5096,6 @@ #define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -5205,7 +5103,6 @@ #define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB _u(18) @@ -5213,7 +5110,6 @@ #define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -5221,7 +5117,6 @@ #define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -5229,7 +5124,6 @@ #define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -5237,7 +5131,6 @@ #define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB _u(14) @@ -5245,7 +5138,6 @@ #define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -5253,7 +5145,6 @@ #define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -5261,7 +5152,6 @@ #define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -5269,7 +5159,6 @@ #define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB _u(10) @@ -5277,7 +5166,6 @@ #define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -5285,7 +5173,6 @@ #define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -5293,7 +5180,6 @@ #define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -5301,7 +5187,6 @@ #define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB _u(6) @@ -5309,7 +5194,6 @@ #define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -5317,7 +5201,6 @@ #define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -5325,7 +5208,6 @@ #define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -5333,7 +5215,6 @@ #define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB _u(2) @@ -5341,7 +5222,6 @@ #define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -5349,7 +5229,6 @@ #define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -5363,7 +5242,6 @@ #define IO_BANK0_INTR1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -5371,7 +5249,6 @@ #define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB _u(30) @@ -5379,7 +5256,6 @@ #define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -5387,7 +5263,6 @@ #define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -5395,7 +5270,6 @@ #define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -5403,7 +5277,6 @@ #define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB _u(26) @@ -5411,7 +5284,6 @@ #define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -5419,7 +5291,6 @@ #define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -5427,7 +5298,6 @@ #define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -5435,7 +5305,6 @@ #define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB _u(22) @@ -5443,7 +5312,6 @@ #define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -5451,7 +5319,6 @@ #define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -5459,7 +5326,6 @@ #define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -5467,7 +5333,6 @@ #define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB _u(18) @@ -5475,7 +5340,6 @@ #define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -5483,7 +5347,6 @@ #define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -5491,7 +5354,6 @@ #define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -5499,7 +5361,6 @@ #define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB _u(14) @@ -5507,7 +5368,6 @@ #define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -5515,7 +5375,6 @@ #define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -5523,7 +5382,6 @@ #define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -5531,7 +5389,6 @@ #define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB _u(10) @@ -5539,7 +5396,6 @@ #define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -5547,7 +5403,6 @@ #define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -5555,7 +5410,6 @@ #define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -5563,7 +5417,6 @@ #define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB _u(6) @@ -5571,7 +5424,6 @@ #define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -5579,7 +5431,6 @@ #define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -5587,7 +5438,6 @@ #define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -5595,7 +5445,6 @@ #define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB _u(2) @@ -5603,7 +5452,6 @@ #define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -5611,7 +5459,6 @@ #define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -5625,7 +5472,6 @@ #define IO_BANK0_INTR2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -5633,7 +5479,6 @@ #define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB _u(30) @@ -5641,7 +5486,6 @@ #define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -5649,7 +5493,6 @@ #define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -5657,7 +5500,6 @@ #define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -5665,7 +5507,6 @@ #define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB _u(26) @@ -5673,7 +5514,6 @@ #define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -5681,7 +5521,6 @@ #define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -5689,7 +5528,6 @@ #define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -5697,7 +5535,6 @@ #define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB _u(22) @@ -5705,7 +5542,6 @@ #define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -5713,7 +5549,6 @@ #define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -5721,7 +5556,6 @@ #define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -5729,7 +5563,6 @@ #define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB _u(18) @@ -5737,7 +5570,6 @@ #define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -5745,7 +5577,6 @@ #define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -5753,7 +5584,6 @@ #define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -5761,7 +5591,6 @@ #define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB _u(14) @@ -5769,7 +5598,6 @@ #define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -5777,7 +5605,6 @@ #define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -5785,7 +5612,6 @@ #define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -5793,7 +5619,6 @@ #define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB _u(10) @@ -5801,7 +5626,6 @@ #define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -5809,7 +5633,6 @@ #define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -5817,7 +5640,6 @@ #define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -5825,7 +5647,6 @@ #define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB _u(6) @@ -5833,7 +5654,6 @@ #define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -5841,7 +5661,6 @@ #define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -5849,7 +5668,6 @@ #define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -5857,7 +5675,6 @@ #define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB _u(2) @@ -5865,7 +5682,6 @@ #define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -5873,7 +5689,6 @@ #define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -5887,7 +5702,6 @@ #define IO_BANK0_INTR3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -5895,7 +5709,6 @@ #define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB _u(22) @@ -5903,7 +5716,6 @@ #define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -5911,7 +5723,6 @@ #define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -5919,7 +5730,6 @@ #define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -5927,7 +5737,6 @@ #define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB _u(18) @@ -5935,7 +5744,6 @@ #define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -5943,7 +5751,6 @@ #define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -5951,7 +5758,6 @@ #define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -5959,7 +5765,6 @@ #define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB _u(14) @@ -5967,7 +5772,6 @@ #define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -5975,7 +5779,6 @@ #define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -5983,7 +5786,6 @@ #define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -5991,7 +5793,6 @@ #define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB _u(10) @@ -5999,7 +5800,6 @@ #define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -6007,7 +5807,6 @@ #define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -6015,7 +5814,6 @@ #define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -6023,7 +5821,6 @@ #define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB _u(6) @@ -6031,7 +5828,6 @@ #define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -6039,7 +5835,6 @@ #define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -6047,7 +5842,6 @@ #define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -6055,7 +5849,6 @@ #define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB _u(2) @@ -6063,7 +5856,6 @@ #define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -6071,7 +5863,6 @@ #define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_INTR3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -6085,7 +5876,6 @@ #define IO_BANK0_PROC0_INTE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -6093,7 +5883,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB _u(30) @@ -6101,7 +5890,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -6109,7 +5897,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -6117,7 +5904,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -6125,7 +5911,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB _u(26) @@ -6133,7 +5918,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -6141,7 +5925,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -6149,7 +5932,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -6157,7 +5939,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB _u(22) @@ -6165,7 +5946,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -6173,7 +5953,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -6181,7 +5960,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -6189,7 +5967,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB _u(18) @@ -6197,7 +5974,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -6205,7 +5981,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -6213,7 +5988,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -6221,7 +5995,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB _u(14) @@ -6229,7 +6002,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -6237,7 +6009,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -6245,7 +6016,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -6253,7 +6023,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB _u(10) @@ -6261,7 +6030,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -6269,7 +6037,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -6277,7 +6044,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -6285,7 +6051,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB _u(6) @@ -6293,7 +6058,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -6301,7 +6065,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -6309,7 +6072,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -6317,7 +6079,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB _u(2) @@ -6325,7 +6086,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -6333,7 +6093,6 @@ #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -6347,7 +6106,6 @@ #define IO_BANK0_PROC0_INTE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -6355,7 +6113,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB _u(30) @@ -6363,7 +6120,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -6371,7 +6127,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -6379,7 +6134,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -6387,7 +6141,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB _u(26) @@ -6395,7 +6148,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -6403,7 +6155,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -6411,7 +6162,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -6419,7 +6169,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB _u(22) @@ -6427,7 +6176,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -6435,7 +6183,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -6443,7 +6190,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -6451,7 +6197,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB _u(18) @@ -6459,7 +6204,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -6467,7 +6211,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -6475,7 +6218,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -6483,7 +6225,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB _u(14) @@ -6491,7 +6232,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -6499,7 +6239,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -6507,7 +6246,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -6515,7 +6253,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB _u(10) @@ -6523,7 +6260,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -6531,7 +6267,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -6539,7 +6274,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -6547,7 +6281,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB _u(6) @@ -6555,7 +6288,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -6563,7 +6295,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -6571,7 +6302,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -6579,7 +6309,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB _u(2) @@ -6587,7 +6316,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -6595,7 +6323,6 @@ #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -6609,7 +6336,6 @@ #define IO_BANK0_PROC0_INTE2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -6617,7 +6343,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB _u(30) @@ -6625,7 +6350,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -6633,7 +6357,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -6641,7 +6364,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -6649,7 +6371,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB _u(26) @@ -6657,7 +6378,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -6665,7 +6385,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -6673,7 +6392,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -6681,7 +6399,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB _u(22) @@ -6689,7 +6406,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -6697,7 +6413,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -6705,7 +6420,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -6713,7 +6427,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB _u(18) @@ -6721,7 +6434,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -6729,7 +6441,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -6737,7 +6448,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -6745,7 +6455,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB _u(14) @@ -6753,7 +6462,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -6761,7 +6469,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -6769,7 +6476,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -6777,7 +6483,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB _u(10) @@ -6785,7 +6490,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -6793,7 +6497,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -6801,7 +6504,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -6809,7 +6511,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB _u(6) @@ -6817,7 +6518,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -6825,7 +6525,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -6833,7 +6532,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -6841,7 +6539,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB _u(2) @@ -6849,7 +6546,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -6857,7 +6553,6 @@ #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -6871,7 +6566,6 @@ #define IO_BANK0_PROC0_INTE3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -6879,7 +6573,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB _u(22) @@ -6887,7 +6580,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -6895,7 +6587,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -6903,7 +6594,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -6911,7 +6601,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB _u(18) @@ -6919,7 +6608,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -6927,7 +6615,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -6935,7 +6622,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -6943,7 +6629,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB _u(14) @@ -6951,7 +6636,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -6959,7 +6643,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -6967,7 +6650,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -6975,7 +6657,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB _u(10) @@ -6983,7 +6664,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -6991,7 +6671,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -6999,7 +6678,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -7007,7 +6685,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB _u(6) @@ -7015,7 +6692,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -7023,7 +6699,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -7031,7 +6706,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -7039,7 +6713,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB _u(2) @@ -7047,7 +6720,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -7055,7 +6727,6 @@ #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -7069,7 +6740,6 @@ #define IO_BANK0_PROC0_INTF0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -7077,7 +6747,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB _u(30) @@ -7085,7 +6754,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -7093,7 +6761,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -7101,7 +6768,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -7109,7 +6775,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB _u(26) @@ -7117,7 +6782,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -7125,7 +6789,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -7133,7 +6796,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -7141,7 +6803,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB _u(22) @@ -7149,7 +6810,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -7157,7 +6817,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -7165,7 +6824,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -7173,7 +6831,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB _u(18) @@ -7181,7 +6838,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -7189,7 +6845,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -7197,7 +6852,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -7205,7 +6859,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB _u(14) @@ -7213,7 +6866,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -7221,7 +6873,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -7229,7 +6880,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -7237,7 +6887,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB _u(10) @@ -7245,7 +6894,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -7253,7 +6901,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -7261,7 +6908,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -7269,7 +6915,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB _u(6) @@ -7277,7 +6922,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -7285,7 +6929,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -7293,7 +6936,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -7301,7 +6943,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB _u(2) @@ -7309,7 +6950,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -7317,7 +6957,6 @@ #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -7331,7 +6970,6 @@ #define IO_BANK0_PROC0_INTF1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -7339,7 +6977,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB _u(30) @@ -7347,7 +6984,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -7355,7 +6991,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -7363,7 +6998,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -7371,7 +7005,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB _u(26) @@ -7379,7 +7012,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -7387,7 +7019,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -7395,7 +7026,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -7403,7 +7033,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB _u(22) @@ -7411,7 +7040,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -7419,7 +7047,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -7427,7 +7054,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -7435,7 +7061,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB _u(18) @@ -7443,7 +7068,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -7451,7 +7075,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -7459,7 +7082,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -7467,7 +7089,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB _u(14) @@ -7475,7 +7096,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -7483,7 +7103,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -7491,7 +7110,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -7499,7 +7117,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB _u(10) @@ -7507,7 +7124,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -7515,7 +7131,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -7523,7 +7138,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -7531,7 +7145,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB _u(6) @@ -7539,7 +7152,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -7547,7 +7159,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -7555,7 +7166,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -7563,7 +7173,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB _u(2) @@ -7571,7 +7180,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -7579,7 +7187,6 @@ #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -7593,7 +7200,6 @@ #define IO_BANK0_PROC0_INTF2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -7601,7 +7207,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB _u(30) @@ -7609,7 +7214,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -7617,7 +7221,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -7625,7 +7228,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -7633,7 +7235,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB _u(26) @@ -7641,7 +7242,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -7649,7 +7249,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -7657,7 +7256,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -7665,7 +7263,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB _u(22) @@ -7673,7 +7270,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -7681,7 +7277,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -7689,7 +7284,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -7697,7 +7291,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB _u(18) @@ -7705,7 +7298,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -7713,7 +7305,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -7721,7 +7312,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -7729,7 +7319,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB _u(14) @@ -7737,7 +7326,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -7745,7 +7333,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -7753,7 +7340,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -7761,7 +7347,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB _u(10) @@ -7769,7 +7354,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -7777,7 +7361,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -7785,7 +7368,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -7793,7 +7375,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB _u(6) @@ -7801,7 +7382,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -7809,7 +7389,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -7817,7 +7396,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -7825,7 +7403,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB _u(2) @@ -7833,7 +7410,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -7841,7 +7417,6 @@ #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -7855,7 +7430,6 @@ #define IO_BANK0_PROC0_INTF3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -7863,7 +7437,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB _u(22) @@ -7871,7 +7444,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -7879,7 +7451,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -7887,7 +7458,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -7895,7 +7465,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB _u(18) @@ -7903,7 +7472,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -7911,7 +7479,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -7919,7 +7486,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -7927,7 +7493,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB _u(14) @@ -7935,7 +7500,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -7943,7 +7507,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -7951,7 +7514,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -7959,7 +7521,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB _u(10) @@ -7967,7 +7528,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -7975,7 +7535,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -7983,7 +7542,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -7991,7 +7549,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB _u(6) @@ -7999,7 +7556,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -8007,7 +7563,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -8015,7 +7570,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -8023,7 +7577,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB _u(2) @@ -8031,7 +7584,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -8039,7 +7591,6 @@ #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -8053,7 +7604,6 @@ #define IO_BANK0_PROC0_INTS0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -8061,7 +7611,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB _u(30) @@ -8069,7 +7618,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -8077,7 +7625,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -8085,7 +7632,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -8093,7 +7639,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB _u(26) @@ -8101,7 +7646,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -8109,7 +7653,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -8117,7 +7660,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -8125,7 +7667,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB _u(22) @@ -8133,7 +7674,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -8141,7 +7681,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -8149,7 +7688,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -8157,7 +7695,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB _u(18) @@ -8165,7 +7702,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -8173,7 +7709,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -8181,7 +7716,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -8189,7 +7723,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB _u(14) @@ -8197,7 +7730,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -8205,7 +7737,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -8213,7 +7744,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -8221,7 +7751,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB _u(10) @@ -8229,7 +7758,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -8237,7 +7765,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -8245,7 +7772,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -8253,7 +7779,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB _u(6) @@ -8261,7 +7786,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -8269,7 +7793,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -8277,7 +7800,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -8285,7 +7807,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB _u(2) @@ -8293,7 +7814,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -8301,7 +7821,6 @@ #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -8315,7 +7834,6 @@ #define IO_BANK0_PROC0_INTS1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -8323,7 +7841,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB _u(30) @@ -8331,7 +7848,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -8339,7 +7855,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -8347,7 +7862,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -8355,7 +7869,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB _u(26) @@ -8363,7 +7876,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -8371,7 +7883,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -8379,7 +7890,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -8387,7 +7897,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB _u(22) @@ -8395,7 +7904,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -8403,7 +7911,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -8411,7 +7918,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -8419,7 +7925,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB _u(18) @@ -8427,7 +7932,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -8435,7 +7939,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -8443,7 +7946,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -8451,7 +7953,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB _u(14) @@ -8459,7 +7960,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -8467,7 +7967,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -8475,7 +7974,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -8483,7 +7981,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB _u(10) @@ -8491,7 +7988,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -8499,7 +7995,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -8507,7 +8002,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -8515,7 +8009,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB _u(6) @@ -8523,7 +8016,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -8531,7 +8023,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -8539,7 +8030,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -8547,7 +8037,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB _u(2) @@ -8555,7 +8044,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -8563,7 +8051,6 @@ #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -8577,7 +8064,6 @@ #define IO_BANK0_PROC0_INTS2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -8585,7 +8071,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB _u(30) @@ -8593,7 +8078,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -8601,7 +8085,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -8609,7 +8092,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -8617,7 +8099,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB _u(26) @@ -8625,7 +8106,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -8633,7 +8113,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -8641,7 +8120,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -8649,7 +8127,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB _u(22) @@ -8657,7 +8134,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -8665,7 +8141,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -8673,7 +8148,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -8681,7 +8155,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB _u(18) @@ -8689,7 +8162,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -8697,7 +8169,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -8705,7 +8176,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -8713,7 +8183,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB _u(14) @@ -8721,7 +8190,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -8729,7 +8197,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -8737,7 +8204,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -8745,7 +8211,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB _u(10) @@ -8753,7 +8218,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -8761,7 +8225,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -8769,7 +8232,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -8777,7 +8239,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB _u(6) @@ -8785,7 +8246,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -8793,7 +8253,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -8801,7 +8260,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -8809,7 +8267,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB _u(2) @@ -8817,7 +8274,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -8825,7 +8281,6 @@ #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -8839,7 +8294,6 @@ #define IO_BANK0_PROC0_INTS3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -8847,7 +8301,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB _u(22) @@ -8855,7 +8308,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -8863,7 +8315,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -8871,7 +8322,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -8879,7 +8329,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB _u(18) @@ -8887,7 +8336,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -8895,7 +8343,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -8903,7 +8350,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -8911,7 +8357,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB _u(14) @@ -8919,7 +8364,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -8927,7 +8371,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -8935,7 +8378,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -8943,7 +8385,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB _u(10) @@ -8951,7 +8392,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -8959,7 +8399,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -8967,7 +8406,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -8975,7 +8413,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB _u(6) @@ -8983,7 +8420,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -8991,7 +8427,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -8999,7 +8434,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -9007,7 +8441,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB _u(2) @@ -9015,7 +8448,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -9023,7 +8455,6 @@ #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -9037,7 +8468,6 @@ #define IO_BANK0_PROC1_INTE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -9045,7 +8475,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB _u(30) @@ -9053,7 +8482,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -9061,7 +8489,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -9069,7 +8496,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -9077,7 +8503,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB _u(26) @@ -9085,7 +8510,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -9093,7 +8517,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -9101,7 +8524,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -9109,7 +8531,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB _u(22) @@ -9117,7 +8538,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -9125,7 +8545,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -9133,7 +8552,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -9141,7 +8559,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB _u(18) @@ -9149,7 +8566,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -9157,7 +8573,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -9165,7 +8580,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -9173,7 +8587,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB _u(14) @@ -9181,7 +8594,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -9189,7 +8601,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -9197,7 +8608,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -9205,7 +8615,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB _u(10) @@ -9213,7 +8622,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -9221,7 +8629,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -9229,7 +8636,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -9237,7 +8643,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB _u(6) @@ -9245,7 +8650,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -9253,7 +8657,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -9261,7 +8664,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -9269,7 +8671,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB _u(2) @@ -9277,7 +8678,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -9285,7 +8685,6 @@ #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -9299,7 +8698,6 @@ #define IO_BANK0_PROC1_INTE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -9307,7 +8705,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB _u(30) @@ -9315,7 +8712,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -9323,7 +8719,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -9331,7 +8726,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -9339,7 +8733,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB _u(26) @@ -9347,7 +8740,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -9355,7 +8747,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -9363,7 +8754,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -9371,7 +8761,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB _u(22) @@ -9379,7 +8768,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -9387,7 +8775,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -9395,7 +8782,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -9403,7 +8789,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB _u(18) @@ -9411,7 +8796,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -9419,7 +8803,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -9427,7 +8810,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -9435,7 +8817,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB _u(14) @@ -9443,7 +8824,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -9451,7 +8831,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -9459,7 +8838,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -9467,7 +8845,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB _u(10) @@ -9475,7 +8852,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -9483,7 +8859,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -9491,7 +8866,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -9499,7 +8873,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB _u(6) @@ -9507,7 +8880,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -9515,7 +8887,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -9523,7 +8894,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -9531,7 +8901,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB _u(2) @@ -9539,7 +8908,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -9547,7 +8915,6 @@ #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -9561,7 +8928,6 @@ #define IO_BANK0_PROC1_INTE2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -9569,7 +8935,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB _u(30) @@ -9577,7 +8942,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -9585,7 +8949,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -9593,7 +8956,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -9601,7 +8963,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB _u(26) @@ -9609,7 +8970,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -9617,7 +8977,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -9625,7 +8984,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -9633,7 +8991,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB _u(22) @@ -9641,7 +8998,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -9649,7 +9005,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -9657,7 +9012,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -9665,7 +9019,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB _u(18) @@ -9673,7 +9026,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -9681,7 +9033,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -9689,7 +9040,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -9697,7 +9047,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB _u(14) @@ -9705,7 +9054,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -9713,7 +9061,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -9721,7 +9068,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -9729,7 +9075,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB _u(10) @@ -9737,7 +9082,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -9745,7 +9089,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -9753,7 +9096,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -9761,7 +9103,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB _u(6) @@ -9769,7 +9110,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -9777,7 +9117,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -9785,7 +9124,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -9793,7 +9131,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB _u(2) @@ -9801,7 +9138,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -9809,7 +9145,6 @@ #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -9823,7 +9158,6 @@ #define IO_BANK0_PROC1_INTE3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -9831,7 +9165,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB _u(22) @@ -9839,7 +9172,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -9847,7 +9179,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -9855,7 +9186,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -9863,7 +9193,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB _u(18) @@ -9871,7 +9200,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -9879,7 +9207,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -9887,7 +9214,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -9895,7 +9221,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB _u(14) @@ -9903,7 +9228,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -9911,7 +9235,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -9919,7 +9242,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -9927,7 +9249,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB _u(10) @@ -9935,7 +9256,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -9943,7 +9263,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -9951,7 +9270,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -9959,7 +9277,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB _u(6) @@ -9967,7 +9284,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -9975,7 +9291,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -9983,7 +9298,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -9991,7 +9305,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB _u(2) @@ -9999,7 +9312,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -10007,7 +9319,6 @@ #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -10021,7 +9332,6 @@ #define IO_BANK0_PROC1_INTF0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -10029,7 +9339,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB _u(30) @@ -10037,7 +9346,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -10045,7 +9353,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -10053,7 +9360,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -10061,7 +9367,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB _u(26) @@ -10069,7 +9374,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -10077,7 +9381,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -10085,7 +9388,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -10093,7 +9395,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB _u(22) @@ -10101,7 +9402,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -10109,7 +9409,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -10117,7 +9416,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -10125,7 +9423,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB _u(18) @@ -10133,7 +9430,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -10141,7 +9437,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -10149,7 +9444,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -10157,7 +9451,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB _u(14) @@ -10165,7 +9458,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -10173,7 +9465,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -10181,7 +9472,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -10189,7 +9479,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB _u(10) @@ -10197,7 +9486,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -10205,7 +9493,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -10213,7 +9500,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -10221,7 +9507,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB _u(6) @@ -10229,7 +9514,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -10237,7 +9521,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -10245,7 +9528,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -10253,7 +9535,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB _u(2) @@ -10261,7 +9542,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -10269,7 +9549,6 @@ #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -10283,7 +9562,6 @@ #define IO_BANK0_PROC1_INTF1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -10291,7 +9569,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB _u(30) @@ -10299,7 +9576,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -10307,7 +9583,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -10315,7 +9590,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -10323,7 +9597,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB _u(26) @@ -10331,7 +9604,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -10339,7 +9611,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -10347,7 +9618,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -10355,7 +9625,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB _u(22) @@ -10363,7 +9632,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -10371,7 +9639,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -10379,7 +9646,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -10387,7 +9653,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB _u(18) @@ -10395,7 +9660,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -10403,7 +9667,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -10411,7 +9674,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -10419,7 +9681,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB _u(14) @@ -10427,7 +9688,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -10435,7 +9695,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -10443,7 +9702,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -10451,7 +9709,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB _u(10) @@ -10459,7 +9716,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -10467,7 +9723,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -10475,7 +9730,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -10483,7 +9737,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB _u(6) @@ -10491,7 +9744,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -10499,7 +9751,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -10507,7 +9758,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -10515,7 +9765,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB _u(2) @@ -10523,7 +9772,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -10531,7 +9779,6 @@ #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -10545,7 +9792,6 @@ #define IO_BANK0_PROC1_INTF2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -10553,7 +9799,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB _u(30) @@ -10561,7 +9806,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -10569,7 +9813,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -10577,7 +9820,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -10585,7 +9827,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB _u(26) @@ -10593,7 +9834,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -10601,7 +9841,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -10609,7 +9848,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -10617,7 +9855,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB _u(22) @@ -10625,7 +9862,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -10633,7 +9869,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -10641,7 +9876,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -10649,7 +9883,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB _u(18) @@ -10657,7 +9890,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -10665,7 +9897,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -10673,7 +9904,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -10681,7 +9911,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB _u(14) @@ -10689,7 +9918,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -10697,7 +9925,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -10705,7 +9932,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -10713,7 +9939,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB _u(10) @@ -10721,7 +9946,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -10729,7 +9953,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -10737,7 +9960,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -10745,7 +9967,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB _u(6) @@ -10753,7 +9974,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -10761,7 +9981,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -10769,7 +9988,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -10777,7 +9995,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB _u(2) @@ -10785,7 +10002,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -10793,7 +10009,6 @@ #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -10807,7 +10022,6 @@ #define IO_BANK0_PROC1_INTF3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -10815,7 +10029,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB _u(22) @@ -10823,7 +10036,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -10831,7 +10043,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -10839,7 +10050,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -10847,7 +10057,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB _u(18) @@ -10855,7 +10064,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -10863,7 +10071,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -10871,7 +10078,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -10879,7 +10085,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB _u(14) @@ -10887,7 +10092,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -10895,7 +10099,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -10903,7 +10106,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -10911,7 +10113,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB _u(10) @@ -10919,7 +10120,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -10927,7 +10127,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -10935,7 +10134,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -10943,7 +10141,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB _u(6) @@ -10951,7 +10148,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -10959,7 +10155,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -10967,7 +10162,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -10975,7 +10169,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB _u(2) @@ -10983,7 +10176,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -10991,7 +10183,6 @@ #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -11005,7 +10196,6 @@ #define IO_BANK0_PROC1_INTS0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -11013,7 +10203,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB _u(30) @@ -11021,7 +10210,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -11029,7 +10217,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -11037,7 +10224,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -11045,7 +10231,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB _u(26) @@ -11053,7 +10238,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -11061,7 +10245,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -11069,7 +10252,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -11077,7 +10259,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB _u(22) @@ -11085,7 +10266,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -11093,7 +10273,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -11101,7 +10280,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -11109,7 +10287,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB _u(18) @@ -11117,7 +10294,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -11125,7 +10301,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -11133,7 +10308,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -11141,7 +10315,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB _u(14) @@ -11149,7 +10322,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -11157,7 +10329,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -11165,7 +10336,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -11173,7 +10343,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB _u(10) @@ -11181,7 +10350,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -11189,7 +10357,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -11197,7 +10364,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -11205,7 +10371,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB _u(6) @@ -11213,7 +10378,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -11221,7 +10385,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -11229,7 +10392,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -11237,7 +10399,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB _u(2) @@ -11245,7 +10406,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -11253,7 +10413,6 @@ #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -11267,7 +10426,6 @@ #define IO_BANK0_PROC1_INTS1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -11275,7 +10433,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB _u(30) @@ -11283,7 +10440,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -11291,7 +10447,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -11299,7 +10454,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -11307,7 +10461,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB _u(26) @@ -11315,7 +10468,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -11323,7 +10475,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -11331,7 +10482,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -11339,7 +10489,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB _u(22) @@ -11347,7 +10496,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -11355,7 +10503,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -11363,7 +10510,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -11371,7 +10517,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB _u(18) @@ -11379,7 +10524,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -11387,7 +10531,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -11395,7 +10538,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -11403,7 +10545,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB _u(14) @@ -11411,7 +10552,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -11419,7 +10559,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -11427,7 +10566,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -11435,7 +10573,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB _u(10) @@ -11443,7 +10580,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -11451,7 +10587,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -11459,7 +10594,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -11467,7 +10601,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB _u(6) @@ -11475,7 +10608,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -11483,7 +10615,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -11491,7 +10622,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -11499,7 +10629,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB _u(2) @@ -11507,7 +10636,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -11515,7 +10643,6 @@ #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -11529,7 +10656,6 @@ #define IO_BANK0_PROC1_INTS2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -11537,7 +10663,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB _u(30) @@ -11545,7 +10670,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -11553,7 +10677,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -11561,7 +10684,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -11569,7 +10691,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB _u(26) @@ -11577,7 +10698,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -11585,7 +10705,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -11593,7 +10712,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -11601,7 +10719,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB _u(22) @@ -11609,7 +10726,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -11617,7 +10733,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -11625,7 +10740,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -11633,7 +10747,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB _u(18) @@ -11641,7 +10754,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -11649,7 +10761,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -11657,7 +10768,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -11665,7 +10775,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB _u(14) @@ -11673,7 +10782,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -11681,7 +10789,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -11689,7 +10796,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -11697,7 +10803,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB _u(10) @@ -11705,7 +10810,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -11713,7 +10817,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -11721,7 +10824,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -11729,7 +10831,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB _u(6) @@ -11737,7 +10838,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -11745,7 +10845,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -11753,7 +10852,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -11761,7 +10859,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB _u(2) @@ -11769,7 +10866,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -11777,7 +10873,6 @@ #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -11791,7 +10886,6 @@ #define IO_BANK0_PROC1_INTS3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -11799,7 +10893,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB _u(22) @@ -11807,7 +10900,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -11815,7 +10907,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -11823,7 +10914,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -11831,7 +10921,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB _u(18) @@ -11839,7 +10928,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -11847,7 +10935,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -11855,7 +10942,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -11863,7 +10949,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB _u(14) @@ -11871,7 +10956,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -11879,7 +10963,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -11887,7 +10970,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -11895,7 +10977,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB _u(10) @@ -11903,7 +10984,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -11911,7 +10991,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -11919,7 +10998,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -11927,7 +11005,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB _u(6) @@ -11935,7 +11012,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -11943,7 +11019,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -11951,7 +11026,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -11959,7 +11033,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB _u(2) @@ -11967,7 +11040,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -11975,7 +11047,6 @@ #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -11989,7 +11060,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -11997,7 +11067,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB _u(30) @@ -12005,7 +11074,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -12013,7 +11081,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -12021,7 +11088,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -12029,7 +11095,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB _u(26) @@ -12037,7 +11102,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -12045,7 +11109,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -12053,7 +11116,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -12061,7 +11123,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB _u(22) @@ -12069,7 +11130,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -12077,7 +11137,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -12085,7 +11144,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -12093,7 +11151,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB _u(18) @@ -12101,7 +11158,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -12109,7 +11165,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -12117,7 +11172,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -12125,7 +11179,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB _u(14) @@ -12133,7 +11186,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -12141,7 +11193,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -12149,7 +11200,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -12157,7 +11207,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB _u(10) @@ -12165,7 +11214,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -12173,7 +11221,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -12181,7 +11228,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -12189,7 +11235,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB _u(6) @@ -12197,7 +11242,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -12205,7 +11249,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -12213,7 +11256,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -12221,7 +11263,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB _u(2) @@ -12229,7 +11270,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -12237,7 +11277,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -12251,7 +11290,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -12259,7 +11297,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB _u(30) @@ -12267,7 +11304,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -12275,7 +11311,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -12283,7 +11318,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -12291,7 +11325,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB _u(26) @@ -12299,7 +11332,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -12307,7 +11339,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -12315,7 +11346,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -12323,7 +11353,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB _u(22) @@ -12331,7 +11360,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -12339,7 +11367,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -12347,7 +11374,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -12355,7 +11381,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB _u(18) @@ -12363,7 +11388,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -12371,7 +11395,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -12379,7 +11402,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -12387,7 +11409,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB _u(14) @@ -12395,7 +11416,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -12403,7 +11423,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -12411,7 +11430,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -12419,7 +11437,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB _u(10) @@ -12427,7 +11444,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -12435,7 +11451,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -12443,7 +11458,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -12451,7 +11465,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB _u(6) @@ -12459,7 +11472,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -12467,7 +11479,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -12475,7 +11486,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -12483,7 +11493,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB _u(2) @@ -12491,7 +11500,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -12499,7 +11507,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -12513,7 +11520,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -12521,7 +11527,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB _u(30) @@ -12529,7 +11534,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -12537,7 +11541,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -12545,7 +11548,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -12553,7 +11555,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB _u(26) @@ -12561,7 +11562,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -12569,7 +11569,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -12577,7 +11576,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -12585,7 +11583,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB _u(22) @@ -12593,7 +11590,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -12601,7 +11597,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -12609,7 +11604,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -12617,7 +11611,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB _u(18) @@ -12625,7 +11618,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -12633,7 +11625,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -12641,7 +11632,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -12649,7 +11639,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB _u(14) @@ -12657,7 +11646,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -12665,7 +11653,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -12673,7 +11660,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -12681,7 +11667,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB _u(10) @@ -12689,7 +11674,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -12697,7 +11681,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -12705,7 +11688,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -12713,7 +11695,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB _u(6) @@ -12721,7 +11702,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -12729,7 +11709,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -12737,7 +11716,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -12745,7 +11723,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB _u(2) @@ -12753,7 +11730,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -12761,7 +11737,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -12775,7 +11750,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -12783,7 +11757,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB _u(22) @@ -12791,7 +11764,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -12799,7 +11771,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -12807,7 +11778,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -12815,7 +11785,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB _u(18) @@ -12823,7 +11792,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -12831,7 +11799,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -12839,7 +11806,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -12847,7 +11813,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB _u(14) @@ -12855,7 +11820,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -12863,7 +11827,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -12871,7 +11834,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -12879,7 +11841,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB _u(10) @@ -12887,7 +11848,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -12895,7 +11855,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -12903,7 +11862,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -12911,7 +11869,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB _u(6) @@ -12919,7 +11876,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -12927,7 +11883,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -12935,7 +11890,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -12943,7 +11897,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB _u(2) @@ -12951,7 +11904,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -12959,7 +11911,6 @@ #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -12973,7 +11924,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -12981,7 +11931,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB _u(30) @@ -12989,7 +11938,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -12997,7 +11945,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -13005,7 +11952,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -13013,7 +11959,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB _u(26) @@ -13021,7 +11966,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -13029,7 +11973,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -13037,7 +11980,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -13045,7 +11987,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB _u(22) @@ -13053,7 +11994,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -13061,7 +12001,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -13069,7 +12008,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -13077,7 +12015,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB _u(18) @@ -13085,7 +12022,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -13093,7 +12029,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -13101,7 +12036,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -13109,7 +12043,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB _u(14) @@ -13117,7 +12050,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -13125,7 +12057,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -13133,7 +12064,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -13141,7 +12071,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB _u(10) @@ -13149,7 +12078,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -13157,7 +12085,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -13165,7 +12092,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -13173,7 +12099,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB _u(6) @@ -13181,7 +12106,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -13189,7 +12113,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -13197,7 +12120,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -13205,7 +12127,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB _u(2) @@ -13213,7 +12134,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -13221,7 +12141,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -13235,7 +12154,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -13243,7 +12161,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB _u(30) @@ -13251,7 +12168,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -13259,7 +12175,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -13267,7 +12182,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -13275,7 +12189,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB _u(26) @@ -13283,7 +12196,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -13291,7 +12203,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -13299,7 +12210,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -13307,7 +12217,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB _u(22) @@ -13315,7 +12224,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -13323,7 +12231,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -13331,7 +12238,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -13339,7 +12245,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB _u(18) @@ -13347,7 +12252,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -13355,7 +12259,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -13363,7 +12266,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -13371,7 +12273,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB _u(14) @@ -13379,7 +12280,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -13387,7 +12287,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -13395,7 +12294,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -13403,7 +12301,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB _u(10) @@ -13411,7 +12308,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -13419,7 +12315,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -13427,7 +12322,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -13435,7 +12329,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB _u(6) @@ -13443,7 +12336,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -13451,7 +12343,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -13459,7 +12350,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -13467,7 +12357,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB _u(2) @@ -13475,7 +12364,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -13483,7 +12371,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -13497,7 +12384,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -13505,7 +12391,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB _u(30) @@ -13513,7 +12398,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -13521,7 +12405,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -13529,7 +12412,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -13537,7 +12419,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB _u(26) @@ -13545,7 +12426,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -13553,7 +12433,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -13561,7 +12440,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -13569,7 +12447,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB _u(22) @@ -13577,7 +12454,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -13585,7 +12461,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -13593,7 +12468,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -13601,7 +12475,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB _u(18) @@ -13609,7 +12482,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -13617,7 +12489,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -13625,7 +12496,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -13633,7 +12503,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB _u(14) @@ -13641,7 +12510,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -13649,7 +12517,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -13657,7 +12524,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -13665,7 +12531,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB _u(10) @@ -13673,7 +12538,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -13681,7 +12545,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -13689,7 +12552,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -13697,7 +12559,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB _u(6) @@ -13705,7 +12566,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -13713,7 +12573,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -13721,7 +12580,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -13729,7 +12587,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB _u(2) @@ -13737,7 +12594,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -13745,7 +12601,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -13759,7 +12614,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -13767,7 +12621,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB _u(22) @@ -13775,7 +12628,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -13783,7 +12635,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -13791,7 +12642,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -13799,7 +12649,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB _u(18) @@ -13807,7 +12656,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -13815,7 +12663,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -13823,7 +12670,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -13831,7 +12677,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB _u(14) @@ -13839,7 +12684,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -13847,7 +12691,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -13855,7 +12698,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -13863,7 +12705,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB _u(10) @@ -13871,7 +12712,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -13879,7 +12719,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -13887,7 +12726,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -13895,7 +12733,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB _u(6) @@ -13903,7 +12740,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -13911,7 +12747,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -13919,7 +12754,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -13927,7 +12761,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB _u(2) @@ -13935,7 +12768,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -13943,7 +12775,6 @@ #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) @@ -13957,7 +12788,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) @@ -13965,7 +12795,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB _u(30) @@ -13973,7 +12802,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) @@ -13981,7 +12809,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) @@ -13989,7 +12816,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) @@ -13997,7 +12823,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB _u(26) @@ -14005,7 +12830,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) @@ -14013,7 +12837,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) @@ -14021,7 +12844,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) @@ -14029,7 +12851,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB _u(22) @@ -14037,7 +12858,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) @@ -14045,7 +12865,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) @@ -14053,7 +12872,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) @@ -14061,7 +12879,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB _u(18) @@ -14069,7 +12886,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) @@ -14077,7 +12893,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) @@ -14085,7 +12900,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) @@ -14093,7 +12907,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB _u(14) @@ -14101,7 +12914,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) @@ -14109,7 +12921,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) @@ -14117,7 +12928,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) @@ -14125,7 +12935,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB _u(10) @@ -14133,7 +12942,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) @@ -14141,7 +12949,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) @@ -14149,7 +12956,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) @@ -14157,7 +12963,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB _u(6) @@ -14165,7 +12970,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) @@ -14173,7 +12977,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) @@ -14181,7 +12984,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) @@ -14189,7 +12991,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB _u(2) @@ -14197,7 +12998,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) @@ -14205,7 +13005,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) @@ -14219,7 +13018,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) @@ -14227,7 +13025,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB _u(30) @@ -14235,7 +13032,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) @@ -14243,7 +13039,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) @@ -14251,7 +13046,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) @@ -14259,7 +13053,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB _u(26) @@ -14267,7 +13060,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) @@ -14275,7 +13067,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) @@ -14283,7 +13074,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) @@ -14291,7 +13081,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB _u(22) @@ -14299,7 +13088,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) @@ -14307,7 +13095,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) @@ -14315,7 +13102,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) @@ -14323,7 +13109,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB _u(18) @@ -14331,7 +13116,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) @@ -14339,7 +13123,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) @@ -14347,7 +13130,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) @@ -14355,7 +13137,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB _u(14) @@ -14363,7 +13144,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) @@ -14371,7 +13151,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) @@ -14379,7 +13158,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) @@ -14387,7 +13165,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB _u(10) @@ -14395,7 +13172,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) @@ -14403,7 +13179,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) @@ -14411,7 +13186,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) @@ -14419,7 +13193,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB _u(6) @@ -14427,7 +13200,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) @@ -14435,7 +13207,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) @@ -14443,7 +13214,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) @@ -14451,7 +13221,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB _u(2) @@ -14459,7 +13228,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) @@ -14467,7 +13235,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) @@ -14481,7 +13248,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) @@ -14489,7 +13255,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB _u(30) @@ -14497,7 +13262,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) @@ -14505,7 +13269,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) @@ -14513,7 +13276,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) @@ -14521,7 +13283,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB _u(26) @@ -14529,7 +13290,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) @@ -14537,7 +13297,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) @@ -14545,7 +13304,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) @@ -14553,7 +13311,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB _u(22) @@ -14561,7 +13318,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) @@ -14569,7 +13325,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) @@ -14577,7 +13332,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) @@ -14585,7 +13339,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB _u(18) @@ -14593,7 +13346,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) @@ -14601,7 +13353,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) @@ -14609,7 +13360,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) @@ -14617,7 +13367,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB _u(14) @@ -14625,7 +13374,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) @@ -14633,7 +13381,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) @@ -14641,7 +13388,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) @@ -14649,7 +13395,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB _u(10) @@ -14657,7 +13402,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) @@ -14665,7 +13409,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) @@ -14673,7 +13416,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) @@ -14681,7 +13423,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB _u(6) @@ -14689,7 +13430,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) @@ -14697,7 +13437,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) @@ -14705,7 +13444,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) @@ -14713,7 +13451,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB _u(2) @@ -14721,7 +13458,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) @@ -14729,7 +13465,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) @@ -14743,7 +13478,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) @@ -14751,7 +13485,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB _u(22) @@ -14759,7 +13492,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) @@ -14767,7 +13499,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) @@ -14775,7 +13506,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) @@ -14783,7 +13513,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB _u(18) @@ -14791,7 +13520,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) @@ -14799,7 +13527,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) @@ -14807,7 +13534,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) @@ -14815,7 +13541,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB _u(14) @@ -14823,7 +13548,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) @@ -14831,7 +13555,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) @@ -14839,7 +13562,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) @@ -14847,7 +13569,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB _u(10) @@ -14855,7 +13576,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) @@ -14863,7 +13583,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) @@ -14871,7 +13590,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) @@ -14879,7 +13597,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB _u(6) @@ -14887,7 +13604,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) @@ -14895,7 +13611,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) @@ -14903,7 +13618,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) @@ -14911,7 +13625,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB _u(2) @@ -14919,7 +13632,6 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) @@ -14927,11 +13639,11 @@ #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW -// Description : None #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) #define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_IO_BANK0_DEFINED +#endif // _HARDWARE_REGS_IO_BANK0_H + diff --git a/lib/rp2040/hardware/regs/io_qspi.h b/lib/pico-sdk/rp2040/hardware/regs/io_qspi.h similarity index 88% rename from lib/rp2040/hardware/regs/io_qspi.h rename to lib/pico-sdk/rp2040/hardware/regs/io_qspi.h index 7c381b7a51b6..5ed0ddbad911 100644 --- a/lib/rp2040/hardware/regs/io_qspi.h +++ b/lib/pico-sdk/rp2040/hardware/regs/io_qspi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : IO_QSPI // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_IO_QSPI_DEFINED -#define HARDWARE_REGS_IO_QSPI_DEFINED +#ifndef _HARDWARE_REGS_IO_QSPI_H +#define _HARDWARE_REGS_IO_QSPI_H // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SCLK_STATUS // Description : GPIO status @@ -91,67 +92,64 @@ #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB _u(8) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -159,14 +157,14 @@ // 0x00 -> xip_sclk // 0x05 -> sio_30 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _u(0x00) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SS_STATUS // Description : GPIO status @@ -247,67 +245,64 @@ #define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB _u(8) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -315,14 +310,14 @@ // 0x00 -> xip_ss_n // 0x05 -> sio_31 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N _u(0x00) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD0_STATUS // Description : GPIO status @@ -403,67 +398,64 @@ #define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -471,14 +463,14 @@ // 0x00 -> xip_sd0 // 0x05 -> sio_32 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD1_STATUS // Description : GPIO status @@ -559,67 +551,64 @@ #define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -627,14 +616,14 @@ // 0x00 -> xip_sd1 // 0x05 -> sio_33 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD2_STATUS // Description : GPIO status @@ -715,67 +704,64 @@ #define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -783,14 +769,14 @@ // 0x00 -> xip_sd2 // 0x05 -> sio_34 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_GPIO_QSPI_SD3_STATUS // Description : GPIO status @@ -871,67 +857,64 @@ #define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET _u(0x0000001f) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER -// Description : 0x0 -> don't invert the interrupt +// 0x0 -> don't invert the interrupt // 0x1 -> invert the interrupt // 0x2 -> drive interrupt low // 0x3 -> drive interrupt high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS _u(0x30000000) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB _u(29) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB _u(28) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER -// Description : 0x0 -> don't invert the peri input +// 0x0 -> don't invert the peri input // 0x1 -> invert the peri input // 0x2 -> drive peri input low // 0x3 -> drive peri input high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS _u(0x00030000) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB _u(17) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB _u(16) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER -// Description : 0x0 -> drive output enable from peripheral signal selected by -// funcsel -// 0x1 -> drive output enable from inverse of peripheral signal -// selected by funcsel +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel // 0x2 -> disable output // 0x3 -> enable output -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS _u(0x00003000) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB _u(13) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB _u(12) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW" -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _u(0x1) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER -// Description : 0x0 -> drive output from peripheral signal selected by funcsel -// 0x1 -> drive output from inverse of peripheral signal selected -// by funcsel +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel // 0x2 -> drive output low // 0x3 -> drive output high -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS _u(0x00000300) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB _u(9) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB _u(8) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS _u(0x00000300) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB _u(8) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) #define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _u(0x2) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) // ----------------------------------------------------------------------------- // Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL // Description : 0-31 -> selects pin function according to the gpio table @@ -939,14 +922,14 @@ // 0x00 -> xip_sd3 // 0x05 -> sio_35 // 0x1f -> null -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _u(0x1f) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS _u(0x0000001f) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB _u(4) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB _u(0) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW" #define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _u(0x00) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 _u(0x05) -#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) // ============================================================================= // Register : IO_QSPI_INTR // Description : Raw Interrupts @@ -955,7 +938,6 @@ #define IO_QSPI_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -963,7 +945,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -971,7 +952,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -979,7 +959,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -987,7 +966,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -995,7 +973,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -1003,7 +980,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -1011,7 +987,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -1019,7 +994,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -1027,7 +1001,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -1035,7 +1008,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -1043,7 +1015,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -1051,7 +1022,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -1059,7 +1029,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -1067,7 +1036,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -1075,7 +1043,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -1083,7 +1050,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -1091,7 +1057,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -1099,7 +1064,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -1107,7 +1071,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -1115,7 +1078,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -1123,7 +1085,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -1131,7 +1092,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -1139,7 +1099,6 @@ #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -1153,7 +1112,6 @@ #define IO_QSPI_PROC0_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -1161,7 +1119,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -1169,7 +1126,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -1177,7 +1133,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -1185,7 +1140,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -1193,7 +1147,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -1201,7 +1154,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -1209,7 +1161,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -1217,7 +1168,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -1225,7 +1175,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -1233,7 +1182,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -1241,7 +1189,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -1249,7 +1196,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -1257,7 +1203,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -1265,7 +1210,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -1273,7 +1217,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -1281,7 +1224,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -1289,7 +1231,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -1297,7 +1238,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -1305,7 +1245,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -1313,7 +1252,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -1321,7 +1259,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -1329,7 +1266,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -1337,7 +1273,6 @@ #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -1351,7 +1286,6 @@ #define IO_QSPI_PROC0_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -1359,7 +1293,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -1367,7 +1300,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -1375,7 +1307,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -1383,7 +1314,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -1391,7 +1321,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -1399,7 +1328,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -1407,7 +1335,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -1415,7 +1342,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -1423,7 +1349,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -1431,7 +1356,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -1439,7 +1363,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -1447,7 +1370,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -1455,7 +1377,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -1463,7 +1384,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -1471,7 +1391,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -1479,7 +1398,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -1487,7 +1405,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -1495,7 +1412,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -1503,7 +1419,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -1511,7 +1426,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -1519,7 +1433,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -1527,7 +1440,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -1535,7 +1447,6 @@ #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -1549,7 +1460,6 @@ #define IO_QSPI_PROC0_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -1557,7 +1467,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -1565,7 +1474,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -1573,7 +1481,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -1581,7 +1488,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -1589,7 +1495,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -1597,7 +1502,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -1605,7 +1509,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -1613,7 +1516,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -1621,7 +1523,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -1629,7 +1530,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -1637,7 +1537,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -1645,7 +1544,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -1653,7 +1551,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -1661,7 +1558,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -1669,7 +1565,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -1677,7 +1572,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -1685,7 +1579,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -1693,7 +1586,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -1701,7 +1593,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -1709,7 +1600,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -1717,7 +1607,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -1725,7 +1614,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -1733,7 +1621,6 @@ #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -1747,7 +1634,6 @@ #define IO_QSPI_PROC1_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -1755,7 +1641,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -1763,7 +1648,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -1771,7 +1655,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -1779,7 +1662,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -1787,7 +1669,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -1795,7 +1676,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -1803,7 +1683,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -1811,7 +1690,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -1819,7 +1697,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -1827,7 +1704,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -1835,7 +1711,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -1843,7 +1718,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -1851,7 +1725,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -1859,7 +1732,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -1867,7 +1739,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -1875,7 +1746,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -1883,7 +1753,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -1891,7 +1760,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -1899,7 +1767,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -1907,7 +1774,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -1915,7 +1781,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -1923,7 +1788,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -1931,7 +1795,6 @@ #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -1945,7 +1808,6 @@ #define IO_QSPI_PROC1_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -1953,7 +1815,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -1961,7 +1822,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -1969,7 +1829,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -1977,7 +1836,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -1985,7 +1843,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -1993,7 +1850,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -2001,7 +1857,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -2009,7 +1864,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -2017,7 +1871,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -2025,7 +1878,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -2033,7 +1885,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -2041,7 +1892,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -2049,7 +1899,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -2057,7 +1906,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -2065,7 +1913,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -2073,7 +1920,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -2081,7 +1927,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -2089,7 +1934,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -2097,7 +1941,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -2105,7 +1948,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -2113,7 +1955,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -2121,7 +1962,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -2129,7 +1969,6 @@ #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -2143,7 +1982,6 @@ #define IO_QSPI_PROC1_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -2151,7 +1989,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -2159,7 +1996,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -2167,7 +2003,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -2175,7 +2010,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -2183,7 +2017,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -2191,7 +2024,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -2199,7 +2031,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -2207,7 +2038,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -2215,7 +2045,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -2223,7 +2052,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -2231,7 +2059,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -2239,7 +2066,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -2247,7 +2073,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -2255,7 +2080,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -2263,7 +2087,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -2271,7 +2094,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -2279,7 +2101,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -2287,7 +2108,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -2295,7 +2115,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -2303,7 +2122,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -2311,7 +2129,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -2319,7 +2136,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -2327,7 +2143,6 @@ #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -2341,7 +2156,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -2349,7 +2163,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -2357,7 +2170,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -2365,7 +2177,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -2373,7 +2184,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -2381,7 +2191,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -2389,7 +2198,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -2397,7 +2205,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -2405,7 +2212,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -2413,7 +2219,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -2421,7 +2226,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -2429,7 +2233,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -2437,7 +2240,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -2445,7 +2247,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -2453,7 +2254,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -2461,7 +2261,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -2469,7 +2268,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -2477,7 +2275,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -2485,7 +2282,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -2493,7 +2289,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -2501,7 +2296,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -2509,7 +2303,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -2517,7 +2310,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -2525,7 +2317,6 @@ #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -2539,7 +2330,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -2547,7 +2337,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -2555,7 +2344,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -2563,7 +2351,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -2571,7 +2358,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -2579,7 +2365,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -2587,7 +2372,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -2595,7 +2379,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -2603,7 +2386,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -2611,7 +2393,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -2619,7 +2400,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -2627,7 +2407,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -2635,7 +2414,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -2643,7 +2421,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -2651,7 +2428,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -2659,7 +2435,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -2667,7 +2442,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -2675,7 +2449,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -2683,7 +2456,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -2691,7 +2463,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -2699,7 +2470,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -2707,7 +2477,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -2715,7 +2484,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -2723,7 +2491,6 @@ #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) @@ -2737,7 +2504,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23) @@ -2745,7 +2511,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22) @@ -2753,7 +2518,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21) @@ -2761,7 +2525,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20) @@ -2769,7 +2532,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19) @@ -2777,7 +2539,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18) @@ -2785,7 +2546,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17) @@ -2793,7 +2553,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16) @@ -2801,7 +2560,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15) @@ -2809,7 +2567,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14) @@ -2817,7 +2574,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13) @@ -2825,7 +2581,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12) @@ -2833,7 +2588,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11) @@ -2841,7 +2595,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10) @@ -2849,7 +2602,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9) @@ -2857,7 +2609,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8) @@ -2865,7 +2616,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7) @@ -2873,7 +2623,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6) @@ -2881,7 +2630,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5) @@ -2889,7 +2637,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4) @@ -2897,7 +2644,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3) @@ -2905,7 +2651,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2) @@ -2913,7 +2658,6 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1) @@ -2921,11 +2665,11 @@ #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW -// Description : None #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0) #define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_IO_QSPI_DEFINED +#endif // _HARDWARE_REGS_IO_QSPI_H + diff --git a/lib/rp2040/hardware/regs/m0plus.h b/lib/pico-sdk/rp2040/hardware/regs/m0plus.h similarity index 99% rename from lib/rp2040/hardware/regs/m0plus.h rename to lib/pico-sdk/rp2040/hardware/regs/m0plus.h index cef5ab0a1fc0..028e5ad85128 100644 --- a/lib/rp2040/hardware/regs/m0plus.h +++ b/lib/pico-sdk/rp2040/hardware/regs/m0plus.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : M0PLUS // Version : 1 // Bus type : ahbl -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_M0PLUS_DEFINED -#define HARDWARE_REGS_M0PLUS_DEFINED +#ifndef _HARDWARE_REGS_M0PLUS_H +#define _HARDWARE_REGS_M0PLUS_H // ============================================================================= // Register : M0PLUS_SYST_CSR // Description : Use the SysTick Control and Status Register to enable the @@ -610,11 +611,11 @@ #define M0PLUS_CPUID_REVISION_ACCESS "RO" // ============================================================================= // Register : M0PLUS_ICSR -// Description : Use the Interrupt Control State Register to set a pending -// Non-Maskable Interrupt (NMI), set or clear a pending PendSV, -// set or clear a pending SysTick, check for pending exceptions, -// check the vector number of the highest priority pended -// exception, check the vector number of the active exception. +// Description : Use the Interrupt Control State Register to set a pending Non- +// Maskable Interrupt (NMI), set or clear a pending PendSV, set or +// clear a pending SysTick, check for pending exceptions, check +// the vector number of the highest priority pended exception, +// check the vector number of the active exception. #define M0PLUS_ICSR_OFFSET _u(0x0000ed04) #define M0PLUS_ICSR_BITS _u(0x9edff1ff) #define M0PLUS_ICSR_RESET _u(0x00000000) @@ -1146,4 +1147,5 @@ #define M0PLUS_MPU_RASR_ENABLE_LSB _u(0) #define M0PLUS_MPU_RASR_ENABLE_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_M0PLUS_DEFINED +#endif // _HARDWARE_REGS_M0PLUS_H + diff --git a/lib/rp2040/hardware/regs/pads_bank0.h b/lib/pico-sdk/rp2040/hardware/regs/pads_bank0.h similarity index 87% rename from lib/rp2040/hardware/regs/pads_bank0.h rename to lib/pico-sdk/rp2040/hardware/regs/pads_bank0.h index 06102ac97b52..04c5e39712e8 100644 --- a/lib/rp2040/hardware/regs/pads_bank0.h +++ b/lib/pico-sdk/rp2040/hardware/regs/pads_bank0.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,21 +9,20 @@ // Register block : PADS_BANK0 // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_PADS_BANK0_DEFINED -#define HARDWARE_REGS_PADS_BANK0_DEFINED +#ifndef _HARDWARE_REGS_PADS_BANK0_H +#define _HARDWARE_REGS_PADS_BANK0_H // ============================================================================= // Register : PADS_BANK0_VOLTAGE_SELECT // Description : Voltage select. Per bank control // 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) // 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) -#define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000) -#define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001) -#define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000) -#define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0) -#define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0) -#define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" +#define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000) +#define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001) +#define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000) +#define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0) +#define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0) +#define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" #define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) #define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) // ============================================================================= @@ -54,14 +55,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO0_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO0_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO0_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO0_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO0_PUE @@ -125,14 +126,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO1_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO1_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO1_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO1_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO1_PUE @@ -196,14 +197,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO2_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO2_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO2_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO2_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO2_PUE @@ -267,14 +268,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO3_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO3_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO3_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO3_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO3_PUE @@ -338,14 +339,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO4_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO4_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO4_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO4_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO4_PUE @@ -409,14 +410,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO5_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO5_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO5_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO5_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO5_PUE @@ -480,14 +481,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO6_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO6_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO6_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO6_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO6_PUE @@ -551,14 +552,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO7_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO7_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO7_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO7_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO7_PUE @@ -622,14 +623,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO8_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO8_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO8_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO8_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO8_PUE @@ -693,14 +694,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO9_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO9_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO9_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO9_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO9_PUE @@ -764,14 +765,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO10_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO10_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO10_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO10_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO10_PUE @@ -835,14 +836,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO11_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO11_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO11_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO11_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO11_PUE @@ -906,14 +907,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO12_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO12_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO12_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO12_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO12_PUE @@ -977,14 +978,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO13_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO13_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO13_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO13_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO13_PUE @@ -1048,14 +1049,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO14_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO14_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO14_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO14_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO14_PUE @@ -1119,14 +1120,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO15_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO15_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO15_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO15_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO15_PUE @@ -1190,14 +1191,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO16_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO16_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO16_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO16_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO16_PUE @@ -1261,14 +1262,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO17_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO17_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO17_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO17_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO17_PUE @@ -1332,14 +1333,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO18_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO18_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO18_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO18_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO18_PUE @@ -1403,14 +1404,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO19_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO19_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO19_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO19_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO19_PUE @@ -1474,14 +1475,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO20_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO20_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO20_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO20_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO20_PUE @@ -1545,14 +1546,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO21_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO21_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO21_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO21_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO21_PUE @@ -1616,14 +1617,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO22_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO22_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO22_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO22_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO22_PUE @@ -1687,14 +1688,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO23_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO23_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO23_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO23_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO23_PUE @@ -1758,14 +1759,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO24_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO24_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO24_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO24_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO24_PUE @@ -1829,14 +1830,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO25_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO25_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO25_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO25_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO25_PUE @@ -1900,14 +1901,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO26_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO26_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO26_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO26_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO26_PUE @@ -1971,14 +1972,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO27_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO27_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO27_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO27_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO27_PUE @@ -2042,14 +2043,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO28_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO28_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO28_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO28_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO28_PUE @@ -2113,14 +2114,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1) -#define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_GPIO29_DRIVE_MSB _u(5) -#define PADS_BANK0_GPIO29_DRIVE_LSB _u(4) -#define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" -#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO29_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO29_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_GPIO29_PUE @@ -2184,14 +2185,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1) -#define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_SWCLK_DRIVE_MSB _u(5) -#define PADS_BANK0_SWCLK_DRIVE_LSB _u(4) -#define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" -#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1) +#define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_SWCLK_DRIVE_MSB _u(5) +#define PADS_BANK0_SWCLK_DRIVE_LSB _u(4) +#define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" +#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWCLK_PUE @@ -2255,14 +2256,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_BANK0_SWD_DRIVE_RESET _u(0x1) -#define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030) -#define PADS_BANK0_SWD_DRIVE_MSB _u(5) -#define PADS_BANK0_SWD_DRIVE_LSB _u(4) -#define PADS_BANK0_SWD_DRIVE_ACCESS "RW" -#define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0) -#define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1) -#define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_SWD_DRIVE_RESET _u(0x1) +#define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_SWD_DRIVE_MSB _u(5) +#define PADS_BANK0_SWD_DRIVE_LSB _u(4) +#define PADS_BANK0_SWD_DRIVE_ACCESS "RW" +#define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2) #define PADS_BANK0_SWD_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_BANK0_SWD_PUE @@ -2297,4 +2298,5 @@ #define PADS_BANK0_SWD_SLEWFAST_LSB _u(0) #define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_PADS_BANK0_DEFINED +#endif // _HARDWARE_REGS_PADS_BANK0_H + diff --git a/lib/rp2040/hardware/regs/pads_qspi.h b/lib/pico-sdk/rp2040/hardware/regs/pads_qspi.h similarity index 86% rename from lib/rp2040/hardware/regs/pads_qspi.h rename to lib/pico-sdk/rp2040/hardware/regs/pads_qspi.h index b3a09e9001f2..4cd27ea7c08b 100644 --- a/lib/rp2040/hardware/regs/pads_qspi.h +++ b/lib/pico-sdk/rp2040/hardware/regs/pads_qspi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,21 +9,20 @@ // Register block : PADS_QSPI // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_PADS_QSPI_DEFINED -#define HARDWARE_REGS_PADS_QSPI_DEFINED +#ifndef _HARDWARE_REGS_PADS_QSPI_H +#define _HARDWARE_REGS_PADS_QSPI_H // ============================================================================= // Register : PADS_QSPI_VOLTAGE_SELECT // Description : Voltage select. Per bank control // 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) // 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) -#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000) -#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001) -#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000) -#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0) -#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0) -#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW" +#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000) +#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001) +#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000) +#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0) +#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0) +#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW" #define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) #define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) // ============================================================================= @@ -54,14 +55,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2) #define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE @@ -125,14 +126,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2) #define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD0_PUE @@ -196,14 +197,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2) #define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD1_PUE @@ -267,14 +268,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2) #define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD2_PUE @@ -338,14 +339,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2) #define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SD3_PUE @@ -409,14 +410,14 @@ // 0x1 -> 4mA // 0x2 -> 8mA // 0x3 -> 12mA -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW" -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1) -#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2) #define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3) // ----------------------------------------------------------------------------- // Field : PADS_QSPI_GPIO_QSPI_SS_PUE @@ -451,4 +452,5 @@ #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0) #define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_PADS_QSPI_DEFINED +#endif // _HARDWARE_REGS_PADS_QSPI_H + diff --git a/lib/rp2040/hardware/regs/pio.h b/lib/pico-sdk/rp2040/hardware/regs/pio.h similarity index 97% rename from lib/rp2040/hardware/regs/pio.h rename to lib/pico-sdk/rp2040/hardware/regs/pio.h index 8b4829fbcbfa..d10de90f2cb0 100644 --- a/lib/rp2040/hardware/regs/pio.h +++ b/lib/pico-sdk/rp2040/hardware/regs/pio.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : ahbl // Description : Programmable IO block // ============================================================================= -#ifndef HARDWARE_REGS_PIO_DEFINED -#define HARDWARE_REGS_PIO_DEFINED +#ifndef _HARDWARE_REGS_PIO_H +#define _HARDWARE_REGS_PIO_H // ============================================================================= // Register : PIO_CTRL // Description : PIO control register @@ -52,6 +54,9 @@ // counter; the waiting-on-IRQ state; any stalled instruction // written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left // asserted due to OUT_STICKY. +// +// The program counter, the contents of the output shift register +// and the X/Y scratch registers are not affected. #define PIO_CTRL_SM_RESTART_RESET _u(0x0) #define PIO_CTRL_SM_RESTART_BITS _u(0x000000f0) #define PIO_CTRL_SM_RESTART_MSB _u(7) @@ -166,7 +171,6 @@ #define PIO_FLEVEL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX3 -// Description : None #define PIO_FLEVEL_RX3_RESET _u(0x0) #define PIO_FLEVEL_RX3_BITS _u(0xf0000000) #define PIO_FLEVEL_RX3_MSB _u(31) @@ -174,7 +178,6 @@ #define PIO_FLEVEL_RX3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX3 -// Description : None #define PIO_FLEVEL_TX3_RESET _u(0x0) #define PIO_FLEVEL_TX3_BITS _u(0x0f000000) #define PIO_FLEVEL_TX3_MSB _u(27) @@ -182,7 +185,6 @@ #define PIO_FLEVEL_TX3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX2 -// Description : None #define PIO_FLEVEL_RX2_RESET _u(0x0) #define PIO_FLEVEL_RX2_BITS _u(0x00f00000) #define PIO_FLEVEL_RX2_MSB _u(23) @@ -190,7 +192,6 @@ #define PIO_FLEVEL_RX2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX2 -// Description : None #define PIO_FLEVEL_TX2_RESET _u(0x0) #define PIO_FLEVEL_TX2_BITS _u(0x000f0000) #define PIO_FLEVEL_TX2_MSB _u(19) @@ -198,7 +199,6 @@ #define PIO_FLEVEL_TX2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX1 -// Description : None #define PIO_FLEVEL_RX1_RESET _u(0x0) #define PIO_FLEVEL_RX1_BITS _u(0x0000f000) #define PIO_FLEVEL_RX1_MSB _u(15) @@ -206,7 +206,6 @@ #define PIO_FLEVEL_RX1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX1 -// Description : None #define PIO_FLEVEL_TX1_RESET _u(0x0) #define PIO_FLEVEL_TX1_BITS _u(0x00000f00) #define PIO_FLEVEL_TX1_MSB _u(11) @@ -214,7 +213,6 @@ #define PIO_FLEVEL_TX1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_RX0 -// Description : None #define PIO_FLEVEL_RX0_RESET _u(0x0) #define PIO_FLEVEL_RX0_BITS _u(0x000000f0) #define PIO_FLEVEL_RX0_MSB _u(7) @@ -222,7 +220,6 @@ #define PIO_FLEVEL_RX0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_FLEVEL_TX0 -// Description : None #define PIO_FLEVEL_TX0_RESET _u(0x0) #define PIO_FLEVEL_TX0_BITS _u(0x0000000f) #define PIO_FLEVEL_TX0_MSB _u(3) @@ -378,7 +375,8 @@ // ============================================================================= // Register : PIO_DBG_PADOUT // Description : Read to sample the pad output values PIO is currently driving -// to the GPIOs. +// to the GPIOs. On RP2040 there are 30 GPIOs, so the two most +// significant bits are hardwired to 0. #define PIO_DBG_PADOUT_OFFSET _u(0x0000003c) #define PIO_DBG_PADOUT_BITS _u(0xffffffff) #define PIO_DBG_PADOUT_RESET _u(0x00000000) @@ -388,7 +386,8 @@ // ============================================================================= // Register : PIO_DBG_PADOE // Description : Read to sample the pad output enables (direction) PIO is -// currently driving to the GPIOs. +// currently driving to the GPIOs. On RP2040 there are 30 GPIOs, +// so the two most significant bits are hardwired to 0. #define PIO_DBG_PADOE_OFFSET _u(0x00000040) #define PIO_DBG_PADOE_BITS _u(0xffffffff) #define PIO_DBG_PADOE_RESET _u(0x00000000) @@ -846,11 +845,11 @@ // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) -#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(4) -#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(4) -#define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(4) +#define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" #define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) #define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- @@ -1021,10 +1020,10 @@ // Description : The lowest-numbered pin that will be affected by a side-set // operation. The MSBs of an instruction's side-set/delay field // (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The -// least-significant bit of the side-set portion is the bit -// written to this pin, with more-significant bits written to -// higher-numbered pins. +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. #define PIO_SM0_PINCTRL_SIDESET_BASE_RESET _u(0x00) #define PIO_SM0_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) #define PIO_SM0_PINCTRL_SIDESET_BASE_MSB _u(14) @@ -1177,11 +1176,11 @@ // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) -#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(4) -#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(4) -#define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(4) +#define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" #define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) #define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- @@ -1352,10 +1351,10 @@ // Description : The lowest-numbered pin that will be affected by a side-set // operation. The MSBs of an instruction's side-set/delay field // (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The -// least-significant bit of the side-set portion is the bit -// written to this pin, with more-significant bits written to -// higher-numbered pins. +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. #define PIO_SM1_PINCTRL_SIDESET_BASE_RESET _u(0x00) #define PIO_SM1_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) #define PIO_SM1_PINCTRL_SIDESET_BASE_MSB _u(14) @@ -1508,11 +1507,11 @@ // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) -#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(4) -#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(4) -#define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(4) +#define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" #define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) #define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- @@ -1683,10 +1682,10 @@ // Description : The lowest-numbered pin that will be affected by a side-set // operation. The MSBs of an instruction's side-set/delay field // (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The -// least-significant bit of the side-set portion is the bit -// written to this pin, with more-significant bits written to -// higher-numbered pins. +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. #define PIO_SM2_PINCTRL_SIDESET_BASE_RESET _u(0x00) #define PIO_SM2_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) #define PIO_SM2_PINCTRL_SIDESET_BASE_MSB _u(14) @@ -1839,11 +1838,11 @@ // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) -#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(4) -#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(4) -#define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000010) +#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(4) +#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(4) +#define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" #define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) #define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- @@ -2014,10 +2013,10 @@ // Description : The lowest-numbered pin that will be affected by a side-set // operation. The MSBs of an instruction's side-set/delay field // (up to 5, determined by SIDESET_COUNT) are used for side-set -// data, with the remaining LSBs used for delay. The -// least-significant bit of the side-set portion is the bit -// written to this pin, with more-significant bits written to -// higher-numbered pins. +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. #define PIO_SM3_PINCTRL_SIDESET_BASE_RESET _u(0x00) #define PIO_SM3_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) #define PIO_SM3_PINCTRL_SIDESET_BASE_MSB _u(14) @@ -2052,7 +2051,6 @@ #define PIO_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM3 -// Description : None #define PIO_INTR_SM3_RESET _u(0x0) #define PIO_INTR_SM3_BITS _u(0x00000800) #define PIO_INTR_SM3_MSB _u(11) @@ -2060,7 +2058,6 @@ #define PIO_INTR_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM2 -// Description : None #define PIO_INTR_SM2_RESET _u(0x0) #define PIO_INTR_SM2_BITS _u(0x00000400) #define PIO_INTR_SM2_MSB _u(10) @@ -2068,7 +2065,6 @@ #define PIO_INTR_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM1 -// Description : None #define PIO_INTR_SM1_RESET _u(0x0) #define PIO_INTR_SM1_BITS _u(0x00000200) #define PIO_INTR_SM1_MSB _u(9) @@ -2076,7 +2072,6 @@ #define PIO_INTR_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM0 -// Description : None #define PIO_INTR_SM0_RESET _u(0x0) #define PIO_INTR_SM0_BITS _u(0x00000100) #define PIO_INTR_SM0_MSB _u(8) @@ -2084,7 +2079,6 @@ #define PIO_INTR_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM3_TXNFULL -// Description : None #define PIO_INTR_SM3_TXNFULL_RESET _u(0x0) #define PIO_INTR_SM3_TXNFULL_BITS _u(0x00000080) #define PIO_INTR_SM3_TXNFULL_MSB _u(7) @@ -2092,7 +2086,6 @@ #define PIO_INTR_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM2_TXNFULL -// Description : None #define PIO_INTR_SM2_TXNFULL_RESET _u(0x0) #define PIO_INTR_SM2_TXNFULL_BITS _u(0x00000040) #define PIO_INTR_SM2_TXNFULL_MSB _u(6) @@ -2100,7 +2093,6 @@ #define PIO_INTR_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM1_TXNFULL -// Description : None #define PIO_INTR_SM1_TXNFULL_RESET _u(0x0) #define PIO_INTR_SM1_TXNFULL_BITS _u(0x00000020) #define PIO_INTR_SM1_TXNFULL_MSB _u(5) @@ -2108,7 +2100,6 @@ #define PIO_INTR_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM0_TXNFULL -// Description : None #define PIO_INTR_SM0_TXNFULL_RESET _u(0x0) #define PIO_INTR_SM0_TXNFULL_BITS _u(0x00000010) #define PIO_INTR_SM0_TXNFULL_MSB _u(4) @@ -2116,7 +2107,6 @@ #define PIO_INTR_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM3_RXNEMPTY -// Description : None #define PIO_INTR_SM3_RXNEMPTY_RESET _u(0x0) #define PIO_INTR_SM3_RXNEMPTY_BITS _u(0x00000008) #define PIO_INTR_SM3_RXNEMPTY_MSB _u(3) @@ -2124,7 +2114,6 @@ #define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM2_RXNEMPTY -// Description : None #define PIO_INTR_SM2_RXNEMPTY_RESET _u(0x0) #define PIO_INTR_SM2_RXNEMPTY_BITS _u(0x00000004) #define PIO_INTR_SM2_RXNEMPTY_MSB _u(2) @@ -2132,7 +2121,6 @@ #define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM1_RXNEMPTY -// Description : None #define PIO_INTR_SM1_RXNEMPTY_RESET _u(0x0) #define PIO_INTR_SM1_RXNEMPTY_BITS _u(0x00000002) #define PIO_INTR_SM1_RXNEMPTY_MSB _u(1) @@ -2140,7 +2128,6 @@ #define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_INTR_SM0_RXNEMPTY -// Description : None #define PIO_INTR_SM0_RXNEMPTY_RESET _u(0x0) #define PIO_INTR_SM0_RXNEMPTY_BITS _u(0x00000001) #define PIO_INTR_SM0_RXNEMPTY_MSB _u(0) @@ -2154,7 +2141,6 @@ #define PIO_IRQ0_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM3 -// Description : None #define PIO_IRQ0_INTE_SM3_RESET _u(0x0) #define PIO_IRQ0_INTE_SM3_BITS _u(0x00000800) #define PIO_IRQ0_INTE_SM3_MSB _u(11) @@ -2162,7 +2148,6 @@ #define PIO_IRQ0_INTE_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM2 -// Description : None #define PIO_IRQ0_INTE_SM2_RESET _u(0x0) #define PIO_IRQ0_INTE_SM2_BITS _u(0x00000400) #define PIO_IRQ0_INTE_SM2_MSB _u(10) @@ -2170,7 +2155,6 @@ #define PIO_IRQ0_INTE_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM1 -// Description : None #define PIO_IRQ0_INTE_SM1_RESET _u(0x0) #define PIO_IRQ0_INTE_SM1_BITS _u(0x00000200) #define PIO_IRQ0_INTE_SM1_MSB _u(9) @@ -2178,7 +2162,6 @@ #define PIO_IRQ0_INTE_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM0 -// Description : None #define PIO_IRQ0_INTE_SM0_RESET _u(0x0) #define PIO_IRQ0_INTE_SM0_BITS _u(0x00000100) #define PIO_IRQ0_INTE_SM0_MSB _u(8) @@ -2186,7 +2169,6 @@ #define PIO_IRQ0_INTE_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM3_TXNFULL -// Description : None #define PIO_IRQ0_INTE_SM3_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTE_SM3_TXNFULL_BITS _u(0x00000080) #define PIO_IRQ0_INTE_SM3_TXNFULL_MSB _u(7) @@ -2194,7 +2176,6 @@ #define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM2_TXNFULL -// Description : None #define PIO_IRQ0_INTE_SM2_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTE_SM2_TXNFULL_BITS _u(0x00000040) #define PIO_IRQ0_INTE_SM2_TXNFULL_MSB _u(6) @@ -2202,7 +2183,6 @@ #define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM1_TXNFULL -// Description : None #define PIO_IRQ0_INTE_SM1_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTE_SM1_TXNFULL_BITS _u(0x00000020) #define PIO_IRQ0_INTE_SM1_TXNFULL_MSB _u(5) @@ -2210,7 +2190,6 @@ #define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM0_TXNFULL -// Description : None #define PIO_IRQ0_INTE_SM0_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTE_SM0_TXNFULL_BITS _u(0x00000010) #define PIO_IRQ0_INTE_SM0_TXNFULL_MSB _u(4) @@ -2218,7 +2197,6 @@ #define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM3_RXNEMPTY -// Description : None #define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) #define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _u(3) @@ -2226,7 +2204,6 @@ #define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM2_RXNEMPTY -// Description : None #define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) #define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _u(2) @@ -2234,7 +2211,6 @@ #define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM1_RXNEMPTY -// Description : None #define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) #define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _u(1) @@ -2242,7 +2218,6 @@ #define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTE_SM0_RXNEMPTY -// Description : None #define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) #define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _u(0) @@ -2256,7 +2231,6 @@ #define PIO_IRQ0_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM3 -// Description : None #define PIO_IRQ0_INTF_SM3_RESET _u(0x0) #define PIO_IRQ0_INTF_SM3_BITS _u(0x00000800) #define PIO_IRQ0_INTF_SM3_MSB _u(11) @@ -2264,7 +2238,6 @@ #define PIO_IRQ0_INTF_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM2 -// Description : None #define PIO_IRQ0_INTF_SM2_RESET _u(0x0) #define PIO_IRQ0_INTF_SM2_BITS _u(0x00000400) #define PIO_IRQ0_INTF_SM2_MSB _u(10) @@ -2272,7 +2245,6 @@ #define PIO_IRQ0_INTF_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM1 -// Description : None #define PIO_IRQ0_INTF_SM1_RESET _u(0x0) #define PIO_IRQ0_INTF_SM1_BITS _u(0x00000200) #define PIO_IRQ0_INTF_SM1_MSB _u(9) @@ -2280,7 +2252,6 @@ #define PIO_IRQ0_INTF_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM0 -// Description : None #define PIO_IRQ0_INTF_SM0_RESET _u(0x0) #define PIO_IRQ0_INTF_SM0_BITS _u(0x00000100) #define PIO_IRQ0_INTF_SM0_MSB _u(8) @@ -2288,7 +2259,6 @@ #define PIO_IRQ0_INTF_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM3_TXNFULL -// Description : None #define PIO_IRQ0_INTF_SM3_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTF_SM3_TXNFULL_BITS _u(0x00000080) #define PIO_IRQ0_INTF_SM3_TXNFULL_MSB _u(7) @@ -2296,7 +2266,6 @@ #define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM2_TXNFULL -// Description : None #define PIO_IRQ0_INTF_SM2_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTF_SM2_TXNFULL_BITS _u(0x00000040) #define PIO_IRQ0_INTF_SM2_TXNFULL_MSB _u(6) @@ -2304,7 +2273,6 @@ #define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM1_TXNFULL -// Description : None #define PIO_IRQ0_INTF_SM1_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTF_SM1_TXNFULL_BITS _u(0x00000020) #define PIO_IRQ0_INTF_SM1_TXNFULL_MSB _u(5) @@ -2312,7 +2280,6 @@ #define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM0_TXNFULL -// Description : None #define PIO_IRQ0_INTF_SM0_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTF_SM0_TXNFULL_BITS _u(0x00000010) #define PIO_IRQ0_INTF_SM0_TXNFULL_MSB _u(4) @@ -2320,7 +2287,6 @@ #define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM3_RXNEMPTY -// Description : None #define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) #define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _u(3) @@ -2328,7 +2294,6 @@ #define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM2_RXNEMPTY -// Description : None #define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) #define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _u(2) @@ -2336,7 +2301,6 @@ #define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM1_RXNEMPTY -// Description : None #define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) #define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _u(1) @@ -2344,7 +2308,6 @@ #define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTF_SM0_RXNEMPTY -// Description : None #define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) #define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _u(0) @@ -2358,7 +2321,6 @@ #define PIO_IRQ0_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM3 -// Description : None #define PIO_IRQ0_INTS_SM3_RESET _u(0x0) #define PIO_IRQ0_INTS_SM3_BITS _u(0x00000800) #define PIO_IRQ0_INTS_SM3_MSB _u(11) @@ -2366,7 +2328,6 @@ #define PIO_IRQ0_INTS_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM2 -// Description : None #define PIO_IRQ0_INTS_SM2_RESET _u(0x0) #define PIO_IRQ0_INTS_SM2_BITS _u(0x00000400) #define PIO_IRQ0_INTS_SM2_MSB _u(10) @@ -2374,7 +2335,6 @@ #define PIO_IRQ0_INTS_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM1 -// Description : None #define PIO_IRQ0_INTS_SM1_RESET _u(0x0) #define PIO_IRQ0_INTS_SM1_BITS _u(0x00000200) #define PIO_IRQ0_INTS_SM1_MSB _u(9) @@ -2382,7 +2342,6 @@ #define PIO_IRQ0_INTS_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM0 -// Description : None #define PIO_IRQ0_INTS_SM0_RESET _u(0x0) #define PIO_IRQ0_INTS_SM0_BITS _u(0x00000100) #define PIO_IRQ0_INTS_SM0_MSB _u(8) @@ -2390,7 +2349,6 @@ #define PIO_IRQ0_INTS_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM3_TXNFULL -// Description : None #define PIO_IRQ0_INTS_SM3_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTS_SM3_TXNFULL_BITS _u(0x00000080) #define PIO_IRQ0_INTS_SM3_TXNFULL_MSB _u(7) @@ -2398,7 +2356,6 @@ #define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM2_TXNFULL -// Description : None #define PIO_IRQ0_INTS_SM2_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTS_SM2_TXNFULL_BITS _u(0x00000040) #define PIO_IRQ0_INTS_SM2_TXNFULL_MSB _u(6) @@ -2406,7 +2363,6 @@ #define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM1_TXNFULL -// Description : None #define PIO_IRQ0_INTS_SM1_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTS_SM1_TXNFULL_BITS _u(0x00000020) #define PIO_IRQ0_INTS_SM1_TXNFULL_MSB _u(5) @@ -2414,7 +2370,6 @@ #define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM0_TXNFULL -// Description : None #define PIO_IRQ0_INTS_SM0_TXNFULL_RESET _u(0x0) #define PIO_IRQ0_INTS_SM0_TXNFULL_BITS _u(0x00000010) #define PIO_IRQ0_INTS_SM0_TXNFULL_MSB _u(4) @@ -2422,7 +2377,6 @@ #define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM3_RXNEMPTY -// Description : None #define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) #define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _u(3) @@ -2430,7 +2384,6 @@ #define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM2_RXNEMPTY -// Description : None #define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) #define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _u(2) @@ -2438,7 +2391,6 @@ #define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM1_RXNEMPTY -// Description : None #define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) #define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _u(1) @@ -2446,7 +2398,6 @@ #define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ0_INTS_SM0_RXNEMPTY -// Description : None #define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) #define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _u(0) @@ -2460,7 +2411,6 @@ #define PIO_IRQ1_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM3 -// Description : None #define PIO_IRQ1_INTE_SM3_RESET _u(0x0) #define PIO_IRQ1_INTE_SM3_BITS _u(0x00000800) #define PIO_IRQ1_INTE_SM3_MSB _u(11) @@ -2468,7 +2418,6 @@ #define PIO_IRQ1_INTE_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM2 -// Description : None #define PIO_IRQ1_INTE_SM2_RESET _u(0x0) #define PIO_IRQ1_INTE_SM2_BITS _u(0x00000400) #define PIO_IRQ1_INTE_SM2_MSB _u(10) @@ -2476,7 +2425,6 @@ #define PIO_IRQ1_INTE_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM1 -// Description : None #define PIO_IRQ1_INTE_SM1_RESET _u(0x0) #define PIO_IRQ1_INTE_SM1_BITS _u(0x00000200) #define PIO_IRQ1_INTE_SM1_MSB _u(9) @@ -2484,7 +2432,6 @@ #define PIO_IRQ1_INTE_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM0 -// Description : None #define PIO_IRQ1_INTE_SM0_RESET _u(0x0) #define PIO_IRQ1_INTE_SM0_BITS _u(0x00000100) #define PIO_IRQ1_INTE_SM0_MSB _u(8) @@ -2492,7 +2439,6 @@ #define PIO_IRQ1_INTE_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM3_TXNFULL -// Description : None #define PIO_IRQ1_INTE_SM3_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTE_SM3_TXNFULL_BITS _u(0x00000080) #define PIO_IRQ1_INTE_SM3_TXNFULL_MSB _u(7) @@ -2500,7 +2446,6 @@ #define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM2_TXNFULL -// Description : None #define PIO_IRQ1_INTE_SM2_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTE_SM2_TXNFULL_BITS _u(0x00000040) #define PIO_IRQ1_INTE_SM2_TXNFULL_MSB _u(6) @@ -2508,7 +2453,6 @@ #define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM1_TXNFULL -// Description : None #define PIO_IRQ1_INTE_SM1_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTE_SM1_TXNFULL_BITS _u(0x00000020) #define PIO_IRQ1_INTE_SM1_TXNFULL_MSB _u(5) @@ -2516,7 +2460,6 @@ #define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM0_TXNFULL -// Description : None #define PIO_IRQ1_INTE_SM0_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTE_SM0_TXNFULL_BITS _u(0x00000010) #define PIO_IRQ1_INTE_SM0_TXNFULL_MSB _u(4) @@ -2524,7 +2467,6 @@ #define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM3_RXNEMPTY -// Description : None #define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) #define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _u(3) @@ -2532,7 +2474,6 @@ #define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM2_RXNEMPTY -// Description : None #define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) #define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _u(2) @@ -2540,7 +2481,6 @@ #define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM1_RXNEMPTY -// Description : None #define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) #define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _u(1) @@ -2548,7 +2488,6 @@ #define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTE_SM0_RXNEMPTY -// Description : None #define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) #define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _u(0) @@ -2562,7 +2501,6 @@ #define PIO_IRQ1_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM3 -// Description : None #define PIO_IRQ1_INTF_SM3_RESET _u(0x0) #define PIO_IRQ1_INTF_SM3_BITS _u(0x00000800) #define PIO_IRQ1_INTF_SM3_MSB _u(11) @@ -2570,7 +2508,6 @@ #define PIO_IRQ1_INTF_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM2 -// Description : None #define PIO_IRQ1_INTF_SM2_RESET _u(0x0) #define PIO_IRQ1_INTF_SM2_BITS _u(0x00000400) #define PIO_IRQ1_INTF_SM2_MSB _u(10) @@ -2578,7 +2515,6 @@ #define PIO_IRQ1_INTF_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM1 -// Description : None #define PIO_IRQ1_INTF_SM1_RESET _u(0x0) #define PIO_IRQ1_INTF_SM1_BITS _u(0x00000200) #define PIO_IRQ1_INTF_SM1_MSB _u(9) @@ -2586,7 +2522,6 @@ #define PIO_IRQ1_INTF_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM0 -// Description : None #define PIO_IRQ1_INTF_SM0_RESET _u(0x0) #define PIO_IRQ1_INTF_SM0_BITS _u(0x00000100) #define PIO_IRQ1_INTF_SM0_MSB _u(8) @@ -2594,7 +2529,6 @@ #define PIO_IRQ1_INTF_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM3_TXNFULL -// Description : None #define PIO_IRQ1_INTF_SM3_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTF_SM3_TXNFULL_BITS _u(0x00000080) #define PIO_IRQ1_INTF_SM3_TXNFULL_MSB _u(7) @@ -2602,7 +2536,6 @@ #define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM2_TXNFULL -// Description : None #define PIO_IRQ1_INTF_SM2_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTF_SM2_TXNFULL_BITS _u(0x00000040) #define PIO_IRQ1_INTF_SM2_TXNFULL_MSB _u(6) @@ -2610,7 +2543,6 @@ #define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM1_TXNFULL -// Description : None #define PIO_IRQ1_INTF_SM1_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTF_SM1_TXNFULL_BITS _u(0x00000020) #define PIO_IRQ1_INTF_SM1_TXNFULL_MSB _u(5) @@ -2618,7 +2550,6 @@ #define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM0_TXNFULL -// Description : None #define PIO_IRQ1_INTF_SM0_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTF_SM0_TXNFULL_BITS _u(0x00000010) #define PIO_IRQ1_INTF_SM0_TXNFULL_MSB _u(4) @@ -2626,7 +2557,6 @@ #define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM3_RXNEMPTY -// Description : None #define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) #define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _u(3) @@ -2634,7 +2564,6 @@ #define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM2_RXNEMPTY -// Description : None #define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) #define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _u(2) @@ -2642,7 +2571,6 @@ #define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM1_RXNEMPTY -// Description : None #define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) #define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _u(1) @@ -2650,7 +2578,6 @@ #define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTF_SM0_RXNEMPTY -// Description : None #define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) #define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _u(0) @@ -2664,7 +2591,6 @@ #define PIO_IRQ1_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM3 -// Description : None #define PIO_IRQ1_INTS_SM3_RESET _u(0x0) #define PIO_IRQ1_INTS_SM3_BITS _u(0x00000800) #define PIO_IRQ1_INTS_SM3_MSB _u(11) @@ -2672,7 +2598,6 @@ #define PIO_IRQ1_INTS_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM2 -// Description : None #define PIO_IRQ1_INTS_SM2_RESET _u(0x0) #define PIO_IRQ1_INTS_SM2_BITS _u(0x00000400) #define PIO_IRQ1_INTS_SM2_MSB _u(10) @@ -2680,7 +2605,6 @@ #define PIO_IRQ1_INTS_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM1 -// Description : None #define PIO_IRQ1_INTS_SM1_RESET _u(0x0) #define PIO_IRQ1_INTS_SM1_BITS _u(0x00000200) #define PIO_IRQ1_INTS_SM1_MSB _u(9) @@ -2688,7 +2612,6 @@ #define PIO_IRQ1_INTS_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM0 -// Description : None #define PIO_IRQ1_INTS_SM0_RESET _u(0x0) #define PIO_IRQ1_INTS_SM0_BITS _u(0x00000100) #define PIO_IRQ1_INTS_SM0_MSB _u(8) @@ -2696,7 +2619,6 @@ #define PIO_IRQ1_INTS_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM3_TXNFULL -// Description : None #define PIO_IRQ1_INTS_SM3_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTS_SM3_TXNFULL_BITS _u(0x00000080) #define PIO_IRQ1_INTS_SM3_TXNFULL_MSB _u(7) @@ -2704,7 +2626,6 @@ #define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM2_TXNFULL -// Description : None #define PIO_IRQ1_INTS_SM2_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTS_SM2_TXNFULL_BITS _u(0x00000040) #define PIO_IRQ1_INTS_SM2_TXNFULL_MSB _u(6) @@ -2712,7 +2633,6 @@ #define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM1_TXNFULL -// Description : None #define PIO_IRQ1_INTS_SM1_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTS_SM1_TXNFULL_BITS _u(0x00000020) #define PIO_IRQ1_INTS_SM1_TXNFULL_MSB _u(5) @@ -2720,7 +2640,6 @@ #define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM0_TXNFULL -// Description : None #define PIO_IRQ1_INTS_SM0_TXNFULL_RESET _u(0x0) #define PIO_IRQ1_INTS_SM0_TXNFULL_BITS _u(0x00000010) #define PIO_IRQ1_INTS_SM0_TXNFULL_MSB _u(4) @@ -2728,7 +2647,6 @@ #define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM3_RXNEMPTY -// Description : None #define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) #define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _u(3) @@ -2736,7 +2654,6 @@ #define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM2_RXNEMPTY -// Description : None #define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) #define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _u(2) @@ -2744,7 +2661,6 @@ #define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM1_RXNEMPTY -// Description : None #define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) #define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _u(1) @@ -2752,11 +2668,11 @@ #define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PIO_IRQ1_INTS_SM0_RXNEMPTY -// Description : None #define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _u(0x0) #define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) #define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _u(0) #define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _u(0) #define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_PIO_DEFINED +#endif // _HARDWARE_REGS_PIO_H + diff --git a/lib/rp2040/hardware/regs/pll.h b/lib/pico-sdk/rp2040/hardware/regs/pll.h similarity index 95% rename from lib/rp2040/hardware/regs/pll.h rename to lib/pico-sdk/rp2040/hardware/regs/pll.h index a0f5ad0efcd4..345982e85970 100644 --- a/lib/rp2040/hardware/regs/pll.h +++ b/lib/pico-sdk/rp2040/hardware/regs/pll.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,17 +9,16 @@ // Register block : PLL // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_PLL_DEFINED -#define HARDWARE_REGS_PLL_DEFINED +#ifndef _HARDWARE_REGS_PLL_H +#define _HARDWARE_REGS_PLL_H // ============================================================================= // Register : PLL_CS // Description : Control and Status // GENERAL CONSTRAINTS: // Reference clock frequency min=5MHz, max=800MHz // Feedback divider min=16, max=320 -// VCO frequency min=400MHz, max=1600MHz +// VCO frequency min=750MHz, max=1600MHz #define PLL_CS_OFFSET _u(0x00000000) #define PLL_CS_BITS _u(0x8000013f) #define PLL_CS_RESET _u(0x00000001) @@ -132,4 +133,5 @@ #define PLL_PRIM_POSTDIV2_LSB _u(12) #define PLL_PRIM_POSTDIV2_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_PLL_DEFINED +#endif // _HARDWARE_REGS_PLL_H + diff --git a/lib/rp2040/hardware/regs/psm.h b/lib/pico-sdk/rp2040/hardware/regs/psm.h similarity index 93% rename from lib/rp2040/hardware/regs/psm.h rename to lib/pico-sdk/rp2040/hardware/regs/psm.h index 8810ae8bbb1b..3433f6dc4e49 100644 --- a/lib/rp2040/hardware/regs/psm.h +++ b/lib/pico-sdk/rp2040/hardware/regs/psm.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : PSM // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_PSM_DEFINED -#define HARDWARE_REGS_PSM_DEFINED +#ifndef _HARDWARE_REGS_PSM_H +#define _HARDWARE_REGS_PSM_H // ============================================================================= // Register : PSM_FRCE_ON // Description : Force block out of reset (i.e. power it on) @@ -19,7 +20,6 @@ #define PSM_FRCE_ON_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_PROC1 -// Description : None #define PSM_FRCE_ON_PROC1_RESET _u(0x0) #define PSM_FRCE_ON_PROC1_BITS _u(0x00010000) #define PSM_FRCE_ON_PROC1_MSB _u(16) @@ -27,7 +27,6 @@ #define PSM_FRCE_ON_PROC1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_PROC0 -// Description : None #define PSM_FRCE_ON_PROC0_RESET _u(0x0) #define PSM_FRCE_ON_PROC0_BITS _u(0x00008000) #define PSM_FRCE_ON_PROC0_MSB _u(15) @@ -35,7 +34,6 @@ #define PSM_FRCE_ON_PROC0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SIO -// Description : None #define PSM_FRCE_ON_SIO_RESET _u(0x0) #define PSM_FRCE_ON_SIO_BITS _u(0x00004000) #define PSM_FRCE_ON_SIO_MSB _u(14) @@ -43,7 +41,6 @@ #define PSM_FRCE_ON_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET -// Description : None #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET _u(0x0) #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS _u(0x00002000) #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB _u(13) @@ -51,7 +48,6 @@ #define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_XIP -// Description : None #define PSM_FRCE_ON_XIP_RESET _u(0x0) #define PSM_FRCE_ON_XIP_BITS _u(0x00001000) #define PSM_FRCE_ON_XIP_MSB _u(12) @@ -59,7 +55,6 @@ #define PSM_FRCE_ON_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM5 -// Description : None #define PSM_FRCE_ON_SRAM5_RESET _u(0x0) #define PSM_FRCE_ON_SRAM5_BITS _u(0x00000800) #define PSM_FRCE_ON_SRAM5_MSB _u(11) @@ -67,7 +62,6 @@ #define PSM_FRCE_ON_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM4 -// Description : None #define PSM_FRCE_ON_SRAM4_RESET _u(0x0) #define PSM_FRCE_ON_SRAM4_BITS _u(0x00000400) #define PSM_FRCE_ON_SRAM4_MSB _u(10) @@ -75,7 +69,6 @@ #define PSM_FRCE_ON_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM3 -// Description : None #define PSM_FRCE_ON_SRAM3_RESET _u(0x0) #define PSM_FRCE_ON_SRAM3_BITS _u(0x00000200) #define PSM_FRCE_ON_SRAM3_MSB _u(9) @@ -83,7 +76,6 @@ #define PSM_FRCE_ON_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM2 -// Description : None #define PSM_FRCE_ON_SRAM2_RESET _u(0x0) #define PSM_FRCE_ON_SRAM2_BITS _u(0x00000100) #define PSM_FRCE_ON_SRAM2_MSB _u(8) @@ -91,7 +83,6 @@ #define PSM_FRCE_ON_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM1 -// Description : None #define PSM_FRCE_ON_SRAM1_RESET _u(0x0) #define PSM_FRCE_ON_SRAM1_BITS _u(0x00000080) #define PSM_FRCE_ON_SRAM1_MSB _u(7) @@ -99,7 +90,6 @@ #define PSM_FRCE_ON_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_SRAM0 -// Description : None #define PSM_FRCE_ON_SRAM0_RESET _u(0x0) #define PSM_FRCE_ON_SRAM0_BITS _u(0x00000040) #define PSM_FRCE_ON_SRAM0_MSB _u(6) @@ -107,7 +97,6 @@ #define PSM_FRCE_ON_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_ROM -// Description : None #define PSM_FRCE_ON_ROM_RESET _u(0x0) #define PSM_FRCE_ON_ROM_BITS _u(0x00000020) #define PSM_FRCE_ON_ROM_MSB _u(5) @@ -115,7 +104,6 @@ #define PSM_FRCE_ON_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_BUSFABRIC -// Description : None #define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0) #define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000010) #define PSM_FRCE_ON_BUSFABRIC_MSB _u(4) @@ -123,7 +111,6 @@ #define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_RESETS -// Description : None #define PSM_FRCE_ON_RESETS_RESET _u(0x0) #define PSM_FRCE_ON_RESETS_BITS _u(0x00000008) #define PSM_FRCE_ON_RESETS_MSB _u(3) @@ -131,7 +118,6 @@ #define PSM_FRCE_ON_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_CLOCKS -// Description : None #define PSM_FRCE_ON_CLOCKS_RESET _u(0x0) #define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000004) #define PSM_FRCE_ON_CLOCKS_MSB _u(2) @@ -139,7 +125,6 @@ #define PSM_FRCE_ON_CLOCKS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_XOSC -// Description : None #define PSM_FRCE_ON_XOSC_RESET _u(0x0) #define PSM_FRCE_ON_XOSC_BITS _u(0x00000002) #define PSM_FRCE_ON_XOSC_MSB _u(1) @@ -147,7 +132,6 @@ #define PSM_FRCE_ON_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_ON_ROSC -// Description : None #define PSM_FRCE_ON_ROSC_RESET _u(0x0) #define PSM_FRCE_ON_ROSC_BITS _u(0x00000001) #define PSM_FRCE_ON_ROSC_MSB _u(0) @@ -161,7 +145,6 @@ #define PSM_FRCE_OFF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_PROC1 -// Description : None #define PSM_FRCE_OFF_PROC1_RESET _u(0x0) #define PSM_FRCE_OFF_PROC1_BITS _u(0x00010000) #define PSM_FRCE_OFF_PROC1_MSB _u(16) @@ -169,7 +152,6 @@ #define PSM_FRCE_OFF_PROC1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_PROC0 -// Description : None #define PSM_FRCE_OFF_PROC0_RESET _u(0x0) #define PSM_FRCE_OFF_PROC0_BITS _u(0x00008000) #define PSM_FRCE_OFF_PROC0_MSB _u(15) @@ -177,7 +159,6 @@ #define PSM_FRCE_OFF_PROC0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SIO -// Description : None #define PSM_FRCE_OFF_SIO_RESET _u(0x0) #define PSM_FRCE_OFF_SIO_BITS _u(0x00004000) #define PSM_FRCE_OFF_SIO_MSB _u(14) @@ -185,7 +166,6 @@ #define PSM_FRCE_OFF_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET -// Description : None #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET _u(0x0) #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS _u(0x00002000) #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB _u(13) @@ -193,7 +173,6 @@ #define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_XIP -// Description : None #define PSM_FRCE_OFF_XIP_RESET _u(0x0) #define PSM_FRCE_OFF_XIP_BITS _u(0x00001000) #define PSM_FRCE_OFF_XIP_MSB _u(12) @@ -201,7 +180,6 @@ #define PSM_FRCE_OFF_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM5 -// Description : None #define PSM_FRCE_OFF_SRAM5_RESET _u(0x0) #define PSM_FRCE_OFF_SRAM5_BITS _u(0x00000800) #define PSM_FRCE_OFF_SRAM5_MSB _u(11) @@ -209,7 +187,6 @@ #define PSM_FRCE_OFF_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM4 -// Description : None #define PSM_FRCE_OFF_SRAM4_RESET _u(0x0) #define PSM_FRCE_OFF_SRAM4_BITS _u(0x00000400) #define PSM_FRCE_OFF_SRAM4_MSB _u(10) @@ -217,7 +194,6 @@ #define PSM_FRCE_OFF_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM3 -// Description : None #define PSM_FRCE_OFF_SRAM3_RESET _u(0x0) #define PSM_FRCE_OFF_SRAM3_BITS _u(0x00000200) #define PSM_FRCE_OFF_SRAM3_MSB _u(9) @@ -225,7 +201,6 @@ #define PSM_FRCE_OFF_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM2 -// Description : None #define PSM_FRCE_OFF_SRAM2_RESET _u(0x0) #define PSM_FRCE_OFF_SRAM2_BITS _u(0x00000100) #define PSM_FRCE_OFF_SRAM2_MSB _u(8) @@ -233,7 +208,6 @@ #define PSM_FRCE_OFF_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM1 -// Description : None #define PSM_FRCE_OFF_SRAM1_RESET _u(0x0) #define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000080) #define PSM_FRCE_OFF_SRAM1_MSB _u(7) @@ -241,7 +215,6 @@ #define PSM_FRCE_OFF_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_SRAM0 -// Description : None #define PSM_FRCE_OFF_SRAM0_RESET _u(0x0) #define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000040) #define PSM_FRCE_OFF_SRAM0_MSB _u(6) @@ -249,7 +222,6 @@ #define PSM_FRCE_OFF_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_ROM -// Description : None #define PSM_FRCE_OFF_ROM_RESET _u(0x0) #define PSM_FRCE_OFF_ROM_BITS _u(0x00000020) #define PSM_FRCE_OFF_ROM_MSB _u(5) @@ -257,7 +229,6 @@ #define PSM_FRCE_OFF_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_BUSFABRIC -// Description : None #define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0) #define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000010) #define PSM_FRCE_OFF_BUSFABRIC_MSB _u(4) @@ -265,7 +236,6 @@ #define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_RESETS -// Description : None #define PSM_FRCE_OFF_RESETS_RESET _u(0x0) #define PSM_FRCE_OFF_RESETS_BITS _u(0x00000008) #define PSM_FRCE_OFF_RESETS_MSB _u(3) @@ -273,7 +243,6 @@ #define PSM_FRCE_OFF_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_CLOCKS -// Description : None #define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0) #define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000004) #define PSM_FRCE_OFF_CLOCKS_MSB _u(2) @@ -281,7 +250,6 @@ #define PSM_FRCE_OFF_CLOCKS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_XOSC -// Description : None #define PSM_FRCE_OFF_XOSC_RESET _u(0x0) #define PSM_FRCE_OFF_XOSC_BITS _u(0x00000002) #define PSM_FRCE_OFF_XOSC_MSB _u(1) @@ -289,7 +257,6 @@ #define PSM_FRCE_OFF_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_FRCE_OFF_ROSC -// Description : None #define PSM_FRCE_OFF_ROSC_RESET _u(0x0) #define PSM_FRCE_OFF_ROSC_BITS _u(0x00000001) #define PSM_FRCE_OFF_ROSC_MSB _u(0) @@ -304,7 +271,6 @@ #define PSM_WDSEL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_PROC1 -// Description : None #define PSM_WDSEL_PROC1_RESET _u(0x0) #define PSM_WDSEL_PROC1_BITS _u(0x00010000) #define PSM_WDSEL_PROC1_MSB _u(16) @@ -312,7 +278,6 @@ #define PSM_WDSEL_PROC1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_PROC0 -// Description : None #define PSM_WDSEL_PROC0_RESET _u(0x0) #define PSM_WDSEL_PROC0_BITS _u(0x00008000) #define PSM_WDSEL_PROC0_MSB _u(15) @@ -320,7 +285,6 @@ #define PSM_WDSEL_PROC0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SIO -// Description : None #define PSM_WDSEL_SIO_RESET _u(0x0) #define PSM_WDSEL_SIO_BITS _u(0x00004000) #define PSM_WDSEL_SIO_MSB _u(14) @@ -328,7 +292,6 @@ #define PSM_WDSEL_SIO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_VREG_AND_CHIP_RESET -// Description : None #define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET _u(0x0) #define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS _u(0x00002000) #define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB _u(13) @@ -336,7 +299,6 @@ #define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_XIP -// Description : None #define PSM_WDSEL_XIP_RESET _u(0x0) #define PSM_WDSEL_XIP_BITS _u(0x00001000) #define PSM_WDSEL_XIP_MSB _u(12) @@ -344,7 +306,6 @@ #define PSM_WDSEL_XIP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM5 -// Description : None #define PSM_WDSEL_SRAM5_RESET _u(0x0) #define PSM_WDSEL_SRAM5_BITS _u(0x00000800) #define PSM_WDSEL_SRAM5_MSB _u(11) @@ -352,7 +313,6 @@ #define PSM_WDSEL_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM4 -// Description : None #define PSM_WDSEL_SRAM4_RESET _u(0x0) #define PSM_WDSEL_SRAM4_BITS _u(0x00000400) #define PSM_WDSEL_SRAM4_MSB _u(10) @@ -360,7 +320,6 @@ #define PSM_WDSEL_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM3 -// Description : None #define PSM_WDSEL_SRAM3_RESET _u(0x0) #define PSM_WDSEL_SRAM3_BITS _u(0x00000200) #define PSM_WDSEL_SRAM3_MSB _u(9) @@ -368,7 +327,6 @@ #define PSM_WDSEL_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM2 -// Description : None #define PSM_WDSEL_SRAM2_RESET _u(0x0) #define PSM_WDSEL_SRAM2_BITS _u(0x00000100) #define PSM_WDSEL_SRAM2_MSB _u(8) @@ -376,7 +334,6 @@ #define PSM_WDSEL_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM1 -// Description : None #define PSM_WDSEL_SRAM1_RESET _u(0x0) #define PSM_WDSEL_SRAM1_BITS _u(0x00000080) #define PSM_WDSEL_SRAM1_MSB _u(7) @@ -384,7 +341,6 @@ #define PSM_WDSEL_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_SRAM0 -// Description : None #define PSM_WDSEL_SRAM0_RESET _u(0x0) #define PSM_WDSEL_SRAM0_BITS _u(0x00000040) #define PSM_WDSEL_SRAM0_MSB _u(6) @@ -392,7 +348,6 @@ #define PSM_WDSEL_SRAM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_ROM -// Description : None #define PSM_WDSEL_ROM_RESET _u(0x0) #define PSM_WDSEL_ROM_BITS _u(0x00000020) #define PSM_WDSEL_ROM_MSB _u(5) @@ -400,7 +355,6 @@ #define PSM_WDSEL_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_BUSFABRIC -// Description : None #define PSM_WDSEL_BUSFABRIC_RESET _u(0x0) #define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000010) #define PSM_WDSEL_BUSFABRIC_MSB _u(4) @@ -408,7 +362,6 @@ #define PSM_WDSEL_BUSFABRIC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_RESETS -// Description : None #define PSM_WDSEL_RESETS_RESET _u(0x0) #define PSM_WDSEL_RESETS_BITS _u(0x00000008) #define PSM_WDSEL_RESETS_MSB _u(3) @@ -416,7 +369,6 @@ #define PSM_WDSEL_RESETS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_CLOCKS -// Description : None #define PSM_WDSEL_CLOCKS_RESET _u(0x0) #define PSM_WDSEL_CLOCKS_BITS _u(0x00000004) #define PSM_WDSEL_CLOCKS_MSB _u(2) @@ -424,7 +376,6 @@ #define PSM_WDSEL_CLOCKS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_XOSC -// Description : None #define PSM_WDSEL_XOSC_RESET _u(0x0) #define PSM_WDSEL_XOSC_BITS _u(0x00000002) #define PSM_WDSEL_XOSC_MSB _u(1) @@ -432,7 +383,6 @@ #define PSM_WDSEL_XOSC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PSM_WDSEL_ROSC -// Description : None #define PSM_WDSEL_ROSC_RESET _u(0x0) #define PSM_WDSEL_ROSC_BITS _u(0x00000001) #define PSM_WDSEL_ROSC_MSB _u(0) @@ -446,7 +396,6 @@ #define PSM_DONE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PSM_DONE_PROC1 -// Description : None #define PSM_DONE_PROC1_RESET _u(0x0) #define PSM_DONE_PROC1_BITS _u(0x00010000) #define PSM_DONE_PROC1_MSB _u(16) @@ -454,7 +403,6 @@ #define PSM_DONE_PROC1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_PROC0 -// Description : None #define PSM_DONE_PROC0_RESET _u(0x0) #define PSM_DONE_PROC0_BITS _u(0x00008000) #define PSM_DONE_PROC0_MSB _u(15) @@ -462,7 +410,6 @@ #define PSM_DONE_PROC0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SIO -// Description : None #define PSM_DONE_SIO_RESET _u(0x0) #define PSM_DONE_SIO_BITS _u(0x00004000) #define PSM_DONE_SIO_MSB _u(14) @@ -470,7 +417,6 @@ #define PSM_DONE_SIO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_VREG_AND_CHIP_RESET -// Description : None #define PSM_DONE_VREG_AND_CHIP_RESET_RESET _u(0x0) #define PSM_DONE_VREG_AND_CHIP_RESET_BITS _u(0x00002000) #define PSM_DONE_VREG_AND_CHIP_RESET_MSB _u(13) @@ -478,7 +424,6 @@ #define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_XIP -// Description : None #define PSM_DONE_XIP_RESET _u(0x0) #define PSM_DONE_XIP_BITS _u(0x00001000) #define PSM_DONE_XIP_MSB _u(12) @@ -486,7 +431,6 @@ #define PSM_DONE_XIP_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM5 -// Description : None #define PSM_DONE_SRAM5_RESET _u(0x0) #define PSM_DONE_SRAM5_BITS _u(0x00000800) #define PSM_DONE_SRAM5_MSB _u(11) @@ -494,7 +438,6 @@ #define PSM_DONE_SRAM5_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM4 -// Description : None #define PSM_DONE_SRAM4_RESET _u(0x0) #define PSM_DONE_SRAM4_BITS _u(0x00000400) #define PSM_DONE_SRAM4_MSB _u(10) @@ -502,7 +445,6 @@ #define PSM_DONE_SRAM4_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM3 -// Description : None #define PSM_DONE_SRAM3_RESET _u(0x0) #define PSM_DONE_SRAM3_BITS _u(0x00000200) #define PSM_DONE_SRAM3_MSB _u(9) @@ -510,7 +452,6 @@ #define PSM_DONE_SRAM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM2 -// Description : None #define PSM_DONE_SRAM2_RESET _u(0x0) #define PSM_DONE_SRAM2_BITS _u(0x00000100) #define PSM_DONE_SRAM2_MSB _u(8) @@ -518,7 +459,6 @@ #define PSM_DONE_SRAM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM1 -// Description : None #define PSM_DONE_SRAM1_RESET _u(0x0) #define PSM_DONE_SRAM1_BITS _u(0x00000080) #define PSM_DONE_SRAM1_MSB _u(7) @@ -526,7 +466,6 @@ #define PSM_DONE_SRAM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_SRAM0 -// Description : None #define PSM_DONE_SRAM0_RESET _u(0x0) #define PSM_DONE_SRAM0_BITS _u(0x00000040) #define PSM_DONE_SRAM0_MSB _u(6) @@ -534,7 +473,6 @@ #define PSM_DONE_SRAM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_ROM -// Description : None #define PSM_DONE_ROM_RESET _u(0x0) #define PSM_DONE_ROM_BITS _u(0x00000020) #define PSM_DONE_ROM_MSB _u(5) @@ -542,7 +480,6 @@ #define PSM_DONE_ROM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_BUSFABRIC -// Description : None #define PSM_DONE_BUSFABRIC_RESET _u(0x0) #define PSM_DONE_BUSFABRIC_BITS _u(0x00000010) #define PSM_DONE_BUSFABRIC_MSB _u(4) @@ -550,7 +487,6 @@ #define PSM_DONE_BUSFABRIC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_RESETS -// Description : None #define PSM_DONE_RESETS_RESET _u(0x0) #define PSM_DONE_RESETS_BITS _u(0x00000008) #define PSM_DONE_RESETS_MSB _u(3) @@ -558,7 +494,6 @@ #define PSM_DONE_RESETS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_CLOCKS -// Description : None #define PSM_DONE_CLOCKS_RESET _u(0x0) #define PSM_DONE_CLOCKS_BITS _u(0x00000004) #define PSM_DONE_CLOCKS_MSB _u(2) @@ -566,7 +501,6 @@ #define PSM_DONE_CLOCKS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_XOSC -// Description : None #define PSM_DONE_XOSC_RESET _u(0x0) #define PSM_DONE_XOSC_BITS _u(0x00000002) #define PSM_DONE_XOSC_MSB _u(1) @@ -574,11 +508,11 @@ #define PSM_DONE_XOSC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PSM_DONE_ROSC -// Description : None #define PSM_DONE_ROSC_RESET _u(0x0) #define PSM_DONE_ROSC_BITS _u(0x00000001) #define PSM_DONE_ROSC_MSB _u(0) #define PSM_DONE_ROSC_LSB _u(0) #define PSM_DONE_ROSC_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_PSM_DEFINED +#endif // _HARDWARE_REGS_PSM_H + diff --git a/lib/rp2040/hardware/regs/pwm.h b/lib/pico-sdk/rp2040/hardware/regs/pwm.h similarity index 91% rename from lib/rp2040/hardware/regs/pwm.h rename to lib/pico-sdk/rp2040/hardware/regs/pwm.h index a853597877e3..29a24f8d0742 100644 --- a/lib/rp2040/hardware/regs/pwm.h +++ b/lib/pico-sdk/rp2040/hardware/regs/pwm.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : apb // Description : Simple PWM // ============================================================================= -#ifndef HARDWARE_REGS_PWM_DEFINED -#define HARDWARE_REGS_PWM_DEFINED +#ifndef _HARDWARE_REGS_PWM_H +#define _HARDWARE_REGS_PWM_H // ============================================================================= // Register : PWM_CH0_CSR // Description : Control and status register @@ -42,21 +44,19 @@ #define PWM_CH0_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH0_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH0_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH0_CSR_DIVMODE_MSB _u(5) -#define PWM_CH0_CSR_DIVMODE_LSB _u(4) -#define PWM_CH0_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH0_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH0_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH0_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH0_CSR_DIVMODE_MSB _u(5) +#define PWM_CH0_CSR_DIVMODE_LSB _u(4) +#define PWM_CH0_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH0_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH0_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH0_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH0_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH0_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH0_CSR_B_INV // Description : Invert output B @@ -99,7 +99,6 @@ #define PWM_CH0_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH0_DIV_INT -// Description : None #define PWM_CH0_DIV_INT_RESET _u(0x01) #define PWM_CH0_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH0_DIV_INT_MSB _u(11) @@ -107,7 +106,6 @@ #define PWM_CH0_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH0_DIV_FRAC -// Description : None #define PWM_CH0_DIV_FRAC_RESET _u(0x0) #define PWM_CH0_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH0_DIV_FRAC_MSB _u(3) @@ -130,7 +128,6 @@ #define PWM_CH0_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH0_CC_B -// Description : None #define PWM_CH0_CC_B_RESET _u(0x0000) #define PWM_CH0_CC_B_BITS _u(0xffff0000) #define PWM_CH0_CC_B_MSB _u(31) @@ -138,7 +135,6 @@ #define PWM_CH0_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH0_CC_A -// Description : None #define PWM_CH0_CC_A_RESET _u(0x0000) #define PWM_CH0_CC_A_BITS _u(0x0000ffff) #define PWM_CH0_CC_A_MSB _u(15) @@ -184,21 +180,19 @@ #define PWM_CH1_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH1_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH1_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH1_CSR_DIVMODE_MSB _u(5) -#define PWM_CH1_CSR_DIVMODE_LSB _u(4) -#define PWM_CH1_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH1_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH1_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH1_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH1_CSR_DIVMODE_MSB _u(5) +#define PWM_CH1_CSR_DIVMODE_LSB _u(4) +#define PWM_CH1_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH1_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH1_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH1_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH1_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH1_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH1_CSR_B_INV // Description : Invert output B @@ -241,7 +235,6 @@ #define PWM_CH1_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH1_DIV_INT -// Description : None #define PWM_CH1_DIV_INT_RESET _u(0x01) #define PWM_CH1_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH1_DIV_INT_MSB _u(11) @@ -249,7 +242,6 @@ #define PWM_CH1_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH1_DIV_FRAC -// Description : None #define PWM_CH1_DIV_FRAC_RESET _u(0x0) #define PWM_CH1_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH1_DIV_FRAC_MSB _u(3) @@ -272,7 +264,6 @@ #define PWM_CH1_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH1_CC_B -// Description : None #define PWM_CH1_CC_B_RESET _u(0x0000) #define PWM_CH1_CC_B_BITS _u(0xffff0000) #define PWM_CH1_CC_B_MSB _u(31) @@ -280,7 +271,6 @@ #define PWM_CH1_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH1_CC_A -// Description : None #define PWM_CH1_CC_A_RESET _u(0x0000) #define PWM_CH1_CC_A_BITS _u(0x0000ffff) #define PWM_CH1_CC_A_MSB _u(15) @@ -326,21 +316,19 @@ #define PWM_CH2_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH2_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH2_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH2_CSR_DIVMODE_MSB _u(5) -#define PWM_CH2_CSR_DIVMODE_LSB _u(4) -#define PWM_CH2_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH2_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH2_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH2_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH2_CSR_DIVMODE_MSB _u(5) +#define PWM_CH2_CSR_DIVMODE_LSB _u(4) +#define PWM_CH2_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH2_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH2_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH2_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH2_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH2_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH2_CSR_B_INV // Description : Invert output B @@ -383,7 +371,6 @@ #define PWM_CH2_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH2_DIV_INT -// Description : None #define PWM_CH2_DIV_INT_RESET _u(0x01) #define PWM_CH2_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH2_DIV_INT_MSB _u(11) @@ -391,7 +378,6 @@ #define PWM_CH2_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH2_DIV_FRAC -// Description : None #define PWM_CH2_DIV_FRAC_RESET _u(0x0) #define PWM_CH2_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH2_DIV_FRAC_MSB _u(3) @@ -414,7 +400,6 @@ #define PWM_CH2_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH2_CC_B -// Description : None #define PWM_CH2_CC_B_RESET _u(0x0000) #define PWM_CH2_CC_B_BITS _u(0xffff0000) #define PWM_CH2_CC_B_MSB _u(31) @@ -422,7 +407,6 @@ #define PWM_CH2_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH2_CC_A -// Description : None #define PWM_CH2_CC_A_RESET _u(0x0000) #define PWM_CH2_CC_A_BITS _u(0x0000ffff) #define PWM_CH2_CC_A_MSB _u(15) @@ -468,21 +452,19 @@ #define PWM_CH3_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH3_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH3_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH3_CSR_DIVMODE_MSB _u(5) -#define PWM_CH3_CSR_DIVMODE_LSB _u(4) -#define PWM_CH3_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH3_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH3_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH3_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH3_CSR_DIVMODE_MSB _u(5) +#define PWM_CH3_CSR_DIVMODE_LSB _u(4) +#define PWM_CH3_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH3_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH3_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH3_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH3_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH3_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH3_CSR_B_INV // Description : Invert output B @@ -525,7 +507,6 @@ #define PWM_CH3_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH3_DIV_INT -// Description : None #define PWM_CH3_DIV_INT_RESET _u(0x01) #define PWM_CH3_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH3_DIV_INT_MSB _u(11) @@ -533,7 +514,6 @@ #define PWM_CH3_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH3_DIV_FRAC -// Description : None #define PWM_CH3_DIV_FRAC_RESET _u(0x0) #define PWM_CH3_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH3_DIV_FRAC_MSB _u(3) @@ -556,7 +536,6 @@ #define PWM_CH3_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH3_CC_B -// Description : None #define PWM_CH3_CC_B_RESET _u(0x0000) #define PWM_CH3_CC_B_BITS _u(0xffff0000) #define PWM_CH3_CC_B_MSB _u(31) @@ -564,7 +543,6 @@ #define PWM_CH3_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH3_CC_A -// Description : None #define PWM_CH3_CC_A_RESET _u(0x0000) #define PWM_CH3_CC_A_BITS _u(0x0000ffff) #define PWM_CH3_CC_A_MSB _u(15) @@ -610,21 +588,19 @@ #define PWM_CH4_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH4_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH4_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH4_CSR_DIVMODE_MSB _u(5) -#define PWM_CH4_CSR_DIVMODE_LSB _u(4) -#define PWM_CH4_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH4_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH4_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH4_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH4_CSR_DIVMODE_MSB _u(5) +#define PWM_CH4_CSR_DIVMODE_LSB _u(4) +#define PWM_CH4_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH4_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH4_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH4_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH4_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH4_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH4_CSR_B_INV // Description : Invert output B @@ -667,7 +643,6 @@ #define PWM_CH4_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH4_DIV_INT -// Description : None #define PWM_CH4_DIV_INT_RESET _u(0x01) #define PWM_CH4_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH4_DIV_INT_MSB _u(11) @@ -675,7 +650,6 @@ #define PWM_CH4_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH4_DIV_FRAC -// Description : None #define PWM_CH4_DIV_FRAC_RESET _u(0x0) #define PWM_CH4_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH4_DIV_FRAC_MSB _u(3) @@ -698,7 +672,6 @@ #define PWM_CH4_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH4_CC_B -// Description : None #define PWM_CH4_CC_B_RESET _u(0x0000) #define PWM_CH4_CC_B_BITS _u(0xffff0000) #define PWM_CH4_CC_B_MSB _u(31) @@ -706,7 +679,6 @@ #define PWM_CH4_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH4_CC_A -// Description : None #define PWM_CH4_CC_A_RESET _u(0x0000) #define PWM_CH4_CC_A_BITS _u(0x0000ffff) #define PWM_CH4_CC_A_MSB _u(15) @@ -752,21 +724,19 @@ #define PWM_CH5_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH5_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH5_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH5_CSR_DIVMODE_MSB _u(5) -#define PWM_CH5_CSR_DIVMODE_LSB _u(4) -#define PWM_CH5_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH5_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH5_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH5_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH5_CSR_DIVMODE_MSB _u(5) +#define PWM_CH5_CSR_DIVMODE_LSB _u(4) +#define PWM_CH5_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH5_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH5_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH5_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH5_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH5_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH5_CSR_B_INV // Description : Invert output B @@ -809,7 +779,6 @@ #define PWM_CH5_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH5_DIV_INT -// Description : None #define PWM_CH5_DIV_INT_RESET _u(0x01) #define PWM_CH5_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH5_DIV_INT_MSB _u(11) @@ -817,7 +786,6 @@ #define PWM_CH5_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH5_DIV_FRAC -// Description : None #define PWM_CH5_DIV_FRAC_RESET _u(0x0) #define PWM_CH5_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH5_DIV_FRAC_MSB _u(3) @@ -840,7 +808,6 @@ #define PWM_CH5_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH5_CC_B -// Description : None #define PWM_CH5_CC_B_RESET _u(0x0000) #define PWM_CH5_CC_B_BITS _u(0xffff0000) #define PWM_CH5_CC_B_MSB _u(31) @@ -848,7 +815,6 @@ #define PWM_CH5_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH5_CC_A -// Description : None #define PWM_CH5_CC_A_RESET _u(0x0000) #define PWM_CH5_CC_A_BITS _u(0x0000ffff) #define PWM_CH5_CC_A_MSB _u(15) @@ -894,21 +860,19 @@ #define PWM_CH6_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH6_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH6_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH6_CSR_DIVMODE_MSB _u(5) -#define PWM_CH6_CSR_DIVMODE_LSB _u(4) -#define PWM_CH6_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH6_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH6_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH6_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH6_CSR_DIVMODE_MSB _u(5) +#define PWM_CH6_CSR_DIVMODE_LSB _u(4) +#define PWM_CH6_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH6_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH6_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH6_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH6_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH6_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH6_CSR_B_INV // Description : Invert output B @@ -951,7 +915,6 @@ #define PWM_CH6_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH6_DIV_INT -// Description : None #define PWM_CH6_DIV_INT_RESET _u(0x01) #define PWM_CH6_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH6_DIV_INT_MSB _u(11) @@ -959,7 +922,6 @@ #define PWM_CH6_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH6_DIV_FRAC -// Description : None #define PWM_CH6_DIV_FRAC_RESET _u(0x0) #define PWM_CH6_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH6_DIV_FRAC_MSB _u(3) @@ -982,7 +944,6 @@ #define PWM_CH6_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH6_CC_B -// Description : None #define PWM_CH6_CC_B_RESET _u(0x0000) #define PWM_CH6_CC_B_BITS _u(0xffff0000) #define PWM_CH6_CC_B_MSB _u(31) @@ -990,7 +951,6 @@ #define PWM_CH6_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH6_CC_A -// Description : None #define PWM_CH6_CC_A_RESET _u(0x0000) #define PWM_CH6_CC_A_BITS _u(0x0000ffff) #define PWM_CH6_CC_A_MSB _u(15) @@ -1036,21 +996,19 @@ #define PWM_CH7_CSR_PH_RET_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_DIVMODE -// Description : 0x0 -> Free-running counting at rate dictated by fractional -// divider +// 0x0 -> Free-running counting at rate dictated by fractional divider // 0x1 -> Fractional divider operation is gated by the PWM B pin. // 0x2 -> Counter advances with each rising edge of the PWM B pin. -// 0x3 -> Counter advances with each falling edge of the PWM B -// pin. -#define PWM_CH7_CSR_DIVMODE_RESET _u(0x0) -#define PWM_CH7_CSR_DIVMODE_BITS _u(0x00000030) -#define PWM_CH7_CSR_DIVMODE_MSB _u(5) -#define PWM_CH7_CSR_DIVMODE_LSB _u(4) -#define PWM_CH7_CSR_DIVMODE_ACCESS "RW" -#define PWM_CH7_CSR_DIVMODE_VALUE_DIV _u(0x0) +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH7_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH7_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH7_CSR_DIVMODE_MSB _u(5) +#define PWM_CH7_CSR_DIVMODE_LSB _u(4) +#define PWM_CH7_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH7_CSR_DIVMODE_VALUE_DIV _u(0x0) #define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL _u(0x1) -#define PWM_CH7_CSR_DIVMODE_VALUE_RISE _u(0x2) -#define PWM_CH7_CSR_DIVMODE_VALUE_FALL _u(0x3) +#define PWM_CH7_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH7_CSR_DIVMODE_VALUE_FALL _u(0x3) // ----------------------------------------------------------------------------- // Field : PWM_CH7_CSR_B_INV // Description : Invert output B @@ -1093,7 +1051,6 @@ #define PWM_CH7_DIV_RESET _u(0x00000010) // ----------------------------------------------------------------------------- // Field : PWM_CH7_DIV_INT -// Description : None #define PWM_CH7_DIV_INT_RESET _u(0x01) #define PWM_CH7_DIV_INT_BITS _u(0x00000ff0) #define PWM_CH7_DIV_INT_MSB _u(11) @@ -1101,7 +1058,6 @@ #define PWM_CH7_DIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH7_DIV_FRAC -// Description : None #define PWM_CH7_DIV_FRAC_RESET _u(0x0) #define PWM_CH7_DIV_FRAC_BITS _u(0x0000000f) #define PWM_CH7_DIV_FRAC_MSB _u(3) @@ -1124,7 +1080,6 @@ #define PWM_CH7_CC_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_CH7_CC_B -// Description : None #define PWM_CH7_CC_B_RESET _u(0x0000) #define PWM_CH7_CC_B_BITS _u(0xffff0000) #define PWM_CH7_CC_B_MSB _u(31) @@ -1132,7 +1087,6 @@ #define PWM_CH7_CC_B_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_CH7_CC_A -// Description : None #define PWM_CH7_CC_A_RESET _u(0x0000) #define PWM_CH7_CC_A_BITS _u(0x0000ffff) #define PWM_CH7_CC_A_MSB _u(15) @@ -1159,7 +1113,6 @@ #define PWM_EN_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_EN_CH7 -// Description : None #define PWM_EN_CH7_RESET _u(0x0) #define PWM_EN_CH7_BITS _u(0x00000080) #define PWM_EN_CH7_MSB _u(7) @@ -1167,7 +1120,6 @@ #define PWM_EN_CH7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH6 -// Description : None #define PWM_EN_CH6_RESET _u(0x0) #define PWM_EN_CH6_BITS _u(0x00000040) #define PWM_EN_CH6_MSB _u(6) @@ -1175,7 +1127,6 @@ #define PWM_EN_CH6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH5 -// Description : None #define PWM_EN_CH5_RESET _u(0x0) #define PWM_EN_CH5_BITS _u(0x00000020) #define PWM_EN_CH5_MSB _u(5) @@ -1183,7 +1134,6 @@ #define PWM_EN_CH5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH4 -// Description : None #define PWM_EN_CH4_RESET _u(0x0) #define PWM_EN_CH4_BITS _u(0x00000010) #define PWM_EN_CH4_MSB _u(4) @@ -1191,7 +1141,6 @@ #define PWM_EN_CH4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH3 -// Description : None #define PWM_EN_CH3_RESET _u(0x0) #define PWM_EN_CH3_BITS _u(0x00000008) #define PWM_EN_CH3_MSB _u(3) @@ -1199,7 +1148,6 @@ #define PWM_EN_CH3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH2 -// Description : None #define PWM_EN_CH2_RESET _u(0x0) #define PWM_EN_CH2_BITS _u(0x00000004) #define PWM_EN_CH2_MSB _u(2) @@ -1207,7 +1155,6 @@ #define PWM_EN_CH2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH1 -// Description : None #define PWM_EN_CH1_RESET _u(0x0) #define PWM_EN_CH1_BITS _u(0x00000002) #define PWM_EN_CH1_MSB _u(1) @@ -1215,7 +1162,6 @@ #define PWM_EN_CH1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_EN_CH0 -// Description : None #define PWM_EN_CH0_RESET _u(0x0) #define PWM_EN_CH0_BITS _u(0x00000001) #define PWM_EN_CH0_MSB _u(0) @@ -1229,7 +1175,6 @@ #define PWM_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH7 -// Description : None #define PWM_INTR_CH7_RESET _u(0x0) #define PWM_INTR_CH7_BITS _u(0x00000080) #define PWM_INTR_CH7_MSB _u(7) @@ -1237,7 +1182,6 @@ #define PWM_INTR_CH7_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH6 -// Description : None #define PWM_INTR_CH6_RESET _u(0x0) #define PWM_INTR_CH6_BITS _u(0x00000040) #define PWM_INTR_CH6_MSB _u(6) @@ -1245,7 +1189,6 @@ #define PWM_INTR_CH6_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH5 -// Description : None #define PWM_INTR_CH5_RESET _u(0x0) #define PWM_INTR_CH5_BITS _u(0x00000020) #define PWM_INTR_CH5_MSB _u(5) @@ -1253,7 +1196,6 @@ #define PWM_INTR_CH5_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH4 -// Description : None #define PWM_INTR_CH4_RESET _u(0x0) #define PWM_INTR_CH4_BITS _u(0x00000010) #define PWM_INTR_CH4_MSB _u(4) @@ -1261,7 +1203,6 @@ #define PWM_INTR_CH4_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH3 -// Description : None #define PWM_INTR_CH3_RESET _u(0x0) #define PWM_INTR_CH3_BITS _u(0x00000008) #define PWM_INTR_CH3_MSB _u(3) @@ -1269,7 +1210,6 @@ #define PWM_INTR_CH3_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH2 -// Description : None #define PWM_INTR_CH2_RESET _u(0x0) #define PWM_INTR_CH2_BITS _u(0x00000004) #define PWM_INTR_CH2_MSB _u(2) @@ -1277,7 +1217,6 @@ #define PWM_INTR_CH2_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH1 -// Description : None #define PWM_INTR_CH1_RESET _u(0x0) #define PWM_INTR_CH1_BITS _u(0x00000002) #define PWM_INTR_CH1_MSB _u(1) @@ -1285,7 +1224,6 @@ #define PWM_INTR_CH1_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PWM_INTR_CH0 -// Description : None #define PWM_INTR_CH0_RESET _u(0x0) #define PWM_INTR_CH0_BITS _u(0x00000001) #define PWM_INTR_CH0_MSB _u(0) @@ -1299,7 +1237,6 @@ #define PWM_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH7 -// Description : None #define PWM_INTE_CH7_RESET _u(0x0) #define PWM_INTE_CH7_BITS _u(0x00000080) #define PWM_INTE_CH7_MSB _u(7) @@ -1307,7 +1244,6 @@ #define PWM_INTE_CH7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH6 -// Description : None #define PWM_INTE_CH6_RESET _u(0x0) #define PWM_INTE_CH6_BITS _u(0x00000040) #define PWM_INTE_CH6_MSB _u(6) @@ -1315,7 +1251,6 @@ #define PWM_INTE_CH6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH5 -// Description : None #define PWM_INTE_CH5_RESET _u(0x0) #define PWM_INTE_CH5_BITS _u(0x00000020) #define PWM_INTE_CH5_MSB _u(5) @@ -1323,7 +1258,6 @@ #define PWM_INTE_CH5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH4 -// Description : None #define PWM_INTE_CH4_RESET _u(0x0) #define PWM_INTE_CH4_BITS _u(0x00000010) #define PWM_INTE_CH4_MSB _u(4) @@ -1331,7 +1265,6 @@ #define PWM_INTE_CH4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH3 -// Description : None #define PWM_INTE_CH3_RESET _u(0x0) #define PWM_INTE_CH3_BITS _u(0x00000008) #define PWM_INTE_CH3_MSB _u(3) @@ -1339,7 +1272,6 @@ #define PWM_INTE_CH3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH2 -// Description : None #define PWM_INTE_CH2_RESET _u(0x0) #define PWM_INTE_CH2_BITS _u(0x00000004) #define PWM_INTE_CH2_MSB _u(2) @@ -1347,7 +1279,6 @@ #define PWM_INTE_CH2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH1 -// Description : None #define PWM_INTE_CH1_RESET _u(0x0) #define PWM_INTE_CH1_BITS _u(0x00000002) #define PWM_INTE_CH1_MSB _u(1) @@ -1355,7 +1286,6 @@ #define PWM_INTE_CH1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTE_CH0 -// Description : None #define PWM_INTE_CH0_RESET _u(0x0) #define PWM_INTE_CH0_BITS _u(0x00000001) #define PWM_INTE_CH0_MSB _u(0) @@ -1369,7 +1299,6 @@ #define PWM_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH7 -// Description : None #define PWM_INTF_CH7_RESET _u(0x0) #define PWM_INTF_CH7_BITS _u(0x00000080) #define PWM_INTF_CH7_MSB _u(7) @@ -1377,7 +1306,6 @@ #define PWM_INTF_CH7_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH6 -// Description : None #define PWM_INTF_CH6_RESET _u(0x0) #define PWM_INTF_CH6_BITS _u(0x00000040) #define PWM_INTF_CH6_MSB _u(6) @@ -1385,7 +1313,6 @@ #define PWM_INTF_CH6_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH5 -// Description : None #define PWM_INTF_CH5_RESET _u(0x0) #define PWM_INTF_CH5_BITS _u(0x00000020) #define PWM_INTF_CH5_MSB _u(5) @@ -1393,7 +1320,6 @@ #define PWM_INTF_CH5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH4 -// Description : None #define PWM_INTF_CH4_RESET _u(0x0) #define PWM_INTF_CH4_BITS _u(0x00000010) #define PWM_INTF_CH4_MSB _u(4) @@ -1401,7 +1327,6 @@ #define PWM_INTF_CH4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH3 -// Description : None #define PWM_INTF_CH3_RESET _u(0x0) #define PWM_INTF_CH3_BITS _u(0x00000008) #define PWM_INTF_CH3_MSB _u(3) @@ -1409,7 +1334,6 @@ #define PWM_INTF_CH3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH2 -// Description : None #define PWM_INTF_CH2_RESET _u(0x0) #define PWM_INTF_CH2_BITS _u(0x00000004) #define PWM_INTF_CH2_MSB _u(2) @@ -1417,7 +1341,6 @@ #define PWM_INTF_CH2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH1 -// Description : None #define PWM_INTF_CH1_RESET _u(0x0) #define PWM_INTF_CH1_BITS _u(0x00000002) #define PWM_INTF_CH1_MSB _u(1) @@ -1425,7 +1348,6 @@ #define PWM_INTF_CH1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PWM_INTF_CH0 -// Description : None #define PWM_INTF_CH0_RESET _u(0x0) #define PWM_INTF_CH0_BITS _u(0x00000001) #define PWM_INTF_CH0_MSB _u(0) @@ -1439,7 +1361,6 @@ #define PWM_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH7 -// Description : None #define PWM_INTS_CH7_RESET _u(0x0) #define PWM_INTS_CH7_BITS _u(0x00000080) #define PWM_INTS_CH7_MSB _u(7) @@ -1447,7 +1368,6 @@ #define PWM_INTS_CH7_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH6 -// Description : None #define PWM_INTS_CH6_RESET _u(0x0) #define PWM_INTS_CH6_BITS _u(0x00000040) #define PWM_INTS_CH6_MSB _u(6) @@ -1455,7 +1375,6 @@ #define PWM_INTS_CH6_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH5 -// Description : None #define PWM_INTS_CH5_RESET _u(0x0) #define PWM_INTS_CH5_BITS _u(0x00000020) #define PWM_INTS_CH5_MSB _u(5) @@ -1463,7 +1382,6 @@ #define PWM_INTS_CH5_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH4 -// Description : None #define PWM_INTS_CH4_RESET _u(0x0) #define PWM_INTS_CH4_BITS _u(0x00000010) #define PWM_INTS_CH4_MSB _u(4) @@ -1471,7 +1389,6 @@ #define PWM_INTS_CH4_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH3 -// Description : None #define PWM_INTS_CH3_RESET _u(0x0) #define PWM_INTS_CH3_BITS _u(0x00000008) #define PWM_INTS_CH3_MSB _u(3) @@ -1479,7 +1396,6 @@ #define PWM_INTS_CH3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH2 -// Description : None #define PWM_INTS_CH2_RESET _u(0x0) #define PWM_INTS_CH2_BITS _u(0x00000004) #define PWM_INTS_CH2_MSB _u(2) @@ -1487,7 +1403,6 @@ #define PWM_INTS_CH2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH1 -// Description : None #define PWM_INTS_CH1_RESET _u(0x0) #define PWM_INTS_CH1_BITS _u(0x00000002) #define PWM_INTS_CH1_MSB _u(1) @@ -1495,11 +1410,11 @@ #define PWM_INTS_CH1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PWM_INTS_CH0 -// Description : None #define PWM_INTS_CH0_RESET _u(0x0) #define PWM_INTS_CH0_BITS _u(0x00000001) #define PWM_INTS_CH0_MSB _u(0) #define PWM_INTS_CH0_LSB _u(0) #define PWM_INTS_CH0_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_PWM_DEFINED +#endif // _HARDWARE_REGS_PWM_H + diff --git a/lib/rp2040/hardware/regs/resets.h b/lib/pico-sdk/rp2040/hardware/regs/resets.h similarity index 93% rename from lib/rp2040/hardware/regs/resets.h rename to lib/pico-sdk/rp2040/hardware/regs/resets.h index 689a358b0f58..03a56e75d95f 100644 --- a/lib/rp2040/hardware/regs/resets.h +++ b/lib/pico-sdk/rp2040/hardware/regs/resets.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : RESETS // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_RESETS_DEFINED -#define HARDWARE_REGS_RESETS_DEFINED +#ifndef _HARDWARE_REGS_RESETS_H +#define _HARDWARE_REGS_RESETS_H // ============================================================================= // Register : RESETS_RESET // Description : Reset control. If a bit is set it means the peripheral is in @@ -20,7 +21,6 @@ #define RESETS_RESET_RESET _u(0x01ffffff) // ----------------------------------------------------------------------------- // Field : RESETS_RESET_USBCTRL -// Description : None #define RESETS_RESET_USBCTRL_RESET _u(0x1) #define RESETS_RESET_USBCTRL_BITS _u(0x01000000) #define RESETS_RESET_USBCTRL_MSB _u(24) @@ -28,7 +28,6 @@ #define RESETS_RESET_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_UART1 -// Description : None #define RESETS_RESET_UART1_RESET _u(0x1) #define RESETS_RESET_UART1_BITS _u(0x00800000) #define RESETS_RESET_UART1_MSB _u(23) @@ -36,7 +35,6 @@ #define RESETS_RESET_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_UART0 -// Description : None #define RESETS_RESET_UART0_RESET _u(0x1) #define RESETS_RESET_UART0_BITS _u(0x00400000) #define RESETS_RESET_UART0_MSB _u(22) @@ -44,7 +42,6 @@ #define RESETS_RESET_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_TIMER -// Description : None #define RESETS_RESET_TIMER_RESET _u(0x1) #define RESETS_RESET_TIMER_BITS _u(0x00200000) #define RESETS_RESET_TIMER_MSB _u(21) @@ -52,7 +49,6 @@ #define RESETS_RESET_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_TBMAN -// Description : None #define RESETS_RESET_TBMAN_RESET _u(0x1) #define RESETS_RESET_TBMAN_BITS _u(0x00100000) #define RESETS_RESET_TBMAN_MSB _u(20) @@ -60,7 +56,6 @@ #define RESETS_RESET_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SYSINFO -// Description : None #define RESETS_RESET_SYSINFO_RESET _u(0x1) #define RESETS_RESET_SYSINFO_BITS _u(0x00080000) #define RESETS_RESET_SYSINFO_MSB _u(19) @@ -68,7 +63,6 @@ #define RESETS_RESET_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SYSCFG -// Description : None #define RESETS_RESET_SYSCFG_RESET _u(0x1) #define RESETS_RESET_SYSCFG_BITS _u(0x00040000) #define RESETS_RESET_SYSCFG_MSB _u(18) @@ -76,7 +70,6 @@ #define RESETS_RESET_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SPI1 -// Description : None #define RESETS_RESET_SPI1_RESET _u(0x1) #define RESETS_RESET_SPI1_BITS _u(0x00020000) #define RESETS_RESET_SPI1_MSB _u(17) @@ -84,7 +77,6 @@ #define RESETS_RESET_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_SPI0 -// Description : None #define RESETS_RESET_SPI0_RESET _u(0x1) #define RESETS_RESET_SPI0_BITS _u(0x00010000) #define RESETS_RESET_SPI0_MSB _u(16) @@ -92,7 +84,6 @@ #define RESETS_RESET_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_RTC -// Description : None #define RESETS_RESET_RTC_RESET _u(0x1) #define RESETS_RESET_RTC_BITS _u(0x00008000) #define RESETS_RESET_RTC_MSB _u(15) @@ -100,7 +91,6 @@ #define RESETS_RESET_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PWM -// Description : None #define RESETS_RESET_PWM_RESET _u(0x1) #define RESETS_RESET_PWM_BITS _u(0x00004000) #define RESETS_RESET_PWM_MSB _u(14) @@ -108,7 +98,6 @@ #define RESETS_RESET_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PLL_USB -// Description : None #define RESETS_RESET_PLL_USB_RESET _u(0x1) #define RESETS_RESET_PLL_USB_BITS _u(0x00002000) #define RESETS_RESET_PLL_USB_MSB _u(13) @@ -116,7 +105,6 @@ #define RESETS_RESET_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PLL_SYS -// Description : None #define RESETS_RESET_PLL_SYS_RESET _u(0x1) #define RESETS_RESET_PLL_SYS_BITS _u(0x00001000) #define RESETS_RESET_PLL_SYS_MSB _u(12) @@ -124,7 +112,6 @@ #define RESETS_RESET_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PIO1 -// Description : None #define RESETS_RESET_PIO1_RESET _u(0x1) #define RESETS_RESET_PIO1_BITS _u(0x00000800) #define RESETS_RESET_PIO1_MSB _u(11) @@ -132,7 +119,6 @@ #define RESETS_RESET_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PIO0 -// Description : None #define RESETS_RESET_PIO0_RESET _u(0x1) #define RESETS_RESET_PIO0_BITS _u(0x00000400) #define RESETS_RESET_PIO0_MSB _u(10) @@ -140,7 +126,6 @@ #define RESETS_RESET_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PADS_QSPI -// Description : None #define RESETS_RESET_PADS_QSPI_RESET _u(0x1) #define RESETS_RESET_PADS_QSPI_BITS _u(0x00000200) #define RESETS_RESET_PADS_QSPI_MSB _u(9) @@ -148,7 +133,6 @@ #define RESETS_RESET_PADS_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_PADS_BANK0 -// Description : None #define RESETS_RESET_PADS_BANK0_RESET _u(0x1) #define RESETS_RESET_PADS_BANK0_BITS _u(0x00000100) #define RESETS_RESET_PADS_BANK0_MSB _u(8) @@ -156,7 +140,6 @@ #define RESETS_RESET_PADS_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_JTAG -// Description : None #define RESETS_RESET_JTAG_RESET _u(0x1) #define RESETS_RESET_JTAG_BITS _u(0x00000080) #define RESETS_RESET_JTAG_MSB _u(7) @@ -164,7 +147,6 @@ #define RESETS_RESET_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_IO_QSPI -// Description : None #define RESETS_RESET_IO_QSPI_RESET _u(0x1) #define RESETS_RESET_IO_QSPI_BITS _u(0x00000040) #define RESETS_RESET_IO_QSPI_MSB _u(6) @@ -172,7 +154,6 @@ #define RESETS_RESET_IO_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_IO_BANK0 -// Description : None #define RESETS_RESET_IO_BANK0_RESET _u(0x1) #define RESETS_RESET_IO_BANK0_BITS _u(0x00000020) #define RESETS_RESET_IO_BANK0_MSB _u(5) @@ -180,7 +161,6 @@ #define RESETS_RESET_IO_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_I2C1 -// Description : None #define RESETS_RESET_I2C1_RESET _u(0x1) #define RESETS_RESET_I2C1_BITS _u(0x00000010) #define RESETS_RESET_I2C1_MSB _u(4) @@ -188,7 +168,6 @@ #define RESETS_RESET_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_I2C0 -// Description : None #define RESETS_RESET_I2C0_RESET _u(0x1) #define RESETS_RESET_I2C0_BITS _u(0x00000008) #define RESETS_RESET_I2C0_MSB _u(3) @@ -196,7 +175,6 @@ #define RESETS_RESET_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DMA -// Description : None #define RESETS_RESET_DMA_RESET _u(0x1) #define RESETS_RESET_DMA_BITS _u(0x00000004) #define RESETS_RESET_DMA_MSB _u(2) @@ -204,7 +182,6 @@ #define RESETS_RESET_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_BUSCTRL -// Description : None #define RESETS_RESET_BUSCTRL_RESET _u(0x1) #define RESETS_RESET_BUSCTRL_BITS _u(0x00000002) #define RESETS_RESET_BUSCTRL_MSB _u(1) @@ -212,7 +189,6 @@ #define RESETS_RESET_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_ADC -// Description : None #define RESETS_RESET_ADC_RESET _u(0x1) #define RESETS_RESET_ADC_BITS _u(0x00000001) #define RESETS_RESET_ADC_MSB _u(0) @@ -227,7 +203,6 @@ #define RESETS_WDSEL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_USBCTRL -// Description : None #define RESETS_WDSEL_USBCTRL_RESET _u(0x0) #define RESETS_WDSEL_USBCTRL_BITS _u(0x01000000) #define RESETS_WDSEL_USBCTRL_MSB _u(24) @@ -235,7 +210,6 @@ #define RESETS_WDSEL_USBCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_UART1 -// Description : None #define RESETS_WDSEL_UART1_RESET _u(0x0) #define RESETS_WDSEL_UART1_BITS _u(0x00800000) #define RESETS_WDSEL_UART1_MSB _u(23) @@ -243,7 +217,6 @@ #define RESETS_WDSEL_UART1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_UART0 -// Description : None #define RESETS_WDSEL_UART0_RESET _u(0x0) #define RESETS_WDSEL_UART0_BITS _u(0x00400000) #define RESETS_WDSEL_UART0_MSB _u(22) @@ -251,7 +224,6 @@ #define RESETS_WDSEL_UART0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_TIMER -// Description : None #define RESETS_WDSEL_TIMER_RESET _u(0x0) #define RESETS_WDSEL_TIMER_BITS _u(0x00200000) #define RESETS_WDSEL_TIMER_MSB _u(21) @@ -259,7 +231,6 @@ #define RESETS_WDSEL_TIMER_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_TBMAN -// Description : None #define RESETS_WDSEL_TBMAN_RESET _u(0x0) #define RESETS_WDSEL_TBMAN_BITS _u(0x00100000) #define RESETS_WDSEL_TBMAN_MSB _u(20) @@ -267,7 +238,6 @@ #define RESETS_WDSEL_TBMAN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SYSINFO -// Description : None #define RESETS_WDSEL_SYSINFO_RESET _u(0x0) #define RESETS_WDSEL_SYSINFO_BITS _u(0x00080000) #define RESETS_WDSEL_SYSINFO_MSB _u(19) @@ -275,7 +245,6 @@ #define RESETS_WDSEL_SYSINFO_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SYSCFG -// Description : None #define RESETS_WDSEL_SYSCFG_RESET _u(0x0) #define RESETS_WDSEL_SYSCFG_BITS _u(0x00040000) #define RESETS_WDSEL_SYSCFG_MSB _u(18) @@ -283,7 +252,6 @@ #define RESETS_WDSEL_SYSCFG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SPI1 -// Description : None #define RESETS_WDSEL_SPI1_RESET _u(0x0) #define RESETS_WDSEL_SPI1_BITS _u(0x00020000) #define RESETS_WDSEL_SPI1_MSB _u(17) @@ -291,7 +259,6 @@ #define RESETS_WDSEL_SPI1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_SPI0 -// Description : None #define RESETS_WDSEL_SPI0_RESET _u(0x0) #define RESETS_WDSEL_SPI0_BITS _u(0x00010000) #define RESETS_WDSEL_SPI0_MSB _u(16) @@ -299,7 +266,6 @@ #define RESETS_WDSEL_SPI0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_RTC -// Description : None #define RESETS_WDSEL_RTC_RESET _u(0x0) #define RESETS_WDSEL_RTC_BITS _u(0x00008000) #define RESETS_WDSEL_RTC_MSB _u(15) @@ -307,7 +273,6 @@ #define RESETS_WDSEL_RTC_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PWM -// Description : None #define RESETS_WDSEL_PWM_RESET _u(0x0) #define RESETS_WDSEL_PWM_BITS _u(0x00004000) #define RESETS_WDSEL_PWM_MSB _u(14) @@ -315,7 +280,6 @@ #define RESETS_WDSEL_PWM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PLL_USB -// Description : None #define RESETS_WDSEL_PLL_USB_RESET _u(0x0) #define RESETS_WDSEL_PLL_USB_BITS _u(0x00002000) #define RESETS_WDSEL_PLL_USB_MSB _u(13) @@ -323,7 +287,6 @@ #define RESETS_WDSEL_PLL_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PLL_SYS -// Description : None #define RESETS_WDSEL_PLL_SYS_RESET _u(0x0) #define RESETS_WDSEL_PLL_SYS_BITS _u(0x00001000) #define RESETS_WDSEL_PLL_SYS_MSB _u(12) @@ -331,7 +294,6 @@ #define RESETS_WDSEL_PLL_SYS_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PIO1 -// Description : None #define RESETS_WDSEL_PIO1_RESET _u(0x0) #define RESETS_WDSEL_PIO1_BITS _u(0x00000800) #define RESETS_WDSEL_PIO1_MSB _u(11) @@ -339,7 +301,6 @@ #define RESETS_WDSEL_PIO1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PIO0 -// Description : None #define RESETS_WDSEL_PIO0_RESET _u(0x0) #define RESETS_WDSEL_PIO0_BITS _u(0x00000400) #define RESETS_WDSEL_PIO0_MSB _u(10) @@ -347,7 +308,6 @@ #define RESETS_WDSEL_PIO0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PADS_QSPI -// Description : None #define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0) #define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000200) #define RESETS_WDSEL_PADS_QSPI_MSB _u(9) @@ -355,7 +315,6 @@ #define RESETS_WDSEL_PADS_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_PADS_BANK0 -// Description : None #define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0) #define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000100) #define RESETS_WDSEL_PADS_BANK0_MSB _u(8) @@ -363,7 +322,6 @@ #define RESETS_WDSEL_PADS_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_JTAG -// Description : None #define RESETS_WDSEL_JTAG_RESET _u(0x0) #define RESETS_WDSEL_JTAG_BITS _u(0x00000080) #define RESETS_WDSEL_JTAG_MSB _u(7) @@ -371,7 +329,6 @@ #define RESETS_WDSEL_JTAG_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_IO_QSPI -// Description : None #define RESETS_WDSEL_IO_QSPI_RESET _u(0x0) #define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000040) #define RESETS_WDSEL_IO_QSPI_MSB _u(6) @@ -379,7 +336,6 @@ #define RESETS_WDSEL_IO_QSPI_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_IO_BANK0 -// Description : None #define RESETS_WDSEL_IO_BANK0_RESET _u(0x0) #define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000020) #define RESETS_WDSEL_IO_BANK0_MSB _u(5) @@ -387,7 +343,6 @@ #define RESETS_WDSEL_IO_BANK0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_I2C1 -// Description : None #define RESETS_WDSEL_I2C1_RESET _u(0x0) #define RESETS_WDSEL_I2C1_BITS _u(0x00000010) #define RESETS_WDSEL_I2C1_MSB _u(4) @@ -395,7 +350,6 @@ #define RESETS_WDSEL_I2C1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_I2C0 -// Description : None #define RESETS_WDSEL_I2C0_RESET _u(0x0) #define RESETS_WDSEL_I2C0_BITS _u(0x00000008) #define RESETS_WDSEL_I2C0_MSB _u(3) @@ -403,7 +357,6 @@ #define RESETS_WDSEL_I2C0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_DMA -// Description : None #define RESETS_WDSEL_DMA_RESET _u(0x0) #define RESETS_WDSEL_DMA_BITS _u(0x00000004) #define RESETS_WDSEL_DMA_MSB _u(2) @@ -411,7 +364,6 @@ #define RESETS_WDSEL_DMA_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_BUSCTRL -// Description : None #define RESETS_WDSEL_BUSCTRL_RESET _u(0x0) #define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002) #define RESETS_WDSEL_BUSCTRL_MSB _u(1) @@ -419,7 +371,6 @@ #define RESETS_WDSEL_BUSCTRL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : RESETS_WDSEL_ADC -// Description : None #define RESETS_WDSEL_ADC_RESET _u(0x0) #define RESETS_WDSEL_ADC_BITS _u(0x00000001) #define RESETS_WDSEL_ADC_MSB _u(0) @@ -435,7 +386,6 @@ #define RESETS_RESET_DONE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_USBCTRL -// Description : None #define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0) #define RESETS_RESET_DONE_USBCTRL_BITS _u(0x01000000) #define RESETS_RESET_DONE_USBCTRL_MSB _u(24) @@ -443,7 +393,6 @@ #define RESETS_RESET_DONE_USBCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_UART1 -// Description : None #define RESETS_RESET_DONE_UART1_RESET _u(0x0) #define RESETS_RESET_DONE_UART1_BITS _u(0x00800000) #define RESETS_RESET_DONE_UART1_MSB _u(23) @@ -451,7 +400,6 @@ #define RESETS_RESET_DONE_UART1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_UART0 -// Description : None #define RESETS_RESET_DONE_UART0_RESET _u(0x0) #define RESETS_RESET_DONE_UART0_BITS _u(0x00400000) #define RESETS_RESET_DONE_UART0_MSB _u(22) @@ -459,7 +407,6 @@ #define RESETS_RESET_DONE_UART0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_TIMER -// Description : None #define RESETS_RESET_DONE_TIMER_RESET _u(0x0) #define RESETS_RESET_DONE_TIMER_BITS _u(0x00200000) #define RESETS_RESET_DONE_TIMER_MSB _u(21) @@ -467,7 +414,6 @@ #define RESETS_RESET_DONE_TIMER_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_TBMAN -// Description : None #define RESETS_RESET_DONE_TBMAN_RESET _u(0x0) #define RESETS_RESET_DONE_TBMAN_BITS _u(0x00100000) #define RESETS_RESET_DONE_TBMAN_MSB _u(20) @@ -475,7 +421,6 @@ #define RESETS_RESET_DONE_TBMAN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SYSINFO -// Description : None #define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0) #define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00080000) #define RESETS_RESET_DONE_SYSINFO_MSB _u(19) @@ -483,7 +428,6 @@ #define RESETS_RESET_DONE_SYSINFO_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SYSCFG -// Description : None #define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0) #define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00040000) #define RESETS_RESET_DONE_SYSCFG_MSB _u(18) @@ -491,7 +435,6 @@ #define RESETS_RESET_DONE_SYSCFG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SPI1 -// Description : None #define RESETS_RESET_DONE_SPI1_RESET _u(0x0) #define RESETS_RESET_DONE_SPI1_BITS _u(0x00020000) #define RESETS_RESET_DONE_SPI1_MSB _u(17) @@ -499,7 +442,6 @@ #define RESETS_RESET_DONE_SPI1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_SPI0 -// Description : None #define RESETS_RESET_DONE_SPI0_RESET _u(0x0) #define RESETS_RESET_DONE_SPI0_BITS _u(0x00010000) #define RESETS_RESET_DONE_SPI0_MSB _u(16) @@ -507,7 +449,6 @@ #define RESETS_RESET_DONE_SPI0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_RTC -// Description : None #define RESETS_RESET_DONE_RTC_RESET _u(0x0) #define RESETS_RESET_DONE_RTC_BITS _u(0x00008000) #define RESETS_RESET_DONE_RTC_MSB _u(15) @@ -515,7 +456,6 @@ #define RESETS_RESET_DONE_RTC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PWM -// Description : None #define RESETS_RESET_DONE_PWM_RESET _u(0x0) #define RESETS_RESET_DONE_PWM_BITS _u(0x00004000) #define RESETS_RESET_DONE_PWM_MSB _u(14) @@ -523,7 +463,6 @@ #define RESETS_RESET_DONE_PWM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PLL_USB -// Description : None #define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0) #define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00002000) #define RESETS_RESET_DONE_PLL_USB_MSB _u(13) @@ -531,7 +470,6 @@ #define RESETS_RESET_DONE_PLL_USB_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PLL_SYS -// Description : None #define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0) #define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00001000) #define RESETS_RESET_DONE_PLL_SYS_MSB _u(12) @@ -539,7 +477,6 @@ #define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PIO1 -// Description : None #define RESETS_RESET_DONE_PIO1_RESET _u(0x0) #define RESETS_RESET_DONE_PIO1_BITS _u(0x00000800) #define RESETS_RESET_DONE_PIO1_MSB _u(11) @@ -547,7 +484,6 @@ #define RESETS_RESET_DONE_PIO1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PIO0 -// Description : None #define RESETS_RESET_DONE_PIO0_RESET _u(0x0) #define RESETS_RESET_DONE_PIO0_BITS _u(0x00000400) #define RESETS_RESET_DONE_PIO0_MSB _u(10) @@ -555,7 +491,6 @@ #define RESETS_RESET_DONE_PIO0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PADS_QSPI -// Description : None #define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0) #define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000200) #define RESETS_RESET_DONE_PADS_QSPI_MSB _u(9) @@ -563,7 +498,6 @@ #define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_PADS_BANK0 -// Description : None #define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0) #define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000100) #define RESETS_RESET_DONE_PADS_BANK0_MSB _u(8) @@ -571,7 +505,6 @@ #define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_JTAG -// Description : None #define RESETS_RESET_DONE_JTAG_RESET _u(0x0) #define RESETS_RESET_DONE_JTAG_BITS _u(0x00000080) #define RESETS_RESET_DONE_JTAG_MSB _u(7) @@ -579,7 +512,6 @@ #define RESETS_RESET_DONE_JTAG_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_IO_QSPI -// Description : None #define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0) #define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000040) #define RESETS_RESET_DONE_IO_QSPI_MSB _u(6) @@ -587,7 +519,6 @@ #define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_IO_BANK0 -// Description : None #define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0) #define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000020) #define RESETS_RESET_DONE_IO_BANK0_MSB _u(5) @@ -595,7 +526,6 @@ #define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_I2C1 -// Description : None #define RESETS_RESET_DONE_I2C1_RESET _u(0x0) #define RESETS_RESET_DONE_I2C1_BITS _u(0x00000010) #define RESETS_RESET_DONE_I2C1_MSB _u(4) @@ -603,7 +533,6 @@ #define RESETS_RESET_DONE_I2C1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_I2C0 -// Description : None #define RESETS_RESET_DONE_I2C0_RESET _u(0x0) #define RESETS_RESET_DONE_I2C0_BITS _u(0x00000008) #define RESETS_RESET_DONE_I2C0_MSB _u(3) @@ -611,7 +540,6 @@ #define RESETS_RESET_DONE_I2C0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_DMA -// Description : None #define RESETS_RESET_DONE_DMA_RESET _u(0x0) #define RESETS_RESET_DONE_DMA_BITS _u(0x00000004) #define RESETS_RESET_DONE_DMA_MSB _u(2) @@ -619,7 +547,6 @@ #define RESETS_RESET_DONE_DMA_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_BUSCTRL -// Description : None #define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0) #define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002) #define RESETS_RESET_DONE_BUSCTRL_MSB _u(1) @@ -627,11 +554,11 @@ #define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : RESETS_RESET_DONE_ADC -// Description : None #define RESETS_RESET_DONE_ADC_RESET _u(0x0) #define RESETS_RESET_DONE_ADC_BITS _u(0x00000001) #define RESETS_RESET_DONE_ADC_MSB _u(0) #define RESETS_RESET_DONE_ADC_LSB _u(0) #define RESETS_RESET_DONE_ADC_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_RESETS_DEFINED +#endif // _HARDWARE_REGS_RESETS_H + diff --git a/lib/rp2040/hardware/regs/rosc.h b/lib/pico-sdk/rp2040/hardware/regs/rosc.h similarity index 86% rename from lib/rp2040/hardware/regs/rosc.h rename to lib/pico-sdk/rp2040/hardware/regs/rosc.h index 5501e7ef2593..bd4bb9d4a9a7 100644 --- a/lib/rp2040/hardware/regs/rosc.h +++ b/lib/pico-sdk/rp2040/hardware/regs/rosc.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : ROSC // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_ROSC_DEFINED -#define HARDWARE_REGS_ROSC_DEFINED +#ifndef _HARDWARE_REGS_ROSC_H +#define _HARDWARE_REGS_ROSC_H // ============================================================================= // Register : ROSC_CTRL // Description : Ring Oscillator control @@ -27,20 +28,20 @@ // oscillator. // 0xd1e -> DISABLE // 0xfab -> ENABLE -#define ROSC_CTRL_ENABLE_RESET "-" -#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000) -#define ROSC_CTRL_ENABLE_MSB _u(23) -#define ROSC_CTRL_ENABLE_LSB _u(12) -#define ROSC_CTRL_ENABLE_ACCESS "RW" +#define ROSC_CTRL_ENABLE_RESET "-" +#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000) +#define ROSC_CTRL_ENABLE_MSB _u(23) +#define ROSC_CTRL_ENABLE_LSB _u(12) +#define ROSC_CTRL_ENABLE_ACCESS "RW" #define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) -#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) +#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) // ----------------------------------------------------------------------------- // Field : ROSC_CTRL_FREQ_RANGE // Description : Controls the number of delay stages in the ROSC ring // LOW uses stages 0 to 7 -// MEDIUM uses stages 0 to 5 -// HIGH uses stages 0 to 3 -// TOOHIGH uses stages 0 to 1 and should not be used because its +// MEDIUM uses stages 2 to 7 +// HIGH uses stages 4 to 7 +// TOOHIGH uses stages 6 to 7 and should not be used because its // frequency exceeds design specifications // The clock output will not glitch when changing the range up one // step at a time @@ -51,14 +52,14 @@ // 0xfa5 -> MEDIUM // 0xfa7 -> HIGH // 0xfa6 -> TOOHIGH -#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0) -#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) -#define ROSC_CTRL_FREQ_RANGE_MSB _u(11) -#define ROSC_CTRL_FREQ_RANGE_LSB _u(0) -#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW" -#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4) -#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5) -#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7) +#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0) +#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) +#define ROSC_CTRL_FREQ_RANGE_MSB _u(11) +#define ROSC_CTRL_FREQ_RANGE_LSB _u(0) +#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW" +#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4) +#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5) +#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7) #define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6) // ============================================================================= // Register : ROSC_FREQA @@ -80,11 +81,11 @@ // Description : Set to 0x9696 to apply the settings // Any other value in this field will set all drive strengths to 0 // 0x9696 -> PASS -#define ROSC_FREQA_PASSWD_RESET _u(0x0000) -#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000) -#define ROSC_FREQA_PASSWD_MSB _u(31) -#define ROSC_FREQA_PASSWD_LSB _u(16) -#define ROSC_FREQA_PASSWD_ACCESS "RW" +#define ROSC_FREQA_PASSWD_RESET _u(0x0000) +#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000) +#define ROSC_FREQA_PASSWD_MSB _u(31) +#define ROSC_FREQA_PASSWD_LSB _u(16) +#define ROSC_FREQA_PASSWD_ACCESS "RW" #define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696) // ----------------------------------------------------------------------------- // Field : ROSC_FREQA_DS3 @@ -129,11 +130,11 @@ // Description : Set to 0x9696 to apply the settings // Any other value in this field will set all drive strengths to 0 // 0x9696 -> PASS -#define ROSC_FREQB_PASSWD_RESET _u(0x0000) -#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000) -#define ROSC_FREQB_PASSWD_MSB _u(31) -#define ROSC_FREQB_PASSWD_LSB _u(16) -#define ROSC_FREQB_PASSWD_ACCESS "RW" +#define ROSC_FREQB_PASSWD_RESET _u(0x0000) +#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000) +#define ROSC_FREQB_PASSWD_MSB _u(31) +#define ROSC_FREQB_PASSWD_LSB _u(16) +#define ROSC_FREQB_PASSWD_ACCESS "RW" #define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696) // ----------------------------------------------------------------------------- // Field : ROSC_FREQB_DS7 @@ -174,16 +175,16 @@ // On power-up this field is initialised to WAKE // An invalid write will also select WAKE // Warning: setup the irq before selecting dormant mode -// 0x636f6d61 -> DORMANT +// 0x636f6d61 -> dormant // 0x77616b65 -> WAKE -#define ROSC_DORMANT_OFFSET _u(0x0000000c) -#define ROSC_DORMANT_BITS _u(0xffffffff) -#define ROSC_DORMANT_RESET "-" -#define ROSC_DORMANT_MSB _u(31) -#define ROSC_DORMANT_LSB _u(0) -#define ROSC_DORMANT_ACCESS "RW" +#define ROSC_DORMANT_OFFSET _u(0x0000000c) +#define ROSC_DORMANT_BITS _u(0xffffffff) +#define ROSC_DORMANT_RESET "-" +#define ROSC_DORMANT_MSB _u(31) +#define ROSC_DORMANT_LSB _u(0) +#define ROSC_DORMANT_ACCESS "RW" #define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) -#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65) +#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65) // ============================================================================= // Register : ROSC_DIV // Description : Controls the output divider @@ -193,12 +194,12 @@ // any other value sets div=31 // this register resets to div=16 // 0xaa0 -> PASS -#define ROSC_DIV_OFFSET _u(0x00000010) -#define ROSC_DIV_BITS _u(0x00000fff) -#define ROSC_DIV_RESET "-" -#define ROSC_DIV_MSB _u(11) -#define ROSC_DIV_LSB _u(0) -#define ROSC_DIV_ACCESS "RW" +#define ROSC_DIV_OFFSET _u(0x00000010) +#define ROSC_DIV_BITS _u(0x00000fff) +#define ROSC_DIV_RESET "-" +#define ROSC_DIV_MSB _u(11) +#define ROSC_DIV_LSB _u(0) +#define ROSC_DIV_ACCESS "RW" #define ROSC_DIV_VALUE_PASS _u(0xaa0) // ============================================================================= // Register : ROSC_PHASE @@ -309,4 +310,5 @@ #define ROSC_COUNT_LSB _u(0) #define ROSC_COUNT_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_ROSC_DEFINED +#endif // _HARDWARE_REGS_ROSC_H + diff --git a/lib/rp2040/hardware/regs/rtc.h b/lib/pico-sdk/rp2040/hardware/regs/rtc.h similarity index 98% rename from lib/rp2040/hardware/regs/rtc.h rename to lib/pico-sdk/rp2040/hardware/regs/rtc.h index 7d62c9d73534..86d519eb04a8 100644 --- a/lib/rp2040/hardware/regs/rtc.h +++ b/lib/pico-sdk/rp2040/hardware/regs/rtc.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : apb // Description : Register block to control RTC // ============================================================================= -#ifndef HARDWARE_REGS_RTC_DEFINED -#define HARDWARE_REGS_RTC_DEFINED +#ifndef _HARDWARE_REGS_RTC_H +#define _HARDWARE_REGS_RTC_H // ============================================================================= // Register : RTC_CLKDIV_M1 // Description : Divider minus 1 for the 1 second counter. Safe to change the @@ -136,7 +138,6 @@ #define RTC_IRQ_SETUP_0_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE -// Description : None #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-" #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS _u(0x20000000) #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB _u(29) @@ -346,7 +347,6 @@ #define RTC_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTR_RTC -// Description : None #define RTC_INTR_RTC_RESET _u(0x0) #define RTC_INTR_RTC_BITS _u(0x00000001) #define RTC_INTR_RTC_MSB _u(0) @@ -360,7 +360,6 @@ #define RTC_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTE_RTC -// Description : None #define RTC_INTE_RTC_RESET _u(0x0) #define RTC_INTE_RTC_BITS _u(0x00000001) #define RTC_INTE_RTC_MSB _u(0) @@ -374,7 +373,6 @@ #define RTC_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTF_RTC -// Description : None #define RTC_INTF_RTC_RESET _u(0x0) #define RTC_INTF_RTC_BITS _u(0x00000001) #define RTC_INTF_RTC_MSB _u(0) @@ -388,11 +386,11 @@ #define RTC_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : RTC_INTS_RTC -// Description : None #define RTC_INTS_RTC_RESET _u(0x0) #define RTC_INTS_RTC_BITS _u(0x00000001) #define RTC_INTS_RTC_MSB _u(0) #define RTC_INTS_RTC_LSB _u(0) #define RTC_INTS_RTC_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_RTC_DEFINED +#endif // _HARDWARE_REGS_RTC_H + diff --git a/lib/rp2040/hardware/regs/sio.h b/lib/pico-sdk/rp2040/hardware/regs/sio.h similarity index 97% rename from lib/rp2040/hardware/regs/sio.h rename to lib/pico-sdk/rp2040/hardware/regs/sio.h index 37ee2c133e4a..2d720e92792b 100644 --- a/lib/rp2040/hardware/regs/sio.h +++ b/lib/pico-sdk/rp2040/hardware/regs/sio.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,8 +13,8 @@ // Provides core-local and inter-core hardware for the two // processors, with single-cycle access. // ============================================================================= -#ifndef HARDWARE_REGS_SIO_DEFINED -#define HARDWARE_REGS_SIO_DEFINED +#ifndef _HARDWARE_REGS_SIO_H +#define _HARDWARE_REGS_SIO_H // ============================================================================= // Register : SIO_CPUID // Description : Processor core identifier @@ -71,7 +73,7 @@ #define SIO_GPIO_OUT_SET_RESET _u(0x00000000) #define SIO_GPIO_OUT_SET_MSB _u(29) #define SIO_GPIO_OUT_SET_LSB _u(0) -#define SIO_GPIO_OUT_SET_ACCESS "RW" +#define SIO_GPIO_OUT_SET_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OUT_CLR // Description : GPIO output value clear @@ -82,7 +84,7 @@ #define SIO_GPIO_OUT_CLR_RESET _u(0x00000000) #define SIO_GPIO_OUT_CLR_MSB _u(29) #define SIO_GPIO_OUT_CLR_LSB _u(0) -#define SIO_GPIO_OUT_CLR_ACCESS "RW" +#define SIO_GPIO_OUT_CLR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OUT_XOR // Description : GPIO output value XOR @@ -93,7 +95,7 @@ #define SIO_GPIO_OUT_XOR_RESET _u(0x00000000) #define SIO_GPIO_OUT_XOR_MSB _u(29) #define SIO_GPIO_OUT_XOR_LSB _u(0) -#define SIO_GPIO_OUT_XOR_ACCESS "RW" +#define SIO_GPIO_OUT_XOR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OE // Description : GPIO output enable @@ -119,7 +121,7 @@ #define SIO_GPIO_OE_SET_RESET _u(0x00000000) #define SIO_GPIO_OE_SET_MSB _u(29) #define SIO_GPIO_OE_SET_LSB _u(0) -#define SIO_GPIO_OE_SET_ACCESS "RW" +#define SIO_GPIO_OE_SET_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OE_CLR // Description : GPIO output enable clear @@ -130,7 +132,7 @@ #define SIO_GPIO_OE_CLR_RESET _u(0x00000000) #define SIO_GPIO_OE_CLR_MSB _u(29) #define SIO_GPIO_OE_CLR_LSB _u(0) -#define SIO_GPIO_OE_CLR_ACCESS "RW" +#define SIO_GPIO_OE_CLR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_OE_XOR // Description : GPIO output enable XOR @@ -141,7 +143,7 @@ #define SIO_GPIO_OE_XOR_RESET _u(0x00000000) #define SIO_GPIO_OE_XOR_MSB _u(29) #define SIO_GPIO_OE_XOR_LSB _u(0) -#define SIO_GPIO_OE_XOR_ACCESS "RW" +#define SIO_GPIO_OE_XOR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OUT // Description : QSPI output value @@ -169,7 +171,7 @@ #define SIO_GPIO_HI_OUT_SET_RESET _u(0x00000000) #define SIO_GPIO_HI_OUT_SET_MSB _u(5) #define SIO_GPIO_HI_OUT_SET_LSB _u(0) -#define SIO_GPIO_HI_OUT_SET_ACCESS "RW" +#define SIO_GPIO_HI_OUT_SET_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OUT_CLR // Description : QSPI output value clear @@ -180,7 +182,7 @@ #define SIO_GPIO_HI_OUT_CLR_RESET _u(0x00000000) #define SIO_GPIO_HI_OUT_CLR_MSB _u(5) #define SIO_GPIO_HI_OUT_CLR_LSB _u(0) -#define SIO_GPIO_HI_OUT_CLR_ACCESS "RW" +#define SIO_GPIO_HI_OUT_CLR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OUT_XOR // Description : QSPI output value XOR @@ -191,7 +193,7 @@ #define SIO_GPIO_HI_OUT_XOR_RESET _u(0x00000000) #define SIO_GPIO_HI_OUT_XOR_MSB _u(5) #define SIO_GPIO_HI_OUT_XOR_LSB _u(0) -#define SIO_GPIO_HI_OUT_XOR_ACCESS "RW" +#define SIO_GPIO_HI_OUT_XOR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OE // Description : QSPI output enable @@ -218,7 +220,7 @@ #define SIO_GPIO_HI_OE_SET_RESET _u(0x00000000) #define SIO_GPIO_HI_OE_SET_MSB _u(5) #define SIO_GPIO_HI_OE_SET_LSB _u(0) -#define SIO_GPIO_HI_OE_SET_ACCESS "RW" +#define SIO_GPIO_HI_OE_SET_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OE_CLR // Description : QSPI output enable clear @@ -229,7 +231,7 @@ #define SIO_GPIO_HI_OE_CLR_RESET _u(0x00000000) #define SIO_GPIO_HI_OE_CLR_MSB _u(5) #define SIO_GPIO_HI_OE_CLR_LSB _u(0) -#define SIO_GPIO_HI_OE_CLR_ACCESS "RW" +#define SIO_GPIO_HI_OE_CLR_ACCESS "WO" // ============================================================================= // Register : SIO_GPIO_HI_OE_XOR // Description : QSPI output enable XOR @@ -240,7 +242,7 @@ #define SIO_GPIO_HI_OE_XOR_RESET _u(0x00000000) #define SIO_GPIO_HI_OE_XOR_MSB _u(5) #define SIO_GPIO_HI_OE_XOR_LSB _u(0) -#define SIO_GPIO_HI_OE_XOR_ACCESS "RW" +#define SIO_GPIO_HI_OE_XOR_ACCESS "WO" // ============================================================================= // Register : SIO_FIFO_ST // Description : Status register for inter-core FIFOs (mailboxes). @@ -344,7 +346,7 @@ // q`. // Any operand write starts a new calculation. The results appear // in QUOTIENT, REMAINDER. -// UDIVIDEND/SDIVIDEND are aliases of the same internal register. +// UDIVISOR/SDIVISOR are aliases of the same internal register. // The U alias starts an // unsigned calculation, and the S alias starts a signed // calculation. @@ -440,8 +442,8 @@ // Writing an operand (xDIVIDEND, xDIVISOR) will immediately start // a new calculation, no // matter if one is already in progress. -// Writing to a result register will immediately terminate any -// in-progress calculation +// Writing to a result register will immediately terminate any in- +// progress calculation // and set the READY and DIRTY flags. #define SIO_DIV_CSR_READY_RESET _u(0x1) #define SIO_DIV_CSR_READY_BITS _u(0x00000001) @@ -1155,7 +1157,7 @@ #define SIO_SPINLOCK0_RESET _u(0x00000000) #define SIO_SPINLOCK0_MSB _u(31) #define SIO_SPINLOCK0_LSB _u(0) -#define SIO_SPINLOCK0_ACCESS "RO" +#define SIO_SPINLOCK0_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK1 // Description : Reading from a spinlock address will: @@ -1171,7 +1173,7 @@ #define SIO_SPINLOCK1_RESET _u(0x00000000) #define SIO_SPINLOCK1_MSB _u(31) #define SIO_SPINLOCK1_LSB _u(0) -#define SIO_SPINLOCK1_ACCESS "RO" +#define SIO_SPINLOCK1_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK2 // Description : Reading from a spinlock address will: @@ -1187,7 +1189,7 @@ #define SIO_SPINLOCK2_RESET _u(0x00000000) #define SIO_SPINLOCK2_MSB _u(31) #define SIO_SPINLOCK2_LSB _u(0) -#define SIO_SPINLOCK2_ACCESS "RO" +#define SIO_SPINLOCK2_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK3 // Description : Reading from a spinlock address will: @@ -1203,7 +1205,7 @@ #define SIO_SPINLOCK3_RESET _u(0x00000000) #define SIO_SPINLOCK3_MSB _u(31) #define SIO_SPINLOCK3_LSB _u(0) -#define SIO_SPINLOCK3_ACCESS "RO" +#define SIO_SPINLOCK3_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK4 // Description : Reading from a spinlock address will: @@ -1219,7 +1221,7 @@ #define SIO_SPINLOCK4_RESET _u(0x00000000) #define SIO_SPINLOCK4_MSB _u(31) #define SIO_SPINLOCK4_LSB _u(0) -#define SIO_SPINLOCK4_ACCESS "RO" +#define SIO_SPINLOCK4_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK5 // Description : Reading from a spinlock address will: @@ -1235,7 +1237,7 @@ #define SIO_SPINLOCK5_RESET _u(0x00000000) #define SIO_SPINLOCK5_MSB _u(31) #define SIO_SPINLOCK5_LSB _u(0) -#define SIO_SPINLOCK5_ACCESS "RO" +#define SIO_SPINLOCK5_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK6 // Description : Reading from a spinlock address will: @@ -1251,7 +1253,7 @@ #define SIO_SPINLOCK6_RESET _u(0x00000000) #define SIO_SPINLOCK6_MSB _u(31) #define SIO_SPINLOCK6_LSB _u(0) -#define SIO_SPINLOCK6_ACCESS "RO" +#define SIO_SPINLOCK6_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK7 // Description : Reading from a spinlock address will: @@ -1267,7 +1269,7 @@ #define SIO_SPINLOCK7_RESET _u(0x00000000) #define SIO_SPINLOCK7_MSB _u(31) #define SIO_SPINLOCK7_LSB _u(0) -#define SIO_SPINLOCK7_ACCESS "RO" +#define SIO_SPINLOCK7_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK8 // Description : Reading from a spinlock address will: @@ -1283,7 +1285,7 @@ #define SIO_SPINLOCK8_RESET _u(0x00000000) #define SIO_SPINLOCK8_MSB _u(31) #define SIO_SPINLOCK8_LSB _u(0) -#define SIO_SPINLOCK8_ACCESS "RO" +#define SIO_SPINLOCK8_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK9 // Description : Reading from a spinlock address will: @@ -1299,7 +1301,7 @@ #define SIO_SPINLOCK9_RESET _u(0x00000000) #define SIO_SPINLOCK9_MSB _u(31) #define SIO_SPINLOCK9_LSB _u(0) -#define SIO_SPINLOCK9_ACCESS "RO" +#define SIO_SPINLOCK9_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK10 // Description : Reading from a spinlock address will: @@ -1315,7 +1317,7 @@ #define SIO_SPINLOCK10_RESET _u(0x00000000) #define SIO_SPINLOCK10_MSB _u(31) #define SIO_SPINLOCK10_LSB _u(0) -#define SIO_SPINLOCK10_ACCESS "RO" +#define SIO_SPINLOCK10_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK11 // Description : Reading from a spinlock address will: @@ -1331,7 +1333,7 @@ #define SIO_SPINLOCK11_RESET _u(0x00000000) #define SIO_SPINLOCK11_MSB _u(31) #define SIO_SPINLOCK11_LSB _u(0) -#define SIO_SPINLOCK11_ACCESS "RO" +#define SIO_SPINLOCK11_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK12 // Description : Reading from a spinlock address will: @@ -1347,7 +1349,7 @@ #define SIO_SPINLOCK12_RESET _u(0x00000000) #define SIO_SPINLOCK12_MSB _u(31) #define SIO_SPINLOCK12_LSB _u(0) -#define SIO_SPINLOCK12_ACCESS "RO" +#define SIO_SPINLOCK12_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK13 // Description : Reading from a spinlock address will: @@ -1363,7 +1365,7 @@ #define SIO_SPINLOCK13_RESET _u(0x00000000) #define SIO_SPINLOCK13_MSB _u(31) #define SIO_SPINLOCK13_LSB _u(0) -#define SIO_SPINLOCK13_ACCESS "RO" +#define SIO_SPINLOCK13_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK14 // Description : Reading from a spinlock address will: @@ -1379,7 +1381,7 @@ #define SIO_SPINLOCK14_RESET _u(0x00000000) #define SIO_SPINLOCK14_MSB _u(31) #define SIO_SPINLOCK14_LSB _u(0) -#define SIO_SPINLOCK14_ACCESS "RO" +#define SIO_SPINLOCK14_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK15 // Description : Reading from a spinlock address will: @@ -1395,7 +1397,7 @@ #define SIO_SPINLOCK15_RESET _u(0x00000000) #define SIO_SPINLOCK15_MSB _u(31) #define SIO_SPINLOCK15_LSB _u(0) -#define SIO_SPINLOCK15_ACCESS "RO" +#define SIO_SPINLOCK15_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK16 // Description : Reading from a spinlock address will: @@ -1411,7 +1413,7 @@ #define SIO_SPINLOCK16_RESET _u(0x00000000) #define SIO_SPINLOCK16_MSB _u(31) #define SIO_SPINLOCK16_LSB _u(0) -#define SIO_SPINLOCK16_ACCESS "RO" +#define SIO_SPINLOCK16_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK17 // Description : Reading from a spinlock address will: @@ -1427,7 +1429,7 @@ #define SIO_SPINLOCK17_RESET _u(0x00000000) #define SIO_SPINLOCK17_MSB _u(31) #define SIO_SPINLOCK17_LSB _u(0) -#define SIO_SPINLOCK17_ACCESS "RO" +#define SIO_SPINLOCK17_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK18 // Description : Reading from a spinlock address will: @@ -1443,7 +1445,7 @@ #define SIO_SPINLOCK18_RESET _u(0x00000000) #define SIO_SPINLOCK18_MSB _u(31) #define SIO_SPINLOCK18_LSB _u(0) -#define SIO_SPINLOCK18_ACCESS "RO" +#define SIO_SPINLOCK18_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK19 // Description : Reading from a spinlock address will: @@ -1459,7 +1461,7 @@ #define SIO_SPINLOCK19_RESET _u(0x00000000) #define SIO_SPINLOCK19_MSB _u(31) #define SIO_SPINLOCK19_LSB _u(0) -#define SIO_SPINLOCK19_ACCESS "RO" +#define SIO_SPINLOCK19_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK20 // Description : Reading from a spinlock address will: @@ -1475,7 +1477,7 @@ #define SIO_SPINLOCK20_RESET _u(0x00000000) #define SIO_SPINLOCK20_MSB _u(31) #define SIO_SPINLOCK20_LSB _u(0) -#define SIO_SPINLOCK20_ACCESS "RO" +#define SIO_SPINLOCK20_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK21 // Description : Reading from a spinlock address will: @@ -1491,7 +1493,7 @@ #define SIO_SPINLOCK21_RESET _u(0x00000000) #define SIO_SPINLOCK21_MSB _u(31) #define SIO_SPINLOCK21_LSB _u(0) -#define SIO_SPINLOCK21_ACCESS "RO" +#define SIO_SPINLOCK21_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK22 // Description : Reading from a spinlock address will: @@ -1507,7 +1509,7 @@ #define SIO_SPINLOCK22_RESET _u(0x00000000) #define SIO_SPINLOCK22_MSB _u(31) #define SIO_SPINLOCK22_LSB _u(0) -#define SIO_SPINLOCK22_ACCESS "RO" +#define SIO_SPINLOCK22_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK23 // Description : Reading from a spinlock address will: @@ -1523,7 +1525,7 @@ #define SIO_SPINLOCK23_RESET _u(0x00000000) #define SIO_SPINLOCK23_MSB _u(31) #define SIO_SPINLOCK23_LSB _u(0) -#define SIO_SPINLOCK23_ACCESS "RO" +#define SIO_SPINLOCK23_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK24 // Description : Reading from a spinlock address will: @@ -1539,7 +1541,7 @@ #define SIO_SPINLOCK24_RESET _u(0x00000000) #define SIO_SPINLOCK24_MSB _u(31) #define SIO_SPINLOCK24_LSB _u(0) -#define SIO_SPINLOCK24_ACCESS "RO" +#define SIO_SPINLOCK24_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK25 // Description : Reading from a spinlock address will: @@ -1555,7 +1557,7 @@ #define SIO_SPINLOCK25_RESET _u(0x00000000) #define SIO_SPINLOCK25_MSB _u(31) #define SIO_SPINLOCK25_LSB _u(0) -#define SIO_SPINLOCK25_ACCESS "RO" +#define SIO_SPINLOCK25_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK26 // Description : Reading from a spinlock address will: @@ -1571,7 +1573,7 @@ #define SIO_SPINLOCK26_RESET _u(0x00000000) #define SIO_SPINLOCK26_MSB _u(31) #define SIO_SPINLOCK26_LSB _u(0) -#define SIO_SPINLOCK26_ACCESS "RO" +#define SIO_SPINLOCK26_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK27 // Description : Reading from a spinlock address will: @@ -1587,7 +1589,7 @@ #define SIO_SPINLOCK27_RESET _u(0x00000000) #define SIO_SPINLOCK27_MSB _u(31) #define SIO_SPINLOCK27_LSB _u(0) -#define SIO_SPINLOCK27_ACCESS "RO" +#define SIO_SPINLOCK27_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK28 // Description : Reading from a spinlock address will: @@ -1603,7 +1605,7 @@ #define SIO_SPINLOCK28_RESET _u(0x00000000) #define SIO_SPINLOCK28_MSB _u(31) #define SIO_SPINLOCK28_LSB _u(0) -#define SIO_SPINLOCK28_ACCESS "RO" +#define SIO_SPINLOCK28_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK29 // Description : Reading from a spinlock address will: @@ -1619,7 +1621,7 @@ #define SIO_SPINLOCK29_RESET _u(0x00000000) #define SIO_SPINLOCK29_MSB _u(31) #define SIO_SPINLOCK29_LSB _u(0) -#define SIO_SPINLOCK29_ACCESS "RO" +#define SIO_SPINLOCK29_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK30 // Description : Reading from a spinlock address will: @@ -1635,7 +1637,7 @@ #define SIO_SPINLOCK30_RESET _u(0x00000000) #define SIO_SPINLOCK30_MSB _u(31) #define SIO_SPINLOCK30_LSB _u(0) -#define SIO_SPINLOCK30_ACCESS "RO" +#define SIO_SPINLOCK30_ACCESS "RW" // ============================================================================= // Register : SIO_SPINLOCK31 // Description : Reading from a spinlock address will: @@ -1651,6 +1653,7 @@ #define SIO_SPINLOCK31_RESET _u(0x00000000) #define SIO_SPINLOCK31_MSB _u(31) #define SIO_SPINLOCK31_LSB _u(0) -#define SIO_SPINLOCK31_ACCESS "RO" +#define SIO_SPINLOCK31_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_SIO_DEFINED +#endif // _HARDWARE_REGS_SIO_H + diff --git a/lib/rp2040/hardware/regs/spi.h b/lib/pico-sdk/rp2040/hardware/regs/spi.h similarity index 99% rename from lib/rp2040/hardware/regs/spi.h rename to lib/pico-sdk/rp2040/hardware/regs/spi.h index 816e150249a1..d9d3b14df67a 100644 --- a/lib/rp2040/hardware/regs/spi.h +++ b/lib/pico-sdk/rp2040/hardware/regs/spi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : SPI // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_SPI_DEFINED -#define HARDWARE_REGS_SPI_DEFINED +#ifndef _HARDWARE_REGS_SPI_H +#define _HARDWARE_REGS_SPI_H // ============================================================================= // Register : SPI_SSPCR0 // Description : Control register 0, SSPCR0 on page 3-4 @@ -518,4 +519,5 @@ #define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0) #define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_SPI_DEFINED +#endif // _HARDWARE_REGS_SPI_H + diff --git a/lib/rp2040/hardware/regs/ssi.h b/lib/pico-sdk/rp2040/hardware/regs/ssi.h similarity index 95% rename from lib/rp2040/hardware/regs/ssi.h rename to lib/pico-sdk/rp2040/hardware/regs/ssi.h index 67fddc0a4ec0..7fe6aa6aace6 100644 --- a/lib/rp2040/hardware/regs/ssi.h +++ b/lib/pico-sdk/rp2040/hardware/regs/ssi.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,8 +71,8 @@ // - Serial clock phase – capture on first edge of serial-clock // directly after reset. // ============================================================================= -#ifndef HARDWARE_REGS_SSI_DEFINED -#define HARDWARE_REGS_SSI_DEFINED +#ifndef _HARDWARE_REGS_SSI_H +#define _HARDWARE_REGS_SSI_H // ============================================================================= // Register : SSI_CTRLR0 // Description : Control register 0 @@ -88,16 +90,15 @@ // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SPI_FRF // Description : SPI frame format -// 0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK, -// full-duplex +// 0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex // 0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex // 0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex -#define SSI_CTRLR0_SPI_FRF_RESET _u(0x0) -#define SSI_CTRLR0_SPI_FRF_BITS _u(0x00600000) -#define SSI_CTRLR0_SPI_FRF_MSB _u(22) -#define SSI_CTRLR0_SPI_FRF_LSB _u(21) -#define SSI_CTRLR0_SPI_FRF_ACCESS "RW" -#define SSI_CTRLR0_SPI_FRF_VALUE_STD _u(0x0) +#define SSI_CTRLR0_SPI_FRF_RESET _u(0x0) +#define SSI_CTRLR0_SPI_FRF_BITS _u(0x00600000) +#define SSI_CTRLR0_SPI_FRF_MSB _u(22) +#define SSI_CTRLR0_SPI_FRF_LSB _u(21) +#define SSI_CTRLR0_SPI_FRF_ACCESS "RW" +#define SSI_CTRLR0_SPI_FRF_VALUE_STD _u(0x0) #define SSI_CTRLR0_SPI_FRF_VALUE_DUAL _u(0x1) #define SSI_CTRLR0_SPI_FRF_VALUE_QUAD _u(0x2) // ----------------------------------------------------------------------------- @@ -140,16 +141,15 @@ // 0x0 -> Both transmit and receive // 0x1 -> Transmit only (not for FRF == 0, standard SPI mode) // 0x2 -> Receive only (not for FRF == 0, standard SPI mode) -// 0x3 -> EEPROM read mode (TX then RX; RX starts after control -// data TX'd) -#define SSI_CTRLR0_TMOD_RESET _u(0x0) -#define SSI_CTRLR0_TMOD_BITS _u(0x00000300) -#define SSI_CTRLR0_TMOD_MSB _u(9) -#define SSI_CTRLR0_TMOD_LSB _u(8) -#define SSI_CTRLR0_TMOD_ACCESS "RW" -#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX _u(0x0) -#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY _u(0x1) -#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY _u(0x2) +// 0x3 -> EEPROM read mode (TX then RX; RX starts after control data TX'd) +#define SSI_CTRLR0_TMOD_RESET _u(0x0) +#define SSI_CTRLR0_TMOD_BITS _u(0x00000300) +#define SSI_CTRLR0_TMOD_MSB _u(9) +#define SSI_CTRLR0_TMOD_LSB _u(8) +#define SSI_CTRLR0_TMOD_ACCESS "RW" +#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX _u(0x0) +#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY _u(0x1) +#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY _u(0x2) #define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ _u(0x3) // ----------------------------------------------------------------------------- // Field : SSI_CTRLR0_SCPOL @@ -758,15 +758,15 @@ // 0x1 -> 4-bit instruction // 0x2 -> 8-bit instruction // 0x3 -> 16-bit instruction -#define SSI_SPI_CTRLR0_INST_L_RESET _u(0x0) -#define SSI_SPI_CTRLR0_INST_L_BITS _u(0x00000300) -#define SSI_SPI_CTRLR0_INST_L_MSB _u(9) -#define SSI_SPI_CTRLR0_INST_L_LSB _u(8) -#define SSI_SPI_CTRLR0_INST_L_ACCESS "RW" +#define SSI_SPI_CTRLR0_INST_L_RESET _u(0x0) +#define SSI_SPI_CTRLR0_INST_L_BITS _u(0x00000300) +#define SSI_SPI_CTRLR0_INST_L_MSB _u(9) +#define SSI_SPI_CTRLR0_INST_L_LSB _u(8) +#define SSI_SPI_CTRLR0_INST_L_ACCESS "RW" #define SSI_SPI_CTRLR0_INST_L_VALUE_NONE _u(0x0) -#define SSI_SPI_CTRLR0_INST_L_VALUE_4B _u(0x1) -#define SSI_SPI_CTRLR0_INST_L_VALUE_8B _u(0x2) -#define SSI_SPI_CTRLR0_INST_L_VALUE_16B _u(0x3) +#define SSI_SPI_CTRLR0_INST_L_VALUE_4B _u(0x1) +#define SSI_SPI_CTRLR0_INST_L_VALUE_8B _u(0x2) +#define SSI_SPI_CTRLR0_INST_L_VALUE_16B _u(0x3) // ----------------------------------------------------------------------------- // Field : SSI_SPI_CTRLR0_ADDR_L // Description : Address length (0b-60b in 4b increments) @@ -779,15 +779,13 @@ // Field : SSI_SPI_CTRLR0_TRANS_TYPE // Description : Address and instruction transfer format // 0x0 -> Command and address both in standard SPI frame format -// 0x1 -> Command in standard SPI format, address in format -// specified by FRF -// 0x2 -> Command and address both in format specified by FRF -// (e.g. Dual-SPI) -#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET _u(0x0) -#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS _u(0x00000003) -#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB _u(1) -#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB _u(0) -#define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS "RW" +// 0x1 -> Command in standard SPI format, address in format specified by FRF +// 0x2 -> Command and address both in format specified by FRF (e.g. Dual-SPI) +#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET _u(0x0) +#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS _u(0x00000003) +#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB _u(1) +#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB _u(0) +#define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS "RW" #define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A _u(0x0) #define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A _u(0x1) #define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A _u(0x2) @@ -806,4 +804,5 @@ #define SSI_TXD_DRIVE_EDGE_TDE_LSB _u(0) #define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_SSI_DEFINED +#endif // _HARDWARE_REGS_SSI_H + diff --git a/lib/rp2040/hardware/regs/syscfg.h b/lib/pico-sdk/rp2040/hardware/regs/syscfg.h similarity index 97% rename from lib/rp2040/hardware/regs/syscfg.h rename to lib/pico-sdk/rp2040/hardware/regs/syscfg.h index 2bf09e26fad1..96672bb499cd 100644 --- a/lib/rp2040/hardware/regs/syscfg.h +++ b/lib/pico-sdk/rp2040/hardware/regs/syscfg.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : apb // Description : Register block for various chip control signals // ============================================================================= -#ifndef HARDWARE_REGS_SYSCFG_DEFINED -#define HARDWARE_REGS_SYSCFG_DEFINED +#ifndef _HARDWARE_REGS_SYSCFG_H +#define _HARDWARE_REGS_SYSCFG_H // ============================================================================= // Register : SYSCFG_PROC0_NMI_MASK // Description : Processor core 0 NMI source mask @@ -191,7 +193,6 @@ #define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_ROM -// Description : None #define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000080) #define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(7) @@ -199,7 +200,6 @@ #define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_USB -// Description : None #define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000040) #define SYSCFG_MEMPOWERDOWN_USB_MSB _u(6) @@ -207,7 +207,6 @@ #define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM5 -// Description : None #define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020) #define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5) @@ -215,7 +214,6 @@ #define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM4 -// Description : None #define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010) #define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4) @@ -223,7 +221,6 @@ #define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM3 -// Description : None #define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008) #define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3) @@ -231,7 +228,6 @@ #define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM2 -// Description : None #define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004) #define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2) @@ -239,7 +235,6 @@ #define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM1 -// Description : None #define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002) #define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1) @@ -247,11 +242,11 @@ #define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : SYSCFG_MEMPOWERDOWN_SRAM0 -// Description : None #define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0) #define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001) #define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0) #define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0) #define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_SYSCFG_DEFINED +#endif // _HARDWARE_REGS_SYSCFG_H + diff --git a/lib/rp2040/hardware/regs/sysinfo.h b/lib/pico-sdk/rp2040/hardware/regs/sysinfo.h similarity index 90% rename from lib/rp2040/hardware/regs/sysinfo.h rename to lib/pico-sdk/rp2040/hardware/regs/sysinfo.h index 2a46658e2ee8..e0cf2efabc80 100644 --- a/lib/rp2040/hardware/regs/sysinfo.h +++ b/lib/pico-sdk/rp2040/hardware/regs/sysinfo.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : SYSINFO // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_SYSINFO_DEFINED -#define HARDWARE_REGS_SYSINFO_DEFINED +#ifndef _HARDWARE_REGS_SYSINFO_H +#define _HARDWARE_REGS_SYSINFO_H // ============================================================================= // Register : SYSINFO_CHIP_ID // Description : JEDEC JEP-106 compliant chip identifier. @@ -19,7 +20,6 @@ #define SYSINFO_CHIP_ID_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_REVISION -// Description : None #define SYSINFO_CHIP_ID_REVISION_RESET "-" #define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000) #define SYSINFO_CHIP_ID_REVISION_MSB _u(31) @@ -27,7 +27,6 @@ #define SYSINFO_CHIP_ID_REVISION_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_PART -// Description : None #define SYSINFO_CHIP_ID_PART_RESET "-" #define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000) #define SYSINFO_CHIP_ID_PART_MSB _u(27) @@ -35,7 +34,6 @@ #define SYSINFO_CHIP_ID_PART_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_CHIP_ID_MANUFACTURER -// Description : None #define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-" #define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000fff) #define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11) @@ -50,7 +48,6 @@ #define SYSINFO_PLATFORM_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : SYSINFO_PLATFORM_ASIC -// Description : None #define SYSINFO_PLATFORM_ASIC_RESET _u(0x0) #define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002) #define SYSINFO_PLATFORM_ASIC_MSB _u(1) @@ -58,7 +55,6 @@ #define SYSINFO_PLATFORM_ASIC_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : SYSINFO_PLATFORM_FPGA -// Description : None #define SYSINFO_PLATFORM_FPGA_RESET _u(0x0) #define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001) #define SYSINFO_PLATFORM_FPGA_MSB _u(0) @@ -67,11 +63,12 @@ // ============================================================================= // Register : SYSINFO_GITREF_RP2040 // Description : Git hash of the chip source. Used to identify chip version. -#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000040) +#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000010) #define SYSINFO_GITREF_RP2040_BITS _u(0xffffffff) #define SYSINFO_GITREF_RP2040_RESET "-" #define SYSINFO_GITREF_RP2040_MSB _u(31) #define SYSINFO_GITREF_RP2040_LSB _u(0) #define SYSINFO_GITREF_RP2040_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_SYSINFO_DEFINED +#endif // _HARDWARE_REGS_SYSINFO_H + diff --git a/lib/rp2040/hardware/regs/tbman.h b/lib/pico-sdk/rp2040/hardware/regs/tbman.h similarity index 88% rename from lib/rp2040/hardware/regs/tbman.h rename to lib/pico-sdk/rp2040/hardware/regs/tbman.h index 4f8f641321d2..49b627c849c8 100644 --- a/lib/rp2040/hardware/regs/tbman.h +++ b/lib/pico-sdk/rp2040/hardware/regs/tbman.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,8 +12,8 @@ // Description : Testbench manager. Allows the programmer to know what // platform their software is running on. // ============================================================================= -#ifndef HARDWARE_REGS_TBMAN_DEFINED -#define HARDWARE_REGS_TBMAN_DEFINED +#ifndef _HARDWARE_REGS_TBMAN_H +#define _HARDWARE_REGS_TBMAN_H // ============================================================================= // Register : TBMAN_PLATFORM // Description : Indicates the type of platform in use @@ -35,4 +37,5 @@ #define TBMAN_PLATFORM_ASIC_LSB _u(0) #define TBMAN_PLATFORM_ASIC_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_TBMAN_DEFINED +#endif // _HARDWARE_REGS_TBMAN_H + diff --git a/lib/rp2040/hardware/regs/timer.h b/lib/pico-sdk/rp2040/hardware/regs/timer.h similarity index 96% rename from lib/rp2040/hardware/regs/timer.h rename to lib/pico-sdk/rp2040/hardware/regs/timer.h index c3ef0c5a1bf1..7cdcbb304182 100644 --- a/lib/rp2040/hardware/regs/timer.h +++ b/lib/pico-sdk/rp2040/hardware/regs/timer.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,8 +27,8 @@ // To clear the interrupt write a 1 to the corresponding // alarm_irq // ============================================================================= -#ifndef HARDWARE_REGS_TIMER_DEFINED -#define HARDWARE_REGS_TIMER_DEFINED +#ifndef _HARDWARE_REGS_TIMER_H +#define _HARDWARE_REGS_TIMER_H // ============================================================================= // Register : TIMER_TIMEHW // Description : Write to bits 63:32 of time @@ -184,7 +186,6 @@ #define TIMER_INTR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_3 -// Description : None #define TIMER_INTR_ALARM_3_RESET _u(0x0) #define TIMER_INTR_ALARM_3_BITS _u(0x00000008) #define TIMER_INTR_ALARM_3_MSB _u(3) @@ -192,7 +193,6 @@ #define TIMER_INTR_ALARM_3_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_2 -// Description : None #define TIMER_INTR_ALARM_2_RESET _u(0x0) #define TIMER_INTR_ALARM_2_BITS _u(0x00000004) #define TIMER_INTR_ALARM_2_MSB _u(2) @@ -200,7 +200,6 @@ #define TIMER_INTR_ALARM_2_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_1 -// Description : None #define TIMER_INTR_ALARM_1_RESET _u(0x0) #define TIMER_INTR_ALARM_1_BITS _u(0x00000002) #define TIMER_INTR_ALARM_1_MSB _u(1) @@ -208,7 +207,6 @@ #define TIMER_INTR_ALARM_1_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : TIMER_INTR_ALARM_0 -// Description : None #define TIMER_INTR_ALARM_0_RESET _u(0x0) #define TIMER_INTR_ALARM_0_BITS _u(0x00000001) #define TIMER_INTR_ALARM_0_MSB _u(0) @@ -222,7 +220,6 @@ #define TIMER_INTE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_3 -// Description : None #define TIMER_INTE_ALARM_3_RESET _u(0x0) #define TIMER_INTE_ALARM_3_BITS _u(0x00000008) #define TIMER_INTE_ALARM_3_MSB _u(3) @@ -230,7 +227,6 @@ #define TIMER_INTE_ALARM_3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_2 -// Description : None #define TIMER_INTE_ALARM_2_RESET _u(0x0) #define TIMER_INTE_ALARM_2_BITS _u(0x00000004) #define TIMER_INTE_ALARM_2_MSB _u(2) @@ -238,7 +234,6 @@ #define TIMER_INTE_ALARM_2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_1 -// Description : None #define TIMER_INTE_ALARM_1_RESET _u(0x0) #define TIMER_INTE_ALARM_1_BITS _u(0x00000002) #define TIMER_INTE_ALARM_1_MSB _u(1) @@ -246,7 +241,6 @@ #define TIMER_INTE_ALARM_1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTE_ALARM_0 -// Description : None #define TIMER_INTE_ALARM_0_RESET _u(0x0) #define TIMER_INTE_ALARM_0_BITS _u(0x00000001) #define TIMER_INTE_ALARM_0_MSB _u(0) @@ -260,7 +254,6 @@ #define TIMER_INTF_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_3 -// Description : None #define TIMER_INTF_ALARM_3_RESET _u(0x0) #define TIMER_INTF_ALARM_3_BITS _u(0x00000008) #define TIMER_INTF_ALARM_3_MSB _u(3) @@ -268,7 +261,6 @@ #define TIMER_INTF_ALARM_3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_2 -// Description : None #define TIMER_INTF_ALARM_2_RESET _u(0x0) #define TIMER_INTF_ALARM_2_BITS _u(0x00000004) #define TIMER_INTF_ALARM_2_MSB _u(2) @@ -276,7 +268,6 @@ #define TIMER_INTF_ALARM_2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_1 -// Description : None #define TIMER_INTF_ALARM_1_RESET _u(0x0) #define TIMER_INTF_ALARM_1_BITS _u(0x00000002) #define TIMER_INTF_ALARM_1_MSB _u(1) @@ -284,7 +275,6 @@ #define TIMER_INTF_ALARM_1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : TIMER_INTF_ALARM_0 -// Description : None #define TIMER_INTF_ALARM_0_RESET _u(0x0) #define TIMER_INTF_ALARM_0_BITS _u(0x00000001) #define TIMER_INTF_ALARM_0_MSB _u(0) @@ -298,7 +288,6 @@ #define TIMER_INTS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_3 -// Description : None #define TIMER_INTS_ALARM_3_RESET _u(0x0) #define TIMER_INTS_ALARM_3_BITS _u(0x00000008) #define TIMER_INTS_ALARM_3_MSB _u(3) @@ -306,7 +295,6 @@ #define TIMER_INTS_ALARM_3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_2 -// Description : None #define TIMER_INTS_ALARM_2_RESET _u(0x0) #define TIMER_INTS_ALARM_2_BITS _u(0x00000004) #define TIMER_INTS_ALARM_2_MSB _u(2) @@ -314,7 +302,6 @@ #define TIMER_INTS_ALARM_2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_1 -// Description : None #define TIMER_INTS_ALARM_1_RESET _u(0x0) #define TIMER_INTS_ALARM_1_BITS _u(0x00000002) #define TIMER_INTS_ALARM_1_MSB _u(1) @@ -322,11 +309,11 @@ #define TIMER_INTS_ALARM_1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : TIMER_INTS_ALARM_0 -// Description : None #define TIMER_INTS_ALARM_0_RESET _u(0x0) #define TIMER_INTS_ALARM_0_BITS _u(0x00000001) #define TIMER_INTS_ALARM_0_MSB _u(0) #define TIMER_INTS_ALARM_0_LSB _u(0) #define TIMER_INTS_ALARM_0_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_TIMER_DEFINED +#endif // _HARDWARE_REGS_TIMER_H + diff --git a/lib/rp2040/hardware/regs/uart.h b/lib/pico-sdk/rp2040/hardware/regs/uart.h similarity index 99% rename from lib/rp2040/hardware/regs/uart.h rename to lib/pico-sdk/rp2040/hardware/regs/uart.h index 409f59821acd..0f7f17ec0fcf 100644 --- a/lib/rp2040/hardware/regs/uart.h +++ b/lib/pico-sdk/rp2040/hardware/regs/uart.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : UART // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_UART_DEFINED -#define HARDWARE_REGS_UART_DEFINED +#ifndef _HARDWARE_REGS_UART_H +#define _HARDWARE_REGS_UART_H // ============================================================================= // Register : UART_UARTDR // Description : Data Register, UARTDR @@ -1145,4 +1146,5 @@ #define UART_UARTPCELLID3_UARTPCELLID3_LSB _u(0) #define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_UART_DEFINED +#endif // _HARDWARE_REGS_UART_H + diff --git a/lib/rp2040/hardware/regs/usb.h b/lib/pico-sdk/rp2040/hardware/regs/usb.h similarity index 96% rename from lib/rp2040/hardware/regs/usb.h rename to lib/pico-sdk/rp2040/hardware/regs/usb.h index 5461c291593c..291f65ee74fc 100644 --- a/lib/rp2040/hardware/regs/usb.h +++ b/lib/pico-sdk/rp2040/hardware/regs/usb.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : ahbl // Description : USB FS/LS controller device registers // ============================================================================= -#ifndef HARDWARE_REGS_USB_DEFINED -#define HARDWARE_REGS_USB_DEFINED +#ifndef _HARDWARE_REGS_USB_H +#define _HARDWARE_REGS_USB_H // ============================================================================= // Register : USB_ADDR_ENDP // Description : Device address and endpoint control @@ -660,7 +662,6 @@ #define USB_SOF_WR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_SOF_WR_COUNT -// Description : None #define USB_SOF_WR_COUNT_RESET _u(0x000) #define USB_SOF_WR_COUNT_BITS _u(0x000007ff) #define USB_SOF_WR_COUNT_MSB _u(10) @@ -676,7 +677,6 @@ #define USB_SOF_RD_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_SOF_RD_COUNT -// Description : None #define USB_SOF_RD_COUNT_RESET _u(0x000) #define USB_SOF_RD_COUNT_BITS _u(0x000007ff) #define USB_SOF_RD_COUNT_MSB _u(10) @@ -1072,7 +1072,7 @@ #define USB_INT_EP_CTRL_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_INT_EP_CTRL_INT_EP_ACTIVE -// Description : Host: Enable interrupt endpoint 1 -> 15 +// Description : Host: Enable interrupt endpoint 1 => 15 #define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET _u(0x0000) #define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS _u(0x0000fffe) #define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB _u(15) @@ -1090,7 +1090,6 @@ #define USB_BUFF_STATUS_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP15_OUT -// Description : None #define USB_BUFF_STATUS_EP15_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP15_OUT_BITS _u(0x80000000) #define USB_BUFF_STATUS_EP15_OUT_MSB _u(31) @@ -1098,7 +1097,6 @@ #define USB_BUFF_STATUS_EP15_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP15_IN -// Description : None #define USB_BUFF_STATUS_EP15_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP15_IN_BITS _u(0x40000000) #define USB_BUFF_STATUS_EP15_IN_MSB _u(30) @@ -1106,7 +1104,6 @@ #define USB_BUFF_STATUS_EP15_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP14_OUT -// Description : None #define USB_BUFF_STATUS_EP14_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP14_OUT_BITS _u(0x20000000) #define USB_BUFF_STATUS_EP14_OUT_MSB _u(29) @@ -1114,7 +1111,6 @@ #define USB_BUFF_STATUS_EP14_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP14_IN -// Description : None #define USB_BUFF_STATUS_EP14_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP14_IN_BITS _u(0x10000000) #define USB_BUFF_STATUS_EP14_IN_MSB _u(28) @@ -1122,7 +1118,6 @@ #define USB_BUFF_STATUS_EP14_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP13_OUT -// Description : None #define USB_BUFF_STATUS_EP13_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP13_OUT_BITS _u(0x08000000) #define USB_BUFF_STATUS_EP13_OUT_MSB _u(27) @@ -1130,7 +1125,6 @@ #define USB_BUFF_STATUS_EP13_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP13_IN -// Description : None #define USB_BUFF_STATUS_EP13_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP13_IN_BITS _u(0x04000000) #define USB_BUFF_STATUS_EP13_IN_MSB _u(26) @@ -1138,7 +1132,6 @@ #define USB_BUFF_STATUS_EP13_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP12_OUT -// Description : None #define USB_BUFF_STATUS_EP12_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP12_OUT_BITS _u(0x02000000) #define USB_BUFF_STATUS_EP12_OUT_MSB _u(25) @@ -1146,7 +1139,6 @@ #define USB_BUFF_STATUS_EP12_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP12_IN -// Description : None #define USB_BUFF_STATUS_EP12_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP12_IN_BITS _u(0x01000000) #define USB_BUFF_STATUS_EP12_IN_MSB _u(24) @@ -1154,7 +1146,6 @@ #define USB_BUFF_STATUS_EP12_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP11_OUT -// Description : None #define USB_BUFF_STATUS_EP11_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP11_OUT_BITS _u(0x00800000) #define USB_BUFF_STATUS_EP11_OUT_MSB _u(23) @@ -1162,7 +1153,6 @@ #define USB_BUFF_STATUS_EP11_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP11_IN -// Description : None #define USB_BUFF_STATUS_EP11_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP11_IN_BITS _u(0x00400000) #define USB_BUFF_STATUS_EP11_IN_MSB _u(22) @@ -1170,7 +1160,6 @@ #define USB_BUFF_STATUS_EP11_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP10_OUT -// Description : None #define USB_BUFF_STATUS_EP10_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP10_OUT_BITS _u(0x00200000) #define USB_BUFF_STATUS_EP10_OUT_MSB _u(21) @@ -1178,7 +1167,6 @@ #define USB_BUFF_STATUS_EP10_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP10_IN -// Description : None #define USB_BUFF_STATUS_EP10_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP10_IN_BITS _u(0x00100000) #define USB_BUFF_STATUS_EP10_IN_MSB _u(20) @@ -1186,7 +1174,6 @@ #define USB_BUFF_STATUS_EP10_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP9_OUT -// Description : None #define USB_BUFF_STATUS_EP9_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP9_OUT_BITS _u(0x00080000) #define USB_BUFF_STATUS_EP9_OUT_MSB _u(19) @@ -1194,7 +1181,6 @@ #define USB_BUFF_STATUS_EP9_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP9_IN -// Description : None #define USB_BUFF_STATUS_EP9_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP9_IN_BITS _u(0x00040000) #define USB_BUFF_STATUS_EP9_IN_MSB _u(18) @@ -1202,7 +1188,6 @@ #define USB_BUFF_STATUS_EP9_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP8_OUT -// Description : None #define USB_BUFF_STATUS_EP8_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP8_OUT_BITS _u(0x00020000) #define USB_BUFF_STATUS_EP8_OUT_MSB _u(17) @@ -1210,7 +1195,6 @@ #define USB_BUFF_STATUS_EP8_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP8_IN -// Description : None #define USB_BUFF_STATUS_EP8_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP8_IN_BITS _u(0x00010000) #define USB_BUFF_STATUS_EP8_IN_MSB _u(16) @@ -1218,7 +1202,6 @@ #define USB_BUFF_STATUS_EP8_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP7_OUT -// Description : None #define USB_BUFF_STATUS_EP7_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP7_OUT_BITS _u(0x00008000) #define USB_BUFF_STATUS_EP7_OUT_MSB _u(15) @@ -1226,7 +1209,6 @@ #define USB_BUFF_STATUS_EP7_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP7_IN -// Description : None #define USB_BUFF_STATUS_EP7_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP7_IN_BITS _u(0x00004000) #define USB_BUFF_STATUS_EP7_IN_MSB _u(14) @@ -1234,7 +1216,6 @@ #define USB_BUFF_STATUS_EP7_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP6_OUT -// Description : None #define USB_BUFF_STATUS_EP6_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP6_OUT_BITS _u(0x00002000) #define USB_BUFF_STATUS_EP6_OUT_MSB _u(13) @@ -1242,7 +1223,6 @@ #define USB_BUFF_STATUS_EP6_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP6_IN -// Description : None #define USB_BUFF_STATUS_EP6_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP6_IN_BITS _u(0x00001000) #define USB_BUFF_STATUS_EP6_IN_MSB _u(12) @@ -1250,7 +1230,6 @@ #define USB_BUFF_STATUS_EP6_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP5_OUT -// Description : None #define USB_BUFF_STATUS_EP5_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP5_OUT_BITS _u(0x00000800) #define USB_BUFF_STATUS_EP5_OUT_MSB _u(11) @@ -1258,7 +1237,6 @@ #define USB_BUFF_STATUS_EP5_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP5_IN -// Description : None #define USB_BUFF_STATUS_EP5_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP5_IN_BITS _u(0x00000400) #define USB_BUFF_STATUS_EP5_IN_MSB _u(10) @@ -1266,7 +1244,6 @@ #define USB_BUFF_STATUS_EP5_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP4_OUT -// Description : None #define USB_BUFF_STATUS_EP4_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP4_OUT_BITS _u(0x00000200) #define USB_BUFF_STATUS_EP4_OUT_MSB _u(9) @@ -1274,7 +1251,6 @@ #define USB_BUFF_STATUS_EP4_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP4_IN -// Description : None #define USB_BUFF_STATUS_EP4_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP4_IN_BITS _u(0x00000100) #define USB_BUFF_STATUS_EP4_IN_MSB _u(8) @@ -1282,7 +1258,6 @@ #define USB_BUFF_STATUS_EP4_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP3_OUT -// Description : None #define USB_BUFF_STATUS_EP3_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP3_OUT_BITS _u(0x00000080) #define USB_BUFF_STATUS_EP3_OUT_MSB _u(7) @@ -1290,7 +1265,6 @@ #define USB_BUFF_STATUS_EP3_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP3_IN -// Description : None #define USB_BUFF_STATUS_EP3_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP3_IN_BITS _u(0x00000040) #define USB_BUFF_STATUS_EP3_IN_MSB _u(6) @@ -1298,7 +1272,6 @@ #define USB_BUFF_STATUS_EP3_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP2_OUT -// Description : None #define USB_BUFF_STATUS_EP2_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP2_OUT_BITS _u(0x00000020) #define USB_BUFF_STATUS_EP2_OUT_MSB _u(5) @@ -1306,7 +1279,6 @@ #define USB_BUFF_STATUS_EP2_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP2_IN -// Description : None #define USB_BUFF_STATUS_EP2_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP2_IN_BITS _u(0x00000010) #define USB_BUFF_STATUS_EP2_IN_MSB _u(4) @@ -1314,7 +1286,6 @@ #define USB_BUFF_STATUS_EP2_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP1_OUT -// Description : None #define USB_BUFF_STATUS_EP1_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP1_OUT_BITS _u(0x00000008) #define USB_BUFF_STATUS_EP1_OUT_MSB _u(3) @@ -1322,7 +1293,6 @@ #define USB_BUFF_STATUS_EP1_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP1_IN -// Description : None #define USB_BUFF_STATUS_EP1_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP1_IN_BITS _u(0x00000004) #define USB_BUFF_STATUS_EP1_IN_MSB _u(2) @@ -1330,7 +1300,6 @@ #define USB_BUFF_STATUS_EP1_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP0_OUT -// Description : None #define USB_BUFF_STATUS_EP0_OUT_RESET _u(0x0) #define USB_BUFF_STATUS_EP0_OUT_BITS _u(0x00000002) #define USB_BUFF_STATUS_EP0_OUT_MSB _u(1) @@ -1338,7 +1307,6 @@ #define USB_BUFF_STATUS_EP0_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_BUFF_STATUS_EP0_IN -// Description : None #define USB_BUFF_STATUS_EP0_IN_RESET _u(0x0) #define USB_BUFF_STATUS_EP0_IN_BITS _u(0x00000001) #define USB_BUFF_STATUS_EP0_IN_MSB _u(0) @@ -1355,7 +1323,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS _u(0x80000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB _u(31) @@ -1363,7 +1330,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS _u(0x40000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB _u(30) @@ -1371,7 +1337,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS _u(0x20000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB _u(29) @@ -1379,7 +1344,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS _u(0x10000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB _u(28) @@ -1387,7 +1351,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS _u(0x08000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB _u(27) @@ -1395,7 +1358,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS _u(0x04000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB _u(26) @@ -1403,7 +1365,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS _u(0x02000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB _u(25) @@ -1411,7 +1372,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS _u(0x01000000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB _u(24) @@ -1419,7 +1379,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS _u(0x00800000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB _u(23) @@ -1427,7 +1386,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS _u(0x00400000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB _u(22) @@ -1435,7 +1393,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS _u(0x00200000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB _u(21) @@ -1443,7 +1400,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS _u(0x00100000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB _u(20) @@ -1451,7 +1407,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS _u(0x00080000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB _u(19) @@ -1459,7 +1414,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS _u(0x00040000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB _u(18) @@ -1467,7 +1421,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS _u(0x00020000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB _u(17) @@ -1475,7 +1428,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS _u(0x00010000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB _u(16) @@ -1483,7 +1435,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS _u(0x00008000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB _u(15) @@ -1491,7 +1442,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS _u(0x00004000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB _u(14) @@ -1499,7 +1449,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS _u(0x00002000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB _u(13) @@ -1507,7 +1456,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS _u(0x00001000) #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB _u(12) @@ -1515,7 +1463,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS _u(0x00000800) #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB _u(11) @@ -1523,7 +1470,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS _u(0x00000400) #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB _u(10) @@ -1531,7 +1477,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS _u(0x00000200) #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB _u(9) @@ -1539,7 +1484,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS _u(0x00000100) #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB _u(8) @@ -1547,7 +1491,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS _u(0x00000080) #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB _u(7) @@ -1555,7 +1498,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS _u(0x00000040) #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB _u(6) @@ -1563,7 +1505,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS _u(0x00000020) #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB _u(5) @@ -1571,7 +1512,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS _u(0x00000010) #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB _u(4) @@ -1579,7 +1519,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS _u(0x00000008) #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB _u(3) @@ -1587,7 +1526,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS _u(0x00000004) #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB _u(2) @@ -1595,7 +1533,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS _u(0x00000002) #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB _u(1) @@ -1603,7 +1540,6 @@ #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN -// Description : None #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET _u(0x0) #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS _u(0x00000001) #define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB _u(0) @@ -1621,7 +1557,6 @@ #define USB_EP_ABORT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP15_OUT -// Description : None #define USB_EP_ABORT_EP15_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP15_OUT_BITS _u(0x80000000) #define USB_EP_ABORT_EP15_OUT_MSB _u(31) @@ -1629,7 +1564,6 @@ #define USB_EP_ABORT_EP15_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP15_IN -// Description : None #define USB_EP_ABORT_EP15_IN_RESET _u(0x0) #define USB_EP_ABORT_EP15_IN_BITS _u(0x40000000) #define USB_EP_ABORT_EP15_IN_MSB _u(30) @@ -1637,7 +1571,6 @@ #define USB_EP_ABORT_EP15_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP14_OUT -// Description : None #define USB_EP_ABORT_EP14_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP14_OUT_BITS _u(0x20000000) #define USB_EP_ABORT_EP14_OUT_MSB _u(29) @@ -1645,7 +1578,6 @@ #define USB_EP_ABORT_EP14_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP14_IN -// Description : None #define USB_EP_ABORT_EP14_IN_RESET _u(0x0) #define USB_EP_ABORT_EP14_IN_BITS _u(0x10000000) #define USB_EP_ABORT_EP14_IN_MSB _u(28) @@ -1653,7 +1585,6 @@ #define USB_EP_ABORT_EP14_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP13_OUT -// Description : None #define USB_EP_ABORT_EP13_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP13_OUT_BITS _u(0x08000000) #define USB_EP_ABORT_EP13_OUT_MSB _u(27) @@ -1661,7 +1592,6 @@ #define USB_EP_ABORT_EP13_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP13_IN -// Description : None #define USB_EP_ABORT_EP13_IN_RESET _u(0x0) #define USB_EP_ABORT_EP13_IN_BITS _u(0x04000000) #define USB_EP_ABORT_EP13_IN_MSB _u(26) @@ -1669,7 +1599,6 @@ #define USB_EP_ABORT_EP13_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP12_OUT -// Description : None #define USB_EP_ABORT_EP12_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP12_OUT_BITS _u(0x02000000) #define USB_EP_ABORT_EP12_OUT_MSB _u(25) @@ -1677,7 +1606,6 @@ #define USB_EP_ABORT_EP12_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP12_IN -// Description : None #define USB_EP_ABORT_EP12_IN_RESET _u(0x0) #define USB_EP_ABORT_EP12_IN_BITS _u(0x01000000) #define USB_EP_ABORT_EP12_IN_MSB _u(24) @@ -1685,7 +1613,6 @@ #define USB_EP_ABORT_EP12_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP11_OUT -// Description : None #define USB_EP_ABORT_EP11_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP11_OUT_BITS _u(0x00800000) #define USB_EP_ABORT_EP11_OUT_MSB _u(23) @@ -1693,7 +1620,6 @@ #define USB_EP_ABORT_EP11_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP11_IN -// Description : None #define USB_EP_ABORT_EP11_IN_RESET _u(0x0) #define USB_EP_ABORT_EP11_IN_BITS _u(0x00400000) #define USB_EP_ABORT_EP11_IN_MSB _u(22) @@ -1701,7 +1627,6 @@ #define USB_EP_ABORT_EP11_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP10_OUT -// Description : None #define USB_EP_ABORT_EP10_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP10_OUT_BITS _u(0x00200000) #define USB_EP_ABORT_EP10_OUT_MSB _u(21) @@ -1709,7 +1634,6 @@ #define USB_EP_ABORT_EP10_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP10_IN -// Description : None #define USB_EP_ABORT_EP10_IN_RESET _u(0x0) #define USB_EP_ABORT_EP10_IN_BITS _u(0x00100000) #define USB_EP_ABORT_EP10_IN_MSB _u(20) @@ -1717,7 +1641,6 @@ #define USB_EP_ABORT_EP10_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP9_OUT -// Description : None #define USB_EP_ABORT_EP9_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP9_OUT_BITS _u(0x00080000) #define USB_EP_ABORT_EP9_OUT_MSB _u(19) @@ -1725,7 +1648,6 @@ #define USB_EP_ABORT_EP9_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP9_IN -// Description : None #define USB_EP_ABORT_EP9_IN_RESET _u(0x0) #define USB_EP_ABORT_EP9_IN_BITS _u(0x00040000) #define USB_EP_ABORT_EP9_IN_MSB _u(18) @@ -1733,7 +1655,6 @@ #define USB_EP_ABORT_EP9_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP8_OUT -// Description : None #define USB_EP_ABORT_EP8_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP8_OUT_BITS _u(0x00020000) #define USB_EP_ABORT_EP8_OUT_MSB _u(17) @@ -1741,7 +1662,6 @@ #define USB_EP_ABORT_EP8_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP8_IN -// Description : None #define USB_EP_ABORT_EP8_IN_RESET _u(0x0) #define USB_EP_ABORT_EP8_IN_BITS _u(0x00010000) #define USB_EP_ABORT_EP8_IN_MSB _u(16) @@ -1749,7 +1669,6 @@ #define USB_EP_ABORT_EP8_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP7_OUT -// Description : None #define USB_EP_ABORT_EP7_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP7_OUT_BITS _u(0x00008000) #define USB_EP_ABORT_EP7_OUT_MSB _u(15) @@ -1757,7 +1676,6 @@ #define USB_EP_ABORT_EP7_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP7_IN -// Description : None #define USB_EP_ABORT_EP7_IN_RESET _u(0x0) #define USB_EP_ABORT_EP7_IN_BITS _u(0x00004000) #define USB_EP_ABORT_EP7_IN_MSB _u(14) @@ -1765,7 +1683,6 @@ #define USB_EP_ABORT_EP7_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP6_OUT -// Description : None #define USB_EP_ABORT_EP6_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP6_OUT_BITS _u(0x00002000) #define USB_EP_ABORT_EP6_OUT_MSB _u(13) @@ -1773,7 +1690,6 @@ #define USB_EP_ABORT_EP6_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP6_IN -// Description : None #define USB_EP_ABORT_EP6_IN_RESET _u(0x0) #define USB_EP_ABORT_EP6_IN_BITS _u(0x00001000) #define USB_EP_ABORT_EP6_IN_MSB _u(12) @@ -1781,7 +1697,6 @@ #define USB_EP_ABORT_EP6_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP5_OUT -// Description : None #define USB_EP_ABORT_EP5_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP5_OUT_BITS _u(0x00000800) #define USB_EP_ABORT_EP5_OUT_MSB _u(11) @@ -1789,7 +1704,6 @@ #define USB_EP_ABORT_EP5_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP5_IN -// Description : None #define USB_EP_ABORT_EP5_IN_RESET _u(0x0) #define USB_EP_ABORT_EP5_IN_BITS _u(0x00000400) #define USB_EP_ABORT_EP5_IN_MSB _u(10) @@ -1797,7 +1711,6 @@ #define USB_EP_ABORT_EP5_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP4_OUT -// Description : None #define USB_EP_ABORT_EP4_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP4_OUT_BITS _u(0x00000200) #define USB_EP_ABORT_EP4_OUT_MSB _u(9) @@ -1805,7 +1718,6 @@ #define USB_EP_ABORT_EP4_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP4_IN -// Description : None #define USB_EP_ABORT_EP4_IN_RESET _u(0x0) #define USB_EP_ABORT_EP4_IN_BITS _u(0x00000100) #define USB_EP_ABORT_EP4_IN_MSB _u(8) @@ -1813,7 +1725,6 @@ #define USB_EP_ABORT_EP4_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP3_OUT -// Description : None #define USB_EP_ABORT_EP3_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP3_OUT_BITS _u(0x00000080) #define USB_EP_ABORT_EP3_OUT_MSB _u(7) @@ -1821,7 +1732,6 @@ #define USB_EP_ABORT_EP3_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP3_IN -// Description : None #define USB_EP_ABORT_EP3_IN_RESET _u(0x0) #define USB_EP_ABORT_EP3_IN_BITS _u(0x00000040) #define USB_EP_ABORT_EP3_IN_MSB _u(6) @@ -1829,7 +1739,6 @@ #define USB_EP_ABORT_EP3_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP2_OUT -// Description : None #define USB_EP_ABORT_EP2_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP2_OUT_BITS _u(0x00000020) #define USB_EP_ABORT_EP2_OUT_MSB _u(5) @@ -1837,7 +1746,6 @@ #define USB_EP_ABORT_EP2_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP2_IN -// Description : None #define USB_EP_ABORT_EP2_IN_RESET _u(0x0) #define USB_EP_ABORT_EP2_IN_BITS _u(0x00000010) #define USB_EP_ABORT_EP2_IN_MSB _u(4) @@ -1845,7 +1753,6 @@ #define USB_EP_ABORT_EP2_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP1_OUT -// Description : None #define USB_EP_ABORT_EP1_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP1_OUT_BITS _u(0x00000008) #define USB_EP_ABORT_EP1_OUT_MSB _u(3) @@ -1853,7 +1760,6 @@ #define USB_EP_ABORT_EP1_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP1_IN -// Description : None #define USB_EP_ABORT_EP1_IN_RESET _u(0x0) #define USB_EP_ABORT_EP1_IN_BITS _u(0x00000004) #define USB_EP_ABORT_EP1_IN_MSB _u(2) @@ -1861,7 +1767,6 @@ #define USB_EP_ABORT_EP1_IN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP0_OUT -// Description : None #define USB_EP_ABORT_EP0_OUT_RESET _u(0x0) #define USB_EP_ABORT_EP0_OUT_BITS _u(0x00000002) #define USB_EP_ABORT_EP0_OUT_MSB _u(1) @@ -1869,7 +1774,6 @@ #define USB_EP_ABORT_EP0_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_EP0_IN -// Description : None #define USB_EP_ABORT_EP0_IN_RESET _u(0x0) #define USB_EP_ABORT_EP0_IN_BITS _u(0x00000001) #define USB_EP_ABORT_EP0_IN_MSB _u(0) @@ -1885,7 +1789,6 @@ #define USB_EP_ABORT_DONE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP15_OUT -// Description : None #define USB_EP_ABORT_DONE_EP15_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP15_OUT_BITS _u(0x80000000) #define USB_EP_ABORT_DONE_EP15_OUT_MSB _u(31) @@ -1893,7 +1796,6 @@ #define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP15_IN -// Description : None #define USB_EP_ABORT_DONE_EP15_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP15_IN_BITS _u(0x40000000) #define USB_EP_ABORT_DONE_EP15_IN_MSB _u(30) @@ -1901,7 +1803,6 @@ #define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP14_OUT -// Description : None #define USB_EP_ABORT_DONE_EP14_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP14_OUT_BITS _u(0x20000000) #define USB_EP_ABORT_DONE_EP14_OUT_MSB _u(29) @@ -1909,7 +1810,6 @@ #define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP14_IN -// Description : None #define USB_EP_ABORT_DONE_EP14_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP14_IN_BITS _u(0x10000000) #define USB_EP_ABORT_DONE_EP14_IN_MSB _u(28) @@ -1917,7 +1817,6 @@ #define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP13_OUT -// Description : None #define USB_EP_ABORT_DONE_EP13_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP13_OUT_BITS _u(0x08000000) #define USB_EP_ABORT_DONE_EP13_OUT_MSB _u(27) @@ -1925,7 +1824,6 @@ #define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP13_IN -// Description : None #define USB_EP_ABORT_DONE_EP13_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP13_IN_BITS _u(0x04000000) #define USB_EP_ABORT_DONE_EP13_IN_MSB _u(26) @@ -1933,7 +1831,6 @@ #define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP12_OUT -// Description : None #define USB_EP_ABORT_DONE_EP12_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP12_OUT_BITS _u(0x02000000) #define USB_EP_ABORT_DONE_EP12_OUT_MSB _u(25) @@ -1941,7 +1838,6 @@ #define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP12_IN -// Description : None #define USB_EP_ABORT_DONE_EP12_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP12_IN_BITS _u(0x01000000) #define USB_EP_ABORT_DONE_EP12_IN_MSB _u(24) @@ -1949,7 +1845,6 @@ #define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP11_OUT -// Description : None #define USB_EP_ABORT_DONE_EP11_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP11_OUT_BITS _u(0x00800000) #define USB_EP_ABORT_DONE_EP11_OUT_MSB _u(23) @@ -1957,7 +1852,6 @@ #define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP11_IN -// Description : None #define USB_EP_ABORT_DONE_EP11_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP11_IN_BITS _u(0x00400000) #define USB_EP_ABORT_DONE_EP11_IN_MSB _u(22) @@ -1965,7 +1859,6 @@ #define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP10_OUT -// Description : None #define USB_EP_ABORT_DONE_EP10_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP10_OUT_BITS _u(0x00200000) #define USB_EP_ABORT_DONE_EP10_OUT_MSB _u(21) @@ -1973,7 +1866,6 @@ #define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP10_IN -// Description : None #define USB_EP_ABORT_DONE_EP10_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP10_IN_BITS _u(0x00100000) #define USB_EP_ABORT_DONE_EP10_IN_MSB _u(20) @@ -1981,7 +1873,6 @@ #define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP9_OUT -// Description : None #define USB_EP_ABORT_DONE_EP9_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP9_OUT_BITS _u(0x00080000) #define USB_EP_ABORT_DONE_EP9_OUT_MSB _u(19) @@ -1989,7 +1880,6 @@ #define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP9_IN -// Description : None #define USB_EP_ABORT_DONE_EP9_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP9_IN_BITS _u(0x00040000) #define USB_EP_ABORT_DONE_EP9_IN_MSB _u(18) @@ -1997,7 +1887,6 @@ #define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP8_OUT -// Description : None #define USB_EP_ABORT_DONE_EP8_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP8_OUT_BITS _u(0x00020000) #define USB_EP_ABORT_DONE_EP8_OUT_MSB _u(17) @@ -2005,7 +1894,6 @@ #define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP8_IN -// Description : None #define USB_EP_ABORT_DONE_EP8_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP8_IN_BITS _u(0x00010000) #define USB_EP_ABORT_DONE_EP8_IN_MSB _u(16) @@ -2013,7 +1901,6 @@ #define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP7_OUT -// Description : None #define USB_EP_ABORT_DONE_EP7_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP7_OUT_BITS _u(0x00008000) #define USB_EP_ABORT_DONE_EP7_OUT_MSB _u(15) @@ -2021,7 +1908,6 @@ #define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP7_IN -// Description : None #define USB_EP_ABORT_DONE_EP7_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP7_IN_BITS _u(0x00004000) #define USB_EP_ABORT_DONE_EP7_IN_MSB _u(14) @@ -2029,7 +1915,6 @@ #define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP6_OUT -// Description : None #define USB_EP_ABORT_DONE_EP6_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP6_OUT_BITS _u(0x00002000) #define USB_EP_ABORT_DONE_EP6_OUT_MSB _u(13) @@ -2037,7 +1922,6 @@ #define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP6_IN -// Description : None #define USB_EP_ABORT_DONE_EP6_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP6_IN_BITS _u(0x00001000) #define USB_EP_ABORT_DONE_EP6_IN_MSB _u(12) @@ -2045,7 +1929,6 @@ #define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP5_OUT -// Description : None #define USB_EP_ABORT_DONE_EP5_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP5_OUT_BITS _u(0x00000800) #define USB_EP_ABORT_DONE_EP5_OUT_MSB _u(11) @@ -2053,7 +1936,6 @@ #define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP5_IN -// Description : None #define USB_EP_ABORT_DONE_EP5_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP5_IN_BITS _u(0x00000400) #define USB_EP_ABORT_DONE_EP5_IN_MSB _u(10) @@ -2061,7 +1943,6 @@ #define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP4_OUT -// Description : None #define USB_EP_ABORT_DONE_EP4_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP4_OUT_BITS _u(0x00000200) #define USB_EP_ABORT_DONE_EP4_OUT_MSB _u(9) @@ -2069,7 +1950,6 @@ #define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP4_IN -// Description : None #define USB_EP_ABORT_DONE_EP4_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP4_IN_BITS _u(0x00000100) #define USB_EP_ABORT_DONE_EP4_IN_MSB _u(8) @@ -2077,7 +1957,6 @@ #define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP3_OUT -// Description : None #define USB_EP_ABORT_DONE_EP3_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP3_OUT_BITS _u(0x00000080) #define USB_EP_ABORT_DONE_EP3_OUT_MSB _u(7) @@ -2085,7 +1964,6 @@ #define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP3_IN -// Description : None #define USB_EP_ABORT_DONE_EP3_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP3_IN_BITS _u(0x00000040) #define USB_EP_ABORT_DONE_EP3_IN_MSB _u(6) @@ -2093,7 +1971,6 @@ #define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP2_OUT -// Description : None #define USB_EP_ABORT_DONE_EP2_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP2_OUT_BITS _u(0x00000020) #define USB_EP_ABORT_DONE_EP2_OUT_MSB _u(5) @@ -2101,7 +1978,6 @@ #define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP2_IN -// Description : None #define USB_EP_ABORT_DONE_EP2_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP2_IN_BITS _u(0x00000010) #define USB_EP_ABORT_DONE_EP2_IN_MSB _u(4) @@ -2109,7 +1985,6 @@ #define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP1_OUT -// Description : None #define USB_EP_ABORT_DONE_EP1_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP1_OUT_BITS _u(0x00000008) #define USB_EP_ABORT_DONE_EP1_OUT_MSB _u(3) @@ -2117,7 +1992,6 @@ #define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP1_IN -// Description : None #define USB_EP_ABORT_DONE_EP1_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP1_IN_BITS _u(0x00000004) #define USB_EP_ABORT_DONE_EP1_IN_MSB _u(2) @@ -2125,7 +1999,6 @@ #define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP0_OUT -// Description : None #define USB_EP_ABORT_DONE_EP0_OUT_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP0_OUT_BITS _u(0x00000002) #define USB_EP_ABORT_DONE_EP0_OUT_MSB _u(1) @@ -2133,7 +2006,6 @@ #define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_ABORT_DONE_EP0_IN -// Description : None #define USB_EP_ABORT_DONE_EP0_IN_RESET _u(0x0) #define USB_EP_ABORT_DONE_EP0_IN_BITS _u(0x00000001) #define USB_EP_ABORT_DONE_EP0_IN_MSB _u(0) @@ -2151,7 +2023,6 @@ #define USB_EP_STALL_ARM_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_STALL_ARM_EP0_OUT -// Description : None #define USB_EP_STALL_ARM_EP0_OUT_RESET _u(0x0) #define USB_EP_STALL_ARM_EP0_OUT_BITS _u(0x00000002) #define USB_EP_STALL_ARM_EP0_OUT_MSB _u(1) @@ -2159,7 +2030,6 @@ #define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_EP_STALL_ARM_EP0_IN -// Description : None #define USB_EP_STALL_ARM_EP0_IN_RESET _u(0x0) #define USB_EP_STALL_ARM_EP0_IN_BITS _u(0x00000001) #define USB_EP_STALL_ARM_EP0_IN_MSB _u(0) @@ -2198,7 +2068,6 @@ #define USB_EP_STATUS_STALL_NAK_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP15_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS _u(0x80000000) #define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB _u(31) @@ -2206,7 +2075,6 @@ #define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP15_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS _u(0x40000000) #define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB _u(30) @@ -2214,7 +2082,6 @@ #define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP14_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS _u(0x20000000) #define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB _u(29) @@ -2222,7 +2089,6 @@ #define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP14_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS _u(0x10000000) #define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB _u(28) @@ -2230,7 +2096,6 @@ #define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP13_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS _u(0x08000000) #define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB _u(27) @@ -2238,7 +2103,6 @@ #define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP13_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS _u(0x04000000) #define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB _u(26) @@ -2246,7 +2110,6 @@ #define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP12_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS _u(0x02000000) #define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB _u(25) @@ -2254,7 +2117,6 @@ #define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP12_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS _u(0x01000000) #define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB _u(24) @@ -2262,7 +2124,6 @@ #define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP11_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS _u(0x00800000) #define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB _u(23) @@ -2270,7 +2131,6 @@ #define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP11_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS _u(0x00400000) #define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB _u(22) @@ -2278,7 +2138,6 @@ #define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP10_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS _u(0x00200000) #define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB _u(21) @@ -2286,7 +2145,6 @@ #define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP10_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS _u(0x00100000) #define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB _u(20) @@ -2294,7 +2152,6 @@ #define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP9_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS _u(0x00080000) #define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB _u(19) @@ -2302,7 +2159,6 @@ #define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP9_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS _u(0x00040000) #define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB _u(18) @@ -2310,7 +2166,6 @@ #define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP8_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS _u(0x00020000) #define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB _u(17) @@ -2318,7 +2173,6 @@ #define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP8_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS _u(0x00010000) #define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB _u(16) @@ -2326,7 +2180,6 @@ #define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP7_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS _u(0x00008000) #define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB _u(15) @@ -2334,7 +2187,6 @@ #define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP7_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS _u(0x00004000) #define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB _u(14) @@ -2342,7 +2194,6 @@ #define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP6_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS _u(0x00002000) #define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB _u(13) @@ -2350,7 +2201,6 @@ #define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP6_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS _u(0x00001000) #define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB _u(12) @@ -2358,7 +2208,6 @@ #define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP5_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS _u(0x00000800) #define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB _u(11) @@ -2366,7 +2215,6 @@ #define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP5_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS _u(0x00000400) #define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB _u(10) @@ -2374,7 +2222,6 @@ #define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP4_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS _u(0x00000200) #define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB _u(9) @@ -2382,7 +2229,6 @@ #define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP4_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS _u(0x00000100) #define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB _u(8) @@ -2390,7 +2236,6 @@ #define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP3_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS _u(0x00000080) #define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB _u(7) @@ -2398,7 +2243,6 @@ #define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP3_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS _u(0x00000040) #define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB _u(6) @@ -2406,7 +2250,6 @@ #define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP2_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS _u(0x00000020) #define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB _u(5) @@ -2414,7 +2257,6 @@ #define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP2_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS _u(0x00000010) #define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB _u(4) @@ -2422,7 +2264,6 @@ #define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP1_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS _u(0x00000008) #define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB _u(3) @@ -2430,7 +2271,6 @@ #define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP1_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS _u(0x00000004) #define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB _u(2) @@ -2438,7 +2278,6 @@ #define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP0_OUT -// Description : None #define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS _u(0x00000002) #define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB _u(1) @@ -2446,7 +2285,6 @@ #define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : USB_EP_STATUS_STALL_NAK_EP0_IN -// Description : None #define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET _u(0x0) #define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS _u(0x00000001) #define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB _u(0) @@ -2461,7 +2299,6 @@ #define USB_USB_MUXING_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_SOFTCON -// Description : None #define USB_USB_MUXING_SOFTCON_RESET _u(0x0) #define USB_USB_MUXING_SOFTCON_BITS _u(0x00000008) #define USB_USB_MUXING_SOFTCON_MSB _u(3) @@ -2469,7 +2306,6 @@ #define USB_USB_MUXING_SOFTCON_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_TO_DIGITAL_PAD -// Description : None #define USB_USB_MUXING_TO_DIGITAL_PAD_RESET _u(0x0) #define USB_USB_MUXING_TO_DIGITAL_PAD_BITS _u(0x00000004) #define USB_USB_MUXING_TO_DIGITAL_PAD_MSB _u(2) @@ -2477,7 +2313,6 @@ #define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_TO_EXTPHY -// Description : None #define USB_USB_MUXING_TO_EXTPHY_RESET _u(0x0) #define USB_USB_MUXING_TO_EXTPHY_BITS _u(0x00000002) #define USB_USB_MUXING_TO_EXTPHY_MSB _u(1) @@ -2485,7 +2320,6 @@ #define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_MUXING_TO_PHY -// Description : None #define USB_USB_MUXING_TO_PHY_RESET _u(0x0) #define USB_USB_MUXING_TO_PHY_BITS _u(0x00000001) #define USB_USB_MUXING_TO_PHY_MSB _u(0) @@ -2495,14 +2329,13 @@ // Register : USB_USB_PWR // Description : Overrides for the power signals in the event that the VBUS // signals are not hooked up to GPIO. Set the value of the -// override and then the override enable to switch over to the +// override and then the override enable so switch over to the // override value. #define USB_USB_PWR_OFFSET _u(0x00000078) #define USB_USB_PWR_BITS _u(0x0000003f) #define USB_USB_PWR_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_OVERCURR_DETECT_EN -// Description : None #define USB_USB_PWR_OVERCURR_DETECT_EN_RESET _u(0x0) #define USB_USB_PWR_OVERCURR_DETECT_EN_BITS _u(0x00000020) #define USB_USB_PWR_OVERCURR_DETECT_EN_MSB _u(5) @@ -2510,7 +2343,6 @@ #define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_OVERCURR_DETECT -// Description : None #define USB_USB_PWR_OVERCURR_DETECT_RESET _u(0x0) #define USB_USB_PWR_OVERCURR_DETECT_BITS _u(0x00000010) #define USB_USB_PWR_OVERCURR_DETECT_MSB _u(4) @@ -2518,7 +2350,6 @@ #define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN -// Description : None #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET _u(0x0) #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS _u(0x00000008) #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB _u(3) @@ -2526,7 +2357,6 @@ #define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_DETECT -// Description : None #define USB_USB_PWR_VBUS_DETECT_RESET _u(0x0) #define USB_USB_PWR_VBUS_DETECT_BITS _u(0x00000004) #define USB_USB_PWR_VBUS_DETECT_MSB _u(2) @@ -2534,7 +2364,6 @@ #define USB_USB_PWR_VBUS_DETECT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_EN_OVERRIDE_EN -// Description : None #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET _u(0x0) #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS _u(0x00000002) #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB _u(1) @@ -2542,7 +2371,6 @@ #define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USB_PWR_VBUS_EN -// Description : None #define USB_USB_PWR_VBUS_EN_RESET _u(0x0) #define USB_USB_PWR_VBUS_EN_BITS _u(0x00000001) #define USB_USB_PWR_VBUS_EN_MSB _u(0) @@ -2550,15 +2378,17 @@ #define USB_USB_PWR_VBUS_EN_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_DIRECT -// Description : This register allows for direct control of the USB phy. Use in -// conjunction with usbphy_direct_override register to enable each -// override bit. +// Description : Note that most functions are driven directly from usb_fsls +// controller. This register allows more detailed control/status +// from the USB PHY. Useful for debug but not expected to be used +// in normal operation +// Use in conjunction with usbphy_direct_override register #define USB_USBPHY_DIRECT_OFFSET _u(0x0000007c) #define USB_USBPHY_DIRECT_BITS _u(0x007fff77) #define USB_USBPHY_DIRECT_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_OVV -// Description : DM over voltage +// Description : Status bit from USB PHY #define USB_USBPHY_DIRECT_DM_OVV_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_OVV_BITS _u(0x00400000) #define USB_USBPHY_DIRECT_DM_OVV_MSB _u(22) @@ -2566,7 +2396,7 @@ #define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_OVV -// Description : DP over voltage +// Description : Status bit from USB PHY #define USB_USBPHY_DIRECT_DP_OVV_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_OVV_BITS _u(0x00200000) #define USB_USBPHY_DIRECT_DP_OVV_MSB _u(21) @@ -2574,7 +2404,7 @@ #define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_OVCN -// Description : DM overcurrent +// Description : Status bit from USB PHY #define USB_USBPHY_DIRECT_DM_OVCN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_OVCN_BITS _u(0x00100000) #define USB_USBPHY_DIRECT_DM_OVCN_MSB _u(20) @@ -2582,7 +2412,7 @@ #define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_OVCN -// Description : DP overcurrent +// Description : Status bit from USB PHY #define USB_USBPHY_DIRECT_DP_OVCN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_OVCN_BITS _u(0x00080000) #define USB_USBPHY_DIRECT_DP_OVCN_MSB _u(19) @@ -2590,7 +2420,8 @@ #define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DM -// Description : DPM pin state +// Description : Status bit from USB PHY +// DPM pin state #define USB_USBPHY_DIRECT_RX_DM_RESET _u(0x0) #define USB_USBPHY_DIRECT_RX_DM_BITS _u(0x00040000) #define USB_USBPHY_DIRECT_RX_DM_MSB _u(18) @@ -2598,7 +2429,8 @@ #define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DP -// Description : DPP pin state +// Description : Status bit from USB PHY +// DPP pin state #define USB_USBPHY_DIRECT_RX_DP_RESET _u(0x0) #define USB_USBPHY_DIRECT_RX_DP_BITS _u(0x00020000) #define USB_USBPHY_DIRECT_RX_DP_MSB _u(17) @@ -2606,7 +2438,8 @@ #define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_DD -// Description : Differential RX +// Description : Status bit from USB PHY +// RX Diff data #define USB_USBPHY_DIRECT_RX_DD_RESET _u(0x0) #define USB_USBPHY_DIRECT_RX_DD_BITS _u(0x00010000) #define USB_USBPHY_DIRECT_RX_DD_MSB _u(16) @@ -2614,9 +2447,6 @@ #define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DIFFMODE -// Description : TX_DIFFMODE=0: Single ended mode -// TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE -// ignored) #define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS _u(0x00008000) #define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB _u(15) @@ -2624,8 +2454,6 @@ #define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_FSSLEW -// Description : TX_FSSLEW=0: Low speed slew rate -// TX_FSSLEW=1: Full speed slew rate #define USB_USBPHY_DIRECT_TX_FSSLEW_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_FSSLEW_BITS _u(0x00004000) #define USB_USBPHY_DIRECT_TX_FSSLEW_MSB _u(14) @@ -2633,8 +2461,6 @@ #define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_PD -// Description : TX power down override (if override enable is set). 1 = powered -// down. #define USB_USBPHY_DIRECT_TX_PD_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_PD_BITS _u(0x00002000) #define USB_USBPHY_DIRECT_TX_PD_MSB _u(13) @@ -2642,8 +2468,6 @@ #define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_RX_PD -// Description : RX power down override (if override enable is set). 1 = powered -// down. #define USB_USBPHY_DIRECT_RX_PD_RESET _u(0x0) #define USB_USBPHY_DIRECT_RX_PD_BITS _u(0x00001000) #define USB_USBPHY_DIRECT_RX_PD_MSB _u(12) @@ -2651,8 +2475,11 @@ #define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DM -// Description : Output data. TX_DIFFMODE=1, Ignored -// TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller +// TX_SEMODE=0, Ignored +// TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. // DPM=TX_DM #define USB_USBPHY_DIRECT_TX_DM_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DM_BITS _u(0x00000800) @@ -2661,9 +2488,12 @@ #define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DP -// Description : Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. -// TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP -// If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller +// TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable +// drive. DPP=TX_DP, DPM=~TX_DP +// TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. // DPP=TX_DP #define USB_USBPHY_DIRECT_TX_DP_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DP_BITS _u(0x00000400) @@ -2672,9 +2502,12 @@ #define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DM_OE -// Description : Output enable. If TX_DIFFMODE=1, Ignored. -// If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - -// DPM driving +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller +// TX_SEMODE=0, Ignored. +// TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM +// driving #define USB_USBPHY_DIRECT_TX_DM_OE_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DM_OE_BITS _u(0x00000200) #define USB_USBPHY_DIRECT_TX_DM_OE_MSB _u(9) @@ -2682,10 +2515,13 @@ #define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_TX_DP_OE -// Description : Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - -// DPP/DPM in Hi-Z state; 1 - DPP/DPM driving -// If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - -// DPP driving +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller +// TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z +// state; 1 - DPP/DPM driving +// TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP +// driving #define USB_USBPHY_DIRECT_TX_DP_OE_RESET _u(0x0) #define USB_USBPHY_DIRECT_TX_DP_OE_BITS _u(0x00000100) #define USB_USBPHY_DIRECT_TX_DP_OE_MSB _u(8) @@ -2693,7 +2529,10 @@ #define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLDN_EN -// Description : DM pull down enable +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller +// 1 - Enable Rpd on DPM #define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS _u(0x00000040) #define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB _u(6) @@ -2701,7 +2540,10 @@ #define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLUP_EN -// Description : DM pull up enable +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller +// 1 - Enable Rpu on DPM #define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS _u(0x00000020) #define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB _u(5) @@ -2709,8 +2551,8 @@ #define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DM_PULLUP_HISEL -// Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - -// Pull = Rpu1 + Rpu2 +// Description : when dm_pullup_en is set high, this enables second resistor. 0 +// - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET _u(0x0) #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS _u(0x00000010) #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB _u(4) @@ -2718,7 +2560,10 @@ #define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLDN_EN -// Description : DP pull down enable +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller +// 1 - Enable Rpd on DPP #define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS _u(0x00000004) #define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB _u(2) @@ -2726,7 +2571,9 @@ #define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLUP_EN -// Description : DP pull up enable +// Description : Value to drive to USB PHY when override enable is set (which +// will override the default value or value driven from USB +// controller #define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS _u(0x00000002) #define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB _u(1) @@ -2734,8 +2581,8 @@ #define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_DP_PULLUP_HISEL -// Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - -// Pull = Rpu1 + Rpu2 +// Description : when dp_pullup_en is set high, this enables second resistor. 0 +// - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET _u(0x0) #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS _u(0x00000001) #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB _u(0) @@ -2743,13 +2590,11 @@ #define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_DIRECT_OVERRIDE -// Description : Override enable for each control in usbphy_direct #define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _u(0x00000080) #define USB_USBPHY_DIRECT_OVERRIDE_BITS _u(0x00009fff) #define USB_USBPHY_DIRECT_OVERRIDE_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN -// Description : None #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS _u(0x00008000) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB _u(15) @@ -2757,7 +2602,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN -// Description : None #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS _u(0x00001000) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB _u(12) @@ -2765,7 +2609,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN -// Description : None #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS _u(0x00000800) #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB _u(11) @@ -2773,7 +2616,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN -// Description : None #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS _u(0x00000400) #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB _u(10) @@ -2781,7 +2623,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN -// Description : None #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS _u(0x00000200) #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB _u(9) @@ -2789,7 +2630,8 @@ #define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN -// Description : None +// Description : Override default value or value driven from USB Controller to +// PHY #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS _u(0x00000100) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB _u(8) @@ -2797,7 +2639,8 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN -// Description : None +// Description : Override default value or value driven from USB Controller to +// PHY #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS _u(0x00000080) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB _u(7) @@ -2805,7 +2648,8 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN -// Description : None +// Description : Override default value or value driven from USB Controller to +// PHY #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS _u(0x00000040) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB _u(6) @@ -2813,7 +2657,8 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN -// Description : None +// Description : Override default value or value driven from USB Controller to +// PHY #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS _u(0x00000020) #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB _u(5) @@ -2821,7 +2666,8 @@ #define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN -// Description : None +// Description : Override default value or value driven from USB Controller to +// PHY #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000010) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB _u(4) @@ -2829,7 +2675,8 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN -// Description : None +// Description : Override default value or value driven from USB Controller to +// PHY #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000008) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB _u(3) @@ -2837,7 +2684,8 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN -// Description : None +// Description : Override default value or value driven from USB Controller to +// PHY #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS _u(0x00000004) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB _u(2) @@ -2845,7 +2693,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN -// Description : None #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000002) #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB _u(1) @@ -2853,7 +2700,6 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN -// Description : None #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000001) #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB _u(0) @@ -2861,7 +2707,10 @@ #define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" // ============================================================================= // Register : USB_USBPHY_TRIM -// Description : Used to adjust trim values of USB phy pull down resistors. +// Description : Note that most functions are driven directly from usb_fsls +// controller. This register allows more detailed control/status +// from the USB PHY. Useful for debug but not expected to be used +// in normal operation #define USB_USBPHY_TRIM_OFFSET _u(0x00000084) #define USB_USBPHY_TRIM_BITS _u(0x00001f1f) #define USB_USBPHY_TRIM_RESET _u(0x00001f1f) @@ -2931,7 +2780,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTR_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTR_DEV_RESUME_FROM_HOST_RESET _u(0x0) #define USB_INTR_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) #define USB_INTR_DEV_RESUME_FROM_HOST_MSB _u(15) @@ -3049,7 +2898,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTR_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTR_HOST_RESUME_RESET _u(0x0) #define USB_INTR_HOST_RESUME_BITS _u(0x00000002) #define USB_INTR_HOST_RESUME_MSB _u(1) @@ -3109,7 +2958,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTE_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTE_DEV_RESUME_FROM_HOST_RESET _u(0x0) #define USB_INTE_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) #define USB_INTE_DEV_RESUME_FROM_HOST_MSB _u(15) @@ -3227,7 +3076,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTE_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTE_HOST_RESUME_RESET _u(0x0) #define USB_INTE_HOST_RESUME_BITS _u(0x00000002) #define USB_INTE_HOST_RESUME_MSB _u(1) @@ -3287,7 +3136,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTF_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTF_DEV_RESUME_FROM_HOST_RESET _u(0x0) #define USB_INTF_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) #define USB_INTF_DEV_RESUME_FROM_HOST_MSB _u(15) @@ -3405,7 +3254,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTF_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTF_HOST_RESUME_RESET _u(0x0) #define USB_INTF_HOST_RESUME_BITS _u(0x00000002) #define USB_INTF_HOST_RESUME_MSB _u(1) @@ -3465,7 +3314,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTS_DEV_RESUME_FROM_HOST // Description : Set when the device receives a resume from the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTS_DEV_RESUME_FROM_HOST_RESET _u(0x0) #define USB_INTS_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) #define USB_INTS_DEV_RESUME_FROM_HOST_MSB _u(15) @@ -3583,7 +3432,7 @@ // ----------------------------------------------------------------------------- // Field : USB_INTS_HOST_RESUME // Description : Host: raised when a device wakes up the host. Cleared by -// writing to SIE_STATUS.RESUME +// writing to SIE_STATUS.RESUME_REMOTE #define USB_INTS_HOST_RESUME_RESET _u(0x0) #define USB_INTS_HOST_RESUME_BITS _u(0x00000002) #define USB_INTS_HOST_RESUME_MSB _u(1) @@ -3600,4 +3449,5 @@ #define USB_INTS_HOST_CONN_DIS_LSB _u(0) #define USB_INTS_HOST_CONN_DIS_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_USB_DEFINED +#endif // _HARDWARE_REGS_USB_H + diff --git a/lib/pico-sdk/rp2040/hardware/regs/usb_device_dpram.h b/lib/pico-sdk/rp2040/hardware/regs/usb_device_dpram.h new file mode 100644 index 000000000000..d3a5ad32e4dd --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/regs/usb_device_dpram.h @@ -0,0 +1,6753 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : USB_DEVICE_DPRAM +// Version : 1 +// Bus type : ahbl +// Description : DPRAM layout for USB device. +// ============================================================================= +#ifndef _HARDWARE_REGS_USB_DEVICE_DPRAM_H +#define _HARDWARE_REGS_USB_DEVICE_DPRAM_H +// ============================================================================= +// Register : USB_DEVICE_DPRAM_SETUP_PACKET_LOW +// Description : Bytes 0-3 of the SETUP packet from the host. +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_OFFSET _u(0x00000000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_BITS _u(0xffff0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_MSB _u(31) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_LSB _u(16) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_RESET _u(0x00) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_BITS _u(0x0000ff00) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_MSB _u(15) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_LSB _u(8) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_RESET _u(0x00) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_BITS _u(0x000000ff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_MSB _u(7) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_LSB _u(0) +#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH +// Description : Bytes 4-7 of the setup packet from the host. +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_OFFSET _u(0x00000004) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_BITS _u(0xffff0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_MSB _u(31) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_LSB _u(16) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_MSB _u(15) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_LSB _u(0) +#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_IN_CONTROL +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_OFFSET _u(0x00000008) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_OFFSET _u(0x0000000c) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_IN_CONTROL +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_OFFSET _u(0x00000010) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_OFFSET _u(0x00000014) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_IN_CONTROL +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_OFFSET _u(0x00000018) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_OFFSET _u(0x0000001c) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_IN_CONTROL +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_OFFSET _u(0x00000020) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_OFFSET _u(0x00000024) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_IN_CONTROL +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_OFFSET _u(0x00000028) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_OFFSET _u(0x0000002c) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_IN_CONTROL +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_OFFSET _u(0x00000030) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_OFFSET _u(0x00000034) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_IN_CONTROL +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_OFFSET _u(0x00000038) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_OFFSET _u(0x0000003c) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_IN_CONTROL +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_OFFSET _u(0x00000040) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_OFFSET _u(0x00000044) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_IN_CONTROL +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_OFFSET _u(0x00000048) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_OFFSET _u(0x0000004c) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_IN_CONTROL +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_OFFSET _u(0x00000050) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_OFFSET _u(0x00000054) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_IN_CONTROL +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_OFFSET _u(0x00000058) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_OFFSET _u(0x0000005c) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_IN_CONTROL +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_OFFSET _u(0x00000060) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_OFFSET _u(0x00000064) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_IN_CONTROL +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_OFFSET _u(0x00000068) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_OFFSET _u(0x0000006c) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_IN_CONTROL +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_OFFSET _u(0x00000070) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_OFFSET _u(0x00000074) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_IN_CONTROL +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_OFFSET _u(0x00000078) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_OUT_CONTROL +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_OFFSET _u(0x0000007c) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BITS _u(0xfc03ffff) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE +// Description : Enable this endpoint. The device will not reply to any packets +// for this endpoint if this bit is not set. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED +// Description : This endpoint is double buffered. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF +// Description : Trigger an interrupt each time a buffer is done. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF +// Description : Trigger an interrupt each time both buffers are done. Only +// valid in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE +// 0x0 -> Control +// 0x1 -> Isochronous +// 0x2 -> Bulk +// 0x3 -> Interrupt +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL +// Description : Trigger an interrupt if a STALL is sent. Intended for debug +// only. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK +// Description : Trigger an interrupt if a NAK is sent. Intended for debug only. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS +// Description : 64 byte aligned buffer address for this EP (bits 0-5 are +// ignored). Relative to the start of the DPRAM. +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_OFFSET _u(0x00000080) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_OFFSET _u(0x00000084) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_OFFSET _u(0x00000088) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_OFFSET _u(0x0000008c) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_OFFSET _u(0x00000090) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_OFFSET _u(0x00000094) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_OFFSET _u(0x00000098) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_OFFSET _u(0x0000009c) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_OFFSET _u(0x000000a0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_OFFSET _u(0x000000a4) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_OFFSET _u(0x000000a8) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ac) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_OFFSET _u(0x000000b0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_OFFSET _u(0x000000b4) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_OFFSET _u(0x000000b8) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_OFFSET _u(0x000000bc) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_OFFSET _u(0x000000c0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_OFFSET _u(0x000000c4) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_OFFSET _u(0x000000c8) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_OFFSET _u(0x000000cc) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_OFFSET _u(0x000000d0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_OFFSET _u(0x000000d4) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_OFFSET _u(0x000000d8) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_OFFSET _u(0x000000dc) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_OFFSET _u(0x000000e0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_OFFSET _u(0x000000e4) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_OFFSET _u(0x000000e8) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ec) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_OFFSET _u(0x000000f0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_OFFSET _u(0x000000f4) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_OFFSET _u(0x000000f8) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +// Register : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL +// Description : Buffer control for both buffers of an endpoint. Fields ending +// in a _1 are for buffer 1. +// Fields ending in a _0 are for buffer 0. Buffer 1 controls are +// only valid if the endpoint is in double buffered mode. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_OFFSET _u(0x000000fc) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_BITS _u(0xffffffff) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1 +// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1 +// Description : Buffer 1 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1 +// Description : The data pid of buffer 1. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_MSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET +// Description : The number of bytes buffer 1 is offset from buffer 0 in +// Isochronous mode. Only valid in double buffered mode for an +// Isochronous endpoint. +// For a non Isochronous endpoint the offset is always 64 bytes. +// 0x0 -> 128 +// 0x1 -> 256 +// 0x2 -> 512 +// 0x3 -> 1024 +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1 +// Description : Buffer 1 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1 +// Description : The length of the data in buffer 1. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0 +// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit +// is set to indicate the data is valid. For an OUT transfer (RX +// from the host) this bit should be left as a 0. The host will +// set it when it has filled the buffer with data. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0 +// Description : Buffer 0 is the last buffer of the transfer. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0 +// Description : The data pid of buffer 0. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_MSB _u(13) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_LSB _u(13) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET +// Description : Reset the buffer selector to buffer 0. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_MSB _u(12) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_LSB _u(12) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL +// Description : Reply with a stall (valid for both buffers). +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_MSB _u(11) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_LSB _u(11) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0 +// Description : Buffer 0 is available. This bit is set to indicate the buffer +// can be used by the controller. The controller clears the +// available bit when writing the status back. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0 +// Description : The length of the data in buffer 0. +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_USB_DEVICE_DPRAM_H + diff --git a/lib/rp2040/hardware/regs/vreg_and_chip_reset.h b/lib/pico-sdk/rp2040/hardware/regs/vreg_and_chip_reset.h similarity index 96% rename from lib/rp2040/hardware/regs/vreg_and_chip_reset.h rename to lib/pico-sdk/rp2040/hardware/regs/vreg_and_chip_reset.h index 356ff568ac4d..da61c01f1abf 100644 --- a/lib/rp2040/hardware/regs/vreg_and_chip_reset.h +++ b/lib/pico-sdk/rp2040/hardware/regs/vreg_and_chip_reset.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,8 +12,8 @@ // Description : control and status for on-chip voltage regulator and chip // level reset subsystem // ============================================================================= -#ifndef HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED -#define HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED +#ifndef _HARDWARE_REGS_VREG_AND_CHIP_RESET_H +#define _HARDWARE_REGS_VREG_AND_CHIP_RESET_H // ============================================================================= // Register : VREG_AND_CHIP_RESET_VREG // Description : Voltage regulator control and status @@ -148,4 +150,5 @@ #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB _u(8) #define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO" // ============================================================================= -#endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED +#endif // _HARDWARE_REGS_VREG_AND_CHIP_RESET_H + diff --git a/lib/rp2040/hardware/regs/watchdog.h b/lib/pico-sdk/rp2040/hardware/regs/watchdog.h similarity index 97% rename from lib/rp2040/hardware/regs/watchdog.h rename to lib/pico-sdk/rp2040/hardware/regs/watchdog.h index 6a9853d4092e..9c941aede4ee 100644 --- a/lib/rp2040/hardware/regs/watchdog.h +++ b/lib/pico-sdk/rp2040/hardware/regs/watchdog.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +9,9 @@ // Register block : WATCHDOG // Version : 1 // Bus type : apb -// Description : None // ============================================================================= -#ifndef HARDWARE_REGS_WATCHDOG_DEFINED -#define HARDWARE_REGS_WATCHDOG_DEFINED +#ifndef _HARDWARE_REGS_WATCHDOG_H +#define _HARDWARE_REGS_WATCHDOG_H // ============================================================================= // Register : WATCHDOG_CTRL // Description : Watchdog control @@ -89,7 +90,6 @@ #define WATCHDOG_REASON_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : WATCHDOG_REASON_FORCE -// Description : None #define WATCHDOG_REASON_FORCE_RESET _u(0x0) #define WATCHDOG_REASON_FORCE_BITS _u(0x00000002) #define WATCHDOG_REASON_FORCE_MSB _u(1) @@ -97,7 +97,6 @@ #define WATCHDOG_REASON_FORCE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : WATCHDOG_REASON_TIMER -// Description : None #define WATCHDOG_REASON_TIMER_RESET _u(0x0) #define WATCHDOG_REASON_TIMER_BITS _u(0x00000001) #define WATCHDOG_REASON_TIMER_MSB _u(0) @@ -223,4 +222,5 @@ #define WATCHDOG_TICK_CYCLES_LSB _u(0) #define WATCHDOG_TICK_CYCLES_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_WATCHDOG_DEFINED +#endif // _HARDWARE_REGS_WATCHDOG_H + diff --git a/lib/rp2040/hardware/regs/xip.h b/lib/pico-sdk/rp2040/hardware/regs/xip.h similarity index 97% rename from lib/rp2040/hardware/regs/xip.h rename to lib/pico-sdk/rp2040/hardware/regs/xip.h index 3964f67456de..e163f36d549a 100644 --- a/lib/rp2040/hardware/regs/xip.h +++ b/lib/pico-sdk/rp2040/hardware/regs/xip.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : ahb // Description : QSPI flash execute-in-place block // ============================================================================= -#ifndef HARDWARE_REGS_XIP_DEFINED -#define HARDWARE_REGS_XIP_DEFINED +#ifndef _HARDWARE_REGS_XIP_H +#define _HARDWARE_REGS_XIP_H // ============================================================================= // Register : XIP_CTRL // Description : Cache control @@ -159,8 +161,8 @@ // a linear data block from flash to the streaming FIFO. // Decrements automatically (1 at a time) as the stream // progresses, and halts on reaching 0. -// Write 0 to halt an in-progress stream, and discard any -// in-flight +// Write 0 to halt an in-progress stream, and discard any in- +// flight // read, so that a new stream can immediately be started (after // draining the FIFO and reinitialising STREAM_ADDR) #define XIP_STREAM_CTR_OFFSET _u(0x00000018) @@ -184,4 +186,5 @@ #define XIP_STREAM_FIFO_LSB _u(0) #define XIP_STREAM_FIFO_ACCESS "RF" // ============================================================================= -#endif // HARDWARE_REGS_XIP_DEFINED +#endif // _HARDWARE_REGS_XIP_H + diff --git a/lib/rp2040/hardware/regs/xosc.h b/lib/pico-sdk/rp2040/hardware/regs/xosc.h similarity index 74% rename from lib/rp2040/hardware/regs/xosc.h rename to lib/pico-sdk/rp2040/hardware/regs/xosc.h index 4af78b956b22..8076a99d4af3 100644 --- a/lib/rp2040/hardware/regs/xosc.h +++ b/lib/pico-sdk/rp2040/hardware/regs/xosc.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : apb // Description : Controls the crystal oscillator // ============================================================================= -#ifndef HARDWARE_REGS_XOSC_DEFINED -#define HARDWARE_REGS_XOSC_DEFINED +#ifndef _HARDWARE_REGS_XOSC_H +#define _HARDWARE_REGS_XOSC_H // ============================================================================= // Register : XOSC_CTRL // Description : Crystal Oscillator Control @@ -22,34 +24,36 @@ // Description : On power-up this field is initialised to DISABLE and the chip // runs from the ROSC. // If the chip has subsequently been programmed to run from the -// XOSC then setting this field to DISABLE may lock-up the chip. -// If this is a concern then run the clk_ref from the ROSC and -// enable the clk_sys RESUS feature. +// XOSC then DISABLE may lock-up the chip. If this is a concern +// then run the clk_ref from the ROSC and enable the clk_sys RESUS +// feature. // The 12-bit code is intended to give some protection against // accidental writes. An invalid setting will enable the // oscillator. // 0xd1e -> DISABLE // 0xfab -> ENABLE -#define XOSC_CTRL_ENABLE_RESET "-" -#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000) -#define XOSC_CTRL_ENABLE_MSB _u(23) -#define XOSC_CTRL_ENABLE_LSB _u(12) -#define XOSC_CTRL_ENABLE_ACCESS "RW" +#define XOSC_CTRL_ENABLE_RESET "-" +#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000) +#define XOSC_CTRL_ENABLE_MSB _u(23) +#define XOSC_CTRL_ENABLE_LSB _u(12) +#define XOSC_CTRL_ENABLE_ACCESS "RW" #define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) -#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) +#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) // ----------------------------------------------------------------------------- // Field : XOSC_CTRL_FREQ_RANGE -// Description : Frequency range. This resets to 0xAA0 and cannot be changed. +// Description : Frequency range. An invalid setting will retain the previous +// value. The actual value being used can be read from +// STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed. // 0xaa0 -> 1_15MHZ // 0xaa1 -> RESERVED_1 // 0xaa2 -> RESERVED_2 // 0xaa3 -> RESERVED_3 -#define XOSC_CTRL_FREQ_RANGE_RESET "-" -#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) -#define XOSC_CTRL_FREQ_RANGE_MSB _u(11) -#define XOSC_CTRL_FREQ_RANGE_LSB _u(0) -#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW" -#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0) +#define XOSC_CTRL_FREQ_RANGE_RESET "-" +#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) +#define XOSC_CTRL_FREQ_RANGE_MSB _u(11) +#define XOSC_CTRL_FREQ_RANGE_LSB _u(0) +#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW" +#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0) #define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 _u(0xaa1) #define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 _u(0xaa2) #define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 _u(0xaa3) @@ -92,12 +96,12 @@ // 0x1 -> RESERVED_1 // 0x2 -> RESERVED_2 // 0x3 -> RESERVED_3 -#define XOSC_STATUS_FREQ_RANGE_RESET "-" -#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003) -#define XOSC_STATUS_FREQ_RANGE_MSB _u(1) -#define XOSC_STATUS_FREQ_RANGE_LSB _u(0) -#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO" -#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0) +#define XOSC_STATUS_FREQ_RANGE_RESET "-" +#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003) +#define XOSC_STATUS_FREQ_RANGE_MSB _u(1) +#define XOSC_STATUS_FREQ_RANGE_LSB _u(0) +#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO" +#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0) #define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 _u(0x1) #define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 _u(0x2) #define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 _u(0x3) @@ -107,18 +111,18 @@ // This is used to save power by pausing the XOSC // On power-up this field is initialised to WAKE // An invalid write will also select WAKE -// WARNING: stop the PLLs before selecting dormant mode -// WARNING: setup the irq before selecting dormant mode -// 0x636f6d61 -> DORMANT +// Warning: stop the PLLs before selecting dormant mode +// Warning: setup the irq before selecting dormant mode +// 0x636f6d61 -> dormant // 0x77616b65 -> WAKE -#define XOSC_DORMANT_OFFSET _u(0x00000008) -#define XOSC_DORMANT_BITS _u(0xffffffff) -#define XOSC_DORMANT_RESET "-" -#define XOSC_DORMANT_MSB _u(31) -#define XOSC_DORMANT_LSB _u(0) -#define XOSC_DORMANT_ACCESS "RW" +#define XOSC_DORMANT_OFFSET _u(0x00000008) +#define XOSC_DORMANT_BITS _u(0xffffffff) +#define XOSC_DORMANT_RESET "-" +#define XOSC_DORMANT_MSB _u(31) +#define XOSC_DORMANT_LSB _u(0) +#define XOSC_DORMANT_ACCESS "RW" #define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) -#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65) +#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65) // ============================================================================= // Register : XOSC_STARTUP // Description : Controls the startup delay @@ -128,7 +132,7 @@ // ----------------------------------------------------------------------------- // Field : XOSC_STARTUP_X4 // Description : Multiplies the startup_delay by 4. This is of little value to -// the user given that the delay can be programmed directly +// the user given that the delay can be programmed directly. #define XOSC_STARTUP_X4_RESET "-" #define XOSC_STARTUP_X4_BITS _u(0x00100000) #define XOSC_STARTUP_X4_MSB _u(20) @@ -136,7 +140,8 @@ #define XOSC_STARTUP_X4_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : XOSC_STARTUP_DELAY -// Description : in multiples of 256*xtal_period +// Description : in multiples of 256*xtal_period. The reset value of 0xc4 +// corresponds to approx 50 000 cycles. #define XOSC_STARTUP_DELAY_RESET "-" #define XOSC_STARTUP_DELAY_BITS _u(0x00003fff) #define XOSC_STARTUP_DELAY_MSB _u(13) @@ -156,4 +161,5 @@ #define XOSC_COUNT_LSB _u(0) #define XOSC_COUNT_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_XOSC_DEFINED +#endif // _HARDWARE_REGS_XOSC_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/adc.h b/lib/pico-sdk/rp2040/hardware/structs/adc.h new file mode 100644 index 000000000000..a1b6f34c5cfc --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/adc.h @@ -0,0 +1,96 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_ADC_H +#define _HARDWARE_STRUCTS_ADC_H + +/** + * \file rp2040/adc.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/adc.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/adc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(ADC_CS_OFFSET) // ADC_CS + // ADC Control and Status + // 0x001f0000 [20:16] RROBIN (0x00) Round-robin sampling + // 0x00007000 [14:12] AINSEL (0x0) Select analog mux input + // 0x00000400 [10] ERR_STICKY (0) Some past ADC conversion encountered an error + // 0x00000200 [9] ERR (0) The most recent ADC conversion encountered an error;... + // 0x00000100 [8] READY (0) 1 if the ADC is ready to start a new conversion + // 0x00000008 [3] START_MANY (0) Continuously perform conversions whilst this bit is 1 + // 0x00000004 [2] START_ONCE (0) Start a single conversion + // 0x00000002 [1] TS_EN (0) Power on temperature sensor + // 0x00000001 [0] EN (0) Power on ADC and enable its clock + io_rw_32 cs; + + _REG_(ADC_RESULT_OFFSET) // ADC_RESULT + // Result of most recent ADC conversion + // 0x00000fff [11:0] RESULT (0x000) + io_ro_32 result; + + _REG_(ADC_FCS_OFFSET) // ADC_FCS + // FIFO control and status + // 0x0f000000 [27:24] THRESH (0x0) DREQ/IRQ asserted when level >= threshold + // 0x000f0000 [19:16] LEVEL (0x0) The number of conversion results currently waiting in the FIFO + // 0x00000800 [11] OVER (0) 1 if the FIFO has been overflowed + // 0x00000400 [10] UNDER (0) 1 if the FIFO has been underflowed + // 0x00000200 [9] FULL (0) + // 0x00000100 [8] EMPTY (0) + // 0x00000008 [3] DREQ_EN (0) If 1: assert DMA requests when FIFO contains data + // 0x00000004 [2] ERR (0) If 1: conversion error bit appears in the FIFO alongside... + // 0x00000002 [1] SHIFT (0) If 1: FIFO results are right-shifted to be one byte in size + // 0x00000001 [0] EN (0) If 1: write result to the FIFO after each conversion + io_rw_32 fcs; + + _REG_(ADC_FIFO_OFFSET) // ADC_FIFO + // Conversion result FIFO + // 0x00008000 [15] ERR (-) 1 if this particular sample experienced a conversion error + // 0x00000fff [11:0] VAL (-) + io_ro_32 fifo; + + _REG_(ADC_DIV_OFFSET) // ADC_DIV + // Clock divider + // 0x00ffff00 [23:8] INT (0x0000) Integer part of clock divisor + // 0x000000ff [7:0] FRAC (0x00) Fractional part of clock divisor + io_rw_32 div; + + _REG_(ADC_INTR_OFFSET) // ADC_INTR + // Raw Interrupts + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_ro_32 intr; + + _REG_(ADC_INTE_OFFSET) // ADC_INTE + // Interrupt Enable + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_rw_32 inte; + + _REG_(ADC_INTF_OFFSET) // ADC_INTF + // Interrupt Force + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_rw_32 intf; + + _REG_(ADC_INTS_OFFSET) // ADC_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_ro_32 ints; +} adc_hw_t; + +#define adc_hw ((adc_hw_t *)ADC_BASE) +static_assert(sizeof (adc_hw_t) == 0x0024, ""); + +#endif // _HARDWARE_STRUCTS_ADC_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/bus_ctrl.h b/lib/pico-sdk/rp2040/hardware/structs/bus_ctrl.h new file mode 100644 index 000000000000..b94a40459c0f --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/bus_ctrl.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/busctrl.h" +#define bus_ctrl_hw busctrl_hw \ No newline at end of file diff --git a/lib/pico-sdk/rp2040/hardware/structs/busctrl.h b/lib/pico-sdk/rp2040/hardware/structs/busctrl.h new file mode 100644 index 000000000000..65893227dd3d --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/busctrl.h @@ -0,0 +1,85 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_BUSCTRL_H +#define _HARDWARE_STRUCTS_BUSCTRL_H + +/** + * \file rp2040/busctrl.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/busctrl.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** \brief Bus fabric performance counters on RP2040 (used as typedef \ref bus_ctrl_perf_counter_t) + * \ingroup hardware_busctrl + */ +typedef enum bus_ctrl_perf_counter_rp2040 { + arbiter_rom_perf_event_access = 19, + arbiter_rom_perf_event_access_contested = 18, + arbiter_xip_main_perf_event_access = 17, + arbiter_xip_main_perf_event_access_contested = 16, + arbiter_sram0_perf_event_access = 15, + arbiter_sram0_perf_event_access_contested = 14, + arbiter_sram1_perf_event_access = 13, + arbiter_sram1_perf_event_access_contested = 12, + arbiter_sram2_perf_event_access = 11, + arbiter_sram2_perf_event_access_contested = 10, + arbiter_sram3_perf_event_access = 9, + arbiter_sram3_perf_event_access_contested = 8, + arbiter_sram4_perf_event_access = 7, + arbiter_sram4_perf_event_access_contested = 6, + arbiter_sram5_perf_event_access = 5, + arbiter_sram5_perf_event_access_contested = 4, + arbiter_fastperi_perf_event_access = 3, + arbiter_fastperi_perf_event_access_contested = 2, + arbiter_apb_perf_event_access = 1, + arbiter_apb_perf_event_access_contested = 0 +} bus_ctrl_perf_counter_t; + +typedef struct { + _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0 + // Bus fabric performance counter 0 + // 0x00ffffff [23:0] PERFCTR0 (0x000000) Busfabric saturating performance counter 0 + + io_rw_32 value; + + _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0 + // Bus fabric performance event select for PERFCTR0 + // 0x0000001f [4:0] PERFSEL0 (0x1f) Select an event for PERFCTR0 + io_rw_32 sel; +} bus_ctrl_perf_hw_t; + +typedef struct { + _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY + // Set the priority of each master for bus arbitration + // 0x00001000 [12] DMA_W (0) 0 - low priority, 1 - high priority + // 0x00000100 [8] DMA_R (0) 0 - low priority, 1 - high priority + // 0x00000010 [4] PROC1 (0) 0 - low priority, 1 - high priority + // 0x00000001 [0] PROC0 (0) 0 - low priority, 1 - high priority + io_rw_32 priority; + + _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK + // Bus priority acknowledge + // 0x00000001 [0] BUS_PRIORITY_ACK (0) Goes to 1 once all arbiters have registered the new... + io_ro_32 priority_ack; + + bus_ctrl_perf_hw_t counter[4]; +} busctrl_hw_t; + +#define busctrl_hw ((busctrl_hw_t *)BUSCTRL_BASE) +static_assert(sizeof (busctrl_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_BUSCTRL_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/clocks.h b/lib/pico-sdk/rp2040/hardware/structs/clocks.h new file mode 100644 index 000000000000..bdca7ee08db9 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/clocks.h @@ -0,0 +1,504 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_CLOCKS_H +#define _HARDWARE_STRUCTS_CLOCKS_H + +/** + * \file rp2040/clocks.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/clocks.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** \brief Clock numbers on RP2040 (used as typedef \ref clock_num_t) + * \ingroup hardware_clocks + */ +/// \tag::clkenum[] +typedef enum clock_num_rp2040 { + clk_gpout0 = 0, ///< Select CLK_GPOUT0 as clock source + clk_gpout1 = 1, ///< Select CLK_GPOUT1 as clock source + clk_gpout2 = 2, ///< Select CLK_GPOUT2 as clock source + clk_gpout3 = 3, ///< Select CLK_GPOUT3 as clock source + clk_ref = 4, ///< Select CLK_REF as clock source + clk_sys = 5, ///< Select CLK_SYS as clock source + clk_peri = 6, ///< Select CLK_PERI as clock source + clk_usb = 7, ///< Select CLK_USB as clock source + clk_adc = 8, ///< Select CLK_ADC as clock source + clk_rtc = 9, ///< Select CLK_RTC as clock source + CLK_COUNT +} clock_num_t; +/// \end::clkenum[] + +/** \brief Clock destination numbers on RP2040 (used as typedef \ref clock_dest_num_t) + * \ingroup hardware_clocks + */ +typedef enum clock_dest_num_rp2040 { + CLK_DEST_SYS_CLOCKS = 0, ///< Select SYS_CLOCKS as clock destination + CLK_DEST_ADC_ADC = 1, ///< Select ADC_ADC as clock destination + CLK_DEST_SYS_ADC = 2, ///< Select SYS_ADC as clock destination + CLK_DEST_SYS_BUSCTRL = 3, ///< Select SYS_BUSCTRL as clock destination + CLK_DEST_SYS_BUSFABRIC = 4, ///< Select SYS_BUSFABRIC as clock destination + CLK_DEST_SYS_DMA = 5, ///< Select SYS_DMA as clock destination + CLK_DEST_SYS_I2C0 = 6, ///< Select SYS_I2C0 as clock destination + CLK_DEST_SYS_I2C1 = 7, ///< Select SYS_I2C1 as clock destination + CLK_DEST_SYS_IO = 8, ///< Select SYS_IO as clock destination + CLK_DEST_SYS_JTAG = 9, ///< Select SYS_JTAG as clock destination + CLK_DEST_SYS_VREG_AND_CHIP_RESET = 10, ///< Select SYS_VREG_AND_CHIP_RESET as clock destination + CLK_DEST_SYS_PADS = 11, ///< Select SYS_PADS as clock destination + CLK_DEST_SYS_PIO0 = 12, ///< Select SYS_PIO0 as clock destination + CLK_DEST_SYS_PIO1 = 13, ///< Select SYS_PIO1 as clock destination + CLK_DEST_SYS_PLL_SYS = 14, ///< Select SYS_PLL_SYS as clock destination + CLK_DEST_SYS_PLL_USB = 15, ///< Select SYS_PLL_USB as clock destination + CLK_DEST_SYS_PSM = 16, ///< Select SYS_PSM as clock destination + CLK_DEST_SYS_PWM = 17, ///< Select SYS_PWM as clock destination + CLK_DEST_SYS_RESETS = 18, ///< Select SYS_RESETS as clock destination + CLK_DEST_SYS_ROM = 19, ///< Select SYS_ROM as clock destination + CLK_DEST_SYS_ROSC = 20, ///< Select SYS_ROSC as clock destination + CLK_DEST_RTC_RTC = 21, ///< Select RTC_RTC as clock destination + CLK_DEST_SYS_RTC = 22, ///< Select SYS_RTC as clock destination + CLK_DEST_SYS_SIO = 23, ///< Select SYS_SIO as clock destination + CLK_DEST_PERI_SPI0 = 24, ///< Select PERI_SPI0 as clock destination + CLK_DEST_SYS_SPI0 = 25, ///< Select SYS_SPI0 as clock destination + CLK_DEST_PERI_SPI1 = 26, ///< Select PERI_SPI1 as clock destination + CLK_DEST_SYS_SPI1 = 27, ///< Select SYS_SPI1 as clock destination + CLK_DEST_SYS_SRAM0 = 28, ///< Select SYS_SRAM0 as clock destination + CLK_DEST_SYS_SRAM1 = 29, ///< Select SYS_SRAM1 as clock destination + CLK_DEST_SYS_SRAM2 = 30, ///< Select SYS_SRAM2 as clock destination + CLK_DEST_SYS_SRAM3 = 31, ///< Select SYS_SRAM3 as clock destination + CLK_DEST_SYS_SRAM4 = 32, ///< Select SYS_SRAM4 as clock destination + CLK_DEST_SYS_SRAM5 = 33, ///< Select SYS_SRAM5 as clock destination + CLK_DEST_SYS_SYSCFG = 34, ///< Select SYS_SYSCFG as clock destination + CLK_DEST_SYS_SYSINFO = 35, ///< Select SYS_SYSINFO as clock destination + CLK_DEST_SYS_TBMAN = 36, ///< Select SYS_TBMAN as clock destination + CLK_DEST_SYS_TIMER = 37, ///< Select SYS_TIMER as clock destination + CLK_DEST_PERI_UART0 = 38, ///< Select PERI_UART0 as clock destination + CLK_DEST_SYS_UART0 = 39, ///< Select SYS_UART0 as clock destination + CLK_DEST_PERI_UART1 = 40, ///< Select PERI_UART1 as clock destination + CLK_DEST_SYS_UART1 = 41, ///< Select SYS_UART1 as clock destination + CLK_DEST_SYS_USBCTRL = 42, ///< Select SYS_USBCTRL as clock destination + CLK_DEST_USB_USBCTRL = 43, ///< Select USB_USBCTRL as clock destination + CLK_DEST_SYS_WATCHDOG = 44, ///< Select SYS_WATCHDOG as clock destination + CLK_DEST_SYS_XIP = 45, ///< Select SYS_XIP as clock destination + CLK_DEST_SYS_XOSC = 46, ///< Select SYS_XOSC as clock destination + NUM_CLOCK_DESTINATIONS +} clock_dest_num_t; + +/// \tag::clock_hw[] +typedef struct { + _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL + // Clock control, can be changed on-the-fly (except for auxsrc) + // 0x00100000 [20] NUDGE (0) An edge on this signal shifts the phase of the output by... + // 0x00030000 [17:16] PHASE (0x0) This delays the enable signal by up to 3 cycles of the... + // 0x00001000 [12] DC50 (0) Enables duty cycle correction for odd divisors + // 0x00000800 [11] ENABLE (0) Starts and stops the clock generator cleanly + // 0x00000400 [10] KILL (0) Asynchronously kills the clock generator + // 0x000001e0 [8:5] AUXSRC (0x0) Selects the auxiliary clock source, will glitch when switching + io_rw_32 ctrl; + + _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV + // Clock divisor, can be changed on-the-fly + // 0xffffff00 [31:8] INT (0x000001) Integer component of the divisor, 0 -> divide by 2^16 + // 0x000000ff [7:0] FRAC (0x00) Fractional component of the divisor + io_rw_32 div; + + _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED + // Indicates which SRC is currently selected by the glitchless mux (one-hot) + // 0xffffffff [31:0] CLK_GPOUT0_SELECTED (0x00000001) This slice does not have a glitchless mux (only the... + io_ro_32 selected; +} clock_hw_t; +/// \end::clock_hw[] + +typedef struct { + _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL + // 0x00010000 [16] CLEAR (0) For clearing the resus after the fault that triggered it... + // 0x00001000 [12] FRCE (0) Force a resus, for test purposes only + // 0x00000100 [8] ENABLE (0) Enable resus + // 0x000000ff [7:0] TIMEOUT (0xff) This is expressed as a number of clk_ref cycles + + io_rw_32 ctrl; + + _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS + // 0x00000001 [0] RESUSSED (0) Clock has been resuscitated, correct the error then send... + io_ro_32 status; +} clock_resus_hw_t; + +typedef struct { + _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ + // Reference clock frequency in kHz + // 0x000fffff [19:0] FC0_REF_KHZ (0x00000) + io_rw_32 ref_khz; + + _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ + // Minimum pass frequency in kHz + // 0x01ffffff [24:0] FC0_MIN_KHZ (0x0000000) + io_rw_32 min_khz; + + _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ + // Maximum pass frequency in kHz + // 0x01ffffff [24:0] FC0_MAX_KHZ (0x1ffffff) + io_rw_32 max_khz; + + _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY + // Delays the start of frequency counting to allow the mux to settle + + // 0x00000007 [2:0] FC0_DELAY (0x1) + io_rw_32 delay; + + _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL + // The test interval is 0 + // 0x0000000f [3:0] FC0_INTERVAL (0x8) + io_rw_32 interval; + + _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC + // Clock sent to frequency counter, set to 0 when not required + + // 0x000000ff [7:0] FC0_SRC (0x00) + io_rw_32 src; + + _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS + // Frequency counter status + // 0x10000000 [28] DIED (0) Test clock stopped during test + // 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_done=1 + // 0x00100000 [20] SLOW (0) Test clock slower than expected, only valid when status_done=1 + // 0x00010000 [16] FAIL (0) Test failed + // 0x00001000 [12] WAITING (0) Waiting for test clock to start + // 0x00000100 [8] RUNNING (0) Test running + // 0x00000010 [4] DONE (0) Test complete + // 0x00000001 [0] PASS (0) Test passed + io_ro_32 status; + + _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT + // Result of frequency measurement, only valid when status_done=1 + // 0x3fffffe0 [29:5] KHZ (0x0000000) + // 0x0000001f [4:0] FRAC (0x00) + io_ro_32 result; +} fc_hw_t; + +typedef struct { + clock_hw_t clk[10]; + + clock_resus_hw_t resus; + + fc_hw_t fc0; + + union { + struct { + _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 + // enable clock in wake mode + // 0x80000000 [31] CLK_SYS_SRAM3 (1) + // 0x40000000 [30] CLK_SYS_SRAM2 (1) + // 0x20000000 [29] CLK_SYS_SRAM1 (1) + // 0x10000000 [28] CLK_SYS_SRAM0 (1) + // 0x08000000 [27] CLK_SYS_SPI1 (1) + // 0x04000000 [26] CLK_PERI_SPI1 (1) + // 0x02000000 [25] CLK_SYS_SPI0 (1) + // 0x01000000 [24] CLK_PERI_SPI0 (1) + // 0x00800000 [23] CLK_SYS_SIOB (1) + // 0x00400000 [22] CLK_SYS_RTC (1) + // 0x00200000 [21] CLK_RTC_RTC (1) + // 0x00100000 [20] CLK_SYS_ROSC (1) + // 0x00080000 [19] CLK_SYS_ROM (1) + // 0x00040000 [18] CLK_SYS_RESETS (1) + // 0x00020000 [17] CLK_SYS_PWM (1) + // 0x00010000 [16] CLK_SYS_POWER (1) + // 0x00008000 [15] CLK_SYS_PLL_USB (1) + // 0x00004000 [14] CLK_SYS_PLL_SYS (1) + // 0x00002000 [13] CLK_SYS_PIO1 (1) + // 0x00001000 [12] CLK_SYS_PIO0 (1) + // 0x00000800 [11] CLK_SYS_PADS (1) + // 0x00000400 [10] CLK_SYS_LDO_POR (1) + // 0x00000200 [9] CLK_SYS_JTAG (1) + // 0x00000100 [8] CLK_SYS_IO (1) + // 0x00000080 [7] CLK_SYS_I2C1 (1) + // 0x00000040 [6] CLK_SYS_I2C0 (1) + // 0x00000020 [5] CLK_SYS_DMA (1) + // 0x00000010 [4] CLK_SYS_BUSFABRIC (1) + // 0x00000008 [3] CLK_SYS_BUSCTRL (1) + // 0x00000004 [2] CLK_SYS_ADC0 (1) + // 0x00000002 [1] CLK_ADC_ADC0 (1) + // 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (1) + io_rw_32 wake_en0; + + _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1 + // enable clock in wake mode + // 0x00004000 [14] CLK_SYS_XOSC (1) + // 0x00002000 [13] CLK_SYS_XIP (1) + // 0x00001000 [12] CLK_SYS_WATCHDOG (1) + // 0x00000800 [11] CLK_USB_USBCTRL (1) + // 0x00000400 [10] CLK_SYS_USBCTRL (1) + // 0x00000200 [9] CLK_SYS_UART1 (1) + // 0x00000100 [8] CLK_PERI_UART1 (1) + // 0x00000080 [7] CLK_SYS_UART0 (1) + // 0x00000040 [6] CLK_PERI_UART0 (1) + // 0x00000020 [5] CLK_SYS_TIMER (1) + // 0x00000010 [4] CLK_SYS_TBMAN (1) + // 0x00000008 [3] CLK_SYS_SYSINFO (1) + // 0x00000004 [2] CLK_SYS_SYSCFG (1) + // 0x00000002 [1] CLK_SYS_SRAM5 (1) + // 0x00000001 [0] CLK_SYS_SRAM4 (1) + io_rw_32 wake_en1; + }; + // (Description copied from array index 0 register CLOCKS_WAKE_EN0 applies similarly to other array indexes) + _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 + // enable clock in wake mode + // 0x80000000 [31] CLK_SYS_SRAM3 (1) + // 0x40000000 [30] CLK_SYS_SRAM2 (1) + // 0x20000000 [29] CLK_SYS_SRAM1 (1) + // 0x10000000 [28] CLK_SYS_SRAM0 (1) + // 0x08000000 [27] CLK_SYS_SPI1 (1) + // 0x04000000 [26] CLK_PERI_SPI1 (1) + // 0x02000000 [25] CLK_SYS_SPI0 (1) + // 0x01000000 [24] CLK_PERI_SPI0 (1) + // 0x00800000 [23] CLK_SYS_SIO (1) + // 0x00400000 [22] CLK_SYS_RTC (1) + // 0x00200000 [21] CLK_RTC_RTC (1) + // 0x00100000 [20] CLK_SYS_ROSC (1) + // 0x00080000 [19] CLK_SYS_ROM (1) + // 0x00040000 [18] CLK_SYS_RESETS (1) + // 0x00020000 [17] CLK_SYS_PWM (1) + // 0x00010000 [16] CLK_SYS_PSM (1) + // 0x00008000 [15] CLK_SYS_PLL_USB (1) + // 0x00004000 [14] CLK_SYS_PLL_SYS (1) + // 0x00002000 [13] CLK_SYS_PIO1 (1) + // 0x00001000 [12] CLK_SYS_PIO0 (1) + // 0x00000800 [11] CLK_SYS_PADS (1) + // 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (1) + // 0x00000200 [9] CLK_SYS_JTAG (1) + // 0x00000100 [8] CLK_SYS_IO (1) + // 0x00000080 [7] CLK_SYS_I2C1 (1) + // 0x00000040 [6] CLK_SYS_I2C0 (1) + // 0x00000020 [5] CLK_SYS_DMA (1) + // 0x00000010 [4] CLK_SYS_BUSFABRIC (1) + // 0x00000008 [3] CLK_SYS_BUSCTRL (1) + // 0x00000004 [2] CLK_SYS_ADC (1) + // 0x00000002 [1] CLK_ADC_ADC (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 wake_en[2]; + }; + + union { + struct { + _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 + // enable clock in sleep mode + // 0x80000000 [31] CLK_SYS_SRAM3 (1) + // 0x40000000 [30] CLK_SYS_SRAM2 (1) + // 0x20000000 [29] CLK_SYS_SRAM1 (1) + // 0x10000000 [28] CLK_SYS_SRAM0 (1) + // 0x08000000 [27] CLK_SYS_SPI1 (1) + // 0x04000000 [26] CLK_PERI_SPI1 (1) + // 0x02000000 [25] CLK_SYS_SPI0 (1) + // 0x01000000 [24] CLK_PERI_SPI0 (1) + // 0x00800000 [23] CLK_SYS_SIOB (1) + // 0x00400000 [22] CLK_SYS_RTC (1) + // 0x00200000 [21] CLK_RTC_RTC (1) + // 0x00100000 [20] CLK_SYS_ROSC (1) + // 0x00080000 [19] CLK_SYS_ROM (1) + // 0x00040000 [18] CLK_SYS_RESETS (1) + // 0x00020000 [17] CLK_SYS_PWM (1) + // 0x00010000 [16] CLK_SYS_POWER (1) + // 0x00008000 [15] CLK_SYS_PLL_USB (1) + // 0x00004000 [14] CLK_SYS_PLL_SYS (1) + // 0x00002000 [13] CLK_SYS_PIO1 (1) + // 0x00001000 [12] CLK_SYS_PIO0 (1) + // 0x00000800 [11] CLK_SYS_PADS (1) + // 0x00000400 [10] CLK_SYS_LDO_POR (1) + // 0x00000200 [9] CLK_SYS_JTAG (1) + // 0x00000100 [8] CLK_SYS_IO (1) + // 0x00000080 [7] CLK_SYS_I2C1 (1) + // 0x00000040 [6] CLK_SYS_I2C0 (1) + // 0x00000020 [5] CLK_SYS_DMA (1) + // 0x00000010 [4] CLK_SYS_BUSFABRIC (1) + // 0x00000008 [3] CLK_SYS_BUSCTRL (1) + // 0x00000004 [2] CLK_SYS_ADC0 (1) + // 0x00000002 [1] CLK_ADC_ADC0 (1) + // 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (1) + io_rw_32 sleep_en0; + + _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1 + // enable clock in sleep mode + // 0x00004000 [14] CLK_SYS_XOSC (1) + // 0x00002000 [13] CLK_SYS_XIP (1) + // 0x00001000 [12] CLK_SYS_WATCHDOG (1) + // 0x00000800 [11] CLK_USB_USBCTRL (1) + // 0x00000400 [10] CLK_SYS_USBCTRL (1) + // 0x00000200 [9] CLK_SYS_UART1 (1) + // 0x00000100 [8] CLK_PERI_UART1 (1) + // 0x00000080 [7] CLK_SYS_UART0 (1) + // 0x00000040 [6] CLK_PERI_UART0 (1) + // 0x00000020 [5] CLK_SYS_TIMER (1) + // 0x00000010 [4] CLK_SYS_TBMAN (1) + // 0x00000008 [3] CLK_SYS_SYSINFO (1) + // 0x00000004 [2] CLK_SYS_SYSCFG (1) + // 0x00000002 [1] CLK_SYS_SRAM5 (1) + // 0x00000001 [0] CLK_SYS_SRAM4 (1) + io_rw_32 sleep_en1; + }; + // (Description copied from array index 0 register CLOCKS_SLEEP_EN0 applies similarly to other array indexes) + _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 + // enable clock in sleep mode + // 0x80000000 [31] CLK_SYS_SRAM3 (1) + // 0x40000000 [30] CLK_SYS_SRAM2 (1) + // 0x20000000 [29] CLK_SYS_SRAM1 (1) + // 0x10000000 [28] CLK_SYS_SRAM0 (1) + // 0x08000000 [27] CLK_SYS_SPI1 (1) + // 0x04000000 [26] CLK_PERI_SPI1 (1) + // 0x02000000 [25] CLK_SYS_SPI0 (1) + // 0x01000000 [24] CLK_PERI_SPI0 (1) + // 0x00800000 [23] CLK_SYS_SIO (1) + // 0x00400000 [22] CLK_SYS_RTC (1) + // 0x00200000 [21] CLK_RTC_RTC (1) + // 0x00100000 [20] CLK_SYS_ROSC (1) + // 0x00080000 [19] CLK_SYS_ROM (1) + // 0x00040000 [18] CLK_SYS_RESETS (1) + // 0x00020000 [17] CLK_SYS_PWM (1) + // 0x00010000 [16] CLK_SYS_PSM (1) + // 0x00008000 [15] CLK_SYS_PLL_USB (1) + // 0x00004000 [14] CLK_SYS_PLL_SYS (1) + // 0x00002000 [13] CLK_SYS_PIO1 (1) + // 0x00001000 [12] CLK_SYS_PIO0 (1) + // 0x00000800 [11] CLK_SYS_PADS (1) + // 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (1) + // 0x00000200 [9] CLK_SYS_JTAG (1) + // 0x00000100 [8] CLK_SYS_IO (1) + // 0x00000080 [7] CLK_SYS_I2C1 (1) + // 0x00000040 [6] CLK_SYS_I2C0 (1) + // 0x00000020 [5] CLK_SYS_DMA (1) + // 0x00000010 [4] CLK_SYS_BUSFABRIC (1) + // 0x00000008 [3] CLK_SYS_BUSCTRL (1) + // 0x00000004 [2] CLK_SYS_ADC (1) + // 0x00000002 [1] CLK_ADC_ADC (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 sleep_en[2]; + }; + + union { + struct { + _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 + // indicates the state of the clock enable + // 0x80000000 [31] CLK_SYS_SRAM3 (0) + // 0x40000000 [30] CLK_SYS_SRAM2 (0) + // 0x20000000 [29] CLK_SYS_SRAM1 (0) + // 0x10000000 [28] CLK_SYS_SRAM0 (0) + // 0x08000000 [27] CLK_SYS_SPI1 (0) + // 0x04000000 [26] CLK_PERI_SPI1 (0) + // 0x02000000 [25] CLK_SYS_SPI0 (0) + // 0x01000000 [24] CLK_PERI_SPI0 (0) + // 0x00800000 [23] CLK_SYS_SIOB (0) + // 0x00400000 [22] CLK_SYS_RTC (0) + // 0x00200000 [21] CLK_RTC_RTC (0) + // 0x00100000 [20] CLK_SYS_ROSC (0) + // 0x00080000 [19] CLK_SYS_ROM (0) + // 0x00040000 [18] CLK_SYS_RESETS (0) + // 0x00020000 [17] CLK_SYS_PWM (0) + // 0x00010000 [16] CLK_SYS_POWER (0) + // 0x00008000 [15] CLK_SYS_PLL_USB (0) + // 0x00004000 [14] CLK_SYS_PLL_SYS (0) + // 0x00002000 [13] CLK_SYS_PIO1 (0) + // 0x00001000 [12] CLK_SYS_PIO0 (0) + // 0x00000800 [11] CLK_SYS_PADS (0) + // 0x00000400 [10] CLK_SYS_LDO_POR (0) + // 0x00000200 [9] CLK_SYS_JTAG (0) + // 0x00000100 [8] CLK_SYS_IO (0) + // 0x00000080 [7] CLK_SYS_I2C1 (0) + // 0x00000040 [6] CLK_SYS_I2C0 (0) + // 0x00000020 [5] CLK_SYS_DMA (0) + // 0x00000010 [4] CLK_SYS_BUSFABRIC (0) + // 0x00000008 [3] CLK_SYS_BUSCTRL (0) + // 0x00000004 [2] CLK_SYS_ADC0 (0) + // 0x00000002 [1] CLK_ADC_ADC0 (0) + // 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (0) + io_ro_32 enabled0; + + _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1 + // indicates the state of the clock enable + // 0x00004000 [14] CLK_SYS_XOSC (0) + // 0x00002000 [13] CLK_SYS_XIP (0) + // 0x00001000 [12] CLK_SYS_WATCHDOG (0) + // 0x00000800 [11] CLK_USB_USBCTRL (0) + // 0x00000400 [10] CLK_SYS_USBCTRL (0) + // 0x00000200 [9] CLK_SYS_UART1 (0) + // 0x00000100 [8] CLK_PERI_UART1 (0) + // 0x00000080 [7] CLK_SYS_UART0 (0) + // 0x00000040 [6] CLK_PERI_UART0 (0) + // 0x00000020 [5] CLK_SYS_TIMER (0) + // 0x00000010 [4] CLK_SYS_TBMAN (0) + // 0x00000008 [3] CLK_SYS_SYSINFO (0) + // 0x00000004 [2] CLK_SYS_SYSCFG (0) + // 0x00000002 [1] CLK_SYS_SRAM5 (0) + // 0x00000001 [0] CLK_SYS_SRAM4 (0) + io_ro_32 enabled1; + }; + // (Description copied from array index 0 register CLOCKS_ENABLED0 applies similarly to other array indexes) + _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 + // indicates the state of the clock enable + // 0x80000000 [31] CLK_SYS_SRAM3 (0) + // 0x40000000 [30] CLK_SYS_SRAM2 (0) + // 0x20000000 [29] CLK_SYS_SRAM1 (0) + // 0x10000000 [28] CLK_SYS_SRAM0 (0) + // 0x08000000 [27] CLK_SYS_SPI1 (0) + // 0x04000000 [26] CLK_PERI_SPI1 (0) + // 0x02000000 [25] CLK_SYS_SPI0 (0) + // 0x01000000 [24] CLK_PERI_SPI0 (0) + // 0x00800000 [23] CLK_SYS_SIO (0) + // 0x00400000 [22] CLK_SYS_RTC (0) + // 0x00200000 [21] CLK_RTC_RTC (0) + // 0x00100000 [20] CLK_SYS_ROSC (0) + // 0x00080000 [19] CLK_SYS_ROM (0) + // 0x00040000 [18] CLK_SYS_RESETS (0) + // 0x00020000 [17] CLK_SYS_PWM (0) + // 0x00010000 [16] CLK_SYS_PSM (0) + // 0x00008000 [15] CLK_SYS_PLL_USB (0) + // 0x00004000 [14] CLK_SYS_PLL_SYS (0) + // 0x00002000 [13] CLK_SYS_PIO1 (0) + // 0x00001000 [12] CLK_SYS_PIO0 (0) + // 0x00000800 [11] CLK_SYS_PADS (0) + // 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (0) + // 0x00000200 [9] CLK_SYS_JTAG (0) + // 0x00000100 [8] CLK_SYS_IO (0) + // 0x00000080 [7] CLK_SYS_I2C1 (0) + // 0x00000040 [6] CLK_SYS_I2C0 (0) + // 0x00000020 [5] CLK_SYS_DMA (0) + // 0x00000010 [4] CLK_SYS_BUSFABRIC (0) + // 0x00000008 [3] CLK_SYS_BUSCTRL (0) + // 0x00000004 [2] CLK_SYS_ADC (0) + // 0x00000002 [1] CLK_ADC_ADC (0) + // 0x00000001 [0] CLK_SYS_CLOCKS (0) + io_ro_32 enabled[2]; + }; + + _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR + // Raw Interrupts + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_ro_32 intr; + + _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE + // Interrupt Enable + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_rw_32 inte; + + _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF + // Interrupt Force + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_rw_32 intf; + + _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_ro_32 ints; +} clocks_hw_t; + +#define clocks_hw ((clocks_hw_t *)CLOCKS_BASE) +static_assert(sizeof (clocks_hw_t) == 0x00c8, ""); + +#endif // _HARDWARE_STRUCTS_CLOCKS_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/dma.h b/lib/pico-sdk/rp2040/hardware/structs/dma.h new file mode 100644 index 000000000000..bc83060f7b9d --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/dma.h @@ -0,0 +1,239 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_DMA_H +#define _HARDWARE_STRUCTS_DMA_H + +/** + * \file rp2040/dma.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/dma.h" +#include "hardware/structs/dma_debug.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR + // DMA Channel 0 Read Address pointer + // 0xffffffff [31:0] CH0_READ_ADDR (0x00000000) This register updates automatically each time a read completes + io_rw_32 read_addr; + + _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR + // DMA Channel 0 Write Address pointer + // 0xffffffff [31:0] CH0_WRITE_ADDR (0x00000000) This register updates automatically each time a write completes + io_rw_32 write_addr; + + _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT + // DMA Channel 0 Transfer Count + // 0xffffffff [31:0] CH0_TRANS_COUNT (0x00000000) Program the number of bus transfers a channel will... + io_rw_32 transfer_count; + + _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG + // DMA Channel 0 Control and Status + // 0x80000000 [31] AHB_ERROR (0) Logical OR of the READ_ERROR and WRITE_ERROR flags + // 0x40000000 [30] READ_ERROR (0) If 1, the channel received a read bus error + // 0x20000000 [29] WRITE_ERROR (0) If 1, the channel received a write bus error + // 0x01000000 [24] BUSY (0) This flag goes high when the channel starts a new... + // 0x00800000 [23] SNIFF_EN (0) If 1, this channel's data transfers are visible to the... + // 0x00400000 [22] BSWAP (0) Apply byte-swap transformation to DMA data + // 0x00200000 [21] IRQ_QUIET (0) In QUIET mode, the channel does not generate IRQs at the... + // 0x001f8000 [20:15] TREQ_SEL (0x00) Select a Transfer Request signal + // 0x00007800 [14:11] CHAIN_TO (0x0) When this channel completes, it will trigger the channel... + // 0x00000400 [10] RING_SEL (0) Select whether RING_SIZE applies to read or write addresses + // 0x000003c0 [9:6] RING_SIZE (0x0) Size of address wrap region + // 0x00000020 [5] INCR_WRITE (0) If 1, the write address increments with each transfer + // 0x00000010 [4] INCR_READ (0) If 1, the read address increments with each transfer + // 0x0000000c [3:2] DATA_SIZE (0x0) Set the size of each bus transfer (byte/halfword/word) + // 0x00000002 [1] HIGH_PRIORITY (0) HIGH_PRIORITY gives a channel preferential treatment in... + // 0x00000001 [0] EN (0) DMA Channel Enable + io_rw_32 ctrl_trig; + + _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL + // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL1_CTRL (-) + io_rw_32 al1_ctrl; + + _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR + // Alias for channel 0 READ_ADDR register + // 0xffffffff [31:0] CH0_AL1_READ_ADDR (-) + io_rw_32 al1_read_addr; + + _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR + // Alias for channel 0 WRITE_ADDR register + // 0xffffffff [31:0] CH0_AL1_WRITE_ADDR (-) + io_rw_32 al1_write_addr; + + _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG + // Alias for channel 0 TRANS_COUNT register + + // 0xffffffff [31:0] CH0_AL1_TRANS_COUNT_TRIG (-) + io_rw_32 al1_transfer_count_trig; + + _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL + // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL2_CTRL (-) + io_rw_32 al2_ctrl; + + _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT + // Alias for channel 0 TRANS_COUNT register + // 0xffffffff [31:0] CH0_AL2_TRANS_COUNT (-) + io_rw_32 al2_transfer_count; + + _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR + // Alias for channel 0 READ_ADDR register + // 0xffffffff [31:0] CH0_AL2_READ_ADDR (-) + io_rw_32 al2_read_addr; + + _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG + // Alias for channel 0 WRITE_ADDR register + + // 0xffffffff [31:0] CH0_AL2_WRITE_ADDR_TRIG (-) + io_rw_32 al2_write_addr_trig; + + _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL + // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL3_CTRL (-) + io_rw_32 al3_ctrl; + + _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR + // Alias for channel 0 WRITE_ADDR register + // 0xffffffff [31:0] CH0_AL3_WRITE_ADDR (-) + io_rw_32 al3_write_addr; + + _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT + // Alias for channel 0 TRANS_COUNT register + // 0xffffffff [31:0] CH0_AL3_TRANS_COUNT (-) + io_rw_32 al3_transfer_count; + + _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG + // Alias for channel 0 READ_ADDR register + + // 0xffffffff [31:0] CH0_AL3_READ_ADDR_TRIG (-) + io_rw_32 al3_read_addr_trig; +} dma_channel_hw_t; + +typedef struct { + _REG_(DMA_INTR_OFFSET) // DMA_INTR + // Interrupt Status (raw) + // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 + io_rw_32 intr; + + _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 + // Interrupt Enables for IRQ 0 + // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 + io_rw_32 inte; + + _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 + // Force Interrupts + // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0 + io_rw_32 intf; + + _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 + // Interrupt Status for IRQ 0 + // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints; +} dma_irq_ctrl_hw_t; + +typedef struct { + dma_channel_hw_t ch[12]; + + uint32_t _pad0[64]; + + union { + struct { + _REG_(DMA_INTR_OFFSET) // DMA_INTR + // Interrupt Status (raw) + // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 + io_rw_32 intr; + + _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 + // Interrupt Enables for IRQ 0 + // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 + io_rw_32 inte0; + + _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 + // Force Interrupts + // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0 + io_rw_32 intf0; + + _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 + // Interrupt Status for IRQ 0 + // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints0; + + uint32_t __pad0; + + _REG_(DMA_INTE1_OFFSET) // DMA_INTE1 + // Interrupt Enables for IRQ 1 + // 0x0000ffff [15:0] INTE1 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 1 + io_rw_32 inte1; + + _REG_(DMA_INTF1_OFFSET) // DMA_INTF1 + // Force Interrupts for IRQ 1 + // 0x0000ffff [15:0] INTF1 (0x0000) Write 1s to force the corresponding bits in INTF1 + io_rw_32 intf1; + + _REG_(DMA_INTS1_OFFSET) // DMA_INTS1 + // Interrupt Status (masked) for IRQ 1 + // 0x0000ffff [15:0] INTS1 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints1; + }; + dma_irq_ctrl_hw_t irq_ctrl[2]; + }; + + // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes) + _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0 + // Pacing (X/Y) Fractional Timer + + // 0xffff0000 [31:16] X (0x0000) Pacing Timer Dividend + // 0x0000ffff [15:0] Y (0x0000) Pacing Timer Divisor + io_rw_32 timer[4]; + + _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER + // Trigger one or more channels simultaneously + // 0x0000ffff [15:0] MULTI_CHAN_TRIGGER (0x0000) Each bit in this register corresponds to a DMA channel + io_wo_32 multi_channel_trigger; + + _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL + // Sniffer Control + // 0x00000800 [11] OUT_INV (0) If set, the result appears inverted (bitwise complement)... + // 0x00000400 [10] OUT_REV (0) If set, the result appears bit-reversed when read + // 0x00000200 [9] BSWAP (0) Locally perform a byte reverse on the sniffed data,... + // 0x000001e0 [8:5] CALC (0x0) + // 0x0000001e [4:1] DMACH (0x0) DMA channel for Sniffer to observe + // 0x00000001 [0] EN (0) Enable sniffer + io_rw_32 sniff_ctrl; + + _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA + // Data accumulator for sniff hardware + // 0xffffffff [31:0] SNIFF_DATA (0x00000000) Write an initial seed value here before starting a DMA... + io_rw_32 sniff_data; + + uint32_t _pad1; + + _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS + // Debug RAF, WAF, TDF levels + // 0x00ff0000 [23:16] RAF_LVL (0x00) Current Read-Address-FIFO fill level + // 0x0000ff00 [15:8] WAF_LVL (0x00) Current Write-Address-FIFO fill level + // 0x000000ff [7:0] TDF_LVL (0x00) Current Transfer-Data-FIFO fill level + io_ro_32 fifo_levels; + + _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT + // Abort an in-progress transfer sequence on one or more channels + // 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel + io_wo_32 abort; +} dma_hw_t; + +#define dma_hw ((dma_hw_t *)DMA_BASE) +static_assert(sizeof (dma_hw_t) == 0x0448, ""); + +#endif // _HARDWARE_STRUCTS_DMA_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/dma_debug.h b/lib/pico-sdk/rp2040/hardware/structs/dma_debug.h new file mode 100644 index 000000000000..239b8cae8602 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/dma_debug.h @@ -0,0 +1,47 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_DMA_DEBUG_H +#define _HARDWARE_STRUCTS_DMA_DEBUG_H + +/** + * \file rp2040/dma_debug.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/dma.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(DMA_CH0_DBG_CTDREQ_OFFSET) // DMA_CH0_DBG_CTDREQ + // Read: get channel DREQ counter (i + // 0x0000003f [5:0] CH0_DBG_CTDREQ (0x00) + io_rw_32 dbg_ctdreq; + + _REG_(DMA_CH0_DBG_TCR_OFFSET) // DMA_CH0_DBG_TCR + // Read to get channel TRANS_COUNT reload value, i + // 0xffffffff [31:0] CH0_DBG_TCR (0x00000000) + io_ro_32 dbg_tcr; + + uint32_t _pad0[14]; +} dma_debug_channel_hw_t; + +typedef struct { + dma_debug_channel_hw_t ch[12]; +} dma_debug_hw_t; + +#define dma_debug_hw ((dma_debug_hw_t *)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) + +#endif // _HARDWARE_STRUCTS_DMA_DEBUG_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/i2c.h b/lib/pico-sdk/rp2040/hardware/structs/i2c.h new file mode 100644 index 000000000000..2ff0997995e7 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/i2c.h @@ -0,0 +1,338 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_I2C_H +#define _HARDWARE_STRUCTS_I2C_H + +/** + * \file rp2040/i2c.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/i2c.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON + // I2C Control Register + // 0x00000400 [10] STOP_DET_IF_MASTER_ACTIVE (0) Master issues the STOP_DET interrupt irrespective of... + // 0x00000200 [9] RX_FIFO_FULL_HLD_CTRL (0) This bit controls whether DW_apb_i2c should hold the bus... + // 0x00000100 [8] TX_EMPTY_CTRL (0) This bit controls the generation of the TX_EMPTY... + // 0x00000080 [7] STOP_DET_IFADDRESSED (0) In slave mode: - 1'b1: issues the STOP_DET interrupt... + // 0x00000040 [6] IC_SLAVE_DISABLE (1) This bit controls whether I2C has its slave disabled,... + // 0x00000020 [5] IC_RESTART_EN (1) Determines whether RESTART conditions may be sent when... + // 0x00000010 [4] IC_10BITADDR_MASTER (0) Controls whether the DW_apb_i2c starts its transfers in... + // 0x00000008 [3] IC_10BITADDR_SLAVE (0) When acting as a slave, this bit controls whether the... + // 0x00000006 [2:1] SPEED (0x2) These bits control at which speed the DW_apb_i2c... + // 0x00000001 [0] MASTER_MODE (1) This bit controls whether the DW_apb_i2c master is enabled + io_rw_32 con; + + _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR + // I2C Target Address Register + // 0x00000800 [11] SPECIAL (0) This bit indicates whether software performs a Device-ID... + // 0x00000400 [10] GC_OR_START (0) If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is... + // 0x000003ff [9:0] IC_TAR (0x055) This is the target address for any master transaction + io_rw_32 tar; + + _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR + // I2C Slave Address Register + // 0x000003ff [9:0] IC_SAR (0x055) The IC_SAR holds the slave address when the I2C is... + io_rw_32 sar; + + uint32_t _pad0; + + _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD + // I2C Rx/Tx Data Buffer and Command Register + // 0x00000800 [11] FIRST_DATA_BYTE (0) Indicates the first data byte received after the address... + // 0x00000400 [10] RESTART (0) This bit controls whether a RESTART is issued before the... + // 0x00000200 [9] STOP (0) This bit controls whether a STOP is issued after the... + // 0x00000100 [8] CMD (0) This bit controls whether a read or a write is performed + // 0x000000ff [7:0] DAT (0x00) This register contains the data to be transmitted or... + io_rw_32 data_cmd; + + _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT + // Standard Speed I2C Clock SCL High Count Register + // 0x0000ffff [15:0] IC_SS_SCL_HCNT (0x0028) This register must be set before any I2C bus transaction... + io_rw_32 ss_scl_hcnt; + + _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT + // Standard Speed I2C Clock SCL Low Count Register + // 0x0000ffff [15:0] IC_SS_SCL_LCNT (0x002f) This register must be set before any I2C bus transaction... + io_rw_32 ss_scl_lcnt; + + _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT + // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + // 0x0000ffff [15:0] IC_FS_SCL_HCNT (0x0006) This register must be set before any I2C bus transaction... + io_rw_32 fs_scl_hcnt; + + _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT + // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + // 0x0000ffff [15:0] IC_FS_SCL_LCNT (0x000d) This register must be set before any I2C bus transaction... + io_rw_32 fs_scl_lcnt; + + uint32_t _pad1[2]; + + _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT + // I2C Interrupt Status Register + // 0x00001000 [12] R_RESTART_DET (0) See IC_RAW_INTR_STAT for a detailed description of... + // 0x00000800 [11] R_GEN_CALL (0) See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit + // 0x00000400 [10] R_START_DET (0) See IC_RAW_INTR_STAT for a detailed description of... + // 0x00000200 [9] R_STOP_DET (0) See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit + // 0x00000100 [8] R_ACTIVITY (0) See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit + // 0x00000080 [7] R_RX_DONE (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit + // 0x00000040 [6] R_TX_ABRT (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit + // 0x00000020 [5] R_RD_REQ (0) See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit + // 0x00000010 [4] R_TX_EMPTY (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit + // 0x00000008 [3] R_TX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit + // 0x00000004 [2] R_RX_FULL (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit + // 0x00000002 [1] R_RX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit + // 0x00000001 [0] R_RX_UNDER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit + io_ro_32 intr_stat; + + _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK + // I2C Interrupt Mask Register + // 0x00001000 [12] M_RESTART_DET (0) This bit masks the R_RESTART_DET interrupt in... + // 0x00000800 [11] M_GEN_CALL (1) This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register + // 0x00000400 [10] M_START_DET (0) This bit masks the R_START_DET interrupt in IC_INTR_STAT register + // 0x00000200 [9] M_STOP_DET (0) This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register + // 0x00000100 [8] M_ACTIVITY (0) This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register + // 0x00000080 [7] M_RX_DONE (1) This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register + // 0x00000040 [6] M_TX_ABRT (1) This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register + // 0x00000020 [5] M_RD_REQ (1) This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register + // 0x00000010 [4] M_TX_EMPTY (1) This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register + // 0x00000008 [3] M_TX_OVER (1) This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register + // 0x00000004 [2] M_RX_FULL (1) This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register + // 0x00000002 [1] M_RX_OVER (1) This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register + // 0x00000001 [0] M_RX_UNDER (1) This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register + io_rw_32 intr_mask; + + _REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT + // I2C Raw Interrupt Status Register + // 0x00001000 [12] RESTART_DET (0) Indicates whether a RESTART condition has occurred on... + // 0x00000800 [11] GEN_CALL (0) Set only when a General Call address is received and it... + // 0x00000400 [10] START_DET (0) Indicates whether a START or RESTART condition has... + // 0x00000200 [9] STOP_DET (0) Indicates whether a STOP condition has occurred on the... + // 0x00000100 [8] ACTIVITY (0) This bit captures DW_apb_i2c activity and stays set... + // 0x00000080 [7] RX_DONE (0) When the DW_apb_i2c is acting as a slave-transmitter,... + // 0x00000040 [6] TX_ABRT (0) This bit indicates if DW_apb_i2c, as an I2C transmitter,... + // 0x00000020 [5] RD_REQ (0) This bit is set to 1 when DW_apb_i2c is acting as a... + // 0x00000010 [4] TX_EMPTY (0) The behavior of the TX_EMPTY interrupt status differs... + // 0x00000008 [3] TX_OVER (0) Set during transmit if the transmit buffer is filled to... + // 0x00000004 [2] RX_FULL (0) Set when the receive buffer reaches or goes above the... + // 0x00000002 [1] RX_OVER (0) Set if the receive buffer is completely filled to... + // 0x00000001 [0] RX_UNDER (0) Set if the processor attempts to read the receive buffer... + io_ro_32 raw_intr_stat; + + _REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL + // I2C Receive FIFO Threshold Register + // 0x000000ff [7:0] RX_TL (0x00) Receive FIFO Threshold Level + io_rw_32 rx_tl; + + _REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL + // I2C Transmit FIFO Threshold Register + // 0x000000ff [7:0] TX_TL (0x00) Transmit FIFO Threshold Level + io_rw_32 tx_tl; + + _REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR + // Clear Combined and Individual Interrupt Register + // 0x00000001 [0] CLR_INTR (0) Read this register to clear the combined interrupt, all... + io_ro_32 clr_intr; + + _REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER + // Clear RX_UNDER Interrupt Register + // 0x00000001 [0] CLR_RX_UNDER (0) Read this register to clear the RX_UNDER interrupt (bit... + io_ro_32 clr_rx_under; + + _REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER + // Clear RX_OVER Interrupt Register + // 0x00000001 [0] CLR_RX_OVER (0) Read this register to clear the RX_OVER interrupt (bit... + io_ro_32 clr_rx_over; + + _REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER + // Clear TX_OVER Interrupt Register + // 0x00000001 [0] CLR_TX_OVER (0) Read this register to clear the TX_OVER interrupt (bit... + io_ro_32 clr_tx_over; + + _REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ + // Clear RD_REQ Interrupt Register + // 0x00000001 [0] CLR_RD_REQ (0) Read this register to clear the RD_REQ interrupt (bit 5)... + io_ro_32 clr_rd_req; + + _REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT + // Clear TX_ABRT Interrupt Register + // 0x00000001 [0] CLR_TX_ABRT (0) Read this register to clear the TX_ABRT interrupt (bit... + io_ro_32 clr_tx_abrt; + + _REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE + // Clear RX_DONE Interrupt Register + // 0x00000001 [0] CLR_RX_DONE (0) Read this register to clear the RX_DONE interrupt (bit... + io_ro_32 clr_rx_done; + + _REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY + // Clear ACTIVITY Interrupt Register + // 0x00000001 [0] CLR_ACTIVITY (0) Reading this register clears the ACTIVITY interrupt if... + io_ro_32 clr_activity; + + _REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET + // Clear STOP_DET Interrupt Register + // 0x00000001 [0] CLR_STOP_DET (0) Read this register to clear the STOP_DET interrupt (bit... + io_ro_32 clr_stop_det; + + _REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET + // Clear START_DET Interrupt Register + // 0x00000001 [0] CLR_START_DET (0) Read this register to clear the START_DET interrupt (bit... + io_ro_32 clr_start_det; + + _REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL + // Clear GEN_CALL Interrupt Register + // 0x00000001 [0] CLR_GEN_CALL (0) Read this register to clear the GEN_CALL interrupt (bit... + io_ro_32 clr_gen_call; + + _REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE + // I2C ENABLE Register + // 0x00000004 [2] TX_CMD_BLOCK (0) In Master mode: - 1'b1: Blocks the transmission of data... + // 0x00000002 [1] ABORT (0) When set, the controller initiates the transfer abort + // 0x00000001 [0] ENABLE (0) Controls whether the DW_apb_i2c is enabled + io_rw_32 enable; + + _REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS + // I2C STATUS Register + // 0x00000040 [6] SLV_ACTIVITY (0) Slave FSM Activity Status + // 0x00000020 [5] MST_ACTIVITY (0) Master FSM Activity Status + // 0x00000010 [4] RFF (0) Receive FIFO Completely Full + // 0x00000008 [3] RFNE (0) Receive FIFO Not Empty + // 0x00000004 [2] TFE (1) Transmit FIFO Completely Empty + // 0x00000002 [1] TFNF (1) Transmit FIFO Not Full + // 0x00000001 [0] ACTIVITY (0) I2C Activity Status + io_ro_32 status; + + _REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR + // I2C Transmit FIFO Level Register + // 0x0000001f [4:0] TXFLR (0x00) Transmit FIFO Level + io_ro_32 txflr; + + _REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR + // I2C Receive FIFO Level Register + // 0x0000001f [4:0] RXFLR (0x00) Receive FIFO Level + io_ro_32 rxflr; + + _REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD + // I2C SDA Hold Time Length Register + // 0x00ff0000 [23:16] IC_SDA_RX_HOLD (0x00) Sets the required SDA hold time in units of ic_clk... + // 0x0000ffff [15:0] IC_SDA_TX_HOLD (0x0001) Sets the required SDA hold time in units of ic_clk... + io_rw_32 sda_hold; + + _REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE + // I2C Transmit Abort Source Register + // 0xff800000 [31:23] TX_FLUSH_CNT (0x000) This field indicates the number of Tx FIFO Data Commands... + // 0x00010000 [16] ABRT_USER_ABRT (0) This is a master-mode-only bit + // 0x00008000 [15] ABRT_SLVRD_INTX (0) 1: When the processor side responds to a slave mode... + // 0x00004000 [14] ABRT_SLV_ARBLOST (0) This field indicates that a Slave has lost the bus while... + // 0x00002000 [13] ABRT_SLVFLUSH_TXFIFO (0) This field specifies that the Slave has received a read... + // 0x00001000 [12] ARB_LOST (0) This field specifies that the Master has lost... + // 0x00000800 [11] ABRT_MASTER_DIS (0) This field indicates that the User tries to initiate a... + // 0x00000400 [10] ABRT_10B_RD_NORSTRT (0) This field indicates that the restart is disabled... + // 0x00000200 [9] ABRT_SBYTE_NORSTRT (0) To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT... + // 0x00000100 [8] ABRT_HS_NORSTRT (0) This field indicates that the restart is disabled... + // 0x00000080 [7] ABRT_SBYTE_ACKDET (0) This field indicates that the Master has sent a START... + // 0x00000040 [6] ABRT_HS_ACKDET (0) This field indicates that the Master is in High Speed... + // 0x00000020 [5] ABRT_GCALL_READ (0) This field indicates that DW_apb_i2c in the master mode... + // 0x00000010 [4] ABRT_GCALL_NOACK (0) This field indicates that DW_apb_i2c in master mode has... + // 0x00000008 [3] ABRT_TXDATA_NOACK (0) This field indicates the master-mode only bit + // 0x00000004 [2] ABRT_10ADDR2_NOACK (0) This field indicates that the Master is in 10-bit... + // 0x00000002 [1] ABRT_10ADDR1_NOACK (0) This field indicates that the Master is in 10-bit... + // 0x00000001 [0] ABRT_7B_ADDR_NOACK (0) This field indicates that the Master is in 7-bit... + io_ro_32 tx_abrt_source; + + _REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY + // Generate Slave Data NACK Register + // 0x00000001 [0] NACK (0) Generate NACK + io_rw_32 slv_data_nack_only; + + _REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR + // DMA Control Register + // 0x00000002 [1] TDMAE (0) Transmit DMA Enable + // 0x00000001 [0] RDMAE (0) Receive DMA Enable + io_rw_32 dma_cr; + + _REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR + // DMA Transmit Data Level Register + // 0x0000000f [3:0] DMATDL (0x0) Transmit Data Level + io_rw_32 dma_tdlr; + + _REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR + // DMA Transmit Data Level Register + // 0x0000000f [3:0] DMARDL (0x0) Receive Data Level + io_rw_32 dma_rdlr; + + _REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP + // I2C SDA Setup Register + // 0x000000ff [7:0] SDA_SETUP (0x64) SDA Setup + io_rw_32 sda_setup; + + _REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL + // I2C ACK General Call Register + // 0x00000001 [0] ACK_GEN_CALL (1) ACK General Call + io_rw_32 ack_general_call; + + _REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS + // I2C Enable Status Register + // 0x00000004 [2] SLV_RX_DATA_LOST (0) Slave Received Data Lost + // 0x00000002 [1] SLV_DISABLED_WHILE_BUSY (0) Slave Disabled While Busy (Transmit, Receive) + // 0x00000001 [0] IC_EN (0) ic_en Status + io_ro_32 enable_status; + + _REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN + // I2C SS, FS or FM+ spike suppression limit + // 0x000000ff [7:0] IC_FS_SPKLEN (0x07) This register must be set before any I2C bus transaction... + io_rw_32 fs_spklen; + + uint32_t _pad2; + + _REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET + // Clear RESTART_DET Interrupt Register + // 0x00000001 [0] CLR_RESTART_DET (0) Read this register to clear the RESTART_DET interrupt... + io_ro_32 clr_restart_det; + + uint32_t _pad3[18]; + + _REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1 + // Component Parameter Register 1 + // 0x00ff0000 [23:16] TX_BUFFER_DEPTH (0x00) TX Buffer Depth = 16 + // 0x0000ff00 [15:8] RX_BUFFER_DEPTH (0x00) RX Buffer Depth = 16 + // 0x00000080 [7] ADD_ENCODED_PARAMS (0) Encoded parameters not visible + // 0x00000040 [6] HAS_DMA (0) DMA handshaking signals are enabled + // 0x00000020 [5] INTR_IO (0) COMBINED Interrupt outputs + // 0x00000010 [4] HC_COUNT_VALUES (0) Programmable count values for each mode + // 0x0000000c [3:2] MAX_SPEED_MODE (0x0) MAX SPEED MODE = FAST MODE + // 0x00000003 [1:0] APB_DATA_WIDTH (0x0) APB data bus width is 32 bits + io_ro_32 comp_param_1; + + _REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION + // I2C Component Version Register + // 0xffffffff [31:0] IC_COMP_VERSION (0x3230312a) + io_ro_32 comp_version; + + _REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE + // I2C Component Type Register + // 0xffffffff [31:0] IC_COMP_TYPE (0x44570140) Designware Component Type number = 0x44_57_01_40 + io_ro_32 comp_type; +} i2c_hw_t; + +#define i2c0_hw ((i2c_hw_t *)I2C0_BASE) +#define i2c1_hw ((i2c_hw_t *)I2C1_BASE) +static_assert(sizeof (i2c_hw_t) == 0x0100, ""); + +#endif // _HARDWARE_STRUCTS_I2C_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/interp.h b/lib/pico-sdk/rp2040/hardware/structs/interp.h new file mode 100644 index 000000000000..abc06843a3fb --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/interp.h @@ -0,0 +1,86 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_INTERP_H +#define _HARDWARE_STRUCTS_INTERP_H + +/** + * \file rp2040/interp.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0 + // Read/write access to accumulator 0 + // 0xffffffff [31:0] INTERP0_ACCUM0 (0x00000000) + io_rw_32 accum[2]; + + // (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0 + // Read/write access to BASE0 register + // 0xffffffff [31:0] INTERP0_BASE0 (0x00000000) + io_rw_32 base[3]; + + // (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0 + // Read LANE0 result, and simultaneously write lane results to both accumulators (POP) + // 0xffffffff [31:0] INTERP0_POP_LANE0 (0x00000000) + io_ro_32 pop[3]; + + // (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0 + // Read LANE0 result, without altering any internal state (PEEK) + // 0xffffffff [31:0] INTERP0_PEEK_LANE0 (0x00000000) + io_ro_32 peek[3]; + + // (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0 + // Control register for lane 0 + // 0x02000000 [25] OVERF (0) Set if either OVERF0 or OVERF1 is set + // 0x01000000 [24] OVERF1 (0) Indicates if any masked-off MSBs in ACCUM1 are set + // 0x00800000 [23] OVERF0 (0) Indicates if any masked-off MSBs in ACCUM0 are set + // 0x00200000 [21] BLEND (0) Only present on INTERP0 on each core + // 0x00180000 [20:19] FORCE_MSB (0x0) ORed into bits 29:28 of the lane result presented to the... + // 0x00040000 [18] ADD_RAW (0) If 1, mask + shift is bypassed for LANE0 result + // 0x00020000 [17] CROSS_RESULT (0) If 1, feed the opposite lane's result into this lane's... + // 0x00010000 [16] CROSS_INPUT (0) If 1, feed the opposite lane's accumulator into this... + // 0x00008000 [15] SIGNED (0) If SIGNED is set, the shifted and masked accumulator... + // 0x00007c00 [14:10] MASK_MSB (0x00) The most-significant bit allowed to pass by the mask... + // 0x000003e0 [9:5] MASK_LSB (0x00) The least-significant bit allowed to pass by the mask (inclusive) + // 0x0000001f [4:0] SHIFT (0x00) Logical right-shift applied to accumulator before masking + io_rw_32 ctrl[2]; + + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes) + _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD + // Values written here are atomically added to ACCUM0 + // 0x00ffffff [23:0] INTERP0_ACCUM0_ADD (0x000000) + io_rw_32 add_raw[2]; + + _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0 + // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + // 0xffffffff [31:0] INTERP0_BASE_1AND0 (0x00000000) + io_wo_32 base01; +} interp_hw_t; + +#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)) +static_assert(sizeof (interp_hw_t) == 0x0040, ""); +#define interp0_hw (&interp_hw_array[0]) +#define interp1_hw (&interp_hw_array[1]) + +#endif // _HARDWARE_STRUCTS_INTERP_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/io_bank0.h b/lib/pico-sdk/rp2040/hardware/structs/io_bank0.h new file mode 100644 index 000000000000..6c09bb043170 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/io_bank0.h @@ -0,0 +1,236 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_IO_BANK0_H +#define _HARDWARE_STRUCTS_IO_BANK0_H + +/** + * \file rp2040/io_bank0.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/io_bank0.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** + * \brief GPIO pin function selectors on RP2040 (used as typedef \ref gpio_function_t) + * \ingroup hardware_gpio + */ +typedef enum gpio_function_rp2040 { + GPIO_FUNC_XIP = 0, ///< Select XIP as GPIO pin function + GPIO_FUNC_SPI = 1, ///< Select SPI as GPIO pin function + GPIO_FUNC_UART = 2, ///< Select UART as GPIO pin function + GPIO_FUNC_I2C = 3, ///< Select I2C as GPIO pin function + GPIO_FUNC_PWM = 4, ///< Select PWM as GPIO pin function + GPIO_FUNC_SIO = 5, ///< Select SIO as GPIO pin function + GPIO_FUNC_PIO0 = 6, ///< Select PIO0 as GPIO pin function + GPIO_FUNC_PIO1 = 7, ///< Select PIO1 as GPIO pin function + GPIO_FUNC_GPCK = 8, ///< Select GPCK as GPIO pin function + GPIO_FUNC_USB = 9, ///< Select USB as GPIO pin function + GPIO_FUNC_NULL = 0x1f, ///< Select NULL as GPIO pin function +} gpio_function_t; + +typedef struct { + _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS + // GPIO status + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x01000000 [24] IRQFROMPAD (0) interrupt from pad before override is applied + // 0x00080000 [19] INTOPERI (0) input signal to peripheral, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before override is applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00001000 [12] OEFROMPERI (0) output enable from selected peripheral, before register... + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + // 0x00000100 [8] OUTFROMPERI (0) output signal from selected peripheral, before register... + io_ro_32 status; + + _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL + // GPIO control including function select and overrides + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x00003000 [13:12] OEOVER (0x0) + // 0x00000300 [9:8] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 ctrl; +} io_bank0_status_ctrl_hw_t; + +typedef struct { + // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0 + // Interrupt Enable for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 inte[4]; + + // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0 + // Interrupt Force for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 intf[4]; + + // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0 + // Interrupt status after masking & forcing for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_ro_32 ints[4]; +} io_bank0_irq_ctrl_hw_t; + +/// \tag::io_bank0_hw[] +typedef struct { + io_bank0_status_ctrl_hw_t io[30]; + + // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes) + _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0 + // Raw Interrupts + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 intr[4]; + + union { + struct { + io_bank0_irq_ctrl_hw_t proc0_irq_ctrl; + io_bank0_irq_ctrl_hw_t proc1_irq_ctrl; + io_bank0_irq_ctrl_hw_t dormant_wake_irq_ctrl; + }; + io_bank0_irq_ctrl_hw_t irq_ctrl[3]; + }; +} io_bank0_hw_t; +/// \end::io_bank0_hw[] + +#define io_bank0_hw ((io_bank0_hw_t *)IO_BANK0_BASE) +static_assert(sizeof (io_bank0_hw_t) == 0x0190, ""); + +#endif // _HARDWARE_STRUCTS_IO_BANK0_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/io_qspi.h b/lib/pico-sdk/rp2040/hardware/structs/io_qspi.h new file mode 100644 index 000000000000..4dca02f5cb30 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/io_qspi.h @@ -0,0 +1,189 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_IO_QSPI_H +#define _HARDWARE_STRUCTS_IO_QSPI_H + +/** + * \file rp2040/io_qspi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/io_qspi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** + * \brief QSPI pin function selectors on RP2040 (used as typedef \ref gpio_function1_t) + */ +typedef enum gpio_function1_rp2040 { + GPIO_FUNC1_XIP = 0, ///< Select XIP as QSPI pin function + GPIO_FUNC1_SIO = 5, ///< Select SIO as QSPI pin function + GPIO_FUNC1_NULL = 0x1f, ///< Select NULL as QSPI pin function +} gpio_function1_t; + +typedef struct { + _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS + // GPIO status + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x01000000 [24] IRQFROMPAD (0) interrupt from pad before override is applied + // 0x00080000 [19] INTOPERI (0) input signal to peripheral, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before override is applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00001000 [12] OEFROMPERI (0) output enable from selected peripheral, before register... + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + // 0x00000100 [8] OUTFROMPERI (0) output signal from selected peripheral, before register... + io_ro_32 status; + + _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL + // GPIO control including function select and overrides + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x00003000 [13:12] OEOVER (0x0) + // 0x00000300 [9:8] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 ctrl; +} io_qspi_status_ctrl_hw_t; + +typedef struct { + _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE + // Interrupt Enable for proc0 + // 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_rw_32 inte; + + _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF + // Interrupt Force for proc0 + // 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_rw_32 intf; + + _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS + // Interrupt status after masking & forcing for proc0 + // 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_ro_32 ints; +} io_qspi_irq_ctrl_hw_t; + +typedef struct { + io_qspi_status_ctrl_hw_t io[6]; + + _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR + // Raw Interrupts + // 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0) + io_rw_32 intr; + + union { + struct { + io_qspi_irq_ctrl_hw_t proc0_irq_ctrl; + io_qspi_irq_ctrl_hw_t proc1_irq_ctrl; + io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl; + }; + io_qspi_irq_ctrl_hw_t irq_ctrl[3]; + }; +} io_qspi_hw_t; + +#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE) +static_assert(sizeof (io_qspi_hw_t) == 0x0058, ""); + +#endif // _HARDWARE_STRUCTS_IO_QSPI_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/iobank0.h b/lib/pico-sdk/rp2040/hardware/structs/iobank0.h new file mode 100644 index 000000000000..2dc31e38d432 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/iobank0.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/io_bank0.h" +#define iobank0_hw io_bank0_hw \ No newline at end of file diff --git a/lib/pico-sdk/rp2040/hardware/structs/ioqspi.h b/lib/pico-sdk/rp2040/hardware/structs/ioqspi.h new file mode 100644 index 000000000000..20cc74c79b48 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/ioqspi.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/io_qspi.h" +#define ioqspi_hw io_qspi_hw \ No newline at end of file diff --git a/lib/pico-sdk/rp2040/hardware/structs/m0plus.h b/lib/pico-sdk/rp2040/hardware/structs/m0plus.h new file mode 100644 index 000000000000..6d30edec0018 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/m0plus.h @@ -0,0 +1,197 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_M0PLUS_H +#define _HARDWARE_STRUCTS_M0PLUS_H + +/** + * \file rp2040/m0plus.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + uint32_t _pad0[14340]; + + _REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR + // SysTick Control and Status Register + // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read + // 0x00000004 [2] CLKSOURCE (0) SysTick clock source + // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + + // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + + io_rw_32 syst_csr; + + _REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR + // SysTick Reload Value Register + // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... + io_rw_32 syst_rvr; + + _REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR + // SysTick Current Value Register + // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter + io_rw_32 syst_cvr; + + _REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB + // SysTick Calibration Value Register + // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... + // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... + // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... + io_ro_32 syst_calib; + + uint32_t _pad1[56]; + + _REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER + // Interrupt Set-Enable Register + // 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits + io_rw_32 nvic_iser; + + uint32_t _pad2[31]; + + _REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER + // Interrupt Clear-Enable Register + // 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits + io_rw_32 nvic_icer; + + uint32_t _pad3[31]; + + _REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR + // Interrupt Set-Pending Register + // 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits + io_rw_32 nvic_ispr; + + uint32_t _pad4[31]; + + _REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR + // Interrupt Clear-Pending Register + // 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits + io_rw_32 nvic_icpr; + + uint32_t _pad5[95]; + + // (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes) + _REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0 + // Interrupt Priority Register 0 + // 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3 + // 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2 + // 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1 + // 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0 + io_rw_32 nvic_ipr[8]; + + uint32_t _pad6[568]; + + _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID + // CPUID Base Register + // 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM + // 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: + + // 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: + + // 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+ + // 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: + + io_ro_32 cpuid; + + _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR + // Interrupt Control and State Register + // 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI + // 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit + // 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit + // 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit + // 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit + // 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted + // 0x00400000 [22] ISRPENDING (0) External interrupt pending flag + // 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority... + // 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field + io_rw_32 icsr; + + _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR + // Vector Table Offset Register + // 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address + io_rw_32 vtor; + + _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR + // Application Interrupt and Reset Control Register + // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + + // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + + // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... + // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... + io_rw_32 aircr; + + _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR + // System Control Register + // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + + // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... + // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... + io_rw_32 scr; + + _REG_(M0PLUS_CCR_OFFSET) // M0PLUS_CCR + // Configuration and Control Register + // 0x00000200 [9] STKALIGN (0) Always reads as one, indicates 8-byte stack alignment on... + // 0x00000008 [3] UNALIGN_TRP (0) Always reads as one, indicates that all unaligned... + io_ro_32 ccr; + + uint32_t _pad7; + + // (Description copied from array index 0 register M0PLUS_SHPR2 applies similarly to other array indexes) + _REG_(M0PLUS_SHPR2_OFFSET) // M0PLUS_SHPR2 + // System Handler Priority Register 2 + // 0xc0000000 [31:30] PRI_11 (0x0) Priority of system handler 11, SVCall + io_rw_32 shpr[2]; + + _REG_(M0PLUS_SHCSR_OFFSET) // M0PLUS_SHCSR + // System Handler Control and State Register + // 0x00008000 [15] SVCALLPENDED (0) Reads as 1 if SVCall is Pending + io_rw_32 shcsr; + + uint32_t _pad8[26]; + + _REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE + // MPU Type Register + // 0x00ff0000 [23:16] IREGION (0x00) Instruction region + // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU + // 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps + io_ro_32 mpu_type; + + _REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL + // MPU Control Register + // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a... + // 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs + // 0x00000001 [0] ENABLE (0) Enables the MPU + io_rw_32 mpu_ctrl; + + _REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR + // MPU Region Number Register + // 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and... + io_rw_32 mpu_rnr; + + _REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR + // MPU Region Base Address Register + // 0xffffff00 [31:8] ADDR (0x000000) Base address of the region + // 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the... + // 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base... + io_rw_32 mpu_rbar; + + _REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR + // MPU Region Attribute and Size Register + // 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field + // 0x0000ff00 [15:8] SRD (0x00) Subregion Disable + // 0x0000003e [5:1] SIZE (0x00) Indicates the region size + // 0x00000001 [0] ENABLE (0) Enables the region + io_rw_32 mpu_rasr; +} m0plus_hw_t; + +#define ppb_hw ((m0plus_hw_t *)PPB_BASE) +static_assert(sizeof (m0plus_hw_t) == 0xeda4, ""); + +#endif // _HARDWARE_STRUCTS_M0PLUS_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/mpu.h b/lib/pico-sdk/rp2040/hardware/structs/mpu.h new file mode 100644 index 000000000000..766f4d589514 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/mpu.h @@ -0,0 +1,66 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_MPU_H +#define _HARDWARE_STRUCTS_MPU_H + +/** + * \file rp2040/mpu.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE + // MPU Type Register + // 0x00ff0000 [23:16] IREGION (0x00) Instruction region + // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU + // 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps + io_ro_32 type; + + _REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL + // MPU Control Register + // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a... + // 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs + // 0x00000001 [0] ENABLE (0) Enables the MPU + io_rw_32 ctrl; + + _REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR + // MPU Region Number Register + // 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and... + io_rw_32 rnr; + + _REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR + // MPU Region Base Address Register + // 0xffffff00 [31:8] ADDR (0x000000) Base address of the region + // 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the... + // 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base... + io_rw_32 rbar; + + _REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR + // MPU Region Attribute and Size Register + // 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field + // 0x0000ff00 [15:8] SRD (0x00) Subregion Disable + // 0x0000003e [5:1] SIZE (0x00) Indicates the region size + // 0x00000001 [0] ENABLE (0) Enables the region + io_rw_32 rasr; +} mpu_hw_t; + +#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET)) +static_assert(sizeof (mpu_hw_t) == 0x0014, ""); + +#endif // _HARDWARE_STRUCTS_MPU_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/nvic.h b/lib/pico-sdk/rp2040/hardware/structs/nvic.h new file mode 100644 index 000000000000..d09ebd19e85a --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/nvic.h @@ -0,0 +1,69 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_NVIC_H +#define _HARDWARE_STRUCTS_NVIC_H + +/** + * \file rp2040/nvic.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER + // Interrupt Set-Enable Register + // 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits + io_rw_32 iser; + + uint32_t _pad0[31]; + + _REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER + // Interrupt Clear-Enable Register + // 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits + io_rw_32 icer; + + uint32_t _pad1[31]; + + _REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR + // Interrupt Set-Pending Register + // 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits + io_rw_32 ispr; + + uint32_t _pad2[31]; + + _REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR + // Interrupt Clear-Pending Register + // 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits + io_rw_32 icpr; + + uint32_t _pad3[95]; + + // (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes) + _REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0 + // Interrupt Priority Register 0 + // 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3 + // 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2 + // 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1 + // 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0 + io_rw_32 ipr[8]; +} nvic_hw_t; + +#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)) +static_assert(sizeof (nvic_hw_t) == 0x0320, ""); + +#endif // _HARDWARE_STRUCTS_NVIC_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/pads_bank0.h b/lib/pico-sdk/rp2040/hardware/structs/pads_bank0.h new file mode 100644 index 000000000000..f00c70afcb44 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/pads_bank0.h @@ -0,0 +1,49 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PADS_BANK0_H +#define _HARDWARE_STRUCTS_PADS_BANK0_H + +/** + * \file rp2040/pads_bank0.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pads_bank0.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT + // Voltage select + // 0x00000001 [0] VOLTAGE_SELECT (0) + io_rw_32 voltage_select; + + // (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes) + _REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0 + // Pad control register + // 0x00000080 [7] OD (0) Output disable + // 0x00000040 [6] IE (1) Input enable + // 0x00000030 [5:4] DRIVE (0x1) Drive strength + // 0x00000008 [3] PUE (0) Pull up enable + // 0x00000004 [2] PDE (1) Pull down enable + // 0x00000002 [1] SCHMITT (1) Enable schmitt trigger + // 0x00000001 [0] SLEWFAST (0) Slew rate control + io_rw_32 io[30]; +} pads_bank0_hw_t; + +#define pads_bank0_hw ((pads_bank0_hw_t *)PADS_BANK0_BASE) +static_assert(sizeof (pads_bank0_hw_t) == 0x007c, ""); + +#endif // _HARDWARE_STRUCTS_PADS_BANK0_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/pads_qspi.h b/lib/pico-sdk/rp2040/hardware/structs/pads_qspi.h new file mode 100644 index 000000000000..66b6c1a1bbd9 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/pads_qspi.h @@ -0,0 +1,49 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H +#define _HARDWARE_STRUCTS_PADS_QSPI_H + +/** + * \file rp2040/pads_qspi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pads_qspi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT + // Voltage select + // 0x00000001 [0] VOLTAGE_SELECT (0) + io_rw_32 voltage_select; + + // (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes) + _REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK + // Pad control register + // 0x00000080 [7] OD (0) Output disable + // 0x00000040 [6] IE (1) Input enable + // 0x00000030 [5:4] DRIVE (0x1) Drive strength + // 0x00000008 [3] PUE (0) Pull up enable + // 0x00000004 [2] PDE (1) Pull down enable + // 0x00000002 [1] SCHMITT (1) Enable schmitt trigger + // 0x00000001 [0] SLEWFAST (0) Slew rate control + io_rw_32 io[6]; +} pads_qspi_hw_t; + +#define pads_qspi_hw ((pads_qspi_hw_t *)PADS_QSPI_BASE) +static_assert(sizeof (pads_qspi_hw_t) == 0x001c, ""); + +#endif // _HARDWARE_STRUCTS_PADS_QSPI_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/padsbank0.h b/lib/pico-sdk/rp2040/hardware/structs/padsbank0.h new file mode 100644 index 000000000000..cb14e792b739 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/padsbank0.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/pads_bank0.h" +#define padsbank0_hw pads_bank0_hw \ No newline at end of file diff --git a/lib/pico-sdk/rp2040/hardware/structs/pio.h b/lib/pico-sdk/rp2040/hardware/structs/pio.h new file mode 100644 index 000000000000..bceb14a71adb --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/pio.h @@ -0,0 +1,343 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PIO_H +#define _HARDWARE_STRUCTS_PIO_H + +/** + * \file rp2040/pio.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pio.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV + // Clock divisor register for state machine 0 + + // 0xffff0000 [31:16] INT (0x0001) Effective frequency is sysclk/(int + frac/256) + // 0x0000ff00 [15:8] FRAC (0x00) Fractional part of clock divisor + io_rw_32 clkdiv; + + _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL + // Execution/behavioural settings for state machine 0 + // 0x80000000 [31] EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,... + // 0x40000000 [30] SIDE_EN (0) If 1, the MSB of the Delay/Side-set instruction field is... + // 0x20000000 [29] SIDE_PINDIR (0) If 1, side-set data is asserted to pin directions,... + // 0x1f000000 [28:24] JMP_PIN (0x00) The GPIO number to use as condition for JMP PIN + // 0x00f80000 [23:19] OUT_EN_SEL (0x00) Which data bit to use for inline OUT enable + // 0x00040000 [18] INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable + + // 0x00020000 [17] OUT_STICKY (0) Continuously assert the most recent OUT/SET to the pins + // 0x0001f000 [16:12] WRAP_TOP (0x1f) After reaching this address, execution is wrapped to wrap_bottom + // 0x00000f80 [11:7] WRAP_BOTTOM (0x00) After reaching wrap_top, execution is wrapped to this address + // 0x00000010 [4] STATUS_SEL (0) Comparison used for the MOV x, STATUS instruction + // 0x0000000f [3:0] STATUS_N (0x0) Comparison level for the MOV x, STATUS instruction + io_rw_32 execctrl; + + _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL + // Control behaviour of the input/output shift registers for state machine 0 + // 0x80000000 [31] FJOIN_RX (0) When 1, RX FIFO steals the TX FIFO's storage, and... + // 0x40000000 [30] FJOIN_TX (0) When 1, TX FIFO steals the RX FIFO's storage, and... + // 0x3e000000 [29:25] PULL_THRESH (0x00) Number of bits shifted out of OSR before autopull, or... + // 0x01f00000 [24:20] PUSH_THRESH (0x00) Number of bits shifted into ISR before autopush, or... + // 0x00080000 [19] OUT_SHIFTDIR (1) 1 = shift out of output shift register to right + // 0x00040000 [18] IN_SHIFTDIR (1) 1 = shift input shift register to right (data enters from left) + // 0x00020000 [17] AUTOPULL (0) Pull automatically when the output shift register is emptied, i + // 0x00010000 [16] AUTOPUSH (0) Push automatically when the input shift register is filled, i + io_rw_32 shiftctrl; + + _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR + // Current instruction address of state machine 0 + // 0x0000001f [4:0] SM0_ADDR (0x00) + io_ro_32 addr; + + _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR + // Read to see the instruction currently addressed by state machine 0's program counter + + // 0x0000ffff [15:0] SM0_INSTR (-) + io_rw_32 instr; + + _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL + // State machine pin control + // 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction... + // 0x1c000000 [28:26] SET_COUNT (0x5) The number of pins asserted by a SET + // 0x03f00000 [25:20] OUT_COUNT (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS... + // 0x000f8000 [19:15] IN_BASE (0x00) The pin which is mapped to the least-significant bit of... + // 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a... + // 0x000003e0 [9:5] SET_BASE (0x00) The lowest-numbered pin that will be affected by a SET... + // 0x0000001f [4:0] OUT_BASE (0x00) The lowest-numbered pin that will be affected by an OUT... + io_rw_32 pinctrl; +} pio_sm_hw_t; + +typedef struct { + _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte; + + _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf; + + _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints; +} pio_irq_ctrl_hw_t; + +typedef struct { + _REG_(PIO_CTRL_OFFSET) // PIO_CTRL + // PIO control register + // 0x00000f00 [11:8] CLKDIV_RESTART (0x0) Restart a state machine's clock divider from an initial... + // 0x000000f0 [7:4] SM_RESTART (0x0) Write 1 to instantly clear internal SM state which may... + // 0x0000000f [3:0] SM_ENABLE (0x0) Enable/disable each of the four state machines by... + io_rw_32 ctrl; + + _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT + // FIFO status register + // 0x0f000000 [27:24] TXEMPTY (0xf) State machine TX FIFO is empty + // 0x000f0000 [19:16] TXFULL (0x0) State machine TX FIFO is full + // 0x00000f00 [11:8] RXEMPTY (0xf) State machine RX FIFO is empty + // 0x0000000f [3:0] RXFULL (0x0) State machine RX FIFO is full + io_ro_32 fstat; + + _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG + // FIFO debug register + // 0x0f000000 [27:24] TXSTALL (0x0) State machine has stalled on empty TX FIFO during a... + // 0x000f0000 [19:16] TXOVER (0x0) TX FIFO overflow (i + // 0x00000f00 [11:8] RXUNDER (0x0) RX FIFO underflow (i + // 0x0000000f [3:0] RXSTALL (0x0) State machine has stalled on full RX FIFO during a... + io_rw_32 fdebug; + + _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL + // FIFO levels + // 0xf0000000 [31:28] RX3 (0x0) + // 0x0f000000 [27:24] TX3 (0x0) + // 0x00f00000 [23:20] RX2 (0x0) + // 0x000f0000 [19:16] TX2 (0x0) + // 0x0000f000 [15:12] RX1 (0x0) + // 0x00000f00 [11:8] TX1 (0x0) + // 0x000000f0 [7:4] RX0 (0x0) + // 0x0000000f [3:0] TX0 (0x0) + io_ro_32 flevel; + + // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes) + _REG_(PIO_TXF0_OFFSET) // PIO_TXF0 + // Direct write access to the TX FIFO for this state machine + // 0xffffffff [31:0] TXF0 (0x00000000) + io_wo_32 txf[4]; + + // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes) + _REG_(PIO_RXF0_OFFSET) // PIO_RXF0 + // Direct read access to the RX FIFO for this state machine + // 0xffffffff [31:0] RXF0 (-) + io_ro_32 rxf[4]; + + _REG_(PIO_IRQ_OFFSET) // PIO_IRQ + // State machine IRQ flags register + // 0x000000ff [7:0] IRQ (0x00) + io_rw_32 irq; + + _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE + // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ + // 0x000000ff [7:0] IRQ_FORCE (0x00) + io_wo_32 irq_force; + + _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS + // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities + // 0xffffffff [31:0] INPUT_SYNC_BYPASS (0x00000000) + io_rw_32 input_sync_bypass; + + _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT + // Read to sample the pad output values PIO is currently driving to the GPIOs + // 0xffffffff [31:0] DBG_PADOUT (0x00000000) + io_ro_32 dbg_padout; + + _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE + // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs + // 0xffffffff [31:0] DBG_PADOE (0x00000000) + io_ro_32 dbg_padoe; + + _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO + // The PIO hardware has some free parameters that may vary between chip products + // 0x003f0000 [21:16] IMEM_SIZE (-) The size of the instruction memory, measured in units of... + // 0x00000f00 [11:8] SM_COUNT (-) The number of state machines this PIO instance is equipped with + // 0x0000003f [5:0] FIFO_DEPTH (-) The depth of the state machine TX/RX FIFOs, measured in words + io_ro_32 dbg_cfginfo; + + // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes) + _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0 + // Write-only access to instruction memory location 0 + // 0x0000ffff [15:0] INSTR_MEM0 (0x0000) + io_wo_32 instr_mem[32]; + + pio_sm_hw_t sm[4]; + + _REG_(PIO_INTR_OFFSET) // PIO_INTR + // Raw Interrupts + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 intr; + + union { + struct { + _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte0; + + _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf0; + + _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints0; + + _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE + // Interrupt Enable for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte1; + + _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF + // Interrupt Force for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf1; + + _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS + // Interrupt status after masking & forcing for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints1; + }; + pio_irq_ctrl_hw_t irq_ctrl[2]; + }; +} pio_hw_t; + +#define pio0_hw ((pio_hw_t *)PIO0_BASE) +#define pio1_hw ((pio_hw_t *)PIO1_BASE) +static_assert(sizeof (pio_hw_t) == 0x0144, ""); + +#endif // _HARDWARE_STRUCTS_PIO_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/pll.h b/lib/pico-sdk/rp2040/hardware/structs/pll.h new file mode 100644 index 000000000000..7d3ccc82b5c4 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/pll.h @@ -0,0 +1,61 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PLL_H +#define _HARDWARE_STRUCTS_PLL_H + +/** + * \file rp2040/pll.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pll.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pll +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pll.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/// \tag::pll_hw[] +typedef struct { + _REG_(PLL_CS_OFFSET) // PLL_CS + // Control and Status + // 0x80000000 [31] LOCK (0) PLL is locked + // 0x00000100 [8] BYPASS (0) Passes the reference clock to the output instead of the... + // 0x0000003f [5:0] REFDIV (0x01) Divides the PLL input reference clock + io_rw_32 cs; + + _REG_(PLL_PWR_OFFSET) // PLL_PWR + // Controls the PLL power modes + // 0x00000020 [5] VCOPD (1) PLL VCO powerdown + + // 0x00000008 [3] POSTDIVPD (1) PLL post divider powerdown + + // 0x00000004 [2] DSMPD (1) PLL DSM powerdown + + // 0x00000001 [0] PD (1) PLL powerdown + + io_rw_32 pwr; + + _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT + // Feedback divisor + // 0x00000fff [11:0] FBDIV_INT (0x000) see ctrl reg description for constraints + io_rw_32 fbdiv_int; + + _REG_(PLL_PRIM_OFFSET) // PLL_PRIM + // Controls the PLL post dividers for the primary output + // 0x00070000 [18:16] POSTDIV1 (0x7) divide by 1-7 + // 0x00007000 [14:12] POSTDIV2 (0x7) divide by 1-7 + io_rw_32 prim; +} pll_hw_t; +/// \end::pll_hw[] + +#define pll_sys_hw ((pll_hw_t *)PLL_SYS_BASE) +#define pll_usb_hw ((pll_hw_t *)PLL_USB_BASE) +static_assert(sizeof (pll_hw_t) == 0x0010, ""); + +#endif // _HARDWARE_STRUCTS_PLL_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/psm.h b/lib/pico-sdk/rp2040/hardware/structs/psm.h new file mode 100644 index 000000000000..74ccaf32ad09 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/psm.h @@ -0,0 +1,116 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PSM_H +#define _HARDWARE_STRUCTS_PSM_H + +/** + * \file rp2040/psm.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/psm.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_psm +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/psm.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON + // Force block out of reset (i + // 0x00010000 [16] PROC1 (0) + // 0x00008000 [15] PROC0 (0) + // 0x00004000 [14] SIO (0) + // 0x00002000 [13] VREG_AND_CHIP_RESET (0) + // 0x00001000 [12] XIP (0) + // 0x00000800 [11] SRAM5 (0) + // 0x00000400 [10] SRAM4 (0) + // 0x00000200 [9] SRAM3 (0) + // 0x00000100 [8] SRAM2 (0) + // 0x00000080 [7] SRAM1 (0) + // 0x00000040 [6] SRAM0 (0) + // 0x00000020 [5] ROM (0) + // 0x00000010 [4] BUSFABRIC (0) + // 0x00000008 [3] RESETS (0) + // 0x00000004 [2] CLOCKS (0) + // 0x00000002 [1] XOSC (0) + // 0x00000001 [0] ROSC (0) + io_rw_32 frce_on; + + _REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF + // Force into reset (i + // 0x00010000 [16] PROC1 (0) + // 0x00008000 [15] PROC0 (0) + // 0x00004000 [14] SIO (0) + // 0x00002000 [13] VREG_AND_CHIP_RESET (0) + // 0x00001000 [12] XIP (0) + // 0x00000800 [11] SRAM5 (0) + // 0x00000400 [10] SRAM4 (0) + // 0x00000200 [9] SRAM3 (0) + // 0x00000100 [8] SRAM2 (0) + // 0x00000080 [7] SRAM1 (0) + // 0x00000040 [6] SRAM0 (0) + // 0x00000020 [5] ROM (0) + // 0x00000010 [4] BUSFABRIC (0) + // 0x00000008 [3] RESETS (0) + // 0x00000004 [2] CLOCKS (0) + // 0x00000002 [1] XOSC (0) + // 0x00000001 [0] ROSC (0) + io_rw_32 frce_off; + + _REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL + // Set to 1 if this peripheral should be reset when the watchdog fires + // 0x00010000 [16] PROC1 (0) + // 0x00008000 [15] PROC0 (0) + // 0x00004000 [14] SIO (0) + // 0x00002000 [13] VREG_AND_CHIP_RESET (0) + // 0x00001000 [12] XIP (0) + // 0x00000800 [11] SRAM5 (0) + // 0x00000400 [10] SRAM4 (0) + // 0x00000200 [9] SRAM3 (0) + // 0x00000100 [8] SRAM2 (0) + // 0x00000080 [7] SRAM1 (0) + // 0x00000040 [6] SRAM0 (0) + // 0x00000020 [5] ROM (0) + // 0x00000010 [4] BUSFABRIC (0) + // 0x00000008 [3] RESETS (0) + // 0x00000004 [2] CLOCKS (0) + // 0x00000002 [1] XOSC (0) + // 0x00000001 [0] ROSC (0) + io_rw_32 wdsel; + + _REG_(PSM_DONE_OFFSET) // PSM_DONE + // Indicates the peripheral's registers are ready to access + // 0x00010000 [16] PROC1 (0) + // 0x00008000 [15] PROC0 (0) + // 0x00004000 [14] SIO (0) + // 0x00002000 [13] VREG_AND_CHIP_RESET (0) + // 0x00001000 [12] XIP (0) + // 0x00000800 [11] SRAM5 (0) + // 0x00000400 [10] SRAM4 (0) + // 0x00000200 [9] SRAM3 (0) + // 0x00000100 [8] SRAM2 (0) + // 0x00000080 [7] SRAM1 (0) + // 0x00000040 [6] SRAM0 (0) + // 0x00000020 [5] ROM (0) + // 0x00000010 [4] BUSFABRIC (0) + // 0x00000008 [3] RESETS (0) + // 0x00000004 [2] CLOCKS (0) + // 0x00000002 [1] XOSC (0) + // 0x00000001 [0] ROSC (0) + io_ro_32 done; +} psm_hw_t; + +#define psm_hw ((psm_hw_t *)PSM_BASE) +static_assert(sizeof (psm_hw_t) == 0x0010, ""); + +#endif // _HARDWARE_STRUCTS_PSM_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/pwm.h b/lib/pico-sdk/rp2040/hardware/structs/pwm.h new file mode 100644 index 000000000000..3eedee4d9f3d --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/pwm.h @@ -0,0 +1,172 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PWM_H +#define _HARDWARE_STRUCTS_PWM_H + +/** + * \file rp2040/pwm.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pwm.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pwm +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR + // Control and status register + // 0x00000080 [7] PH_ADV (0) Advance the phase of the counter by 1 count, while it is running + // 0x00000040 [6] PH_RET (0) Retard the phase of the counter by 1 count, while it is running + // 0x00000030 [5:4] DIVMODE (0x0) + // 0x00000008 [3] B_INV (0) Invert output B + // 0x00000004 [2] A_INV (0) Invert output A + // 0x00000002 [1] PH_CORRECT (0) 1: Enable phase-correct modulation + // 0x00000001 [0] EN (0) Enable the PWM channel + io_rw_32 csr; + + _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV + // INT and FRAC form a fixed-point fractional number + // 0x00000ff0 [11:4] INT (0x01) + // 0x0000000f [3:0] FRAC (0x0) + io_rw_32 div; + + _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR + // Direct access to the PWM counter + // 0x0000ffff [15:0] CH0_CTR (0x0000) + io_rw_32 ctr; + + _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC + // Counter compare values + // 0xffff0000 [31:16] B (0x0000) + // 0x0000ffff [15:0] A (0x0000) + io_rw_32 cc; + + _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP + // Counter wrap value + // 0x0000ffff [15:0] CH0_TOP (0xffff) + io_rw_32 top; +} pwm_slice_hw_t; + +typedef struct { + _REG_(PWM_INTE_OFFSET) // PWM_INTE + // Interrupt Enable + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 inte; + + _REG_(PWM_INTF_OFFSET) // PWM_INTF + // Interrupt Force + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intf; + + _REG_(PWM_INTS_OFFSET) // PWM_INTS + // Interrupt status after masking & forcing + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_ro_32 ints; +} pwm_irq_ctrl_hw_t; + +typedef struct { + pwm_slice_hw_t slice[8]; + + _REG_(PWM_EN_OFFSET) // PWM_EN + // This register aliases the CSR_EN bits for all channels + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 en; + + _REG_(PWM_INTR_OFFSET) // PWM_INTR + // Raw Interrupts + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intr; + + union { + struct { + _REG_(PWM_INTE_OFFSET) // PWM_INTE + // Interrupt Enable + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 inte; + + _REG_(PWM_INTF_OFFSET) // PWM_INTF + // Interrupt Force + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intf; + + _REG_(PWM_INTS_OFFSET) // PWM_INTS + // Interrupt status after masking & forcing + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 ints; + }; + pwm_irq_ctrl_hw_t irq_ctrl[1]; + }; +} pwm_hw_t; + +#define pwm_hw ((pwm_hw_t *)PWM_BASE) +static_assert(sizeof (pwm_hw_t) == 0x00b4, ""); + +#endif // _HARDWARE_STRUCTS_PWM_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/resets.h b/lib/pico-sdk/rp2040/hardware/structs/resets.h new file mode 100644 index 000000000000..ca3a62970bf9 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/resets.h @@ -0,0 +1,153 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_RESETS_H +#define _HARDWARE_STRUCTS_RESETS_H + +/** + * \file rp2040/resets.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/resets.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_resets +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/resets.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** \brief Resettable component numbers on RP2040 (used as typedef \ref reset_num_t) + * \ingroup hardware_resets + */ +typedef enum reset_num_rp2040 { + RESET_ADC = 0, ///< Select ADC to be reset + RESET_BUSCTRL = 1, ///< Select BUSCTRL to be reset + RESET_DMA = 2, ///< Select DMA to be reset + RESET_I2C0 = 3, ///< Select I2C0 to be reset + RESET_I2C1 = 4, ///< Select I2C1 to be reset + RESET_IO_BANK0 = 5, ///< Select IO_BANK0 to be reset + RESET_IO_QSPI = 6, ///< Select IO_QSPI to be reset + RESET_JTAG = 7, ///< Select JTAG to be reset + RESET_PADS_BANK0 = 8, ///< Select PADS_BANK0 to be reset + RESET_PADS_QSPI = 9, ///< Select PADS_QSPI to be reset + RESET_PIO0 = 10, ///< Select PIO0 to be reset + RESET_PIO1 = 11, ///< Select PIO1 to be reset + RESET_PLL_SYS = 12, ///< Select PLL_SYS to be reset + RESET_PLL_USB = 13, ///< Select PLL_USB to be reset + RESET_PWM = 14, ///< Select PWM to be reset + RESET_RTC = 15, ///< Select RTC to be reset + RESET_SPI0 = 16, ///< Select SPI0 to be reset + RESET_SPI1 = 17, ///< Select SPI1 to be reset + RESET_SYSCFG = 18, ///< Select SYSCFG to be reset + RESET_SYSINFO = 19, ///< Select SYSINFO to be reset + RESET_TBMAN = 20, ///< Select TBMAN to be reset + RESET_TIMER = 21, ///< Select TIMER to be reset + RESET_UART0 = 22, ///< Select UART0 to be reset + RESET_UART1 = 23, ///< Select UART1 to be reset + RESET_USBCTRL = 24, ///< Select USBCTRL to be reset + RESET_COUNT +} reset_num_t; + +/// \tag::resets_hw[] +typedef struct { + _REG_(RESETS_RESET_OFFSET) // RESETS_RESET + // Reset control. + // 0x01000000 [24] USBCTRL (1) + // 0x00800000 [23] UART1 (1) + // 0x00400000 [22] UART0 (1) + // 0x00200000 [21] TIMER (1) + // 0x00100000 [20] TBMAN (1) + // 0x00080000 [19] SYSINFO (1) + // 0x00040000 [18] SYSCFG (1) + // 0x00020000 [17] SPI1 (1) + // 0x00010000 [16] SPI0 (1) + // 0x00008000 [15] RTC (1) + // 0x00004000 [14] PWM (1) + // 0x00002000 [13] PLL_USB (1) + // 0x00001000 [12] PLL_SYS (1) + // 0x00000800 [11] PIO1 (1) + // 0x00000400 [10] PIO0 (1) + // 0x00000200 [9] PADS_QSPI (1) + // 0x00000100 [8] PADS_BANK0 (1) + // 0x00000080 [7] JTAG (1) + // 0x00000040 [6] IO_QSPI (1) + // 0x00000020 [5] IO_BANK0 (1) + // 0x00000010 [4] I2C1 (1) + // 0x00000008 [3] I2C0 (1) + // 0x00000004 [2] DMA (1) + // 0x00000002 [1] BUSCTRL (1) + // 0x00000001 [0] ADC (1) + io_rw_32 reset; + + _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL + // Watchdog select. + // 0x01000000 [24] USBCTRL (0) + // 0x00800000 [23] UART1 (0) + // 0x00400000 [22] UART0 (0) + // 0x00200000 [21] TIMER (0) + // 0x00100000 [20] TBMAN (0) + // 0x00080000 [19] SYSINFO (0) + // 0x00040000 [18] SYSCFG (0) + // 0x00020000 [17] SPI1 (0) + // 0x00010000 [16] SPI0 (0) + // 0x00008000 [15] RTC (0) + // 0x00004000 [14] PWM (0) + // 0x00002000 [13] PLL_USB (0) + // 0x00001000 [12] PLL_SYS (0) + // 0x00000800 [11] PIO1 (0) + // 0x00000400 [10] PIO0 (0) + // 0x00000200 [9] PADS_QSPI (0) + // 0x00000100 [8] PADS_BANK0 (0) + // 0x00000080 [7] JTAG (0) + // 0x00000040 [6] IO_QSPI (0) + // 0x00000020 [5] IO_BANK0 (0) + // 0x00000010 [4] I2C1 (0) + // 0x00000008 [3] I2C0 (0) + // 0x00000004 [2] DMA (0) + // 0x00000002 [1] BUSCTRL (0) + // 0x00000001 [0] ADC (0) + io_rw_32 wdsel; + + _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE + // Reset done. + // 0x01000000 [24] USBCTRL (0) + // 0x00800000 [23] UART1 (0) + // 0x00400000 [22] UART0 (0) + // 0x00200000 [21] TIMER (0) + // 0x00100000 [20] TBMAN (0) + // 0x00080000 [19] SYSINFO (0) + // 0x00040000 [18] SYSCFG (0) + // 0x00020000 [17] SPI1 (0) + // 0x00010000 [16] SPI0 (0) + // 0x00008000 [15] RTC (0) + // 0x00004000 [14] PWM (0) + // 0x00002000 [13] PLL_USB (0) + // 0x00001000 [12] PLL_SYS (0) + // 0x00000800 [11] PIO1 (0) + // 0x00000400 [10] PIO0 (0) + // 0x00000200 [9] PADS_QSPI (0) + // 0x00000100 [8] PADS_BANK0 (0) + // 0x00000080 [7] JTAG (0) + // 0x00000040 [6] IO_QSPI (0) + // 0x00000020 [5] IO_BANK0 (0) + // 0x00000010 [4] I2C1 (0) + // 0x00000008 [3] I2C0 (0) + // 0x00000004 [2] DMA (0) + // 0x00000002 [1] BUSCTRL (0) + // 0x00000001 [0] ADC (0) + io_ro_32 reset_done; +} resets_hw_t; +/// \end::resets_hw[] + +#define resets_hw ((resets_hw_t *)RESETS_BASE) +static_assert(sizeof (resets_hw_t) == 0x000c, ""); + +#endif // _HARDWARE_STRUCTS_RESETS_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/rosc.h b/lib/pico-sdk/rp2040/hardware/structs/rosc.h new file mode 100644 index 000000000000..2bc82007b080 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/rosc.h @@ -0,0 +1,92 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_ROSC_H +#define _HARDWARE_STRUCTS_ROSC_H + +/** + * \file rp2040/rosc.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/rosc.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rosc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL + // Ring Oscillator control + // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to ENABLE + + // 0x00000fff [11:0] FREQ_RANGE (0xaa0) Controls the number of delay stages in the ROSC ring + + io_rw_32 ctrl; + + _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA + // Ring Oscillator frequency control A + // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings + + // 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength + // 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength + // 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength + // 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength + io_rw_32 freqa; + + _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB + // Ring Oscillator frequency control B + // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings + + // 0x00007000 [14:12] DS7 (0x0) Stage 7 drive strength + // 0x00000700 [10:8] DS6 (0x0) Stage 6 drive strength + // 0x00000070 [6:4] DS5 (0x0) Stage 5 drive strength + // 0x00000007 [2:0] DS4 (0x0) Stage 4 drive strength + io_rw_32 freqb; + + _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT + // Ring Oscillator pause control + // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the ROSC + + io_rw_32 dormant; + + _REG_(ROSC_DIV_OFFSET) // ROSC_DIV + // Controls the output divider + // 0x00000fff [11:0] DIV (-) set to 0xaa0 + div where + + io_rw_32 div; + + _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE + // Controls the phase shifted output + // 0x00000ff0 [11:4] PASSWD (0x00) set to 0xaa + + // 0x00000008 [3] ENABLE (1) enable the phase-shifted output + + // 0x00000004 [2] FLIP (0) invert the phase-shifted output + + // 0x00000003 [1:0] SHIFT (0x0) phase shift the phase-shifted output by SHIFT input clocks + + io_rw_32 phase; + + _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS + // Ring Oscillator Status + // 0x80000000 [31] STABLE (0) Oscillator is running and stable + // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or... + // 0x00010000 [16] DIV_RUNNING (-) post-divider is running + + // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and stable + + io_rw_32 status; + + _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT + // Returns a 1 bit random value + // 0x00000001 [0] RANDOMBIT (1) + io_ro_32 randombit; + + _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT + // A down counter running at the ROSC frequency which counts to zero and stops. + // 0x000000ff [7:0] COUNT (0x00) + io_rw_32 count; +} rosc_hw_t; + +#define rosc_hw ((rosc_hw_t *)ROSC_BASE) +static_assert(sizeof (rosc_hw_t) == 0x0024, ""); + +#endif // _HARDWARE_STRUCTS_ROSC_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/rtc.h b/lib/pico-sdk/rp2040/hardware/structs/rtc.h new file mode 100644 index 000000000000..6f35b682a1a9 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/rtc.h @@ -0,0 +1,119 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_RTC_H +#define _HARDWARE_STRUCTS_RTC_H + +/** + * \file rp2040/rtc.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/rtc.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rtc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/rtc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(RTC_CLKDIV_M1_OFFSET) // RTC_CLKDIV_M1 + // Divider minus 1 for the 1 second counter + // 0x0000ffff [15:0] CLKDIV_M1 (0x0000) + io_rw_32 clkdiv_m1; + + _REG_(RTC_SETUP_0_OFFSET) // RTC_SETUP_0 + // RTC setup register 0 + // 0x00fff000 [23:12] YEAR (0x000) Year + // 0x00000f00 [11:8] MONTH (0x0) Month (1 + // 0x0000001f [4:0] DAY (0x00) Day of the month (1 + io_rw_32 setup_0; + + _REG_(RTC_SETUP_1_OFFSET) // RTC_SETUP_1 + // RTC setup register 1 + // 0x07000000 [26:24] DOTW (0x0) Day of the week: 1-Monday + // 0x001f0000 [20:16] HOUR (0x00) Hours + // 0x00003f00 [13:8] MIN (0x00) Minutes + // 0x0000003f [5:0] SEC (0x00) Seconds + io_rw_32 setup_1; + + _REG_(RTC_CTRL_OFFSET) // RTC_CTRL + // RTC Control and status + // 0x00000100 [8] FORCE_NOTLEAPYEAR (0) If set, leapyear is forced off + // 0x00000010 [4] LOAD (0) Load RTC + // 0x00000002 [1] RTC_ACTIVE (-) RTC enabled (running) + // 0x00000001 [0] RTC_ENABLE (0) Enable RTC + io_rw_32 ctrl; + + _REG_(RTC_IRQ_SETUP_0_OFFSET) // RTC_IRQ_SETUP_0 + // Interrupt setup register 0 + // 0x20000000 [29] MATCH_ACTIVE (-) + // 0x10000000 [28] MATCH_ENA (0) Global match enable + // 0x04000000 [26] YEAR_ENA (0) Enable year matching + // 0x02000000 [25] MONTH_ENA (0) Enable month matching + // 0x01000000 [24] DAY_ENA (0) Enable day matching + // 0x00fff000 [23:12] YEAR (0x000) Year + // 0x00000f00 [11:8] MONTH (0x0) Month (1 + // 0x0000001f [4:0] DAY (0x00) Day of the month (1 + io_rw_32 irq_setup_0; + + _REG_(RTC_IRQ_SETUP_1_OFFSET) // RTC_IRQ_SETUP_1 + // Interrupt setup register 1 + // 0x80000000 [31] DOTW_ENA (0) Enable day of the week matching + // 0x40000000 [30] HOUR_ENA (0) Enable hour matching + // 0x20000000 [29] MIN_ENA (0) Enable minute matching + // 0x10000000 [28] SEC_ENA (0) Enable second matching + // 0x07000000 [26:24] DOTW (0x0) Day of the week + // 0x001f0000 [20:16] HOUR (0x00) Hours + // 0x00003f00 [13:8] MIN (0x00) Minutes + // 0x0000003f [5:0] SEC (0x00) Seconds + io_rw_32 irq_setup_1; + + _REG_(RTC_RTC_1_OFFSET) // RTC_RTC_1 + // RTC register 1 + // 0x00fff000 [23:12] YEAR (-) Year + // 0x00000f00 [11:8] MONTH (-) Month (1 + // 0x0000001f [4:0] DAY (-) Day of the month (1 + io_ro_32 rtc_1; + + _REG_(RTC_RTC_0_OFFSET) // RTC_RTC_0 + // RTC register 0 + + // 0x07000000 [26:24] DOTW (-) Day of the week + // 0x001f0000 [20:16] HOUR (-) Hours + // 0x00003f00 [13:8] MIN (-) Minutes + // 0x0000003f [5:0] SEC (-) Seconds + io_ro_32 rtc_0; + + _REG_(RTC_INTR_OFFSET) // RTC_INTR + // Raw Interrupts + // 0x00000001 [0] RTC (0) + io_ro_32 intr; + + _REG_(RTC_INTE_OFFSET) // RTC_INTE + // Interrupt Enable + // 0x00000001 [0] RTC (0) + io_rw_32 inte; + + _REG_(RTC_INTF_OFFSET) // RTC_INTF + // Interrupt Force + // 0x00000001 [0] RTC (0) + io_rw_32 intf; + + _REG_(RTC_INTS_OFFSET) // RTC_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] RTC (0) + io_ro_32 ints; +} rtc_hw_t; + +#define rtc_hw ((rtc_hw_t *)RTC_BASE) +static_assert(sizeof (rtc_hw_t) == 0x0030, ""); + +#endif // _HARDWARE_STRUCTS_RTC_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/scb.h b/lib/pico-sdk/rp2040/hardware/structs/scb.h new file mode 100644 index 000000000000..d4af74800855 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/scb.h @@ -0,0 +1,74 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SCB_H +#define _HARDWARE_STRUCTS_SCB_H + +/** + * \file rp2040/scb.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID + // CPUID Base Register + // 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM + // 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: + + // 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: + + // 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+ + // 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: + + io_ro_32 cpuid; + + _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR + // Interrupt Control and State Register + // 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI + // 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit + // 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit + // 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit + // 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit + // 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted + // 0x00400000 [22] ISRPENDING (0) External interrupt pending flag + // 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority... + // 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field + io_rw_32 icsr; + + _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR + // Vector Table Offset Register + // 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address + io_rw_32 vtor; + + _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR + // Application Interrupt and Reset Control Register + // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + + // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + + // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... + // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... + io_rw_32 aircr; + + _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR + // System Control Register + // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + + // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... + // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... + io_rw_32 scr; +} armv6m_scb_hw_t; + +#define scb_hw ((armv6m_scb_hw_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET)) +static_assert(sizeof (armv6m_scb_hw_t) == 0x0014, ""); + +#endif // _HARDWARE_STRUCTS_SCB_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/sio.h b/lib/pico-sdk/rp2040/hardware/structs/sio.h new file mode 100644 index 000000000000..412a7d868d0e --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/sio.h @@ -0,0 +1,200 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SIO_H +#define _HARDWARE_STRUCTS_SIO_H + +/** + * \file rp2040/sio.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" +#include "hardware/structs/interp.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + + +typedef struct { + _REG_(SIO_CPUID_OFFSET) // SIO_CPUID + // Processor core identifier + // 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when... + io_ro_32 cpuid; + + _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN + // Input value for GPIO pins + // 0x3fffffff [29:0] GPIO_IN (0x00000000) Input value for GPIO0 + io_ro_32 gpio_in; + + _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN + // Input value for QSPI pins + // 0x0000003f [5:0] GPIO_HI_IN (0x00) Input value on QSPI IO in order 0 + io_ro_32 gpio_hi_in; + + uint32_t _pad0; + + _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT + // GPIO output value + // 0x3fffffff [29:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0 + io_rw_32 gpio_out; + + _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET + // GPIO output value set + // 0x3fffffff [29:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i + io_wo_32 gpio_set; + + _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR + // GPIO output value clear + // 0x3fffffff [29:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i + io_wo_32 gpio_clr; + + _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR + // GPIO output value XOR + // 0x3fffffff [29:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i + io_wo_32 gpio_togl; + + _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE + // GPIO output enable + // 0x3fffffff [29:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0 + io_rw_32 gpio_oe; + + _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET + // GPIO output enable set + // 0x3fffffff [29:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i + io_wo_32 gpio_oe_set; + + _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR + // GPIO output enable clear + // 0x3fffffff [29:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i + io_wo_32 gpio_oe_clr; + + _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR + // GPIO output enable XOR + // 0x3fffffff [29:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i + io_wo_32 gpio_oe_togl; + + _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT + // QSPI output value + // 0x0000003f [5:0] GPIO_HI_OUT (0x00) Set output level (1/0 -> high/low) for QSPI IO0 + io_rw_32 gpio_hi_out; + + _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET + // QSPI output value set + // 0x0000003f [5:0] GPIO_HI_OUT_SET (0x00) Perform an atomic bit-set on GPIO_HI_OUT, i + io_wo_32 gpio_hi_set; + + _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR + // QSPI output value clear + // 0x0000003f [5:0] GPIO_HI_OUT_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OUT, i + io_wo_32 gpio_hi_clr; + + _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR + // QSPI output value XOR + // 0x0000003f [5:0] GPIO_HI_OUT_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OUT, i + io_wo_32 gpio_hi_togl; + + _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE + // QSPI output enable + // 0x0000003f [5:0] GPIO_HI_OE (0x00) Set output enable (1/0 -> output/input) for QSPI IO0 + io_rw_32 gpio_hi_oe; + + _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET + // QSPI output enable set + // 0x0000003f [5:0] GPIO_HI_OE_SET (0x00) Perform an atomic bit-set on GPIO_HI_OE, i + io_wo_32 gpio_hi_oe_set; + + _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR + // QSPI output enable clear + // 0x0000003f [5:0] GPIO_HI_OE_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OE, i + io_wo_32 gpio_hi_oe_clr; + + _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR + // QSPI output enable XOR + // 0x0000003f [5:0] GPIO_HI_OE_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OE, i + io_wo_32 gpio_hi_oe_togl; + + _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST + // Status register for inter-core FIFOs (mailboxes). + // 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty + // 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full + // 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i + // 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i + io_rw_32 fifo_st; + + _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR + // Write access to this core's TX FIFO + // 0xffffffff [31:0] FIFO_WR (0x00000000) + io_wo_32 fifo_wr; + + _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD + // Read access to this core's RX FIFO + // 0xffffffff [31:0] FIFO_RD (-) + io_ro_32 fifo_rd; + + _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST + // Spinlock state + // 0xffffffff [31:0] SPINLOCK_ST (0x00000000) + io_ro_32 spinlock_st; + + _REG_(SIO_DIV_UDIVIDEND_OFFSET) // SIO_DIV_UDIVIDEND + // Divider unsigned dividend + // 0xffffffff [31:0] DIV_UDIVIDEND (0x00000000) + io_rw_32 div_udividend; + + _REG_(SIO_DIV_UDIVISOR_OFFSET) // SIO_DIV_UDIVISOR + // Divider unsigned divisor + // 0xffffffff [31:0] DIV_UDIVISOR (0x00000000) + io_rw_32 div_udivisor; + + _REG_(SIO_DIV_SDIVIDEND_OFFSET) // SIO_DIV_SDIVIDEND + // Divider signed dividend + // 0xffffffff [31:0] DIV_SDIVIDEND (0x00000000) + io_rw_32 div_sdividend; + + _REG_(SIO_DIV_SDIVISOR_OFFSET) // SIO_DIV_SDIVISOR + // Divider signed divisor + // 0xffffffff [31:0] DIV_SDIVISOR (0x00000000) + io_rw_32 div_sdivisor; + + _REG_(SIO_DIV_QUOTIENT_OFFSET) // SIO_DIV_QUOTIENT + // Divider result quotient + // 0xffffffff [31:0] DIV_QUOTIENT (0x00000000) + io_rw_32 div_quotient; + + _REG_(SIO_DIV_REMAINDER_OFFSET) // SIO_DIV_REMAINDER + // Divider result remainder + // 0xffffffff [31:0] DIV_REMAINDER (0x00000000) + io_rw_32 div_remainder; + + _REG_(SIO_DIV_CSR_OFFSET) // SIO_DIV_CSR + // Control and status register for divider + // 0x00000002 [1] DIRTY (0) Changes to 1 when any register is written, and back to 0... + // 0x00000001 [0] READY (1) Reads as 0 when a calculation is in progress, 1 otherwise + io_ro_32 div_csr; + + uint32_t _pad1; + + interp_hw_t interp[2]; + + // (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes) + _REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0 + // Spinlock register 0 + // 0xffffffff [31:0] SPINLOCK0 (0x00000000) + io_rw_32 spinlock[32]; +} sio_hw_t; + +#define sio_hw ((sio_hw_t *)SIO_BASE) +static_assert(sizeof (sio_hw_t) == 0x0180, ""); + +#endif // _HARDWARE_STRUCTS_SIO_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/spi.h b/lib/pico-sdk/rp2040/hardware/structs/spi.h new file mode 100644 index 000000000000..7d1956e91fa4 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/spi.h @@ -0,0 +1,105 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SPI_H +#define _HARDWARE_STRUCTS_SPI_H + +/** + * \file rp2040/spi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/spi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_spi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/spi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0 + // Control register 0, SSPCR0 on page 3-4 + // 0x0000ff00 [15:8] SCR (0x00) Serial clock rate + // 0x00000080 [7] SPH (0) SSPCLKOUT phase, applicable to Motorola SPI frame format only + // 0x00000040 [6] SPO (0) SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // 0x00000030 [5:4] FRF (0x0) Frame format: 00 Motorola SPI frame format + // 0x0000000f [3:0] DSS (0x0) Data Size Select: 0000 Reserved, undefined operation + io_rw_32 cr0; + + _REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1 + // Control register 1, SSPCR1 on page 3-5 + // 0x00000008 [3] SOD (0) Slave-mode output disable + // 0x00000004 [2] MS (0) Master or slave mode select + // 0x00000002 [1] SSE (0) Synchronous serial port enable: 0 SSP operation disabled + // 0x00000001 [0] LBM (0) Loop back mode: 0 Normal serial port operation enabled + io_rw_32 cr1; + + _REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR + // Data register, SSPDR on page 3-6 + // 0x0000ffff [15:0] DATA (-) Transmit/Receive FIFO: Read Receive FIFO + io_rw_32 dr; + + _REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR + // Status register, SSPSR on page 3-7 + // 0x00000010 [4] BSY (0) PrimeCell SSP busy flag, RO: 0 SSP is idle + // 0x00000008 [3] RFF (0) Receive FIFO full, RO: 0 Receive FIFO is not full + // 0x00000004 [2] RNE (0) Receive FIFO not empty, RO: 0 Receive FIFO is empty + // 0x00000002 [1] TNF (1) Transmit FIFO not full, RO: 0 Transmit FIFO is full + // 0x00000001 [0] TFE (1) Transmit FIFO empty, RO: 0 Transmit FIFO is not empty + io_ro_32 sr; + + _REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR + // Clock prescale register, SSPCPSR on page 3-8 + // 0x000000ff [7:0] CPSDVSR (0x00) Clock prescale divisor + io_rw_32 cpsr; + + _REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC + // Interrupt mask set or clear register, SSPIMSC on page 3-9 + // 0x00000008 [3] TXIM (0) Transmit FIFO interrupt mask: 0 Transmit FIFO half empty... + // 0x00000004 [2] RXIM (0) Receive FIFO interrupt mask: 0 Receive FIFO half full or... + // 0x00000002 [1] RTIM (0) Receive timeout interrupt mask: 0 Receive FIFO not empty... + // 0x00000001 [0] RORIM (0) Receive overrun interrupt mask: 0 Receive FIFO written... + io_rw_32 imsc; + + _REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS + // Raw interrupt status register, SSPRIS on page 3-10 + // 0x00000008 [3] TXRIS (1) Gives the raw interrupt state, prior to masking, of the... + // 0x00000004 [2] RXRIS (0) Gives the raw interrupt state, prior to masking, of the... + // 0x00000002 [1] RTRIS (0) Gives the raw interrupt state, prior to masking, of the... + // 0x00000001 [0] RORRIS (0) Gives the raw interrupt state, prior to masking, of the... + io_ro_32 ris; + + _REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS + // Masked interrupt status register, SSPMIS on page 3-11 + // 0x00000008 [3] TXMIS (0) Gives the transmit FIFO masked interrupt state, after... + // 0x00000004 [2] RXMIS (0) Gives the receive FIFO masked interrupt state, after... + // 0x00000002 [1] RTMIS (0) Gives the receive timeout masked interrupt state, after... + // 0x00000001 [0] RORMIS (0) Gives the receive over run masked interrupt status,... + io_ro_32 mis; + + _REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR + // Interrupt clear register, SSPICR on page 3-11 + // 0x00000002 [1] RTIC (0) Clears the SSPRTINTR interrupt + // 0x00000001 [0] RORIC (0) Clears the SSPRORINTR interrupt + io_rw_32 icr; + + _REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR + // DMA control register, SSPDMACR on page 3-12 + // 0x00000002 [1] TXDMAE (0) Transmit DMA Enable + // 0x00000001 [0] RXDMAE (0) Receive DMA Enable + io_rw_32 dmacr; +} spi_hw_t; + +#define spi0_hw ((spi_hw_t *)SPI0_BASE) +#define spi1_hw ((spi_hw_t *)SPI1_BASE) +static_assert(sizeof (spi_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_SPI_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/ssi.h b/lib/pico-sdk/rp2040/hardware/structs/ssi.h new file mode 100644 index 000000000000..9d5fdace6e9d --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/ssi.h @@ -0,0 +1,215 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SSI_H +#define _HARDWARE_STRUCTS_SSI_H + +/** + * \file rp2040/ssi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/ssi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_ssi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/ssi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SSI_CTRLR0_OFFSET) // SSI_CTRLR0 + // Control register 0 + // 0x01000000 [24] SSTE (0) Slave select toggle enable + // 0x00600000 [22:21] SPI_FRF (0x0) SPI frame format + // 0x001f0000 [20:16] DFS_32 (0x00) Data frame size in 32b transfer mode + + // 0x0000f000 [15:12] CFS (0x0) Control frame size + + // 0x00000800 [11] SRL (0) Shift register loop (test mode) + // 0x00000400 [10] SLV_OE (0) Slave output enable + // 0x00000300 [9:8] TMOD (0x0) Transfer mode + // 0x00000080 [7] SCPOL (0) Serial clock polarity + // 0x00000040 [6] SCPH (0) Serial clock phase + // 0x00000030 [5:4] FRF (0x0) Frame format + // 0x0000000f [3:0] DFS (0x0) Data frame size + io_rw_32 ctrlr0; + + _REG_(SSI_CTRLR1_OFFSET) // SSI_CTRLR1 + // Master Control register 1 + // 0x0000ffff [15:0] NDF (0x0000) Number of data frames + io_rw_32 ctrlr1; + + _REG_(SSI_SSIENR_OFFSET) // SSI_SSIENR + // SSI Enable + // 0x00000001 [0] SSI_EN (0) SSI enable + io_rw_32 ssienr; + + _REG_(SSI_MWCR_OFFSET) // SSI_MWCR + // Microwire Control + // 0x00000004 [2] MHS (0) Microwire handshaking + // 0x00000002 [1] MDD (0) Microwire control + // 0x00000001 [0] MWMOD (0) Microwire transfer mode + io_rw_32 mwcr; + + _REG_(SSI_SER_OFFSET) // SSI_SER + // Slave enable + // 0x00000001 [0] SER (0) For each bit: + + io_rw_32 ser; + + _REG_(SSI_BAUDR_OFFSET) // SSI_BAUDR + // Baud rate + // 0x0000ffff [15:0] SCKDV (0x0000) SSI clock divider + io_rw_32 baudr; + + _REG_(SSI_TXFTLR_OFFSET) // SSI_TXFTLR + // TX FIFO threshold level + // 0x000000ff [7:0] TFT (0x00) Transmit FIFO threshold + io_rw_32 txftlr; + + _REG_(SSI_RXFTLR_OFFSET) // SSI_RXFTLR + // RX FIFO threshold level + // 0x000000ff [7:0] RFT (0x00) Receive FIFO threshold + io_rw_32 rxftlr; + + _REG_(SSI_TXFLR_OFFSET) // SSI_TXFLR + // TX FIFO level + // 0x000000ff [7:0] TFTFL (0x00) Transmit FIFO level + io_ro_32 txflr; + + _REG_(SSI_RXFLR_OFFSET) // SSI_RXFLR + // RX FIFO level + // 0x000000ff [7:0] RXTFL (0x00) Receive FIFO level + io_ro_32 rxflr; + + _REG_(SSI_SR_OFFSET) // SSI_SR + // Status register + // 0x00000040 [6] DCOL (0) Data collision error + // 0x00000020 [5] TXE (0) Transmission error + // 0x00000010 [4] RFF (0) Receive FIFO full + // 0x00000008 [3] RFNE (0) Receive FIFO not empty + // 0x00000004 [2] TFE (0) Transmit FIFO empty + // 0x00000002 [1] TFNF (0) Transmit FIFO not full + // 0x00000001 [0] BUSY (0) SSI busy flag + io_ro_32 sr; + + _REG_(SSI_IMR_OFFSET) // SSI_IMR + // Interrupt mask + // 0x00000020 [5] MSTIM (0) Multi-master contention interrupt mask + // 0x00000010 [4] RXFIM (0) Receive FIFO full interrupt mask + // 0x00000008 [3] RXOIM (0) Receive FIFO overflow interrupt mask + // 0x00000004 [2] RXUIM (0) Receive FIFO underflow interrupt mask + // 0x00000002 [1] TXOIM (0) Transmit FIFO overflow interrupt mask + // 0x00000001 [0] TXEIM (0) Transmit FIFO empty interrupt mask + io_rw_32 imr; + + _REG_(SSI_ISR_OFFSET) // SSI_ISR + // Interrupt status + // 0x00000020 [5] MSTIS (0) Multi-master contention interrupt status + // 0x00000010 [4] RXFIS (0) Receive FIFO full interrupt status + // 0x00000008 [3] RXOIS (0) Receive FIFO overflow interrupt status + // 0x00000004 [2] RXUIS (0) Receive FIFO underflow interrupt status + // 0x00000002 [1] TXOIS (0) Transmit FIFO overflow interrupt status + // 0x00000001 [0] TXEIS (0) Transmit FIFO empty interrupt status + io_ro_32 isr; + + _REG_(SSI_RISR_OFFSET) // SSI_RISR + // Raw interrupt status + // 0x00000020 [5] MSTIR (0) Multi-master contention raw interrupt status + // 0x00000010 [4] RXFIR (0) Receive FIFO full raw interrupt status + // 0x00000008 [3] RXOIR (0) Receive FIFO overflow raw interrupt status + // 0x00000004 [2] RXUIR (0) Receive FIFO underflow raw interrupt status + // 0x00000002 [1] TXOIR (0) Transmit FIFO overflow raw interrupt status + // 0x00000001 [0] TXEIR (0) Transmit FIFO empty raw interrupt status + io_ro_32 risr; + + _REG_(SSI_TXOICR_OFFSET) // SSI_TXOICR + // TX FIFO overflow interrupt clear + // 0x00000001 [0] TXOICR (0) Clear-on-read transmit FIFO overflow interrupt + io_ro_32 txoicr; + + _REG_(SSI_RXOICR_OFFSET) // SSI_RXOICR + // RX FIFO overflow interrupt clear + // 0x00000001 [0] RXOICR (0) Clear-on-read receive FIFO overflow interrupt + io_ro_32 rxoicr; + + _REG_(SSI_RXUICR_OFFSET) // SSI_RXUICR + // RX FIFO underflow interrupt clear + // 0x00000001 [0] RXUICR (0) Clear-on-read receive FIFO underflow interrupt + io_ro_32 rxuicr; + + _REG_(SSI_MSTICR_OFFSET) // SSI_MSTICR + // Multi-master interrupt clear + // 0x00000001 [0] MSTICR (0) Clear-on-read multi-master contention interrupt + io_ro_32 msticr; + + _REG_(SSI_ICR_OFFSET) // SSI_ICR + // Interrupt clear + // 0x00000001 [0] ICR (0) Clear-on-read all active interrupts + io_ro_32 icr; + + _REG_(SSI_DMACR_OFFSET) // SSI_DMACR + // DMA control + // 0x00000002 [1] TDMAE (0) Transmit DMA enable + // 0x00000001 [0] RDMAE (0) Receive DMA enable + io_rw_32 dmacr; + + _REG_(SSI_DMATDLR_OFFSET) // SSI_DMATDLR + // DMA TX data level + // 0x000000ff [7:0] DMATDL (0x00) Transmit data watermark level + io_rw_32 dmatdlr; + + _REG_(SSI_DMARDLR_OFFSET) // SSI_DMARDLR + // DMA RX data level + // 0x000000ff [7:0] DMARDL (0x00) Receive data watermark level (DMARDLR+1) + io_rw_32 dmardlr; + + _REG_(SSI_IDR_OFFSET) // SSI_IDR + // Identification register + // 0xffffffff [31:0] IDCODE (0x51535049) Peripheral dentification code + io_ro_32 idr; + + _REG_(SSI_SSI_VERSION_ID_OFFSET) // SSI_SSI_VERSION_ID + // Version ID + // 0xffffffff [31:0] SSI_COMP_VERSION (0x3430312a) SNPS component version (format X + io_ro_32 ssi_version_id; + + _REG_(SSI_DR0_OFFSET) // SSI_DR0 + // Data Register 0 (of 36) + // 0xffffffff [31:0] DR (0x00000000) First data register of 36 + io_rw_32 dr0; + + uint32_t _pad0[35]; + + _REG_(SSI_RX_SAMPLE_DLY_OFFSET) // SSI_RX_SAMPLE_DLY + // RX sample delay + // 0x000000ff [7:0] RSD (0x00) RXD sample delay (in SCLK cycles) + io_rw_32 rx_sample_dly; + + _REG_(SSI_SPI_CTRLR0_OFFSET) // SSI_SPI_CTRLR0 + // SPI control + // 0xff000000 [31:24] XIP_CMD (0x03) SPI Command to send in XIP mode (INST_L = 8-bit) or to... + // 0x00040000 [18] SPI_RXDS_EN (0) Read data strobe enable + // 0x00020000 [17] INST_DDR_EN (0) Instruction DDR transfer enable + // 0x00010000 [16] SPI_DDR_EN (0) SPI DDR transfer enable + // 0x0000f800 [15:11] WAIT_CYCLES (0x00) Wait cycles between control frame transmit and data... + // 0x00000300 [9:8] INST_L (0x0) Instruction length (0/4/8/16b) + // 0x0000003c [5:2] ADDR_L (0x0) Address length (0b-60b in 4b increments) + // 0x00000003 [1:0] TRANS_TYPE (0x0) Address and instruction transfer format + io_rw_32 spi_ctrlr0; + + _REG_(SSI_TXD_DRIVE_EDGE_OFFSET) // SSI_TXD_DRIVE_EDGE + // TX drive edge + // 0x000000ff [7:0] TDE (0x00) TXD drive edge + io_rw_32 txd_drive_edge; +} ssi_hw_t; + +#define ssi_hw ((ssi_hw_t *)XIP_SSI_BASE) +static_assert(sizeof (ssi_hw_t) == 0x00fc, ""); + +#endif // _HARDWARE_STRUCTS_SSI_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/syscfg.h b/lib/pico-sdk/rp2040/hardware/structs/syscfg.h new file mode 100644 index 000000000000..1d63dc75f39e --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/syscfg.h @@ -0,0 +1,84 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SYSCFG_H +#define _HARDWARE_STRUCTS_SYSCFG_H + +/** + * \file rp2040/syscfg.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/syscfg.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_syscfg +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SYSCFG_PROC0_NMI_MASK_OFFSET) // SYSCFG_PROC0_NMI_MASK + // Processor core 0 NMI source mask + // 0xffffffff [31:0] PROC0_NMI_MASK (0x00000000) Set a bit high to enable NMI from that IRQ + io_rw_32 proc0_nmi_mask; + + _REG_(SYSCFG_PROC1_NMI_MASK_OFFSET) // SYSCFG_PROC1_NMI_MASK + // Processor core 1 NMI source mask + // 0xffffffff [31:0] PROC1_NMI_MASK (0x00000000) Set a bit high to enable NMI from that IRQ + io_rw_32 proc1_nmi_mask; + + _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG + // Configuration for processors + // 0xf0000000 [31:28] PROC1_DAP_INSTID (0x1) Configure proc1 DAP instance ID + // 0x0f000000 [27:24] PROC0_DAP_INSTID (0x0) Configure proc0 DAP instance ID + // 0x00000002 [1] PROC1_HALTED (0) Indication that proc1 has halted + // 0x00000001 [0] PROC0_HALTED (0) Indication that proc0 has halted + io_rw_32 proc_config; + + _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS + // For each bit, if 1, bypass the input synchronizer between that GPIO + + // 0x3fffffff [29:0] PROC_IN_SYNC_BYPASS (0x00000000) + io_rw_32 proc_in_sync_bypass; + + _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI + // For each bit, if 1, bypass the input synchronizer between that GPIO + + // 0x0000003f [5:0] PROC_IN_SYNC_BYPASS_HI (0x00) + io_rw_32 proc_in_sync_bypass_hi; + + _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE + // Directly control the SWD debug port of either processor + // 0x00000080 [7] PROC1_ATTACH (0) Attach processor 1 debug port to syscfg controls, and... + // 0x00000040 [6] PROC1_SWCLK (1) Directly drive processor 1 SWCLK, if PROC1_ATTACH is set + // 0x00000020 [5] PROC1_SWDI (1) Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set + // 0x00000010 [4] PROC1_SWDO (-) Observe the value of processor 1 SWDIO output + // 0x00000008 [3] PROC0_ATTACH (0) Attach processor 0 debug port to syscfg controls, and... + // 0x00000004 [2] PROC0_SWCLK (1) Directly drive processor 0 SWCLK, if PROC0_ATTACH is set + // 0x00000002 [1] PROC0_SWDI (1) Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set + // 0x00000001 [0] PROC0_SWDO (-) Observe the value of processor 0 SWDIO output + io_rw_32 dbgforce; + + _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN + // Control power downs to memories + // 0x00000080 [7] ROM (0) + // 0x00000040 [6] USB (0) + // 0x00000020 [5] SRAM5 (0) + // 0x00000010 [4] SRAM4 (0) + // 0x00000008 [3] SRAM3 (0) + // 0x00000004 [2] SRAM2 (0) + // 0x00000002 [1] SRAM1 (0) + // 0x00000001 [0] SRAM0 (0) + io_rw_32 mempowerdown; +} syscfg_hw_t; + +#define syscfg_hw ((syscfg_hw_t *)SYSCFG_BASE) +static_assert(sizeof (syscfg_hw_t) == 0x001c, ""); + +#endif // _HARDWARE_STRUCTS_SYSCFG_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/sysinfo.h b/lib/pico-sdk/rp2040/hardware/structs/sysinfo.h new file mode 100644 index 000000000000..6c0502f6e7d8 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/sysinfo.h @@ -0,0 +1,52 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SYSINFO_H +#define _HARDWARE_STRUCTS_SYSINFO_H + +/** + * \file rp2040/sysinfo.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sysinfo.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sysinfo +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sysinfo.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SYSINFO_CHIP_ID_OFFSET) // SYSINFO_CHIP_ID + // JEDEC JEP-106 compliant chip identifier + // 0xf0000000 [31:28] REVISION (-) + // 0x0ffff000 [27:12] PART (-) + // 0x00000fff [11:0] MANUFACTURER (-) + io_ro_32 chip_id; + + _REG_(SYSINFO_PLATFORM_OFFSET) // SYSINFO_PLATFORM + // Platform register + // 0x00000002 [1] ASIC (0) + // 0x00000001 [0] FPGA (0) + io_ro_32 platform; + + uint32_t _pad0[2]; + + _REG_(SYSINFO_GITREF_RP2040_OFFSET) // SYSINFO_GITREF_RP2040 + // Git hash of the chip source + // 0xffffffff [31:0] GITREF_RP2040 (-) + io_ro_32 gitref_rp2040; +} sysinfo_hw_t; + +#define sysinfo_hw ((sysinfo_hw_t *)SYSINFO_BASE) +static_assert(sizeof (sysinfo_hw_t) == 0x0014, ""); + +#endif // _HARDWARE_STRUCTS_SYSINFO_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/systick.h b/lib/pico-sdk/rp2040/hardware/structs/systick.h new file mode 100644 index 000000000000..ee878719b1cf --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/systick.h @@ -0,0 +1,57 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SYSTICK_H +#define _HARDWARE_STRUCTS_SYSTICK_H + +/** + * \file rp2040/systick.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m0plus.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR + // SysTick Control and Status Register + // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read + // 0x00000004 [2] CLKSOURCE (0) SysTick clock source + // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + + // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + + io_rw_32 csr; + + _REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR + // SysTick Reload Value Register + // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... + io_rw_32 rvr; + + _REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR + // SysTick Current Value Register + // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter + io_rw_32 cvr; + + _REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB + // SysTick Calibration Value Register + // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... + // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... + // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... + io_ro_32 calib; +} systick_hw_t; + +#define systick_hw ((systick_hw_t *)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET)) +static_assert(sizeof (systick_hw_t) == 0x0010, ""); + +#endif // _HARDWARE_STRUCTS_SYSTICK_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/tbman.h b/lib/pico-sdk/rp2040/hardware/structs/tbman.h new file mode 100644 index 000000000000..78a5f3b22b7a --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/tbman.h @@ -0,0 +1,38 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TBMAN_H +#define _HARDWARE_STRUCTS_TBMAN_H + +/** + * \file rp2040/tbman.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/tbman.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_tbman +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/tbman.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(TBMAN_PLATFORM_OFFSET) // TBMAN_PLATFORM + // Indicates the type of platform in use + // 0x00000002 [1] FPGA (0) Indicates the platform is an FPGA + // 0x00000001 [0] ASIC (1) Indicates the platform is an ASIC + io_ro_32 platform; +} tbman_hw_t; + +#define tbman_hw ((tbman_hw_t *)TBMAN_BASE) +static_assert(sizeof (tbman_hw_t) == 0x0004, ""); + +#endif // _HARDWARE_STRUCTS_TBMAN_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/timer.h b/lib/pico-sdk/rp2040/hardware/structs/timer.h new file mode 100644 index 000000000000..1b059ad56c72 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/timer.h @@ -0,0 +1,116 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TIMER_H +#define _HARDWARE_STRUCTS_TIMER_H + +/** + * \file rp2040/timer.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/timer.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_timer +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/timer.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW + // Write to bits 63:32 of time + + // 0xffffffff [31:0] TIMEHW (0x00000000) + io_wo_32 timehw; + + _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW + // Write to bits 31:0 of time + + // 0xffffffff [31:0] TIMELW (0x00000000) + io_wo_32 timelw; + + _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR + // Read from bits 63:32 of time + + // 0xffffffff [31:0] TIMEHR (0x00000000) + io_ro_32 timehr; + + _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR + // Read from bits 31:0 of time + // 0xffffffff [31:0] TIMELR (0x00000000) + io_ro_32 timelr; + + // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes) + _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0 + // Arm alarm 0, and configure the time it will fire + // 0xffffffff [31:0] ALARM0 (0x00000000) + io_rw_32 alarm[4]; + + _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED + // Indicates the armed/disarmed status of each alarm + // 0x0000000f [3:0] ARMED (0x0) + io_rw_32 armed; + + _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH + // Raw read from bits 63:32 of time (no side effects) + // 0xffffffff [31:0] TIMERAWH (0x00000000) + io_ro_32 timerawh; + + _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL + // Raw read from bits 31:0 of time (no side effects) + // 0xffffffff [31:0] TIMERAWL (0x00000000) + io_ro_32 timerawl; + + _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE + // Set bits high to enable pause when the corresponding debug ports are active + // 0x00000004 [2] DBG1 (1) Pause when processor 1 is in debug mode + // 0x00000002 [1] DBG0 (1) Pause when processor 0 is in debug mode + io_rw_32 dbgpause; + + _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE + // Set high to pause the timer + // 0x00000001 [0] PAUSE (0) + io_rw_32 pause; + + _REG_(TIMER_INTR_OFFSET) // TIMER_INTR + // Raw Interrupts + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_rw_32 intr; + + _REG_(TIMER_INTE_OFFSET) // TIMER_INTE + // Interrupt Enable + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_rw_32 inte; + + _REG_(TIMER_INTF_OFFSET) // TIMER_INTF + // Interrupt Force + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_rw_32 intf; + + _REG_(TIMER_INTS_OFFSET) // TIMER_INTS + // Interrupt status after masking & forcing + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_ro_32 ints; +} timer_hw_t; + +#define timer_hw ((timer_hw_t *)TIMER_BASE) +static_assert(sizeof (timer_hw_t) == 0x0044, ""); + +#endif // _HARDWARE_STRUCTS_TIMER_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/uart.h b/lib/pico-sdk/rp2040/hardware/structs/uart.h new file mode 100644 index 000000000000..db0b4be40ee6 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/uart.h @@ -0,0 +1,182 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_UART_H +#define _HARDWARE_STRUCTS_UART_H + +/** + * \file rp2040/uart.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/uart.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_uart +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/uart.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(UART_UARTDR_OFFSET) // UART_UARTDR + // Data Register, UARTDR + // 0x00000800 [11] OE (-) Overrun error + // 0x00000400 [10] BE (-) Break error + // 0x00000200 [9] PE (-) Parity error + // 0x00000100 [8] FE (-) Framing error + // 0x000000ff [7:0] DATA (-) Receive (read) data character + io_rw_32 dr; + + _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR + // Receive Status Register/Error Clear Register, UARTRSR/UARTECR + // 0x00000008 [3] OE (0) Overrun error + // 0x00000004 [2] BE (0) Break error + // 0x00000002 [1] PE (0) Parity error + // 0x00000001 [0] FE (0) Framing error + io_rw_32 rsr; + + uint32_t _pad0[4]; + + _REG_(UART_UARTFR_OFFSET) // UART_UARTFR + // Flag Register, UARTFR + // 0x00000100 [8] RI (-) Ring indicator + // 0x00000080 [7] TXFE (1) Transmit FIFO empty + // 0x00000040 [6] RXFF (0) Receive FIFO full + // 0x00000020 [5] TXFF (0) Transmit FIFO full + // 0x00000010 [4] RXFE (1) Receive FIFO empty + // 0x00000008 [3] BUSY (0) UART busy + // 0x00000004 [2] DCD (-) Data carrier detect + // 0x00000002 [1] DSR (-) Data set ready + // 0x00000001 [0] CTS (-) Clear to send + io_ro_32 fr; + + uint32_t _pad1; + + _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR + // IrDA Low-Power Counter Register, UARTILPR + // 0x000000ff [7:0] ILPDVSR (0x00) 8-bit low-power divisor value + io_rw_32 ilpr; + + _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD + // Integer Baud Rate Register, UARTIBRD + // 0x0000ffff [15:0] BAUD_DIVINT (0x0000) The integer baud rate divisor + io_rw_32 ibrd; + + _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD + // Fractional Baud Rate Register, UARTFBRD + // 0x0000003f [5:0] BAUD_DIVFRAC (0x00) The fractional baud rate divisor + io_rw_32 fbrd; + + _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H + // Line Control Register, UARTLCR_H + // 0x00000080 [7] SPS (0) Stick parity select + // 0x00000060 [6:5] WLEN (0x0) Word length + // 0x00000010 [4] FEN (0) Enable FIFOs: 0 = FIFOs are disabled (character mode)... + // 0x00000008 [3] STP2 (0) Two stop bits select + // 0x00000004 [2] EPS (0) Even parity select + // 0x00000002 [1] PEN (0) Parity enable: 0 = parity is disabled and no parity bit... + // 0x00000001 [0] BRK (0) Send break + io_rw_32 lcr_h; + + _REG_(UART_UARTCR_OFFSET) // UART_UARTCR + // Control Register, UARTCR + // 0x00008000 [15] CTSEN (0) CTS hardware flow control enable + // 0x00004000 [14] RTSEN (0) RTS hardware flow control enable + // 0x00002000 [13] OUT2 (0) This bit is the complement of the UART Out2 (nUARTOut2)... + // 0x00001000 [12] OUT1 (0) This bit is the complement of the UART Out1 (nUARTOut1)... + // 0x00000800 [11] RTS (0) Request to send + // 0x00000400 [10] DTR (0) Data transmit ready + // 0x00000200 [9] RXE (1) Receive enable + // 0x00000100 [8] TXE (1) Transmit enable + // 0x00000080 [7] LBE (0) Loopback enable + // 0x00000004 [2] SIRLP (0) SIR low-power IrDA mode + // 0x00000002 [1] SIREN (0) SIR enable: 0 = IrDA SIR ENDEC is disabled + // 0x00000001 [0] UARTEN (0) UART enable: 0 = UART is disabled + io_rw_32 cr; + + _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS + // Interrupt FIFO Level Select Register, UARTIFLS + // 0x00000038 [5:3] RXIFLSEL (0x2) Receive interrupt FIFO level select + // 0x00000007 [2:0] TXIFLSEL (0x2) Transmit interrupt FIFO level select + io_rw_32 ifls; + + _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC + // Interrupt Mask Set/Clear Register, UARTIMSC + // 0x00000400 [10] OEIM (0) Overrun error interrupt mask + // 0x00000200 [9] BEIM (0) Break error interrupt mask + // 0x00000100 [8] PEIM (0) Parity error interrupt mask + // 0x00000080 [7] FEIM (0) Framing error interrupt mask + // 0x00000040 [6] RTIM (0) Receive timeout interrupt mask + // 0x00000020 [5] TXIM (0) Transmit interrupt mask + // 0x00000010 [4] RXIM (0) Receive interrupt mask + // 0x00000008 [3] DSRMIM (0) nUARTDSR modem interrupt mask + // 0x00000004 [2] DCDMIM (0) nUARTDCD modem interrupt mask + // 0x00000002 [1] CTSMIM (0) nUARTCTS modem interrupt mask + // 0x00000001 [0] RIMIM (0) nUARTRI modem interrupt mask + io_rw_32 imsc; + + _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS + // Raw Interrupt Status Register, UARTRIS + // 0x00000400 [10] OERIS (0) Overrun error interrupt status + // 0x00000200 [9] BERIS (0) Break error interrupt status + // 0x00000100 [8] PERIS (0) Parity error interrupt status + // 0x00000080 [7] FERIS (0) Framing error interrupt status + // 0x00000040 [6] RTRIS (0) Receive timeout interrupt status + // 0x00000020 [5] TXRIS (0) Transmit interrupt status + // 0x00000010 [4] RXRIS (0) Receive interrupt status + // 0x00000008 [3] DSRRMIS (-) nUARTDSR modem interrupt status + // 0x00000004 [2] DCDRMIS (-) nUARTDCD modem interrupt status + // 0x00000002 [1] CTSRMIS (-) nUARTCTS modem interrupt status + // 0x00000001 [0] RIRMIS (-) nUARTRI modem interrupt status + io_ro_32 ris; + + _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS + // Masked Interrupt Status Register, UARTMIS + // 0x00000400 [10] OEMIS (0) Overrun error masked interrupt status + // 0x00000200 [9] BEMIS (0) Break error masked interrupt status + // 0x00000100 [8] PEMIS (0) Parity error masked interrupt status + // 0x00000080 [7] FEMIS (0) Framing error masked interrupt status + // 0x00000040 [6] RTMIS (0) Receive timeout masked interrupt status + // 0x00000020 [5] TXMIS (0) Transmit masked interrupt status + // 0x00000010 [4] RXMIS (0) Receive masked interrupt status + // 0x00000008 [3] DSRMMIS (-) nUARTDSR modem masked interrupt status + // 0x00000004 [2] DCDMMIS (-) nUARTDCD modem masked interrupt status + // 0x00000002 [1] CTSMMIS (-) nUARTCTS modem masked interrupt status + // 0x00000001 [0] RIMMIS (-) nUARTRI modem masked interrupt status + io_ro_32 mis; + + _REG_(UART_UARTICR_OFFSET) // UART_UARTICR + // Interrupt Clear Register, UARTICR + // 0x00000400 [10] OEIC (-) Overrun error interrupt clear + // 0x00000200 [9] BEIC (-) Break error interrupt clear + // 0x00000100 [8] PEIC (-) Parity error interrupt clear + // 0x00000080 [7] FEIC (-) Framing error interrupt clear + // 0x00000040 [6] RTIC (-) Receive timeout interrupt clear + // 0x00000020 [5] TXIC (-) Transmit interrupt clear + // 0x00000010 [4] RXIC (-) Receive interrupt clear + // 0x00000008 [3] DSRMIC (-) nUARTDSR modem interrupt clear + // 0x00000004 [2] DCDMIC (-) nUARTDCD modem interrupt clear + // 0x00000002 [1] CTSMIC (-) nUARTCTS modem interrupt clear + // 0x00000001 [0] RIMIC (-) nUARTRI modem interrupt clear + io_rw_32 icr; + + _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR + // DMA Control Register, UARTDMACR + // 0x00000004 [2] DMAONERR (0) DMA on error + // 0x00000002 [1] TXDMAE (0) Transmit DMA enable + // 0x00000001 [0] RXDMAE (0) Receive DMA enable + io_rw_32 dmacr; +} uart_hw_t; + +#define uart0_hw ((uart_hw_t *)UART0_BASE) +#define uart1_hw ((uart_hw_t *)UART1_BASE) +static_assert(sizeof (uart_hw_t) == 0x004c, ""); + +#endif // _HARDWARE_STRUCTS_UART_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/usb.h b/lib/pico-sdk/rp2040/hardware/structs/usb.h new file mode 100644 index 000000000000..399845f1725e --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/usb.h @@ -0,0 +1,476 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_USB_H +#define _HARDWARE_STRUCTS_USB_H + +/** + * \file rp2040/usb.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/usb.h" +#include "hardware/structs/usb_dpram.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_usb +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP + // Device address and endpoint control + // 0x000f0000 [19:16] ENDPOINT (0x0) Device endpoint to send data to + // 0x0000007f [6:0] ADDRESS (0x00) In device mode, the address that the device should respond to + io_rw_32 dev_addr_ctrl; + + // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes) + _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1 + // Interrupt endpoint 1 + // 0x04000000 [26] INTEP_PREAMBLE (0) Interrupt EP requires preamble (is a low speed device on... + // 0x02000000 [25] INTEP_DIR (0) Direction of the interrupt endpoint + // 0x000f0000 [19:16] ENDPOINT (0x0) Endpoint number of the interrupt endpoint + // 0x0000007f [6:0] ADDRESS (0x00) Device address + io_rw_32 int_ep_addr_ctrl[15]; + + _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL + // Main control register + // 0x80000000 [31] SIM_TIMING (0) Reduced timings for simulation + // 0x00000002 [1] HOST_NDEVICE (0) Device mode = 0, Host mode = 1 + // 0x00000001 [0] CONTROLLER_EN (0) Enable controller + io_rw_32 main_ctrl; + + _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR + // Set the SOF (Start of Frame) frame number in the host controller + // 0x000007ff [10:0] COUNT (0x000) + io_wo_32 sof_wr; + + _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD + // Read the last SOF (Start of Frame) frame number seen + // 0x000007ff [10:0] COUNT (0x000) + io_ro_32 sof_rd; + + _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL + // SIE control register + // 0x80000000 [31] EP0_INT_STALL (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + // 0x40000000 [30] EP0_DOUBLE_BUF (0) Device: EP0 single buffered = 0, double buffered = 1 + // 0x20000000 [29] EP0_INT_1BUF (0) Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + // 0x10000000 [28] EP0_INT_2BUF (0) Device: Set bit in BUFF_STATUS for every 2 buffers... + // 0x08000000 [27] EP0_INT_NAK (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + // 0x04000000 [26] DIRECT_EN (0) Direct bus drive enable + // 0x02000000 [25] DIRECT_DP (0) Direct control of DP + // 0x01000000 [24] DIRECT_DM (0) Direct control of DM + // 0x00040000 [18] TRANSCEIVER_PD (0) Power down bus transceiver + // 0x00020000 [17] RPU_OPT (0) Device: Pull-up strength (0=1K2, 1=2k3) + // 0x00010000 [16] PULLUP_EN (0) Device: Enable pull up resistor + // 0x00008000 [15] PULLDOWN_EN (0) Host: Enable pull down resistors + // 0x00002000 [13] RESET_BUS (0) Host: Reset bus + // 0x00001000 [12] RESUME (0) Device: Remote wakeup + // 0x00000800 [11] VBUS_EN (0) Host: Enable VBUS + // 0x00000400 [10] KEEP_ALIVE_EN (0) Host: Enable keep alive packet (for low speed bus) + // 0x00000200 [9] SOF_EN (0) Host: Enable SOF generation (for full speed bus) + // 0x00000100 [8] SOF_SYNC (0) Host: Delay packet(s) until after SOF + // 0x00000040 [6] PREAMBLE_EN (0) Host: Preable enable for LS device on FS hub + // 0x00000010 [4] STOP_TRANS (0) Host: Stop transaction + // 0x00000008 [3] RECEIVE_DATA (0) Host: Receive transaction (IN to host) + // 0x00000004 [2] SEND_DATA (0) Host: Send transaction (OUT from host) + // 0x00000002 [1] SEND_SETUP (0) Host: Send Setup packet + // 0x00000001 [0] START_TRANS (0) Host: Start transaction + io_rw_32 sie_ctrl; + + _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS + // SIE status register + // 0x80000000 [31] DATA_SEQ_ERROR (0) Data Sequence Error + // 0x40000000 [30] ACK_REC (0) ACK received + // 0x20000000 [29] STALL_REC (0) Host: STALL received + // 0x10000000 [28] NAK_REC (0) Host: NAK received + // 0x08000000 [27] RX_TIMEOUT (0) RX timeout is raised by both the host and device if an... + // 0x04000000 [26] RX_OVERFLOW (0) RX overflow is raised by the Serial RX engine if the... + // 0x02000000 [25] BIT_STUFF_ERROR (0) Bit Stuff Error + // 0x01000000 [24] CRC_ERROR (0) CRC Error + // 0x00080000 [19] BUS_RESET (0) Device: bus reset received + // 0x00040000 [18] TRANS_COMPLETE (0) Transaction complete + // 0x00020000 [17] SETUP_REC (0) Device: Setup packet received + // 0x00010000 [16] CONNECTED (0) Device: connected + // 0x00000800 [11] RESUME (0) Host: Device has initiated a remote resume + // 0x00000400 [10] VBUS_OVER_CURR (0) VBUS over current detected + // 0x00000300 [9:8] SPEED (0x0) Host: device speed + // 0x00000010 [4] SUSPENDED (0) Bus in suspended state + // 0x0000000c [3:2] LINE_STATE (0x0) USB bus line state + // 0x00000001 [0] VBUS_DETECTED (0) Device: VBUS Detected + io_rw_32 sie_status; + + _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL + // interrupt endpoint control register + // 0x0000fffe [15:1] INT_EP_ACTIVE (0x0000) Host: Enable interrupt endpoint 1 => 15 + io_rw_32 int_ep_ctrl; + + _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS + // Buffer status register + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 buf_status; + + _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE + // Which of the double buffers should be handled + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_ro_32 buf_cpu_should_handle; + + _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT + // Device only: Can be set to ignore the buffer control register for this endpoint in case you... + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 abort; + + _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE + // Device only: Used in conjunction with `EP_ABORT` + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 abort_done; + + _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM + // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register... + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 ep_stall_arm; + + _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL + // Used by the host controller + // 0x03ff0000 [25:16] DELAY_FS (0x010) NAK polling interval for a full speed device + // 0x000003ff [9:0] DELAY_LS (0x010) NAK polling interval for a low speed device + io_rw_32 nak_poll; + + _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK + // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 ep_nak_stall_status; + + _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING + // Where to connect the USB controller + // 0x00000008 [3] SOFTCON (0) + // 0x00000004 [2] TO_DIGITAL_PAD (0) + // 0x00000002 [1] TO_EXTPHY (0) + // 0x00000001 [0] TO_PHY (0) + io_rw_32 muxing; + + _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR + // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO + // 0x00000020 [5] OVERCURR_DETECT_EN (0) + // 0x00000010 [4] OVERCURR_DETECT (0) + // 0x00000008 [3] VBUS_DETECT_OVERRIDE_EN (0) + // 0x00000004 [2] VBUS_DETECT (0) + // 0x00000002 [1] VBUS_EN_OVERRIDE_EN (0) + // 0x00000001 [0] VBUS_EN (0) + io_rw_32 pwr; + + _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT + // Note that most functions are driven directly from usb_fsls controller + // 0x00400000 [22] DM_OVV (0) Status bit from USB PHY + // 0x00200000 [21] DP_OVV (0) Status bit from USB PHY + // 0x00100000 [20] DM_OVCN (0) Status bit from USB PHY + // 0x00080000 [19] DP_OVCN (0) Status bit from USB PHY + // 0x00040000 [18] RX_DM (0) Status bit from USB PHY + + // 0x00020000 [17] RX_DP (0) Status bit from USB PHY + + // 0x00010000 [16] RX_DD (0) Status bit from USB PHY + + // 0x00008000 [15] TX_DIFFMODE (0) + // 0x00004000 [14] TX_FSSLEW (0) + // 0x00002000 [13] TX_PD (0) + // 0x00001000 [12] RX_PD (0) + // 0x00000800 [11] TX_DM (0) Value to drive to USB PHY when override enable is set... + // 0x00000400 [10] TX_DP (0) Value to drive to USB PHY when override enable is set... + // 0x00000200 [9] TX_DM_OE (0) Value to drive to USB PHY when override enable is set... + // 0x00000100 [8] TX_DP_OE (0) Value to drive to USB PHY when override enable is set... + // 0x00000040 [6] DM_PULLDN_EN (0) Value to drive to USB PHY when override enable is set... + // 0x00000020 [5] DM_PULLUP_EN (0) Value to drive to USB PHY when override enable is set... + // 0x00000010 [4] DM_PULLUP_HISEL (0) when dm_pullup_en is set high, this enables second resistor + // 0x00000004 [2] DP_PULLDN_EN (0) Value to drive to USB PHY when override enable is set... + // 0x00000002 [1] DP_PULLUP_EN (0) Value to drive to USB PHY when override enable is set... + // 0x00000001 [0] DP_PULLUP_HISEL (0) when dp_pullup_en is set high, this enables second resistor + io_rw_32 phy_direct; + + _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE + // 0x00008000 [15] TX_DIFFMODE_OVERRIDE_EN (0) + // 0x00001000 [12] DM_PULLUP_OVERRIDE_EN (0) + // 0x00000800 [11] TX_FSSLEW_OVERRIDE_EN (0) + // 0x00000400 [10] TX_PD_OVERRIDE_EN (0) + // 0x00000200 [9] RX_PD_OVERRIDE_EN (0) + // 0x00000100 [8] TX_DM_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000080 [7] TX_DP_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000040 [6] TX_DM_OE_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000020 [5] TX_DP_OE_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000010 [4] DM_PULLDN_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000008 [3] DP_PULLDN_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000004 [2] DP_PULLUP_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY + // 0x00000002 [1] DM_PULLUP_HISEL_OVERRIDE_EN (0) + // 0x00000001 [0] DP_PULLUP_HISEL_OVERRIDE_EN (0) + io_rw_32 phy_direct_override; + + _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM + // Note that most functions are driven directly from usb_fsls controller + // 0x00001f00 [12:8] DM_PULLDN_TRIM (0x1f) Value to drive to USB PHY + + // 0x0000001f [4:0] DP_PULLDN_TRIM (0x1f) Value to drive to USB PHY + + io_rw_32 phy_trim; + + uint32_t _pad0; + + _REG_(USB_INTR_OFFSET) // USB_INTR + // Raw Interrupts + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_ro_32 intr; + + _REG_(USB_INTE_OFFSET) // USB_INTE + // Interrupt Enable + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_rw_32 inte; + + _REG_(USB_INTF_OFFSET) // USB_INTF + // Interrupt Force + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_rw_32 intf; + + _REG_(USB_INTS_OFFSET) // USB_INTS + // Interrupt status after masking & forcing + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_ro_32 ints; +} usb_hw_t; + +#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE) +static_assert(sizeof (usb_hw_t) == 0x009c, ""); + +#endif // _HARDWARE_STRUCTS_USB_H + diff --git a/lib/rp2040/hardware/structs/usb.h b/lib/pico-sdk/rp2040/hardware/structs/usb_dpram.h similarity index 76% rename from lib/rp2040/hardware/structs/usb.h rename to lib/pico-sdk/rp2040/hardware/structs/usb_dpram.h index 0254e61dfc85..aaa4ec58b861 100644 --- a/lib/rp2040/hardware/structs/usb.h +++ b/lib/pico-sdk/rp2040/hardware/structs/usb_dpram.h @@ -1,15 +1,24 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. +/** + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef _HARDWARE_STRUCTS_USB_H -#define _HARDWARE_STRUCTS_USB_H +#ifndef _HARDWARE_STRUCTS_USB_DPRAM_H +#define _HARDWARE_STRUCTS_USB_DPRAM_H #include "hardware/address_mapped.h" #include "hardware/regs/usb.h" +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_usb +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + + // 0-15 #define USB_NUM_ENDPOINTS 16 @@ -39,10 +48,10 @@ #define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28) #define EP_CTRL_INTERRUPT_ON_NAK (1u << 16) #define EP_CTRL_INTERRUPT_ON_STALL (1u << 17) -#define EP_CTRL_BUFFER_TYPE_LSB 26 -#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16 +#define EP_CTRL_BUFFER_TYPE_LSB 26u +#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u -#define USB_DPRAM_SIZE 4096 +#define USB_DPRAM_SIZE 4096u // PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb // Allow user to claim some of the USB RAM for themselves @@ -111,39 +120,9 @@ typedef struct { static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, ""); static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, ""); -typedef struct { - io_rw_32 dev_addr_ctrl; - io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; - io_rw_32 main_ctrl; - io_rw_32 sof_rw; - io_ro_32 sof_rd; - io_rw_32 sie_ctrl; - io_rw_32 sie_status; - io_rw_32 int_ep_ctrl; - io_rw_32 buf_status; - io_rw_32 buf_cpu_should_handle; // for double buff - io_rw_32 abort; - io_rw_32 abort_done; - io_rw_32 ep_stall_arm; - io_rw_32 nak_poll; - io_rw_32 ep_nak_stall_status; - io_rw_32 muxing; - io_rw_32 pwr; - io_rw_32 phy_direct; - io_rw_32 phy_direct_override; - io_rw_32 phy_trim; - io_rw_32 linestate_tuning; - io_rw_32 intr; - io_rw_32 inte; - io_rw_32 intf; - io_rw_32 ints; -} usb_hw_t; - -check_hw_layout(usb_hw_t, ints, USB_INTS_OFFSET); - -#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE) - #define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE) #define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE) -#endif +static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, ""); + +#endif // _HARDWARE_STRUCTS_USB_DPRAM_H \ No newline at end of file diff --git a/lib/pico-sdk/rp2040/hardware/structs/vreg_and_chip_reset.h b/lib/pico-sdk/rp2040/hardware/structs/vreg_and_chip_reset.h new file mode 100644 index 000000000000..0f16a0a04630 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/vreg_and_chip_reset.h @@ -0,0 +1,54 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H +#define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H + +/** + * \file rp2040/vreg_and_chip_reset.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/vreg_and_chip_reset.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_vreg_and_chip_reset +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/vreg_and_chip_reset.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(VREG_AND_CHIP_RESET_VREG_OFFSET) // VREG_AND_CHIP_RESET_VREG + // Voltage regulator control and status + // 0x00001000 [12] ROK (0) regulation status + + // 0x000000f0 [7:4] VSEL (0xb) output voltage select + + // 0x00000002 [1] HIZ (0) high impedance mode select + + // 0x00000001 [0] EN (1) enable + + io_rw_32 vreg; + + _REG_(VREG_AND_CHIP_RESET_BOD_OFFSET) // VREG_AND_CHIP_RESET_BOD + // brown-out detection control + // 0x000000f0 [7:4] VSEL (0x9) threshold select + + // 0x00000001 [0] EN (1) enable + + io_rw_32 bod; + + _REG_(VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET) // VREG_AND_CHIP_RESET_CHIP_RESET + // Chip reset control and status + // 0x01000000 [24] PSM_RESTART_FLAG (0) This is set by psm_restart from the debugger + // 0x00100000 [20] HAD_PSM_RESTART (0) Last reset was from the debug port + // 0x00010000 [16] HAD_RUN (0) Last reset was from the RUN pin + // 0x00000100 [8] HAD_POR (0) Last reset was from the power-on reset or brown-out... + io_rw_32 chip_reset; +} vreg_and_chip_reset_hw_t; + +#define vreg_and_chip_reset_hw ((vreg_and_chip_reset_hw_t *)VREG_AND_CHIP_RESET_BASE) +static_assert(sizeof (vreg_and_chip_reset_hw_t) == 0x000c, ""); + +#endif // _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/watchdog.h b/lib/pico-sdk/rp2040/hardware/structs/watchdog.h new file mode 100644 index 000000000000..7667aa499d8a --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/watchdog.h @@ -0,0 +1,67 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_WATCHDOG_H +#define _HARDWARE_STRUCTS_WATCHDOG_H + +/** + * \file rp2040/watchdog.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/watchdog.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_watchdog +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL + // Watchdog control + // 0x80000000 [31] TRIGGER (0) Trigger a watchdog reset + // 0x40000000 [30] ENABLE (0) When not enabled the watchdog timer is paused + // 0x04000000 [26] PAUSE_DBG1 (1) Pause the watchdog timer when processor 1 is in debug mode + // 0x02000000 [25] PAUSE_DBG0 (1) Pause the watchdog timer when processor 0 is in debug mode + // 0x01000000 [24] PAUSE_JTAG (1) Pause the watchdog timer when JTAG is accessing the bus fabric + // 0x00ffffff [23:0] TIME (0x000000) Indicates the number of ticks / 2 (see errata RP2040-E1)... + io_rw_32 ctrl; + + _REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD + // Load the watchdog timer. + // 0x00ffffff [23:0] LOAD (0x000000) + io_wo_32 load; + + _REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON + // Logs the reason for the last reset. + // 0x00000002 [1] FORCE (0) + // 0x00000001 [0] TIMER (0) + io_ro_32 reason; + + // (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes) + _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0 + // Scratch register + // 0xffffffff [31:0] SCRATCH0 (0x00000000) + io_rw_32 scratch[8]; + + _REG_(WATCHDOG_TICK_OFFSET) // WATCHDOG_TICK + // Controls the tick generator + // 0x000ff800 [19:11] COUNT (-) Count down timer: the remaining number clk_tick cycles... + // 0x00000400 [10] RUNNING (-) Is the tick generator running? + // 0x00000200 [9] ENABLE (1) start / stop tick generation + // 0x000001ff [8:0] CYCLES (0x000) Total number of clk_tick cycles before the next tick + io_rw_32 tick; +} watchdog_hw_t; + +#define watchdog_hw ((watchdog_hw_t *)WATCHDOG_BASE) +static_assert(sizeof (watchdog_hw_t) == 0x0030, ""); + +#endif // _HARDWARE_STRUCTS_WATCHDOG_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/xip.h b/lib/pico-sdk/rp2040/hardware/structs/xip.h new file mode 100644 index 000000000000..332e8ccf10e8 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/xip.h @@ -0,0 +1,76 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XIP_H +#define _HARDWARE_STRUCTS_XIP_H + +/** + * \file rp2040/xip.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/xip.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xip.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(XIP_CTRL_OFFSET) // XIP_CTRL + // Cache control + // 0x00000008 [3] POWER_DOWN (0) When 1, the cache memories are powered down + // 0x00000002 [1] ERR_BADWRITE (1) When 1, writes to any alias other than 0x0 (caching,... + // 0x00000001 [0] EN (1) When 1, enable the cache + io_rw_32 ctrl; + + _REG_(XIP_FLUSH_OFFSET) // XIP_FLUSH + // Cache Flush control + // 0x00000001 [0] FLUSH (0) Write 1 to flush the cache + io_wo_32 flush; + + _REG_(XIP_STAT_OFFSET) // XIP_STAT + // Cache Status + // 0x00000004 [2] FIFO_FULL (0) When 1, indicates the XIP streaming FIFO is completely full + // 0x00000002 [1] FIFO_EMPTY (1) When 1, indicates the XIP streaming FIFO is completely empty + // 0x00000001 [0] FLUSH_READY (0) Reads as 0 while a cache flush is in progress, and 1 otherwise + io_ro_32 stat; + + _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT + // Cache Hit counter + // 0xffffffff [31:0] CTR_HIT (0x00000000) A 32 bit saturating counter that increments upon each... + io_rw_32 ctr_hit; + + _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC + // Cache Access counter + // 0xffffffff [31:0] CTR_ACC (0x00000000) A 32 bit saturating counter that increments upon each... + io_rw_32 ctr_acc; + + _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR + // FIFO stream address + // 0xfffffffc [31:2] STREAM_ADDR (0x00000000) The address of the next word to be streamed from flash... + io_rw_32 stream_addr; + + _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR + // FIFO stream control + // 0x003fffff [21:0] STREAM_CTR (0x000000) Write a nonzero value to start a streaming read + io_rw_32 stream_ctr; + + _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO + // FIFO stream data + // 0xffffffff [31:0] STREAM_FIFO (0x00000000) Streamed data is buffered here, for retrieval by the system DMA + io_ro_32 stream_fifo; +} xip_ctrl_hw_t; + +#define xip_ctrl_hw ((xip_ctrl_hw_t *)XIP_CTRL_BASE) +static_assert(sizeof (xip_ctrl_hw_t) == 0x0020, ""); + +#endif // _HARDWARE_STRUCTS_XIP_H + diff --git a/lib/pico-sdk/rp2040/hardware/structs/xip_ctrl.h b/lib/pico-sdk/rp2040/hardware/structs/xip_ctrl.h new file mode 100644 index 000000000000..c31569b60fd9 --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/xip_ctrl.h @@ -0,0 +1,11 @@ +/** + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/xip.h" +#define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS +#define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS +#define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS diff --git a/lib/pico-sdk/rp2040/hardware/structs/xosc.h b/lib/pico-sdk/rp2040/hardware/structs/xosc.h new file mode 100644 index 000000000000..ee5a234f6b1c --- /dev/null +++ b/lib/pico-sdk/rp2040/hardware/structs/xosc.h @@ -0,0 +1,66 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XOSC_H +#define _HARDWARE_STRUCTS_XOSC_H + +/** + * \file rp2040/xosc.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/xosc.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xosc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xosc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/// \tag::xosc_hw[] +typedef struct { + _REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL + // Crystal Oscillator Control + // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to DISABLE and the... + // 0x00000fff [11:0] FREQ_RANGE (-) Frequency range + io_rw_32 ctrl; + + _REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS + // Crystal Oscillator Status + // 0x80000000 [31] STABLE (0) Oscillator is running and stable + // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or... + // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and... + // 0x00000003 [1:0] FREQ_RANGE (-) The current frequency range setting, always reads 0 + io_rw_32 status; + + _REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT + // Crystal Oscillator pause control + // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the XOSC + + io_rw_32 dormant; + + _REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP + // Controls the startup delay + // 0x00100000 [20] X4 (-) Multiplies the startup_delay by 4 + // 0x00003fff [13:0] DELAY (-) in multiples of 256*xtal_period + io_rw_32 startup; + + uint32_t _pad0[3]; + + _REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT + // A down counter running at the XOSC frequency which counts to zero and stops. + // 0x000000ff [7:0] COUNT (0x00) + io_rw_32 count; +} xosc_hw_t; +/// \end::xosc_hw[] + +#define xosc_hw ((xosc_hw_t *)XOSC_BASE) +static_assert(sizeof (xosc_hw_t) == 0x0020, ""); + +#endif // _HARDWARE_STRUCTS_XOSC_H + diff --git a/lib/pico-sdk/rp2040/pico/asm_helper.S b/lib/pico-sdk/rp2040/pico/asm_helper.S new file mode 100644 index 000000000000..59c67db19ad3 --- /dev/null +++ b/lib/pico-sdk/rp2040/pico/asm_helper.S @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +//#include "pico.h" + +# note we don't do this by default in this file for backwards comaptibility with user code +# that may include this file, but not use unified syntax. Note that this macro does equivalent +# setup to the pico_default_asm macro for inline assembly in C code. +.macro pico_default_asm_setup +.syntax unified +.cpu cortex-m0plus +.thumb +.endm + +// do not put align in here as it is used mid function sometimes +.macro regular_func x +.global \x +.type \x,%function +.thumb_func +\x: +.endm + +.macro weak_func x +.weak \x +.type \x,%function +.thumb_func +\x: +.endm + +.macro regular_func_with_section x +.section .text.\x +regular_func \x +.endm + +// do not put align in here as it is used mid function sometimes +.macro wrapper_func x +regular_func WRAPPER_FUNC_NAME(\x) +.endm + +.macro weak_wrapper_func x +weak_func WRAPPER_FUNC_NAME(\x) +.endm + +# backwards compatibility +.macro __pre_init func, priority_string +.section .preinit_array.\priority_string +.p2align 2 +.word \func +.endm diff --git a/lib/pico-sdk/rp2350/cmsis_include/RP2350.h b/lib/pico-sdk/rp2350/cmsis_include/RP2350.h new file mode 100644 index 000000000000..94d0f178c086 --- /dev/null +++ b/lib/pico-sdk/rp2350/cmsis_include/RP2350.h @@ -0,0 +1,6070 @@ +/* + * Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause + * + * @file src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h + * @brief CMSIS HeaderFile + * @version 0.1 + * @date Thu Aug 8 04:04:02 2024 + * @note Generated by SVDConv V3.3.47 + * from File 'src/rp2_common/cmsis/../../rp2350/hardware_regs/RP2350.svd', + * last modified on Thu Aug 8 03:59:33 2024 + */ + + +/** @addtogroup Raspberry Pi + * @{ + */ + + +/** @addtogroup RP2350 + * @{ + */ + + +#ifndef RP2350_H +#define RP2350_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* =========================================== RP2350 Specific Interrupt Numbers =========================================== */ + TIMER0_IRQ_0_IRQn = 0, /*!< 0 TIMER0_IRQ_0 */ + TIMER0_IRQ_1_IRQn = 1, /*!< 1 TIMER0_IRQ_1 */ + TIMER0_IRQ_2_IRQn = 2, /*!< 2 TIMER0_IRQ_2 */ + TIMER0_IRQ_3_IRQn = 3, /*!< 3 TIMER0_IRQ_3 */ + TIMER1_IRQ_0_IRQn = 4, /*!< 4 TIMER1_IRQ_0 */ + TIMER1_IRQ_1_IRQn = 5, /*!< 5 TIMER1_IRQ_1 */ + TIMER1_IRQ_2_IRQn = 6, /*!< 6 TIMER1_IRQ_2 */ + TIMER1_IRQ_3_IRQn = 7, /*!< 7 TIMER1_IRQ_3 */ + PWM_IRQ_WRAP_0_IRQn = 8, /*!< 8 PWM_IRQ_WRAP_0 */ + PWM_IRQ_WRAP_1_IRQn = 9, /*!< 9 PWM_IRQ_WRAP_1 */ + DMA_IRQ_0_IRQn = 10, /*!< 10 DMA_IRQ_0 */ + DMA_IRQ_1_IRQn = 11, /*!< 11 DMA_IRQ_1 */ + DMA_IRQ_2_IRQn = 12, /*!< 12 DMA_IRQ_2 */ + DMA_IRQ_3_IRQn = 13, /*!< 13 DMA_IRQ_3 */ + USBCTRL_IRQ_IRQn = 14, /*!< 14 USBCTRL_IRQ */ + PIO0_IRQ_0_IRQn = 15, /*!< 15 PIO0_IRQ_0 */ + PIO0_IRQ_1_IRQn = 16, /*!< 16 PIO0_IRQ_1 */ + PIO1_IRQ_0_IRQn = 17, /*!< 17 PIO1_IRQ_0 */ + PIO1_IRQ_1_IRQn = 18, /*!< 18 PIO1_IRQ_1 */ + PIO2_IRQ_0_IRQn = 19, /*!< 19 PIO2_IRQ_0 */ + PIO2_IRQ_1_IRQn = 20, /*!< 20 PIO2_IRQ_1 */ + IO_IRQ_BANK0_IRQn = 21, /*!< 21 IO_IRQ_BANK0 */ + IO_IRQ_BANK0_NS_IRQn = 22, /*!< 22 IO_IRQ_BANK0_NS */ + IO_IRQ_QSPI_IRQn = 23, /*!< 23 IO_IRQ_QSPI */ + IO_IRQ_QSPI_NS_IRQn = 24, /*!< 24 IO_IRQ_QSPI_NS */ + SIO_IRQ_FIFO_IRQn = 25, /*!< 25 SIO_IRQ_FIFO */ + SIO_IRQ_BELL_IRQn = 26, /*!< 26 SIO_IRQ_BELL */ + SIO_IRQ_FIFO_NS_IRQn = 27, /*!< 27 SIO_IRQ_FIFO_NS */ + SIO_IRQ_BELL_NS_IRQn = 28, /*!< 28 SIO_IRQ_BELL_NS */ + SIO_IRQ_MTIMECMP_IRQn = 29, /*!< 29 SIO_IRQ_MTIMECMP */ + CLOCKS_IRQ_IRQn = 30, /*!< 30 CLOCKS_IRQ */ + SPI0_IRQ_IRQn = 31, /*!< 31 SPI0_IRQ */ + SPI1_IRQ_IRQn = 32, /*!< 32 SPI1_IRQ */ + UART0_IRQ_IRQn = 33, /*!< 33 UART0_IRQ */ + UART1_IRQ_IRQn = 34, /*!< 34 UART1_IRQ */ + ADC_IRQ_FIFO_IRQn = 35, /*!< 35 ADC_IRQ_FIFO */ + I2C0_IRQ_IRQn = 36, /*!< 36 I2C0_IRQ */ + I2C1_IRQ_IRQn = 37, /*!< 37 I2C1_IRQ */ + OTP_IRQ_IRQn = 38, /*!< 38 OTP_IRQ */ + TRNG_IRQ_IRQn = 39, /*!< 39 TRNG_IRQ */ + PLL_SYS_IRQ_IRQn = 42, /*!< 42 PLL_SYS_IRQ */ + PLL_USB_IRQ_IRQn = 43, /*!< 43 PLL_USB_IRQ */ + POWMAN_IRQ_POW_IRQn = 44, /*!< 44 POWMAN_IRQ_POW */ + POWMAN_IRQ_TIMER_IRQn = 45 /*!< 45 POWMAN_IRQ_TIMER */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ +#define __CM33_REV 0x0100U /*!< CM33 Core Revision */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ +#define __FPU_DP 0 /*!< Double Precision FPU */ +#define __DSP_PRESENT 1 /*!< DSP extension present */ +#define __SAUREGION_PRESENT 1 /*!< SAU region present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_RP2350.h" /*!< RP2350 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ RESETS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief RESETS (RESETS) + */ + +typedef struct { /*!< RESETS Structure */ + __IOM uint32_t RESET; /*!< RESET */ + __IOM uint32_t WDSEL; /*!< WDSEL */ + __IOM uint32_t RESET_DONE; /*!< RESET_DONE */ +} RESETS_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ PSM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PSM (PSM) + */ + +typedef struct { /*!< PSM Structure */ + __IOM uint32_t FRCE_ON; /*!< Force block out of reset (i.e. power it on) */ + __IOM uint32_t FRCE_OFF; /*!< Force into reset (i.e. power it off) */ + __IOM uint32_t WDSEL; /*!< Set to 1 if the watchdog should reset this */ + __IOM uint32_t DONE; /*!< Is the subsystem ready? */ +} PSM_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCKS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CLOCKS (CLOCKS) + */ + +typedef struct { /*!< CLOCKS Structure */ + __IOM uint32_t CLK_GPOUT0_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT0_DIV; /*!< CLK_GPOUT0_DIV */ + __IOM uint32_t CLK_GPOUT0_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_GPOUT1_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT1_DIV; /*!< CLK_GPOUT1_DIV */ + __IOM uint32_t CLK_GPOUT1_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_GPOUT2_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT2_DIV; /*!< CLK_GPOUT2_DIV */ + __IOM uint32_t CLK_GPOUT2_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_GPOUT3_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_GPOUT3_DIV; /*!< CLK_GPOUT3_DIV */ + __IOM uint32_t CLK_GPOUT3_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_REF_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_REF_DIV; /*!< CLK_REF_DIV */ + __IOM uint32_t CLK_REF_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_SYS_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_SYS_DIV; /*!< CLK_SYS_DIV */ + __IOM uint32_t CLK_SYS_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_PERI_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_PERI_DIV; /*!< CLK_PERI_DIV */ + __IOM uint32_t CLK_PERI_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_HSTX_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_HSTX_DIV; /*!< CLK_HSTX_DIV */ + __IOM uint32_t CLK_HSTX_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_USB_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_USB_DIV; /*!< CLK_USB_DIV */ + __IOM uint32_t CLK_USB_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t CLK_ADC_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ + __IOM uint32_t CLK_ADC_DIV; /*!< CLK_ADC_DIV */ + __IOM uint32_t CLK_ADC_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ + __IOM uint32_t DFTCLK_XOSC_CTRL; /*!< DFTCLK_XOSC_CTRL */ + __IOM uint32_t DFTCLK_ROSC_CTRL; /*!< DFTCLK_ROSC_CTRL */ + __IOM uint32_t DFTCLK_LPOSC_CTRL; /*!< DFTCLK_LPOSC_CTRL */ + __IOM uint32_t CLK_SYS_RESUS_CTRL; /*!< CLK_SYS_RESUS_CTRL */ + __IOM uint32_t CLK_SYS_RESUS_STATUS; /*!< CLK_SYS_RESUS_STATUS */ + __IOM uint32_t FC0_REF_KHZ; /*!< Reference clock frequency in kHz */ + __IOM uint32_t FC0_MIN_KHZ; /*!< Minimum pass frequency in kHz. This is optional. Set to 0 if + you are not using the pass/fail flags */ + __IOM uint32_t FC0_MAX_KHZ; /*!< Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff + if you are not using the pass/fail flags */ + __IOM uint32_t FC0_DELAY; /*!< Delays the start of frequency counting to allow the mux to settle + Delay is measured in multiples of the reference clock period */ + __IOM uint32_t FC0_INTERVAL; /*!< The test interval is 0.98us * 2**interval, but let's call it + 1us * 2**interval The default gives a test interval of + 250us */ + __IOM uint32_t FC0_SRC; /*!< Clock sent to frequency counter, set to 0 when not required + Writing to this register initiates the frequency count */ + __IOM uint32_t FC0_STATUS; /*!< Frequency counter status */ + __IOM uint32_t FC0_RESULT; /*!< Result of frequency measurement, only valid when status_done=1 */ + __IOM uint32_t WAKE_EN0; /*!< enable clock in wake mode */ + __IOM uint32_t WAKE_EN1; /*!< enable clock in wake mode */ + __IOM uint32_t SLEEP_EN0; /*!< enable clock in sleep mode */ + __IOM uint32_t SLEEP_EN1; /*!< enable clock in sleep mode */ + __IOM uint32_t ENABLED0; /*!< indicates the state of the clock enable */ + __IOM uint32_t ENABLED1; /*!< indicates the state of the clock enable */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} CLOCKS_Type; /*!< Size = 212 (0xd4) */ + + + +/* =========================================================================================================================== */ +/* ================ TICKS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief TICKS (TICKS) + */ + +typedef struct { /*!< TICKS Structure */ + __IOM uint32_t PROC0_CTRL; /*!< Controls the tick generator */ + __IOM uint32_t PROC0_CYCLES; /*!< PROC0_CYCLES */ + __IOM uint32_t PROC0_COUNT; /*!< PROC0_COUNT */ + __IOM uint32_t PROC1_CTRL; /*!< Controls the tick generator */ + __IOM uint32_t PROC1_CYCLES; /*!< PROC1_CYCLES */ + __IOM uint32_t PROC1_COUNT; /*!< PROC1_COUNT */ + __IOM uint32_t TIMER0_CTRL; /*!< Controls the tick generator */ + __IOM uint32_t TIMER0_CYCLES; /*!< TIMER0_CYCLES */ + __IOM uint32_t TIMER0_COUNT; /*!< TIMER0_COUNT */ + __IOM uint32_t TIMER1_CTRL; /*!< Controls the tick generator */ + __IOM uint32_t TIMER1_CYCLES; /*!< TIMER1_CYCLES */ + __IOM uint32_t TIMER1_COUNT; /*!< TIMER1_COUNT */ + __IOM uint32_t WATCHDOG_CTRL; /*!< Controls the tick generator */ + __IOM uint32_t WATCHDOG_CYCLES; /*!< WATCHDOG_CYCLES */ + __IOM uint32_t WATCHDOG_COUNT; /*!< WATCHDOG_COUNT */ + __IOM uint32_t RISCV_CTRL; /*!< Controls the tick generator */ + __IOM uint32_t RISCV_CYCLES; /*!< RISCV_CYCLES */ + __IOM uint32_t RISCV_COUNT; /*!< RISCV_COUNT */ +} TICKS_Type; /*!< Size = 72 (0x48) */ + + + +/* =========================================================================================================================== */ +/* ================ PADS_BANK0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PADS_BANK0 (PADS_BANK0) + */ + +typedef struct { /*!< PADS_BANK0 Structure */ + __IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */ + __IOM uint32_t GPIO0; /*!< GPIO0 */ + __IOM uint32_t GPIO1; /*!< GPIO1 */ + __IOM uint32_t GPIO2; /*!< GPIO2 */ + __IOM uint32_t GPIO3; /*!< GPIO3 */ + __IOM uint32_t GPIO4; /*!< GPIO4 */ + __IOM uint32_t GPIO5; /*!< GPIO5 */ + __IOM uint32_t GPIO6; /*!< GPIO6 */ + __IOM uint32_t GPIO7; /*!< GPIO7 */ + __IOM uint32_t GPIO8; /*!< GPIO8 */ + __IOM uint32_t GPIO9; /*!< GPIO9 */ + __IOM uint32_t GPIO10; /*!< GPIO10 */ + __IOM uint32_t GPIO11; /*!< GPIO11 */ + __IOM uint32_t GPIO12; /*!< GPIO12 */ + __IOM uint32_t GPIO13; /*!< GPIO13 */ + __IOM uint32_t GPIO14; /*!< GPIO14 */ + __IOM uint32_t GPIO15; /*!< GPIO15 */ + __IOM uint32_t GPIO16; /*!< GPIO16 */ + __IOM uint32_t GPIO17; /*!< GPIO17 */ + __IOM uint32_t GPIO18; /*!< GPIO18 */ + __IOM uint32_t GPIO19; /*!< GPIO19 */ + __IOM uint32_t GPIO20; /*!< GPIO20 */ + __IOM uint32_t GPIO21; /*!< GPIO21 */ + __IOM uint32_t GPIO22; /*!< GPIO22 */ + __IOM uint32_t GPIO23; /*!< GPIO23 */ + __IOM uint32_t GPIO24; /*!< GPIO24 */ + __IOM uint32_t GPIO25; /*!< GPIO25 */ + __IOM uint32_t GPIO26; /*!< GPIO26 */ + __IOM uint32_t GPIO27; /*!< GPIO27 */ + __IOM uint32_t GPIO28; /*!< GPIO28 */ + __IOM uint32_t GPIO29; /*!< GPIO29 */ + __IOM uint32_t GPIO30; /*!< GPIO30 */ + __IOM uint32_t GPIO31; /*!< GPIO31 */ + __IOM uint32_t GPIO32; /*!< GPIO32 */ + __IOM uint32_t GPIO33; /*!< GPIO33 */ + __IOM uint32_t GPIO34; /*!< GPIO34 */ + __IOM uint32_t GPIO35; /*!< GPIO35 */ + __IOM uint32_t GPIO36; /*!< GPIO36 */ + __IOM uint32_t GPIO37; /*!< GPIO37 */ + __IOM uint32_t GPIO38; /*!< GPIO38 */ + __IOM uint32_t GPIO39; /*!< GPIO39 */ + __IOM uint32_t GPIO40; /*!< GPIO40 */ + __IOM uint32_t GPIO41; /*!< GPIO41 */ + __IOM uint32_t GPIO42; /*!< GPIO42 */ + __IOM uint32_t GPIO43; /*!< GPIO43 */ + __IOM uint32_t GPIO44; /*!< GPIO44 */ + __IOM uint32_t GPIO45; /*!< GPIO45 */ + __IOM uint32_t GPIO46; /*!< GPIO46 */ + __IOM uint32_t GPIO47; /*!< GPIO47 */ + __IOM uint32_t SWCLK; /*!< SWCLK */ + __IOM uint32_t SWD; /*!< SWD */ +} PADS_BANK0_Type; /*!< Size = 204 (0xcc) */ + + + +/* =========================================================================================================================== */ +/* ================ PADS_QSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PADS_QSPI (PADS_QSPI) + */ + +typedef struct { /*!< PADS_QSPI Structure */ + __IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */ + __IOM uint32_t GPIO_QSPI_SCLK; /*!< GPIO_QSPI_SCLK */ + __IOM uint32_t GPIO_QSPI_SD0; /*!< GPIO_QSPI_SD0 */ + __IOM uint32_t GPIO_QSPI_SD1; /*!< GPIO_QSPI_SD1 */ + __IOM uint32_t GPIO_QSPI_SD2; /*!< GPIO_QSPI_SD2 */ + __IOM uint32_t GPIO_QSPI_SD3; /*!< GPIO_QSPI_SD3 */ + __IOM uint32_t GPIO_QSPI_SS; /*!< GPIO_QSPI_SS */ +} PADS_QSPI_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ IO_QSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief IO_QSPI (IO_QSPI) + */ + +typedef struct { /*!< IO_QSPI Structure */ + __IOM uint32_t USBPHY_DP_STATUS; /*!< USBPHY_DP_STATUS */ + __IOM uint32_t USBPHY_DP_CTRL; /*!< USBPHY_DP_CTRL */ + __IOM uint32_t USBPHY_DM_STATUS; /*!< USBPHY_DM_STATUS */ + __IOM uint32_t USBPHY_DM_CTRL; /*!< USBPHY_DM_CTRL */ + __IOM uint32_t GPIO_QSPI_SCLK_STATUS; /*!< GPIO_QSPI_SCLK_STATUS */ + __IOM uint32_t GPIO_QSPI_SCLK_CTRL; /*!< GPIO_QSPI_SCLK_CTRL */ + __IOM uint32_t GPIO_QSPI_SS_STATUS; /*!< GPIO_QSPI_SS_STATUS */ + __IOM uint32_t GPIO_QSPI_SS_CTRL; /*!< GPIO_QSPI_SS_CTRL */ + __IOM uint32_t GPIO_QSPI_SD0_STATUS; /*!< GPIO_QSPI_SD0_STATUS */ + __IOM uint32_t GPIO_QSPI_SD0_CTRL; /*!< GPIO_QSPI_SD0_CTRL */ + __IOM uint32_t GPIO_QSPI_SD1_STATUS; /*!< GPIO_QSPI_SD1_STATUS */ + __IOM uint32_t GPIO_QSPI_SD1_CTRL; /*!< GPIO_QSPI_SD1_CTRL */ + __IOM uint32_t GPIO_QSPI_SD2_STATUS; /*!< GPIO_QSPI_SD2_STATUS */ + __IOM uint32_t GPIO_QSPI_SD2_CTRL; /*!< GPIO_QSPI_SD2_CTRL */ + __IOM uint32_t GPIO_QSPI_SD3_STATUS; /*!< GPIO_QSPI_SD3_STATUS */ + __IOM uint32_t GPIO_QSPI_SD3_CTRL; /*!< GPIO_QSPI_SD3_CTRL */ + __IM uint32_t RESERVED[112]; + __IOM uint32_t IRQSUMMARY_PROC0_SECURE; /*!< IRQSUMMARY_PROC0_SECURE */ + __IOM uint32_t IRQSUMMARY_PROC0_NONSECURE; /*!< IRQSUMMARY_PROC0_NONSECURE */ + __IOM uint32_t IRQSUMMARY_PROC1_SECURE; /*!< IRQSUMMARY_PROC1_SECURE */ + __IOM uint32_t IRQSUMMARY_PROC1_NONSECURE; /*!< IRQSUMMARY_PROC1_NONSECURE */ + __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE */ + __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t PROC0_INTE; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTF; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTS; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC1_INTE; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTF; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTS; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t DORMANT_WAKE_INTE; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS; /*!< Interrupt status after masking & forcing for dormant_wake */ +} IO_QSPI_Type; /*!< Size = 576 (0x240) */ + + + +/* =========================================================================================================================== */ +/* ================ IO_BANK0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief IO_BANK0 (IO_BANK0) + */ + +typedef struct { /*!< IO_BANK0 Structure */ + __IOM uint32_t GPIO0_STATUS; /*!< GPIO0_STATUS */ + __IOM uint32_t GPIO0_CTRL; /*!< GPIO0_CTRL */ + __IOM uint32_t GPIO1_STATUS; /*!< GPIO1_STATUS */ + __IOM uint32_t GPIO1_CTRL; /*!< GPIO1_CTRL */ + __IOM uint32_t GPIO2_STATUS; /*!< GPIO2_STATUS */ + __IOM uint32_t GPIO2_CTRL; /*!< GPIO2_CTRL */ + __IOM uint32_t GPIO3_STATUS; /*!< GPIO3_STATUS */ + __IOM uint32_t GPIO3_CTRL; /*!< GPIO3_CTRL */ + __IOM uint32_t GPIO4_STATUS; /*!< GPIO4_STATUS */ + __IOM uint32_t GPIO4_CTRL; /*!< GPIO4_CTRL */ + __IOM uint32_t GPIO5_STATUS; /*!< GPIO5_STATUS */ + __IOM uint32_t GPIO5_CTRL; /*!< GPIO5_CTRL */ + __IOM uint32_t GPIO6_STATUS; /*!< GPIO6_STATUS */ + __IOM uint32_t GPIO6_CTRL; /*!< GPIO6_CTRL */ + __IOM uint32_t GPIO7_STATUS; /*!< GPIO7_STATUS */ + __IOM uint32_t GPIO7_CTRL; /*!< GPIO7_CTRL */ + __IOM uint32_t GPIO8_STATUS; /*!< GPIO8_STATUS */ + __IOM uint32_t GPIO8_CTRL; /*!< GPIO8_CTRL */ + __IOM uint32_t GPIO9_STATUS; /*!< GPIO9_STATUS */ + __IOM uint32_t GPIO9_CTRL; /*!< GPIO9_CTRL */ + __IOM uint32_t GPIO10_STATUS; /*!< GPIO10_STATUS */ + __IOM uint32_t GPIO10_CTRL; /*!< GPIO10_CTRL */ + __IOM uint32_t GPIO11_STATUS; /*!< GPIO11_STATUS */ + __IOM uint32_t GPIO11_CTRL; /*!< GPIO11_CTRL */ + __IOM uint32_t GPIO12_STATUS; /*!< GPIO12_STATUS */ + __IOM uint32_t GPIO12_CTRL; /*!< GPIO12_CTRL */ + __IOM uint32_t GPIO13_STATUS; /*!< GPIO13_STATUS */ + __IOM uint32_t GPIO13_CTRL; /*!< GPIO13_CTRL */ + __IOM uint32_t GPIO14_STATUS; /*!< GPIO14_STATUS */ + __IOM uint32_t GPIO14_CTRL; /*!< GPIO14_CTRL */ + __IOM uint32_t GPIO15_STATUS; /*!< GPIO15_STATUS */ + __IOM uint32_t GPIO15_CTRL; /*!< GPIO15_CTRL */ + __IOM uint32_t GPIO16_STATUS; /*!< GPIO16_STATUS */ + __IOM uint32_t GPIO16_CTRL; /*!< GPIO16_CTRL */ + __IOM uint32_t GPIO17_STATUS; /*!< GPIO17_STATUS */ + __IOM uint32_t GPIO17_CTRL; /*!< GPIO17_CTRL */ + __IOM uint32_t GPIO18_STATUS; /*!< GPIO18_STATUS */ + __IOM uint32_t GPIO18_CTRL; /*!< GPIO18_CTRL */ + __IOM uint32_t GPIO19_STATUS; /*!< GPIO19_STATUS */ + __IOM uint32_t GPIO19_CTRL; /*!< GPIO19_CTRL */ + __IOM uint32_t GPIO20_STATUS; /*!< GPIO20_STATUS */ + __IOM uint32_t GPIO20_CTRL; /*!< GPIO20_CTRL */ + __IOM uint32_t GPIO21_STATUS; /*!< GPIO21_STATUS */ + __IOM uint32_t GPIO21_CTRL; /*!< GPIO21_CTRL */ + __IOM uint32_t GPIO22_STATUS; /*!< GPIO22_STATUS */ + __IOM uint32_t GPIO22_CTRL; /*!< GPIO22_CTRL */ + __IOM uint32_t GPIO23_STATUS; /*!< GPIO23_STATUS */ + __IOM uint32_t GPIO23_CTRL; /*!< GPIO23_CTRL */ + __IOM uint32_t GPIO24_STATUS; /*!< GPIO24_STATUS */ + __IOM uint32_t GPIO24_CTRL; /*!< GPIO24_CTRL */ + __IOM uint32_t GPIO25_STATUS; /*!< GPIO25_STATUS */ + __IOM uint32_t GPIO25_CTRL; /*!< GPIO25_CTRL */ + __IOM uint32_t GPIO26_STATUS; /*!< GPIO26_STATUS */ + __IOM uint32_t GPIO26_CTRL; /*!< GPIO26_CTRL */ + __IOM uint32_t GPIO27_STATUS; /*!< GPIO27_STATUS */ + __IOM uint32_t GPIO27_CTRL; /*!< GPIO27_CTRL */ + __IOM uint32_t GPIO28_STATUS; /*!< GPIO28_STATUS */ + __IOM uint32_t GPIO28_CTRL; /*!< GPIO28_CTRL */ + __IOM uint32_t GPIO29_STATUS; /*!< GPIO29_STATUS */ + __IOM uint32_t GPIO29_CTRL; /*!< GPIO29_CTRL */ + __IOM uint32_t GPIO30_STATUS; /*!< GPIO30_STATUS */ + __IOM uint32_t GPIO30_CTRL; /*!< GPIO30_CTRL */ + __IOM uint32_t GPIO31_STATUS; /*!< GPIO31_STATUS */ + __IOM uint32_t GPIO31_CTRL; /*!< GPIO31_CTRL */ + __IOM uint32_t GPIO32_STATUS; /*!< GPIO32_STATUS */ + __IOM uint32_t GPIO32_CTRL; /*!< GPIO32_CTRL */ + __IOM uint32_t GPIO33_STATUS; /*!< GPIO33_STATUS */ + __IOM uint32_t GPIO33_CTRL; /*!< GPIO33_CTRL */ + __IOM uint32_t GPIO34_STATUS; /*!< GPIO34_STATUS */ + __IOM uint32_t GPIO34_CTRL; /*!< GPIO34_CTRL */ + __IOM uint32_t GPIO35_STATUS; /*!< GPIO35_STATUS */ + __IOM uint32_t GPIO35_CTRL; /*!< GPIO35_CTRL */ + __IOM uint32_t GPIO36_STATUS; /*!< GPIO36_STATUS */ + __IOM uint32_t GPIO36_CTRL; /*!< GPIO36_CTRL */ + __IOM uint32_t GPIO37_STATUS; /*!< GPIO37_STATUS */ + __IOM uint32_t GPIO37_CTRL; /*!< GPIO37_CTRL */ + __IOM uint32_t GPIO38_STATUS; /*!< GPIO38_STATUS */ + __IOM uint32_t GPIO38_CTRL; /*!< GPIO38_CTRL */ + __IOM uint32_t GPIO39_STATUS; /*!< GPIO39_STATUS */ + __IOM uint32_t GPIO39_CTRL; /*!< GPIO39_CTRL */ + __IOM uint32_t GPIO40_STATUS; /*!< GPIO40_STATUS */ + __IOM uint32_t GPIO40_CTRL; /*!< GPIO40_CTRL */ + __IOM uint32_t GPIO41_STATUS; /*!< GPIO41_STATUS */ + __IOM uint32_t GPIO41_CTRL; /*!< GPIO41_CTRL */ + __IOM uint32_t GPIO42_STATUS; /*!< GPIO42_STATUS */ + __IOM uint32_t GPIO42_CTRL; /*!< GPIO42_CTRL */ + __IOM uint32_t GPIO43_STATUS; /*!< GPIO43_STATUS */ + __IOM uint32_t GPIO43_CTRL; /*!< GPIO43_CTRL */ + __IOM uint32_t GPIO44_STATUS; /*!< GPIO44_STATUS */ + __IOM uint32_t GPIO44_CTRL; /*!< GPIO44_CTRL */ + __IOM uint32_t GPIO45_STATUS; /*!< GPIO45_STATUS */ + __IOM uint32_t GPIO45_CTRL; /*!< GPIO45_CTRL */ + __IOM uint32_t GPIO46_STATUS; /*!< GPIO46_STATUS */ + __IOM uint32_t GPIO46_CTRL; /*!< GPIO46_CTRL */ + __IOM uint32_t GPIO47_STATUS; /*!< GPIO47_STATUS */ + __IOM uint32_t GPIO47_CTRL; /*!< GPIO47_CTRL */ + __IM uint32_t RESERVED[32]; + __IOM uint32_t IRQSUMMARY_PROC0_SECURE0; /*!< IRQSUMMARY_PROC0_SECURE0 */ + __IOM uint32_t IRQSUMMARY_PROC0_SECURE1; /*!< IRQSUMMARY_PROC0_SECURE1 */ + __IOM uint32_t IRQSUMMARY_PROC0_NONSECURE0; /*!< IRQSUMMARY_PROC0_NONSECURE0 */ + __IOM uint32_t IRQSUMMARY_PROC0_NONSECURE1; /*!< IRQSUMMARY_PROC0_NONSECURE1 */ + __IOM uint32_t IRQSUMMARY_PROC1_SECURE0; /*!< IRQSUMMARY_PROC1_SECURE0 */ + __IOM uint32_t IRQSUMMARY_PROC1_SECURE1; /*!< IRQSUMMARY_PROC1_SECURE1 */ + __IOM uint32_t IRQSUMMARY_PROC1_NONSECURE0; /*!< IRQSUMMARY_PROC1_NONSECURE0 */ + __IOM uint32_t IRQSUMMARY_PROC1_NONSECURE1; /*!< IRQSUMMARY_PROC1_NONSECURE1 */ + __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE0;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE0 */ + __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE1;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE1 */ + __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE0;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE0 */ + __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE1;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE1 */ + __IOM uint32_t INTR0; /*!< Raw Interrupts */ + __IOM uint32_t INTR1; /*!< Raw Interrupts */ + __IOM uint32_t INTR2; /*!< Raw Interrupts */ + __IOM uint32_t INTR3; /*!< Raw Interrupts */ + __IOM uint32_t INTR4; /*!< Raw Interrupts */ + __IOM uint32_t INTR5; /*!< Raw Interrupts */ + __IOM uint32_t PROC0_INTE0; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE1; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE2; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE3; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE4; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE5; /*!< Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTF0; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF1; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF2; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF3; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF4; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF5; /*!< Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTS0; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS1; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS2; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS3; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS4; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC0_INTS5; /*!< Interrupt status after masking & forcing for proc0 */ + __IOM uint32_t PROC1_INTE0; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE1; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE2; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE3; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE4; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE5; /*!< Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTF0; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF1; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF2; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF3; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF4; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF5; /*!< Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTS0; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS1; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS2; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS3; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS4; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t PROC1_INTS5; /*!< Interrupt status after masking & forcing for proc1 */ + __IOM uint32_t DORMANT_WAKE_INTE0; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE1; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE2; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE3; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE4; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE5; /*!< Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF0; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF1; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF2; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF3; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF4; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF5; /*!< Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS0; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS1; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS2; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS3; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS4; /*!< Interrupt status after masking & forcing for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS5; /*!< Interrupt status after masking & forcing for dormant_wake */ +} IO_BANK0_Type; /*!< Size = 800 (0x320) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSINFO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SYSINFO (SYSINFO) + */ + +typedef struct { /*!< SYSINFO Structure */ + __IOM uint32_t CHIP_ID; /*!< JEDEC JEP-106 compliant chip identifier. */ + __IOM uint32_t PACKAGE_SEL; /*!< PACKAGE_SEL */ + __IOM uint32_t PLATFORM; /*!< Platform register. Allows software to know what environment + it is running in during pre-production development. Post-production, + the PLATFORM is always ASIC, non-SIM. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t GITREF_RP2350; /*!< Git hash of the chip source. Used to identify chip version. */ +} SYSINFO_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ SHA256 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SHA-256 hash function implementation (SHA256) + */ + +typedef struct { /*!< SHA256 Structure */ + __IOM uint32_t CSR; /*!< Control and status register */ + __IOM uint32_t WDATA; /*!< Write data register */ + __IOM uint32_t SUM0; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + __IOM uint32_t SUM1; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + __IOM uint32_t SUM2; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + __IOM uint32_t SUM3; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + __IOM uint32_t SUM4; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + __IOM uint32_t SUM5; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + __IOM uint32_t SUM6; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ + __IOM uint32_t SUM7; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD + is 0. */ +} SHA256_Type; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ HSTX_FIFO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FIFO status and write access for HSTX (HSTX_FIFO) + */ + +typedef struct { /*!< HSTX_FIFO Structure */ + __IOM uint32_t STAT; /*!< FIFO status */ + __IOM uint32_t FIFO; /*!< Write access to FIFO */ +} HSTX_FIFO_Type; /*!< Size = 8 (0x8) */ + + + +/* =========================================================================================================================== */ +/* ================ HSTX_CTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. (HSTX_CTRL) + */ + +typedef struct { /*!< HSTX_CTRL Structure */ + __IOM uint32_t CSR; /*!< CSR */ + __IOM uint32_t BIT0; /*!< Data control register for output bit 0 */ + __IOM uint32_t BIT1; /*!< Data control register for output bit 1 */ + __IOM uint32_t BIT2; /*!< Data control register for output bit 2 */ + __IOM uint32_t BIT3; /*!< Data control register for output bit 3 */ + __IOM uint32_t BIT4; /*!< Data control register for output bit 4 */ + __IOM uint32_t BIT5; /*!< Data control register for output bit 5 */ + __IOM uint32_t BIT6; /*!< Data control register for output bit 6 */ + __IOM uint32_t BIT7; /*!< Data control register for output bit 7 */ + __IOM uint32_t EXPAND_SHIFT; /*!< Configure the optional shifter inside the command expander */ + __IOM uint32_t EXPAND_TMDS; /*!< Configure the optional TMDS encoder inside the command expander */ +} HSTX_CTRL_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ EPPB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Cortex-M33 EPPB vendor register block for RP2350 (EPPB) + */ + +typedef struct { /*!< EPPB Structure */ + __IOM uint32_t NMI_MASK0; /*!< NMI mask for IRQs 0 through 31. This register is core-local, + and is reset by a processor warm reset. */ + __IOM uint32_t NMI_MASK1; /*!< NMI mask for IRQs 0 though 51. This register is core-local, + and is reset by a processor warm reset. */ + __IOM uint32_t SLEEPCTRL; /*!< Nonstandard sleep control register */ +} EPPB_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ PPB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief TEAL registers accessible through the debug interface (PPB) + */ + +typedef struct { /*!< PPB Structure */ + __IOM uint32_t ITM_STIM0; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM1; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM2; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM3; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM4; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM5; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM6; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM7; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM8; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM9; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM10; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM11; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM12; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM13; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM14; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM15; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM16; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM17; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM18; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM19; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM20; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM21; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM22; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM23; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM24; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM25; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM26; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM27; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM28; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM29; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM30; /*!< Provides the interface for generating Instrumentation packets */ + __IOM uint32_t ITM_STIM31; /*!< Provides the interface for generating Instrumentation packets */ + __IM uint32_t RESERVED[864]; + __IOM uint32_t ITM_TER0; /*!< Provide an individual enable bit for each ITM_STIM register */ + __IM uint32_t RESERVED1[15]; + __IOM uint32_t ITM_TPR; /*!< Controls which stimulus ports can be accessed by unprivileged + code */ + __IM uint32_t RESERVED2[15]; + __IOM uint32_t ITM_TCR; /*!< Configures and controls transfers through the ITM interface */ + __IM uint32_t RESERVED3[27]; + __IOM uint32_t INT_ATREADY; /*!< Integration Mode: Read ATB Ready */ + __IM uint32_t RESERVED4; + __IOM uint32_t INT_ATVALID; /*!< Integration Mode: Write ATB Valid */ + __IM uint32_t RESERVED5; + __IOM uint32_t ITM_ITCTRL; /*!< Integration Mode Control Register */ + __IM uint32_t RESERVED6[46]; + __IOM uint32_t ITM_DEVARCH; /*!< Provides CoreSight discovery information for the ITM */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t ITM_DEVTYPE; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR4; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR5; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR6; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR7; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR0; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR1; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR2; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_PIDR3; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_CIDR0; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_CIDR1; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_CIDR2; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t ITM_CIDR3; /*!< Provides CoreSight discovery information for the ITM */ + __IOM uint32_t DWT_CTRL; /*!< Provides configuration and status information for the DWT unit, + and used to control features of the unit */ + __IOM uint32_t DWT_CYCCNT; /*!< Shows or sets the value of the processor cycle counter, CYCCNT */ + __IM uint32_t RESERVED8; + __IOM uint32_t DWT_EXCCNT; /*!< Counts the total cycles spent in exception processing */ + __IM uint32_t RESERVED9; + __IOM uint32_t DWT_LSUCNT; /*!< Increments on the additional cycles required to execute all + load or store instructions */ + __IOM uint32_t DWT_FOLDCNT; /*!< Increments on the additional cycles required to execute all + load or store instructions */ + __IM uint32_t RESERVED10; + __IOM uint32_t DWT_COMP0; /*!< Provides a reference value for use by watchpoint comparator + 0 */ + __IM uint32_t RESERVED11; + __IOM uint32_t DWT_FUNCTION0; /*!< Controls the operation of watchpoint comparator 0 */ + __IM uint32_t RESERVED12; + __IOM uint32_t DWT_COMP1; /*!< Provides a reference value for use by watchpoint comparator + 1 */ + __IM uint32_t RESERVED13; + __IOM uint32_t DWT_FUNCTION1; /*!< Controls the operation of watchpoint comparator 1 */ + __IM uint32_t RESERVED14; + __IOM uint32_t DWT_COMP2; /*!< Provides a reference value for use by watchpoint comparator + 2 */ + __IM uint32_t RESERVED15; + __IOM uint32_t DWT_FUNCTION2; /*!< Controls the operation of watchpoint comparator 2 */ + __IM uint32_t RESERVED16; + __IOM uint32_t DWT_COMP3; /*!< Provides a reference value for use by watchpoint comparator + 3 */ + __IM uint32_t RESERVED17; + __IOM uint32_t DWT_FUNCTION3; /*!< Controls the operation of watchpoint comparator 3 */ + __IM uint32_t RESERVED18[984]; + __IOM uint32_t DWT_DEVARCH; /*!< Provides CoreSight discovery information for the DWT */ + __IM uint32_t RESERVED19[3]; + __IOM uint32_t DWT_DEVTYPE; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR4; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR5; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR6; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR7; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR0; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR1; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR2; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_PIDR3; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_CIDR0; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_CIDR1; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_CIDR2; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t DWT_CIDR3; /*!< Provides CoreSight discovery information for the DWT */ + __IOM uint32_t FP_CTRL; /*!< Provides FPB implementation information, and the global enable + for the FPB unit */ + __IOM uint32_t FP_REMAP; /*!< Indicates whether the implementation supports Flash Patch remap + and, if it does, holds the target address for remap */ + __IOM uint32_t FP_COMP0; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IOM uint32_t FP_COMP1; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IOM uint32_t FP_COMP2; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IOM uint32_t FP_COMP3; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IOM uint32_t FP_COMP4; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IOM uint32_t FP_COMP5; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IOM uint32_t FP_COMP6; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IOM uint32_t FP_COMP7; /*!< Holds an address for comparison. The effect of the match depends + on the configuration of the FPB and whether the comparator + is an instruction address comparator or a literal address + comparator */ + __IM uint32_t RESERVED20[997]; + __IOM uint32_t FP_DEVARCH; /*!< Provides CoreSight discovery information for the FPB */ + __IM uint32_t RESERVED21[3]; + __IOM uint32_t FP_DEVTYPE; /*!< Provides CoreSight discovery information for the FPB */ + __IOM uint32_t FP_PIDR4; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_PIDR5; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_PIDR6; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_PIDR7; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_PIDR0; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_PIDR1; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_PIDR2; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_PIDR3; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_CIDR0; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_CIDR1; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_CIDR2; /*!< Provides CoreSight discovery information for the FP */ + __IOM uint32_t FP_CIDR3; /*!< Provides CoreSight discovery information for the FP */ + __IM uint32_t RESERVED22[11265]; + __IOM uint32_t ICTR; /*!< Provides information about the interrupt controller */ + __IOM uint32_t ACTLR; /*!< Provides IMPLEMENTATION DEFINED configuration and control options */ + __IM uint32_t RESERVED23; + __IOM uint32_t SYST_CSR; /*!< Use the SysTick Control and Status Register to enable the SysTick + features. */ + __IOM uint32_t SYST_RVR; /*!< Use the SysTick Reload Value Register to specify the start value + to load into the current value register when the counter + reaches 0. It can be any value between 0 and 0x00FFFFFF. + A start value of 0 is possible, but has no effect because + the SysTick interrupt and COUNTFLAG are activated when + counting from 1 to 0. The reset value of this register + is UNKNOWN. To generate a multi-shot timer with a period + of N processor clock cycles, use a RELOAD value of N-1. + For example, if the SysTick interrupt is required every + 100 clock pulses, set RELOAD to 99. */ + __IOM uint32_t SYST_CVR; /*!< Use the SysTick Current Value Register to find the current value + in the register. The reset value of this register is UNKNOWN. */ + __IOM uint32_t SYST_CALIB; /*!< Use the SysTick Calibration Value Register to enable software + to scale to any required speed using divide and multiply. */ + __IM uint32_t RESERVED24[56]; + __IOM uint32_t NVIC_ISER0; /*!< Enables or reads the enabled state of each group of 32 interrupts */ + __IOM uint32_t NVIC_ISER1; /*!< Enables or reads the enabled state of each group of 32 interrupts */ + __IM uint32_t RESERVED25[30]; + __IOM uint32_t NVIC_ICER0; /*!< Clears or reads the enabled state of each group of 32 interrupts */ + __IOM uint32_t NVIC_ICER1; /*!< Clears or reads the enabled state of each group of 32 interrupts */ + __IM uint32_t RESERVED26[30]; + __IOM uint32_t NVIC_ISPR0; /*!< Enables or reads the pending state of each group of 32 interrupts */ + __IOM uint32_t NVIC_ISPR1; /*!< Enables or reads the pending state of each group of 32 interrupts */ + __IM uint32_t RESERVED27[30]; + __IOM uint32_t NVIC_ICPR0; /*!< Clears or reads the pending state of each group of 32 interrupts */ + __IOM uint32_t NVIC_ICPR1; /*!< Clears or reads the pending state of each group of 32 interrupts */ + __IM uint32_t RESERVED28[30]; + __IOM uint32_t NVIC_IABR0; /*!< For each group of 32 interrupts, shows the active state of each + interrupt */ + __IOM uint32_t NVIC_IABR1; /*!< For each group of 32 interrupts, shows the active state of each + interrupt */ + __IM uint32_t RESERVED29[30]; + __IOM uint32_t NVIC_ITNS0; /*!< For each group of 32 interrupts, determines whether each interrupt + targets Non-secure or Secure state */ + __IOM uint32_t NVIC_ITNS1; /*!< For each group of 32 interrupts, determines whether each interrupt + targets Non-secure or Secure state */ + __IM uint32_t RESERVED30[30]; + __IOM uint32_t NVIC_IPR0; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR1; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR2; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR3; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR4; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR5; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR6; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR7; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR8; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR9; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR10; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR11; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR12; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR13; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR14; /*!< Sets or reads interrupt priorities */ + __IOM uint32_t NVIC_IPR15; /*!< Sets or reads interrupt priorities */ + __IM uint32_t RESERVED31[560]; + __IOM uint32_t CPUID; /*!< Provides identification information for the PE, including an + implementer code for the device and a device ID number */ + __IOM uint32_t ICSR; /*!< Controls and provides status information for NMI, PendSV, SysTick + and interrupts */ + __IOM uint32_t VTOR; /*!< The VTOR indicates the offset of the vector table base address + from memory address 0x00000000. */ + __IOM uint32_t AIRCR; /*!< Use the Application Interrupt and Reset Control Register to: + determine data endianness, clear all active state information + from debug halt mode, request a system reset. */ + __IOM uint32_t SCR; /*!< System Control Register. Use the System Control Register for + power-management functions: signal to the system when the + processor can enter a low power state, control how the + processor enters and exits low power states. */ + __IOM uint32_t CCR; /*!< Sets or returns configuration and control data */ + __IOM uint32_t SHPR1; /*!< Sets or returns priority for system handlers 4 - 7 */ + __IOM uint32_t SHPR2; /*!< Sets or returns priority for system handlers 8 - 11 */ + __IOM uint32_t SHPR3; /*!< Sets or returns priority for system handlers 12 - 15 */ + __IOM uint32_t SHCSR; /*!< Provides access to the active and pending status of system exceptions */ + __IOM uint32_t CFSR; /*!< Contains the three Configurable Fault Status Registers. 31:16 + UFSR: Provides information on UsageFault exceptions 15:8 + BFSR: Provides information on BusFault exceptions 7:0 MMFSR: + Provides information on MemManage exceptions */ + __IOM uint32_t HFSR; /*!< Shows the cause of any HardFaults */ + __IOM uint32_t DFSR; /*!< Shows which debug event occurred */ + __IOM uint32_t MMFAR; /*!< Shows the address of the memory location that caused an MPU + fault */ + __IOM uint32_t BFAR; /*!< Shows the address associated with a precise data access BusFault */ + __IM uint32_t RESERVED32; + __IOM uint32_t ID_PFR0; /*!< Gives top-level information about the instruction set supported + by the PE */ + __IOM uint32_t ID_PFR1; /*!< Gives information about the programmers' model and Extensions + support */ + __IOM uint32_t ID_DFR0; /*!< Provides top level information about the debug system */ + __IOM uint32_t ID_AFR0; /*!< Provides information about the IMPLEMENTATION DEFINED features + of the PE */ + __IOM uint32_t ID_MMFR0; /*!< Provides information about the implemented memory model and + memory management support */ + __IOM uint32_t ID_MMFR1; /*!< Provides information about the implemented memory model and + memory management support */ + __IOM uint32_t ID_MMFR2; /*!< Provides information about the implemented memory model and + memory management support */ + __IOM uint32_t ID_MMFR3; /*!< Provides information about the implemented memory model and + memory management support */ + __IOM uint32_t ID_ISAR0; /*!< Provides information about the instruction set implemented by + the PE */ + __IOM uint32_t ID_ISAR1; /*!< Provides information about the instruction set implemented by + the PE */ + __IOM uint32_t ID_ISAR2; /*!< Provides information about the instruction set implemented by + the PE */ + __IOM uint32_t ID_ISAR3; /*!< Provides information about the instruction set implemented by + the PE */ + __IOM uint32_t ID_ISAR4; /*!< Provides information about the instruction set implemented by + the PE */ + __IOM uint32_t ID_ISAR5; /*!< Provides information about the instruction set implemented by + the PE */ + __IM uint32_t RESERVED33; + __IOM uint32_t CTR; /*!< Provides information about the architecture of the caches. CTR + is RES0 if CLIDR is zero. */ + __IM uint32_t RESERVED34[2]; + __IOM uint32_t CPACR; /*!< Specifies the access privileges for coprocessors and the FP + Extension */ + __IOM uint32_t NSACR; /*!< Defines the Non-secure access permissions for both the FP Extension + and coprocessors CP0 to CP7 */ + __IOM uint32_t MPU_TYPE; /*!< The MPU Type Register indicates how many regions the MPU `FTSSS + supports */ + __IOM uint32_t MPU_CTRL; /*!< Enables the MPU and, when the MPU is enabled, controls whether + the default memory map is enabled as a background region + for privileged accesses, and whether the MPU is enabled + for HardFaults, NMIs, and exception handlers when FAULTMASK + is set to 1 */ + __IOM uint32_t MPU_RNR; /*!< Selects the region currently accessed by MPU_RBAR and MPU_RLAR */ + __IOM uint32_t MPU_RBAR; /*!< Provides indirect read and write access to the base address + of the currently selected MPU region `FTSSS */ + __IOM uint32_t MPU_RLAR; /*!< Provides indirect read and write access to the limit address + of the currently selected MPU region `FTSSS */ + __IOM uint32_t MPU_RBAR_A1; /*!< Provides indirect read and write access to the base address + of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS */ + __IOM uint32_t MPU_RLAR_A1; /*!< Provides indirect read and write access to the limit address + of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) + `FTSSS */ + __IOM uint32_t MPU_RBAR_A2; /*!< Provides indirect read and write access to the base address + of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS */ + __IOM uint32_t MPU_RLAR_A2; /*!< Provides indirect read and write access to the limit address + of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) + `FTSSS */ + __IOM uint32_t MPU_RBAR_A3; /*!< Provides indirect read and write access to the base address + of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS */ + __IOM uint32_t MPU_RLAR_A3; /*!< Provides indirect read and write access to the limit address + of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) + `FTSSS */ + __IM uint32_t RESERVED35; + __IOM uint32_t MPU_MAIR0; /*!< Along with MPU_MAIR1, provides the memory attribute encodings + corresponding to the AttrIndex values */ + __IOM uint32_t MPU_MAIR1; /*!< Along with MPU_MAIR0, provides the memory attribute encodings + corresponding to the AttrIndex values */ + __IM uint32_t RESERVED36[2]; + __IOM uint32_t SAU_CTRL; /*!< Allows enabling of the Security Attribution Unit */ + __IOM uint32_t SAU_TYPE; /*!< Indicates the number of regions implemented by the Security + Attribution Unit */ + __IOM uint32_t SAU_RNR; /*!< Selects the region currently accessed by SAU_RBAR and SAU_RLAR */ + __IOM uint32_t SAU_RBAR; /*!< Provides indirect read and write access to the base address + of the currently selected SAU region */ + __IOM uint32_t SAU_RLAR; /*!< Provides indirect read and write access to the limit address + of the currently selected SAU region */ + __IOM uint32_t SFSR; /*!< Provides information about any security related faults */ + __IOM uint32_t SFAR; /*!< Shows the address of the memory location that caused a Security + violation */ + __IM uint32_t RESERVED37; + __IOM uint32_t DHCSR; /*!< Controls halting debug */ + __IOM uint32_t DCRSR; /*!< With the DCRDR, provides debug access to the general-purpose + registers, special-purpose registers, and the FP extension + registers. A write to the DCRSR specifies the register + to transfer, whether the transfer is a read or write, and + starts the transfer */ + __IOM uint32_t DCRDR; /*!< With the DCRSR, provides debug access to the general-purpose + registers, special-purpose registers, and the FP Extension + registers. If the Main Extension is implemented, it can + also be used for message passing between an external debugger + and a debug agent running on the PE */ + __IOM uint32_t DEMCR; /*!< Manages vector catch behavior and DebugMonitor handling when + debugging */ + __IM uint32_t RESERVED38[2]; + __IOM uint32_t DSCSR; /*!< Provides control and status information for Secure debug */ + __IM uint32_t RESERVED39[61]; + __IOM uint32_t STIR; /*!< Provides a mechanism for software to generate an interrupt */ + __IM uint32_t RESERVED40[12]; + __IOM uint32_t FPCCR; /*!< Holds control data for the Floating-point extension */ + __IOM uint32_t FPCAR; /*!< Holds the location of the unpopulated floating-point register + space allocated on an exception stack frame */ + __IOM uint32_t FPDSCR; /*!< Holds the default values for the floating-point status control + data that the PE assigns to the FPSCR when it creates a + new floating-point context */ + __IOM uint32_t MVFR0; /*!< Describes the features provided by the Floating-point Extension */ + __IOM uint32_t MVFR1; /*!< Describes the features provided by the Floating-point Extension */ + __IOM uint32_t MVFR2; /*!< Describes the features provided by the Floating-point Extension */ + __IM uint32_t RESERVED41[28]; + __IOM uint32_t DDEVARCH; /*!< Provides CoreSight discovery information for the SCS */ + __IM uint32_t RESERVED42[3]; + __IOM uint32_t DDEVTYPE; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR4; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR5; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR6; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR7; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR0; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR1; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR2; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DPIDR3; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DCIDR0; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DCIDR1; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DCIDR2; /*!< Provides CoreSight discovery information for the SCS */ + __IOM uint32_t DCIDR3; /*!< Provides CoreSight discovery information for the SCS */ + __IM uint32_t RESERVED43[51201]; + __IOM uint32_t TRCPRGCTLR; /*!< Programming Control Register */ + __IM uint32_t RESERVED44; + __IOM uint32_t TRCSTATR; /*!< The TRCSTATR indicates the ETM-Teal status */ + __IOM uint32_t TRCCONFIGR; /*!< The TRCCONFIGR sets the basic tracing options for the trace + unit */ + __IM uint32_t RESERVED45[3]; + __IOM uint32_t TRCEVENTCTL0R; /*!< The TRCEVENTCTL0R controls the tracing of events in the trace + stream. The events also drive the ETM-Teal external outputs. */ + __IOM uint32_t TRCEVENTCTL1R; /*!< The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R + behave */ + __IM uint32_t RESERVED46; + __IOM uint32_t TRCSTALLCTLR; /*!< The TRCSTALLCTLR enables ETM-Teal to stall the processor if + the ETM-Teal FIFO goes over the programmed level to minimize + risk of overflow */ + __IOM uint32_t TRCTSCTLR; /*!< The TRCTSCTLR controls the insertion of global timestamps into + the trace stream. A timestamp is always inserted into the + instruction trace stream */ + __IOM uint32_t TRCSYNCPR; /*!< The TRCSYNCPR specifies the period of trace synchronization + of the trace streams. TRCSYNCPR defines a number of bytes + of trace between requests for trace synchronization. This + value is always a power of two */ + __IOM uint32_t TRCCCCTLR; /*!< The TRCCCCTLR sets the threshold value for instruction trace + cycle counting. The threshold represents the minimum interval + between cycle count trace packets */ + __IM uint32_t RESERVED47[17]; + __IOM uint32_t TRCVICTLR; /*!< The TRCVICTLR controls instruction trace filtering */ + __IM uint32_t RESERVED48[47]; + __IOM uint32_t TRCCNTRLDVR0; /*!< The TRCCNTRLDVR defines the reload value for the reduced function + counter */ + __IM uint32_t RESERVED49[15]; + __IOM uint32_t TRCIDR8; /*!< TRCIDR8 */ + __IOM uint32_t TRCIDR9; /*!< TRCIDR9 */ + __IOM uint32_t TRCIDR10; /*!< TRCIDR10 */ + __IOM uint32_t TRCIDR11; /*!< TRCIDR11 */ + __IOM uint32_t TRCIDR12; /*!< TRCIDR12 */ + __IOM uint32_t TRCIDR13; /*!< TRCIDR13 */ + __IM uint32_t RESERVED50[10]; + __IOM uint32_t TRCIMSPEC; /*!< The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC + features, and enables any features that are provided */ + __IM uint32_t RESERVED51[7]; + __IOM uint32_t TRCIDR0; /*!< TRCIDR0 */ + __IOM uint32_t TRCIDR1; /*!< TRCIDR1 */ + __IOM uint32_t TRCIDR2; /*!< TRCIDR2 */ + __IOM uint32_t TRCIDR3; /*!< TRCIDR3 */ + __IOM uint32_t TRCIDR4; /*!< TRCIDR4 */ + __IOM uint32_t TRCIDR5; /*!< TRCIDR5 */ + __IOM uint32_t TRCIDR6; /*!< TRCIDR6 */ + __IOM uint32_t TRCIDR7; /*!< TRCIDR7 */ + __IM uint32_t RESERVED52[2]; + __IOM uint32_t TRCRSCTLR2; /*!< The TRCRSCTLR controls the trace resources */ + __IOM uint32_t TRCRSCTLR3; /*!< The TRCRSCTLR controls the trace resources */ + __IM uint32_t RESERVED53[36]; + __IOM uint32_t TRCSSCSR; /*!< Controls the corresponding single-shot comparator resource */ + __IM uint32_t RESERVED54[7]; + __IOM uint32_t TRCSSPCICR; /*!< Selects the PE comparator inputs for Single-shot control */ + __IM uint32_t RESERVED55[19]; + __IOM uint32_t TRCPDCR; /*!< Requests the system to provide power to the trace unit */ + __IOM uint32_t TRCPDSR; /*!< Returns the following information about the trace unit: - OS + Lock status. - Core power domain status. - Power interruption + status */ + __IM uint32_t RESERVED56[755]; + __IOM uint32_t TRCITATBIDR; /*!< Trace Integration ATB Identification Register */ + __IM uint32_t RESERVED57[3]; + __IOM uint32_t TRCITIATBINR; /*!< Trace Integration Instruction ATB In Register */ + __IM uint32_t RESERVED58; + __IOM uint32_t TRCITIATBOUTR; /*!< Trace Integration Instruction ATB Out Register */ + __IM uint32_t RESERVED59[40]; + __IOM uint32_t TRCCLAIMSET; /*!< Claim Tag Set Register */ + __IOM uint32_t TRCCLAIMCLR; /*!< Claim Tag Clear Register */ + __IM uint32_t RESERVED60[4]; + __IOM uint32_t TRCAUTHSTATUS; /*!< Returns the level of tracing that the trace unit can support */ + __IOM uint32_t TRCDEVARCH; /*!< TRCDEVARCH */ + __IM uint32_t RESERVED61[2]; + __IOM uint32_t TRCDEVID; /*!< TRCDEVID */ + __IOM uint32_t TRCDEVTYPE; /*!< TRCDEVTYPE */ + __IOM uint32_t TRCPIDR4; /*!< TRCPIDR4 */ + __IOM uint32_t TRCPIDR5; /*!< TRCPIDR5 */ + __IOM uint32_t TRCPIDR6; /*!< TRCPIDR6 */ + __IOM uint32_t TRCPIDR7; /*!< TRCPIDR7 */ + __IOM uint32_t TRCPIDR0; /*!< TRCPIDR0 */ + __IOM uint32_t TRCPIDR1; /*!< TRCPIDR1 */ + __IOM uint32_t TRCPIDR2; /*!< TRCPIDR2 */ + __IOM uint32_t TRCPIDR3; /*!< TRCPIDR3 */ + __IOM uint32_t TRCCIDR0; /*!< TRCCIDR0 */ + __IOM uint32_t TRCCIDR1; /*!< TRCCIDR1 */ + __IOM uint32_t TRCCIDR2; /*!< TRCCIDR2 */ + __IOM uint32_t TRCCIDR3; /*!< TRCCIDR3 */ + __IOM uint32_t CTICONTROL; /*!< CTI Control Register */ + __IM uint32_t RESERVED62[3]; + __IOM uint32_t CTIINTACK; /*!< CTI Interrupt Acknowledge Register */ + __IOM uint32_t CTIAPPSET; /*!< CTI Application Trigger Set Register */ + __IOM uint32_t CTIAPPCLEAR; /*!< CTI Application Trigger Clear Register */ + __IOM uint32_t CTIAPPPULSE; /*!< CTI Application Pulse Register */ + __IOM uint32_t CTIINEN0; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIINEN1; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIINEN2; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIINEN3; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIINEN4; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIINEN5; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIINEN6; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIINEN7; /*!< CTI Trigger to Channel Enable Registers */ + __IM uint32_t RESERVED63[24]; + __IOM uint32_t CTIOUTEN0; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIOUTEN1; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIOUTEN2; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIOUTEN3; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIOUTEN4; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIOUTEN5; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIOUTEN6; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTIOUTEN7; /*!< CTI Trigger to Channel Enable Registers */ + __IM uint32_t RESERVED64[28]; + __IOM uint32_t CTITRIGINSTATUS; /*!< CTI Trigger to Channel Enable Registers */ + __IOM uint32_t CTITRIGOUTSTATUS; /*!< CTI Trigger In Status Register */ + __IOM uint32_t CTICHINSTATUS; /*!< CTI Channel In Status Register */ + __IM uint32_t RESERVED65; + __IOM uint32_t CTIGATE; /*!< Enable CTI Channel Gate register */ + __IOM uint32_t ASICCTL; /*!< External Multiplexer Control register */ + __IM uint32_t RESERVED66[871]; + __IOM uint32_t ITCHOUT; /*!< Integration Test Channel Output register */ + __IOM uint32_t ITTRIGOUT; /*!< Integration Test Trigger Output register */ + __IM uint32_t RESERVED67[2]; + __IOM uint32_t ITCHIN; /*!< Integration Test Channel Input register */ + __IM uint32_t RESERVED68[2]; + __IOM uint32_t ITCTRL; /*!< Integration Mode Control register */ + __IM uint32_t RESERVED69[46]; + __IOM uint32_t DEVARCH; /*!< Device Architecture register */ + __IM uint32_t RESERVED70[2]; + __IOM uint32_t DEVID; /*!< Device Configuration register */ + __IOM uint32_t DEVTYPE; /*!< Device Type Identifier register */ + __IOM uint32_t PIDR4; /*!< CoreSight Peripheral ID4 */ + __IOM uint32_t PIDR5; /*!< CoreSight Peripheral ID5 */ + __IOM uint32_t PIDR6; /*!< CoreSight Peripheral ID6 */ + __IOM uint32_t PIDR7; /*!< CoreSight Peripheral ID7 */ + __IOM uint32_t PIDR0; /*!< CoreSight Peripheral ID0 */ + __IOM uint32_t PIDR1; /*!< CoreSight Peripheral ID1 */ + __IOM uint32_t PIDR2; /*!< CoreSight Peripheral ID2 */ + __IOM uint32_t PIDR3; /*!< CoreSight Peripheral ID3 */ + __IOM uint32_t CIDR0; /*!< CoreSight Component ID0 */ + __IOM uint32_t CIDR1; /*!< CoreSight Component ID1 */ + __IOM uint32_t CIDR2; /*!< CoreSight Component ID2 */ + __IOM uint32_t CIDR3; /*!< CoreSight Component ID3 */ +} PPB_Type; /*!< Size = 274432 (0x43000) */ + + + +/* =========================================================================================================================== */ +/* ================ QMI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief QSPI Memory Interface. + + Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device. (QMI) + */ + +typedef struct { /*!< QMI Structure */ + __IOM uint32_t DIRECT_CSR; /*!< Control and status for direct serial mode Direct serial mode + allows the processor to send and receive raw serial frames, + for programming, configuration and control of the external + memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. */ + __IOM uint32_t DIRECT_TX; /*!< Transmit FIFO for direct mode */ + __IOM uint32_t DIRECT_RX; /*!< Receive FIFO for direct mode */ + __IOM uint32_t M0_TIMING; /*!< Timing configuration register for memory address window 0. */ + __IOM uint32_t M0_RFMT; /*!< Read transfer format configuration for memory address window + 0. Configure the bus width of each transfer phase individually, + and configure the length or presence of the command prefix, + command suffix and dummy/turnaround transfer phases. Only + 24-bit addresses are supported. The reset value of the + M0_RFMT register is configured to support a basic 03h serial + read transfer with no additional configuration. */ + __IOM uint32_t M0_RCMD; /*!< Command constants used for reads from memory address window + 0. The reset value of the M0_RCMD register is configured + to support a basic 03h serial read transfer with no additional + configuration. */ + __IOM uint32_t M0_WFMT; /*!< Write transfer format configuration for memory address window + 0. Configure the bus width of each transfer phase individually, + and configure the length or presence of the command prefix, + command suffix and dummy/turnaround transfer phases. Only + 24-bit addresses are supported. The reset value of the + M0_WFMT register is configured to support a basic 02h serial + write transfer. However, writes to this window must first + be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory + is read-only by default. */ + __IOM uint32_t M0_WCMD; /*!< Command constants used for writes to memory address window 0. + The reset value of the M0_WCMD register is configured to + support a basic 02h serial write transfer with no additional + configuration. */ + __IOM uint32_t M1_TIMING; /*!< Timing configuration register for memory address window 1. */ + __IOM uint32_t M1_RFMT; /*!< Read transfer format configuration for memory address window + 1. Configure the bus width of each transfer phase individually, + and configure the length or presence of the command prefix, + command suffix and dummy/turnaround transfer phases. Only + 24-bit addresses are supported. The reset value of the + M1_RFMT register is configured to support a basic 03h serial + read transfer with no additional configuration. */ + __IOM uint32_t M1_RCMD; /*!< Command constants used for reads from memory address window + 1. The reset value of the M1_RCMD register is configured + to support a basic 03h serial read transfer with no additional + configuration. */ + __IOM uint32_t M1_WFMT; /*!< Write transfer format configuration for memory address window + 1. Configure the bus width of each transfer phase individually, + and configure the length or presence of the command prefix, + command suffix and dummy/turnaround transfer phases. Only + 24-bit addresses are supported. The reset value of the + M1_WFMT register is configured to support a basic 02h serial + write transfer. However, writes to this window must first + be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory + is read-only by default. */ + __IOM uint32_t M1_WCMD; /*!< Command constants used for writes to memory address window 1. + The reset value of the M1_WCMD register is configured to + support a basic 02h serial write transfer with no additional + configuration. */ + __IOM uint32_t ATRANS0; /*!< Configure address translation for XIP virtual addresses 0x000000 + through 0x3fffff (a 4 MiB window starting at +0 MiB). Address + translation allows a program image to be executed in place + at multiple physical flash addresses (for example, a double-buffered + flash image for over-the-air updates), without the overhead + of position-independent code. At reset, the address translation + registers are initialised to an identity mapping, so that + they can be ignored if address translation is not required. + Note that the XIP cache is fully virtually addressed, so + a cache flush is required after changing the address translation. */ + __IOM uint32_t ATRANS1; /*!< Configure address translation for XIP virtual addresses 0x400000 + through 0x7fffff (a 4 MiB window starting at +4 MiB). Address + translation allows a program image to be executed in place + at multiple physical flash addresses (for example, a double-buffered + flash image for over-the-air updates), without the overhead + of position-independent code. At reset, the address translation + registers are initialised to an identity mapping, so that + they can be ignored if address translation is not required. + Note that the XIP cache is fully virtually addressed, so + a cache flush is required after changing the address translation. */ + __IOM uint32_t ATRANS2; /*!< Configure address translation for XIP virtual addresses 0x800000 + through 0xbfffff (a 4 MiB window starting at +8 MiB). Address + translation allows a program image to be executed in place + at multiple physical flash addresses (for example, a double-buffered + flash image for over-the-air updates), without the overhead + of position-independent code. At reset, the address translation + registers are initialised to an identity mapping, so that + they can be ignored if address translation is not required. + Note that the XIP cache is fully virtually addressed, so + a cache flush is required after changing the address translation. */ + __IOM uint32_t ATRANS3; /*!< Configure address translation for XIP virtual addresses 0xc00000 + through 0xffffff (a 4 MiB window starting at +12 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ + __IOM uint32_t ATRANS4; /*!< Configure address translation for XIP virtual addresses 0x1000000 + through 0x13fffff (a 4 MiB window starting at +16 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ + __IOM uint32_t ATRANS5; /*!< Configure address translation for XIP virtual addresses 0x1400000 + through 0x17fffff (a 4 MiB window starting at +20 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ + __IOM uint32_t ATRANS6; /*!< Configure address translation for XIP virtual addresses 0x1800000 + through 0x1bfffff (a 4 MiB window starting at +24 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ + __IOM uint32_t ATRANS7; /*!< Configure address translation for XIP virtual addresses 0x1c00000 + through 0x1ffffff (a 4 MiB window starting at +28 MiB). + Address translation allows a program image to be executed + in place at multiple physical flash addresses (for example, + a double-buffered flash image for over-the-air updates), + without the overhead of position-independent code. At reset, + the address translation registers are initialised to an + identity mapping, so that they can be ignored if address + translation is not required. Note that the XIP cache is + fully virtually addressed, so a cache flush is required + after changing the address translation. */ +} QMI_Type; /*!< Size = 84 (0x54) */ + + + +/* =========================================================================================================================== */ +/* ================ XIP_CTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief QSPI flash execute-in-place block (XIP_CTRL) + */ + +typedef struct { /*!< XIP_CTRL Structure */ + __IOM uint32_t CTRL; /*!< Cache control register. Read-only from a Non-secure context. */ + __IM uint32_t RESERVED; + __IOM uint32_t STAT; /*!< STAT */ + __IOM uint32_t CTR_HIT; /*!< Cache Hit counter */ + __IOM uint32_t CTR_ACC; /*!< Cache Access counter */ + __IOM uint32_t STREAM_ADDR; /*!< FIFO stream address */ + __IOM uint32_t STREAM_CTR; /*!< FIFO stream control */ + __IOM uint32_t STREAM_FIFO; /*!< FIFO stream data */ +} XIP_CTRL_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ XIP_AUX ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Auxiliary DMA access to XIP FIFOs, via fast AHB bus access (XIP_AUX) + */ + +typedef struct { /*!< XIP_AUX Structure */ + __IOM uint32_t STREAM; /*!< Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) */ + __IOM uint32_t QMI_DIRECT_TX; /*!< Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) */ + __IOM uint32_t QMI_DIRECT_RX; /*!< Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) */ +} XIP_AUX_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ SYSCFG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Register block for various chip control signals (SYSCFG) + */ + +typedef struct { /*!< SYSCFG Structure */ + __IOM uint32_t PROC_CONFIG; /*!< Configuration for processors */ + __IOM uint32_t PROC_IN_SYNC_BYPASS; /*!< For each bit, if 1, bypass the input synchronizer between that + GPIO and the GPIO input register in the SIO. The input + synchronizers should generally be unbypassed, to avoid + injecting metastabilities into processors. If you're feeling + brave, you can bypass to save two cycles of input latency. + This register applies to GPIO 0...31. */ + __IOM uint32_t PROC_IN_SYNC_BYPASS_HI; /*!< For each bit, if 1, bypass the input synchronizer between that + GPIO and the GPIO input register in the SIO. The input + synchronizers should generally be unbypassed, to avoid + injecting metastabilities into processors. If you're feeling + brave, you can bypass to save two cycles of input latency. + This register applies to GPIO 32...47. USB GPIO 56..57 + QSPI GPIO 58..63 */ + __IOM uint32_t DBGFORCE; /*!< Directly control the chip SWD debug port */ + __IOM uint32_t MEMPOWERDOWN; /*!< Control PD pins to memories. Set high to put memories to a low + power state. In this state the memories will retain contents + but not be accessible Use with caution */ + __IOM uint32_t AUXCTRL; /*!< Auxiliary system control register */ +} SYSCFG_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ XOSC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controls the crystal oscillator (XOSC) + */ + +typedef struct { /*!< XOSC Structure */ + __IOM uint32_t CTRL; /*!< Crystal Oscillator Control */ + __IOM uint32_t STATUS; /*!< Crystal Oscillator Status */ + __IOM uint32_t DORMANT; /*!< Crystal Oscillator pause control */ + __IOM uint32_t STARTUP; /*!< Controls the startup delay */ + __IOM uint32_t COUNT; /*!< A down counter running at the xosc frequency which counts to + zero and stops. Can be used for short software pauses when + setting up time sensitive hardware. To start the counter, + write a non-zero value. Reads will return 1 while the count + is running and 0 when it has finished. Minimum count value + is 4. Count values <4 will be treated as count value =4. + Note that synchronisation to the register clock domain + costs 2 register clock cycles and the counter cannot compensate + for that. */ +} XOSC_Type; /*!< Size = 20 (0x14) */ + + + +/* =========================================================================================================================== */ +/* ================ PLL_SYS ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief PLL_SYS (PLL_SYS) + */ + +typedef struct { /*!< PLL_SYS Structure */ + __IOM uint32_t CS; /*!< Control and Status GENERAL CONSTRAINTS: Reference clock frequency + min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO + frequency min=750MHz, max=1600MHz */ + __IOM uint32_t PWR; /*!< Controls the PLL power modes. */ + __IOM uint32_t FBDIV_INT; /*!< Feedback divisor (note: this PLL does not support fractional + division) */ + __IOM uint32_t PRIM; /*!< Controls the PLL post dividers for the primary output (note: + this PLL does not have a secondary output) the primary + output is driven from VCO divided by postdiv1*postdiv2 */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} PLL_SYS_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ ACCESSCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Hardware access control registers (ACCESSCTRL) + */ + +typedef struct { /*!< ACCESSCTRL Structure */ + __IOM uint32_t LOCK; /*!< Once a LOCK bit is written to 1, ACCESSCTRL silently ignores + writes from that master. LOCK is writable only by a Secure, + Privileged processor or debugger. LOCK bits are only writable + when their value is zero. Once set, they can never be cleared, + except by a full reset of ACCESSCTRL Setting the LOCK bit + does not affect whether an access raises a bus error. Unprivileged + writes, or writes from the DMA, will continue to raise + bus errors. All other accesses will continue not to. */ + __IOM uint32_t FORCE_CORE_NS; /*!< Force core 1's bus accesses to always be Non-secure, no matter + the core's internal state. Useful for schemes where one + core is designated as the Non-secure core, since some peripherals + may filter individual registers internally based on security + state but not on master ID. */ + __IOM uint32_t CFGRESET; /*!< Write 1 to reset all ACCESSCTRL configuration, except for the + LOCK and FORCE_CORE_NS registers. This bit is used in the + RP2350 bootrom to quickly restore ACCESSCTRL to a known + state during the boot path. Note that, like all registers + in ACCESSCTRL, this register is not writable when the writer's + corresponding LOCK bit is set, therefore a master which + has been locked out of ACCESSCTRL can not use the CFGRESET + register to disturb its contents. */ + __IOM uint32_t GPIO_NSMASK0; /*!< Control whether GPIO0...31 are accessible to Non-secure code. + Writable only by a Secure, Privileged processor or debugger. + 0 -> Secure access only 1 -> Secure + Non-secure access */ + __IOM uint32_t GPIO_NSMASK1; /*!< Control whether GPIO32..47 are accessible to Non-secure code, + and whether QSPI and USB bitbang are accessible through + the Non-secure SIO. Writable only by a Secure, Privileged + processor or debugger. */ + __IOM uint32_t ROM; /*!< Control whether debugger, DMA, core 0 and core 1 can access + ROM, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t XIP_MAIN; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XIP_MAIN, and at what security/privilege levels they can + do so. Defaults to fully open access. This register is + writable only from a Secure, Privileged processor or debugger, + with the exception of the NSU bit, which becomes Non-secure-Privileged-wr + table when the NSP bit is set. */ + __IOM uint32_t SRAM0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM0, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM1; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM1, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM2; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM2, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM3; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM3, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM4; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM4, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM5; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM5, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM6; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM6, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM7; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM7, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM8; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM8, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t SRAM9; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SRAM9, and at what security/privilege levels they can do + so. Defaults to fully open access. This register is writable + only from a Secure, Privileged processor or debugger, with + the exception of the NSU bit, which becomes Non-secure-Privileged-writabl + when the NSP bit is set. */ + __IOM uint32_t DMA; /*!< Control whether debugger, DMA, core 0 and core 1 can access + DMA, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t USBCTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access + USBCTRL, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t PIO0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PIO0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t PIO1; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PIO1, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t PIO2; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PIO2, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t CORESIGHT_TRACE; /*!< Control whether debugger, DMA, core 0 and core 1 can access + CORESIGHT_TRACE, and at what security/privilege levels + they can do so. Defaults to Secure, Privileged processor + or debug access only. This register is writable only from + a Secure, Privileged processor or debugger, with the exception + of the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t CORESIGHT_PERIPH; /*!< Control whether debugger, DMA, core 0 and core 1 can access + CORESIGHT_PERIPH, and at what security/privilege levels + they can do so. Defaults to Secure, Privileged processor + or debug access only. This register is writable only from + a Secure, Privileged processor or debugger, with the exception + of the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t SYSINFO; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SYSINFO, and at what security/privilege levels they can + do so. Defaults to fully open access. This register is + writable only from a Secure, Privileged processor or debugger, + with the exception of the NSU bit, which becomes Non-secure-Privileged-wr + table when the NSP bit is set. */ + __IOM uint32_t RESETS; /*!< Control whether debugger, DMA, core 0 and core 1 can access + RESETS, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t IO_BANK0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + IO_BANK0, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t IO_BANK1; /*!< Control whether debugger, DMA, core 0 and core 1 can access + IO_BANK1, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t PADS_BANK0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PADS_BANK0, and at what security/privilege levels they + can do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t PADS_QSPI; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PADS_QSPI, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t BUSCTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access + BUSCTRL, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t ADC0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + ADC0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t HSTX; /*!< Control whether debugger, DMA, core 0 and core 1 can access + HSTX, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t I2C0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + I2C0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t I2C1; /*!< Control whether debugger, DMA, core 0 and core 1 can access + I2C1, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t PWM; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PWM, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t SPI0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SPI0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t SPI1; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SPI1, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t TIMER0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TIMER0, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t TIMER1; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TIMER1, and at what security/privilege levels they can + do so. Defaults to Secure access from any master. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t UART0; /*!< Control whether debugger, DMA, core 0 and core 1 can access + UART0, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t UART1; /*!< Control whether debugger, DMA, core 0 and core 1 can access + UART1, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t OTP; /*!< Control whether debugger, DMA, core 0 and core 1 can access + OTP, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t TBMAN; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TBMAN, and at what security/privilege levels they can do + so. Defaults to Secure access from any master. This register + is writable only from a Secure, Privileged processor or + debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t POWMAN; /*!< Control whether debugger, DMA, core 0 and core 1 can access + POWMAN, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t TRNG; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TRNG, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + __IOM uint32_t SHA256; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SHA256, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged access only. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ + __IOM uint32_t SYSCFG; /*!< Control whether debugger, DMA, core 0 and core 1 can access + SYSCFG, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t CLOCKS; /*!< Control whether debugger, DMA, core 0 and core 1 can access + CLOCKS, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t XOSC; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XOSC, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + __IOM uint32_t ROSC; /*!< Control whether debugger, DMA, core 0 and core 1 can access + ROSC, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + __IOM uint32_t PLL_SYS; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PLL_SYS, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t PLL_USB; /*!< Control whether debugger, DMA, core 0 and core 1 can access + PLL_USB, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t TICKS; /*!< Control whether debugger, DMA, core 0 and core 1 can access + TICKS, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + __IOM uint32_t WATCHDOG; /*!< Control whether debugger, DMA, core 0 and core 1 can access + WATCHDOG, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t RSM; /*!< Control whether debugger, DMA, core 0 and core 1 can access + RSM, and at what security/privilege levels they can do + so. Defaults to Secure, Privileged processor or debug access + only. This register is writable only from a Secure, Privileged + processor or debugger, with the exception of the NSU bit, + which becomes Non-secure-Privileged-writable when the NSP + bit is set. */ + __IOM uint32_t XIP_CTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XIP_CTRL, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t XIP_QMI; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XIP_QMI, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged processor or debug + access only. This register is writable only from a Secure, + Privileged processor or debugger, with the exception of + the NSU bit, which becomes Non-secure-Privileged-writable + when the NSP bit is set. */ + __IOM uint32_t XIP_AUX; /*!< Control whether debugger, DMA, core 0 and core 1 can access + XIP_AUX, and at what security/privilege levels they can + do so. Defaults to Secure, Privileged access only. This + register is writable only from a Secure, Privileged processor + or debugger, with the exception of the NSU bit, which becomes + Non-secure-Privileged-writable when the NSP bit is set. */ +} ACCESSCTRL_Type; /*!< Size = 236 (0xec) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART0 (UART0) + */ + +typedef struct { /*!< UART0 Structure */ + __IOM uint32_t UARTDR; /*!< Data Register, UARTDR */ + __IOM uint32_t UARTRSR; /*!< Receive Status Register/Error Clear Register, UARTRSR/UARTECR */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t UARTFR; /*!< Flag Register, UARTFR */ + __IM uint32_t RESERVED1; + __IOM uint32_t UARTILPR; /*!< IrDA Low-Power Counter Register, UARTILPR */ + __IOM uint32_t UARTIBRD; /*!< Integer Baud Rate Register, UARTIBRD */ + __IOM uint32_t UARTFBRD; /*!< Fractional Baud Rate Register, UARTFBRD */ + __IOM uint32_t UARTLCR_H; /*!< Line Control Register, UARTLCR_H */ + __IOM uint32_t UARTCR; /*!< Control Register, UARTCR */ + __IOM uint32_t UARTIFLS; /*!< Interrupt FIFO Level Select Register, UARTIFLS */ + __IOM uint32_t UARTIMSC; /*!< Interrupt Mask Set/Clear Register, UARTIMSC */ + __IOM uint32_t UARTRIS; /*!< Raw Interrupt Status Register, UARTRIS */ + __IOM uint32_t UARTMIS; /*!< Masked Interrupt Status Register, UARTMIS */ + __IOM uint32_t UARTICR; /*!< Interrupt Clear Register, UARTICR */ + __IOM uint32_t UARTDMACR; /*!< DMA Control Register, UARTDMACR */ + __IM uint32_t RESERVED2[997]; + __IOM uint32_t UARTPERIPHID0; /*!< UARTPeriphID0 Register */ + __IOM uint32_t UARTPERIPHID1; /*!< UARTPeriphID1 Register */ + __IOM uint32_t UARTPERIPHID2; /*!< UARTPeriphID2 Register */ + __IOM uint32_t UARTPERIPHID3; /*!< UARTPeriphID3 Register */ + __IOM uint32_t UARTPCELLID0; /*!< UARTPCellID0 Register */ + __IOM uint32_t UARTPCELLID1; /*!< UARTPCellID1 Register */ + __IOM uint32_t UARTPCELLID2; /*!< UARTPCellID2 Register */ + __IOM uint32_t UARTPCELLID3; /*!< UARTPCellID3 Register */ +} UART0_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ ROSC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ROSC (ROSC) + */ + +typedef struct { /*!< ROSC Structure */ + __IOM uint32_t CTRL; /*!< Ring Oscillator control */ + __IOM uint32_t FREQA; /*!< The FREQA & FREQB registers control the frequency by controlling + the drive strength of each stage The drive strength has + 4 levels determined by the number of bits set Increasing + the number of bits set increases the drive strength and + increases the oscillation frequency 0 bits set is the default + drive strength 1 bit set doubles the drive strength 2 bits + set triples drive strength 3 bits set quadruples drive + strength For frequency randomisation set both DS0_RANDOM=1 + & DS1_RANDOM=1 */ + __IOM uint32_t FREQB; /*!< For a detailed description see freqa register */ + __IOM uint32_t RANDOM; /*!< Loads a value to the LFSR randomiser */ + __IOM uint32_t DORMANT; /*!< Ring Oscillator pause control */ + __IOM uint32_t DIV; /*!< Controls the output divider */ + __IOM uint32_t PHASE; /*!< Controls the phase shifted output */ + __IOM uint32_t STATUS; /*!< Ring Oscillator Status */ + __IOM uint32_t RANDOMBIT; /*!< This just reads the state of the oscillator output so randomness + is compromised if the ring oscillator is stopped or run + at a harmonic of the bus frequency */ + __IOM uint32_t COUNT; /*!< A down counter running at the ROSC frequency which counts to + zero and stops. To start the counter write a non-zero value. + Can be used for short software pauses when setting up time + sensitive hardware. */ +} ROSC_Type; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ POWMAN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use (POWMAN) + */ + +typedef struct { /*!< POWMAN Structure */ + __IOM uint32_t BADPASSWD; /*!< Indicates a bad password has been used */ + __IOM uint32_t VREG_CTRL; /*!< Voltage Regulator Control */ + __IOM uint32_t VREG_STS; /*!< Voltage Regulator Status */ + __IOM uint32_t VREG; /*!< Voltage Regulator Settings */ + __IOM uint32_t VREG_LP_ENTRY; /*!< Voltage Regulator Low Power Entry Settings */ + __IOM uint32_t VREG_LP_EXIT; /*!< Voltage Regulator Low Power Exit Settings */ + __IOM uint32_t BOD_CTRL; /*!< Brown-out Detection Control */ + __IOM uint32_t BOD; /*!< Brown-out Detection Settings */ + __IOM uint32_t BOD_LP_ENTRY; /*!< Brown-out Detection Low Power Entry Settings */ + __IOM uint32_t BOD_LP_EXIT; /*!< Brown-out Detection Low Power Exit Settings */ + __IOM uint32_t LPOSC; /*!< Low power oscillator control register. */ + __IOM uint32_t CHIP_RESET; /*!< Chip reset control and status */ + __IOM uint32_t WDSEL; /*!< Allows a watchdog reset to reset the internal state of powman + in addition to the power-on state machine (PSM). Note that + powman ignores watchdog resets that do not select at least + the CLOCKS stage or earlier stages in the PSM. If using + these bits, it's recommended to set PSM_WDSEL to all-ones + in addition to the desired bits in this register. Failing + to select CLOCKS or earlier will result in the POWMAN_WDSEL + register having no effect. */ + __IOM uint32_t SEQ_CFG; /*!< For configuration of the power sequencer Writes are ignored + while POWMAN_STATE_CHANGING=1 */ + __IOM uint32_t STATE; /*!< This register controls the power state of the 4 power domains. + The current power state is indicated in POWMAN_STATE_CURRENT + which is read-only. To change the state, write to POWMAN_STATE_REQ. + The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds + to the power states defined in the datasheet: bit 3 = SWCORE + bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered + up 1 = powered down When POWMAN_STATE_REQ is written, the + POWMAN_STATE_WAITING flag is set while the Power Manager + determines what is required. If an invalid transition is + requested the Power Manager will still register the request + in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ + flag. It will then implement the power-up requests and + ignore the power down requests. To do nothing would risk + entering an unrecoverable lock-up state. Invalid requests + are: any combination of power up and power down requests + any request that results in swcore boing powered and xip + unpowered If the request is to power down the switched-core + domain then POWMAN_STATE_WAITING stays active until the + processors halt. During this time the POWMAN_STATE_REQ + field can be re-written to change or cancel the request. + When the power state transition begins the POWMAN_STATE_WAITING_flag + is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN + register writes are ignored until the transition completes. */ + __IOM uint32_t POW_FASTDIV; /*!< POW_FASTDIV */ + __IOM uint32_t POW_DELAY; /*!< power state machine delays */ + __IOM uint32_t EXT_CTRL0; /*!< Configures a gpio as a power mode aware control output */ + __IOM uint32_t EXT_CTRL1; /*!< Configures a gpio as a power mode aware control output */ + __IOM uint32_t EXT_TIME_REF; /*!< Select a GPIO to use as a time reference, the source can be + used to drive the low power clock at 32kHz, or to provide + a 1ms tick to the timer, or provide a 1Hz tick to the timer. + The tick selection is controlled by the POWMAN_TIMER register. */ + __IOM uint32_t LPOSC_FREQ_KHZ_INT; /*!< Informs the AON Timer of the integer component of the clock + frequency when running off the LPOSC. */ + __IOM uint32_t LPOSC_FREQ_KHZ_FRAC; /*!< Informs the AON Timer of the fractional component of the clock + frequency when running off the LPOSC. */ + __IOM uint32_t XOSC_FREQ_KHZ_INT; /*!< Informs the AON Timer of the integer component of the clock + frequency when running off the XOSC. */ + __IOM uint32_t XOSC_FREQ_KHZ_FRAC; /*!< Informs the AON Timer of the fractional component of the clock + frequency when running off the XOSC. */ + __IOM uint32_t SET_TIME_63TO48; /*!< SET_TIME_63TO48 */ + __IOM uint32_t SET_TIME_47TO32; /*!< SET_TIME_47TO32 */ + __IOM uint32_t SET_TIME_31TO16; /*!< SET_TIME_31TO16 */ + __IOM uint32_t SET_TIME_15TO0; /*!< SET_TIME_15TO0 */ + __IOM uint32_t READ_TIME_UPPER; /*!< READ_TIME_UPPER */ + __IOM uint32_t READ_TIME_LOWER; /*!< READ_TIME_LOWER */ + __IOM uint32_t ALARM_TIME_63TO48; /*!< ALARM_TIME_63TO48 */ + __IOM uint32_t ALARM_TIME_47TO32; /*!< ALARM_TIME_47TO32 */ + __IOM uint32_t ALARM_TIME_31TO16; /*!< ALARM_TIME_31TO16 */ + __IOM uint32_t ALARM_TIME_15TO0; /*!< ALARM_TIME_15TO0 */ + __IOM uint32_t TIMER; /*!< TIMER */ + __IOM uint32_t PWRUP0; /*!< 4 GPIO powerup events can be configured to wake the chip up + from a low power state. The pwrups are level/edge sensitive + and can be set to trigger on a high/rising or low/falling + event The number of gpios available depends on the package + option. An invalid selection will be ignored source = 0 + selects gpio0 . . source = 47 selects gpio47 source = 48 + selects qspi_ss source = 49 selects qspi_sd0 source = 50 + selects qspi_sd1 source = 51 selects qspi_sd2 source = + 52 selects qspi_sd3 source = 53 selects qspi_sclk level + = 0 triggers the pwrup when the source is low level = 1 + triggers the pwrup when the source is high */ + __IOM uint32_t PWRUP1; /*!< 4 GPIO powerup events can be configured to wake the chip up + from a low power state. The pwrups are level/edge sensitive + and can be set to trigger on a high/rising or low/falling + event The number of gpios available depends on the package + option. An invalid selection will be ignored source = 0 + selects gpio0 . . source = 47 selects gpio47 source = 48 + selects qspi_ss source = 49 selects qspi_sd0 source = 50 + selects qspi_sd1 source = 51 selects qspi_sd2 source = + 52 selects qspi_sd3 source = 53 selects qspi_sclk level + = 0 triggers the pwrup when the source is low level = 1 + triggers the pwrup when the source is high */ + __IOM uint32_t PWRUP2; /*!< 4 GPIO powerup events can be configured to wake the chip up + from a low power state. The pwrups are level/edge sensitive + and can be set to trigger on a high/rising or low/falling + event The number of gpios available depends on the package + option. An invalid selection will be ignored source = 0 + selects gpio0 . . source = 47 selects gpio47 source = 48 + selects qspi_ss source = 49 selects qspi_sd0 source = 50 + selects qspi_sd1 source = 51 selects qspi_sd2 source = + 52 selects qspi_sd3 source = 53 selects qspi_sclk level + = 0 triggers the pwrup when the source is low level = 1 + triggers the pwrup when the source is high */ + __IOM uint32_t PWRUP3; /*!< 4 GPIO powerup events can be configured to wake the chip up + from a low power state. The pwrups are level/edge sensitive + and can be set to trigger on a high/rising or low/falling + event The number of gpios available depends on the package + option. An invalid selection will be ignored source = 0 + selects gpio0 . . source = 47 selects gpio47 source = 48 + selects qspi_ss source = 49 selects qspi_sd0 source = 50 + selects qspi_sd1 source = 51 selects qspi_sd2 source = + 52 selects qspi_sd3 source = 53 selects qspi_sclk level + = 0 triggers the pwrup when the source is low level = 1 + triggers the pwrup when the source is high */ + __IOM uint32_t CURRENT_PWRUP_REQ; /*!< Indicates current powerup request state pwrup events can be + cleared by removing the enable from the pwrup register. + The alarm pwrup req can be cleared by clearing timer.alarm_enab + 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET + 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup + 6 = alarm_pwrup */ + __IOM uint32_t LAST_SWCORE_PWRUP; /*!< Indicates which pwrup source triggered the last switched-core + power up 0 = chip reset, for the source of the last reset + see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 + 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup */ + __IOM uint32_t DBG_PWRCFG; /*!< DBG_PWRCFG */ + __IOM uint32_t BOOTDIS; /*!< Tell the bootrom to ignore the BOOT0..3 registers following + the next RSM reset (e.g. the next core power down/up). + If an early boot stage has soft-locked some OTP pages in + order to protect their contents from later stages, there + is a risk that Secure code running at a later stage can + unlock the pages by powering the core up and down. This + register can be used to ensure that the bootloader runs + as normal on the next power up, preventing Secure code + at a later stage from accessing OTP in its unlocked state. + Should be used in conjunction with the OTP BOOTDIS register. */ + __IOM uint32_t DBGCONFIG; /*!< DBGCONFIG */ + __IOM uint32_t SCRATCH0; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t SCRATCH1; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t SCRATCH2; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t SCRATCH3; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t SCRATCH4; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t SCRATCH5; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t SCRATCH6; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t SCRATCH7; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t BOOT0; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t BOOT1; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t BOOT2; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t BOOT3; /*!< Scratch register. Information persists in low power mode */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} POWMAN_Type; /*!< Size = 240 (0xf0) */ + + + +/* =========================================================================================================================== */ +/* ================ WATCHDOG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief WATCHDOG (WATCHDOG) + */ + +typedef struct { /*!< WATCHDOG Structure */ + __IOM uint32_t CTRL; /*!< Watchdog control The rst_wdsel register determines which subsystems + are reset when the watchdog is triggered. The watchdog + can be triggered in software. */ + __IOM uint32_t LOAD; /*!< Load the watchdog timer. The maximum setting is 0xffffff which + corresponds to approximately 16 seconds. */ + __IOM uint32_t REASON; /*!< Logs the reason for the last reset. Both bits are zero for the + case of a hardware reset. Additionally, as of RP2350, a + debugger warm reset of either core (SYSRESETREQ or hartreset) + will also clear the watchdog reason register, so that software + loaded under the debugger following a watchdog timeout + will not continue to see the timeout condition. */ + __IOM uint32_t SCRATCH0; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH1; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH2; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH3; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH4; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH5; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH6; /*!< Scratch register. Information persists through soft reset of + the chip. */ + __IOM uint32_t SCRATCH7; /*!< Scratch register. Information persists through soft reset of + the chip. */ +} WATCHDOG_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ DMA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DMA with separate read and write masters (DMA) + */ + +typedef struct { /*!< DMA Structure */ + __IOM uint32_t CH0_READ_ADDR; /*!< DMA Channel 0 Read Address pointer */ + __IOM uint32_t CH0_WRITE_ADDR; /*!< DMA Channel 0 Write Address pointer */ + __IOM uint32_t CH0_TRANS_COUNT; /*!< DMA Channel 0 Transfer Count */ + __IOM uint32_t CH0_CTRL_TRIG; /*!< DMA Channel 0 Control and Status */ + __IOM uint32_t CH0_AL1_CTRL; /*!< Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL1_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */ + __IOM uint32_t CH0_AL1_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */ + __IOM uint32_t CH0_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 0 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH0_AL2_CTRL; /*!< Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL2_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */ + __IOM uint32_t CH0_AL2_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */ + __IOM uint32_t CH0_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 0 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH0_AL3_CTRL; /*!< Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL3_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */ + __IOM uint32_t CH0_AL3_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */ + __IOM uint32_t CH0_AL3_READ_ADDR_TRIG; /*!< Alias for channel 0 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH1_READ_ADDR; /*!< DMA Channel 1 Read Address pointer */ + __IOM uint32_t CH1_WRITE_ADDR; /*!< DMA Channel 1 Write Address pointer */ + __IOM uint32_t CH1_TRANS_COUNT; /*!< DMA Channel 1 Transfer Count */ + __IOM uint32_t CH1_CTRL_TRIG; /*!< DMA Channel 1 Control and Status */ + __IOM uint32_t CH1_AL1_CTRL; /*!< Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL1_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */ + __IOM uint32_t CH1_AL1_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */ + __IOM uint32_t CH1_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 1 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH1_AL2_CTRL; /*!< Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL2_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */ + __IOM uint32_t CH1_AL2_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */ + __IOM uint32_t CH1_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 1 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH1_AL3_CTRL; /*!< Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL3_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */ + __IOM uint32_t CH1_AL3_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */ + __IOM uint32_t CH1_AL3_READ_ADDR_TRIG; /*!< Alias for channel 1 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH2_READ_ADDR; /*!< DMA Channel 2 Read Address pointer */ + __IOM uint32_t CH2_WRITE_ADDR; /*!< DMA Channel 2 Write Address pointer */ + __IOM uint32_t CH2_TRANS_COUNT; /*!< DMA Channel 2 Transfer Count */ + __IOM uint32_t CH2_CTRL_TRIG; /*!< DMA Channel 2 Control and Status */ + __IOM uint32_t CH2_AL1_CTRL; /*!< Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL1_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */ + __IOM uint32_t CH2_AL1_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */ + __IOM uint32_t CH2_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 2 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH2_AL2_CTRL; /*!< Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL2_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */ + __IOM uint32_t CH2_AL2_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */ + __IOM uint32_t CH2_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 2 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH2_AL3_CTRL; /*!< Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL3_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */ + __IOM uint32_t CH2_AL3_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */ + __IOM uint32_t CH2_AL3_READ_ADDR_TRIG; /*!< Alias for channel 2 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH3_READ_ADDR; /*!< DMA Channel 3 Read Address pointer */ + __IOM uint32_t CH3_WRITE_ADDR; /*!< DMA Channel 3 Write Address pointer */ + __IOM uint32_t CH3_TRANS_COUNT; /*!< DMA Channel 3 Transfer Count */ + __IOM uint32_t CH3_CTRL_TRIG; /*!< DMA Channel 3 Control and Status */ + __IOM uint32_t CH3_AL1_CTRL; /*!< Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL1_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */ + __IOM uint32_t CH3_AL1_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */ + __IOM uint32_t CH3_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 3 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH3_AL2_CTRL; /*!< Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL2_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */ + __IOM uint32_t CH3_AL2_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */ + __IOM uint32_t CH3_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 3 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH3_AL3_CTRL; /*!< Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL3_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */ + __IOM uint32_t CH3_AL3_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */ + __IOM uint32_t CH3_AL3_READ_ADDR_TRIG; /*!< Alias for channel 3 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH4_READ_ADDR; /*!< DMA Channel 4 Read Address pointer */ + __IOM uint32_t CH4_WRITE_ADDR; /*!< DMA Channel 4 Write Address pointer */ + __IOM uint32_t CH4_TRANS_COUNT; /*!< DMA Channel 4 Transfer Count */ + __IOM uint32_t CH4_CTRL_TRIG; /*!< DMA Channel 4 Control and Status */ + __IOM uint32_t CH4_AL1_CTRL; /*!< Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL1_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */ + __IOM uint32_t CH4_AL1_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */ + __IOM uint32_t CH4_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 4 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH4_AL2_CTRL; /*!< Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL2_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */ + __IOM uint32_t CH4_AL2_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */ + __IOM uint32_t CH4_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 4 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH4_AL3_CTRL; /*!< Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL3_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */ + __IOM uint32_t CH4_AL3_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */ + __IOM uint32_t CH4_AL3_READ_ADDR_TRIG; /*!< Alias for channel 4 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH5_READ_ADDR; /*!< DMA Channel 5 Read Address pointer */ + __IOM uint32_t CH5_WRITE_ADDR; /*!< DMA Channel 5 Write Address pointer */ + __IOM uint32_t CH5_TRANS_COUNT; /*!< DMA Channel 5 Transfer Count */ + __IOM uint32_t CH5_CTRL_TRIG; /*!< DMA Channel 5 Control and Status */ + __IOM uint32_t CH5_AL1_CTRL; /*!< Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL1_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */ + __IOM uint32_t CH5_AL1_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */ + __IOM uint32_t CH5_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 5 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH5_AL2_CTRL; /*!< Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL2_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */ + __IOM uint32_t CH5_AL2_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */ + __IOM uint32_t CH5_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 5 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH5_AL3_CTRL; /*!< Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL3_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */ + __IOM uint32_t CH5_AL3_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */ + __IOM uint32_t CH5_AL3_READ_ADDR_TRIG; /*!< Alias for channel 5 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH6_READ_ADDR; /*!< DMA Channel 6 Read Address pointer */ + __IOM uint32_t CH6_WRITE_ADDR; /*!< DMA Channel 6 Write Address pointer */ + __IOM uint32_t CH6_TRANS_COUNT; /*!< DMA Channel 6 Transfer Count */ + __IOM uint32_t CH6_CTRL_TRIG; /*!< DMA Channel 6 Control and Status */ + __IOM uint32_t CH6_AL1_CTRL; /*!< Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL1_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */ + __IOM uint32_t CH6_AL1_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */ + __IOM uint32_t CH6_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 6 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH6_AL2_CTRL; /*!< Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL2_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */ + __IOM uint32_t CH6_AL2_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */ + __IOM uint32_t CH6_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 6 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH6_AL3_CTRL; /*!< Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL3_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */ + __IOM uint32_t CH6_AL3_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */ + __IOM uint32_t CH6_AL3_READ_ADDR_TRIG; /*!< Alias for channel 6 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH7_READ_ADDR; /*!< DMA Channel 7 Read Address pointer */ + __IOM uint32_t CH7_WRITE_ADDR; /*!< DMA Channel 7 Write Address pointer */ + __IOM uint32_t CH7_TRANS_COUNT; /*!< DMA Channel 7 Transfer Count */ + __IOM uint32_t CH7_CTRL_TRIG; /*!< DMA Channel 7 Control and Status */ + __IOM uint32_t CH7_AL1_CTRL; /*!< Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL1_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */ + __IOM uint32_t CH7_AL1_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */ + __IOM uint32_t CH7_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 7 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH7_AL2_CTRL; /*!< Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL2_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */ + __IOM uint32_t CH7_AL2_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */ + __IOM uint32_t CH7_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 7 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH7_AL3_CTRL; /*!< Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL3_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */ + __IOM uint32_t CH7_AL3_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */ + __IOM uint32_t CH7_AL3_READ_ADDR_TRIG; /*!< Alias for channel 7 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH8_READ_ADDR; /*!< DMA Channel 8 Read Address pointer */ + __IOM uint32_t CH8_WRITE_ADDR; /*!< DMA Channel 8 Write Address pointer */ + __IOM uint32_t CH8_TRANS_COUNT; /*!< DMA Channel 8 Transfer Count */ + __IOM uint32_t CH8_CTRL_TRIG; /*!< DMA Channel 8 Control and Status */ + __IOM uint32_t CH8_AL1_CTRL; /*!< Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL1_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */ + __IOM uint32_t CH8_AL1_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */ + __IOM uint32_t CH8_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 8 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH8_AL2_CTRL; /*!< Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL2_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */ + __IOM uint32_t CH8_AL2_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */ + __IOM uint32_t CH8_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 8 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH8_AL3_CTRL; /*!< Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL3_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */ + __IOM uint32_t CH8_AL3_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */ + __IOM uint32_t CH8_AL3_READ_ADDR_TRIG; /*!< Alias for channel 8 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH9_READ_ADDR; /*!< DMA Channel 9 Read Address pointer */ + __IOM uint32_t CH9_WRITE_ADDR; /*!< DMA Channel 9 Write Address pointer */ + __IOM uint32_t CH9_TRANS_COUNT; /*!< DMA Channel 9 Transfer Count */ + __IOM uint32_t CH9_CTRL_TRIG; /*!< DMA Channel 9 Control and Status */ + __IOM uint32_t CH9_AL1_CTRL; /*!< Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL1_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */ + __IOM uint32_t CH9_AL1_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */ + __IOM uint32_t CH9_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 9 TRANS_COUNT register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH9_AL2_CTRL; /*!< Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL2_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */ + __IOM uint32_t CH9_AL2_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */ + __IOM uint32_t CH9_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 9 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH9_AL3_CTRL; /*!< Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL3_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */ + __IOM uint32_t CH9_AL3_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */ + __IOM uint32_t CH9_AL3_READ_ADDR_TRIG; /*!< Alias for channel 9 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH10_READ_ADDR; /*!< DMA Channel 10 Read Address pointer */ + __IOM uint32_t CH10_WRITE_ADDR; /*!< DMA Channel 10 Write Address pointer */ + __IOM uint32_t CH10_TRANS_COUNT; /*!< DMA Channel 10 Transfer Count */ + __IOM uint32_t CH10_CTRL_TRIG; /*!< DMA Channel 10 Control and Status */ + __IOM uint32_t CH10_AL1_CTRL; /*!< Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL1_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */ + __IOM uint32_t CH10_AL1_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */ + __IOM uint32_t CH10_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 10 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH10_AL2_CTRL; /*!< Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL2_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */ + __IOM uint32_t CH10_AL2_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */ + __IOM uint32_t CH10_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 10 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH10_AL3_CTRL; /*!< Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL3_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */ + __IOM uint32_t CH10_AL3_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */ + __IOM uint32_t CH10_AL3_READ_ADDR_TRIG; /*!< Alias for channel 10 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH11_READ_ADDR; /*!< DMA Channel 11 Read Address pointer */ + __IOM uint32_t CH11_WRITE_ADDR; /*!< DMA Channel 11 Write Address pointer */ + __IOM uint32_t CH11_TRANS_COUNT; /*!< DMA Channel 11 Transfer Count */ + __IOM uint32_t CH11_CTRL_TRIG; /*!< DMA Channel 11 Control and Status */ + __IOM uint32_t CH11_AL1_CTRL; /*!< Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL1_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */ + __IOM uint32_t CH11_AL1_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */ + __IOM uint32_t CH11_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 11 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH11_AL2_CTRL; /*!< Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL2_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */ + __IOM uint32_t CH11_AL2_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */ + __IOM uint32_t CH11_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 11 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH11_AL3_CTRL; /*!< Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL3_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */ + __IOM uint32_t CH11_AL3_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */ + __IOM uint32_t CH11_AL3_READ_ADDR_TRIG; /*!< Alias for channel 11 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH12_READ_ADDR; /*!< DMA Channel 12 Read Address pointer */ + __IOM uint32_t CH12_WRITE_ADDR; /*!< DMA Channel 12 Write Address pointer */ + __IOM uint32_t CH12_TRANS_COUNT; /*!< DMA Channel 12 Transfer Count */ + __IOM uint32_t CH12_CTRL_TRIG; /*!< DMA Channel 12 Control and Status */ + __IOM uint32_t CH12_AL1_CTRL; /*!< Alias for channel 12 CTRL register */ + __IOM uint32_t CH12_AL1_READ_ADDR; /*!< Alias for channel 12 READ_ADDR register */ + __IOM uint32_t CH12_AL1_WRITE_ADDR; /*!< Alias for channel 12 WRITE_ADDR register */ + __IOM uint32_t CH12_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 12 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH12_AL2_CTRL; /*!< Alias for channel 12 CTRL register */ + __IOM uint32_t CH12_AL2_TRANS_COUNT; /*!< Alias for channel 12 TRANS_COUNT register */ + __IOM uint32_t CH12_AL2_READ_ADDR; /*!< Alias for channel 12 READ_ADDR register */ + __IOM uint32_t CH12_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 12 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH12_AL3_CTRL; /*!< Alias for channel 12 CTRL register */ + __IOM uint32_t CH12_AL3_WRITE_ADDR; /*!< Alias for channel 12 WRITE_ADDR register */ + __IOM uint32_t CH12_AL3_TRANS_COUNT; /*!< Alias for channel 12 TRANS_COUNT register */ + __IOM uint32_t CH12_AL3_READ_ADDR_TRIG; /*!< Alias for channel 12 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH13_READ_ADDR; /*!< DMA Channel 13 Read Address pointer */ + __IOM uint32_t CH13_WRITE_ADDR; /*!< DMA Channel 13 Write Address pointer */ + __IOM uint32_t CH13_TRANS_COUNT; /*!< DMA Channel 13 Transfer Count */ + __IOM uint32_t CH13_CTRL_TRIG; /*!< DMA Channel 13 Control and Status */ + __IOM uint32_t CH13_AL1_CTRL; /*!< Alias for channel 13 CTRL register */ + __IOM uint32_t CH13_AL1_READ_ADDR; /*!< Alias for channel 13 READ_ADDR register */ + __IOM uint32_t CH13_AL1_WRITE_ADDR; /*!< Alias for channel 13 WRITE_ADDR register */ + __IOM uint32_t CH13_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 13 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH13_AL2_CTRL; /*!< Alias for channel 13 CTRL register */ + __IOM uint32_t CH13_AL2_TRANS_COUNT; /*!< Alias for channel 13 TRANS_COUNT register */ + __IOM uint32_t CH13_AL2_READ_ADDR; /*!< Alias for channel 13 READ_ADDR register */ + __IOM uint32_t CH13_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 13 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH13_AL3_CTRL; /*!< Alias for channel 13 CTRL register */ + __IOM uint32_t CH13_AL3_WRITE_ADDR; /*!< Alias for channel 13 WRITE_ADDR register */ + __IOM uint32_t CH13_AL3_TRANS_COUNT; /*!< Alias for channel 13 TRANS_COUNT register */ + __IOM uint32_t CH13_AL3_READ_ADDR_TRIG; /*!< Alias for channel 13 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH14_READ_ADDR; /*!< DMA Channel 14 Read Address pointer */ + __IOM uint32_t CH14_WRITE_ADDR; /*!< DMA Channel 14 Write Address pointer */ + __IOM uint32_t CH14_TRANS_COUNT; /*!< DMA Channel 14 Transfer Count */ + __IOM uint32_t CH14_CTRL_TRIG; /*!< DMA Channel 14 Control and Status */ + __IOM uint32_t CH14_AL1_CTRL; /*!< Alias for channel 14 CTRL register */ + __IOM uint32_t CH14_AL1_READ_ADDR; /*!< Alias for channel 14 READ_ADDR register */ + __IOM uint32_t CH14_AL1_WRITE_ADDR; /*!< Alias for channel 14 WRITE_ADDR register */ + __IOM uint32_t CH14_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 14 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH14_AL2_CTRL; /*!< Alias for channel 14 CTRL register */ + __IOM uint32_t CH14_AL2_TRANS_COUNT; /*!< Alias for channel 14 TRANS_COUNT register */ + __IOM uint32_t CH14_AL2_READ_ADDR; /*!< Alias for channel 14 READ_ADDR register */ + __IOM uint32_t CH14_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 14 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH14_AL3_CTRL; /*!< Alias for channel 14 CTRL register */ + __IOM uint32_t CH14_AL3_WRITE_ADDR; /*!< Alias for channel 14 WRITE_ADDR register */ + __IOM uint32_t CH14_AL3_TRANS_COUNT; /*!< Alias for channel 14 TRANS_COUNT register */ + __IOM uint32_t CH14_AL3_READ_ADDR_TRIG; /*!< Alias for channel 14 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH15_READ_ADDR; /*!< DMA Channel 15 Read Address pointer */ + __IOM uint32_t CH15_WRITE_ADDR; /*!< DMA Channel 15 Write Address pointer */ + __IOM uint32_t CH15_TRANS_COUNT; /*!< DMA Channel 15 Transfer Count */ + __IOM uint32_t CH15_CTRL_TRIG; /*!< DMA Channel 15 Control and Status */ + __IOM uint32_t CH15_AL1_CTRL; /*!< Alias for channel 15 CTRL register */ + __IOM uint32_t CH15_AL1_READ_ADDR; /*!< Alias for channel 15 READ_ADDR register */ + __IOM uint32_t CH15_AL1_WRITE_ADDR; /*!< Alias for channel 15 WRITE_ADDR register */ + __IOM uint32_t CH15_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 15 TRANS_COUNT register This is a trigger + register (0xc). Writing a nonzero value will reload the + channel counter and start the channel. */ + __IOM uint32_t CH15_AL2_CTRL; /*!< Alias for channel 15 CTRL register */ + __IOM uint32_t CH15_AL2_TRANS_COUNT; /*!< Alias for channel 15 TRANS_COUNT register */ + __IOM uint32_t CH15_AL2_READ_ADDR; /*!< Alias for channel 15 READ_ADDR register */ + __IOM uint32_t CH15_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 15 WRITE_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t CH15_AL3_CTRL; /*!< Alias for channel 15 CTRL register */ + __IOM uint32_t CH15_AL3_WRITE_ADDR; /*!< Alias for channel 15 WRITE_ADDR register */ + __IOM uint32_t CH15_AL3_TRANS_COUNT; /*!< Alias for channel 15 TRANS_COUNT register */ + __IOM uint32_t CH15_AL3_READ_ADDR_TRIG; /*!< Alias for channel 15 READ_ADDR register This is a trigger register + (0xc). Writing a nonzero value will reload the channel + counter and start the channel. */ + __IOM uint32_t INTR; /*!< Interrupt Status (raw) */ + __IOM uint32_t INTE0; /*!< Interrupt Enables for IRQ 0 */ + __IOM uint32_t INTF0; /*!< Force Interrupts */ + __IOM uint32_t INTS0; /*!< Interrupt Status for IRQ 0 */ + __IOM uint32_t INTR1; /*!< Interrupt Status (raw) */ + __IOM uint32_t INTE1; /*!< Interrupt Enables for IRQ 1 */ + __IOM uint32_t INTF1; /*!< Force Interrupts */ + __IOM uint32_t INTS1; /*!< Interrupt Status for IRQ 1 */ + __IOM uint32_t INTR2; /*!< Interrupt Status (raw) */ + __IOM uint32_t INTE2; /*!< Interrupt Enables for IRQ 2 */ + __IOM uint32_t INTF2; /*!< Force Interrupts */ + __IOM uint32_t INTS2; /*!< Interrupt Status for IRQ 2 */ + __IOM uint32_t INTR3; /*!< Interrupt Status (raw) */ + __IOM uint32_t INTE3; /*!< Interrupt Enables for IRQ 3 */ + __IOM uint32_t INTF3; /*!< Force Interrupts */ + __IOM uint32_t INTS3; /*!< Interrupt Status for IRQ 3 */ + __IOM uint32_t TIMER0; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t TIMER1; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t TIMER2; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t TIMER3; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ + assertions at a rate set by ((X/Y) * sys_clk). This equation + is evaluated every sys_clk cycles and therefore can only + generate TREQs at a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t MULTI_CHAN_TRIGGER; /*!< Trigger one or more channels simultaneously */ + __IOM uint32_t SNIFF_CTRL; /*!< Sniffer Control */ + __IOM uint32_t SNIFF_DATA; /*!< Data accumulator for sniff hardware */ + __IM uint32_t RESERVED; + __IOM uint32_t FIFO_LEVELS; /*!< Debug RAF, WAF, TDF levels */ + __IOM uint32_t CHAN_ABORT; /*!< Abort an in-progress transfer sequence on one or more channels */ + __IOM uint32_t N_CHANNELS; /*!< The number of channels this DMA instance is equipped with. This + DMA supports up to 16 hardware channels, but can be configured + with as few as one, to minimise silicon area. */ + __IM uint32_t RESERVED1[5]; + __IOM uint32_t SECCFG_CH0; /*!< Security configuration for channel 0. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH1; /*!< Security configuration for channel 1. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH2; /*!< Security configuration for channel 2. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH3; /*!< Security configuration for channel 3. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH4; /*!< Security configuration for channel 4. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH5; /*!< Security configuration for channel 5. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH6; /*!< Security configuration for channel 6. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH7; /*!< Security configuration for channel 7. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH8; /*!< Security configuration for channel 8. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH9; /*!< Security configuration for channel 9. Control whether this channel + performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH10; /*!< Security configuration for channel 10. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH11; /*!< Security configuration for channel 11. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH12; /*!< Security configuration for channel 12. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH13; /*!< Security configuration for channel 13. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH14; /*!< Security configuration for channel 14. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_CH15; /*!< Security configuration for channel 15. Control whether this + channel performs Secure/Non-secure and Privileged/Unprivileged + bus accesses. If this channel generates bus accesses of + some security level, an access of at least that level (in + the order S+P > S+U > NS+P > NS+U) is required to program, + trigger, abort, check the status of, interrupt on or acknowledge + the interrupt of this channel. This register automatically + locks down (becomes read-only) once software starts to + configure the channel. This register is world-readable, + but is writable only from a Secure, Privileged context. */ + __IOM uint32_t SECCFG_IRQ0; /*!< Security configuration for IRQ 0. Control whether the IRQ permits + configuration by Non-secure/Unprivileged contexts, and + whether it can observe Secure/Privileged channel interrupt + flags. */ + __IOM uint32_t SECCFG_IRQ1; /*!< Security configuration for IRQ 1. Control whether the IRQ permits + configuration by Non-secure/Unprivileged contexts, and + whether it can observe Secure/Privileged channel interrupt + flags. */ + __IOM uint32_t SECCFG_IRQ2; /*!< Security configuration for IRQ 2. Control whether the IRQ permits + configuration by Non-secure/Unprivileged contexts, and + whether it can observe Secure/Privileged channel interrupt + flags. */ + __IOM uint32_t SECCFG_IRQ3; /*!< Security configuration for IRQ 3. Control whether the IRQ permits + configuration by Non-secure/Unprivileged contexts, and + whether it can observe Secure/Privileged channel interrupt + flags. */ + __IOM uint32_t SECCFG_MISC; /*!< Miscellaneous security configuration */ + __IM uint32_t RESERVED2[11]; + __IOM uint32_t MPU_CTRL; /*!< Control register for DMA MPU. Accessible only from a Privileged + context. */ + __IOM uint32_t MPU_BAR0; /*!< Base address register for MPU region 0. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR0; /*!< Limit address register for MPU region 0. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IOM uint32_t MPU_BAR1; /*!< Base address register for MPU region 1. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR1; /*!< Limit address register for MPU region 1. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IOM uint32_t MPU_BAR2; /*!< Base address register for MPU region 2. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR2; /*!< Limit address register for MPU region 2. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IOM uint32_t MPU_BAR3; /*!< Base address register for MPU region 3. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR3; /*!< Limit address register for MPU region 3. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IOM uint32_t MPU_BAR4; /*!< Base address register for MPU region 4. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR4; /*!< Limit address register for MPU region 4. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IOM uint32_t MPU_BAR5; /*!< Base address register for MPU region 5. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR5; /*!< Limit address register for MPU region 5. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IOM uint32_t MPU_BAR6; /*!< Base address register for MPU region 6. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR6; /*!< Limit address register for MPU region 6. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IOM uint32_t MPU_BAR7; /*!< Base address register for MPU region 7. Writable only from a + Secure, Privileged context. */ + __IOM uint32_t MPU_LAR7; /*!< Limit address register for MPU region 7. Writable only from + a Secure, Privileged context, with the exception of the + P bit. */ + __IM uint32_t RESERVED3[175]; + __IOM uint32_t CH0_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH0_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED4[14]; + __IOM uint32_t CH1_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH1_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED5[14]; + __IOM uint32_t CH2_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH2_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED6[14]; + __IOM uint32_t CH3_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH3_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED7[14]; + __IOM uint32_t CH4_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH4_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED8[14]; + __IOM uint32_t CH5_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH5_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED9[14]; + __IOM uint32_t CH6_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH6_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED10[14]; + __IOM uint32_t CH7_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH7_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t CH8_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH8_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED12[14]; + __IOM uint32_t CH9_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH9_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED13[14]; + __IOM uint32_t CH10_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH10_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED14[14]; + __IOM uint32_t CH11_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH11_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED15[14]; + __IOM uint32_t CH12_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH12_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED16[14]; + __IOM uint32_t CH13_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH13_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED17[14]; + __IOM uint32_t CH14_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH14_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ + __IM uint32_t RESERVED18[14]; + __IOM uint32_t CH15_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA + expects it can perform on the peripheral without overflow/underflow. + Write any value: clears the counter, and cause channel + to re-initiate DREQ handshake. */ + __IOM uint32_t CH15_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length + of the next transfer */ +} DMA_Type; /*!< Size = 3016 (0xbc8) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controls time and alarms + + time is a 64 bit value indicating the time since power-on + + timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr + + An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing (TIMER0) + */ + +typedef struct { /*!< TIMER0 Structure */ + __IOM uint32_t TIMEHW; /*!< Write to bits 63:32 of time always write timelw before timehw */ + __IOM uint32_t TIMELW; /*!< Write to bits 31:0 of time writes do not get copied to time + until timehw is written */ + __IOM uint32_t TIMEHR; /*!< Read from bits 63:32 of time always read timelr before timehr */ + __IOM uint32_t TIMELR; /*!< Read from bits 31:0 of time */ + __IOM uint32_t ALARM0; /*!< Arm alarm 0, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM0 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ALARM1; /*!< Arm alarm 1, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM1 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ALARM2; /*!< Arm alarm 2, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM2 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ALARM3; /*!< Arm alarm 3, and configure the time it will fire. Once armed, + the alarm fires when TIMER_ALARM3 == TIMELR. The alarm + will disarm itself once it fires, and can be disarmed early + using the ARMED status register. */ + __IOM uint32_t ARMED; /*!< Indicates the armed/disarmed status of each alarm. A write to + the corresponding ALARMx register arms the alarm. Alarms + automatically disarm upon firing, but writing ones here + will disarm immediately without waiting to fire. */ + __IOM uint32_t TIMERAWH; /*!< Raw read from bits 63:32 of time (no side effects) */ + __IOM uint32_t TIMERAWL; /*!< Raw read from bits 31:0 of time (no side effects) */ + __IOM uint32_t DBGPAUSE; /*!< Set bits high to enable pause when the corresponding debug ports + are active */ + __IOM uint32_t PAUSE; /*!< Set high to pause the timer */ + __IOM uint32_t LOCKED; /*!< Set locked bit to disable write access to timer Once set, cannot + be cleared (without a reset) */ + __IOM uint32_t SOURCE; /*!< Selects the source for the timer. Defaults to the normal tick + configured in the ticks block (typically configured to + 1 microsecond). Writing to 1 will ignore the tick and count + clk_sys cycles instead. */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} TIMER0_Type; /*!< Size = 76 (0x4c) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Simple PWM (PWM) + */ + +typedef struct { /*!< PWM Structure */ + __IOM uint32_t CH0_CSR; /*!< Control and status register */ + __IOM uint32_t CH0_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH0_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH0_CC; /*!< Counter compare values */ + __IOM uint32_t CH0_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH1_CSR; /*!< Control and status register */ + __IOM uint32_t CH1_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH1_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH1_CC; /*!< Counter compare values */ + __IOM uint32_t CH1_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH2_CSR; /*!< Control and status register */ + __IOM uint32_t CH2_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH2_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH2_CC; /*!< Counter compare values */ + __IOM uint32_t CH2_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH3_CSR; /*!< Control and status register */ + __IOM uint32_t CH3_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH3_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH3_CC; /*!< Counter compare values */ + __IOM uint32_t CH3_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH4_CSR; /*!< Control and status register */ + __IOM uint32_t CH4_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH4_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH4_CC; /*!< Counter compare values */ + __IOM uint32_t CH4_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH5_CSR; /*!< Control and status register */ + __IOM uint32_t CH5_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH5_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH5_CC; /*!< Counter compare values */ + __IOM uint32_t CH5_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH6_CSR; /*!< Control and status register */ + __IOM uint32_t CH6_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH6_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH6_CC; /*!< Counter compare values */ + __IOM uint32_t CH6_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH7_CSR; /*!< Control and status register */ + __IOM uint32_t CH7_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH7_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH7_CC; /*!< Counter compare values */ + __IOM uint32_t CH7_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH8_CSR; /*!< Control and status register */ + __IOM uint32_t CH8_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH8_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH8_CC; /*!< Counter compare values */ + __IOM uint32_t CH8_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH9_CSR; /*!< Control and status register */ + __IOM uint32_t CH9_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH9_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH9_CC; /*!< Counter compare values */ + __IOM uint32_t CH9_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH10_CSR; /*!< Control and status register */ + __IOM uint32_t CH10_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH10_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH10_CC; /*!< Counter compare values */ + __IOM uint32_t CH10_TOP; /*!< Counter wrap value */ + __IOM uint32_t CH11_CSR; /*!< Control and status register */ + __IOM uint32_t CH11_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting + rate is system clock frequency divided by this number. + Fractional division uses simple 1st-order sigma-delta. */ + __IOM uint32_t CH11_CTR; /*!< Direct access to the PWM counter */ + __IOM uint32_t CH11_CC; /*!< Counter compare values */ + __IOM uint32_t CH11_TOP; /*!< Counter wrap value */ + __IOM uint32_t EN; /*!< This register aliases the CSR_EN bits for all channels. Writing + to this register allows multiple channels to be enabled + or disabled simultaneously, so they can run in perfect + sync. For each channel, there is only one physical EN register + bit, which can be accessed through here or CHx_CSR. */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t IRQ0_INTE; /*!< Interrupt Enable for irq0 */ + __IOM uint32_t IRQ0_INTF; /*!< Interrupt Force for irq0 */ + __IOM uint32_t IRQ0_INTS; /*!< Interrupt status after masking & forcing for irq0 */ + __IOM uint32_t IRQ1_INTE; /*!< Interrupt Enable for irq1 */ + __IOM uint32_t IRQ1_INTF; /*!< Interrupt Force for irq1 */ + __IOM uint32_t IRQ1_INTS; /*!< Interrupt status after masking & forcing for irq1 */ +} PWM_Type; /*!< Size = 272 (0x110) */ + + + +/* =========================================================================================================================== */ +/* ================ ADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Control and data interface to SAR ADC (ADC) + */ + +typedef struct { /*!< ADC Structure */ + __IOM uint32_t CS; /*!< ADC Control and Status */ + __IOM uint32_t RESULT; /*!< Result of most recent ADC conversion */ + __IOM uint32_t FCS; /*!< FIFO control and status */ + __IOM uint32_t FIFO; /*!< Conversion result FIFO */ + __IOM uint32_t DIV; /*!< Clock divider. If non-zero, CS_START_MANY will start conversions + at regular intervals rather than back-to-back. The divider + is reset when either of these fields are written. Total + period is 1 + INT + FRAC / 256 */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} ADC_Type; /*!< Size = 36 (0x24) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DW_apb_i2c address block + + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): + + IC_ULTRA_FAST_MODE ................ 0x0 + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 + IC_UFM_SCL_LOW_COUNT .............. 0x0008 + IC_UFM_SCL_HIGH_COUNT ............. 0x0006 + IC_TX_TL .......................... 0x0 + IC_TX_CMD_BLOCK ................... 0x1 + IC_HAS_DMA ........................ 0x1 + IC_HAS_ASYNC_FIFO ................. 0x0 + IC_SMBUS_ARP ...................... 0x0 + IC_FIRST_DATA_BYTE_STATUS ......... 0x1 + IC_INTR_IO ........................ 0x1 + IC_MASTER_MODE .................... 0x1 + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 + IC_INTR_POL ....................... 0x1 + IC_OPTIONAL_SAR ................... 0x0 + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 + IC_DEFAULT_SLAVE_ADDR ............. 0x055 + IC_DEFAULT_HS_SPKLEN .............. 0x1 + IC_FS_SCL_HIGH_COUNT .............. 0x0006 + IC_HS_SCL_LOW_COUNT ............... 0x0008 + IC_DEVICE_ID_VALUE ................ 0x0 + IC_10BITADDR_MASTER ............... 0x0 + IC_CLK_FREQ_OPTIMIZATION .......... 0x0 + IC_DEFAULT_FS_SPKLEN .............. 0x7 + IC_ADD_ENCODED_PARAMS ............. 0x0 + IC_DEFAULT_SDA_HOLD ............... 0x000001 + IC_DEFAULT_SDA_SETUP .............. 0x64 + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 + IC_CLOCK_PERIOD ................... 100 + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 + IC_RESTART_EN ..................... 0x1 + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 + IC_BUS_CLEAR_FEATURE .............. 0x0 + IC_CAP_LOADING .................... 100 + IC_FS_SCL_LOW_COUNT ............... 0x000d + APB_DATA_WIDTH .................... 32 + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_SLV_DATA_NACK_ONLY ............. 0x1 + IC_10BITADDR_SLAVE ................ 0x0 + IC_CLK_TYPE ....................... 0x0 + IC_SMBUS_UDID_MSB ................. 0x0 + IC_SMBUS_SUSPEND_ALERT ............ 0x0 + IC_HS_SCL_HIGH_COUNT .............. 0x0006 + IC_SLV_RESTART_DET_EN ............. 0x1 + IC_SMBUS .......................... 0x0 + IC_OPTIONAL_SAR_DEFAULT ........... 0x0 + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 + IC_USE_COUNTS ..................... 0x0 + IC_RX_BUFFER_DEPTH ................ 16 + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff + IC_RX_FULL_HLD_BUS_EN ............. 0x1 + IC_SLAVE_DISABLE .................. 0x1 + IC_RX_TL .......................... 0x0 + IC_DEVICE_ID ...................... 0x0 + IC_HC_COUNT_VALUES ................ 0x0 + I2C_DYNAMIC_TAR_UPDATE ............ 0 + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff + IC_HS_MASTER_CODE ................. 0x1 + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff + IC_SS_SCL_HIGH_COUNT .............. 0x0028 + IC_SS_SCL_LOW_COUNT ............... 0x002f + IC_MAX_SPEED_MODE ................. 0x2 + IC_STAT_FOR_CLK_STRETCH ........... 0x0 + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 + IC_DEFAULT_UFM_SPKLEN ............. 0x1 + IC_TX_BUFFER_DEPTH ................ 16 (I2C0) + */ + +typedef struct { /*!< I2C0 Structure */ + __IOM uint32_t IC_CON; /*!< I2C Control Register. This register can be written only when + the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] + register being set to 0. Writes at other times have no + effect. Read/Write Access: - bit 10 is read only. - bit + 11 is read only - bit 16 is read only - bit 17 is read + only - bits 18 and 19 are read only. */ + __IOM uint32_t IC_TAR; /*!< I2C Target Address Register This register is 12 bits wide, and + bits 31:12 are reserved. This register can be written to + only when IC_ENABLE[0] is set to 0. Note: If the software + or application is aware that the DW_apb_i2c is not using + the TAR address for the pending commands in the Tx FIFO, + then it is possible to update the TAR address even while + the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not + necessary to perform any write to this register if DW_apb_i2c + is enabled as an I2C slave only. */ + __IOM uint32_t IC_SAR; /*!< I2C Slave Address Register */ + __IM uint32_t RESERVED; + __IOM uint32_t IC_DATA_CMD; /*!< I2C Rx/Tx Data Buffer and Command Register; this is the register + the CPU writes to when filling the TX FIFO and the CPU + reads from when retrieving bytes from RX FIFO. The size + of the register changes as follows: Write: - 11 bits when + IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 + Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 + bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order + for the DW_apb_i2c to continue acknowledging reads, a read + command should be written for every byte that is to be + received; otherwise the DW_apb_i2c will stop acknowledging. */ + __IOM uint32_t IC_SS_SCL_HCNT; /*!< Standard Speed I2C Clock SCL High Count Register */ + __IOM uint32_t IC_SS_SCL_LCNT; /*!< Standard Speed I2C Clock SCL Low Count Register */ + __IOM uint32_t IC_FS_SCL_HCNT; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register */ + __IOM uint32_t IC_FS_SCL_LCNT; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t IC_INTR_STAT; /*!< I2C Interrupt Status Register Each bit in this register has + a corresponding mask bit in the IC_INTR_MASK register. + These bits are cleared by reading the matching interrupt + clear register. The unmasked raw versions of these bits + are available in the IC_RAW_INTR_STAT register. */ + __IOM uint32_t IC_INTR_MASK; /*!< I2C Interrupt Mask Register. These bits mask their corresponding + interrupt status bits. This register is active low; a value + of 0 masks the interrupt, whereas a value of 1 unmasks + the interrupt. */ + __IOM uint32_t IC_RAW_INTR_STAT; /*!< I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, + these bits are not masked so they always show the true + status of the DW_apb_i2c. */ + __IOM uint32_t IC_RX_TL; /*!< I2C Receive FIFO Threshold Register */ + __IOM uint32_t IC_TX_TL; /*!< I2C Transmit FIFO Threshold Register */ + __IOM uint32_t IC_CLR_INTR; /*!< Clear Combined and Individual Interrupt Register */ + __IOM uint32_t IC_CLR_RX_UNDER; /*!< Clear RX_UNDER Interrupt Register */ + __IOM uint32_t IC_CLR_RX_OVER; /*!< Clear RX_OVER Interrupt Register */ + __IOM uint32_t IC_CLR_TX_OVER; /*!< Clear TX_OVER Interrupt Register */ + __IOM uint32_t IC_CLR_RD_REQ; /*!< Clear RD_REQ Interrupt Register */ + __IOM uint32_t IC_CLR_TX_ABRT; /*!< Clear TX_ABRT Interrupt Register */ + __IOM uint32_t IC_CLR_RX_DONE; /*!< Clear RX_DONE Interrupt Register */ + __IOM uint32_t IC_CLR_ACTIVITY; /*!< Clear ACTIVITY Interrupt Register */ + __IOM uint32_t IC_CLR_STOP_DET; /*!< Clear STOP_DET Interrupt Register */ + __IOM uint32_t IC_CLR_START_DET; /*!< Clear START_DET Interrupt Register */ + __IOM uint32_t IC_CLR_GEN_CALL; /*!< Clear GEN_CALL Interrupt Register */ + __IOM uint32_t IC_ENABLE; /*!< I2C Enable Register */ + __IOM uint32_t IC_STATUS; /*!< I2C Status Register This is a read-only register used to indicate + the current transfer status and FIFO status. The status + register may be read at any time. None of the bits in this + register request an interrupt. When the I2C is disabled + by writing 0 in bit 0 of the IC_ENABLE register: - Bits + 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When + the master or slave state machines goes to idle and ic_en=0: + - Bits 5 and 6 are set to 0 */ + __IOM uint32_t IC_TXFLR; /*!< I2C Transmit FIFO Level Register This register contains the + number of valid data entries in the transmit FIFO buffer. + It is cleared whenever: - The I2C is disabled - There is + a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT + register - The slave bulk transmit mode is aborted The + register increments whenever data is placed into the transmit + FIFO and decrements when data is taken from the transmit + FIFO. */ + __IOM uint32_t IC_RXFLR; /*!< I2C Receive FIFO Level Register This register contains the number + of valid data entries in the receive FIFO buffer. It is + cleared whenever: - The I2C is disabled - Whenever there + is a transmit abort caused by any of the events tracked + in IC_TX_ABRT_SOURCE The register increments whenever data + is placed into the receive FIFO and decrements when data + is taken from the receive FIFO. */ + __IOM uint32_t IC_SDA_HOLD; /*!< I2C SDA Hold Time Length Register The bits [15:0] of this register + are used to control the hold time of SDA during transmit + in both slave and master mode (after SCL goes from HIGH + to LOW). The bits [23:16] of this register are used to + extend the SDA transition (if any) whenever SCL is HIGH + in the receiver in either master or slave mode. Writes + to this register succeed only when IC_ENABLE[0]=0. The + values in this register are in units of ic_clk period. + The value programmed in IC_SDA_TX_HOLD must be greater + than the minimum hold time in each mode (one cycle in master + mode, seven cycles in slave mode) for the value to be implemented. + The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) + cannot exceed at any time the duration of the low part + of scl. Therefore the programmed value cannot be larger + than N_SCL_LOW-2, where N_SCL_LOW is the duration of the + low part of the scl period measured in ic_clk cycles. */ + __IOM uint32_t IC_TX_ABRT_SOURCE; /*!< I2C Transmit Abort Source Register This register has 32 bits + that indicate the source of the TX_ABRT bit. Except for + Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT + register or the IC_CLR_INTR register is read. To clear + Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed + first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL + bit must be cleared (IC_TAR[11]), or the GC_OR_START bit + must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT + is fixed, then this bit can be cleared in the same manner + as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT + is not fixed before attempting to clear this bit, Bit 9 + clears for one cycle and is then re-asserted. */ + __IOM uint32_t IC_SLV_DATA_NACK_ONLY; /*!< Generate Slave Data NACK Register The register is used to generate + a NACK for the data part of a transfer when DW_apb_i2c + is acting as a slave-receiver. This register only exists + when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When + this parameter disabled, this register does not exist and + writing to the register's address has no effect. A write + can occur on this register if both of the following conditions + are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - + Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] + is a register read-back location for the internal slv_activity + signal; the user should poll this before writing the ic_slv_data_nack_onl + bit. */ + __IOM uint32_t IC_DMA_CR; /*!< DMA Control Register The register is used to enable the DMA + Controller interface operation. There is a separate bit + for transmit and receive. This can be programmed regardless + of the state of IC_ENABLE. */ + __IOM uint32_t IC_DMA_TDLR; /*!< DMA Transmit Data Level Register */ + __IOM uint32_t IC_DMA_RDLR; /*!< I2C Receive Data Level Register */ + __IOM uint32_t IC_SDA_SETUP; /*!< I2C SDA Setup Register This register controls the amount of + time delay (in terms of number of ic_clk clock periods) + introduced in the rising edge of SCL - relative to SDA + changing - when DW_apb_i2c services a read request in a + slave-transmitter operation. The relevant I2C requirement + is tSU:DAT (note 4) as detailed in the I2C Bus Specification. + This register must be programmed with a value equal to + or greater than 2. Writes to this register succeed only + when IC_ENABLE[0] = 0. Note: The length of setup time is + calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], + so if the user requires 10 ic_clk periods of setup time, + they should program a value of 11. The IC_SDA_SETUP register + is only used by the DW_apb_i2c when operating as a slave + transmitter. */ + __IOM uint32_t IC_ACK_GENERAL_CALL; /*!< I2C ACK General Call Register The register controls whether + DW_apb_i2c responds with a ACK or NACK when it receives + an I2C General Call address. This register is applicable + only when the DW_apb_i2c is in slave mode. */ + __IOM uint32_t IC_ENABLE_STATUS; /*!< I2C Enable Status Register The register is used to report the + DW_apb_i2c hardware status when the IC_ENABLE[0] register + is set from 1 to 0; that is, when DW_apb_i2c is disabled. + If IC_ENABLE[0] has been set to 1, bits 2:1 are forced + to 0, and bit 0 is forced to 1. If IC_ENABLE[0] has been + set to 0, bits 2:1 is only be valid as soon as bit 0 is + read as '0'. Note: When IC_ENABLE[0] has been set to 0, + a delay occurs for bit 0 to be read as 0 because disabling + the DW_apb_i2c depends on I2C bus activities. */ + __IOM uint32_t IC_FS_SPKLEN; /*!< I2C SS, FS or FM+ spike suppression limit This register is used + to store the duration, measured in ic_clk cycles, of the + longest spike that is filtered out by the spike suppression + logic when the component is operating in SS, FS or FM+ + modes. The relevant I2C requirement is tSP (table 4) as + detailed in the I2C Bus Specification. This register must + be programmed with a minimum value of 1. */ + __IM uint32_t RESERVED2; + __IOM uint32_t IC_CLR_RESTART_DET; /*!< Clear RESTART_DET Interrupt Register */ + __IM uint32_t RESERVED3[18]; + __IOM uint32_t IC_COMP_PARAM_1; /*!< Component Parameter Register 1 Note This register is not implemented + and therefore reads as 0. If it was implemented it would + be a constant read-only register that contains encoded + information about the component's parameter settings. Fields + shown below are the settings for those parameters */ + __IOM uint32_t IC_COMP_VERSION; /*!< I2C Component Version Register */ + __IOM uint32_t IC_COMP_TYPE; /*!< I2C Component Type Register */ +} I2C0_Type; /*!< Size = 256 (0x100) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI0 (SPI0) + */ + +typedef struct { /*!< SPI0 Structure */ + __IOM uint32_t SSPCR0; /*!< Control register 0, SSPCR0 on page 3-4 */ + __IOM uint32_t SSPCR1; /*!< Control register 1, SSPCR1 on page 3-5 */ + __IOM uint32_t SSPDR; /*!< Data register, SSPDR on page 3-6 */ + __IOM uint32_t SSPSR; /*!< Status register, SSPSR on page 3-7 */ + __IOM uint32_t SSPCPSR; /*!< Clock prescale register, SSPCPSR on page 3-8 */ + __IOM uint32_t SSPIMSC; /*!< Interrupt mask set or clear register, SSPIMSC on page 3-9 */ + __IOM uint32_t SSPRIS; /*!< Raw interrupt status register, SSPRIS on page 3-10 */ + __IOM uint32_t SSPMIS; /*!< Masked interrupt status register, SSPMIS on page 3-11 */ + __IOM uint32_t SSPICR; /*!< Interrupt clear register, SSPICR on page 3-11 */ + __IOM uint32_t SSPDMACR; /*!< DMA control register, SSPDMACR on page 3-12 */ + __IM uint32_t RESERVED[1006]; + __IOM uint32_t SSPPERIPHID0; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPERIPHID1; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPERIPHID2; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPERIPHID3; /*!< Peripheral identification registers, SSPPeriphID0-3 on page + 3-13 */ + __IOM uint32_t SSPPCELLID0; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + __IOM uint32_t SSPPCELLID1; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + __IOM uint32_t SSPPCELLID2; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ + __IOM uint32_t SSPPCELLID3; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ +} SPI0_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ PIO0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable IO block (PIO0) + */ + +typedef struct { /*!< PIO0 Structure */ + __IOM uint32_t CTRL; /*!< PIO control register */ + __IOM uint32_t FSTAT; /*!< FIFO status register */ + __IOM uint32_t FDEBUG; /*!< FIFO debug register */ + __IOM uint32_t FLEVEL; /*!< FIFO levels */ + __IOM uint32_t TXF0; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t TXF1; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t TXF2; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t TXF3; /*!< Direct write access to the TX FIFO for this state machine. Each + write pushes one word to the FIFO. Attempting to write + to a full FIFO has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ + __IOM uint32_t RXF0; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t RXF1; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t RXF2; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t RXF3; /*!< Direct read access to the RX FIFO for this state machine. Each + read pops one word from the FIFO. Attempting to read from + an empty FIFO has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for this FIFO. The + data returned to the system on a read from an empty FIFO + is undefined. */ + __IOM uint32_t IRQ; /*!< State machine IRQ flags register. Write 1 to clear. There are + eight state machine IRQ flags, which can be set, cleared, + and waited on by the state machines. There's no fixed association + between flags and state machines -- any state machine can + use any flag. Any of the eight flags can be used for timing + synchronisation between state machines, using IRQ and WAIT + instructions. Any combination of the eight flags can also + routed out to either of the two system-level interrupt + requests, alongside FIFO status interrupts -- see e.g. + IRQ0_INTE. */ + __IOM uint32_t IRQ_FORCE; /*!< Writing a 1 to each of these bits will forcibly assert the corresponding + IRQ. Note this is different to the INTF register: writing + here affects PIO internal state. INTF just asserts the + processor-facing IRQ signal for testing ISRs, and is not + visible to the state machines. */ + __IOM uint32_t INPUT_SYNC_BYPASS; /*!< There is a 2-flipflop synchronizer on each GPIO input, which + protects PIO logic from metastabilities. This increases + input delay, and for fast synchronous IO (e.g. SPI) these + synchronizers may need to be bypassed. Each bit in this + register corresponds to one GPIO. 0 -> input is synchronized + (default) 1 -> synchronizer is bypassed If in doubt, leave + this register as all zeroes. */ + __IOM uint32_t DBG_PADOUT; /*!< Read to sample the pad output values PIO is currently driving + to the GPIOs. On RP2040 there are 30 GPIOs, so the two + most significant bits are hardwired to 0. */ + __IOM uint32_t DBG_PADOE; /*!< Read to sample the pad output enables (direction) PIO is currently + driving to the GPIOs. On RP2040 there are 30 GPIOs, so + the two most significant bits are hardwired to 0. */ + __IOM uint32_t DBG_CFGINFO; /*!< The PIO hardware has some free parameters that may vary between + chip products. These should be provided in the chip datasheet, + but are also exposed here. */ + __IOM uint32_t INSTR_MEM0; /*!< Write-only access to instruction memory location 0 */ + __IOM uint32_t INSTR_MEM1; /*!< Write-only access to instruction memory location 1 */ + __IOM uint32_t INSTR_MEM2; /*!< Write-only access to instruction memory location 2 */ + __IOM uint32_t INSTR_MEM3; /*!< Write-only access to instruction memory location 3 */ + __IOM uint32_t INSTR_MEM4; /*!< Write-only access to instruction memory location 4 */ + __IOM uint32_t INSTR_MEM5; /*!< Write-only access to instruction memory location 5 */ + __IOM uint32_t INSTR_MEM6; /*!< Write-only access to instruction memory location 6 */ + __IOM uint32_t INSTR_MEM7; /*!< Write-only access to instruction memory location 7 */ + __IOM uint32_t INSTR_MEM8; /*!< Write-only access to instruction memory location 8 */ + __IOM uint32_t INSTR_MEM9; /*!< Write-only access to instruction memory location 9 */ + __IOM uint32_t INSTR_MEM10; /*!< Write-only access to instruction memory location 10 */ + __IOM uint32_t INSTR_MEM11; /*!< Write-only access to instruction memory location 11 */ + __IOM uint32_t INSTR_MEM12; /*!< Write-only access to instruction memory location 12 */ + __IOM uint32_t INSTR_MEM13; /*!< Write-only access to instruction memory location 13 */ + __IOM uint32_t INSTR_MEM14; /*!< Write-only access to instruction memory location 14 */ + __IOM uint32_t INSTR_MEM15; /*!< Write-only access to instruction memory location 15 */ + __IOM uint32_t INSTR_MEM16; /*!< Write-only access to instruction memory location 16 */ + __IOM uint32_t INSTR_MEM17; /*!< Write-only access to instruction memory location 17 */ + __IOM uint32_t INSTR_MEM18; /*!< Write-only access to instruction memory location 18 */ + __IOM uint32_t INSTR_MEM19; /*!< Write-only access to instruction memory location 19 */ + __IOM uint32_t INSTR_MEM20; /*!< Write-only access to instruction memory location 20 */ + __IOM uint32_t INSTR_MEM21; /*!< Write-only access to instruction memory location 21 */ + __IOM uint32_t INSTR_MEM22; /*!< Write-only access to instruction memory location 22 */ + __IOM uint32_t INSTR_MEM23; /*!< Write-only access to instruction memory location 23 */ + __IOM uint32_t INSTR_MEM24; /*!< Write-only access to instruction memory location 24 */ + __IOM uint32_t INSTR_MEM25; /*!< Write-only access to instruction memory location 25 */ + __IOM uint32_t INSTR_MEM26; /*!< Write-only access to instruction memory location 26 */ + __IOM uint32_t INSTR_MEM27; /*!< Write-only access to instruction memory location 27 */ + __IOM uint32_t INSTR_MEM28; /*!< Write-only access to instruction memory location 28 */ + __IOM uint32_t INSTR_MEM29; /*!< Write-only access to instruction memory location 29 */ + __IOM uint32_t INSTR_MEM30; /*!< Write-only access to instruction memory location 30 */ + __IOM uint32_t INSTR_MEM31; /*!< Write-only access to instruction memory location 31 */ + __IOM uint32_t SM0_CLKDIV; /*!< Clock divisor register for state machine 0 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM0_EXECCTRL; /*!< Execution/behavioural settings for state machine 0 */ + __IOM uint32_t SM0_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 0 */ + __IOM uint32_t SM0_ADDR; /*!< Current instruction address of state machine 0 */ + __IOM uint32_t SM0_INSTR; /*!< Read to see the instruction currently addressed by state machine + 0's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM0_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t SM1_CLKDIV; /*!< Clock divisor register for state machine 1 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM1_EXECCTRL; /*!< Execution/behavioural settings for state machine 1 */ + __IOM uint32_t SM1_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 1 */ + __IOM uint32_t SM1_ADDR; /*!< Current instruction address of state machine 1 */ + __IOM uint32_t SM1_INSTR; /*!< Read to see the instruction currently addressed by state machine + 1's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM1_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t SM2_CLKDIV; /*!< Clock divisor register for state machine 2 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM2_EXECCTRL; /*!< Execution/behavioural settings for state machine 2 */ + __IOM uint32_t SM2_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 2 */ + __IOM uint32_t SM2_ADDR; /*!< Current instruction address of state machine 2 */ + __IOM uint32_t SM2_INSTR; /*!< Read to see the instruction currently addressed by state machine + 2's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM2_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t SM3_CLKDIV; /*!< Clock divisor register for state machine 3 Frequency = clock + freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ + __IOM uint32_t SM3_EXECCTRL; /*!< Execution/behavioural settings for state machine 3 */ + __IOM uint32_t SM3_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state + machine 3 */ + __IOM uint32_t SM3_ADDR; /*!< Current instruction address of state machine 3 */ + __IOM uint32_t SM3_INSTR; /*!< Read to see the instruction currently addressed by state machine + 3's program counter Write to execute an instruction immediately + (including jumps) and then resume execution. */ + __IOM uint32_t SM3_PINCTRL; /*!< State machine pin control */ + __IOM uint32_t RXF0_PUTGET0; /*!< Direct read/write access to entry 0 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF0_PUTGET1; /*!< Direct read/write access to entry 1 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF0_PUTGET2; /*!< Direct read/write access to entry 2 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF0_PUTGET3; /*!< Direct read/write access to entry 3 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF1_PUTGET0; /*!< Direct read/write access to entry 0 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF1_PUTGET1; /*!< Direct read/write access to entry 1 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF1_PUTGET2; /*!< Direct read/write access to entry 2 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF1_PUTGET3; /*!< Direct read/write access to entry 3 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF2_PUTGET0; /*!< Direct read/write access to entry 0 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF2_PUTGET1; /*!< Direct read/write access to entry 1 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF2_PUTGET2; /*!< Direct read/write access to entry 2 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF2_PUTGET3; /*!< Direct read/write access to entry 3 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF3_PUTGET0; /*!< Direct read/write access to entry 0 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF3_PUTGET1; /*!< Direct read/write access to entry 1 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF3_PUTGET2; /*!< Direct read/write access to entry 2 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t RXF3_PUTGET3; /*!< Direct read/write access to entry 3 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU + xor SHIFTCTRL_FJOIN_RX_GET is set. */ + __IOM uint32_t GPIOBASE; /*!< Relocate GPIO 0 (from PIO's point of view) in the system GPIO + numbering, to access more than 32 GPIOs from PIO. Only + the values 0 and 16 are supported (only bit 4 is writable). */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t IRQ0_INTE; /*!< Interrupt Enable for irq0 */ + __IOM uint32_t IRQ0_INTF; /*!< Interrupt Force for irq0 */ + __IOM uint32_t IRQ0_INTS; /*!< Interrupt status after masking & forcing for irq0 */ + __IOM uint32_t IRQ1_INTE; /*!< Interrupt Enable for irq1 */ + __IOM uint32_t IRQ1_INTF; /*!< Interrupt Force for irq1 */ + __IOM uint32_t IRQ1_INTS; /*!< Interrupt status after masking & forcing for irq1 */ +} PIO0_Type; /*!< Size = 392 (0x188) */ + + + +/* =========================================================================================================================== */ +/* ================ BUSCTRL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Register block for busfabric control signals and performance counters (BUSCTRL) + */ + +typedef struct { /*!< BUSCTRL Structure */ + __IOM uint32_t BUS_PRIORITY; /*!< Set the priority of each master for bus arbitration. */ + __IOM uint32_t BUS_PRIORITY_ACK; /*!< Bus priority acknowledge */ + __IOM uint32_t PERFCTR_EN; /*!< Enable the performance counters. If 0, the performance counters + do not increment. This can be used to precisely start/stop + event sampling around the profiled section of code. The + performance counters are initially disabled, to save energy. */ + __IOM uint32_t PERFCTR0; /*!< Bus fabric performance counter 0 */ + __IOM uint32_t PERFSEL0; /*!< Bus fabric performance event select for PERFCTR0 */ + __IOM uint32_t PERFCTR1; /*!< Bus fabric performance counter 1 */ + __IOM uint32_t PERFSEL1; /*!< Bus fabric performance event select for PERFCTR1 */ + __IOM uint32_t PERFCTR2; /*!< Bus fabric performance counter 2 */ + __IOM uint32_t PERFSEL2; /*!< Bus fabric performance event select for PERFCTR2 */ + __IOM uint32_t PERFCTR3; /*!< Bus fabric performance counter 3 */ + __IOM uint32_t PERFSEL3; /*!< Bus fabric performance event select for PERFCTR3 */ +} BUSCTRL_Type; /*!< Size = 44 (0x2c) */ + + + +/* =========================================================================================================================== */ +/* ================ SIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Single-cycle IO block + Provides core-local and inter-core hardware for the two processors, with single-cycle access. (SIO) + */ + +typedef struct { /*!< SIO Structure */ + __IOM uint32_t CPUID; /*!< Processor core identifier */ + __IOM uint32_t GPIO_IN; /*!< Input value for GPIO0...31. In the Non-secure SIO, Secure-only + GPIOs (as per ACCESSCTRL) appear as zero. */ + __IOM uint32_t GPIO_HI_IN; /*!< Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure + SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. */ + __IM uint32_t RESERVED; + __IOM uint32_t GPIO_OUT; /*!< GPIO0...31 output value */ + __IOM uint32_t GPIO_HI_OUT; /*!< Output value for GPIO32...47, QSPI IOs and USB pins. Write to + set output level (1/0 -> high/low). Reading back gives + the last value written, NOT the input value from the pins. + If core 0 and core 1 both write to GPIO_HI_OUT simultaneously + (or to a SET/CLR/XOR alias), the result is as though the + write from core 0 took place first, and the write from + core 1 was then applied to that intermediate result. In + the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) + ignore writes, and their output status reads back as zero. + This is also true for SET/CLR/XOR aliases of this register. */ + __IOM uint32_t GPIO_OUT_SET; /*!< GPIO0...31 output value set */ + __IOM uint32_t GPIO_HI_OUT_SET; /*!< Output value set for GPIO32..47, QSPI IOs and USB pins. Perform + an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= + wdata` */ + __IOM uint32_t GPIO_OUT_CLR; /*!< GPIO0...31 output value clear */ + __IOM uint32_t GPIO_HI_OUT_CLR; /*!< Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform + an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= + ~wdata` */ + __IOM uint32_t GPIO_OUT_XOR; /*!< GPIO0...31 output value XOR */ + __IOM uint32_t GPIO_HI_OUT_XOR; /*!< Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform + an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT + ^= wdata` */ + __IOM uint32_t GPIO_OE; /*!< GPIO0...31 output enable */ + __IOM uint32_t GPIO_HI_OE; /*!< Output enable value for GPIO32...47, QSPI IOs and USB pins. + Write output enable (1/0 -> output/input). Reading back + gives the last value written. If core 0 and core 1 both + write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR + alias), the result is as though the write from core 0 took + place first, and the write from core 1 was then applied + to that intermediate result. In the Non-secure SIO, Secure-only + GPIOs (as per ACCESSCTRL) ignore writes, and their output + status reads back as zero. This is also true for SET/CLR/XOR + aliases of this register. */ + __IOM uint32_t GPIO_OE_SET; /*!< GPIO0...31 output enable set */ + __IOM uint32_t GPIO_HI_OE_SET; /*!< Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform + an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` */ + __IOM uint32_t GPIO_OE_CLR; /*!< GPIO0...31 output enable clear */ + __IOM uint32_t GPIO_HI_OE_CLR; /*!< Output enable clear for GPIO32...47, QSPI IOs and USB pins. + Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE + &= ~wdata` */ + __IOM uint32_t GPIO_OE_XOR; /*!< GPIO0...31 output enable XOR */ + __IOM uint32_t GPIO_HI_OE_XOR; /*!< Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform + an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= + wdata` */ + __IOM uint32_t FIFO_ST; /*!< Status register for inter-core FIFOs (mailboxes). There is one + FIFO in the core 0 -> core 1 direction, and one core 1 + -> core 0. Both are 32 bits wide and 8 words deep. Core + 0 can see the read side of the 1->0 FIFO (RX), and the + write side of 0->1 FIFO (TX). Core 1 can see the read side + of the 0->1 FIFO (RX), and the write side of 1->0 FIFO + (TX). The SIO IRQ for each core is the logical OR of the + VLD, WOF and ROE fields of its FIFO_ST register. */ + __IOM uint32_t FIFO_WR; /*!< Write access to this core's TX FIFO */ + __IOM uint32_t FIFO_RD; /*!< Read access to this core's RX FIFO */ + __IOM uint32_t SPINLOCK_ST; /*!< Spinlock state A bitmap containing the state of all 32 spinlocks + (1=locked). Mainly intended for debugging. */ + __IM uint32_t RESERVED1[8]; + __IOM uint32_t INTERP0_ACCUM0; /*!< Read/write access to accumulator 0 */ + __IOM uint32_t INTERP0_ACCUM1; /*!< Read/write access to accumulator 1 */ + __IOM uint32_t INTERP0_BASE0; /*!< Read/write access to BASE0 register. */ + __IOM uint32_t INTERP0_BASE1; /*!< Read/write access to BASE1 register. */ + __IOM uint32_t INTERP0_BASE2; /*!< Read/write access to BASE2 register. */ + __IOM uint32_t INTERP0_POP_LANE0; /*!< Read LANE0 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP0_POP_LANE1; /*!< Read LANE1 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP0_POP_FULL; /*!< Read FULL result, and simultaneously write lane results to both + accumulators (POP). */ + __IOM uint32_t INTERP0_PEEK_LANE0; /*!< Read LANE0 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP0_PEEK_LANE1; /*!< Read LANE1 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP0_PEEK_FULL; /*!< Read FULL result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP0_CTRL_LANE0; /*!< Control register for lane 0 */ + __IOM uint32_t INTERP0_CTRL_LANE1; /*!< Control register for lane 1 */ + __IOM uint32_t INTERP0_ACCUM0_ADD; /*!< Values written here are atomically added to ACCUM0 Reading yields + lane 0's raw shift and mask value (BASE0 not added). */ + __IOM uint32_t INTERP0_ACCUM1_ADD; /*!< Values written here are atomically added to ACCUM1 Reading yields + lane 1's raw shift and mask value (BASE1 not added). */ + __IOM uint32_t INTERP0_BASE_1AND0; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 + simultaneously. Each half is sign-extended to 32 bits if + that lane's SIGNED flag is set. */ + __IOM uint32_t INTERP1_ACCUM0; /*!< Read/write access to accumulator 0 */ + __IOM uint32_t INTERP1_ACCUM1; /*!< Read/write access to accumulator 1 */ + __IOM uint32_t INTERP1_BASE0; /*!< Read/write access to BASE0 register. */ + __IOM uint32_t INTERP1_BASE1; /*!< Read/write access to BASE1 register. */ + __IOM uint32_t INTERP1_BASE2; /*!< Read/write access to BASE2 register. */ + __IOM uint32_t INTERP1_POP_LANE0; /*!< Read LANE0 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP1_POP_LANE1; /*!< Read LANE1 result, and simultaneously write lane results to + both accumulators (POP). */ + __IOM uint32_t INTERP1_POP_FULL; /*!< Read FULL result, and simultaneously write lane results to both + accumulators (POP). */ + __IOM uint32_t INTERP1_PEEK_LANE0; /*!< Read LANE0 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP1_PEEK_LANE1; /*!< Read LANE1 result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP1_PEEK_FULL; /*!< Read FULL result, without altering any internal state (PEEK). */ + __IOM uint32_t INTERP1_CTRL_LANE0; /*!< Control register for lane 0 */ + __IOM uint32_t INTERP1_CTRL_LANE1; /*!< Control register for lane 1 */ + __IOM uint32_t INTERP1_ACCUM0_ADD; /*!< Values written here are atomically added to ACCUM0 Reading yields + lane 0's raw shift and mask value (BASE0 not added). */ + __IOM uint32_t INTERP1_ACCUM1_ADD; /*!< Values written here are atomically added to ACCUM1 Reading yields + lane 1's raw shift and mask value (BASE1 not added). */ + __IOM uint32_t INTERP1_BASE_1AND0; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 + simultaneously. Each half is sign-extended to 32 bits if + that lane's SIGNED flag is set. */ + __IOM uint32_t SPINLOCK0; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK1; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK2; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK3; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK4; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK5; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK6; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK7; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK8; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK9; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK10; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK11; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK12; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK13; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK14; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK15; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK16; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK17; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK18; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK19; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK20; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK21; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK22; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK23; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK24; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK25; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK26; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK27; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK28; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK29; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK30; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t SPINLOCK31; /*!< Reading from a spinlock address will: - Return 0 if lock is + already locked - Otherwise return nonzero, and simultaneously + claim the lock Writing (any value) releases the lock. If + core 0 and core 1 attempt to claim the same lock simultaneously, + core 0 wins. The value returned on success is 0x1 << lock + number. */ + __IOM uint32_t DOORBELL_OUT_SET; /*!< Trigger a doorbell interrupt on the opposite core. Write 1 to + a bit to set the corresponding bit in DOORBELL_IN on the + opposite core. This raises the opposite core's doorbell + interrupt. Read to get the status of the doorbells currently + asserted on the opposite core. This is equivalent to that + core reading its own DOORBELL_IN status. */ + __IOM uint32_t DOORBELL_OUT_CLR; /*!< Clear doorbells which have been posted to the opposite core. + This register is intended for debugging and initialisation + purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears + the corresponding bit in DOORBELL_IN on the opposite core. + Clearing all bits will cause that core's doorbell interrupt + to deassert. Since the usual order of events is for software + to send events using DOORBELL_OUT_SET, and acknowledge + incoming events by writing to DOORBELL_IN_CLR, this register + should be used with caution to avoid race conditions. Reading + returns the status of the doorbells currently asserted + on the other core, i.e. is equivalent to that core reading + its own DOORBELL_IN status. */ + __IOM uint32_t DOORBELL_IN_SET; /*!< Write 1s to trigger doorbell interrupts on this core. Read to + get status of doorbells currently asserted on this core. */ + __IOM uint32_t DOORBELL_IN_CLR; /*!< Check and acknowledge doorbells posted to this core. This core's + doorbell interrupt is asserted when any bit in this register + is 1. Write 1 to each bit to clear that bit. The doorbell + interrupt deasserts once all bits are cleared. Read to + get status of doorbells currently asserted on this core. */ + __IOM uint32_t PERI_NONSEC; /*!< Detach certain core-local peripherals from Secure SIO, and attach + them to Non-secure SIO, so that Non-secure software can + use them. Attempting to access one of these peripherals + from the Secure SIO when it is attached to the Non-secure + SIO, or vice versa, will generate a bus error. This register + is per-core, and is only present on the Secure SIO. Most + SIO hardware is duplicated across the Secure and Non-secure + SIO, so is not listed in this register. */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t RISCV_SOFTIRQ; /*!< Control the assertion of the standard software interrupt (MIP.MSIP) + on the RISC-V cores. Unlike the RISC-V timer, this interrupt + is not routed to a normal system-level interrupt line, + so can not be used by the Arm cores. It is safe for both + cores to write to this register on the same cycle. The + set/clear effect is accumulated across both cores, and + then applied. If a flag is both set and cleared on the + same cycle, only the set takes effect. */ + __IOM uint32_t MTIME_CTRL; /*!< Control register for the RISC-V 64-bit Machine-mode timer. This + timer is only present in the Secure SIO, so is only accessible + to an Arm core in Secure mode or a RISC-V core in Machine + mode. Note whilst this timer follows the RISC-V privileged + specification, it is equally usable by the Arm cores. The + interrupts are routed to normal system-level interrupt + lines as well as to the MIP.MTIP inputs on the RISC-V cores. */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t MTIME; /*!< Read/write access to the high half of RISC-V Machine-mode timer. + This register is shared between both cores. If both cores + write on the same cycle, core 1 takes precedence. */ + __IOM uint32_t MTIMEH; /*!< Read/write access to the high half of RISC-V Machine-mode timer. + This register is shared between both cores. If both cores + write on the same cycle, core 1 takes precedence. */ + __IOM uint32_t MTIMECMP; /*!< Low half of RISC-V Machine-mode timer comparator. This register + is core-local, i.e., each core gets a copy of this register, + with the comparison result routed to its own interrupt + line. The timer interrupt is asserted whenever MTIME is + greater than or equal to MTIMECMP. This comparison is unsigned, + and performed on the full 64-bit values. */ + __IOM uint32_t MTIMECMPH; /*!< High half of RISC-V Machine-mode timer comparator. This register + is core-local. The timer interrupt is asserted whenever + MTIME is greater than or equal to MTIMECMP. This comparison + is unsigned, and performed on the full 64-bit values. */ + __IOM uint32_t TMDS_CTRL; /*!< Control register for TMDS encoder. */ + __IOM uint32_t TMDS_WDATA; /*!< Write-only access to the TMDS colour data register. */ + __IOM uint32_t TMDS_PEEK_SINGLE; /*!< Get the encoding of one pixel's worth of colour data, packed + into a 32-bit value (3x10-bit symbols). The PEEK alias + does not shift the colour register when read, but still + advances the running DC balance state of each encoder. + This is useful for pixel doubling. */ + __IOM uint32_t TMDS_POP_SINGLE; /*!< Get the encoding of one pixel's worth of colour data, packed + into a 32-bit value. The packing is 5 chunks of 3 lanes + times 2 bits (30 bits total). Each chunk contains two bits + of a TMDS symbol per lane. This format is intended for + shifting out with the HSTX peripheral on RP2350. The POP + alias shifts the colour register when read, as well as + advancing the running DC balance state of each encoder. */ + __IOM uint32_t TMDS_PEEK_DOUBLE_L0; /*!< Get lane 0 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The PEEK alias does not shift the colour register + when read, but still advances the lane 0 DC balance state. + This is useful if all 3 lanes' worth of encode are to be + read at once, rather than processing the entire scanline + for one lane before moving to the next lane. */ + __IOM uint32_t TMDS_POP_DOUBLE_L0; /*!< Get lane 0 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The POP alias shifts the colour register when read, + according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ + __IOM uint32_t TMDS_PEEK_DOUBLE_L1; /*!< Get lane 1 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The PEEK alias does not shift the colour register + when read, but still advances the lane 1 DC balance state. + This is useful if all 3 lanes' worth of encode are to be + read at once, rather than processing the entire scanline + for one lane before moving to the next lane. */ + __IOM uint32_t TMDS_POP_DOUBLE_L1; /*!< Get lane 1 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The POP alias shifts the colour register when read, + according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ + __IOM uint32_t TMDS_PEEK_DOUBLE_L2; /*!< Get lane 2 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The PEEK alias does not shift the colour register + when read, but still advances the lane 2 DC balance state. + This is useful if all 3 lanes' worth of encode are to be + read at once, rather than processing the entire scanline + for one lane before moving to the next lane. */ + __IOM uint32_t TMDS_POP_DOUBLE_L2; /*!< Get lane 2 of the encoding of two pixels' worth of colour data. + Two 10-bit TMDS symbols are packed at the bottom of a 32-bit + word. The POP alias shifts the colour register when read, + according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ +} SIO_Type; /*!< Size = 488 (0x1e8) */ + + + +/* =========================================================================================================================== */ +/* ================ BOOTRAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Additional registers mapped adjacent to the bootram, for use by the bootrom. (BOOTRAM) + */ + +typedef struct { /*!< BOOTRAM Structure */ + __IM uint32_t RESERVED[512]; + __IOM uint32_t WRITE_ONCE0; /*!< This registers always ORs writes into its current contents. + Once a bit is set, it can only be cleared by a reset. */ + __IOM uint32_t WRITE_ONCE1; /*!< This registers always ORs writes into its current contents. + Once a bit is set, it can only be cleared by a reset. */ + __IOM uint32_t BOOTLOCK_STAT; /*!< Bootlock status register. 1=unclaimed, 0=claimed. These locks + function identically to the SIO spinlocks, but are reserved + for bootrom use. */ + __IOM uint32_t BOOTLOCK0; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + __IOM uint32_t BOOTLOCK1; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + __IOM uint32_t BOOTLOCK2; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + __IOM uint32_t BOOTLOCK3; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + __IOM uint32_t BOOTLOCK4; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + __IOM uint32_t BOOTLOCK5; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + __IOM uint32_t BOOTLOCK6; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ + __IOM uint32_t BOOTLOCK7; /*!< Read to claim and check. Write to unclaim. The value returned + on successful claim is 1 << n, and on failed claim is zero. */ +} BOOTRAM_Type; /*!< Size = 2092 (0x82c) */ + + + +/* =========================================================================================================================== */ +/* ================ CORESIGHT_TRACE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Coresight block - RP specific registers (CORESIGHT_TRACE) + */ + +typedef struct { /*!< CORESIGHT_TRACE Structure */ + __IOM uint32_t CTRL_STATUS; /*!< Control and status register */ + __IOM uint32_t TRACE_CAPTURE_FIFO; /*!< FIFO for trace data captured from the TPIU */ +} CORESIGHT_TRACE_Type; /*!< Size = 8 (0x8) */ + + + +/* =========================================================================================================================== */ +/* ================ USB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief USB FS/LS controller device registers (USB) + */ + +typedef struct { /*!< USB Structure */ + __IOM uint32_t ADDR_ENDP; /*!< Device address and endpoint control */ + __IOM uint32_t ADDR_ENDP1; /*!< Interrupt endpoint 1. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP2; /*!< Interrupt endpoint 2. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP3; /*!< Interrupt endpoint 3. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP4; /*!< Interrupt endpoint 4. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP5; /*!< Interrupt endpoint 5. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP6; /*!< Interrupt endpoint 6. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP7; /*!< Interrupt endpoint 7. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP8; /*!< Interrupt endpoint 8. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP9; /*!< Interrupt endpoint 9. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP10; /*!< Interrupt endpoint 10. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP11; /*!< Interrupt endpoint 11. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP12; /*!< Interrupt endpoint 12. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP13; /*!< Interrupt endpoint 13. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP14; /*!< Interrupt endpoint 14. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP15; /*!< Interrupt endpoint 15. Only valid for HOST mode. */ + __IOM uint32_t MAIN_CTRL; /*!< Main control register */ + __IOM uint32_t SOF_WR; /*!< Set the SOF (Start of Frame) frame number in the host controller. + The SOF packet is sent every 1ms and the host will increment + the frame number by 1 each time. */ + __IOM uint32_t SOF_RD; /*!< Read the last SOF (Start of Frame) frame number seen. In device + mode the last SOF received from the host. In host mode + the last SOF sent by the host. */ + __IOM uint32_t SIE_CTRL; /*!< SIE control register */ + __IOM uint32_t SIE_STATUS; /*!< SIE status register */ + __IOM uint32_t INT_EP_CTRL; /*!< interrupt endpoint control register */ + __IOM uint32_t BUFF_STATUS; /*!< Buffer status register. A bit set here indicates that a buffer + has completed on the endpoint (if the buffer interrupt + is enabled). It is possible for 2 buffers to be completed, + so clearing the buffer status bit may instantly re set + it on the next clock cycle. */ + __IOM uint32_t BUFF_CPU_SHOULD_HANDLE; /*!< Which of the double buffers should be handled. Only valid if + using an interrupt per buffer (i.e. not per 2 buffers). + Not valid for host interrupt endpoint polling because they + are only single buffered. */ + __IOM uint32_t EP_ABORT; /*!< Device only: Can be set to ignore the buffer control register + for this endpoint in case you would like to revoke a buffer. + A NAK will be sent for every access to the endpoint until + this bit is cleared. A corresponding bit in `EP_ABORT_DONE` + is set when it is safe to modify the buffer control register. */ + __IOM uint32_t EP_ABORT_DONE; /*!< Device only: Used in conjunction with `EP_ABORT`. Set once an + endpoint is idle so the programmer knows it is safe to + modify the buffer control register. */ + __IOM uint32_t EP_STALL_ARM; /*!< Device: this bit must be set in conjunction with the `STALL` + bit in the buffer control register to send a STALL on EP0. + The device controller clears these bits when a SETUP packet + is received because the USB spec requires that a STALL + condition is cleared when a SETUP packet is received. */ + __IOM uint32_t NAK_POLL; /*!< Used by the host controller. Sets the wait time in microseconds + before trying again if the device replies with a NAK. */ + __IOM uint32_t EP_STATUS_STALL_NAK; /*!< Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` + bits are set. For EP0 this comes from `SIE_CTRL`. For all + other endpoints it comes from the endpoint control register. */ + __IOM uint32_t USB_MUXING; /*!< Where to connect the USB controller. Should be to_phy by default. */ + __IOM uint32_t USB_PWR; /*!< Overrides for the power signals in the event that the VBUS signals + are not hooked up to GPIO. Set the value of the override + and then the override enable to switch over to the override + value. */ + __IOM uint32_t USBPHY_DIRECT; /*!< This register allows for direct control of the USB phy. Use + in conjunction with usbphy_direct_override register to + enable each override bit. */ + __IOM uint32_t USBPHY_DIRECT_OVERRIDE; /*!< Override enable for each control in usbphy_direct */ + __IOM uint32_t USBPHY_TRIM; /*!< Used to adjust trim values of USB phy pull down resistors. */ + __IOM uint32_t LINESTATE_TUNING; /*!< Used for debug only. */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ + __IM uint32_t RESERVED[25]; + __IOM uint32_t SOF_TIMESTAMP_RAW; /*!< Device only. Raw value of free-running PHY clock counter @48MHz. + Used to calculate time between SOF events. */ + __IOM uint32_t SOF_TIMESTAMP_LAST; /*!< Device only. Value of free-running PHY clock counter @48MHz + when last SOF event occurred. */ + __IOM uint32_t SM_STATE; /*!< SM_STATE */ + __IOM uint32_t EP_TX_ERROR; /*!< TX error count for each endpoint. Write to each field to reset + the counter to 0. */ + __IOM uint32_t EP_RX_ERROR; /*!< RX error count for each endpoint. Write to each field to reset + the counter to 0. */ + __IOM uint32_t DEV_SM_WATCHDOG; /*!< Watchdog that forces the device state machine to idle and raises + an interrupt if the device stays in a state that isn't + idle for the configured limit. The counter is reset on + every state transition. Set limit while enable is low and + then set the enable. */ +} USB_Type; /*!< Size = 280 (0x118) */ + + + +/* =========================================================================================================================== */ +/* ================ TRNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ARM TrustZone RNG register block (TRNG) + */ + +typedef struct { /*!< TRNG Structure */ + __IM uint32_t RESERVED[64]; + __IOM uint32_t RNG_IMR; /*!< Interrupt masking. */ + __IOM uint32_t RNG_ISR; /*!< RNG status register. If corresponding RNG_IMR bit is unmasked, + an interrupt will be generated. */ + __IOM uint32_t RNG_ICR; /*!< Interrupt/status bit clear Register. */ + __IOM uint32_t TRNG_CONFIG; /*!< Selecting the inverter-chain length. */ + __IOM uint32_t TRNG_VALID; /*!< 192 bit collection indication. */ + __IOM uint32_t EHR_DATA0; /*!< RNG collected bits. */ + __IOM uint32_t EHR_DATA1; /*!< RNG collected bits. */ + __IOM uint32_t EHR_DATA2; /*!< RNG collected bits. */ + __IOM uint32_t EHR_DATA3; /*!< RNG collected bits. */ + __IOM uint32_t EHR_DATA4; /*!< RNG collected bits. */ + __IOM uint32_t EHR_DATA5; /*!< RNG collected bits. */ + __IOM uint32_t RND_SOURCE_ENABLE; /*!< Enable signal for the random source. */ + __IOM uint32_t SAMPLE_CNT1; /*!< Counts clocks between sampling of random bit. */ + __IOM uint32_t AUTOCORR_STATISTIC; /*!< Statistic about Autocorrelation test activations. */ + __IOM uint32_t TRNG_DEBUG_CONTROL; /*!< Debug register. */ + __IM uint32_t RESERVED1; + __IOM uint32_t TRNG_SW_RESET; /*!< Generate internal SW reset within the RNG block. */ + __IM uint32_t RESERVED2[28]; + __IOM uint32_t RNG_DEBUG_EN_INPUT; /*!< Enable the RNG debug mode */ + __IOM uint32_t TRNG_BUSY; /*!< RNG Busy indication. */ + __IOM uint32_t RST_BITS_COUNTER; /*!< Reset the counter of collected bits in the RNG. */ + __IOM uint32_t RNG_VERSION; /*!< Displays the version settings of the TRNG. */ + __IM uint32_t RESERVED3[7]; + __IOM uint32_t RNG_BIST_CNTR_0; /*!< Collected BIST results. */ + __IOM uint32_t RNG_BIST_CNTR_1; /*!< Collected BIST results. */ + __IOM uint32_t RNG_BIST_CNTR_2; /*!< Collected BIST results. */ +} TRNG_Type; /*!< Size = 492 (0x1ec) */ + + + +/* =========================================================================================================================== */ +/* ================ GLITCH_DETECTOR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Glitch detector controls (GLITCH_DETECTOR) + */ + +typedef struct { /*!< GLITCH_DETECTOR Structure */ + __IOM uint32_t ARM; /*!< Forcibly arm the glitch detectors, if they are not already armed + by OTP. When armed, any individual detector trigger will + cause a restart of the switched core power domain's power-on + reset state machine. Glitch detector triggers are recorded + accumulatively in TRIG_STATUS. If the system is reset by + a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. + This register is Secure read/write only. */ + __IOM uint32_t DISARM; /*!< DISARM */ + __IOM uint32_t SENSITIVITY; /*!< Adjust the sensitivity of glitch detectors to values other than + their OTP-provided defaults. This register is Secure read/write + only. */ + __IOM uint32_t LOCK; /*!< LOCK */ + __IOM uint32_t TRIG_STATUS; /*!< Set when a detector output triggers. Write-1-clear. (May immediately + return high if the detector remains in a failed state. + Detectors can only be cleared by a full reset of the switched + core power domain.) This register is Secure read/write + only. */ + __IOM uint32_t TRIG_FORCE; /*!< Simulate the firing of one or more detectors. Writing ones to + this register will set the matching bits in STATUS_TRIG. + If the glitch detectors are currently armed, writing ones + will also immediately reset the switched core power domain, + and set the reset reason latches in POWMAN_CHIP_RESET to + indicate a glitch detector resets. This register is Secure + read/write only. */ +} GLITCH_DETECTOR_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ OTP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SNPS OTP control IF (SBPI and RPi wrapper control) (OTP) + */ + +typedef struct { /*!< OTP Structure */ + __IOM uint32_t SW_LOCK0; /*!< Software lock register for page 0. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK1; /*!< Software lock register for page 1. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK2; /*!< Software lock register for page 2. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK3; /*!< Software lock register for page 3. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK4; /*!< Software lock register for page 4. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK5; /*!< Software lock register for page 5. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK6; /*!< Software lock register for page 6. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK7; /*!< Software lock register for page 7. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK8; /*!< Software lock register for page 8. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK9; /*!< Software lock register for page 9. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK10; /*!< Software lock register for page 10. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK11; /*!< Software lock register for page 11. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK12; /*!< Software lock register for page 12. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK13; /*!< Software lock register for page 13. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK14; /*!< Software lock register for page 14. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK15; /*!< Software lock register for page 15. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK16; /*!< Software lock register for page 16. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK17; /*!< Software lock register for page 17. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK18; /*!< Software lock register for page 18. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK19; /*!< Software lock register for page 19. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK20; /*!< Software lock register for page 20. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK21; /*!< Software lock register for page 21. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK22; /*!< Software lock register for page 22. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK23; /*!< Software lock register for page 23. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK24; /*!< Software lock register for page 24. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK25; /*!< Software lock register for page 25. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK26; /*!< Software lock register for page 26. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK27; /*!< Software lock register for page 27. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK28; /*!< Software lock register for page 28. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK29; /*!< Software lock register for page 29. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK30; /*!< Software lock register for page 30. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK31; /*!< Software lock register for page 31. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK32; /*!< Software lock register for page 32. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK33; /*!< Software lock register for page 33. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK34; /*!< Software lock register for page 34. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK35; /*!< Software lock register for page 35. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK36; /*!< Software lock register for page 36. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK37; /*!< Software lock register for page 37. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK38; /*!< Software lock register for page 38. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK39; /*!< Software lock register for page 39. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK40; /*!< Software lock register for page 40. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK41; /*!< Software lock register for page 41. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK42; /*!< Software lock register for page 42. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK43; /*!< Software lock register for page 43. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK44; /*!< Software lock register for page 44. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK45; /*!< Software lock register for page 45. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK46; /*!< Software lock register for page 46. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK47; /*!< Software lock register for page 47. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK48; /*!< Software lock register for page 48. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK49; /*!< Software lock register for page 49. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK50; /*!< Software lock register for page 50. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK51; /*!< Software lock register for page 51. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK52; /*!< Software lock register for page 52. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK53; /*!< Software lock register for page 53. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK54; /*!< Software lock register for page 54. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK55; /*!< Software lock register for page 55. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK56; /*!< Software lock register for page 56. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK57; /*!< Software lock register for page 57. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK58; /*!< Software lock register for page 58. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK59; /*!< Software lock register for page 59. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK60; /*!< Software lock register for page 60. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK61; /*!< Software lock register for page 61. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK62; /*!< Software lock register for page 62. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SW_LOCK63; /*!< Software lock register for page 63. Locks are initialised from + the OTP lock pages at reset. This register can be written + to further advance the lock state of each page (until next + reset), and read to check the current lock state of a page. */ + __IOM uint32_t SBPI_INSTR; /*!< Dispatch instructions to the SBPI interface, used for programming + the OTP fuses. */ + __IOM uint32_t SBPI_WDATA_0; /*!< SBPI write payload bytes 3..0 */ + __IOM uint32_t SBPI_WDATA_1; /*!< SBPI write payload bytes 7..4 */ + __IOM uint32_t SBPI_WDATA_2; /*!< SBPI write payload bytes 11..8 */ + __IOM uint32_t SBPI_WDATA_3; /*!< SBPI write payload bytes 15..12 */ + __IOM uint32_t SBPI_RDATA_0; /*!< Read payload bytes 3..0. Once read, the data in the register + will automatically clear to 0. */ + __IOM uint32_t SBPI_RDATA_1; /*!< Read payload bytes 7..4. Once read, the data in the register + will automatically clear to 0. */ + __IOM uint32_t SBPI_RDATA_2; /*!< Read payload bytes 11..8. Once read, the data in the register + will automatically clear to 0. */ + __IOM uint32_t SBPI_RDATA_3; /*!< Read payload bytes 15..12. Once read, the data in the register + will automatically clear to 0. */ + __IOM uint32_t SBPI_STATUS; /*!< SBPI_STATUS */ + __IOM uint32_t USR; /*!< Controls for APB data read interface (USER interface) */ + __IOM uint32_t DBG; /*!< Debug for OTP power-on state machine */ + __IM uint32_t RESERVED; + __IOM uint32_t BIST; /*!< During BIST, count address locations that have at least one + leaky bit */ + __IOM uint32_t CRT_KEY_W0; /*!< Word 0 (bits 31..0) of the key. Write only, read returns 0x0 */ + __IOM uint32_t CRT_KEY_W1; /*!< Word 1 (bits 63..32) of the key. Write only, read returns 0x0 */ + __IOM uint32_t CRT_KEY_W2; /*!< Word 2 (bits 95..64) of the key. Write only, read returns 0x0 */ + __IOM uint32_t CRT_KEY_W3; /*!< Word 3 (bits 127..96) of the key. Write only, read returns 0x0 */ + __IOM uint32_t CRITICAL; /*!< Quickly check values of critical flags read during boot up */ + __IOM uint32_t KEY_VALID; /*!< Which keys were valid (enrolled) at boot time */ + __IOM uint32_t DEBUGEN; /*!< Enable a debug feature that has been disabled. Debug features + are disabled if one of the relevant critical boot flags + is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), + OR if a debug key is marked valid in OTP, and the matching + key value has not been supplied over SWD. Specifically: + - The DEBUG_DISABLE flag disables all debug features. This + can be fully overridden by setting all bits of this register. + - The SECURE_DEBUG_DISABLE flag disables secure processor + debug. This can be fully overridden by setting the PROC0_SECURE + and PROC1_SECURE bits of this register. - If a single debug + key has been registered, and no matching key value has + been supplied over SWD, then all debug features are disabled. + This can be fully overridden by setting all bits of this + register. - If both debug keys have been registered, and + the Non-secure key's value (key 6) has been supplied over + SWD, secure processor debug is disabled. This can be fully + overridden by setting the PROC0_SECURE and PROC1_SECURE + bits of this register. - If both debug keys have been registered, + and the Secure key's value (key 5) has been supplied over + SWD, then no debug features are disabled by the key mechanism. + However, note that in this case debug features may still + be disabled by the critical boot flags. */ + __IOM uint32_t DEBUGEN_LOCK; /*!< Write 1s to lock corresponding bits in DEBUGEN. This register + is reset by the processor cold reset. */ + __IOM uint32_t ARCHSEL; /*!< Architecture select (Arm/RISC-V). The default and allowable + values of this register are constrained by the critical + boot flags. This register is reset by the earliest reset + in the switched core power domain (before a processor cold + reset). Cores sample their architecture select signal on + a warm reset. The source of the warm reset could be the + system power-up state machine, the watchdog timer, Arm + SYSRESETREQ or from RISC-V hartresetreq. Note that when + an Arm core is deselected, its cold reset domain is also + held in reset, since in particular the SYSRESETREQ bit + becomes inaccessible once the core is deselected. Note + also the RISC-V cores do not have a cold reset domain, + since their corresponding controls are located in the Debug + Module. */ + __IOM uint32_t ARCHSEL_STATUS; /*!< Get the current architecture select state of each core. Cores + sample the current value of the ARCHSEL register when their + warm reset is released, at which point the corresponding + bit in this register will also update. */ + __IOM uint32_t BOOTDIS; /*!< Tell the bootrom to ignore scratch register boot vectors (both + power manager and watchdog) on the next power up. If an + early boot stage has soft-locked some OTP pages in order + to protect their contents from later stages, there is a + risk that Secure code running at a later stage can unlock + the pages by performing a watchdog reset that resets the + OTP. This register can be used to ensure that the bootloader + runs as normal on the next power up, preventing Secure + code at a later stage from accessing OTP in its unlocked + state. Should be used in conjunction with the power manager + BOOTDIS register. */ + __IOM uint32_t INTR; /*!< Raw Interrupts */ + __IOM uint32_t INTE; /*!< Interrupt Enable */ + __IOM uint32_t INTF; /*!< Interrupt Force */ + __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ +} OTP_Type; /*!< Size = 372 (0x174) */ + + + +/* =========================================================================================================================== */ +/* ================ OTP_DATA ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Predefined OTP data layout for RP2350 (OTP_DATA) + */ + +typedef struct { /*!< OTP_DATA Structure */ + __IOM uint16_t CHIPID0; /*!< Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain + a 64-bit random identifier for this chip, which can be + read from the USB bootloader PICOBOOT interface or from + the get_sys_info ROM API. The number of random bits makes + the occurrence of twins exceedingly unlikely: for example, + a fleet of a hundred million devices has a 99.97% probability + of no twinned IDs. This is estimated to be lower than the + occurrence of process errors in the assignment of sequential + random IDs, and for practical purposes CHIPID may be treated + as unique. */ + __IOM uint16_t CHIPID1; /*!< Bits 31:16 of public device ID (ECC) */ + __IOM uint16_t CHIPID2; /*!< Bits 47:32 of public device ID (ECC) */ + __IOM uint16_t CHIPID3; /*!< Bits 63:48 of public device ID (ECC) */ + __IOM uint16_t RANDID0; /*!< Bits 15:0 of private per-device random number (ECC) The RANDID0..7 + rows form a 128-bit random number generated during device + test. This ID is not exposed through the USB PICOBOOT GET_INFO + command or the ROM `get_sys_info()` API. However note that + the USB PICOBOOT OTP access point can read the entirety + of page 0, so this value is not meaningfully private unless + the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBO + T_IFC flag in BOOT_FLAGS0. */ + __IOM uint16_t RANDID1; /*!< Bits 31:16 of private per-device random number (ECC) */ + __IOM uint16_t RANDID2; /*!< Bits 47:32 of private per-device random number (ECC) */ + __IOM uint16_t RANDID3; /*!< Bits 63:48 of private per-device random number (ECC) */ + __IOM uint16_t RANDID4; /*!< Bits 79:64 of private per-device random number (ECC) */ + __IOM uint16_t RANDID5; /*!< Bits 95:80 of private per-device random number (ECC) */ + __IOM uint16_t RANDID6; /*!< Bits 111:96 of private per-device random number (ECC) */ + __IOM uint16_t RANDID7; /*!< Bits 127:112 of private per-device random number (ECC) */ + __IM uint16_t RESERVED[4]; + __IOM uint16_t ROSC_CALIB; /*!< Ring oscillator frequency in kHz, measured during manufacturing + (ECC) This is measured at 1.1 V, at room temperature, with + the ROSC configuration registers in their reset state. */ + __IOM uint16_t LPOSC_CALIB; /*!< Low-power oscillator frequency in Hz, measured during manufacturing + (ECC) This is measured at 1.1V, at room temperature, with + the LPOSC trim register in its reset state. */ + __IM uint16_t RESERVED1[6]; + __IOM uint16_t NUM_GPIOS; /*!< The number of main user GPIOs (bank 0). Should read 48 in the + QFN80 package, and 30 in the QFN60 package. (ECC) */ + __IM uint16_t RESERVED2[29]; + __IOM uint16_t INFO_CRC0; /*!< Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial + 0x4c11db7, input reflected, output reflected, seed all-ones, + final XOR all-ones) (ECC) */ + __IOM uint16_t INFO_CRC1; /*!< Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) */ + __IM uint16_t RESERVED3[28]; + __IOM uint16_t FLASH_DEVINFO; /*!< Stores information about external flash device(s). (ECC) Assumed + to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. */ + __IOM uint16_t FLASH_PARTITION_SLOT_SIZE; /*!< Gap between partition table slot 0 and slot 1 at the start of + flash (the default size is 4096 bytes) (ECC) Enabled by + the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, + the size is 4096 * (value + 1) */ + __IOM uint16_t BOOTSEL_LED_CFG; /*!< Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. */ + __IOM uint16_t BOOTSEL_PLL_CFG; /*!< Optional PLL configuration for BOOTSEL mode. (ECC) This should + be configured to produce an exact 48 MHz based on the crystal + oscillator frequency. User mode software may also use this + value to calculate the expected crystal frequency based + on an assumed 48 MHz PLL output. If no configuration is + given, the crystal is assumed to be 12 MHz. The PLL frequency + can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) + x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal + frequency can be calculated as: XOSC frequency = 48 MHz + x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the + +1 on REFDIV is because the value stored in this OTP location + is the actual divisor value minus one.) Used if and only + if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. + That bit should be set only after this row and BOOTSEL_XOSC_CFG + are both correctly programmed. */ + __IOM uint16_t BOOTSEL_XOSC_CFG; /*!< Non-default crystal oscillator configuration for the USB bootloader. + (ECC) These values may also be used by user code configuring + the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PL + _XOSC_CFG is set in BOOT_FLAGS0. That bit should be set + only after this row and BOOTSEL_PLL_CFG are both correctly + programmed. */ + __IM uint16_t RESERVED4[3]; + __IOM uint16_t USB_WHITE_LABEL_ADDR; /*!< Row index of the USB_WHITE_LABEL structure within OTP (ECC) + The table has 16 rows, each of which are also ECC and marked + valid by the corresponding valid bit in USB_BOOT_FLAGS + (ECC). The entries are either _VALUEs where the 16 bit + value is used as is, or _STRDEFs which acts as a pointers + to a string value. The value stored in a _STRDEF is two + separate bytes: The low seven bits of the first (LSB) byte + indicates the number of characters in the string, and the + top bit of the first (LSB) byte if set to indicate that + each character in the string is two bytes (Unicode) versus + one byte if unset. The second (MSB) byte represents the + location of the string data, and is encoded as the number + of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of + the start of the string is USB_WHITE_LABEL_ADDR value + + msb_byte. In each case, the corresponding valid bit enables + replacing the default value for the corresponding item + provided by the boot rom. Note that Unicode _STRDEFs are + only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_ST + DEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values + will be ignored if specified for other fields, and non-unicode + values for these three items will be converted to Unicode + characters by setting the upper 8 bits to zero. Note that + if the USB_WHITE_LABEL structure or the corresponding strings + are not readable by BOOTSEL mode based on OTP permissions, + or if alignment requirements are not met, then the corresponding + default values are used. The index values indicate where + each field is located (row USB_WHITE_LABEL_ADDR value + + index): */ + __IM uint16_t RESERVED5; + __IOM uint16_t OTPBOOT_SRC; /*!< OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, + the bootrom will load from this location into SRAM and + then directly enter the loaded image. Note that the image + must be signed if SECURE_BOOT_ENABLE is set. The image + itself is assumed to be ECC-protected. This must be an + even number. Equivalently, the OTP boot image must start + at a word-aligned location in the ECC read data address + window. */ + __IOM uint16_t OTPBOOT_LEN; /*!< Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must + be even. The total image size must be a multiple of 4 bytes + (32 bits). */ + __IOM uint16_t OTPBOOT_DST0; /*!< Bits 15:0 of the OTP boot image load destination (and entry + point). (ECC) This must be a location in main SRAM (main + SRAM is addresses 0x20000000 through 0x20082000) and must + be word-aligned. */ + __IOM uint16_t OTPBOOT_DST1; /*!< Bits 31:16 of the OTP boot image load destination (and entry + point). (ECC) This must be a location in main SRAM (main + SRAM is addresses 0x20000000 through 0x20082000) and must + be word-aligned. */ + __IM uint16_t RESERVED6[30]; + __IOM uint16_t BOOTKEY0_0; /*!< Bits 15:0 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_1; /*!< Bits 31:16 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_2; /*!< Bits 47:32 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_3; /*!< Bits 63:48 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_4; /*!< Bits 79:64 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_5; /*!< Bits 95:80 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_6; /*!< Bits 111:96 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_7; /*!< Bits 127:112 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_8; /*!< Bits 143:128 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_9; /*!< Bits 159:144 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_10; /*!< Bits 175:160 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_11; /*!< Bits 191:176 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_12; /*!< Bits 207:192 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_13; /*!< Bits 223:208 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_14; /*!< Bits 239:224 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY0_15; /*!< Bits 255:240 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint16_t BOOTKEY1_0; /*!< Bits 15:0 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_1; /*!< Bits 31:16 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_2; /*!< Bits 47:32 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_3; /*!< Bits 63:48 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_4; /*!< Bits 79:64 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_5; /*!< Bits 95:80 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_6; /*!< Bits 111:96 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_7; /*!< Bits 127:112 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_8; /*!< Bits 143:128 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_9; /*!< Bits 159:144 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_10; /*!< Bits 175:160 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_11; /*!< Bits 191:176 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_12; /*!< Bits 207:192 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_13; /*!< Bits 223:208 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_14; /*!< Bits 239:224 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY1_15; /*!< Bits 255:240 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint16_t BOOTKEY2_0; /*!< Bits 15:0 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_1; /*!< Bits 31:16 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_2; /*!< Bits 47:32 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_3; /*!< Bits 63:48 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_4; /*!< Bits 79:64 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_5; /*!< Bits 95:80 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_6; /*!< Bits 111:96 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_7; /*!< Bits 127:112 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_8; /*!< Bits 143:128 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_9; /*!< Bits 159:144 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_10; /*!< Bits 175:160 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_11; /*!< Bits 191:176 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_12; /*!< Bits 207:192 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_13; /*!< Bits 223:208 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_14; /*!< Bits 239:224 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY2_15; /*!< Bits 255:240 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint16_t BOOTKEY3_0; /*!< Bits 15:0 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_1; /*!< Bits 31:16 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_2; /*!< Bits 47:32 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_3; /*!< Bits 63:48 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_4; /*!< Bits 79:64 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_5; /*!< Bits 95:80 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_6; /*!< Bits 111:96 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_7; /*!< Bits 127:112 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_8; /*!< Bits 143:128 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_9; /*!< Bits 159:144 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_10; /*!< Bits 175:160 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_11; /*!< Bits 191:176 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_12; /*!< Bits 207:192 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_13; /*!< Bits 223:208 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_14; /*!< Bits 239:224 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint16_t BOOTKEY3_15; /*!< Bits 255:240 of SHA-256 hash of boot key 3 (ECC) */ + __IM uint16_t RESERVED7[3720]; + __IOM uint16_t KEY1_0; /*!< Bits 15:0 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY1_1; /*!< Bits 31:16 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY1_2; /*!< Bits 47:32 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY1_3; /*!< Bits 63:48 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY1_4; /*!< Bits 79:64 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY1_5; /*!< Bits 95:80 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY1_6; /*!< Bits 111:96 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY1_7; /*!< Bits 127:112 of OTP access key 1 (ECC) */ + __IOM uint16_t KEY2_0; /*!< Bits 15:0 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY2_1; /*!< Bits 31:16 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY2_2; /*!< Bits 47:32 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY2_3; /*!< Bits 63:48 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY2_4; /*!< Bits 79:64 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY2_5; /*!< Bits 95:80 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY2_6; /*!< Bits 111:96 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY2_7; /*!< Bits 127:112 of OTP access key 2 (ECC) */ + __IOM uint16_t KEY3_0; /*!< Bits 15:0 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY3_1; /*!< Bits 31:16 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY3_2; /*!< Bits 47:32 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY3_3; /*!< Bits 63:48 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY3_4; /*!< Bits 79:64 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY3_5; /*!< Bits 95:80 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY3_6; /*!< Bits 111:96 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY3_7; /*!< Bits 127:112 of OTP access key 3 (ECC) */ + __IOM uint16_t KEY4_0; /*!< Bits 15:0 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY4_1; /*!< Bits 31:16 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY4_2; /*!< Bits 47:32 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY4_3; /*!< Bits 63:48 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY4_4; /*!< Bits 79:64 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY4_5; /*!< Bits 95:80 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY4_6; /*!< Bits 111:96 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY4_7; /*!< Bits 127:112 of OTP access key 4 (ECC) */ + __IOM uint16_t KEY5_0; /*!< Bits 15:0 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY5_1; /*!< Bits 31:16 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY5_2; /*!< Bits 47:32 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY5_3; /*!< Bits 63:48 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY5_4; /*!< Bits 79:64 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY5_5; /*!< Bits 95:80 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY5_6; /*!< Bits 111:96 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY5_7; /*!< Bits 127:112 of OTP access key 5 (ECC) */ + __IOM uint16_t KEY6_0; /*!< Bits 15:0 of OTP access key 6 (ECC) */ + __IOM uint16_t KEY6_1; /*!< Bits 31:16 of OTP access key 6 (ECC) */ + __IOM uint16_t KEY6_2; /*!< Bits 47:32 of OTP access key 6 (ECC) */ + __IOM uint16_t KEY6_3; /*!< Bits 63:48 of OTP access key 6 (ECC) */ + __IOM uint16_t KEY6_4; /*!< Bits 79:64 of OTP access key 6 (ECC) */ + __IOM uint16_t KEY6_5; /*!< Bits 95:80 of OTP access key 6 (ECC) */ + __IOM uint16_t KEY6_6; /*!< Bits 111:96 of OTP access key 6 (ECC) */ + __IOM uint16_t KEY6_7; /*!< Bits 127:112 of OTP access key 6 (ECC) */ +} OTP_DATA_Type; /*!< Size = 7920 (0x1ef0) */ + + + +/* =========================================================================================================================== */ +/* ================ OTP_DATA_RAW ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Predefined OTP data layout for RP2350 (OTP_DATA_RAW) + */ + +typedef struct { /*!< OTP_DATA_RAW Structure */ + __IOM uint32_t CHIPID0; /*!< Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain + a 64-bit random identifier for this chip, which can be + read from the USB bootloader PICOBOOT interface or from + the get_sys_info ROM API. The number of random bits makes + the occurrence of twins exceedingly unlikely: for example, + a fleet of a hundred million devices has a 99.97% probability + of no twinned IDs. This is estimated to be lower than the + occurrence of process errors in the assignment of sequential + random IDs, and for practical purposes CHIPID may be treated + as unique. */ + __IOM uint32_t CHIPID1; /*!< Bits 31:16 of public device ID (ECC) */ + __IOM uint32_t CHIPID2; /*!< Bits 47:32 of public device ID (ECC) */ + __IOM uint32_t CHIPID3; /*!< Bits 63:48 of public device ID (ECC) */ + __IOM uint32_t RANDID0; /*!< Bits 15:0 of private per-device random number (ECC) The RANDID0..7 + rows form a 128-bit random number generated during device + test. This ID is not exposed through the USB PICOBOOT GET_INFO + command or the ROM `get_sys_info()` API. However note that + the USB PICOBOOT OTP access point can read the entirety + of page 0, so this value is not meaningfully private unless + the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBO + T_IFC flag in BOOT_FLAGS0. */ + __IOM uint32_t RANDID1; /*!< Bits 31:16 of private per-device random number (ECC) */ + __IOM uint32_t RANDID2; /*!< Bits 47:32 of private per-device random number (ECC) */ + __IOM uint32_t RANDID3; /*!< Bits 63:48 of private per-device random number (ECC) */ + __IOM uint32_t RANDID4; /*!< Bits 79:64 of private per-device random number (ECC) */ + __IOM uint32_t RANDID5; /*!< Bits 95:80 of private per-device random number (ECC) */ + __IOM uint32_t RANDID6; /*!< Bits 111:96 of private per-device random number (ECC) */ + __IOM uint32_t RANDID7; /*!< Bits 127:112 of private per-device random number (ECC) */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t ROSC_CALIB; /*!< Ring oscillator frequency in kHz, measured during manufacturing + (ECC) This is measured at 1.1 V, at room temperature, with + the ROSC configuration registers in their reset state. */ + __IOM uint32_t LPOSC_CALIB; /*!< Low-power oscillator frequency in Hz, measured during manufacturing + (ECC) This is measured at 1.1V, at room temperature, with + the LPOSC trim register in its reset state. */ + __IM uint32_t RESERVED1[6]; + __IOM uint32_t NUM_GPIOS; /*!< The number of main user GPIOs (bank 0). Should read 48 in the + QFN80 package, and 30 in the QFN60 package. (ECC) */ + __IM uint32_t RESERVED2[29]; + __IOM uint32_t INFO_CRC0; /*!< Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial + 0x4c11db7, input reflected, output reflected, seed all-ones, + final XOR all-ones) (ECC) */ + __IOM uint32_t INFO_CRC1; /*!< Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) */ + __IOM uint32_t CRIT0; /*!< Page 0 critical boot flags (RBIT-8) */ + __IOM uint32_t CRIT0_R1; /*!< Redundant copy of CRIT0 */ + __IOM uint32_t CRIT0_R2; /*!< Redundant copy of CRIT0 */ + __IOM uint32_t CRIT0_R3; /*!< Redundant copy of CRIT0 */ + __IOM uint32_t CRIT0_R4; /*!< Redundant copy of CRIT0 */ + __IOM uint32_t CRIT0_R5; /*!< Redundant copy of CRIT0 */ + __IOM uint32_t CRIT0_R6; /*!< Redundant copy of CRIT0 */ + __IOM uint32_t CRIT0_R7; /*!< Redundant copy of CRIT0 */ + __IOM uint32_t CRIT1; /*!< Page 1 critical boot flags (RBIT-8) */ + __IOM uint32_t CRIT1_R1; /*!< Redundant copy of CRIT1 */ + __IOM uint32_t CRIT1_R2; /*!< Redundant copy of CRIT1 */ + __IOM uint32_t CRIT1_R3; /*!< Redundant copy of CRIT1 */ + __IOM uint32_t CRIT1_R4; /*!< Redundant copy of CRIT1 */ + __IOM uint32_t CRIT1_R5; /*!< Redundant copy of CRIT1 */ + __IOM uint32_t CRIT1_R6; /*!< Redundant copy of CRIT1 */ + __IOM uint32_t CRIT1_R7; /*!< Redundant copy of CRIT1 */ + __IOM uint32_t BOOT_FLAGS0; /*!< Disable/Enable boot paths/features in the RP2350 mask ROM. Disables + always supersede enables. Enables are provided where there + are other configurations in OTP that must be valid. (RBIT-3) */ + __IOM uint32_t BOOT_FLAGS0_R1; /*!< Redundant copy of BOOT_FLAGS0 */ + __IOM uint32_t BOOT_FLAGS0_R2; /*!< Redundant copy of BOOT_FLAGS0 */ + __IOM uint32_t BOOT_FLAGS1; /*!< Disable/Enable boot paths/features in the RP2350 mask ROM. Disables + always supersede enables. Enables are provided where there + are other configurations in OTP that must be valid. (RBIT-3) */ + __IOM uint32_t BOOT_FLAGS1_R1; /*!< Redundant copy of BOOT_FLAGS1 */ + __IOM uint32_t BOOT_FLAGS1_R2; /*!< Redundant copy of BOOT_FLAGS1 */ + __IOM uint32_t DEFAULT_BOOT_VERSION0; /*!< Default boot version thermometer counter, bits 23:0 (RBIT-3) */ + __IOM uint32_t DEFAULT_BOOT_VERSION0_R1; /*!< Redundant copy of DEFAULT_BOOT_VERSION0 */ + __IOM uint32_t DEFAULT_BOOT_VERSION0_R2; /*!< Redundant copy of DEFAULT_BOOT_VERSION0 */ + __IOM uint32_t DEFAULT_BOOT_VERSION1; /*!< Default boot version thermometer counter, bits 47:24 (RBIT-3) */ + __IOM uint32_t DEFAULT_BOOT_VERSION1_R1; /*!< Redundant copy of DEFAULT_BOOT_VERSION1 */ + __IOM uint32_t DEFAULT_BOOT_VERSION1_R2; /*!< Redundant copy of DEFAULT_BOOT_VERSION1 */ + __IOM uint32_t FLASH_DEVINFO; /*!< Stores information about external flash device(s). (ECC) Assumed + to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. */ + __IOM uint32_t FLASH_PARTITION_SLOT_SIZE; /*!< Gap between partition table slot 0 and slot 1 at the start of + flash (the default size is 4096 bytes) (ECC) Enabled by + the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, + the size is 4096 * (value + 1) */ + __IOM uint32_t BOOTSEL_LED_CFG; /*!< Pin configuration for LED status, used by USB bootloader. (ECC) + Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. */ + __IOM uint32_t BOOTSEL_PLL_CFG; /*!< Optional PLL configuration for BOOTSEL mode. (ECC) This should + be configured to produce an exact 48 MHz based on the crystal + oscillator frequency. User mode software may also use this + value to calculate the expected crystal frequency based + on an assumed 48 MHz PLL output. If no configuration is + given, the crystal is assumed to be 12 MHz. The PLL frequency + can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) + x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal + frequency can be calculated as: XOSC frequency = 48 MHz + x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the + +1 on REFDIV is because the value stored in this OTP location + is the actual divisor value minus one.) Used if and only + if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. + That bit should be set only after this row and BOOTSEL_XOSC_CFG + are both correctly programmed. */ + __IOM uint32_t BOOTSEL_XOSC_CFG; /*!< Non-default crystal oscillator configuration for the USB bootloader. + (ECC) These values may also be used by user code configuring + the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PL + _XOSC_CFG is set in BOOT_FLAGS0. That bit should be set + only after this row and BOOTSEL_PLL_CFG are both correctly + programmed. */ + __IOM uint32_t USB_BOOT_FLAGS; /*!< USB boot specific feature flags (RBIT-3) */ + __IOM uint32_t USB_BOOT_FLAGS_R1; /*!< Redundant copy of USB_BOOT_FLAGS */ + __IOM uint32_t USB_BOOT_FLAGS_R2; /*!< Redundant copy of USB_BOOT_FLAGS */ + __IOM uint32_t USB_WHITE_LABEL_ADDR; /*!< Row index of the USB_WHITE_LABEL structure within OTP (ECC) + The table has 16 rows, each of which are also ECC and marked + valid by the corresponding valid bit in USB_BOOT_FLAGS + (ECC). The entries are either _VALUEs where the 16 bit + value is used as is, or _STRDEFs which acts as a pointers + to a string value. The value stored in a _STRDEF is two + separate bytes: The low seven bits of the first (LSB) byte + indicates the number of characters in the string, and the + top bit of the first (LSB) byte if set to indicate that + each character in the string is two bytes (Unicode) versus + one byte if unset. The second (MSB) byte represents the + location of the string data, and is encoded as the number + of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of + the start of the string is USB_WHITE_LABEL_ADDR value + + msb_byte. In each case, the corresponding valid bit enables + replacing the default value for the corresponding item + provided by the boot rom. Note that Unicode _STRDEFs are + only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_ST + DEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values + will be ignored if specified for other fields, and non-unicode + values for these three items will be converted to Unicode + characters by setting the upper 8 bits to zero. Note that + if the USB_WHITE_LABEL structure or the corresponding strings + are not readable by BOOTSEL mode based on OTP permissions, + or if alignment requirements are not met, then the corresponding + default values are used. The index values indicate where + each field is located (row USB_WHITE_LABEL_ADDR value + + index): */ + __IM uint32_t RESERVED3; + __IOM uint32_t OTPBOOT_SRC; /*!< OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, + the bootrom will load from this location into SRAM and + then directly enter the loaded image. Note that the image + must be signed if SECURE_BOOT_ENABLE is set. The image + itself is assumed to be ECC-protected. This must be an + even number. Equivalently, the OTP boot image must start + at a word-aligned location in the ECC read data address + window. */ + __IOM uint32_t OTPBOOT_LEN; /*!< Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must + be even. The total image size must be a multiple of 4 bytes + (32 bits). */ + __IOM uint32_t OTPBOOT_DST0; /*!< Bits 15:0 of the OTP boot image load destination (and entry + point). (ECC) This must be a location in main SRAM (main + SRAM is addresses 0x20000000 through 0x20082000) and must + be word-aligned. */ + __IOM uint32_t OTPBOOT_DST1; /*!< Bits 31:16 of the OTP boot image load destination (and entry + point). (ECC) This must be a location in main SRAM (main + SRAM is addresses 0x20000000 through 0x20082000) and must + be word-aligned. */ + __IM uint32_t RESERVED4[30]; + __IOM uint32_t BOOTKEY0_0; /*!< Bits 15:0 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_1; /*!< Bits 31:16 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_2; /*!< Bits 47:32 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_3; /*!< Bits 63:48 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_4; /*!< Bits 79:64 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_5; /*!< Bits 95:80 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_6; /*!< Bits 111:96 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_7; /*!< Bits 127:112 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_8; /*!< Bits 143:128 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_9; /*!< Bits 159:144 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_10; /*!< Bits 175:160 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_11; /*!< Bits 191:176 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_12; /*!< Bits 207:192 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_13; /*!< Bits 223:208 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_14; /*!< Bits 239:224 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY0_15; /*!< Bits 255:240 of SHA-256 hash of boot key 0 (ECC) */ + __IOM uint32_t BOOTKEY1_0; /*!< Bits 15:0 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_1; /*!< Bits 31:16 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_2; /*!< Bits 47:32 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_3; /*!< Bits 63:48 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_4; /*!< Bits 79:64 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_5; /*!< Bits 95:80 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_6; /*!< Bits 111:96 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_7; /*!< Bits 127:112 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_8; /*!< Bits 143:128 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_9; /*!< Bits 159:144 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_10; /*!< Bits 175:160 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_11; /*!< Bits 191:176 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_12; /*!< Bits 207:192 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_13; /*!< Bits 223:208 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_14; /*!< Bits 239:224 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY1_15; /*!< Bits 255:240 of SHA-256 hash of boot key 1 (ECC) */ + __IOM uint32_t BOOTKEY2_0; /*!< Bits 15:0 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_1; /*!< Bits 31:16 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_2; /*!< Bits 47:32 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_3; /*!< Bits 63:48 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_4; /*!< Bits 79:64 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_5; /*!< Bits 95:80 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_6; /*!< Bits 111:96 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_7; /*!< Bits 127:112 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_8; /*!< Bits 143:128 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_9; /*!< Bits 159:144 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_10; /*!< Bits 175:160 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_11; /*!< Bits 191:176 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_12; /*!< Bits 207:192 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_13; /*!< Bits 223:208 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_14; /*!< Bits 239:224 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY2_15; /*!< Bits 255:240 of SHA-256 hash of boot key 2 (ECC) */ + __IOM uint32_t BOOTKEY3_0; /*!< Bits 15:0 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_1; /*!< Bits 31:16 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_2; /*!< Bits 47:32 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_3; /*!< Bits 63:48 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_4; /*!< Bits 79:64 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_5; /*!< Bits 95:80 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_6; /*!< Bits 111:96 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_7; /*!< Bits 127:112 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_8; /*!< Bits 143:128 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_9; /*!< Bits 159:144 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_10; /*!< Bits 175:160 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_11; /*!< Bits 191:176 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_12; /*!< Bits 207:192 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_13; /*!< Bits 223:208 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_14; /*!< Bits 239:224 of SHA-256 hash of boot key 3 (ECC) */ + __IOM uint32_t BOOTKEY3_15; /*!< Bits 255:240 of SHA-256 hash of boot key 3 (ECC) */ + __IM uint32_t RESERVED5[3720]; + __IOM uint32_t KEY1_0; /*!< Bits 15:0 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY1_1; /*!< Bits 31:16 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY1_2; /*!< Bits 47:32 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY1_3; /*!< Bits 63:48 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY1_4; /*!< Bits 79:64 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY1_5; /*!< Bits 95:80 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY1_6; /*!< Bits 111:96 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY1_7; /*!< Bits 127:112 of OTP access key 1 (ECC) */ + __IOM uint32_t KEY2_0; /*!< Bits 15:0 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY2_1; /*!< Bits 31:16 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY2_2; /*!< Bits 47:32 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY2_3; /*!< Bits 63:48 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY2_4; /*!< Bits 79:64 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY2_5; /*!< Bits 95:80 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY2_6; /*!< Bits 111:96 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY2_7; /*!< Bits 127:112 of OTP access key 2 (ECC) */ + __IOM uint32_t KEY3_0; /*!< Bits 15:0 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY3_1; /*!< Bits 31:16 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY3_2; /*!< Bits 47:32 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY3_3; /*!< Bits 63:48 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY3_4; /*!< Bits 79:64 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY3_5; /*!< Bits 95:80 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY3_6; /*!< Bits 111:96 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY3_7; /*!< Bits 127:112 of OTP access key 3 (ECC) */ + __IOM uint32_t KEY4_0; /*!< Bits 15:0 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY4_1; /*!< Bits 31:16 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY4_2; /*!< Bits 47:32 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY4_3; /*!< Bits 63:48 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY4_4; /*!< Bits 79:64 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY4_5; /*!< Bits 95:80 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY4_6; /*!< Bits 111:96 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY4_7; /*!< Bits 127:112 of OTP access key 4 (ECC) */ + __IOM uint32_t KEY5_0; /*!< Bits 15:0 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY5_1; /*!< Bits 31:16 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY5_2; /*!< Bits 47:32 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY5_3; /*!< Bits 63:48 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY5_4; /*!< Bits 79:64 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY5_5; /*!< Bits 95:80 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY5_6; /*!< Bits 111:96 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY5_7; /*!< Bits 127:112 of OTP access key 5 (ECC) */ + __IOM uint32_t KEY6_0; /*!< Bits 15:0 of OTP access key 6 (ECC) */ + __IOM uint32_t KEY6_1; /*!< Bits 31:16 of OTP access key 6 (ECC) */ + __IOM uint32_t KEY6_2; /*!< Bits 47:32 of OTP access key 6 (ECC) */ + __IOM uint32_t KEY6_3; /*!< Bits 63:48 of OTP access key 6 (ECC) */ + __IOM uint32_t KEY6_4; /*!< Bits 79:64 of OTP access key 6 (ECC) */ + __IOM uint32_t KEY6_5; /*!< Bits 95:80 of OTP access key 6 (ECC) */ + __IOM uint32_t KEY6_6; /*!< Bits 111:96 of OTP access key 6 (ECC) */ + __IOM uint32_t KEY6_7; /*!< Bits 127:112 of OTP access key 6 (ECC) */ + __IM uint32_t RESERVED6; + __IOM uint32_t KEY1_VALID; /*!< Valid flag for key 1. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + __IOM uint32_t KEY2_VALID; /*!< Valid flag for key 2. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + __IOM uint32_t KEY3_VALID; /*!< Valid flag for key 3. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + __IOM uint32_t KEY4_VALID; /*!< Valid flag for key 4. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + __IOM uint32_t KEY5_VALID; /*!< Valid flag for key 5. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + __IOM uint32_t KEY6_VALID; /*!< Valid flag for key 6. Once the valid flag is set, the key can + no longer be read or written, and becomes a valid fixed + key for protecting OTP pages. */ + __IM uint32_t RESERVED7; + __IOM uint32_t PAGE0_LOCK0; /*!< Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE0_LOCK1; /*!< Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE1_LOCK0; /*!< Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE1_LOCK1; /*!< Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE2_LOCK0; /*!< Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE2_LOCK1; /*!< Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE3_LOCK0; /*!< Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE3_LOCK1; /*!< Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE4_LOCK0; /*!< Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE4_LOCK1; /*!< Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE5_LOCK0; /*!< Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE5_LOCK1; /*!< Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE6_LOCK0; /*!< Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE6_LOCK1; /*!< Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE7_LOCK0; /*!< Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE7_LOCK1; /*!< Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE8_LOCK0; /*!< Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE8_LOCK1; /*!< Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE9_LOCK0; /*!< Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE9_LOCK1; /*!< Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE10_LOCK0; /*!< Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE10_LOCK1; /*!< Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE11_LOCK0; /*!< Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE11_LOCK1; /*!< Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE12_LOCK0; /*!< Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE12_LOCK1; /*!< Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE13_LOCK0; /*!< Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE13_LOCK1; /*!< Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE14_LOCK0; /*!< Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE14_LOCK1; /*!< Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE15_LOCK0; /*!< Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE15_LOCK1; /*!< Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE16_LOCK0; /*!< Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE16_LOCK1; /*!< Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE17_LOCK0; /*!< Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE17_LOCK1; /*!< Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE18_LOCK0; /*!< Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE18_LOCK1; /*!< Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE19_LOCK0; /*!< Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE19_LOCK1; /*!< Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE20_LOCK0; /*!< Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE20_LOCK1; /*!< Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE21_LOCK0; /*!< Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE21_LOCK1; /*!< Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE22_LOCK0; /*!< Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE22_LOCK1; /*!< Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE23_LOCK0; /*!< Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE23_LOCK1; /*!< Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE24_LOCK0; /*!< Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE24_LOCK1; /*!< Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE25_LOCK0; /*!< Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE25_LOCK1; /*!< Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE26_LOCK0; /*!< Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE26_LOCK1; /*!< Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE27_LOCK0; /*!< Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE27_LOCK1; /*!< Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE28_LOCK0; /*!< Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE28_LOCK1; /*!< Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE29_LOCK0; /*!< Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE29_LOCK1; /*!< Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE30_LOCK0; /*!< Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE30_LOCK1; /*!< Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE31_LOCK0; /*!< Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE31_LOCK1; /*!< Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE32_LOCK0; /*!< Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE32_LOCK1; /*!< Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE33_LOCK0; /*!< Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE33_LOCK1; /*!< Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE34_LOCK0; /*!< Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE34_LOCK1; /*!< Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE35_LOCK0; /*!< Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE35_LOCK1; /*!< Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE36_LOCK0; /*!< Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE36_LOCK1; /*!< Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE37_LOCK0; /*!< Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE37_LOCK1; /*!< Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE38_LOCK0; /*!< Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE38_LOCK1; /*!< Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE39_LOCK0; /*!< Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE39_LOCK1; /*!< Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE40_LOCK0; /*!< Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE40_LOCK1; /*!< Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE41_LOCK0; /*!< Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE41_LOCK1; /*!< Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE42_LOCK0; /*!< Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE42_LOCK1; /*!< Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE43_LOCK0; /*!< Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE43_LOCK1; /*!< Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE44_LOCK0; /*!< Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE44_LOCK1; /*!< Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE45_LOCK0; /*!< Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE45_LOCK1; /*!< Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE46_LOCK0; /*!< Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE46_LOCK1; /*!< Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE47_LOCK0; /*!< Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE47_LOCK1; /*!< Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE48_LOCK0; /*!< Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE48_LOCK1; /*!< Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE49_LOCK0; /*!< Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE49_LOCK1; /*!< Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE50_LOCK0; /*!< Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE50_LOCK1; /*!< Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE51_LOCK0; /*!< Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE51_LOCK1; /*!< Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE52_LOCK0; /*!< Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE52_LOCK1; /*!< Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE53_LOCK0; /*!< Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE53_LOCK1; /*!< Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE54_LOCK0; /*!< Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE54_LOCK1; /*!< Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE55_LOCK0; /*!< Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE55_LOCK1; /*!< Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE56_LOCK0; /*!< Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE56_LOCK1; /*!< Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE57_LOCK0; /*!< Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE57_LOCK1; /*!< Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE58_LOCK0; /*!< Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE58_LOCK1; /*!< Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE59_LOCK0; /*!< Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE59_LOCK1; /*!< Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE60_LOCK0; /*!< Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE60_LOCK1; /*!< Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE61_LOCK0; /*!< Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE61_LOCK1; /*!< Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE62_LOCK0; /*!< Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE62_LOCK1; /*!< Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE63_LOCK0; /*!< Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ + __IOM uint32_t PAGE63_LOCK1; /*!< Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). + Locks are stored with 3-way majority vote encoding, so + that bits can be set independently. This OTP location is + always readable, and is write-protected by its own permissions. */ +} OTP_DATA_RAW_Type; /*!< Size = 16384 (0x4000) */ + + + +/* =========================================================================================================================== */ +/* ================ TBMAN ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief For managing simulation testbenches (TBMAN) + */ + +typedef struct { /*!< TBMAN Structure */ + __IOM uint32_t PLATFORM; /*!< Indicates the type of platform in use */ +} TBMAN_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ USB_DPRAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DPRAM layout for USB device. (USB_DPRAM) + */ + +typedef struct { /*!< USB_DPRAM Structure */ + __IOM uint32_t SETUP_PACKET_LOW; /*!< Bytes 0-3 of the SETUP packet from the host. */ + __IOM uint32_t SETUP_PACKET_HIGH; /*!< Bytes 4-7 of the setup packet from the host. */ + __IOM uint32_t EP1_IN_CONTROL; /*!< EP1_IN_CONTROL */ + __IOM uint32_t EP1_OUT_CONTROL; /*!< EP1_OUT_CONTROL */ + __IOM uint32_t EP2_IN_CONTROL; /*!< EP2_IN_CONTROL */ + __IOM uint32_t EP2_OUT_CONTROL; /*!< EP2_OUT_CONTROL */ + __IOM uint32_t EP3_IN_CONTROL; /*!< EP3_IN_CONTROL */ + __IOM uint32_t EP3_OUT_CONTROL; /*!< EP3_OUT_CONTROL */ + __IOM uint32_t EP4_IN_CONTROL; /*!< EP4_IN_CONTROL */ + __IOM uint32_t EP4_OUT_CONTROL; /*!< EP4_OUT_CONTROL */ + __IOM uint32_t EP5_IN_CONTROL; /*!< EP5_IN_CONTROL */ + __IOM uint32_t EP5_OUT_CONTROL; /*!< EP5_OUT_CONTROL */ + __IOM uint32_t EP6_IN_CONTROL; /*!< EP6_IN_CONTROL */ + __IOM uint32_t EP6_OUT_CONTROL; /*!< EP6_OUT_CONTROL */ + __IOM uint32_t EP7_IN_CONTROL; /*!< EP7_IN_CONTROL */ + __IOM uint32_t EP7_OUT_CONTROL; /*!< EP7_OUT_CONTROL */ + __IOM uint32_t EP8_IN_CONTROL; /*!< EP8_IN_CONTROL */ + __IOM uint32_t EP8_OUT_CONTROL; /*!< EP8_OUT_CONTROL */ + __IOM uint32_t EP9_IN_CONTROL; /*!< EP9_IN_CONTROL */ + __IOM uint32_t EP9_OUT_CONTROL; /*!< EP9_OUT_CONTROL */ + __IOM uint32_t EP10_IN_CONTROL; /*!< EP10_IN_CONTROL */ + __IOM uint32_t EP10_OUT_CONTROL; /*!< EP10_OUT_CONTROL */ + __IOM uint32_t EP11_IN_CONTROL; /*!< EP11_IN_CONTROL */ + __IOM uint32_t EP11_OUT_CONTROL; /*!< EP11_OUT_CONTROL */ + __IOM uint32_t EP12_IN_CONTROL; /*!< EP12_IN_CONTROL */ + __IOM uint32_t EP12_OUT_CONTROL; /*!< EP12_OUT_CONTROL */ + __IOM uint32_t EP13_IN_CONTROL; /*!< EP13_IN_CONTROL */ + __IOM uint32_t EP13_OUT_CONTROL; /*!< EP13_OUT_CONTROL */ + __IOM uint32_t EP14_IN_CONTROL; /*!< EP14_IN_CONTROL */ + __IOM uint32_t EP14_OUT_CONTROL; /*!< EP14_OUT_CONTROL */ + __IOM uint32_t EP15_IN_CONTROL; /*!< EP15_IN_CONTROL */ + __IOM uint32_t EP15_OUT_CONTROL; /*!< EP15_OUT_CONTROL */ + __IOM uint32_t EP0_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP0_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP1_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP1_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP2_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP2_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP3_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP3_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP4_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP4_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP5_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP5_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP6_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP6_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP7_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP7_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP8_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP8_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP9_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP9_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP10_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP10_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP11_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP11_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP12_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP12_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP13_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP13_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP14_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP14_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP15_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ + __IOM uint32_t EP15_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending + in a _1 are for buffer 1. Fields ending in a _0 are for + buffer 0. Buffer 1 controls are only valid if the endpoint + is in double buffered mode. */ +} USB_DPRAM_Type; /*!< Size = 256 (0x100) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#if 0 +#define RESETS_BASE 0x40020000UL +#define PSM_BASE 0x40018000UL +#define CLOCKS_BASE 0x40010000UL +#define TICKS_BASE 0x40108000UL +#define PADS_BANK0_BASE 0x40038000UL +#define PADS_QSPI_BASE 0x40040000UL +#define IO_QSPI_BASE 0x40030000UL +#define IO_BANK0_BASE 0x40028000UL +#define SYSINFO_BASE 0x40000000UL +#define SHA256_BASE 0x400F8000UL +#define HSTX_FIFO_BASE 0x50600000UL +#define HSTX_CTRL_BASE 0x400C0000UL +#define EPPB_BASE 0xE0080000UL +#define PPB_BASE 0xE0000000UL +#define PPB_NS_BASE 0xE0020000UL +#define QMI_BASE 0x400D0000UL +#define XIP_CTRL_BASE 0x400C8000UL +#define XIP_AUX_BASE 0x50500000UL +#define SYSCFG_BASE 0x40008000UL +#define XOSC_BASE 0x40048000UL +#define PLL_SYS_BASE 0x40050000UL +#define PLL_USB_BASE 0x40058000UL +#define ACCESSCTRL_BASE 0x40060000UL +#define UART0_BASE 0x40070000UL +#define UART1_BASE 0x40078000UL +#define ROSC_BASE 0x400E8000UL +#define POWMAN_BASE 0x40100000UL +#define WATCHDOG_BASE 0x400D8000UL +#define DMA_BASE 0x50000000UL +#define TIMER0_BASE 0x400B0000UL +#define TIMER1_BASE 0x400B8000UL +#define PWM_BASE 0x400A8000UL +#define ADC_BASE 0x400A0000UL +#define I2C0_BASE 0x40090000UL +#define I2C1_BASE 0x40098000UL +#define SPI0_BASE 0x40080000UL +#define SPI1_BASE 0x40088000UL +#define PIO0_BASE 0x50200000UL +#define PIO1_BASE 0x50300000UL +#define PIO2_BASE 0x50400000UL +#define BUSCTRL_BASE 0x40068000UL +#define SIO_BASE 0xD0000000UL +#define SIO_NS_BASE 0xD0020000UL +#define BOOTRAM_BASE 0x400E0000UL +#define CORESIGHT_TRACE_BASE 0x50700000UL +#define USB_BASE 0x50110000UL +#define TRNG_BASE 0x400F0000UL +#define GLITCH_DETECTOR_BASE 0x40158000UL +#define OTP_BASE 0x40120000UL +#define OTP_DATA_BASE 0x40130000UL +#define OTP_DATA_RAW_BASE 0x40134000UL +#define TBMAN_BASE 0x40160000UL +#define USB_DPRAM_BASE 0x50100000UL +#endif + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define RESETS ((RESETS_Type*) RESETS_BASE) +#define PSM ((PSM_Type*) PSM_BASE) +#define CLOCKS ((CLOCKS_Type*) CLOCKS_BASE) +#define TICKS ((TICKS_Type*) TICKS_BASE) +#define PADS_BANK0 ((PADS_BANK0_Type*) PADS_BANK0_BASE) +#define PADS_QSPI ((PADS_QSPI_Type*) PADS_QSPI_BASE) +#define IO_QSPI ((IO_QSPI_Type*) IO_QSPI_BASE) +#define IO_BANK0 ((IO_BANK0_Type*) IO_BANK0_BASE) +#define SYSINFO ((SYSINFO_Type*) SYSINFO_BASE) +#define SHA256 ((SHA256_Type*) SHA256_BASE) +#define HSTX_FIFO ((HSTX_FIFO_Type*) HSTX_FIFO_BASE) +#define HSTX_CTRL ((HSTX_CTRL_Type*) HSTX_CTRL_BASE) +#define EPPB ((EPPB_Type*) EPPB_BASE) +#define PPB ((PPB_Type*) PPB_BASE) +#define PPB_NS ((PPB_Type*) PPB_NS_BASE) +#define QMI ((QMI_Type*) QMI_BASE) +#define XIP_CTRL ((XIP_CTRL_Type*) XIP_CTRL_BASE) +#define XIP_AUX ((XIP_AUX_Type*) XIP_AUX_BASE) +#define SYSCFG ((SYSCFG_Type*) SYSCFG_BASE) +#define XOSC ((XOSC_Type*) XOSC_BASE) +#define PLL_SYS ((PLL_SYS_Type*) PLL_SYS_BASE) +#define PLL_USB ((PLL_SYS_Type*) PLL_USB_BASE) +#define ACCESSCTRL ((ACCESSCTRL_Type*) ACCESSCTRL_BASE) +#define UART0 ((UART0_Type*) UART0_BASE) +#define UART1 ((UART0_Type*) UART1_BASE) +#define ROSC ((ROSC_Type*) ROSC_BASE) +#define POWMAN ((POWMAN_Type*) POWMAN_BASE) +#define WATCHDOG ((WATCHDOG_Type*) WATCHDOG_BASE) +#define DMA ((DMA_Type*) DMA_BASE) +#define TIMER0 ((TIMER0_Type*) TIMER0_BASE) +#define TIMER1 ((TIMER0_Type*) TIMER1_BASE) +#define PWM ((PWM_Type*) PWM_BASE) +#define ADC ((ADC_Type*) ADC_BASE) +#define I2C0 ((I2C0_Type*) I2C0_BASE) +#define I2C1 ((I2C0_Type*) I2C1_BASE) +#define SPI0 ((SPI0_Type*) SPI0_BASE) +#define SPI1 ((SPI0_Type*) SPI1_BASE) +#define PIO0 ((PIO0_Type*) PIO0_BASE) +#define PIO1 ((PIO0_Type*) PIO1_BASE) +#define PIO2 ((PIO0_Type*) PIO2_BASE) +#define BUSCTRL ((BUSCTRL_Type*) BUSCTRL_BASE) +#define SIO ((SIO_Type*) SIO_BASE) +#define SIO_NS ((SIO_Type*) SIO_NS_BASE) +#define BOOTRAM ((BOOTRAM_Type*) BOOTRAM_BASE) +#define CORESIGHT_TRACE ((CORESIGHT_TRACE_Type*) CORESIGHT_TRACE_BASE) +#define USB ((USB_Type*) USB_BASE) +#define TRNG ((TRNG_Type*) TRNG_BASE) +#define GLITCH_DETECTOR ((GLITCH_DETECTOR_Type*) GLITCH_DETECTOR_BASE) +#define OTP ((OTP_Type*) OTP_BASE) +#define OTP_DATA ((OTP_DATA_Type*) OTP_DATA_BASE) +#define OTP_DATA_RAW ((OTP_DATA_RAW_Type*) OTP_DATA_RAW_BASE) +#define TBMAN ((TBMAN_Type*) TBMAN_BASE) +#define USB_DPRAM ((USB_DPRAM_Type*) USB_DPRAM_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +#ifdef __cplusplus +} +#endif + +#endif /* RP2350_H */ + + +/** @} */ /* End of group RP2350 */ + +/** @} */ /* End of group Raspberry Pi */ diff --git a/lib/pico-sdk/rp2350/cmsis_include/system_RP2350.h b/lib/pico-sdk/rp2350/cmsis_include/system_RP2350.h new file mode 100644 index 000000000000..30881ccc63bf --- /dev/null +++ b/lib/pico-sdk/rp2350/cmsis_include/system_RP2350.h @@ -0,0 +1,65 @@ +/*************************************************************************//** + * @file system_RP2040.h + * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for + * Device RP2040 + * @version V1.0.0 + * @date 5. May 2021 + *****************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CMSIS_SYSTEM_RP2040_H +#define _CMSIS_SYSTEM_RP2040_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief Exception / Interrupt Handler Function Prototype +*/ +typedef void(*VECTOR_TABLE_Type)(void); + +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _CMSIS_SYSTEM_RP2040_H */ diff --git a/lib/pico-sdk/rp2350/hardware/regs/accessctrl.h b/lib/pico-sdk/rp2350/hardware/regs/accessctrl.h new file mode 100644 index 000000000000..2b8c4ca1f45c --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/accessctrl.h @@ -0,0 +1,4953 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : ACCESSCTRL +// Version : 1 +// Bus type : apb +// Description : Hardware access control registers +// ============================================================================= +#ifndef _HARDWARE_REGS_ACCESSCTRL_H +#define _HARDWARE_REGS_ACCESSCTRL_H +// ============================================================================= +// Register : ACCESSCTRL_LOCK +// Description : Once a LOCK bit is written to 1, ACCESSCTRL silently ignores +// writes from that master. LOCK is writable only by a Secure, +// Privileged processor or debugger. +// +// LOCK bits are only writable when their value is zero. Once set, +// they can never be cleared, except by a full reset of ACCESSCTRL +// +// Setting the LOCK bit does not affect whether an access raises a +// bus error. Unprivileged writes, or writes from the DMA, will +// continue to raise bus errors. All other accesses will continue +// not to. +#define ACCESSCTRL_LOCK_OFFSET _u(0x00000000) +#define ACCESSCTRL_LOCK_BITS _u(0x0000000f) +#define ACCESSCTRL_LOCK_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_LOCK_DEBUG +#define ACCESSCTRL_LOCK_DEBUG_RESET _u(0x0) +#define ACCESSCTRL_LOCK_DEBUG_BITS _u(0x00000008) +#define ACCESSCTRL_LOCK_DEBUG_MSB _u(3) +#define ACCESSCTRL_LOCK_DEBUG_LSB _u(3) +#define ACCESSCTRL_LOCK_DEBUG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_LOCK_DMA +#define ACCESSCTRL_LOCK_DMA_RESET _u(0x1) +#define ACCESSCTRL_LOCK_DMA_BITS _u(0x00000004) +#define ACCESSCTRL_LOCK_DMA_MSB _u(2) +#define ACCESSCTRL_LOCK_DMA_LSB _u(2) +#define ACCESSCTRL_LOCK_DMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_LOCK_CORE1 +#define ACCESSCTRL_LOCK_CORE1_RESET _u(0x0) +#define ACCESSCTRL_LOCK_CORE1_BITS _u(0x00000002) +#define ACCESSCTRL_LOCK_CORE1_MSB _u(1) +#define ACCESSCTRL_LOCK_CORE1_LSB _u(1) +#define ACCESSCTRL_LOCK_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_LOCK_CORE0 +#define ACCESSCTRL_LOCK_CORE0_RESET _u(0x0) +#define ACCESSCTRL_LOCK_CORE0_BITS _u(0x00000001) +#define ACCESSCTRL_LOCK_CORE0_MSB _u(0) +#define ACCESSCTRL_LOCK_CORE0_LSB _u(0) +#define ACCESSCTRL_LOCK_CORE0_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_FORCE_CORE_NS +// Description : Force core 1's bus accesses to always be Non-secure, no matter +// the core's internal state. +// +// Useful for schemes where one core is designated as the Non- +// secure core, since some peripherals may filter individual +// registers internally based on security state but not on master +// ID. +#define ACCESSCTRL_FORCE_CORE_NS_OFFSET _u(0x00000004) +#define ACCESSCTRL_FORCE_CORE_NS_BITS _u(0x00000002) +#define ACCESSCTRL_FORCE_CORE_NS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_FORCE_CORE_NS_CORE1 +#define ACCESSCTRL_FORCE_CORE_NS_CORE1_RESET _u(0x0) +#define ACCESSCTRL_FORCE_CORE_NS_CORE1_BITS _u(0x00000002) +#define ACCESSCTRL_FORCE_CORE_NS_CORE1_MSB _u(1) +#define ACCESSCTRL_FORCE_CORE_NS_CORE1_LSB _u(1) +#define ACCESSCTRL_FORCE_CORE_NS_CORE1_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_CFGRESET +// Description : Write 1 to reset all ACCESSCTRL configuration, except for the +// LOCK and FORCE_CORE_NS registers. +// +// This bit is used in the RP2350 bootrom to quickly restore +// ACCESSCTRL to a known state during the boot path. +// +// Note that, like all registers in ACCESSCTRL, this register is +// not writable when the writer's corresponding LOCK bit is set, +// therefore a master which has been locked out of ACCESSCTRL can +// not use the CFGRESET register to disturb its contents. +#define ACCESSCTRL_CFGRESET_OFFSET _u(0x00000008) +#define ACCESSCTRL_CFGRESET_BITS _u(0x00000001) +#define ACCESSCTRL_CFGRESET_RESET _u(0x00000000) +#define ACCESSCTRL_CFGRESET_MSB _u(0) +#define ACCESSCTRL_CFGRESET_LSB _u(0) +#define ACCESSCTRL_CFGRESET_ACCESS "SC" +// ============================================================================= +// Register : ACCESSCTRL_GPIO_NSMASK0 +// Description : Control whether GPIO0...31 are accessible to Non-secure code. +// Writable only by a Secure, Privileged processor or debugger. +// +// 0 -> Secure access only +// +// 1 -> Secure + Non-secure access +#define ACCESSCTRL_GPIO_NSMASK0_OFFSET _u(0x0000000c) +#define ACCESSCTRL_GPIO_NSMASK0_BITS _u(0xffffffff) +#define ACCESSCTRL_GPIO_NSMASK0_RESET _u(0x00000000) +#define ACCESSCTRL_GPIO_NSMASK0_MSB _u(31) +#define ACCESSCTRL_GPIO_NSMASK0_LSB _u(0) +#define ACCESSCTRL_GPIO_NSMASK0_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_GPIO_NSMASK1 +// Description : Control whether GPIO32..47 are accessible to Non-secure code, +// and whether QSPI and USB bitbang are accessible through the +// Non-secure SIO. Writable only by a Secure, Privileged processor +// or debugger. +#define ACCESSCTRL_GPIO_NSMASK1_OFFSET _u(0x00000010) +#define ACCESSCTRL_GPIO_NSMASK1_BITS _u(0xff00ffff) +#define ACCESSCTRL_GPIO_NSMASK1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_GPIO_NSMASK1_QSPI_SD +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_RESET _u(0x0) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_BITS _u(0xf0000000) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_MSB _u(31) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_LSB _u(28) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_RESET _u(0x0) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_BITS _u(0x08000000) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_MSB _u(27) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_LSB _u(27) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_CSN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_RESET _u(0x0) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_BITS _u(0x04000000) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_MSB _u(26) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_LSB _u(26) +#define ACCESSCTRL_GPIO_NSMASK1_QSPI_SCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_GPIO_NSMASK1_USB_DM +#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_RESET _u(0x0) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_BITS _u(0x02000000) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_MSB _u(25) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_LSB _u(25) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_GPIO_NSMASK1_USB_DP +#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_RESET _u(0x0) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_BITS _u(0x01000000) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_MSB _u(24) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_LSB _u(24) +#define ACCESSCTRL_GPIO_NSMASK1_USB_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_GPIO_NSMASK1_GPIO +#define ACCESSCTRL_GPIO_NSMASK1_GPIO_RESET _u(0x0000) +#define ACCESSCTRL_GPIO_NSMASK1_GPIO_BITS _u(0x0000ffff) +#define ACCESSCTRL_GPIO_NSMASK1_GPIO_MSB _u(15) +#define ACCESSCTRL_GPIO_NSMASK1_GPIO_LSB _u(0) +#define ACCESSCTRL_GPIO_NSMASK1_GPIO_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_ROM +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// ROM, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_ROM_OFFSET _u(0x00000014) +#define ACCESSCTRL_ROM_BITS _u(0x000000ff) +#define ACCESSCTRL_ROM_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_DBG +// Description : If 1, ROM can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_ROM_DBG_RESET _u(0x1) +#define ACCESSCTRL_ROM_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_ROM_DBG_MSB _u(7) +#define ACCESSCTRL_ROM_DBG_LSB _u(7) +#define ACCESSCTRL_ROM_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_DMA +// Description : If 1, ROM can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ROM_DMA_RESET _u(0x1) +#define ACCESSCTRL_ROM_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_ROM_DMA_MSB _u(6) +#define ACCESSCTRL_ROM_DMA_LSB _u(6) +#define ACCESSCTRL_ROM_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_CORE1 +// Description : If 1, ROM can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ROM_CORE1_RESET _u(0x1) +#define ACCESSCTRL_ROM_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_ROM_CORE1_MSB _u(5) +#define ACCESSCTRL_ROM_CORE1_LSB _u(5) +#define ACCESSCTRL_ROM_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_CORE0 +// Description : If 1, ROM can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ROM_CORE0_RESET _u(0x1) +#define ACCESSCTRL_ROM_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_ROM_CORE0_MSB _u(4) +#define ACCESSCTRL_ROM_CORE0_LSB _u(4) +#define ACCESSCTRL_ROM_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_SP +// Description : If 1, ROM can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_ROM_SP_RESET _u(0x1) +#define ACCESSCTRL_ROM_SP_BITS _u(0x00000008) +#define ACCESSCTRL_ROM_SP_MSB _u(3) +#define ACCESSCTRL_ROM_SP_LSB _u(3) +#define ACCESSCTRL_ROM_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_SU +// Description : If 1, and SP is also set, ROM can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_ROM_SU_RESET _u(0x1) +#define ACCESSCTRL_ROM_SU_BITS _u(0x00000004) +#define ACCESSCTRL_ROM_SU_MSB _u(2) +#define ACCESSCTRL_ROM_SU_LSB _u(2) +#define ACCESSCTRL_ROM_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_NSP +// Description : If 1, ROM can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_ROM_NSP_RESET _u(0x1) +#define ACCESSCTRL_ROM_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_ROM_NSP_MSB _u(1) +#define ACCESSCTRL_ROM_NSP_LSB _u(1) +#define ACCESSCTRL_ROM_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROM_NSU +// Description : If 1, and NSP is also set, ROM can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_ROM_NSU_RESET _u(0x1) +#define ACCESSCTRL_ROM_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_ROM_NSU_MSB _u(0) +#define ACCESSCTRL_ROM_NSU_LSB _u(0) +#define ACCESSCTRL_ROM_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_XIP_MAIN +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// XIP_MAIN, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_XIP_MAIN_OFFSET _u(0x00000018) +#define ACCESSCTRL_XIP_MAIN_BITS _u(0x000000ff) +#define ACCESSCTRL_XIP_MAIN_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_DBG +// Description : If 1, XIP_MAIN can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_XIP_MAIN_DBG_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_XIP_MAIN_DBG_MSB _u(7) +#define ACCESSCTRL_XIP_MAIN_DBG_LSB _u(7) +#define ACCESSCTRL_XIP_MAIN_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_DMA +// Description : If 1, XIP_MAIN can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_XIP_MAIN_DMA_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_XIP_MAIN_DMA_MSB _u(6) +#define ACCESSCTRL_XIP_MAIN_DMA_LSB _u(6) +#define ACCESSCTRL_XIP_MAIN_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_CORE1 +// Description : If 1, XIP_MAIN can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_MAIN_CORE1_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_XIP_MAIN_CORE1_MSB _u(5) +#define ACCESSCTRL_XIP_MAIN_CORE1_LSB _u(5) +#define ACCESSCTRL_XIP_MAIN_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_CORE0 +// Description : If 1, XIP_MAIN can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_MAIN_CORE0_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_XIP_MAIN_CORE0_MSB _u(4) +#define ACCESSCTRL_XIP_MAIN_CORE0_LSB _u(4) +#define ACCESSCTRL_XIP_MAIN_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_SP +// Description : If 1, XIP_MAIN can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_XIP_MAIN_SP_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_SP_BITS _u(0x00000008) +#define ACCESSCTRL_XIP_MAIN_SP_MSB _u(3) +#define ACCESSCTRL_XIP_MAIN_SP_LSB _u(3) +#define ACCESSCTRL_XIP_MAIN_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_SU +// Description : If 1, and SP is also set, XIP_MAIN can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_XIP_MAIN_SU_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_SU_BITS _u(0x00000004) +#define ACCESSCTRL_XIP_MAIN_SU_MSB _u(2) +#define ACCESSCTRL_XIP_MAIN_SU_LSB _u(2) +#define ACCESSCTRL_XIP_MAIN_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_NSP +// Description : If 1, XIP_MAIN can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_XIP_MAIN_NSP_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_XIP_MAIN_NSP_MSB _u(1) +#define ACCESSCTRL_XIP_MAIN_NSP_LSB _u(1) +#define ACCESSCTRL_XIP_MAIN_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_MAIN_NSU +// Description : If 1, and NSP is also set, XIP_MAIN can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_XIP_MAIN_NSU_RESET _u(0x1) +#define ACCESSCTRL_XIP_MAIN_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_XIP_MAIN_NSU_MSB _u(0) +#define ACCESSCTRL_XIP_MAIN_NSU_LSB _u(0) +#define ACCESSCTRL_XIP_MAIN_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM0, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM0_OFFSET _u(0x0000001c) +#define ACCESSCTRL_SRAM0_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM0_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_DBG +// Description : If 1, SRAM0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM0_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM0_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM0_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_DMA +// Description : If 1, SRAM0 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM0_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM0_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM0_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_CORE1 +// Description : If 1, SRAM0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM0_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM0_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_CORE0 +// Description : If 1, SRAM0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM0_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM0_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_SP +// Description : If 1, SRAM0 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM0_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM0_SP_MSB _u(3) +#define ACCESSCTRL_SRAM0_SP_LSB _u(3) +#define ACCESSCTRL_SRAM0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_SU +// Description : If 1, and SP is also set, SRAM0 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM0_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM0_SU_MSB _u(2) +#define ACCESSCTRL_SRAM0_SU_LSB _u(2) +#define ACCESSCTRL_SRAM0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_NSP +// Description : If 1, SRAM0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM0_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM0_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM0_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM0_NSU +// Description : If 1, and NSP is also set, SRAM0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM0_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM0_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM0_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM1 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM1, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM1_OFFSET _u(0x00000020) +#define ACCESSCTRL_SRAM1_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM1_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_DBG +// Description : If 1, SRAM1 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM1_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM1_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM1_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM1_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_DMA +// Description : If 1, SRAM1 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM1_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM1_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM1_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM1_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_CORE1 +// Description : If 1, SRAM1 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM1_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM1_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM1_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM1_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_CORE0 +// Description : If 1, SRAM1 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM1_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM1_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM1_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM1_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_SP +// Description : If 1, SRAM1 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM1_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM1_SP_MSB _u(3) +#define ACCESSCTRL_SRAM1_SP_LSB _u(3) +#define ACCESSCTRL_SRAM1_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_SU +// Description : If 1, and SP is also set, SRAM1 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM1_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM1_SU_MSB _u(2) +#define ACCESSCTRL_SRAM1_SU_LSB _u(2) +#define ACCESSCTRL_SRAM1_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_NSP +// Description : If 1, SRAM1 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM1_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM1_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM1_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM1_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM1_NSU +// Description : If 1, and NSP is also set, SRAM1 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM1_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM1_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM1_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM1_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM1_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM2 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM2, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM2_OFFSET _u(0x00000024) +#define ACCESSCTRL_SRAM2_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM2_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_DBG +// Description : If 1, SRAM2 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM2_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM2_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM2_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM2_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_DMA +// Description : If 1, SRAM2 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM2_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM2_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM2_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM2_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_CORE1 +// Description : If 1, SRAM2 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM2_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM2_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM2_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM2_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_CORE0 +// Description : If 1, SRAM2 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM2_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM2_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM2_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM2_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_SP +// Description : If 1, SRAM2 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM2_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM2_SP_MSB _u(3) +#define ACCESSCTRL_SRAM2_SP_LSB _u(3) +#define ACCESSCTRL_SRAM2_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_SU +// Description : If 1, and SP is also set, SRAM2 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM2_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM2_SU_MSB _u(2) +#define ACCESSCTRL_SRAM2_SU_LSB _u(2) +#define ACCESSCTRL_SRAM2_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_NSP +// Description : If 1, SRAM2 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM2_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM2_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM2_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM2_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM2_NSU +// Description : If 1, and NSP is also set, SRAM2 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM2_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM2_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM2_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM2_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM2_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM3 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM3, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM3_OFFSET _u(0x00000028) +#define ACCESSCTRL_SRAM3_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM3_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_DBG +// Description : If 1, SRAM3 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM3_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM3_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM3_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM3_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_DMA +// Description : If 1, SRAM3 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM3_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM3_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM3_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM3_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_CORE1 +// Description : If 1, SRAM3 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM3_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM3_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM3_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM3_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_CORE0 +// Description : If 1, SRAM3 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM3_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM3_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM3_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM3_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_SP +// Description : If 1, SRAM3 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM3_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM3_SP_MSB _u(3) +#define ACCESSCTRL_SRAM3_SP_LSB _u(3) +#define ACCESSCTRL_SRAM3_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_SU +// Description : If 1, and SP is also set, SRAM3 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM3_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM3_SU_MSB _u(2) +#define ACCESSCTRL_SRAM3_SU_LSB _u(2) +#define ACCESSCTRL_SRAM3_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_NSP +// Description : If 1, SRAM3 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM3_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM3_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM3_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM3_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM3_NSU +// Description : If 1, and NSP is also set, SRAM3 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM3_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM3_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM3_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM3_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM3_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM4 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM4, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM4_OFFSET _u(0x0000002c) +#define ACCESSCTRL_SRAM4_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM4_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_DBG +// Description : If 1, SRAM4 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM4_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM4_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM4_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM4_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_DMA +// Description : If 1, SRAM4 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM4_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM4_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM4_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM4_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_CORE1 +// Description : If 1, SRAM4 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM4_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM4_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM4_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM4_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_CORE0 +// Description : If 1, SRAM4 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM4_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM4_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM4_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM4_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_SP +// Description : If 1, SRAM4 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM4_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM4_SP_MSB _u(3) +#define ACCESSCTRL_SRAM4_SP_LSB _u(3) +#define ACCESSCTRL_SRAM4_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_SU +// Description : If 1, and SP is also set, SRAM4 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM4_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM4_SU_MSB _u(2) +#define ACCESSCTRL_SRAM4_SU_LSB _u(2) +#define ACCESSCTRL_SRAM4_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_NSP +// Description : If 1, SRAM4 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM4_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM4_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM4_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM4_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM4_NSU +// Description : If 1, and NSP is also set, SRAM4 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM4_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM4_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM4_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM4_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM4_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM5 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM5, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM5_OFFSET _u(0x00000030) +#define ACCESSCTRL_SRAM5_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM5_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_DBG +// Description : If 1, SRAM5 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM5_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM5_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM5_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM5_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_DMA +// Description : If 1, SRAM5 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM5_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM5_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM5_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM5_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_CORE1 +// Description : If 1, SRAM5 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM5_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM5_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM5_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM5_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_CORE0 +// Description : If 1, SRAM5 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM5_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM5_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM5_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM5_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_SP +// Description : If 1, SRAM5 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM5_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM5_SP_MSB _u(3) +#define ACCESSCTRL_SRAM5_SP_LSB _u(3) +#define ACCESSCTRL_SRAM5_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_SU +// Description : If 1, and SP is also set, SRAM5 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM5_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM5_SU_MSB _u(2) +#define ACCESSCTRL_SRAM5_SU_LSB _u(2) +#define ACCESSCTRL_SRAM5_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_NSP +// Description : If 1, SRAM5 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM5_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM5_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM5_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM5_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM5_NSU +// Description : If 1, and NSP is also set, SRAM5 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM5_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM5_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM5_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM5_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM5_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM6 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM6, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM6_OFFSET _u(0x00000034) +#define ACCESSCTRL_SRAM6_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM6_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_DBG +// Description : If 1, SRAM6 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM6_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM6_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM6_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM6_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_DMA +// Description : If 1, SRAM6 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM6_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM6_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM6_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM6_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_CORE1 +// Description : If 1, SRAM6 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM6_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM6_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM6_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM6_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_CORE0 +// Description : If 1, SRAM6 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM6_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM6_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM6_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM6_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_SP +// Description : If 1, SRAM6 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM6_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM6_SP_MSB _u(3) +#define ACCESSCTRL_SRAM6_SP_LSB _u(3) +#define ACCESSCTRL_SRAM6_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_SU +// Description : If 1, and SP is also set, SRAM6 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM6_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM6_SU_MSB _u(2) +#define ACCESSCTRL_SRAM6_SU_LSB _u(2) +#define ACCESSCTRL_SRAM6_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_NSP +// Description : If 1, SRAM6 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM6_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM6_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM6_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM6_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM6_NSU +// Description : If 1, and NSP is also set, SRAM6 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM6_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM6_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM6_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM6_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM6_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM7 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM7, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM7_OFFSET _u(0x00000038) +#define ACCESSCTRL_SRAM7_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM7_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_DBG +// Description : If 1, SRAM7 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM7_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM7_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM7_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM7_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_DMA +// Description : If 1, SRAM7 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM7_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM7_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM7_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM7_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_CORE1 +// Description : If 1, SRAM7 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM7_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM7_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM7_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM7_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_CORE0 +// Description : If 1, SRAM7 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM7_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM7_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM7_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM7_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_SP +// Description : If 1, SRAM7 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM7_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM7_SP_MSB _u(3) +#define ACCESSCTRL_SRAM7_SP_LSB _u(3) +#define ACCESSCTRL_SRAM7_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_SU +// Description : If 1, and SP is also set, SRAM7 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM7_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM7_SU_MSB _u(2) +#define ACCESSCTRL_SRAM7_SU_LSB _u(2) +#define ACCESSCTRL_SRAM7_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_NSP +// Description : If 1, SRAM7 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM7_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM7_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM7_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM7_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM7_NSU +// Description : If 1, and NSP is also set, SRAM7 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM7_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM7_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM7_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM7_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM7_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM8 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM8, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM8_OFFSET _u(0x0000003c) +#define ACCESSCTRL_SRAM8_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM8_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_DBG +// Description : If 1, SRAM8 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM8_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM8_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM8_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM8_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_DMA +// Description : If 1, SRAM8 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM8_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM8_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM8_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM8_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_CORE1 +// Description : If 1, SRAM8 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM8_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM8_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM8_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM8_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_CORE0 +// Description : If 1, SRAM8 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM8_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM8_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM8_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM8_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_SP +// Description : If 1, SRAM8 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM8_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM8_SP_MSB _u(3) +#define ACCESSCTRL_SRAM8_SP_LSB _u(3) +#define ACCESSCTRL_SRAM8_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_SU +// Description : If 1, and SP is also set, SRAM8 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM8_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM8_SU_MSB _u(2) +#define ACCESSCTRL_SRAM8_SU_LSB _u(2) +#define ACCESSCTRL_SRAM8_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_NSP +// Description : If 1, SRAM8 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM8_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM8_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM8_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM8_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM8_NSU +// Description : If 1, and NSP is also set, SRAM8 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM8_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM8_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM8_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM8_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM8_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SRAM9 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SRAM9, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SRAM9_OFFSET _u(0x00000040) +#define ACCESSCTRL_SRAM9_BITS _u(0x000000ff) +#define ACCESSCTRL_SRAM9_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_DBG +// Description : If 1, SRAM9 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SRAM9_DBG_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SRAM9_DBG_MSB _u(7) +#define ACCESSCTRL_SRAM9_DBG_LSB _u(7) +#define ACCESSCTRL_SRAM9_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_DMA +// Description : If 1, SRAM9 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM9_DMA_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SRAM9_DMA_MSB _u(6) +#define ACCESSCTRL_SRAM9_DMA_LSB _u(6) +#define ACCESSCTRL_SRAM9_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_CORE1 +// Description : If 1, SRAM9 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM9_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SRAM9_CORE1_MSB _u(5) +#define ACCESSCTRL_SRAM9_CORE1_LSB _u(5) +#define ACCESSCTRL_SRAM9_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_CORE0 +// Description : If 1, SRAM9 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SRAM9_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SRAM9_CORE0_MSB _u(4) +#define ACCESSCTRL_SRAM9_CORE0_LSB _u(4) +#define ACCESSCTRL_SRAM9_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_SP +// Description : If 1, SRAM9 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SRAM9_SP_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SRAM9_SP_MSB _u(3) +#define ACCESSCTRL_SRAM9_SP_LSB _u(3) +#define ACCESSCTRL_SRAM9_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_SU +// Description : If 1, and SP is also set, SRAM9 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SRAM9_SU_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SRAM9_SU_MSB _u(2) +#define ACCESSCTRL_SRAM9_SU_LSB _u(2) +#define ACCESSCTRL_SRAM9_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_NSP +// Description : If 1, SRAM9 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SRAM9_NSP_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SRAM9_NSP_MSB _u(1) +#define ACCESSCTRL_SRAM9_NSP_LSB _u(1) +#define ACCESSCTRL_SRAM9_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SRAM9_NSU +// Description : If 1, and NSP is also set, SRAM9 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SRAM9_NSU_RESET _u(0x1) +#define ACCESSCTRL_SRAM9_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SRAM9_NSU_MSB _u(0) +#define ACCESSCTRL_SRAM9_NSU_LSB _u(0) +#define ACCESSCTRL_SRAM9_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_DMA +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// DMA, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_DMA_OFFSET _u(0x00000044) +#define ACCESSCTRL_DMA_BITS _u(0x000000ff) +#define ACCESSCTRL_DMA_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_DBG +// Description : If 1, DMA can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_DMA_DBG_RESET _u(0x1) +#define ACCESSCTRL_DMA_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_DMA_DBG_MSB _u(7) +#define ACCESSCTRL_DMA_DBG_LSB _u(7) +#define ACCESSCTRL_DMA_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_DMA +// Description : If 1, DMA can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_DMA_DMA_RESET _u(0x1) +#define ACCESSCTRL_DMA_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_DMA_DMA_MSB _u(6) +#define ACCESSCTRL_DMA_DMA_LSB _u(6) +#define ACCESSCTRL_DMA_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_CORE1 +// Description : If 1, DMA can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_DMA_CORE1_RESET _u(0x1) +#define ACCESSCTRL_DMA_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_DMA_CORE1_MSB _u(5) +#define ACCESSCTRL_DMA_CORE1_LSB _u(5) +#define ACCESSCTRL_DMA_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_CORE0 +// Description : If 1, DMA can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_DMA_CORE0_RESET _u(0x1) +#define ACCESSCTRL_DMA_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_DMA_CORE0_MSB _u(4) +#define ACCESSCTRL_DMA_CORE0_LSB _u(4) +#define ACCESSCTRL_DMA_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_SP +// Description : If 1, DMA can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_DMA_SP_RESET _u(0x1) +#define ACCESSCTRL_DMA_SP_BITS _u(0x00000008) +#define ACCESSCTRL_DMA_SP_MSB _u(3) +#define ACCESSCTRL_DMA_SP_LSB _u(3) +#define ACCESSCTRL_DMA_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_SU +// Description : If 1, and SP is also set, DMA can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_DMA_SU_RESET _u(0x1) +#define ACCESSCTRL_DMA_SU_BITS _u(0x00000004) +#define ACCESSCTRL_DMA_SU_MSB _u(2) +#define ACCESSCTRL_DMA_SU_LSB _u(2) +#define ACCESSCTRL_DMA_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_NSP +// Description : If 1, DMA can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_DMA_NSP_RESET _u(0x0) +#define ACCESSCTRL_DMA_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_DMA_NSP_MSB _u(1) +#define ACCESSCTRL_DMA_NSP_LSB _u(1) +#define ACCESSCTRL_DMA_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_DMA_NSU +// Description : If 1, and NSP is also set, DMA can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_DMA_NSU_RESET _u(0x0) +#define ACCESSCTRL_DMA_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_DMA_NSU_MSB _u(0) +#define ACCESSCTRL_DMA_NSU_LSB _u(0) +#define ACCESSCTRL_DMA_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_USBCTRL +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// USBCTRL, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_USBCTRL_OFFSET _u(0x00000048) +#define ACCESSCTRL_USBCTRL_BITS _u(0x000000ff) +#define ACCESSCTRL_USBCTRL_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_DBG +// Description : If 1, USBCTRL can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_USBCTRL_DBG_RESET _u(0x1) +#define ACCESSCTRL_USBCTRL_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_USBCTRL_DBG_MSB _u(7) +#define ACCESSCTRL_USBCTRL_DBG_LSB _u(7) +#define ACCESSCTRL_USBCTRL_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_DMA +// Description : If 1, USBCTRL can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_USBCTRL_DMA_RESET _u(0x1) +#define ACCESSCTRL_USBCTRL_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_USBCTRL_DMA_MSB _u(6) +#define ACCESSCTRL_USBCTRL_DMA_LSB _u(6) +#define ACCESSCTRL_USBCTRL_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_CORE1 +// Description : If 1, USBCTRL can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_USBCTRL_CORE1_RESET _u(0x1) +#define ACCESSCTRL_USBCTRL_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_USBCTRL_CORE1_MSB _u(5) +#define ACCESSCTRL_USBCTRL_CORE1_LSB _u(5) +#define ACCESSCTRL_USBCTRL_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_CORE0 +// Description : If 1, USBCTRL can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_USBCTRL_CORE0_RESET _u(0x1) +#define ACCESSCTRL_USBCTRL_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_USBCTRL_CORE0_MSB _u(4) +#define ACCESSCTRL_USBCTRL_CORE0_LSB _u(4) +#define ACCESSCTRL_USBCTRL_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_SP +// Description : If 1, USBCTRL can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_USBCTRL_SP_RESET _u(0x1) +#define ACCESSCTRL_USBCTRL_SP_BITS _u(0x00000008) +#define ACCESSCTRL_USBCTRL_SP_MSB _u(3) +#define ACCESSCTRL_USBCTRL_SP_LSB _u(3) +#define ACCESSCTRL_USBCTRL_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_SU +// Description : If 1, and SP is also set, USBCTRL can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_USBCTRL_SU_RESET _u(0x1) +#define ACCESSCTRL_USBCTRL_SU_BITS _u(0x00000004) +#define ACCESSCTRL_USBCTRL_SU_MSB _u(2) +#define ACCESSCTRL_USBCTRL_SU_LSB _u(2) +#define ACCESSCTRL_USBCTRL_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_NSP +// Description : If 1, USBCTRL can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_USBCTRL_NSP_RESET _u(0x0) +#define ACCESSCTRL_USBCTRL_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_USBCTRL_NSP_MSB _u(1) +#define ACCESSCTRL_USBCTRL_NSP_LSB _u(1) +#define ACCESSCTRL_USBCTRL_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_USBCTRL_NSU +// Description : If 1, and NSP is also set, USBCTRL can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_USBCTRL_NSU_RESET _u(0x0) +#define ACCESSCTRL_USBCTRL_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_USBCTRL_NSU_MSB _u(0) +#define ACCESSCTRL_USBCTRL_NSU_LSB _u(0) +#define ACCESSCTRL_USBCTRL_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PIO0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PIO0, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PIO0_OFFSET _u(0x0000004c) +#define ACCESSCTRL_PIO0_BITS _u(0x000000ff) +#define ACCESSCTRL_PIO0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_DBG +// Description : If 1, PIO0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PIO0_DBG_RESET _u(0x1) +#define ACCESSCTRL_PIO0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PIO0_DBG_MSB _u(7) +#define ACCESSCTRL_PIO0_DBG_LSB _u(7) +#define ACCESSCTRL_PIO0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_DMA +// Description : If 1, PIO0 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO0_DMA_RESET _u(0x1) +#define ACCESSCTRL_PIO0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PIO0_DMA_MSB _u(6) +#define ACCESSCTRL_PIO0_DMA_LSB _u(6) +#define ACCESSCTRL_PIO0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_CORE1 +// Description : If 1, PIO0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PIO0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PIO0_CORE1_MSB _u(5) +#define ACCESSCTRL_PIO0_CORE1_LSB _u(5) +#define ACCESSCTRL_PIO0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_CORE0 +// Description : If 1, PIO0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PIO0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PIO0_CORE0_MSB _u(4) +#define ACCESSCTRL_PIO0_CORE0_LSB _u(4) +#define ACCESSCTRL_PIO0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_SP +// Description : If 1, PIO0 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_PIO0_SP_RESET _u(0x1) +#define ACCESSCTRL_PIO0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PIO0_SP_MSB _u(3) +#define ACCESSCTRL_PIO0_SP_LSB _u(3) +#define ACCESSCTRL_PIO0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_SU +// Description : If 1, and SP is also set, PIO0 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_PIO0_SU_RESET _u(0x1) +#define ACCESSCTRL_PIO0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PIO0_SU_MSB _u(2) +#define ACCESSCTRL_PIO0_SU_LSB _u(2) +#define ACCESSCTRL_PIO0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_NSP +// Description : If 1, PIO0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PIO0_NSP_RESET _u(0x0) +#define ACCESSCTRL_PIO0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PIO0_NSP_MSB _u(1) +#define ACCESSCTRL_PIO0_NSP_LSB _u(1) +#define ACCESSCTRL_PIO0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO0_NSU +// Description : If 1, and NSP is also set, PIO0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PIO0_NSU_RESET _u(0x0) +#define ACCESSCTRL_PIO0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PIO0_NSU_MSB _u(0) +#define ACCESSCTRL_PIO0_NSU_LSB _u(0) +#define ACCESSCTRL_PIO0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PIO1 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PIO1, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PIO1_OFFSET _u(0x00000050) +#define ACCESSCTRL_PIO1_BITS _u(0x000000ff) +#define ACCESSCTRL_PIO1_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_DBG +// Description : If 1, PIO1 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PIO1_DBG_RESET _u(0x1) +#define ACCESSCTRL_PIO1_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PIO1_DBG_MSB _u(7) +#define ACCESSCTRL_PIO1_DBG_LSB _u(7) +#define ACCESSCTRL_PIO1_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_DMA +// Description : If 1, PIO1 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO1_DMA_RESET _u(0x1) +#define ACCESSCTRL_PIO1_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PIO1_DMA_MSB _u(6) +#define ACCESSCTRL_PIO1_DMA_LSB _u(6) +#define ACCESSCTRL_PIO1_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_CORE1 +// Description : If 1, PIO1 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO1_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PIO1_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PIO1_CORE1_MSB _u(5) +#define ACCESSCTRL_PIO1_CORE1_LSB _u(5) +#define ACCESSCTRL_PIO1_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_CORE0 +// Description : If 1, PIO1 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO1_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PIO1_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PIO1_CORE0_MSB _u(4) +#define ACCESSCTRL_PIO1_CORE0_LSB _u(4) +#define ACCESSCTRL_PIO1_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_SP +// Description : If 1, PIO1 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_PIO1_SP_RESET _u(0x1) +#define ACCESSCTRL_PIO1_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PIO1_SP_MSB _u(3) +#define ACCESSCTRL_PIO1_SP_LSB _u(3) +#define ACCESSCTRL_PIO1_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_SU +// Description : If 1, and SP is also set, PIO1 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_PIO1_SU_RESET _u(0x1) +#define ACCESSCTRL_PIO1_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PIO1_SU_MSB _u(2) +#define ACCESSCTRL_PIO1_SU_LSB _u(2) +#define ACCESSCTRL_PIO1_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_NSP +// Description : If 1, PIO1 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PIO1_NSP_RESET _u(0x0) +#define ACCESSCTRL_PIO1_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PIO1_NSP_MSB _u(1) +#define ACCESSCTRL_PIO1_NSP_LSB _u(1) +#define ACCESSCTRL_PIO1_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO1_NSU +// Description : If 1, and NSP is also set, PIO1 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PIO1_NSU_RESET _u(0x0) +#define ACCESSCTRL_PIO1_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PIO1_NSU_MSB _u(0) +#define ACCESSCTRL_PIO1_NSU_LSB _u(0) +#define ACCESSCTRL_PIO1_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PIO2 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PIO2, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PIO2_OFFSET _u(0x00000054) +#define ACCESSCTRL_PIO2_BITS _u(0x000000ff) +#define ACCESSCTRL_PIO2_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_DBG +// Description : If 1, PIO2 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PIO2_DBG_RESET _u(0x1) +#define ACCESSCTRL_PIO2_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PIO2_DBG_MSB _u(7) +#define ACCESSCTRL_PIO2_DBG_LSB _u(7) +#define ACCESSCTRL_PIO2_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_DMA +// Description : If 1, PIO2 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO2_DMA_RESET _u(0x1) +#define ACCESSCTRL_PIO2_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PIO2_DMA_MSB _u(6) +#define ACCESSCTRL_PIO2_DMA_LSB _u(6) +#define ACCESSCTRL_PIO2_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_CORE1 +// Description : If 1, PIO2 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO2_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PIO2_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PIO2_CORE1_MSB _u(5) +#define ACCESSCTRL_PIO2_CORE1_LSB _u(5) +#define ACCESSCTRL_PIO2_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_CORE0 +// Description : If 1, PIO2 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PIO2_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PIO2_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PIO2_CORE0_MSB _u(4) +#define ACCESSCTRL_PIO2_CORE0_LSB _u(4) +#define ACCESSCTRL_PIO2_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_SP +// Description : If 1, PIO2 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_PIO2_SP_RESET _u(0x1) +#define ACCESSCTRL_PIO2_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PIO2_SP_MSB _u(3) +#define ACCESSCTRL_PIO2_SP_LSB _u(3) +#define ACCESSCTRL_PIO2_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_SU +// Description : If 1, and SP is also set, PIO2 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_PIO2_SU_RESET _u(0x1) +#define ACCESSCTRL_PIO2_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PIO2_SU_MSB _u(2) +#define ACCESSCTRL_PIO2_SU_LSB _u(2) +#define ACCESSCTRL_PIO2_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_NSP +// Description : If 1, PIO2 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PIO2_NSP_RESET _u(0x0) +#define ACCESSCTRL_PIO2_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PIO2_NSP_MSB _u(1) +#define ACCESSCTRL_PIO2_NSP_LSB _u(1) +#define ACCESSCTRL_PIO2_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PIO2_NSU +// Description : If 1, and NSP is also set, PIO2 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PIO2_NSU_RESET _u(0x0) +#define ACCESSCTRL_PIO2_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PIO2_NSU_MSB _u(0) +#define ACCESSCTRL_PIO2_NSU_LSB _u(0) +#define ACCESSCTRL_PIO2_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_CORESIGHT_TRACE +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// CORESIGHT_TRACE, and at what security/privilege levels they can +// do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_CORESIGHT_TRACE_OFFSET _u(0x00000058) +#define ACCESSCTRL_CORESIGHT_TRACE_BITS _u(0x000000ff) +#define ACCESSCTRL_CORESIGHT_TRACE_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_DBG +// Description : If 1, CORESIGHT_TRACE can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_TRACE_DBG_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_TRACE_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_CORESIGHT_TRACE_DBG_MSB _u(7) +#define ACCESSCTRL_CORESIGHT_TRACE_DBG_LSB _u(7) +#define ACCESSCTRL_CORESIGHT_TRACE_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_DMA +// Description : If 1, CORESIGHT_TRACE can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_TRACE_DMA_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_TRACE_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_CORESIGHT_TRACE_DMA_MSB _u(6) +#define ACCESSCTRL_CORESIGHT_TRACE_DMA_LSB _u(6) +#define ACCESSCTRL_CORESIGHT_TRACE_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_CORE1 +// Description : If 1, CORESIGHT_TRACE can be accessed by core 1, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_MSB _u(5) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_LSB _u(5) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_CORE0 +// Description : If 1, CORESIGHT_TRACE can be accessed by core 0, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_MSB _u(4) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_LSB _u(4) +#define ACCESSCTRL_CORESIGHT_TRACE_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_SP +// Description : If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_CORESIGHT_TRACE_SP_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_TRACE_SP_BITS _u(0x00000008) +#define ACCESSCTRL_CORESIGHT_TRACE_SP_MSB _u(3) +#define ACCESSCTRL_CORESIGHT_TRACE_SP_LSB _u(3) +#define ACCESSCTRL_CORESIGHT_TRACE_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_SU +// Description : If 1, and SP is also set, CORESIGHT_TRACE can be accessed from +// a Secure, Unprivileged context. +#define ACCESSCTRL_CORESIGHT_TRACE_SU_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_TRACE_SU_BITS _u(0x00000004) +#define ACCESSCTRL_CORESIGHT_TRACE_SU_MSB _u(2) +#define ACCESSCTRL_CORESIGHT_TRACE_SU_LSB _u(2) +#define ACCESSCTRL_CORESIGHT_TRACE_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_NSP +// Description : If 1, CORESIGHT_TRACE can be accessed from a Non-secure, +// Privileged context. +#define ACCESSCTRL_CORESIGHT_TRACE_NSP_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_TRACE_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_CORESIGHT_TRACE_NSP_MSB _u(1) +#define ACCESSCTRL_CORESIGHT_TRACE_NSP_LSB _u(1) +#define ACCESSCTRL_CORESIGHT_TRACE_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_TRACE_NSU +// Description : If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from +// a Non-secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_CORESIGHT_TRACE_NSU_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_TRACE_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_CORESIGHT_TRACE_NSU_MSB _u(0) +#define ACCESSCTRL_CORESIGHT_TRACE_NSU_LSB _u(0) +#define ACCESSCTRL_CORESIGHT_TRACE_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_CORESIGHT_PERIPH +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// CORESIGHT_PERIPH, and at what security/privilege levels they +// can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_CORESIGHT_PERIPH_OFFSET _u(0x0000005c) +#define ACCESSCTRL_CORESIGHT_PERIPH_BITS _u(0x000000ff) +#define ACCESSCTRL_CORESIGHT_PERIPH_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_DBG +// Description : If 1, CORESIGHT_PERIPH can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_MSB _u(7) +#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_LSB _u(7) +#define ACCESSCTRL_CORESIGHT_PERIPH_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_DMA +// Description : If 1, CORESIGHT_PERIPH can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_MSB _u(6) +#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_LSB _u(6) +#define ACCESSCTRL_CORESIGHT_PERIPH_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_CORE1 +// Description : If 1, CORESIGHT_PERIPH can be accessed by core 1, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_MSB _u(5) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_LSB _u(5) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_CORE0 +// Description : If 1, CORESIGHT_PERIPH can be accessed by core 0, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_MSB _u(4) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_LSB _u(4) +#define ACCESSCTRL_CORESIGHT_PERIPH_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_SP +// Description : If 1, CORESIGHT_PERIPH can be accessed from a Secure, +// Privileged context. +#define ACCESSCTRL_CORESIGHT_PERIPH_SP_RESET _u(0x1) +#define ACCESSCTRL_CORESIGHT_PERIPH_SP_BITS _u(0x00000008) +#define ACCESSCTRL_CORESIGHT_PERIPH_SP_MSB _u(3) +#define ACCESSCTRL_CORESIGHT_PERIPH_SP_LSB _u(3) +#define ACCESSCTRL_CORESIGHT_PERIPH_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_SU +// Description : If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from +// a Secure, Unprivileged context. +#define ACCESSCTRL_CORESIGHT_PERIPH_SU_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_PERIPH_SU_BITS _u(0x00000004) +#define ACCESSCTRL_CORESIGHT_PERIPH_SU_MSB _u(2) +#define ACCESSCTRL_CORESIGHT_PERIPH_SU_LSB _u(2) +#define ACCESSCTRL_CORESIGHT_PERIPH_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_NSP +// Description : If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, +// Privileged context. +#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_MSB _u(1) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_LSB _u(1) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CORESIGHT_PERIPH_NSU +// Description : If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed +// from a Non-secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_RESET _u(0x0) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_MSB _u(0) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_LSB _u(0) +#define ACCESSCTRL_CORESIGHT_PERIPH_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SYSINFO +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SYSINFO, and at what security/privilege levels they can do so. +// +// Defaults to fully open access. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SYSINFO_OFFSET _u(0x00000060) +#define ACCESSCTRL_SYSINFO_BITS _u(0x000000ff) +#define ACCESSCTRL_SYSINFO_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_DBG +// Description : If 1, SYSINFO can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SYSINFO_DBG_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SYSINFO_DBG_MSB _u(7) +#define ACCESSCTRL_SYSINFO_DBG_LSB _u(7) +#define ACCESSCTRL_SYSINFO_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_DMA +// Description : If 1, SYSINFO can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SYSINFO_DMA_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SYSINFO_DMA_MSB _u(6) +#define ACCESSCTRL_SYSINFO_DMA_LSB _u(6) +#define ACCESSCTRL_SYSINFO_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_CORE1 +// Description : If 1, SYSINFO can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SYSINFO_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SYSINFO_CORE1_MSB _u(5) +#define ACCESSCTRL_SYSINFO_CORE1_LSB _u(5) +#define ACCESSCTRL_SYSINFO_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_CORE0 +// Description : If 1, SYSINFO can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SYSINFO_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SYSINFO_CORE0_MSB _u(4) +#define ACCESSCTRL_SYSINFO_CORE0_LSB _u(4) +#define ACCESSCTRL_SYSINFO_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_SP +// Description : If 1, SYSINFO can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_SYSINFO_SP_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SYSINFO_SP_MSB _u(3) +#define ACCESSCTRL_SYSINFO_SP_LSB _u(3) +#define ACCESSCTRL_SYSINFO_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_SU +// Description : If 1, and SP is also set, SYSINFO can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_SYSINFO_SU_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SYSINFO_SU_MSB _u(2) +#define ACCESSCTRL_SYSINFO_SU_LSB _u(2) +#define ACCESSCTRL_SYSINFO_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_NSP +// Description : If 1, SYSINFO can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SYSINFO_NSP_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SYSINFO_NSP_MSB _u(1) +#define ACCESSCTRL_SYSINFO_NSP_LSB _u(1) +#define ACCESSCTRL_SYSINFO_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSINFO_NSU +// Description : If 1, and NSP is also set, SYSINFO can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SYSINFO_NSU_RESET _u(0x1) +#define ACCESSCTRL_SYSINFO_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SYSINFO_NSU_MSB _u(0) +#define ACCESSCTRL_SYSINFO_NSU_LSB _u(0) +#define ACCESSCTRL_SYSINFO_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_RESETS +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// RESETS, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_RESETS_OFFSET _u(0x00000064) +#define ACCESSCTRL_RESETS_BITS _u(0x000000ff) +#define ACCESSCTRL_RESETS_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_DBG +// Description : If 1, RESETS can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_RESETS_DBG_RESET _u(0x1) +#define ACCESSCTRL_RESETS_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_RESETS_DBG_MSB _u(7) +#define ACCESSCTRL_RESETS_DBG_LSB _u(7) +#define ACCESSCTRL_RESETS_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_DMA +// Description : If 1, RESETS can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_RESETS_DMA_RESET _u(0x1) +#define ACCESSCTRL_RESETS_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_RESETS_DMA_MSB _u(6) +#define ACCESSCTRL_RESETS_DMA_LSB _u(6) +#define ACCESSCTRL_RESETS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_CORE1 +// Description : If 1, RESETS can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_RESETS_CORE1_RESET _u(0x1) +#define ACCESSCTRL_RESETS_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_RESETS_CORE1_MSB _u(5) +#define ACCESSCTRL_RESETS_CORE1_LSB _u(5) +#define ACCESSCTRL_RESETS_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_CORE0 +// Description : If 1, RESETS can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_RESETS_CORE0_RESET _u(0x1) +#define ACCESSCTRL_RESETS_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_RESETS_CORE0_MSB _u(4) +#define ACCESSCTRL_RESETS_CORE0_LSB _u(4) +#define ACCESSCTRL_RESETS_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_SP +// Description : If 1, RESETS can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_RESETS_SP_RESET _u(0x1) +#define ACCESSCTRL_RESETS_SP_BITS _u(0x00000008) +#define ACCESSCTRL_RESETS_SP_MSB _u(3) +#define ACCESSCTRL_RESETS_SP_LSB _u(3) +#define ACCESSCTRL_RESETS_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_SU +// Description : If 1, and SP is also set, RESETS can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_RESETS_SU_RESET _u(0x1) +#define ACCESSCTRL_RESETS_SU_BITS _u(0x00000004) +#define ACCESSCTRL_RESETS_SU_MSB _u(2) +#define ACCESSCTRL_RESETS_SU_LSB _u(2) +#define ACCESSCTRL_RESETS_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_NSP +// Description : If 1, RESETS can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_RESETS_NSP_RESET _u(0x0) +#define ACCESSCTRL_RESETS_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_RESETS_NSP_MSB _u(1) +#define ACCESSCTRL_RESETS_NSP_LSB _u(1) +#define ACCESSCTRL_RESETS_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RESETS_NSU +// Description : If 1, and NSP is also set, RESETS can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_RESETS_NSU_RESET _u(0x0) +#define ACCESSCTRL_RESETS_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_RESETS_NSU_MSB _u(0) +#define ACCESSCTRL_RESETS_NSU_LSB _u(0) +#define ACCESSCTRL_RESETS_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_IO_BANK0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// IO_BANK0, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_IO_BANK0_OFFSET _u(0x00000068) +#define ACCESSCTRL_IO_BANK0_BITS _u(0x000000ff) +#define ACCESSCTRL_IO_BANK0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_DBG +// Description : If 1, IO_BANK0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_IO_BANK0_DBG_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_IO_BANK0_DBG_MSB _u(7) +#define ACCESSCTRL_IO_BANK0_DBG_LSB _u(7) +#define ACCESSCTRL_IO_BANK0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_DMA +// Description : If 1, IO_BANK0 can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_IO_BANK0_DMA_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_IO_BANK0_DMA_MSB _u(6) +#define ACCESSCTRL_IO_BANK0_DMA_LSB _u(6) +#define ACCESSCTRL_IO_BANK0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_CORE1 +// Description : If 1, IO_BANK0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_IO_BANK0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_IO_BANK0_CORE1_MSB _u(5) +#define ACCESSCTRL_IO_BANK0_CORE1_LSB _u(5) +#define ACCESSCTRL_IO_BANK0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_CORE0 +// Description : If 1, IO_BANK0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_IO_BANK0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_IO_BANK0_CORE0_MSB _u(4) +#define ACCESSCTRL_IO_BANK0_CORE0_LSB _u(4) +#define ACCESSCTRL_IO_BANK0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_SP +// Description : If 1, IO_BANK0 can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_IO_BANK0_SP_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_IO_BANK0_SP_MSB _u(3) +#define ACCESSCTRL_IO_BANK0_SP_LSB _u(3) +#define ACCESSCTRL_IO_BANK0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_SU +// Description : If 1, and SP is also set, IO_BANK0 can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_IO_BANK0_SU_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_IO_BANK0_SU_MSB _u(2) +#define ACCESSCTRL_IO_BANK0_SU_LSB _u(2) +#define ACCESSCTRL_IO_BANK0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_NSP +// Description : If 1, IO_BANK0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_IO_BANK0_NSP_RESET _u(0x0) +#define ACCESSCTRL_IO_BANK0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_IO_BANK0_NSP_MSB _u(1) +#define ACCESSCTRL_IO_BANK0_NSP_LSB _u(1) +#define ACCESSCTRL_IO_BANK0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK0_NSU +// Description : If 1, and NSP is also set, IO_BANK0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_IO_BANK0_NSU_RESET _u(0x0) +#define ACCESSCTRL_IO_BANK0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_IO_BANK0_NSU_MSB _u(0) +#define ACCESSCTRL_IO_BANK0_NSU_LSB _u(0) +#define ACCESSCTRL_IO_BANK0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_IO_BANK1 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// IO_BANK1, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_IO_BANK1_OFFSET _u(0x0000006c) +#define ACCESSCTRL_IO_BANK1_BITS _u(0x000000ff) +#define ACCESSCTRL_IO_BANK1_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_DBG +// Description : If 1, IO_BANK1 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_IO_BANK1_DBG_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK1_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_IO_BANK1_DBG_MSB _u(7) +#define ACCESSCTRL_IO_BANK1_DBG_LSB _u(7) +#define ACCESSCTRL_IO_BANK1_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_DMA +// Description : If 1, IO_BANK1 can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_IO_BANK1_DMA_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK1_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_IO_BANK1_DMA_MSB _u(6) +#define ACCESSCTRL_IO_BANK1_DMA_LSB _u(6) +#define ACCESSCTRL_IO_BANK1_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_CORE1 +// Description : If 1, IO_BANK1 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_IO_BANK1_CORE1_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK1_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_IO_BANK1_CORE1_MSB _u(5) +#define ACCESSCTRL_IO_BANK1_CORE1_LSB _u(5) +#define ACCESSCTRL_IO_BANK1_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_CORE0 +// Description : If 1, IO_BANK1 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_IO_BANK1_CORE0_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK1_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_IO_BANK1_CORE0_MSB _u(4) +#define ACCESSCTRL_IO_BANK1_CORE0_LSB _u(4) +#define ACCESSCTRL_IO_BANK1_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_SP +// Description : If 1, IO_BANK1 can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_IO_BANK1_SP_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK1_SP_BITS _u(0x00000008) +#define ACCESSCTRL_IO_BANK1_SP_MSB _u(3) +#define ACCESSCTRL_IO_BANK1_SP_LSB _u(3) +#define ACCESSCTRL_IO_BANK1_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_SU +// Description : If 1, and SP is also set, IO_BANK1 can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_IO_BANK1_SU_RESET _u(0x1) +#define ACCESSCTRL_IO_BANK1_SU_BITS _u(0x00000004) +#define ACCESSCTRL_IO_BANK1_SU_MSB _u(2) +#define ACCESSCTRL_IO_BANK1_SU_LSB _u(2) +#define ACCESSCTRL_IO_BANK1_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_NSP +// Description : If 1, IO_BANK1 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_IO_BANK1_NSP_RESET _u(0x0) +#define ACCESSCTRL_IO_BANK1_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_IO_BANK1_NSP_MSB _u(1) +#define ACCESSCTRL_IO_BANK1_NSP_LSB _u(1) +#define ACCESSCTRL_IO_BANK1_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_IO_BANK1_NSU +// Description : If 1, and NSP is also set, IO_BANK1 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_IO_BANK1_NSU_RESET _u(0x0) +#define ACCESSCTRL_IO_BANK1_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_IO_BANK1_NSU_MSB _u(0) +#define ACCESSCTRL_IO_BANK1_NSU_LSB _u(0) +#define ACCESSCTRL_IO_BANK1_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PADS_BANK0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PADS_BANK0, and at what security/privilege levels they can do +// so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PADS_BANK0_OFFSET _u(0x00000070) +#define ACCESSCTRL_PADS_BANK0_BITS _u(0x000000ff) +#define ACCESSCTRL_PADS_BANK0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_DBG +// Description : If 1, PADS_BANK0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_BANK0_DBG_RESET _u(0x1) +#define ACCESSCTRL_PADS_BANK0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PADS_BANK0_DBG_MSB _u(7) +#define ACCESSCTRL_PADS_BANK0_DBG_LSB _u(7) +#define ACCESSCTRL_PADS_BANK0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_DMA +// Description : If 1, PADS_BANK0 can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_BANK0_DMA_RESET _u(0x1) +#define ACCESSCTRL_PADS_BANK0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PADS_BANK0_DMA_MSB _u(6) +#define ACCESSCTRL_PADS_BANK0_DMA_LSB _u(6) +#define ACCESSCTRL_PADS_BANK0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_CORE1 +// Description : If 1, PADS_BANK0 can be accessed by core 1, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_BANK0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PADS_BANK0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PADS_BANK0_CORE1_MSB _u(5) +#define ACCESSCTRL_PADS_BANK0_CORE1_LSB _u(5) +#define ACCESSCTRL_PADS_BANK0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_CORE0 +// Description : If 1, PADS_BANK0 can be accessed by core 0, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_BANK0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PADS_BANK0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PADS_BANK0_CORE0_MSB _u(4) +#define ACCESSCTRL_PADS_BANK0_CORE0_LSB _u(4) +#define ACCESSCTRL_PADS_BANK0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_SP +// Description : If 1, PADS_BANK0 can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_PADS_BANK0_SP_RESET _u(0x1) +#define ACCESSCTRL_PADS_BANK0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PADS_BANK0_SP_MSB _u(3) +#define ACCESSCTRL_PADS_BANK0_SP_LSB _u(3) +#define ACCESSCTRL_PADS_BANK0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_SU +// Description : If 1, and SP is also set, PADS_BANK0 can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_PADS_BANK0_SU_RESET _u(0x1) +#define ACCESSCTRL_PADS_BANK0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PADS_BANK0_SU_MSB _u(2) +#define ACCESSCTRL_PADS_BANK0_SU_LSB _u(2) +#define ACCESSCTRL_PADS_BANK0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_NSP +// Description : If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PADS_BANK0_NSP_RESET _u(0x0) +#define ACCESSCTRL_PADS_BANK0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PADS_BANK0_NSP_MSB _u(1) +#define ACCESSCTRL_PADS_BANK0_NSP_LSB _u(1) +#define ACCESSCTRL_PADS_BANK0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_BANK0_NSU +// Description : If 1, and NSP is also set, PADS_BANK0 can be accessed from a +// Non-secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PADS_BANK0_NSU_RESET _u(0x0) +#define ACCESSCTRL_PADS_BANK0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PADS_BANK0_NSU_MSB _u(0) +#define ACCESSCTRL_PADS_BANK0_NSU_LSB _u(0) +#define ACCESSCTRL_PADS_BANK0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PADS_QSPI +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PADS_QSPI, and at what security/privilege levels they can do +// so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PADS_QSPI_OFFSET _u(0x00000074) +#define ACCESSCTRL_PADS_QSPI_BITS _u(0x000000ff) +#define ACCESSCTRL_PADS_QSPI_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_DBG +// Description : If 1, PADS_QSPI can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_QSPI_DBG_RESET _u(0x1) +#define ACCESSCTRL_PADS_QSPI_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PADS_QSPI_DBG_MSB _u(7) +#define ACCESSCTRL_PADS_QSPI_DBG_LSB _u(7) +#define ACCESSCTRL_PADS_QSPI_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_DMA +// Description : If 1, PADS_QSPI can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_QSPI_DMA_RESET _u(0x1) +#define ACCESSCTRL_PADS_QSPI_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PADS_QSPI_DMA_MSB _u(6) +#define ACCESSCTRL_PADS_QSPI_DMA_LSB _u(6) +#define ACCESSCTRL_PADS_QSPI_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_CORE1 +// Description : If 1, PADS_QSPI can be accessed by core 1, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_QSPI_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PADS_QSPI_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PADS_QSPI_CORE1_MSB _u(5) +#define ACCESSCTRL_PADS_QSPI_CORE1_LSB _u(5) +#define ACCESSCTRL_PADS_QSPI_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_CORE0 +// Description : If 1, PADS_QSPI can be accessed by core 0, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PADS_QSPI_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PADS_QSPI_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PADS_QSPI_CORE0_MSB _u(4) +#define ACCESSCTRL_PADS_QSPI_CORE0_LSB _u(4) +#define ACCESSCTRL_PADS_QSPI_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_SP +// Description : If 1, PADS_QSPI can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_PADS_QSPI_SP_RESET _u(0x1) +#define ACCESSCTRL_PADS_QSPI_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PADS_QSPI_SP_MSB _u(3) +#define ACCESSCTRL_PADS_QSPI_SP_LSB _u(3) +#define ACCESSCTRL_PADS_QSPI_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_SU +// Description : If 1, and SP is also set, PADS_QSPI can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_PADS_QSPI_SU_RESET _u(0x1) +#define ACCESSCTRL_PADS_QSPI_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PADS_QSPI_SU_MSB _u(2) +#define ACCESSCTRL_PADS_QSPI_SU_LSB _u(2) +#define ACCESSCTRL_PADS_QSPI_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_NSP +// Description : If 1, PADS_QSPI can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PADS_QSPI_NSP_RESET _u(0x0) +#define ACCESSCTRL_PADS_QSPI_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PADS_QSPI_NSP_MSB _u(1) +#define ACCESSCTRL_PADS_QSPI_NSP_LSB _u(1) +#define ACCESSCTRL_PADS_QSPI_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PADS_QSPI_NSU +// Description : If 1, and NSP is also set, PADS_QSPI can be accessed from a +// Non-secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PADS_QSPI_NSU_RESET _u(0x0) +#define ACCESSCTRL_PADS_QSPI_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PADS_QSPI_NSU_MSB _u(0) +#define ACCESSCTRL_PADS_QSPI_NSU_LSB _u(0) +#define ACCESSCTRL_PADS_QSPI_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_BUSCTRL +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// BUSCTRL, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_BUSCTRL_OFFSET _u(0x00000078) +#define ACCESSCTRL_BUSCTRL_BITS _u(0x000000ff) +#define ACCESSCTRL_BUSCTRL_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_DBG +// Description : If 1, BUSCTRL can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_BUSCTRL_DBG_RESET _u(0x1) +#define ACCESSCTRL_BUSCTRL_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_BUSCTRL_DBG_MSB _u(7) +#define ACCESSCTRL_BUSCTRL_DBG_LSB _u(7) +#define ACCESSCTRL_BUSCTRL_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_DMA +// Description : If 1, BUSCTRL can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_BUSCTRL_DMA_RESET _u(0x1) +#define ACCESSCTRL_BUSCTRL_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_BUSCTRL_DMA_MSB _u(6) +#define ACCESSCTRL_BUSCTRL_DMA_LSB _u(6) +#define ACCESSCTRL_BUSCTRL_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_CORE1 +// Description : If 1, BUSCTRL can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_BUSCTRL_CORE1_RESET _u(0x1) +#define ACCESSCTRL_BUSCTRL_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_BUSCTRL_CORE1_MSB _u(5) +#define ACCESSCTRL_BUSCTRL_CORE1_LSB _u(5) +#define ACCESSCTRL_BUSCTRL_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_CORE0 +// Description : If 1, BUSCTRL can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_BUSCTRL_CORE0_RESET _u(0x1) +#define ACCESSCTRL_BUSCTRL_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_BUSCTRL_CORE0_MSB _u(4) +#define ACCESSCTRL_BUSCTRL_CORE0_LSB _u(4) +#define ACCESSCTRL_BUSCTRL_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_SP +// Description : If 1, BUSCTRL can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_BUSCTRL_SP_RESET _u(0x1) +#define ACCESSCTRL_BUSCTRL_SP_BITS _u(0x00000008) +#define ACCESSCTRL_BUSCTRL_SP_MSB _u(3) +#define ACCESSCTRL_BUSCTRL_SP_LSB _u(3) +#define ACCESSCTRL_BUSCTRL_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_SU +// Description : If 1, and SP is also set, BUSCTRL can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_BUSCTRL_SU_RESET _u(0x1) +#define ACCESSCTRL_BUSCTRL_SU_BITS _u(0x00000004) +#define ACCESSCTRL_BUSCTRL_SU_MSB _u(2) +#define ACCESSCTRL_BUSCTRL_SU_LSB _u(2) +#define ACCESSCTRL_BUSCTRL_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_NSP +// Description : If 1, BUSCTRL can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_BUSCTRL_NSP_RESET _u(0x0) +#define ACCESSCTRL_BUSCTRL_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_BUSCTRL_NSP_MSB _u(1) +#define ACCESSCTRL_BUSCTRL_NSP_LSB _u(1) +#define ACCESSCTRL_BUSCTRL_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_BUSCTRL_NSU +// Description : If 1, and NSP is also set, BUSCTRL can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_BUSCTRL_NSU_RESET _u(0x0) +#define ACCESSCTRL_BUSCTRL_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_BUSCTRL_NSU_MSB _u(0) +#define ACCESSCTRL_BUSCTRL_NSU_LSB _u(0) +#define ACCESSCTRL_BUSCTRL_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_ADC0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// ADC0, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_ADC0_OFFSET _u(0x0000007c) +#define ACCESSCTRL_ADC0_BITS _u(0x000000ff) +#define ACCESSCTRL_ADC0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_DBG +// Description : If 1, ADC0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_ADC0_DBG_RESET _u(0x1) +#define ACCESSCTRL_ADC0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_ADC0_DBG_MSB _u(7) +#define ACCESSCTRL_ADC0_DBG_LSB _u(7) +#define ACCESSCTRL_ADC0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_DMA +// Description : If 1, ADC0 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ADC0_DMA_RESET _u(0x1) +#define ACCESSCTRL_ADC0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_ADC0_DMA_MSB _u(6) +#define ACCESSCTRL_ADC0_DMA_LSB _u(6) +#define ACCESSCTRL_ADC0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_CORE1 +// Description : If 1, ADC0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ADC0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_ADC0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_ADC0_CORE1_MSB _u(5) +#define ACCESSCTRL_ADC0_CORE1_LSB _u(5) +#define ACCESSCTRL_ADC0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_CORE0 +// Description : If 1, ADC0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ADC0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_ADC0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_ADC0_CORE0_MSB _u(4) +#define ACCESSCTRL_ADC0_CORE0_LSB _u(4) +#define ACCESSCTRL_ADC0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_SP +// Description : If 1, ADC0 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_ADC0_SP_RESET _u(0x1) +#define ACCESSCTRL_ADC0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_ADC0_SP_MSB _u(3) +#define ACCESSCTRL_ADC0_SP_LSB _u(3) +#define ACCESSCTRL_ADC0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_SU +// Description : If 1, and SP is also set, ADC0 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_ADC0_SU_RESET _u(0x1) +#define ACCESSCTRL_ADC0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_ADC0_SU_MSB _u(2) +#define ACCESSCTRL_ADC0_SU_LSB _u(2) +#define ACCESSCTRL_ADC0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_NSP +// Description : If 1, ADC0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_ADC0_NSP_RESET _u(0x0) +#define ACCESSCTRL_ADC0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_ADC0_NSP_MSB _u(1) +#define ACCESSCTRL_ADC0_NSP_LSB _u(1) +#define ACCESSCTRL_ADC0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ADC0_NSU +// Description : If 1, and NSP is also set, ADC0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_ADC0_NSU_RESET _u(0x0) +#define ACCESSCTRL_ADC0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_ADC0_NSU_MSB _u(0) +#define ACCESSCTRL_ADC0_NSU_LSB _u(0) +#define ACCESSCTRL_ADC0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_HSTX +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// HSTX, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_HSTX_OFFSET _u(0x00000080) +#define ACCESSCTRL_HSTX_BITS _u(0x000000ff) +#define ACCESSCTRL_HSTX_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_DBG +// Description : If 1, HSTX can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_HSTX_DBG_RESET _u(0x1) +#define ACCESSCTRL_HSTX_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_HSTX_DBG_MSB _u(7) +#define ACCESSCTRL_HSTX_DBG_LSB _u(7) +#define ACCESSCTRL_HSTX_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_DMA +// Description : If 1, HSTX can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_HSTX_DMA_RESET _u(0x1) +#define ACCESSCTRL_HSTX_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_HSTX_DMA_MSB _u(6) +#define ACCESSCTRL_HSTX_DMA_LSB _u(6) +#define ACCESSCTRL_HSTX_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_CORE1 +// Description : If 1, HSTX can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_HSTX_CORE1_RESET _u(0x1) +#define ACCESSCTRL_HSTX_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_HSTX_CORE1_MSB _u(5) +#define ACCESSCTRL_HSTX_CORE1_LSB _u(5) +#define ACCESSCTRL_HSTX_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_CORE0 +// Description : If 1, HSTX can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_HSTX_CORE0_RESET _u(0x1) +#define ACCESSCTRL_HSTX_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_HSTX_CORE0_MSB _u(4) +#define ACCESSCTRL_HSTX_CORE0_LSB _u(4) +#define ACCESSCTRL_HSTX_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_SP +// Description : If 1, HSTX can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_HSTX_SP_RESET _u(0x1) +#define ACCESSCTRL_HSTX_SP_BITS _u(0x00000008) +#define ACCESSCTRL_HSTX_SP_MSB _u(3) +#define ACCESSCTRL_HSTX_SP_LSB _u(3) +#define ACCESSCTRL_HSTX_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_SU +// Description : If 1, and SP is also set, HSTX can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_HSTX_SU_RESET _u(0x1) +#define ACCESSCTRL_HSTX_SU_BITS _u(0x00000004) +#define ACCESSCTRL_HSTX_SU_MSB _u(2) +#define ACCESSCTRL_HSTX_SU_LSB _u(2) +#define ACCESSCTRL_HSTX_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_NSP +// Description : If 1, HSTX can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_HSTX_NSP_RESET _u(0x0) +#define ACCESSCTRL_HSTX_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_HSTX_NSP_MSB _u(1) +#define ACCESSCTRL_HSTX_NSP_LSB _u(1) +#define ACCESSCTRL_HSTX_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_HSTX_NSU +// Description : If 1, and NSP is also set, HSTX can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_HSTX_NSU_RESET _u(0x0) +#define ACCESSCTRL_HSTX_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_HSTX_NSU_MSB _u(0) +#define ACCESSCTRL_HSTX_NSU_LSB _u(0) +#define ACCESSCTRL_HSTX_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_I2C0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// I2C0, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_I2C0_OFFSET _u(0x00000084) +#define ACCESSCTRL_I2C0_BITS _u(0x000000ff) +#define ACCESSCTRL_I2C0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_DBG +// Description : If 1, I2C0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_I2C0_DBG_RESET _u(0x1) +#define ACCESSCTRL_I2C0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_I2C0_DBG_MSB _u(7) +#define ACCESSCTRL_I2C0_DBG_LSB _u(7) +#define ACCESSCTRL_I2C0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_DMA +// Description : If 1, I2C0 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_I2C0_DMA_RESET _u(0x1) +#define ACCESSCTRL_I2C0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_I2C0_DMA_MSB _u(6) +#define ACCESSCTRL_I2C0_DMA_LSB _u(6) +#define ACCESSCTRL_I2C0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_CORE1 +// Description : If 1, I2C0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_I2C0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_I2C0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_I2C0_CORE1_MSB _u(5) +#define ACCESSCTRL_I2C0_CORE1_LSB _u(5) +#define ACCESSCTRL_I2C0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_CORE0 +// Description : If 1, I2C0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_I2C0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_I2C0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_I2C0_CORE0_MSB _u(4) +#define ACCESSCTRL_I2C0_CORE0_LSB _u(4) +#define ACCESSCTRL_I2C0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_SP +// Description : If 1, I2C0 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_I2C0_SP_RESET _u(0x1) +#define ACCESSCTRL_I2C0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_I2C0_SP_MSB _u(3) +#define ACCESSCTRL_I2C0_SP_LSB _u(3) +#define ACCESSCTRL_I2C0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_SU +// Description : If 1, and SP is also set, I2C0 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_I2C0_SU_RESET _u(0x1) +#define ACCESSCTRL_I2C0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_I2C0_SU_MSB _u(2) +#define ACCESSCTRL_I2C0_SU_LSB _u(2) +#define ACCESSCTRL_I2C0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_NSP +// Description : If 1, I2C0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_I2C0_NSP_RESET _u(0x0) +#define ACCESSCTRL_I2C0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_I2C0_NSP_MSB _u(1) +#define ACCESSCTRL_I2C0_NSP_LSB _u(1) +#define ACCESSCTRL_I2C0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C0_NSU +// Description : If 1, and NSP is also set, I2C0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_I2C0_NSU_RESET _u(0x0) +#define ACCESSCTRL_I2C0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_I2C0_NSU_MSB _u(0) +#define ACCESSCTRL_I2C0_NSU_LSB _u(0) +#define ACCESSCTRL_I2C0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_I2C1 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// I2C1, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_I2C1_OFFSET _u(0x00000088) +#define ACCESSCTRL_I2C1_BITS _u(0x000000ff) +#define ACCESSCTRL_I2C1_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_DBG +// Description : If 1, I2C1 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_I2C1_DBG_RESET _u(0x1) +#define ACCESSCTRL_I2C1_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_I2C1_DBG_MSB _u(7) +#define ACCESSCTRL_I2C1_DBG_LSB _u(7) +#define ACCESSCTRL_I2C1_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_DMA +// Description : If 1, I2C1 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_I2C1_DMA_RESET _u(0x1) +#define ACCESSCTRL_I2C1_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_I2C1_DMA_MSB _u(6) +#define ACCESSCTRL_I2C1_DMA_LSB _u(6) +#define ACCESSCTRL_I2C1_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_CORE1 +// Description : If 1, I2C1 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_I2C1_CORE1_RESET _u(0x1) +#define ACCESSCTRL_I2C1_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_I2C1_CORE1_MSB _u(5) +#define ACCESSCTRL_I2C1_CORE1_LSB _u(5) +#define ACCESSCTRL_I2C1_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_CORE0 +// Description : If 1, I2C1 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_I2C1_CORE0_RESET _u(0x1) +#define ACCESSCTRL_I2C1_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_I2C1_CORE0_MSB _u(4) +#define ACCESSCTRL_I2C1_CORE0_LSB _u(4) +#define ACCESSCTRL_I2C1_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_SP +// Description : If 1, I2C1 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_I2C1_SP_RESET _u(0x1) +#define ACCESSCTRL_I2C1_SP_BITS _u(0x00000008) +#define ACCESSCTRL_I2C1_SP_MSB _u(3) +#define ACCESSCTRL_I2C1_SP_LSB _u(3) +#define ACCESSCTRL_I2C1_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_SU +// Description : If 1, and SP is also set, I2C1 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_I2C1_SU_RESET _u(0x1) +#define ACCESSCTRL_I2C1_SU_BITS _u(0x00000004) +#define ACCESSCTRL_I2C1_SU_MSB _u(2) +#define ACCESSCTRL_I2C1_SU_LSB _u(2) +#define ACCESSCTRL_I2C1_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_NSP +// Description : If 1, I2C1 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_I2C1_NSP_RESET _u(0x0) +#define ACCESSCTRL_I2C1_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_I2C1_NSP_MSB _u(1) +#define ACCESSCTRL_I2C1_NSP_LSB _u(1) +#define ACCESSCTRL_I2C1_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_I2C1_NSU +// Description : If 1, and NSP is also set, I2C1 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_I2C1_NSU_RESET _u(0x0) +#define ACCESSCTRL_I2C1_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_I2C1_NSU_MSB _u(0) +#define ACCESSCTRL_I2C1_NSU_LSB _u(0) +#define ACCESSCTRL_I2C1_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PWM +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PWM, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PWM_OFFSET _u(0x0000008c) +#define ACCESSCTRL_PWM_BITS _u(0x000000ff) +#define ACCESSCTRL_PWM_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_DBG +// Description : If 1, PWM can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PWM_DBG_RESET _u(0x1) +#define ACCESSCTRL_PWM_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PWM_DBG_MSB _u(7) +#define ACCESSCTRL_PWM_DBG_LSB _u(7) +#define ACCESSCTRL_PWM_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_DMA +// Description : If 1, PWM can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PWM_DMA_RESET _u(0x1) +#define ACCESSCTRL_PWM_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PWM_DMA_MSB _u(6) +#define ACCESSCTRL_PWM_DMA_LSB _u(6) +#define ACCESSCTRL_PWM_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_CORE1 +// Description : If 1, PWM can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PWM_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PWM_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PWM_CORE1_MSB _u(5) +#define ACCESSCTRL_PWM_CORE1_LSB _u(5) +#define ACCESSCTRL_PWM_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_CORE0 +// Description : If 1, PWM can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PWM_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PWM_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PWM_CORE0_MSB _u(4) +#define ACCESSCTRL_PWM_CORE0_LSB _u(4) +#define ACCESSCTRL_PWM_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_SP +// Description : If 1, PWM can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_PWM_SP_RESET _u(0x1) +#define ACCESSCTRL_PWM_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PWM_SP_MSB _u(3) +#define ACCESSCTRL_PWM_SP_LSB _u(3) +#define ACCESSCTRL_PWM_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_SU +// Description : If 1, and SP is also set, PWM can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_PWM_SU_RESET _u(0x1) +#define ACCESSCTRL_PWM_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PWM_SU_MSB _u(2) +#define ACCESSCTRL_PWM_SU_LSB _u(2) +#define ACCESSCTRL_PWM_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_NSP +// Description : If 1, PWM can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PWM_NSP_RESET _u(0x0) +#define ACCESSCTRL_PWM_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PWM_NSP_MSB _u(1) +#define ACCESSCTRL_PWM_NSP_LSB _u(1) +#define ACCESSCTRL_PWM_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PWM_NSU +// Description : If 1, and NSP is also set, PWM can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PWM_NSU_RESET _u(0x0) +#define ACCESSCTRL_PWM_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PWM_NSU_MSB _u(0) +#define ACCESSCTRL_PWM_NSU_LSB _u(0) +#define ACCESSCTRL_PWM_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SPI0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SPI0, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SPI0_OFFSET _u(0x00000090) +#define ACCESSCTRL_SPI0_BITS _u(0x000000ff) +#define ACCESSCTRL_SPI0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_DBG +// Description : If 1, SPI0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SPI0_DBG_RESET _u(0x1) +#define ACCESSCTRL_SPI0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SPI0_DBG_MSB _u(7) +#define ACCESSCTRL_SPI0_DBG_LSB _u(7) +#define ACCESSCTRL_SPI0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_DMA +// Description : If 1, SPI0 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SPI0_DMA_RESET _u(0x1) +#define ACCESSCTRL_SPI0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SPI0_DMA_MSB _u(6) +#define ACCESSCTRL_SPI0_DMA_LSB _u(6) +#define ACCESSCTRL_SPI0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_CORE1 +// Description : If 1, SPI0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SPI0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SPI0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SPI0_CORE1_MSB _u(5) +#define ACCESSCTRL_SPI0_CORE1_LSB _u(5) +#define ACCESSCTRL_SPI0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_CORE0 +// Description : If 1, SPI0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SPI0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SPI0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SPI0_CORE0_MSB _u(4) +#define ACCESSCTRL_SPI0_CORE0_LSB _u(4) +#define ACCESSCTRL_SPI0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_SP +// Description : If 1, SPI0 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SPI0_SP_RESET _u(0x1) +#define ACCESSCTRL_SPI0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SPI0_SP_MSB _u(3) +#define ACCESSCTRL_SPI0_SP_LSB _u(3) +#define ACCESSCTRL_SPI0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_SU +// Description : If 1, and SP is also set, SPI0 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SPI0_SU_RESET _u(0x1) +#define ACCESSCTRL_SPI0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SPI0_SU_MSB _u(2) +#define ACCESSCTRL_SPI0_SU_LSB _u(2) +#define ACCESSCTRL_SPI0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_NSP +// Description : If 1, SPI0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SPI0_NSP_RESET _u(0x0) +#define ACCESSCTRL_SPI0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SPI0_NSP_MSB _u(1) +#define ACCESSCTRL_SPI0_NSP_LSB _u(1) +#define ACCESSCTRL_SPI0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI0_NSU +// Description : If 1, and NSP is also set, SPI0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SPI0_NSU_RESET _u(0x0) +#define ACCESSCTRL_SPI0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SPI0_NSU_MSB _u(0) +#define ACCESSCTRL_SPI0_NSU_LSB _u(0) +#define ACCESSCTRL_SPI0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SPI1 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SPI1, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SPI1_OFFSET _u(0x00000094) +#define ACCESSCTRL_SPI1_BITS _u(0x000000ff) +#define ACCESSCTRL_SPI1_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_DBG +// Description : If 1, SPI1 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SPI1_DBG_RESET _u(0x1) +#define ACCESSCTRL_SPI1_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SPI1_DBG_MSB _u(7) +#define ACCESSCTRL_SPI1_DBG_LSB _u(7) +#define ACCESSCTRL_SPI1_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_DMA +// Description : If 1, SPI1 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SPI1_DMA_RESET _u(0x1) +#define ACCESSCTRL_SPI1_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SPI1_DMA_MSB _u(6) +#define ACCESSCTRL_SPI1_DMA_LSB _u(6) +#define ACCESSCTRL_SPI1_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_CORE1 +// Description : If 1, SPI1 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SPI1_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SPI1_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SPI1_CORE1_MSB _u(5) +#define ACCESSCTRL_SPI1_CORE1_LSB _u(5) +#define ACCESSCTRL_SPI1_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_CORE0 +// Description : If 1, SPI1 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SPI1_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SPI1_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SPI1_CORE0_MSB _u(4) +#define ACCESSCTRL_SPI1_CORE0_LSB _u(4) +#define ACCESSCTRL_SPI1_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_SP +// Description : If 1, SPI1 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SPI1_SP_RESET _u(0x1) +#define ACCESSCTRL_SPI1_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SPI1_SP_MSB _u(3) +#define ACCESSCTRL_SPI1_SP_LSB _u(3) +#define ACCESSCTRL_SPI1_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_SU +// Description : If 1, and SP is also set, SPI1 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SPI1_SU_RESET _u(0x1) +#define ACCESSCTRL_SPI1_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SPI1_SU_MSB _u(2) +#define ACCESSCTRL_SPI1_SU_LSB _u(2) +#define ACCESSCTRL_SPI1_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_NSP +// Description : If 1, SPI1 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SPI1_NSP_RESET _u(0x0) +#define ACCESSCTRL_SPI1_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SPI1_NSP_MSB _u(1) +#define ACCESSCTRL_SPI1_NSP_LSB _u(1) +#define ACCESSCTRL_SPI1_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SPI1_NSU +// Description : If 1, and NSP is also set, SPI1 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SPI1_NSU_RESET _u(0x0) +#define ACCESSCTRL_SPI1_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SPI1_NSU_MSB _u(0) +#define ACCESSCTRL_SPI1_NSU_LSB _u(0) +#define ACCESSCTRL_SPI1_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_TIMER0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// TIMER0, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_TIMER0_OFFSET _u(0x00000098) +#define ACCESSCTRL_TIMER0_BITS _u(0x000000ff) +#define ACCESSCTRL_TIMER0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_DBG +// Description : If 1, TIMER0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_TIMER0_DBG_RESET _u(0x1) +#define ACCESSCTRL_TIMER0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_TIMER0_DBG_MSB _u(7) +#define ACCESSCTRL_TIMER0_DBG_LSB _u(7) +#define ACCESSCTRL_TIMER0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_DMA +// Description : If 1, TIMER0 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TIMER0_DMA_RESET _u(0x1) +#define ACCESSCTRL_TIMER0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_TIMER0_DMA_MSB _u(6) +#define ACCESSCTRL_TIMER0_DMA_LSB _u(6) +#define ACCESSCTRL_TIMER0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_CORE1 +// Description : If 1, TIMER0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TIMER0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_TIMER0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_TIMER0_CORE1_MSB _u(5) +#define ACCESSCTRL_TIMER0_CORE1_LSB _u(5) +#define ACCESSCTRL_TIMER0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_CORE0 +// Description : If 1, TIMER0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TIMER0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_TIMER0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_TIMER0_CORE0_MSB _u(4) +#define ACCESSCTRL_TIMER0_CORE0_LSB _u(4) +#define ACCESSCTRL_TIMER0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_SP +// Description : If 1, TIMER0 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_TIMER0_SP_RESET _u(0x1) +#define ACCESSCTRL_TIMER0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_TIMER0_SP_MSB _u(3) +#define ACCESSCTRL_TIMER0_SP_LSB _u(3) +#define ACCESSCTRL_TIMER0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_SU +// Description : If 1, and SP is also set, TIMER0 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_TIMER0_SU_RESET _u(0x1) +#define ACCESSCTRL_TIMER0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_TIMER0_SU_MSB _u(2) +#define ACCESSCTRL_TIMER0_SU_LSB _u(2) +#define ACCESSCTRL_TIMER0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_NSP +// Description : If 1, TIMER0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_TIMER0_NSP_RESET _u(0x0) +#define ACCESSCTRL_TIMER0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_TIMER0_NSP_MSB _u(1) +#define ACCESSCTRL_TIMER0_NSP_LSB _u(1) +#define ACCESSCTRL_TIMER0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER0_NSU +// Description : If 1, and NSP is also set, TIMER0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_TIMER0_NSU_RESET _u(0x0) +#define ACCESSCTRL_TIMER0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_TIMER0_NSU_MSB _u(0) +#define ACCESSCTRL_TIMER0_NSU_LSB _u(0) +#define ACCESSCTRL_TIMER0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_TIMER1 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// TIMER1, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_TIMER1_OFFSET _u(0x0000009c) +#define ACCESSCTRL_TIMER1_BITS _u(0x000000ff) +#define ACCESSCTRL_TIMER1_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_DBG +// Description : If 1, TIMER1 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_TIMER1_DBG_RESET _u(0x1) +#define ACCESSCTRL_TIMER1_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_TIMER1_DBG_MSB _u(7) +#define ACCESSCTRL_TIMER1_DBG_LSB _u(7) +#define ACCESSCTRL_TIMER1_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_DMA +// Description : If 1, TIMER1 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TIMER1_DMA_RESET _u(0x1) +#define ACCESSCTRL_TIMER1_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_TIMER1_DMA_MSB _u(6) +#define ACCESSCTRL_TIMER1_DMA_LSB _u(6) +#define ACCESSCTRL_TIMER1_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_CORE1 +// Description : If 1, TIMER1 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TIMER1_CORE1_RESET _u(0x1) +#define ACCESSCTRL_TIMER1_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_TIMER1_CORE1_MSB _u(5) +#define ACCESSCTRL_TIMER1_CORE1_LSB _u(5) +#define ACCESSCTRL_TIMER1_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_CORE0 +// Description : If 1, TIMER1 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TIMER1_CORE0_RESET _u(0x1) +#define ACCESSCTRL_TIMER1_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_TIMER1_CORE0_MSB _u(4) +#define ACCESSCTRL_TIMER1_CORE0_LSB _u(4) +#define ACCESSCTRL_TIMER1_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_SP +// Description : If 1, TIMER1 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_TIMER1_SP_RESET _u(0x1) +#define ACCESSCTRL_TIMER1_SP_BITS _u(0x00000008) +#define ACCESSCTRL_TIMER1_SP_MSB _u(3) +#define ACCESSCTRL_TIMER1_SP_LSB _u(3) +#define ACCESSCTRL_TIMER1_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_SU +// Description : If 1, and SP is also set, TIMER1 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_TIMER1_SU_RESET _u(0x1) +#define ACCESSCTRL_TIMER1_SU_BITS _u(0x00000004) +#define ACCESSCTRL_TIMER1_SU_MSB _u(2) +#define ACCESSCTRL_TIMER1_SU_LSB _u(2) +#define ACCESSCTRL_TIMER1_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_NSP +// Description : If 1, TIMER1 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_TIMER1_NSP_RESET _u(0x0) +#define ACCESSCTRL_TIMER1_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_TIMER1_NSP_MSB _u(1) +#define ACCESSCTRL_TIMER1_NSP_LSB _u(1) +#define ACCESSCTRL_TIMER1_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TIMER1_NSU +// Description : If 1, and NSP is also set, TIMER1 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_TIMER1_NSU_RESET _u(0x0) +#define ACCESSCTRL_TIMER1_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_TIMER1_NSU_MSB _u(0) +#define ACCESSCTRL_TIMER1_NSU_LSB _u(0) +#define ACCESSCTRL_TIMER1_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_UART0 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// UART0, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_UART0_OFFSET _u(0x000000a0) +#define ACCESSCTRL_UART0_BITS _u(0x000000ff) +#define ACCESSCTRL_UART0_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_DBG +// Description : If 1, UART0 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_UART0_DBG_RESET _u(0x1) +#define ACCESSCTRL_UART0_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_UART0_DBG_MSB _u(7) +#define ACCESSCTRL_UART0_DBG_LSB _u(7) +#define ACCESSCTRL_UART0_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_DMA +// Description : If 1, UART0 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_UART0_DMA_RESET _u(0x1) +#define ACCESSCTRL_UART0_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_UART0_DMA_MSB _u(6) +#define ACCESSCTRL_UART0_DMA_LSB _u(6) +#define ACCESSCTRL_UART0_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_CORE1 +// Description : If 1, UART0 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_UART0_CORE1_RESET _u(0x1) +#define ACCESSCTRL_UART0_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_UART0_CORE1_MSB _u(5) +#define ACCESSCTRL_UART0_CORE1_LSB _u(5) +#define ACCESSCTRL_UART0_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_CORE0 +// Description : If 1, UART0 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_UART0_CORE0_RESET _u(0x1) +#define ACCESSCTRL_UART0_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_UART0_CORE0_MSB _u(4) +#define ACCESSCTRL_UART0_CORE0_LSB _u(4) +#define ACCESSCTRL_UART0_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_SP +// Description : If 1, UART0 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_UART0_SP_RESET _u(0x1) +#define ACCESSCTRL_UART0_SP_BITS _u(0x00000008) +#define ACCESSCTRL_UART0_SP_MSB _u(3) +#define ACCESSCTRL_UART0_SP_LSB _u(3) +#define ACCESSCTRL_UART0_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_SU +// Description : If 1, and SP is also set, UART0 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_UART0_SU_RESET _u(0x1) +#define ACCESSCTRL_UART0_SU_BITS _u(0x00000004) +#define ACCESSCTRL_UART0_SU_MSB _u(2) +#define ACCESSCTRL_UART0_SU_LSB _u(2) +#define ACCESSCTRL_UART0_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_NSP +// Description : If 1, UART0 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_UART0_NSP_RESET _u(0x0) +#define ACCESSCTRL_UART0_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_UART0_NSP_MSB _u(1) +#define ACCESSCTRL_UART0_NSP_LSB _u(1) +#define ACCESSCTRL_UART0_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART0_NSU +// Description : If 1, and NSP is also set, UART0 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_UART0_NSU_RESET _u(0x0) +#define ACCESSCTRL_UART0_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_UART0_NSU_MSB _u(0) +#define ACCESSCTRL_UART0_NSU_LSB _u(0) +#define ACCESSCTRL_UART0_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_UART1 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// UART1, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_UART1_OFFSET _u(0x000000a4) +#define ACCESSCTRL_UART1_BITS _u(0x000000ff) +#define ACCESSCTRL_UART1_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_DBG +// Description : If 1, UART1 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_UART1_DBG_RESET _u(0x1) +#define ACCESSCTRL_UART1_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_UART1_DBG_MSB _u(7) +#define ACCESSCTRL_UART1_DBG_LSB _u(7) +#define ACCESSCTRL_UART1_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_DMA +// Description : If 1, UART1 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_UART1_DMA_RESET _u(0x1) +#define ACCESSCTRL_UART1_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_UART1_DMA_MSB _u(6) +#define ACCESSCTRL_UART1_DMA_LSB _u(6) +#define ACCESSCTRL_UART1_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_CORE1 +// Description : If 1, UART1 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_UART1_CORE1_RESET _u(0x1) +#define ACCESSCTRL_UART1_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_UART1_CORE1_MSB _u(5) +#define ACCESSCTRL_UART1_CORE1_LSB _u(5) +#define ACCESSCTRL_UART1_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_CORE0 +// Description : If 1, UART1 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_UART1_CORE0_RESET _u(0x1) +#define ACCESSCTRL_UART1_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_UART1_CORE0_MSB _u(4) +#define ACCESSCTRL_UART1_CORE0_LSB _u(4) +#define ACCESSCTRL_UART1_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_SP +// Description : If 1, UART1 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_UART1_SP_RESET _u(0x1) +#define ACCESSCTRL_UART1_SP_BITS _u(0x00000008) +#define ACCESSCTRL_UART1_SP_MSB _u(3) +#define ACCESSCTRL_UART1_SP_LSB _u(3) +#define ACCESSCTRL_UART1_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_SU +// Description : If 1, and SP is also set, UART1 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_UART1_SU_RESET _u(0x1) +#define ACCESSCTRL_UART1_SU_BITS _u(0x00000004) +#define ACCESSCTRL_UART1_SU_MSB _u(2) +#define ACCESSCTRL_UART1_SU_LSB _u(2) +#define ACCESSCTRL_UART1_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_NSP +// Description : If 1, UART1 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_UART1_NSP_RESET _u(0x0) +#define ACCESSCTRL_UART1_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_UART1_NSP_MSB _u(1) +#define ACCESSCTRL_UART1_NSP_LSB _u(1) +#define ACCESSCTRL_UART1_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_UART1_NSU +// Description : If 1, and NSP is also set, UART1 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_UART1_NSU_RESET _u(0x0) +#define ACCESSCTRL_UART1_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_UART1_NSU_MSB _u(0) +#define ACCESSCTRL_UART1_NSU_LSB _u(0) +#define ACCESSCTRL_UART1_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_OTP +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// OTP, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_OTP_OFFSET _u(0x000000a8) +#define ACCESSCTRL_OTP_BITS _u(0x000000ff) +#define ACCESSCTRL_OTP_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_DBG +// Description : If 1, OTP can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_OTP_DBG_RESET _u(0x1) +#define ACCESSCTRL_OTP_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_OTP_DBG_MSB _u(7) +#define ACCESSCTRL_OTP_DBG_LSB _u(7) +#define ACCESSCTRL_OTP_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_DMA +// Description : If 1, OTP can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_OTP_DMA_RESET _u(0x1) +#define ACCESSCTRL_OTP_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_OTP_DMA_MSB _u(6) +#define ACCESSCTRL_OTP_DMA_LSB _u(6) +#define ACCESSCTRL_OTP_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_CORE1 +// Description : If 1, OTP can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_OTP_CORE1_RESET _u(0x1) +#define ACCESSCTRL_OTP_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_OTP_CORE1_MSB _u(5) +#define ACCESSCTRL_OTP_CORE1_LSB _u(5) +#define ACCESSCTRL_OTP_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_CORE0 +// Description : If 1, OTP can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_OTP_CORE0_RESET _u(0x1) +#define ACCESSCTRL_OTP_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_OTP_CORE0_MSB _u(4) +#define ACCESSCTRL_OTP_CORE0_LSB _u(4) +#define ACCESSCTRL_OTP_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_SP +// Description : If 1, OTP can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_OTP_SP_RESET _u(0x1) +#define ACCESSCTRL_OTP_SP_BITS _u(0x00000008) +#define ACCESSCTRL_OTP_SP_MSB _u(3) +#define ACCESSCTRL_OTP_SP_LSB _u(3) +#define ACCESSCTRL_OTP_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_SU +// Description : If 1, and SP is also set, OTP can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_OTP_SU_RESET _u(0x1) +#define ACCESSCTRL_OTP_SU_BITS _u(0x00000004) +#define ACCESSCTRL_OTP_SU_MSB _u(2) +#define ACCESSCTRL_OTP_SU_LSB _u(2) +#define ACCESSCTRL_OTP_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_NSP +// Description : If 1, OTP can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_OTP_NSP_RESET _u(0x0) +#define ACCESSCTRL_OTP_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_OTP_NSP_MSB _u(1) +#define ACCESSCTRL_OTP_NSP_LSB _u(1) +#define ACCESSCTRL_OTP_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_OTP_NSU +// Description : If 1, and NSP is also set, OTP can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_OTP_NSU_RESET _u(0x0) +#define ACCESSCTRL_OTP_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_OTP_NSU_MSB _u(0) +#define ACCESSCTRL_OTP_NSU_LSB _u(0) +#define ACCESSCTRL_OTP_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_TBMAN +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// TBMAN, and at what security/privilege levels they can do so. +// +// Defaults to Secure access from any master. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_TBMAN_OFFSET _u(0x000000ac) +#define ACCESSCTRL_TBMAN_BITS _u(0x000000ff) +#define ACCESSCTRL_TBMAN_RESET _u(0x000000fc) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_DBG +// Description : If 1, TBMAN can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_TBMAN_DBG_RESET _u(0x1) +#define ACCESSCTRL_TBMAN_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_TBMAN_DBG_MSB _u(7) +#define ACCESSCTRL_TBMAN_DBG_LSB _u(7) +#define ACCESSCTRL_TBMAN_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_DMA +// Description : If 1, TBMAN can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TBMAN_DMA_RESET _u(0x1) +#define ACCESSCTRL_TBMAN_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_TBMAN_DMA_MSB _u(6) +#define ACCESSCTRL_TBMAN_DMA_LSB _u(6) +#define ACCESSCTRL_TBMAN_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_CORE1 +// Description : If 1, TBMAN can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TBMAN_CORE1_RESET _u(0x1) +#define ACCESSCTRL_TBMAN_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_TBMAN_CORE1_MSB _u(5) +#define ACCESSCTRL_TBMAN_CORE1_LSB _u(5) +#define ACCESSCTRL_TBMAN_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_CORE0 +// Description : If 1, TBMAN can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TBMAN_CORE0_RESET _u(0x1) +#define ACCESSCTRL_TBMAN_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_TBMAN_CORE0_MSB _u(4) +#define ACCESSCTRL_TBMAN_CORE0_LSB _u(4) +#define ACCESSCTRL_TBMAN_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_SP +// Description : If 1, TBMAN can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_TBMAN_SP_RESET _u(0x1) +#define ACCESSCTRL_TBMAN_SP_BITS _u(0x00000008) +#define ACCESSCTRL_TBMAN_SP_MSB _u(3) +#define ACCESSCTRL_TBMAN_SP_LSB _u(3) +#define ACCESSCTRL_TBMAN_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_SU +// Description : If 1, and SP is also set, TBMAN can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_TBMAN_SU_RESET _u(0x1) +#define ACCESSCTRL_TBMAN_SU_BITS _u(0x00000004) +#define ACCESSCTRL_TBMAN_SU_MSB _u(2) +#define ACCESSCTRL_TBMAN_SU_LSB _u(2) +#define ACCESSCTRL_TBMAN_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_NSP +// Description : If 1, TBMAN can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_TBMAN_NSP_RESET _u(0x0) +#define ACCESSCTRL_TBMAN_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_TBMAN_NSP_MSB _u(1) +#define ACCESSCTRL_TBMAN_NSP_LSB _u(1) +#define ACCESSCTRL_TBMAN_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TBMAN_NSU +// Description : If 1, and NSP is also set, TBMAN can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_TBMAN_NSU_RESET _u(0x0) +#define ACCESSCTRL_TBMAN_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_TBMAN_NSU_MSB _u(0) +#define ACCESSCTRL_TBMAN_NSU_LSB _u(0) +#define ACCESSCTRL_TBMAN_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_POWMAN +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// POWMAN, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_POWMAN_OFFSET _u(0x000000b0) +#define ACCESSCTRL_POWMAN_BITS _u(0x000000ff) +#define ACCESSCTRL_POWMAN_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_DBG +// Description : If 1, POWMAN can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_POWMAN_DBG_RESET _u(0x1) +#define ACCESSCTRL_POWMAN_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_POWMAN_DBG_MSB _u(7) +#define ACCESSCTRL_POWMAN_DBG_LSB _u(7) +#define ACCESSCTRL_POWMAN_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_DMA +// Description : If 1, POWMAN can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_POWMAN_DMA_RESET _u(0x0) +#define ACCESSCTRL_POWMAN_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_POWMAN_DMA_MSB _u(6) +#define ACCESSCTRL_POWMAN_DMA_LSB _u(6) +#define ACCESSCTRL_POWMAN_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_CORE1 +// Description : If 1, POWMAN can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_POWMAN_CORE1_RESET _u(0x1) +#define ACCESSCTRL_POWMAN_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_POWMAN_CORE1_MSB _u(5) +#define ACCESSCTRL_POWMAN_CORE1_LSB _u(5) +#define ACCESSCTRL_POWMAN_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_CORE0 +// Description : If 1, POWMAN can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_POWMAN_CORE0_RESET _u(0x1) +#define ACCESSCTRL_POWMAN_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_POWMAN_CORE0_MSB _u(4) +#define ACCESSCTRL_POWMAN_CORE0_LSB _u(4) +#define ACCESSCTRL_POWMAN_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_SP +// Description : If 1, POWMAN can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_POWMAN_SP_RESET _u(0x1) +#define ACCESSCTRL_POWMAN_SP_BITS _u(0x00000008) +#define ACCESSCTRL_POWMAN_SP_MSB _u(3) +#define ACCESSCTRL_POWMAN_SP_LSB _u(3) +#define ACCESSCTRL_POWMAN_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_SU +// Description : If 1, and SP is also set, POWMAN can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_POWMAN_SU_RESET _u(0x0) +#define ACCESSCTRL_POWMAN_SU_BITS _u(0x00000004) +#define ACCESSCTRL_POWMAN_SU_MSB _u(2) +#define ACCESSCTRL_POWMAN_SU_LSB _u(2) +#define ACCESSCTRL_POWMAN_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_NSP +// Description : If 1, POWMAN can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_POWMAN_NSP_RESET _u(0x0) +#define ACCESSCTRL_POWMAN_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_POWMAN_NSP_MSB _u(1) +#define ACCESSCTRL_POWMAN_NSP_LSB _u(1) +#define ACCESSCTRL_POWMAN_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_POWMAN_NSU +// Description : If 1, and NSP is also set, POWMAN can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_POWMAN_NSU_RESET _u(0x0) +#define ACCESSCTRL_POWMAN_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_POWMAN_NSU_MSB _u(0) +#define ACCESSCTRL_POWMAN_NSU_LSB _u(0) +#define ACCESSCTRL_POWMAN_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_TRNG +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// TRNG, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_TRNG_OFFSET _u(0x000000b4) +#define ACCESSCTRL_TRNG_BITS _u(0x000000ff) +#define ACCESSCTRL_TRNG_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_DBG +// Description : If 1, TRNG can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_TRNG_DBG_RESET _u(0x1) +#define ACCESSCTRL_TRNG_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_TRNG_DBG_MSB _u(7) +#define ACCESSCTRL_TRNG_DBG_LSB _u(7) +#define ACCESSCTRL_TRNG_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_DMA +// Description : If 1, TRNG can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TRNG_DMA_RESET _u(0x0) +#define ACCESSCTRL_TRNG_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_TRNG_DMA_MSB _u(6) +#define ACCESSCTRL_TRNG_DMA_LSB _u(6) +#define ACCESSCTRL_TRNG_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_CORE1 +// Description : If 1, TRNG can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TRNG_CORE1_RESET _u(0x1) +#define ACCESSCTRL_TRNG_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_TRNG_CORE1_MSB _u(5) +#define ACCESSCTRL_TRNG_CORE1_LSB _u(5) +#define ACCESSCTRL_TRNG_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_CORE0 +// Description : If 1, TRNG can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TRNG_CORE0_RESET _u(0x1) +#define ACCESSCTRL_TRNG_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_TRNG_CORE0_MSB _u(4) +#define ACCESSCTRL_TRNG_CORE0_LSB _u(4) +#define ACCESSCTRL_TRNG_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_SP +// Description : If 1, TRNG can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_TRNG_SP_RESET _u(0x1) +#define ACCESSCTRL_TRNG_SP_BITS _u(0x00000008) +#define ACCESSCTRL_TRNG_SP_MSB _u(3) +#define ACCESSCTRL_TRNG_SP_LSB _u(3) +#define ACCESSCTRL_TRNG_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_SU +// Description : If 1, and SP is also set, TRNG can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_TRNG_SU_RESET _u(0x0) +#define ACCESSCTRL_TRNG_SU_BITS _u(0x00000004) +#define ACCESSCTRL_TRNG_SU_MSB _u(2) +#define ACCESSCTRL_TRNG_SU_LSB _u(2) +#define ACCESSCTRL_TRNG_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_NSP +// Description : If 1, TRNG can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_TRNG_NSP_RESET _u(0x0) +#define ACCESSCTRL_TRNG_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_TRNG_NSP_MSB _u(1) +#define ACCESSCTRL_TRNG_NSP_LSB _u(1) +#define ACCESSCTRL_TRNG_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TRNG_NSU +// Description : If 1, and NSP is also set, TRNG can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_TRNG_NSU_RESET _u(0x0) +#define ACCESSCTRL_TRNG_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_TRNG_NSU_MSB _u(0) +#define ACCESSCTRL_TRNG_NSU_LSB _u(0) +#define ACCESSCTRL_TRNG_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SHA256 +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SHA256, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SHA256_OFFSET _u(0x000000b8) +#define ACCESSCTRL_SHA256_BITS _u(0x000000ff) +#define ACCESSCTRL_SHA256_RESET _u(0x000000f8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_DBG +// Description : If 1, SHA256 can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SHA256_DBG_RESET _u(0x1) +#define ACCESSCTRL_SHA256_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SHA256_DBG_MSB _u(7) +#define ACCESSCTRL_SHA256_DBG_LSB _u(7) +#define ACCESSCTRL_SHA256_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_DMA +// Description : If 1, SHA256 can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SHA256_DMA_RESET _u(0x1) +#define ACCESSCTRL_SHA256_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SHA256_DMA_MSB _u(6) +#define ACCESSCTRL_SHA256_DMA_LSB _u(6) +#define ACCESSCTRL_SHA256_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_CORE1 +// Description : If 1, SHA256 can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SHA256_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SHA256_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SHA256_CORE1_MSB _u(5) +#define ACCESSCTRL_SHA256_CORE1_LSB _u(5) +#define ACCESSCTRL_SHA256_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_CORE0 +// Description : If 1, SHA256 can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SHA256_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SHA256_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SHA256_CORE0_MSB _u(4) +#define ACCESSCTRL_SHA256_CORE0_LSB _u(4) +#define ACCESSCTRL_SHA256_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_SP +// Description : If 1, SHA256 can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SHA256_SP_RESET _u(0x1) +#define ACCESSCTRL_SHA256_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SHA256_SP_MSB _u(3) +#define ACCESSCTRL_SHA256_SP_LSB _u(3) +#define ACCESSCTRL_SHA256_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_SU +// Description : If 1, and SP is also set, SHA256 can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SHA256_SU_RESET _u(0x0) +#define ACCESSCTRL_SHA256_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SHA256_SU_MSB _u(2) +#define ACCESSCTRL_SHA256_SU_LSB _u(2) +#define ACCESSCTRL_SHA256_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_NSP +// Description : If 1, SHA256 can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SHA256_NSP_RESET _u(0x0) +#define ACCESSCTRL_SHA256_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SHA256_NSP_MSB _u(1) +#define ACCESSCTRL_SHA256_NSP_LSB _u(1) +#define ACCESSCTRL_SHA256_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SHA256_NSU +// Description : If 1, and NSP is also set, SHA256 can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SHA256_NSU_RESET _u(0x0) +#define ACCESSCTRL_SHA256_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SHA256_NSU_MSB _u(0) +#define ACCESSCTRL_SHA256_NSU_LSB _u(0) +#define ACCESSCTRL_SHA256_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_SYSCFG +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// SYSCFG, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_SYSCFG_OFFSET _u(0x000000bc) +#define ACCESSCTRL_SYSCFG_BITS _u(0x000000ff) +#define ACCESSCTRL_SYSCFG_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_DBG +// Description : If 1, SYSCFG can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_SYSCFG_DBG_RESET _u(0x1) +#define ACCESSCTRL_SYSCFG_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_SYSCFG_DBG_MSB _u(7) +#define ACCESSCTRL_SYSCFG_DBG_LSB _u(7) +#define ACCESSCTRL_SYSCFG_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_DMA +// Description : If 1, SYSCFG can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SYSCFG_DMA_RESET _u(0x0) +#define ACCESSCTRL_SYSCFG_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_SYSCFG_DMA_MSB _u(6) +#define ACCESSCTRL_SYSCFG_DMA_LSB _u(6) +#define ACCESSCTRL_SYSCFG_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_CORE1 +// Description : If 1, SYSCFG can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SYSCFG_CORE1_RESET _u(0x1) +#define ACCESSCTRL_SYSCFG_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_SYSCFG_CORE1_MSB _u(5) +#define ACCESSCTRL_SYSCFG_CORE1_LSB _u(5) +#define ACCESSCTRL_SYSCFG_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_CORE0 +// Description : If 1, SYSCFG can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_SYSCFG_CORE0_RESET _u(0x1) +#define ACCESSCTRL_SYSCFG_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_SYSCFG_CORE0_MSB _u(4) +#define ACCESSCTRL_SYSCFG_CORE0_LSB _u(4) +#define ACCESSCTRL_SYSCFG_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_SP +// Description : If 1, SYSCFG can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_SYSCFG_SP_RESET _u(0x1) +#define ACCESSCTRL_SYSCFG_SP_BITS _u(0x00000008) +#define ACCESSCTRL_SYSCFG_SP_MSB _u(3) +#define ACCESSCTRL_SYSCFG_SP_LSB _u(3) +#define ACCESSCTRL_SYSCFG_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_SU +// Description : If 1, and SP is also set, SYSCFG can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_SYSCFG_SU_RESET _u(0x0) +#define ACCESSCTRL_SYSCFG_SU_BITS _u(0x00000004) +#define ACCESSCTRL_SYSCFG_SU_MSB _u(2) +#define ACCESSCTRL_SYSCFG_SU_LSB _u(2) +#define ACCESSCTRL_SYSCFG_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_NSP +// Description : If 1, SYSCFG can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_SYSCFG_NSP_RESET _u(0x0) +#define ACCESSCTRL_SYSCFG_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_SYSCFG_NSP_MSB _u(1) +#define ACCESSCTRL_SYSCFG_NSP_LSB _u(1) +#define ACCESSCTRL_SYSCFG_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_SYSCFG_NSU +// Description : If 1, and NSP is also set, SYSCFG can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_SYSCFG_NSU_RESET _u(0x0) +#define ACCESSCTRL_SYSCFG_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_SYSCFG_NSU_MSB _u(0) +#define ACCESSCTRL_SYSCFG_NSU_LSB _u(0) +#define ACCESSCTRL_SYSCFG_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_CLOCKS +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// CLOCKS, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_CLOCKS_OFFSET _u(0x000000c0) +#define ACCESSCTRL_CLOCKS_BITS _u(0x000000ff) +#define ACCESSCTRL_CLOCKS_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_DBG +// Description : If 1, CLOCKS can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_CLOCKS_DBG_RESET _u(0x1) +#define ACCESSCTRL_CLOCKS_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_CLOCKS_DBG_MSB _u(7) +#define ACCESSCTRL_CLOCKS_DBG_LSB _u(7) +#define ACCESSCTRL_CLOCKS_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_DMA +// Description : If 1, CLOCKS can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_CLOCKS_DMA_RESET _u(0x0) +#define ACCESSCTRL_CLOCKS_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_CLOCKS_DMA_MSB _u(6) +#define ACCESSCTRL_CLOCKS_DMA_LSB _u(6) +#define ACCESSCTRL_CLOCKS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_CORE1 +// Description : If 1, CLOCKS can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_CLOCKS_CORE1_RESET _u(0x1) +#define ACCESSCTRL_CLOCKS_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_CLOCKS_CORE1_MSB _u(5) +#define ACCESSCTRL_CLOCKS_CORE1_LSB _u(5) +#define ACCESSCTRL_CLOCKS_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_CORE0 +// Description : If 1, CLOCKS can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_CLOCKS_CORE0_RESET _u(0x1) +#define ACCESSCTRL_CLOCKS_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_CLOCKS_CORE0_MSB _u(4) +#define ACCESSCTRL_CLOCKS_CORE0_LSB _u(4) +#define ACCESSCTRL_CLOCKS_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_SP +// Description : If 1, CLOCKS can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_CLOCKS_SP_RESET _u(0x1) +#define ACCESSCTRL_CLOCKS_SP_BITS _u(0x00000008) +#define ACCESSCTRL_CLOCKS_SP_MSB _u(3) +#define ACCESSCTRL_CLOCKS_SP_LSB _u(3) +#define ACCESSCTRL_CLOCKS_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_SU +// Description : If 1, and SP is also set, CLOCKS can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_CLOCKS_SU_RESET _u(0x0) +#define ACCESSCTRL_CLOCKS_SU_BITS _u(0x00000004) +#define ACCESSCTRL_CLOCKS_SU_MSB _u(2) +#define ACCESSCTRL_CLOCKS_SU_LSB _u(2) +#define ACCESSCTRL_CLOCKS_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_NSP +// Description : If 1, CLOCKS can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_CLOCKS_NSP_RESET _u(0x0) +#define ACCESSCTRL_CLOCKS_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_CLOCKS_NSP_MSB _u(1) +#define ACCESSCTRL_CLOCKS_NSP_LSB _u(1) +#define ACCESSCTRL_CLOCKS_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_CLOCKS_NSU +// Description : If 1, and NSP is also set, CLOCKS can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_CLOCKS_NSU_RESET _u(0x0) +#define ACCESSCTRL_CLOCKS_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_CLOCKS_NSU_MSB _u(0) +#define ACCESSCTRL_CLOCKS_NSU_LSB _u(0) +#define ACCESSCTRL_CLOCKS_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_XOSC +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// XOSC, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_XOSC_OFFSET _u(0x000000c4) +#define ACCESSCTRL_XOSC_BITS _u(0x000000ff) +#define ACCESSCTRL_XOSC_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_DBG +// Description : If 1, XOSC can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_XOSC_DBG_RESET _u(0x1) +#define ACCESSCTRL_XOSC_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_XOSC_DBG_MSB _u(7) +#define ACCESSCTRL_XOSC_DBG_LSB _u(7) +#define ACCESSCTRL_XOSC_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_DMA +// Description : If 1, XOSC can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XOSC_DMA_RESET _u(0x0) +#define ACCESSCTRL_XOSC_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_XOSC_DMA_MSB _u(6) +#define ACCESSCTRL_XOSC_DMA_LSB _u(6) +#define ACCESSCTRL_XOSC_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_CORE1 +// Description : If 1, XOSC can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XOSC_CORE1_RESET _u(0x1) +#define ACCESSCTRL_XOSC_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_XOSC_CORE1_MSB _u(5) +#define ACCESSCTRL_XOSC_CORE1_LSB _u(5) +#define ACCESSCTRL_XOSC_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_CORE0 +// Description : If 1, XOSC can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XOSC_CORE0_RESET _u(0x1) +#define ACCESSCTRL_XOSC_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_XOSC_CORE0_MSB _u(4) +#define ACCESSCTRL_XOSC_CORE0_LSB _u(4) +#define ACCESSCTRL_XOSC_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_SP +// Description : If 1, XOSC can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_XOSC_SP_RESET _u(0x1) +#define ACCESSCTRL_XOSC_SP_BITS _u(0x00000008) +#define ACCESSCTRL_XOSC_SP_MSB _u(3) +#define ACCESSCTRL_XOSC_SP_LSB _u(3) +#define ACCESSCTRL_XOSC_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_SU +// Description : If 1, and SP is also set, XOSC can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_XOSC_SU_RESET _u(0x0) +#define ACCESSCTRL_XOSC_SU_BITS _u(0x00000004) +#define ACCESSCTRL_XOSC_SU_MSB _u(2) +#define ACCESSCTRL_XOSC_SU_LSB _u(2) +#define ACCESSCTRL_XOSC_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_NSP +// Description : If 1, XOSC can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_XOSC_NSP_RESET _u(0x0) +#define ACCESSCTRL_XOSC_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_XOSC_NSP_MSB _u(1) +#define ACCESSCTRL_XOSC_NSP_LSB _u(1) +#define ACCESSCTRL_XOSC_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XOSC_NSU +// Description : If 1, and NSP is also set, XOSC can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_XOSC_NSU_RESET _u(0x0) +#define ACCESSCTRL_XOSC_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_XOSC_NSU_MSB _u(0) +#define ACCESSCTRL_XOSC_NSU_LSB _u(0) +#define ACCESSCTRL_XOSC_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_ROSC +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// ROSC, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_ROSC_OFFSET _u(0x000000c8) +#define ACCESSCTRL_ROSC_BITS _u(0x000000ff) +#define ACCESSCTRL_ROSC_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_DBG +// Description : If 1, ROSC can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_ROSC_DBG_RESET _u(0x1) +#define ACCESSCTRL_ROSC_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_ROSC_DBG_MSB _u(7) +#define ACCESSCTRL_ROSC_DBG_LSB _u(7) +#define ACCESSCTRL_ROSC_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_DMA +// Description : If 1, ROSC can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ROSC_DMA_RESET _u(0x0) +#define ACCESSCTRL_ROSC_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_ROSC_DMA_MSB _u(6) +#define ACCESSCTRL_ROSC_DMA_LSB _u(6) +#define ACCESSCTRL_ROSC_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_CORE1 +// Description : If 1, ROSC can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ROSC_CORE1_RESET _u(0x1) +#define ACCESSCTRL_ROSC_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_ROSC_CORE1_MSB _u(5) +#define ACCESSCTRL_ROSC_CORE1_LSB _u(5) +#define ACCESSCTRL_ROSC_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_CORE0 +// Description : If 1, ROSC can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_ROSC_CORE0_RESET _u(0x1) +#define ACCESSCTRL_ROSC_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_ROSC_CORE0_MSB _u(4) +#define ACCESSCTRL_ROSC_CORE0_LSB _u(4) +#define ACCESSCTRL_ROSC_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_SP +// Description : If 1, ROSC can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_ROSC_SP_RESET _u(0x1) +#define ACCESSCTRL_ROSC_SP_BITS _u(0x00000008) +#define ACCESSCTRL_ROSC_SP_MSB _u(3) +#define ACCESSCTRL_ROSC_SP_LSB _u(3) +#define ACCESSCTRL_ROSC_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_SU +// Description : If 1, and SP is also set, ROSC can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_ROSC_SU_RESET _u(0x0) +#define ACCESSCTRL_ROSC_SU_BITS _u(0x00000004) +#define ACCESSCTRL_ROSC_SU_MSB _u(2) +#define ACCESSCTRL_ROSC_SU_LSB _u(2) +#define ACCESSCTRL_ROSC_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_NSP +// Description : If 1, ROSC can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_ROSC_NSP_RESET _u(0x0) +#define ACCESSCTRL_ROSC_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_ROSC_NSP_MSB _u(1) +#define ACCESSCTRL_ROSC_NSP_LSB _u(1) +#define ACCESSCTRL_ROSC_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_ROSC_NSU +// Description : If 1, and NSP is also set, ROSC can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_ROSC_NSU_RESET _u(0x0) +#define ACCESSCTRL_ROSC_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_ROSC_NSU_MSB _u(0) +#define ACCESSCTRL_ROSC_NSU_LSB _u(0) +#define ACCESSCTRL_ROSC_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PLL_SYS +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PLL_SYS, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PLL_SYS_OFFSET _u(0x000000cc) +#define ACCESSCTRL_PLL_SYS_BITS _u(0x000000ff) +#define ACCESSCTRL_PLL_SYS_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_DBG +// Description : If 1, PLL_SYS can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PLL_SYS_DBG_RESET _u(0x1) +#define ACCESSCTRL_PLL_SYS_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PLL_SYS_DBG_MSB _u(7) +#define ACCESSCTRL_PLL_SYS_DBG_LSB _u(7) +#define ACCESSCTRL_PLL_SYS_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_DMA +// Description : If 1, PLL_SYS can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PLL_SYS_DMA_RESET _u(0x0) +#define ACCESSCTRL_PLL_SYS_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PLL_SYS_DMA_MSB _u(6) +#define ACCESSCTRL_PLL_SYS_DMA_LSB _u(6) +#define ACCESSCTRL_PLL_SYS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_CORE1 +// Description : If 1, PLL_SYS can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PLL_SYS_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PLL_SYS_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PLL_SYS_CORE1_MSB _u(5) +#define ACCESSCTRL_PLL_SYS_CORE1_LSB _u(5) +#define ACCESSCTRL_PLL_SYS_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_CORE0 +// Description : If 1, PLL_SYS can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PLL_SYS_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PLL_SYS_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PLL_SYS_CORE0_MSB _u(4) +#define ACCESSCTRL_PLL_SYS_CORE0_LSB _u(4) +#define ACCESSCTRL_PLL_SYS_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_SP +// Description : If 1, PLL_SYS can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_PLL_SYS_SP_RESET _u(0x1) +#define ACCESSCTRL_PLL_SYS_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PLL_SYS_SP_MSB _u(3) +#define ACCESSCTRL_PLL_SYS_SP_LSB _u(3) +#define ACCESSCTRL_PLL_SYS_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_SU +// Description : If 1, and SP is also set, PLL_SYS can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_PLL_SYS_SU_RESET _u(0x0) +#define ACCESSCTRL_PLL_SYS_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PLL_SYS_SU_MSB _u(2) +#define ACCESSCTRL_PLL_SYS_SU_LSB _u(2) +#define ACCESSCTRL_PLL_SYS_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_NSP +// Description : If 1, PLL_SYS can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PLL_SYS_NSP_RESET _u(0x0) +#define ACCESSCTRL_PLL_SYS_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PLL_SYS_NSP_MSB _u(1) +#define ACCESSCTRL_PLL_SYS_NSP_LSB _u(1) +#define ACCESSCTRL_PLL_SYS_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_SYS_NSU +// Description : If 1, and NSP is also set, PLL_SYS can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PLL_SYS_NSU_RESET _u(0x0) +#define ACCESSCTRL_PLL_SYS_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PLL_SYS_NSU_MSB _u(0) +#define ACCESSCTRL_PLL_SYS_NSU_LSB _u(0) +#define ACCESSCTRL_PLL_SYS_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_PLL_USB +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// PLL_USB, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_PLL_USB_OFFSET _u(0x000000d0) +#define ACCESSCTRL_PLL_USB_BITS _u(0x000000ff) +#define ACCESSCTRL_PLL_USB_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_DBG +// Description : If 1, PLL_USB can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_PLL_USB_DBG_RESET _u(0x1) +#define ACCESSCTRL_PLL_USB_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_PLL_USB_DBG_MSB _u(7) +#define ACCESSCTRL_PLL_USB_DBG_LSB _u(7) +#define ACCESSCTRL_PLL_USB_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_DMA +// Description : If 1, PLL_USB can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PLL_USB_DMA_RESET _u(0x0) +#define ACCESSCTRL_PLL_USB_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_PLL_USB_DMA_MSB _u(6) +#define ACCESSCTRL_PLL_USB_DMA_LSB _u(6) +#define ACCESSCTRL_PLL_USB_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_CORE1 +// Description : If 1, PLL_USB can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PLL_USB_CORE1_RESET _u(0x1) +#define ACCESSCTRL_PLL_USB_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_PLL_USB_CORE1_MSB _u(5) +#define ACCESSCTRL_PLL_USB_CORE1_LSB _u(5) +#define ACCESSCTRL_PLL_USB_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_CORE0 +// Description : If 1, PLL_USB can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_PLL_USB_CORE0_RESET _u(0x1) +#define ACCESSCTRL_PLL_USB_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_PLL_USB_CORE0_MSB _u(4) +#define ACCESSCTRL_PLL_USB_CORE0_LSB _u(4) +#define ACCESSCTRL_PLL_USB_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_SP +// Description : If 1, PLL_USB can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_PLL_USB_SP_RESET _u(0x1) +#define ACCESSCTRL_PLL_USB_SP_BITS _u(0x00000008) +#define ACCESSCTRL_PLL_USB_SP_MSB _u(3) +#define ACCESSCTRL_PLL_USB_SP_LSB _u(3) +#define ACCESSCTRL_PLL_USB_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_SU +// Description : If 1, and SP is also set, PLL_USB can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_PLL_USB_SU_RESET _u(0x0) +#define ACCESSCTRL_PLL_USB_SU_BITS _u(0x00000004) +#define ACCESSCTRL_PLL_USB_SU_MSB _u(2) +#define ACCESSCTRL_PLL_USB_SU_LSB _u(2) +#define ACCESSCTRL_PLL_USB_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_NSP +// Description : If 1, PLL_USB can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_PLL_USB_NSP_RESET _u(0x0) +#define ACCESSCTRL_PLL_USB_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_PLL_USB_NSP_MSB _u(1) +#define ACCESSCTRL_PLL_USB_NSP_LSB _u(1) +#define ACCESSCTRL_PLL_USB_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_PLL_USB_NSU +// Description : If 1, and NSP is also set, PLL_USB can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_PLL_USB_NSU_RESET _u(0x0) +#define ACCESSCTRL_PLL_USB_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_PLL_USB_NSU_MSB _u(0) +#define ACCESSCTRL_PLL_USB_NSU_LSB _u(0) +#define ACCESSCTRL_PLL_USB_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_TICKS +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// TICKS, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_TICKS_OFFSET _u(0x000000d4) +#define ACCESSCTRL_TICKS_BITS _u(0x000000ff) +#define ACCESSCTRL_TICKS_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_DBG +// Description : If 1, TICKS can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_TICKS_DBG_RESET _u(0x1) +#define ACCESSCTRL_TICKS_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_TICKS_DBG_MSB _u(7) +#define ACCESSCTRL_TICKS_DBG_LSB _u(7) +#define ACCESSCTRL_TICKS_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_DMA +// Description : If 1, TICKS can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TICKS_DMA_RESET _u(0x0) +#define ACCESSCTRL_TICKS_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_TICKS_DMA_MSB _u(6) +#define ACCESSCTRL_TICKS_DMA_LSB _u(6) +#define ACCESSCTRL_TICKS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_CORE1 +// Description : If 1, TICKS can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TICKS_CORE1_RESET _u(0x1) +#define ACCESSCTRL_TICKS_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_TICKS_CORE1_MSB _u(5) +#define ACCESSCTRL_TICKS_CORE1_LSB _u(5) +#define ACCESSCTRL_TICKS_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_CORE0 +// Description : If 1, TICKS can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_TICKS_CORE0_RESET _u(0x1) +#define ACCESSCTRL_TICKS_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_TICKS_CORE0_MSB _u(4) +#define ACCESSCTRL_TICKS_CORE0_LSB _u(4) +#define ACCESSCTRL_TICKS_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_SP +// Description : If 1, TICKS can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_TICKS_SP_RESET _u(0x1) +#define ACCESSCTRL_TICKS_SP_BITS _u(0x00000008) +#define ACCESSCTRL_TICKS_SP_MSB _u(3) +#define ACCESSCTRL_TICKS_SP_LSB _u(3) +#define ACCESSCTRL_TICKS_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_SU +// Description : If 1, and SP is also set, TICKS can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_TICKS_SU_RESET _u(0x0) +#define ACCESSCTRL_TICKS_SU_BITS _u(0x00000004) +#define ACCESSCTRL_TICKS_SU_MSB _u(2) +#define ACCESSCTRL_TICKS_SU_LSB _u(2) +#define ACCESSCTRL_TICKS_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_NSP +// Description : If 1, TICKS can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_TICKS_NSP_RESET _u(0x0) +#define ACCESSCTRL_TICKS_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_TICKS_NSP_MSB _u(1) +#define ACCESSCTRL_TICKS_NSP_LSB _u(1) +#define ACCESSCTRL_TICKS_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_TICKS_NSU +// Description : If 1, and NSP is also set, TICKS can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_TICKS_NSU_RESET _u(0x0) +#define ACCESSCTRL_TICKS_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_TICKS_NSU_MSB _u(0) +#define ACCESSCTRL_TICKS_NSU_LSB _u(0) +#define ACCESSCTRL_TICKS_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_WATCHDOG +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// WATCHDOG, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_WATCHDOG_OFFSET _u(0x000000d8) +#define ACCESSCTRL_WATCHDOG_BITS _u(0x000000ff) +#define ACCESSCTRL_WATCHDOG_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_DBG +// Description : If 1, WATCHDOG can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_WATCHDOG_DBG_RESET _u(0x1) +#define ACCESSCTRL_WATCHDOG_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_WATCHDOG_DBG_MSB _u(7) +#define ACCESSCTRL_WATCHDOG_DBG_LSB _u(7) +#define ACCESSCTRL_WATCHDOG_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_DMA +// Description : If 1, WATCHDOG can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_WATCHDOG_DMA_RESET _u(0x0) +#define ACCESSCTRL_WATCHDOG_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_WATCHDOG_DMA_MSB _u(6) +#define ACCESSCTRL_WATCHDOG_DMA_LSB _u(6) +#define ACCESSCTRL_WATCHDOG_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_CORE1 +// Description : If 1, WATCHDOG can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_WATCHDOG_CORE1_RESET _u(0x1) +#define ACCESSCTRL_WATCHDOG_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_WATCHDOG_CORE1_MSB _u(5) +#define ACCESSCTRL_WATCHDOG_CORE1_LSB _u(5) +#define ACCESSCTRL_WATCHDOG_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_CORE0 +// Description : If 1, WATCHDOG can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_WATCHDOG_CORE0_RESET _u(0x1) +#define ACCESSCTRL_WATCHDOG_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_WATCHDOG_CORE0_MSB _u(4) +#define ACCESSCTRL_WATCHDOG_CORE0_LSB _u(4) +#define ACCESSCTRL_WATCHDOG_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_SP +// Description : If 1, WATCHDOG can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_WATCHDOG_SP_RESET _u(0x1) +#define ACCESSCTRL_WATCHDOG_SP_BITS _u(0x00000008) +#define ACCESSCTRL_WATCHDOG_SP_MSB _u(3) +#define ACCESSCTRL_WATCHDOG_SP_LSB _u(3) +#define ACCESSCTRL_WATCHDOG_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_SU +// Description : If 1, and SP is also set, WATCHDOG can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_WATCHDOG_SU_RESET _u(0x0) +#define ACCESSCTRL_WATCHDOG_SU_BITS _u(0x00000004) +#define ACCESSCTRL_WATCHDOG_SU_MSB _u(2) +#define ACCESSCTRL_WATCHDOG_SU_LSB _u(2) +#define ACCESSCTRL_WATCHDOG_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_NSP +// Description : If 1, WATCHDOG can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_WATCHDOG_NSP_RESET _u(0x0) +#define ACCESSCTRL_WATCHDOG_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_WATCHDOG_NSP_MSB _u(1) +#define ACCESSCTRL_WATCHDOG_NSP_LSB _u(1) +#define ACCESSCTRL_WATCHDOG_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_WATCHDOG_NSU +// Description : If 1, and NSP is also set, WATCHDOG can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_WATCHDOG_NSU_RESET _u(0x0) +#define ACCESSCTRL_WATCHDOG_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_WATCHDOG_NSU_MSB _u(0) +#define ACCESSCTRL_WATCHDOG_NSU_LSB _u(0) +#define ACCESSCTRL_WATCHDOG_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_RSM +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// RSM, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_RSM_OFFSET _u(0x000000dc) +#define ACCESSCTRL_RSM_BITS _u(0x000000ff) +#define ACCESSCTRL_RSM_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_DBG +// Description : If 1, RSM can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_RSM_DBG_RESET _u(0x1) +#define ACCESSCTRL_RSM_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_RSM_DBG_MSB _u(7) +#define ACCESSCTRL_RSM_DBG_LSB _u(7) +#define ACCESSCTRL_RSM_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_DMA +// Description : If 1, RSM can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_RSM_DMA_RESET _u(0x0) +#define ACCESSCTRL_RSM_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_RSM_DMA_MSB _u(6) +#define ACCESSCTRL_RSM_DMA_LSB _u(6) +#define ACCESSCTRL_RSM_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_CORE1 +// Description : If 1, RSM can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_RSM_CORE1_RESET _u(0x1) +#define ACCESSCTRL_RSM_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_RSM_CORE1_MSB _u(5) +#define ACCESSCTRL_RSM_CORE1_LSB _u(5) +#define ACCESSCTRL_RSM_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_CORE0 +// Description : If 1, RSM can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_RSM_CORE0_RESET _u(0x1) +#define ACCESSCTRL_RSM_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_RSM_CORE0_MSB _u(4) +#define ACCESSCTRL_RSM_CORE0_LSB _u(4) +#define ACCESSCTRL_RSM_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_SP +// Description : If 1, RSM can be accessed from a Secure, Privileged context. +#define ACCESSCTRL_RSM_SP_RESET _u(0x1) +#define ACCESSCTRL_RSM_SP_BITS _u(0x00000008) +#define ACCESSCTRL_RSM_SP_MSB _u(3) +#define ACCESSCTRL_RSM_SP_LSB _u(3) +#define ACCESSCTRL_RSM_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_SU +// Description : If 1, and SP is also set, RSM can be accessed from a Secure, +// Unprivileged context. +#define ACCESSCTRL_RSM_SU_RESET _u(0x0) +#define ACCESSCTRL_RSM_SU_BITS _u(0x00000004) +#define ACCESSCTRL_RSM_SU_MSB _u(2) +#define ACCESSCTRL_RSM_SU_LSB _u(2) +#define ACCESSCTRL_RSM_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_NSP +// Description : If 1, RSM can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_RSM_NSP_RESET _u(0x0) +#define ACCESSCTRL_RSM_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_RSM_NSP_MSB _u(1) +#define ACCESSCTRL_RSM_NSP_LSB _u(1) +#define ACCESSCTRL_RSM_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_RSM_NSU +// Description : If 1, and NSP is also set, RSM can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_RSM_NSU_RESET _u(0x0) +#define ACCESSCTRL_RSM_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_RSM_NSU_MSB _u(0) +#define ACCESSCTRL_RSM_NSU_LSB _u(0) +#define ACCESSCTRL_RSM_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_XIP_CTRL +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// XIP_CTRL, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_XIP_CTRL_OFFSET _u(0x000000e0) +#define ACCESSCTRL_XIP_CTRL_BITS _u(0x000000ff) +#define ACCESSCTRL_XIP_CTRL_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_DBG +// Description : If 1, XIP_CTRL can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_XIP_CTRL_DBG_RESET _u(0x1) +#define ACCESSCTRL_XIP_CTRL_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_XIP_CTRL_DBG_MSB _u(7) +#define ACCESSCTRL_XIP_CTRL_DBG_LSB _u(7) +#define ACCESSCTRL_XIP_CTRL_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_DMA +// Description : If 1, XIP_CTRL can be accessed by the DMA, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_XIP_CTRL_DMA_RESET _u(0x0) +#define ACCESSCTRL_XIP_CTRL_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_XIP_CTRL_DMA_MSB _u(6) +#define ACCESSCTRL_XIP_CTRL_DMA_LSB _u(6) +#define ACCESSCTRL_XIP_CTRL_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_CORE1 +// Description : If 1, XIP_CTRL can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_CTRL_CORE1_RESET _u(0x1) +#define ACCESSCTRL_XIP_CTRL_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_XIP_CTRL_CORE1_MSB _u(5) +#define ACCESSCTRL_XIP_CTRL_CORE1_LSB _u(5) +#define ACCESSCTRL_XIP_CTRL_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_CORE0 +// Description : If 1, XIP_CTRL can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_CTRL_CORE0_RESET _u(0x1) +#define ACCESSCTRL_XIP_CTRL_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_XIP_CTRL_CORE0_MSB _u(4) +#define ACCESSCTRL_XIP_CTRL_CORE0_LSB _u(4) +#define ACCESSCTRL_XIP_CTRL_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_SP +// Description : If 1, XIP_CTRL can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_XIP_CTRL_SP_RESET _u(0x1) +#define ACCESSCTRL_XIP_CTRL_SP_BITS _u(0x00000008) +#define ACCESSCTRL_XIP_CTRL_SP_MSB _u(3) +#define ACCESSCTRL_XIP_CTRL_SP_LSB _u(3) +#define ACCESSCTRL_XIP_CTRL_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_SU +// Description : If 1, and SP is also set, XIP_CTRL can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_XIP_CTRL_SU_RESET _u(0x0) +#define ACCESSCTRL_XIP_CTRL_SU_BITS _u(0x00000004) +#define ACCESSCTRL_XIP_CTRL_SU_MSB _u(2) +#define ACCESSCTRL_XIP_CTRL_SU_LSB _u(2) +#define ACCESSCTRL_XIP_CTRL_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_NSP +// Description : If 1, XIP_CTRL can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_XIP_CTRL_NSP_RESET _u(0x0) +#define ACCESSCTRL_XIP_CTRL_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_XIP_CTRL_NSP_MSB _u(1) +#define ACCESSCTRL_XIP_CTRL_NSP_LSB _u(1) +#define ACCESSCTRL_XIP_CTRL_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_CTRL_NSU +// Description : If 1, and NSP is also set, XIP_CTRL can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_XIP_CTRL_NSU_RESET _u(0x0) +#define ACCESSCTRL_XIP_CTRL_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_XIP_CTRL_NSU_MSB _u(0) +#define ACCESSCTRL_XIP_CTRL_NSU_LSB _u(0) +#define ACCESSCTRL_XIP_CTRL_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_XIP_QMI +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// XIP_QMI, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged processor or debug access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_XIP_QMI_OFFSET _u(0x000000e4) +#define ACCESSCTRL_XIP_QMI_BITS _u(0x000000ff) +#define ACCESSCTRL_XIP_QMI_RESET _u(0x000000b8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_DBG +// Description : If 1, XIP_QMI can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_XIP_QMI_DBG_RESET _u(0x1) +#define ACCESSCTRL_XIP_QMI_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_XIP_QMI_DBG_MSB _u(7) +#define ACCESSCTRL_XIP_QMI_DBG_LSB _u(7) +#define ACCESSCTRL_XIP_QMI_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_DMA +// Description : If 1, XIP_QMI can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_QMI_DMA_RESET _u(0x0) +#define ACCESSCTRL_XIP_QMI_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_XIP_QMI_DMA_MSB _u(6) +#define ACCESSCTRL_XIP_QMI_DMA_LSB _u(6) +#define ACCESSCTRL_XIP_QMI_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_CORE1 +// Description : If 1, XIP_QMI can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_QMI_CORE1_RESET _u(0x1) +#define ACCESSCTRL_XIP_QMI_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_XIP_QMI_CORE1_MSB _u(5) +#define ACCESSCTRL_XIP_QMI_CORE1_LSB _u(5) +#define ACCESSCTRL_XIP_QMI_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_CORE0 +// Description : If 1, XIP_QMI can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_QMI_CORE0_RESET _u(0x1) +#define ACCESSCTRL_XIP_QMI_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_XIP_QMI_CORE0_MSB _u(4) +#define ACCESSCTRL_XIP_QMI_CORE0_LSB _u(4) +#define ACCESSCTRL_XIP_QMI_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_SP +// Description : If 1, XIP_QMI can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_XIP_QMI_SP_RESET _u(0x1) +#define ACCESSCTRL_XIP_QMI_SP_BITS _u(0x00000008) +#define ACCESSCTRL_XIP_QMI_SP_MSB _u(3) +#define ACCESSCTRL_XIP_QMI_SP_LSB _u(3) +#define ACCESSCTRL_XIP_QMI_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_SU +// Description : If 1, and SP is also set, XIP_QMI can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_XIP_QMI_SU_RESET _u(0x0) +#define ACCESSCTRL_XIP_QMI_SU_BITS _u(0x00000004) +#define ACCESSCTRL_XIP_QMI_SU_MSB _u(2) +#define ACCESSCTRL_XIP_QMI_SU_LSB _u(2) +#define ACCESSCTRL_XIP_QMI_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_NSP +// Description : If 1, XIP_QMI can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_XIP_QMI_NSP_RESET _u(0x0) +#define ACCESSCTRL_XIP_QMI_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_XIP_QMI_NSP_MSB _u(1) +#define ACCESSCTRL_XIP_QMI_NSP_LSB _u(1) +#define ACCESSCTRL_XIP_QMI_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_QMI_NSU +// Description : If 1, and NSP is also set, XIP_QMI can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_XIP_QMI_NSU_RESET _u(0x0) +#define ACCESSCTRL_XIP_QMI_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_XIP_QMI_NSU_MSB _u(0) +#define ACCESSCTRL_XIP_QMI_NSU_LSB _u(0) +#define ACCESSCTRL_XIP_QMI_NSU_ACCESS "RW" +// ============================================================================= +// Register : ACCESSCTRL_XIP_AUX +// Description : Control whether debugger, DMA, core 0 and core 1 can access +// XIP_AUX, and at what security/privilege levels they can do so. +// +// Defaults to Secure, Privileged access only. +// +// This register is writable only from a Secure, Privileged +// processor or debugger, with the exception of the NSU bit, which +// becomes Non-secure-Privileged-writable when the NSP bit is set. +#define ACCESSCTRL_XIP_AUX_OFFSET _u(0x000000e8) +#define ACCESSCTRL_XIP_AUX_BITS _u(0x000000ff) +#define ACCESSCTRL_XIP_AUX_RESET _u(0x000000f8) +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_DBG +// Description : If 1, XIP_AUX can be accessed by the debugger, at +// security/privilege levels permitted by SP/NSP/SU/NSU in this +// register. +#define ACCESSCTRL_XIP_AUX_DBG_RESET _u(0x1) +#define ACCESSCTRL_XIP_AUX_DBG_BITS _u(0x00000080) +#define ACCESSCTRL_XIP_AUX_DBG_MSB _u(7) +#define ACCESSCTRL_XIP_AUX_DBG_LSB _u(7) +#define ACCESSCTRL_XIP_AUX_DBG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_DMA +// Description : If 1, XIP_AUX can be accessed by the DMA, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_AUX_DMA_RESET _u(0x1) +#define ACCESSCTRL_XIP_AUX_DMA_BITS _u(0x00000040) +#define ACCESSCTRL_XIP_AUX_DMA_MSB _u(6) +#define ACCESSCTRL_XIP_AUX_DMA_LSB _u(6) +#define ACCESSCTRL_XIP_AUX_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_CORE1 +// Description : If 1, XIP_AUX can be accessed by core 1, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_AUX_CORE1_RESET _u(0x1) +#define ACCESSCTRL_XIP_AUX_CORE1_BITS _u(0x00000020) +#define ACCESSCTRL_XIP_AUX_CORE1_MSB _u(5) +#define ACCESSCTRL_XIP_AUX_CORE1_LSB _u(5) +#define ACCESSCTRL_XIP_AUX_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_CORE0 +// Description : If 1, XIP_AUX can be accessed by core 0, at security/privilege +// levels permitted by SP/NSP/SU/NSU in this register. +#define ACCESSCTRL_XIP_AUX_CORE0_RESET _u(0x1) +#define ACCESSCTRL_XIP_AUX_CORE0_BITS _u(0x00000010) +#define ACCESSCTRL_XIP_AUX_CORE0_MSB _u(4) +#define ACCESSCTRL_XIP_AUX_CORE0_LSB _u(4) +#define ACCESSCTRL_XIP_AUX_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_SP +// Description : If 1, XIP_AUX can be accessed from a Secure, Privileged +// context. +#define ACCESSCTRL_XIP_AUX_SP_RESET _u(0x1) +#define ACCESSCTRL_XIP_AUX_SP_BITS _u(0x00000008) +#define ACCESSCTRL_XIP_AUX_SP_MSB _u(3) +#define ACCESSCTRL_XIP_AUX_SP_LSB _u(3) +#define ACCESSCTRL_XIP_AUX_SP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_SU +// Description : If 1, and SP is also set, XIP_AUX can be accessed from a +// Secure, Unprivileged context. +#define ACCESSCTRL_XIP_AUX_SU_RESET _u(0x0) +#define ACCESSCTRL_XIP_AUX_SU_BITS _u(0x00000004) +#define ACCESSCTRL_XIP_AUX_SU_MSB _u(2) +#define ACCESSCTRL_XIP_AUX_SU_LSB _u(2) +#define ACCESSCTRL_XIP_AUX_SU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_NSP +// Description : If 1, XIP_AUX can be accessed from a Non-secure, Privileged +// context. +#define ACCESSCTRL_XIP_AUX_NSP_RESET _u(0x0) +#define ACCESSCTRL_XIP_AUX_NSP_BITS _u(0x00000002) +#define ACCESSCTRL_XIP_AUX_NSP_MSB _u(1) +#define ACCESSCTRL_XIP_AUX_NSP_LSB _u(1) +#define ACCESSCTRL_XIP_AUX_NSP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ACCESSCTRL_XIP_AUX_NSU +// Description : If 1, and NSP is also set, XIP_AUX can be accessed from a Non- +// secure, Unprivileged context. +// +// This bit is writable from a Non-secure, Privileged context, if +// and only if the NSP bit is set. +#define ACCESSCTRL_XIP_AUX_NSU_RESET _u(0x0) +#define ACCESSCTRL_XIP_AUX_NSU_BITS _u(0x00000001) +#define ACCESSCTRL_XIP_AUX_NSU_MSB _u(0) +#define ACCESSCTRL_XIP_AUX_NSU_LSB _u(0) +#define ACCESSCTRL_XIP_AUX_NSU_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_ACCESSCTRL_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/adc.h b/lib/pico-sdk/rp2350/hardware/regs/adc.h new file mode 100644 index 000000000000..1778d502df7c --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/adc.h @@ -0,0 +1,316 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : ADC +// Version : 2 +// Bus type : apb +// Description : Control and data interface to SAR ADC +// ============================================================================= +#ifndef _HARDWARE_REGS_ADC_H +#define _HARDWARE_REGS_ADC_H +// ============================================================================= +// Register : ADC_CS +// Description : ADC Control and Status +#define ADC_CS_OFFSET _u(0x00000000) +#define ADC_CS_BITS _u(0x01fff70f) +#define ADC_CS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_CS_RROBIN +// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to +// disable. +// Otherwise, the ADC will cycle through each enabled channel in a +// round-robin fashion. +// The first channel to be sampled will be the one currently +// indicated by AINSEL. +// AINSEL will be updated after each conversion with the newly- +// selected channel. +#define ADC_CS_RROBIN_RESET _u(0x000) +#define ADC_CS_RROBIN_BITS _u(0x01ff0000) +#define ADC_CS_RROBIN_MSB _u(24) +#define ADC_CS_RROBIN_LSB _u(16) +#define ADC_CS_RROBIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_AINSEL +// Description : Select analog mux input. Updated automatically in round-robin +// mode. +// This is corrected for the package option so only ADC channels +// which are bonded are available, and in the correct order +#define ADC_CS_AINSEL_RESET _u(0x0) +#define ADC_CS_AINSEL_BITS _u(0x0000f000) +#define ADC_CS_AINSEL_MSB _u(15) +#define ADC_CS_AINSEL_LSB _u(12) +#define ADC_CS_AINSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_ERR_STICKY +// Description : Some past ADC conversion encountered an error. Write 1 to +// clear. +#define ADC_CS_ERR_STICKY_RESET _u(0x0) +#define ADC_CS_ERR_STICKY_BITS _u(0x00000400) +#define ADC_CS_ERR_STICKY_MSB _u(10) +#define ADC_CS_ERR_STICKY_LSB _u(10) +#define ADC_CS_ERR_STICKY_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_ERR +// Description : The most recent ADC conversion encountered an error; result is +// undefined or noisy. +#define ADC_CS_ERR_RESET _u(0x0) +#define ADC_CS_ERR_BITS _u(0x00000200) +#define ADC_CS_ERR_MSB _u(9) +#define ADC_CS_ERR_LSB _u(9) +#define ADC_CS_ERR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_READY +// Description : 1 if the ADC is ready to start a new conversion. Implies any +// previous conversion has completed. +// 0 whilst conversion in progress. +#define ADC_CS_READY_RESET _u(0x0) +#define ADC_CS_READY_BITS _u(0x00000100) +#define ADC_CS_READY_MSB _u(8) +#define ADC_CS_READY_LSB _u(8) +#define ADC_CS_READY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_START_MANY +// Description : Continuously perform conversions whilst this bit is 1. A new +// conversion will start immediately after the previous finishes. +#define ADC_CS_START_MANY_RESET _u(0x0) +#define ADC_CS_START_MANY_BITS _u(0x00000008) +#define ADC_CS_START_MANY_MSB _u(3) +#define ADC_CS_START_MANY_LSB _u(3) +#define ADC_CS_START_MANY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_START_ONCE +// Description : Start a single conversion. Self-clearing. Ignored if start_many +// is asserted. +#define ADC_CS_START_ONCE_RESET _u(0x0) +#define ADC_CS_START_ONCE_BITS _u(0x00000004) +#define ADC_CS_START_ONCE_MSB _u(2) +#define ADC_CS_START_ONCE_LSB _u(2) +#define ADC_CS_START_ONCE_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_TS_EN +// Description : Power on temperature sensor. 1 - enabled. 0 - disabled. +#define ADC_CS_TS_EN_RESET _u(0x0) +#define ADC_CS_TS_EN_BITS _u(0x00000002) +#define ADC_CS_TS_EN_MSB _u(1) +#define ADC_CS_TS_EN_LSB _u(1) +#define ADC_CS_TS_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_CS_EN +// Description : Power on ADC and enable its clock. +// 1 - enabled. 0 - disabled. +#define ADC_CS_EN_RESET _u(0x0) +#define ADC_CS_EN_BITS _u(0x00000001) +#define ADC_CS_EN_MSB _u(0) +#define ADC_CS_EN_LSB _u(0) +#define ADC_CS_EN_ACCESS "RW" +// ============================================================================= +// Register : ADC_RESULT +// Description : Result of most recent ADC conversion +#define ADC_RESULT_OFFSET _u(0x00000004) +#define ADC_RESULT_BITS _u(0x00000fff) +#define ADC_RESULT_RESET _u(0x00000000) +#define ADC_RESULT_MSB _u(11) +#define ADC_RESULT_LSB _u(0) +#define ADC_RESULT_ACCESS "RO" +// ============================================================================= +// Register : ADC_FCS +// Description : FIFO control and status +#define ADC_FCS_OFFSET _u(0x00000008) +#define ADC_FCS_BITS _u(0x0f0f0f0f) +#define ADC_FCS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_THRESH +// Description : DREQ/IRQ asserted when level >= threshold +#define ADC_FCS_THRESH_RESET _u(0x0) +#define ADC_FCS_THRESH_BITS _u(0x0f000000) +#define ADC_FCS_THRESH_MSB _u(27) +#define ADC_FCS_THRESH_LSB _u(24) +#define ADC_FCS_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_LEVEL +// Description : The number of conversion results currently waiting in the FIFO +#define ADC_FCS_LEVEL_RESET _u(0x0) +#define ADC_FCS_LEVEL_BITS _u(0x000f0000) +#define ADC_FCS_LEVEL_MSB _u(19) +#define ADC_FCS_LEVEL_LSB _u(16) +#define ADC_FCS_LEVEL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_OVER +// Description : 1 if the FIFO has been overflowed. Write 1 to clear. +#define ADC_FCS_OVER_RESET _u(0x0) +#define ADC_FCS_OVER_BITS _u(0x00000800) +#define ADC_FCS_OVER_MSB _u(11) +#define ADC_FCS_OVER_LSB _u(11) +#define ADC_FCS_OVER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_UNDER +// Description : 1 if the FIFO has been underflowed. Write 1 to clear. +#define ADC_FCS_UNDER_RESET _u(0x0) +#define ADC_FCS_UNDER_BITS _u(0x00000400) +#define ADC_FCS_UNDER_MSB _u(10) +#define ADC_FCS_UNDER_LSB _u(10) +#define ADC_FCS_UNDER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_FULL +#define ADC_FCS_FULL_RESET _u(0x0) +#define ADC_FCS_FULL_BITS _u(0x00000200) +#define ADC_FCS_FULL_MSB _u(9) +#define ADC_FCS_FULL_LSB _u(9) +#define ADC_FCS_FULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_EMPTY +#define ADC_FCS_EMPTY_RESET _u(0x0) +#define ADC_FCS_EMPTY_BITS _u(0x00000100) +#define ADC_FCS_EMPTY_MSB _u(8) +#define ADC_FCS_EMPTY_LSB _u(8) +#define ADC_FCS_EMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_DREQ_EN +// Description : If 1: assert DMA requests when FIFO contains data +#define ADC_FCS_DREQ_EN_RESET _u(0x0) +#define ADC_FCS_DREQ_EN_BITS _u(0x00000008) +#define ADC_FCS_DREQ_EN_MSB _u(3) +#define ADC_FCS_DREQ_EN_LSB _u(3) +#define ADC_FCS_DREQ_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_ERR +// Description : If 1: conversion error bit appears in the FIFO alongside the +// result +#define ADC_FCS_ERR_RESET _u(0x0) +#define ADC_FCS_ERR_BITS _u(0x00000004) +#define ADC_FCS_ERR_MSB _u(2) +#define ADC_FCS_ERR_LSB _u(2) +#define ADC_FCS_ERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_SHIFT +// Description : If 1: FIFO results are right-shifted to be one byte in size. +// Enables DMA to byte buffers. +#define ADC_FCS_SHIFT_RESET _u(0x0) +#define ADC_FCS_SHIFT_BITS _u(0x00000002) +#define ADC_FCS_SHIFT_MSB _u(1) +#define ADC_FCS_SHIFT_LSB _u(1) +#define ADC_FCS_SHIFT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_FCS_EN +// Description : If 1: write result to the FIFO after each conversion. +#define ADC_FCS_EN_RESET _u(0x0) +#define ADC_FCS_EN_BITS _u(0x00000001) +#define ADC_FCS_EN_MSB _u(0) +#define ADC_FCS_EN_LSB _u(0) +#define ADC_FCS_EN_ACCESS "RW" +// ============================================================================= +// Register : ADC_FIFO +// Description : Conversion result FIFO +#define ADC_FIFO_OFFSET _u(0x0000000c) +#define ADC_FIFO_BITS _u(0x00008fff) +#define ADC_FIFO_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_FIFO_ERR +// Description : 1 if this particular sample experienced a conversion error. +// Remains in the same location if the sample is shifted. +#define ADC_FIFO_ERR_RESET "-" +#define ADC_FIFO_ERR_BITS _u(0x00008000) +#define ADC_FIFO_ERR_MSB _u(15) +#define ADC_FIFO_ERR_LSB _u(15) +#define ADC_FIFO_ERR_ACCESS "RF" +// ----------------------------------------------------------------------------- +// Field : ADC_FIFO_VAL +#define ADC_FIFO_VAL_RESET "-" +#define ADC_FIFO_VAL_BITS _u(0x00000fff) +#define ADC_FIFO_VAL_MSB _u(11) +#define ADC_FIFO_VAL_LSB _u(0) +#define ADC_FIFO_VAL_ACCESS "RF" +// ============================================================================= +// Register : ADC_DIV +// Description : Clock divider. If non-zero, CS_START_MANY will start +// conversions +// at regular intervals rather than back-to-back. +// The divider is reset when either of these fields are written. +// Total period is 1 + INT + FRAC / 256 +#define ADC_DIV_OFFSET _u(0x00000010) +#define ADC_DIV_BITS _u(0x00ffffff) +#define ADC_DIV_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_DIV_INT +// Description : Integer part of clock divisor. +#define ADC_DIV_INT_RESET _u(0x0000) +#define ADC_DIV_INT_BITS _u(0x00ffff00) +#define ADC_DIV_INT_MSB _u(23) +#define ADC_DIV_INT_LSB _u(8) +#define ADC_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ADC_DIV_FRAC +// Description : Fractional part of clock divisor. First-order delta-sigma. +#define ADC_DIV_FRAC_RESET _u(0x00) +#define ADC_DIV_FRAC_BITS _u(0x000000ff) +#define ADC_DIV_FRAC_MSB _u(7) +#define ADC_DIV_FRAC_LSB _u(0) +#define ADC_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : ADC_INTR +// Description : Raw Interrupts +#define ADC_INTR_OFFSET _u(0x00000014) +#define ADC_INTR_BITS _u(0x00000001) +#define ADC_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_INTR_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTR_FIFO_RESET _u(0x0) +#define ADC_INTR_FIFO_BITS _u(0x00000001) +#define ADC_INTR_FIFO_MSB _u(0) +#define ADC_INTR_FIFO_LSB _u(0) +#define ADC_INTR_FIFO_ACCESS "RO" +// ============================================================================= +// Register : ADC_INTE +// Description : Interrupt Enable +#define ADC_INTE_OFFSET _u(0x00000018) +#define ADC_INTE_BITS _u(0x00000001) +#define ADC_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_INTE_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTE_FIFO_RESET _u(0x0) +#define ADC_INTE_FIFO_BITS _u(0x00000001) +#define ADC_INTE_FIFO_MSB _u(0) +#define ADC_INTE_FIFO_LSB _u(0) +#define ADC_INTE_FIFO_ACCESS "RW" +// ============================================================================= +// Register : ADC_INTF +// Description : Interrupt Force +#define ADC_INTF_OFFSET _u(0x0000001c) +#define ADC_INTF_BITS _u(0x00000001) +#define ADC_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_INTF_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTF_FIFO_RESET _u(0x0) +#define ADC_INTF_FIFO_BITS _u(0x00000001) +#define ADC_INTF_FIFO_MSB _u(0) +#define ADC_INTF_FIFO_LSB _u(0) +#define ADC_INTF_FIFO_ACCESS "RW" +// ============================================================================= +// Register : ADC_INTS +// Description : Interrupt status after masking & forcing +#define ADC_INTS_OFFSET _u(0x00000020) +#define ADC_INTS_BITS _u(0x00000001) +#define ADC_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ADC_INTS_FIFO +// Description : Triggered when the sample FIFO reaches a certain level. +// This level can be programmed via the FCS_THRESH field. +#define ADC_INTS_FIFO_RESET _u(0x0) +#define ADC_INTS_FIFO_BITS _u(0x00000001) +#define ADC_INTS_FIFO_MSB _u(0) +#define ADC_INTS_FIFO_LSB _u(0) +#define ADC_INTS_FIFO_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_ADC_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/addressmap.h b/lib/pico-sdk/rp2350/hardware/regs/addressmap.h new file mode 100644 index 000000000000..0e8df5201368 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/addressmap.h @@ -0,0 +1,112 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _ADDRESSMAP_H +#define _ADDRESSMAP_H + +/** + * \file rp2350/addressmap.h + */ + +#include "hardware/platform_defs.h" + +// Register address offsets for atomic RMW aliases +#define REG_ALIAS_RW_BITS (_u(0x0) << _u(12)) +#define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12)) +#define REG_ALIAS_SET_BITS (_u(0x2) << _u(12)) +#define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12)) + +#define ROM_BASE _u(0x00000000) +#define XIP_BASE _u(0x10000000) +#define XIP_SRAM_BASE _u(0x13ffc000) +#define XIP_END _u(0x14000000) +#define XIP_NOCACHE_NOALLOC_BASE _u(0x14000000) +#define XIP_SRAM_END _u(0x14000000) +#define XIP_NOCACHE_NOALLOC_END _u(0x18000000) +#define XIP_MAINTENANCE_BASE _u(0x18000000) +#define XIP_NOCACHE_NOALLOC_NOTRANSLATE_BASE _u(0x1c000000) +#define SRAM0_BASE _u(0x20000000) +#define XIP_NOCACHE_NOALLOC_NOTRANSLATE_END _u(0x20000000) +#define SRAM_BASE _u(0x20000000) +#define SRAM_STRIPED_BASE _u(0x20000000) +#define SRAM4_BASE _u(0x20040000) +#define SRAM8_BASE _u(0x20080000) +#define SRAM_STRIPED_END _u(0x20080000) +#define SRAM_SCRATCH_X_BASE _u(0x20080000) +#define SRAM9_BASE _u(0x20081000) +#define SRAM_SCRATCH_Y_BASE _u(0x20081000) +#define SRAM_END _u(0x20082000) +#define SYSINFO_BASE _u(0x40000000) +#define SYSCFG_BASE _u(0x40008000) +#define CLOCKS_BASE _u(0x40010000) +#define PSM_BASE _u(0x40018000) +#define RESETS_BASE _u(0x40020000) +#define IO_BANK0_BASE _u(0x40028000) +#define IO_QSPI_BASE _u(0x40030000) +#define PADS_BANK0_BASE _u(0x40038000) +#define PADS_QSPI_BASE _u(0x40040000) +#define XOSC_BASE _u(0x40048000) +#define PLL_SYS_BASE _u(0x40050000) +#define PLL_USB_BASE _u(0x40058000) +#define ACCESSCTRL_BASE _u(0x40060000) +#define BUSCTRL_BASE _u(0x40068000) +#define UART0_BASE _u(0x40070000) +#define UART1_BASE _u(0x40078000) +#define SPI0_BASE _u(0x40080000) +#define SPI1_BASE _u(0x40088000) +#define I2C0_BASE _u(0x40090000) +#define I2C1_BASE _u(0x40098000) +#define ADC_BASE _u(0x400a0000) +#define PWM_BASE _u(0x400a8000) +#define TIMER0_BASE _u(0x400b0000) +#define TIMER1_BASE _u(0x400b8000) +#define HSTX_CTRL_BASE _u(0x400c0000) +#define XIP_CTRL_BASE _u(0x400c8000) +#define XIP_QMI_BASE _u(0x400d0000) +#define WATCHDOG_BASE _u(0x400d8000) +#define BOOTRAM_BASE _u(0x400e0000) +#define BOOTRAM_END _u(0x400e0400) +#define ROSC_BASE _u(0x400e8000) +#define TRNG_BASE _u(0x400f0000) +#define SHA256_BASE _u(0x400f8000) +#define POWMAN_BASE _u(0x40100000) +#define TICKS_BASE _u(0x40108000) +#define OTP_BASE _u(0x40120000) +#define OTP_DATA_BASE _u(0x40130000) +#define OTP_DATA_RAW_BASE _u(0x40134000) +#define OTP_DATA_GUARDED_BASE _u(0x40138000) +#define OTP_DATA_RAW_GUARDED_BASE _u(0x4013c000) +#define CORESIGHT_PERIPH_BASE _u(0x40140000) +#define CORESIGHT_ROMTABLE_BASE _u(0x40140000) +#define CORESIGHT_AHB_AP_CORE0_BASE _u(0x40142000) +#define CORESIGHT_AHB_AP_CORE1_BASE _u(0x40144000) +#define CORESIGHT_TIMESTAMP_GEN_BASE _u(0x40146000) +#define CORESIGHT_ATB_FUNNEL_BASE _u(0x40147000) +#define CORESIGHT_TPIU_BASE _u(0x40148000) +#define CORESIGHT_CTI_BASE _u(0x40149000) +#define CORESIGHT_APB_AP_RISCV_BASE _u(0x4014a000) +#define DFT_BASE _u(0x40150000) +#define GLITCH_DETECTOR_BASE _u(0x40158000) +#define TBMAN_BASE _u(0x40160000) +#define DMA_BASE _u(0x50000000) +#define USBCTRL_BASE _u(0x50100000) +#define USBCTRL_DPRAM_BASE _u(0x50100000) +#define USBCTRL_REGS_BASE _u(0x50110000) +#define PIO0_BASE _u(0x50200000) +#define PIO1_BASE _u(0x50300000) +#define PIO2_BASE _u(0x50400000) +#define XIP_AUX_BASE _u(0x50500000) +#define HSTX_FIFO_BASE _u(0x50600000) +#define CORESIGHT_TRACE_BASE _u(0x50700000) +#define SIO_BASE _u(0xd0000000) +#define SIO_NONSEC_BASE _u(0xd0020000) +#define PPB_BASE _u(0xe0000000) +#define PPB_NONSEC_BASE _u(0xe0020000) +#define EPPB_BASE _u(0xe0080000) + +#endif // _ADDRESSMAP_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/bootram.h b/lib/pico-sdk/rp2350/hardware/regs/bootram.h new file mode 100644 index 000000000000..0d8695cb0049 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/bootram.h @@ -0,0 +1,130 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : BOOTRAM +// Version : 1 +// Bus type : apb +// Description : Additional registers mapped adjacent to the bootram, for use +// by the bootrom. +// ============================================================================= +#ifndef _HARDWARE_REGS_BOOTRAM_H +#define _HARDWARE_REGS_BOOTRAM_H +// ============================================================================= +// Register : BOOTRAM_WRITE_ONCE0 +// Description : This registers always ORs writes into its current contents. +// Once a bit is set, it can only be cleared by a reset. +#define BOOTRAM_WRITE_ONCE0_OFFSET _u(0x00000800) +#define BOOTRAM_WRITE_ONCE0_BITS _u(0xffffffff) +#define BOOTRAM_WRITE_ONCE0_RESET _u(0x00000000) +#define BOOTRAM_WRITE_ONCE0_MSB _u(31) +#define BOOTRAM_WRITE_ONCE0_LSB _u(0) +#define BOOTRAM_WRITE_ONCE0_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_WRITE_ONCE1 +// Description : This registers always ORs writes into its current contents. +// Once a bit is set, it can only be cleared by a reset. +#define BOOTRAM_WRITE_ONCE1_OFFSET _u(0x00000804) +#define BOOTRAM_WRITE_ONCE1_BITS _u(0xffffffff) +#define BOOTRAM_WRITE_ONCE1_RESET _u(0x00000000) +#define BOOTRAM_WRITE_ONCE1_MSB _u(31) +#define BOOTRAM_WRITE_ONCE1_LSB _u(0) +#define BOOTRAM_WRITE_ONCE1_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK_STAT +// Description : Bootlock status register. 1=unclaimed, 0=claimed. These locks +// function identically to the SIO spinlocks, but are reserved for +// bootrom use. +#define BOOTRAM_BOOTLOCK_STAT_OFFSET _u(0x00000808) +#define BOOTRAM_BOOTLOCK_STAT_BITS _u(0x000000ff) +#define BOOTRAM_BOOTLOCK_STAT_RESET _u(0x000000ff) +#define BOOTRAM_BOOTLOCK_STAT_MSB _u(7) +#define BOOTRAM_BOOTLOCK_STAT_LSB _u(0) +#define BOOTRAM_BOOTLOCK_STAT_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK0 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK0_OFFSET _u(0x0000080c) +#define BOOTRAM_BOOTLOCK0_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK0_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK0_MSB _u(31) +#define BOOTRAM_BOOTLOCK0_LSB _u(0) +#define BOOTRAM_BOOTLOCK0_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK1 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK1_OFFSET _u(0x00000810) +#define BOOTRAM_BOOTLOCK1_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK1_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK1_MSB _u(31) +#define BOOTRAM_BOOTLOCK1_LSB _u(0) +#define BOOTRAM_BOOTLOCK1_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK2 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK2_OFFSET _u(0x00000814) +#define BOOTRAM_BOOTLOCK2_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK2_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK2_MSB _u(31) +#define BOOTRAM_BOOTLOCK2_LSB _u(0) +#define BOOTRAM_BOOTLOCK2_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK3 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK3_OFFSET _u(0x00000818) +#define BOOTRAM_BOOTLOCK3_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK3_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK3_MSB _u(31) +#define BOOTRAM_BOOTLOCK3_LSB _u(0) +#define BOOTRAM_BOOTLOCK3_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK4 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK4_OFFSET _u(0x0000081c) +#define BOOTRAM_BOOTLOCK4_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK4_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK4_MSB _u(31) +#define BOOTRAM_BOOTLOCK4_LSB _u(0) +#define BOOTRAM_BOOTLOCK4_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK5 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK5_OFFSET _u(0x00000820) +#define BOOTRAM_BOOTLOCK5_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK5_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK5_MSB _u(31) +#define BOOTRAM_BOOTLOCK5_LSB _u(0) +#define BOOTRAM_BOOTLOCK5_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK6 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK6_OFFSET _u(0x00000824) +#define BOOTRAM_BOOTLOCK6_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK6_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK6_MSB _u(31) +#define BOOTRAM_BOOTLOCK6_LSB _u(0) +#define BOOTRAM_BOOTLOCK6_ACCESS "RW" +// ============================================================================= +// Register : BOOTRAM_BOOTLOCK7 +// Description : Read to claim and check. Write to unclaim. The value returned +// on successful claim is 1 << n, and on failed claim is zero. +#define BOOTRAM_BOOTLOCK7_OFFSET _u(0x00000828) +#define BOOTRAM_BOOTLOCK7_BITS _u(0xffffffff) +#define BOOTRAM_BOOTLOCK7_RESET _u(0x00000000) +#define BOOTRAM_BOOTLOCK7_MSB _u(31) +#define BOOTRAM_BOOTLOCK7_LSB _u(0) +#define BOOTRAM_BOOTLOCK7_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_BOOTRAM_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/busctrl.h b/lib/pico-sdk/rp2350/hardware/regs/busctrl.h new file mode 100644 index 000000000000..c3bf3e139e59 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/busctrl.h @@ -0,0 +1,753 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : BUSCTRL +// Version : 1 +// Bus type : apb +// Description : Register block for busfabric control signals and performance +// counters +// ============================================================================= +#ifndef _HARDWARE_REGS_BUSCTRL_H +#define _HARDWARE_REGS_BUSCTRL_H +// ============================================================================= +// Register : BUSCTRL_BUS_PRIORITY +// Description : Set the priority of each master for bus arbitration. +#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000) +#define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111) +#define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_DMA_W +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000) +#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12) +#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12) +#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_DMA_R +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100) +#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8) +#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8) +#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_PROC1 +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010) +#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4) +#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4) +#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : BUSCTRL_BUS_PRIORITY_PROC0 +// Description : 0 - low priority, 1 - high priority +#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0) +#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001) +#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0) +#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0) +#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW" +// ============================================================================= +// Register : BUSCTRL_BUS_PRIORITY_ACK +// Description : Bus priority acknowledge +// Goes to 1 once all arbiters have registered the new global +// priority levels. +// Arbiters update their local priority when servicing a new +// nonsequential access. +// In normal circumstances this will happen almost immediately. +#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004) +#define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001) +#define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000) +#define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0) +#define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0) +#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO" +// ============================================================================= +// Register : BUSCTRL_PERFCTR_EN +// Description : Enable the performance counters. If 0, the performance counters +// do not increment. This can be used to precisely start/stop +// event sampling around the profiled section of code. +// +// The performance counters are initially disabled, to save +// energy. +#define BUSCTRL_PERFCTR_EN_OFFSET _u(0x00000008) +#define BUSCTRL_PERFCTR_EN_BITS _u(0x00000001) +#define BUSCTRL_PERFCTR_EN_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR_EN_MSB _u(0) +#define BUSCTRL_PERFCTR_EN_LSB _u(0) +#define BUSCTRL_PERFCTR_EN_ACCESS "RW" +// ============================================================================= +// Register : BUSCTRL_PERFCTR0 +// Description : Bus fabric performance counter 0 +// Busfabric saturating performance counter 0 +// Count some event signal from the busfabric arbiters, if +// PERFCTR_EN is set. +// Write any value to clear. Select an event to count using +// PERFSEL0 +#define BUSCTRL_PERFCTR0_OFFSET _u(0x0000000c) +#define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR0_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR0_MSB _u(23) +#define BUSCTRL_PERFCTR0_LSB _u(0) +#define BUSCTRL_PERFCTR0_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL0 +// Description : Bus fabric performance event select for PERFCTR0 +// Select an event for PERFCTR0. For each downstream port of the +// main crossbar, four events are available: ACCESS, an access +// took place; ACCESS_CONTESTED, an access took place that +// previously stalled due to contention from other masters; +// STALL_DOWNSTREAM, count cycles where any master stalled due to +// a stall on the downstream bus; STALL_UPSTREAM, count cycles +// where any master stalled for any reason, including contention +// from other masters. +// 0x00 -> siob_proc1_stall_upstream +// 0x01 -> siob_proc1_stall_downstream +// 0x02 -> siob_proc1_access_contested +// 0x03 -> siob_proc1_access +// 0x04 -> siob_proc0_stall_upstream +// 0x05 -> siob_proc0_stall_downstream +// 0x06 -> siob_proc0_access_contested +// 0x07 -> siob_proc0_access +// 0x08 -> apb_stall_upstream +// 0x09 -> apb_stall_downstream +// 0x0a -> apb_access_contested +// 0x0b -> apb_access +// 0x0c -> fastperi_stall_upstream +// 0x0d -> fastperi_stall_downstream +// 0x0e -> fastperi_access_contested +// 0x0f -> fastperi_access +// 0x10 -> sram9_stall_upstream +// 0x11 -> sram9_stall_downstream +// 0x12 -> sram9_access_contested +// 0x13 -> sram9_access +// 0x14 -> sram8_stall_upstream +// 0x15 -> sram8_stall_downstream +// 0x16 -> sram8_access_contested +// 0x17 -> sram8_access +// 0x18 -> sram7_stall_upstream +// 0x19 -> sram7_stall_downstream +// 0x1a -> sram7_access_contested +// 0x1b -> sram7_access +// 0x1c -> sram6_stall_upstream +// 0x1d -> sram6_stall_downstream +// 0x1e -> sram6_access_contested +// 0x1f -> sram6_access +// 0x20 -> sram5_stall_upstream +// 0x21 -> sram5_stall_downstream +// 0x22 -> sram5_access_contested +// 0x23 -> sram5_access +// 0x24 -> sram4_stall_upstream +// 0x25 -> sram4_stall_downstream +// 0x26 -> sram4_access_contested +// 0x27 -> sram4_access +// 0x28 -> sram3_stall_upstream +// 0x29 -> sram3_stall_downstream +// 0x2a -> sram3_access_contested +// 0x2b -> sram3_access +// 0x2c -> sram2_stall_upstream +// 0x2d -> sram2_stall_downstream +// 0x2e -> sram2_access_contested +// 0x2f -> sram2_access +// 0x30 -> sram1_stall_upstream +// 0x31 -> sram1_stall_downstream +// 0x32 -> sram1_access_contested +// 0x33 -> sram1_access +// 0x34 -> sram0_stall_upstream +// 0x35 -> sram0_stall_downstream +// 0x36 -> sram0_access_contested +// 0x37 -> sram0_access +// 0x38 -> xip_main1_stall_upstream +// 0x39 -> xip_main1_stall_downstream +// 0x3a -> xip_main1_access_contested +// 0x3b -> xip_main1_access +// 0x3c -> xip_main0_stall_upstream +// 0x3d -> xip_main0_stall_downstream +// 0x3e -> xip_main0_access_contested +// 0x3f -> xip_main0_access +// 0x40 -> rom_stall_upstream +// 0x41 -> rom_stall_downstream +// 0x42 -> rom_access_contested +// 0x43 -> rom_access +#define BUSCTRL_PERFSEL0_OFFSET _u(0x00000010) +#define BUSCTRL_PERFSEL0_BITS _u(0x0000007f) +#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL0_MSB _u(6) +#define BUSCTRL_PERFSEL0_LSB _u(0) +#define BUSCTRL_PERFSEL0_ACCESS "RW" +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS _u(0x03) +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS _u(0x07) +#define BUSCTRL_PERFSEL0_VALUE_APB_STALL_UPSTREAM _u(0x08) +#define BUSCTRL_PERFSEL0_VALUE_APB_STALL_DOWNSTREAM _u(0x09) +#define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS _u(0x0b) +#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) +#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) +#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_ACCESS _u(0x0f) +#define BUSCTRL_PERFSEL0_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) +#define BUSCTRL_PERFSEL0_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) +#define BUSCTRL_PERFSEL0_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL0_VALUE_SRAM9_ACCESS _u(0x13) +#define BUSCTRL_PERFSEL0_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) +#define BUSCTRL_PERFSEL0_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) +#define BUSCTRL_PERFSEL0_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) +#define BUSCTRL_PERFSEL0_VALUE_SRAM8_ACCESS _u(0x17) +#define BUSCTRL_PERFSEL0_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) +#define BUSCTRL_PERFSEL0_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) +#define BUSCTRL_PERFSEL0_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) +#define BUSCTRL_PERFSEL0_VALUE_SRAM7_ACCESS _u(0x1b) +#define BUSCTRL_PERFSEL0_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) +#define BUSCTRL_PERFSEL0_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) +#define BUSCTRL_PERFSEL0_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) +#define BUSCTRL_PERFSEL0_VALUE_SRAM6_ACCESS _u(0x1f) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) +#define BUSCTRL_PERFSEL0_VALUE_SRAM5_ACCESS _u(0x23) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) +#define BUSCTRL_PERFSEL0_VALUE_SRAM4_ACCESS _u(0x27) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) +#define BUSCTRL_PERFSEL0_VALUE_SRAM3_ACCESS _u(0x2b) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) +#define BUSCTRL_PERFSEL0_VALUE_SRAM2_ACCESS _u(0x2f) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) +#define BUSCTRL_PERFSEL0_VALUE_SRAM1_ACCESS _u(0x33) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) +#define BUSCTRL_PERFSEL0_VALUE_SRAM0_ACCESS _u(0x37) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_ACCESS _u(0x3b) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) +#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_ACCESS _u(0x3f) +#define BUSCTRL_PERFSEL0_VALUE_ROM_STALL_UPSTREAM _u(0x40) +#define BUSCTRL_PERFSEL0_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) +#define BUSCTRL_PERFSEL0_VALUE_ROM_ACCESS_CONTESTED _u(0x42) +#define BUSCTRL_PERFSEL0_VALUE_ROM_ACCESS _u(0x43) +// ============================================================================= +// Register : BUSCTRL_PERFCTR1 +// Description : Bus fabric performance counter 1 +// Busfabric saturating performance counter 1 +// Count some event signal from the busfabric arbiters, if +// PERFCTR_EN is set. +// Write any value to clear. Select an event to count using +// PERFSEL1 +#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000014) +#define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR1_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR1_MSB _u(23) +#define BUSCTRL_PERFCTR1_LSB _u(0) +#define BUSCTRL_PERFCTR1_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL1 +// Description : Bus fabric performance event select for PERFCTR1 +// Select an event for PERFCTR1. For each downstream port of the +// main crossbar, four events are available: ACCESS, an access +// took place; ACCESS_CONTESTED, an access took place that +// previously stalled due to contention from other masters; +// STALL_DOWNSTREAM, count cycles where any master stalled due to +// a stall on the downstream bus; STALL_UPSTREAM, count cycles +// where any master stalled for any reason, including contention +// from other masters. +// 0x00 -> siob_proc1_stall_upstream +// 0x01 -> siob_proc1_stall_downstream +// 0x02 -> siob_proc1_access_contested +// 0x03 -> siob_proc1_access +// 0x04 -> siob_proc0_stall_upstream +// 0x05 -> siob_proc0_stall_downstream +// 0x06 -> siob_proc0_access_contested +// 0x07 -> siob_proc0_access +// 0x08 -> apb_stall_upstream +// 0x09 -> apb_stall_downstream +// 0x0a -> apb_access_contested +// 0x0b -> apb_access +// 0x0c -> fastperi_stall_upstream +// 0x0d -> fastperi_stall_downstream +// 0x0e -> fastperi_access_contested +// 0x0f -> fastperi_access +// 0x10 -> sram9_stall_upstream +// 0x11 -> sram9_stall_downstream +// 0x12 -> sram9_access_contested +// 0x13 -> sram9_access +// 0x14 -> sram8_stall_upstream +// 0x15 -> sram8_stall_downstream +// 0x16 -> sram8_access_contested +// 0x17 -> sram8_access +// 0x18 -> sram7_stall_upstream +// 0x19 -> sram7_stall_downstream +// 0x1a -> sram7_access_contested +// 0x1b -> sram7_access +// 0x1c -> sram6_stall_upstream +// 0x1d -> sram6_stall_downstream +// 0x1e -> sram6_access_contested +// 0x1f -> sram6_access +// 0x20 -> sram5_stall_upstream +// 0x21 -> sram5_stall_downstream +// 0x22 -> sram5_access_contested +// 0x23 -> sram5_access +// 0x24 -> sram4_stall_upstream +// 0x25 -> sram4_stall_downstream +// 0x26 -> sram4_access_contested +// 0x27 -> sram4_access +// 0x28 -> sram3_stall_upstream +// 0x29 -> sram3_stall_downstream +// 0x2a -> sram3_access_contested +// 0x2b -> sram3_access +// 0x2c -> sram2_stall_upstream +// 0x2d -> sram2_stall_downstream +// 0x2e -> sram2_access_contested +// 0x2f -> sram2_access +// 0x30 -> sram1_stall_upstream +// 0x31 -> sram1_stall_downstream +// 0x32 -> sram1_access_contested +// 0x33 -> sram1_access +// 0x34 -> sram0_stall_upstream +// 0x35 -> sram0_stall_downstream +// 0x36 -> sram0_access_contested +// 0x37 -> sram0_access +// 0x38 -> xip_main1_stall_upstream +// 0x39 -> xip_main1_stall_downstream +// 0x3a -> xip_main1_access_contested +// 0x3b -> xip_main1_access +// 0x3c -> xip_main0_stall_upstream +// 0x3d -> xip_main0_stall_downstream +// 0x3e -> xip_main0_access_contested +// 0x3f -> xip_main0_access +// 0x40 -> rom_stall_upstream +// 0x41 -> rom_stall_downstream +// 0x42 -> rom_access_contested +// 0x43 -> rom_access +#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000018) +#define BUSCTRL_PERFSEL1_BITS _u(0x0000007f) +#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL1_MSB _u(6) +#define BUSCTRL_PERFSEL1_LSB _u(0) +#define BUSCTRL_PERFSEL1_ACCESS "RW" +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS _u(0x03) +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS _u(0x07) +#define BUSCTRL_PERFSEL1_VALUE_APB_STALL_UPSTREAM _u(0x08) +#define BUSCTRL_PERFSEL1_VALUE_APB_STALL_DOWNSTREAM _u(0x09) +#define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS _u(0x0b) +#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) +#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) +#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_ACCESS _u(0x0f) +#define BUSCTRL_PERFSEL1_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) +#define BUSCTRL_PERFSEL1_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) +#define BUSCTRL_PERFSEL1_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL1_VALUE_SRAM9_ACCESS _u(0x13) +#define BUSCTRL_PERFSEL1_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) +#define BUSCTRL_PERFSEL1_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) +#define BUSCTRL_PERFSEL1_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) +#define BUSCTRL_PERFSEL1_VALUE_SRAM8_ACCESS _u(0x17) +#define BUSCTRL_PERFSEL1_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) +#define BUSCTRL_PERFSEL1_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) +#define BUSCTRL_PERFSEL1_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) +#define BUSCTRL_PERFSEL1_VALUE_SRAM7_ACCESS _u(0x1b) +#define BUSCTRL_PERFSEL1_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) +#define BUSCTRL_PERFSEL1_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) +#define BUSCTRL_PERFSEL1_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) +#define BUSCTRL_PERFSEL1_VALUE_SRAM6_ACCESS _u(0x1f) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) +#define BUSCTRL_PERFSEL1_VALUE_SRAM5_ACCESS _u(0x23) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) +#define BUSCTRL_PERFSEL1_VALUE_SRAM4_ACCESS _u(0x27) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) +#define BUSCTRL_PERFSEL1_VALUE_SRAM3_ACCESS _u(0x2b) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) +#define BUSCTRL_PERFSEL1_VALUE_SRAM2_ACCESS _u(0x2f) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) +#define BUSCTRL_PERFSEL1_VALUE_SRAM1_ACCESS _u(0x33) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) +#define BUSCTRL_PERFSEL1_VALUE_SRAM0_ACCESS _u(0x37) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_ACCESS _u(0x3b) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) +#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_ACCESS _u(0x3f) +#define BUSCTRL_PERFSEL1_VALUE_ROM_STALL_UPSTREAM _u(0x40) +#define BUSCTRL_PERFSEL1_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) +#define BUSCTRL_PERFSEL1_VALUE_ROM_ACCESS_CONTESTED _u(0x42) +#define BUSCTRL_PERFSEL1_VALUE_ROM_ACCESS _u(0x43) +// ============================================================================= +// Register : BUSCTRL_PERFCTR2 +// Description : Bus fabric performance counter 2 +// Busfabric saturating performance counter 2 +// Count some event signal from the busfabric arbiters, if +// PERFCTR_EN is set. +// Write any value to clear. Select an event to count using +// PERFSEL2 +#define BUSCTRL_PERFCTR2_OFFSET _u(0x0000001c) +#define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR2_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR2_MSB _u(23) +#define BUSCTRL_PERFCTR2_LSB _u(0) +#define BUSCTRL_PERFCTR2_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL2 +// Description : Bus fabric performance event select for PERFCTR2 +// Select an event for PERFCTR2. For each downstream port of the +// main crossbar, four events are available: ACCESS, an access +// took place; ACCESS_CONTESTED, an access took place that +// previously stalled due to contention from other masters; +// STALL_DOWNSTREAM, count cycles where any master stalled due to +// a stall on the downstream bus; STALL_UPSTREAM, count cycles +// where any master stalled for any reason, including contention +// from other masters. +// 0x00 -> siob_proc1_stall_upstream +// 0x01 -> siob_proc1_stall_downstream +// 0x02 -> siob_proc1_access_contested +// 0x03 -> siob_proc1_access +// 0x04 -> siob_proc0_stall_upstream +// 0x05 -> siob_proc0_stall_downstream +// 0x06 -> siob_proc0_access_contested +// 0x07 -> siob_proc0_access +// 0x08 -> apb_stall_upstream +// 0x09 -> apb_stall_downstream +// 0x0a -> apb_access_contested +// 0x0b -> apb_access +// 0x0c -> fastperi_stall_upstream +// 0x0d -> fastperi_stall_downstream +// 0x0e -> fastperi_access_contested +// 0x0f -> fastperi_access +// 0x10 -> sram9_stall_upstream +// 0x11 -> sram9_stall_downstream +// 0x12 -> sram9_access_contested +// 0x13 -> sram9_access +// 0x14 -> sram8_stall_upstream +// 0x15 -> sram8_stall_downstream +// 0x16 -> sram8_access_contested +// 0x17 -> sram8_access +// 0x18 -> sram7_stall_upstream +// 0x19 -> sram7_stall_downstream +// 0x1a -> sram7_access_contested +// 0x1b -> sram7_access +// 0x1c -> sram6_stall_upstream +// 0x1d -> sram6_stall_downstream +// 0x1e -> sram6_access_contested +// 0x1f -> sram6_access +// 0x20 -> sram5_stall_upstream +// 0x21 -> sram5_stall_downstream +// 0x22 -> sram5_access_contested +// 0x23 -> sram5_access +// 0x24 -> sram4_stall_upstream +// 0x25 -> sram4_stall_downstream +// 0x26 -> sram4_access_contested +// 0x27 -> sram4_access +// 0x28 -> sram3_stall_upstream +// 0x29 -> sram3_stall_downstream +// 0x2a -> sram3_access_contested +// 0x2b -> sram3_access +// 0x2c -> sram2_stall_upstream +// 0x2d -> sram2_stall_downstream +// 0x2e -> sram2_access_contested +// 0x2f -> sram2_access +// 0x30 -> sram1_stall_upstream +// 0x31 -> sram1_stall_downstream +// 0x32 -> sram1_access_contested +// 0x33 -> sram1_access +// 0x34 -> sram0_stall_upstream +// 0x35 -> sram0_stall_downstream +// 0x36 -> sram0_access_contested +// 0x37 -> sram0_access +// 0x38 -> xip_main1_stall_upstream +// 0x39 -> xip_main1_stall_downstream +// 0x3a -> xip_main1_access_contested +// 0x3b -> xip_main1_access +// 0x3c -> xip_main0_stall_upstream +// 0x3d -> xip_main0_stall_downstream +// 0x3e -> xip_main0_access_contested +// 0x3f -> xip_main0_access +// 0x40 -> rom_stall_upstream +// 0x41 -> rom_stall_downstream +// 0x42 -> rom_access_contested +// 0x43 -> rom_access +#define BUSCTRL_PERFSEL2_OFFSET _u(0x00000020) +#define BUSCTRL_PERFSEL2_BITS _u(0x0000007f) +#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL2_MSB _u(6) +#define BUSCTRL_PERFSEL2_LSB _u(0) +#define BUSCTRL_PERFSEL2_ACCESS "RW" +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS _u(0x03) +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS _u(0x07) +#define BUSCTRL_PERFSEL2_VALUE_APB_STALL_UPSTREAM _u(0x08) +#define BUSCTRL_PERFSEL2_VALUE_APB_STALL_DOWNSTREAM _u(0x09) +#define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS _u(0x0b) +#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) +#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) +#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_ACCESS _u(0x0f) +#define BUSCTRL_PERFSEL2_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) +#define BUSCTRL_PERFSEL2_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) +#define BUSCTRL_PERFSEL2_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL2_VALUE_SRAM9_ACCESS _u(0x13) +#define BUSCTRL_PERFSEL2_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) +#define BUSCTRL_PERFSEL2_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) +#define BUSCTRL_PERFSEL2_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) +#define BUSCTRL_PERFSEL2_VALUE_SRAM8_ACCESS _u(0x17) +#define BUSCTRL_PERFSEL2_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) +#define BUSCTRL_PERFSEL2_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) +#define BUSCTRL_PERFSEL2_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) +#define BUSCTRL_PERFSEL2_VALUE_SRAM7_ACCESS _u(0x1b) +#define BUSCTRL_PERFSEL2_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) +#define BUSCTRL_PERFSEL2_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) +#define BUSCTRL_PERFSEL2_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) +#define BUSCTRL_PERFSEL2_VALUE_SRAM6_ACCESS _u(0x1f) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) +#define BUSCTRL_PERFSEL2_VALUE_SRAM5_ACCESS _u(0x23) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) +#define BUSCTRL_PERFSEL2_VALUE_SRAM4_ACCESS _u(0x27) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) +#define BUSCTRL_PERFSEL2_VALUE_SRAM3_ACCESS _u(0x2b) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) +#define BUSCTRL_PERFSEL2_VALUE_SRAM2_ACCESS _u(0x2f) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) +#define BUSCTRL_PERFSEL2_VALUE_SRAM1_ACCESS _u(0x33) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) +#define BUSCTRL_PERFSEL2_VALUE_SRAM0_ACCESS _u(0x37) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_ACCESS _u(0x3b) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) +#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_ACCESS _u(0x3f) +#define BUSCTRL_PERFSEL2_VALUE_ROM_STALL_UPSTREAM _u(0x40) +#define BUSCTRL_PERFSEL2_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) +#define BUSCTRL_PERFSEL2_VALUE_ROM_ACCESS_CONTESTED _u(0x42) +#define BUSCTRL_PERFSEL2_VALUE_ROM_ACCESS _u(0x43) +// ============================================================================= +// Register : BUSCTRL_PERFCTR3 +// Description : Bus fabric performance counter 3 +// Busfabric saturating performance counter 3 +// Count some event signal from the busfabric arbiters, if +// PERFCTR_EN is set. +// Write any value to clear. Select an event to count using +// PERFSEL3 +#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000024) +#define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff) +#define BUSCTRL_PERFCTR3_RESET _u(0x00000000) +#define BUSCTRL_PERFCTR3_MSB _u(23) +#define BUSCTRL_PERFCTR3_LSB _u(0) +#define BUSCTRL_PERFCTR3_ACCESS "WC" +// ============================================================================= +// Register : BUSCTRL_PERFSEL3 +// Description : Bus fabric performance event select for PERFCTR3 +// Select an event for PERFCTR3. For each downstream port of the +// main crossbar, four events are available: ACCESS, an access +// took place; ACCESS_CONTESTED, an access took place that +// previously stalled due to contention from other masters; +// STALL_DOWNSTREAM, count cycles where any master stalled due to +// a stall on the downstream bus; STALL_UPSTREAM, count cycles +// where any master stalled for any reason, including contention +// from other masters. +// 0x00 -> siob_proc1_stall_upstream +// 0x01 -> siob_proc1_stall_downstream +// 0x02 -> siob_proc1_access_contested +// 0x03 -> siob_proc1_access +// 0x04 -> siob_proc0_stall_upstream +// 0x05 -> siob_proc0_stall_downstream +// 0x06 -> siob_proc0_access_contested +// 0x07 -> siob_proc0_access +// 0x08 -> apb_stall_upstream +// 0x09 -> apb_stall_downstream +// 0x0a -> apb_access_contested +// 0x0b -> apb_access +// 0x0c -> fastperi_stall_upstream +// 0x0d -> fastperi_stall_downstream +// 0x0e -> fastperi_access_contested +// 0x0f -> fastperi_access +// 0x10 -> sram9_stall_upstream +// 0x11 -> sram9_stall_downstream +// 0x12 -> sram9_access_contested +// 0x13 -> sram9_access +// 0x14 -> sram8_stall_upstream +// 0x15 -> sram8_stall_downstream +// 0x16 -> sram8_access_contested +// 0x17 -> sram8_access +// 0x18 -> sram7_stall_upstream +// 0x19 -> sram7_stall_downstream +// 0x1a -> sram7_access_contested +// 0x1b -> sram7_access +// 0x1c -> sram6_stall_upstream +// 0x1d -> sram6_stall_downstream +// 0x1e -> sram6_access_contested +// 0x1f -> sram6_access +// 0x20 -> sram5_stall_upstream +// 0x21 -> sram5_stall_downstream +// 0x22 -> sram5_access_contested +// 0x23 -> sram5_access +// 0x24 -> sram4_stall_upstream +// 0x25 -> sram4_stall_downstream +// 0x26 -> sram4_access_contested +// 0x27 -> sram4_access +// 0x28 -> sram3_stall_upstream +// 0x29 -> sram3_stall_downstream +// 0x2a -> sram3_access_contested +// 0x2b -> sram3_access +// 0x2c -> sram2_stall_upstream +// 0x2d -> sram2_stall_downstream +// 0x2e -> sram2_access_contested +// 0x2f -> sram2_access +// 0x30 -> sram1_stall_upstream +// 0x31 -> sram1_stall_downstream +// 0x32 -> sram1_access_contested +// 0x33 -> sram1_access +// 0x34 -> sram0_stall_upstream +// 0x35 -> sram0_stall_downstream +// 0x36 -> sram0_access_contested +// 0x37 -> sram0_access +// 0x38 -> xip_main1_stall_upstream +// 0x39 -> xip_main1_stall_downstream +// 0x3a -> xip_main1_access_contested +// 0x3b -> xip_main1_access +// 0x3c -> xip_main0_stall_upstream +// 0x3d -> xip_main0_stall_downstream +// 0x3e -> xip_main0_access_contested +// 0x3f -> xip_main0_access +// 0x40 -> rom_stall_upstream +// 0x41 -> rom_stall_downstream +// 0x42 -> rom_access_contested +// 0x43 -> rom_access +#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000028) +#define BUSCTRL_PERFSEL3_BITS _u(0x0000007f) +#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f) +#define BUSCTRL_PERFSEL3_MSB _u(6) +#define BUSCTRL_PERFSEL3_LSB _u(0) +#define BUSCTRL_PERFSEL3_ACCESS "RW" +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00) +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01) +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02) +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS _u(0x03) +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04) +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05) +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06) +#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS _u(0x07) +#define BUSCTRL_PERFSEL3_VALUE_APB_STALL_UPSTREAM _u(0x08) +#define BUSCTRL_PERFSEL3_VALUE_APB_STALL_DOWNSTREAM _u(0x09) +#define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS_CONTESTED _u(0x0a) +#define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS _u(0x0b) +#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c) +#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d) +#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e) +#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_ACCESS _u(0x0f) +#define BUSCTRL_PERFSEL3_VALUE_SRAM9_STALL_UPSTREAM _u(0x10) +#define BUSCTRL_PERFSEL3_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11) +#define BUSCTRL_PERFSEL3_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12) +#define BUSCTRL_PERFSEL3_VALUE_SRAM9_ACCESS _u(0x13) +#define BUSCTRL_PERFSEL3_VALUE_SRAM8_STALL_UPSTREAM _u(0x14) +#define BUSCTRL_PERFSEL3_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15) +#define BUSCTRL_PERFSEL3_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16) +#define BUSCTRL_PERFSEL3_VALUE_SRAM8_ACCESS _u(0x17) +#define BUSCTRL_PERFSEL3_VALUE_SRAM7_STALL_UPSTREAM _u(0x18) +#define BUSCTRL_PERFSEL3_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19) +#define BUSCTRL_PERFSEL3_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a) +#define BUSCTRL_PERFSEL3_VALUE_SRAM7_ACCESS _u(0x1b) +#define BUSCTRL_PERFSEL3_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c) +#define BUSCTRL_PERFSEL3_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d) +#define BUSCTRL_PERFSEL3_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e) +#define BUSCTRL_PERFSEL3_VALUE_SRAM6_ACCESS _u(0x1f) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5_STALL_UPSTREAM _u(0x20) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22) +#define BUSCTRL_PERFSEL3_VALUE_SRAM5_ACCESS _u(0x23) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4_STALL_UPSTREAM _u(0x24) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26) +#define BUSCTRL_PERFSEL3_VALUE_SRAM4_ACCESS _u(0x27) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3_STALL_UPSTREAM _u(0x28) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a) +#define BUSCTRL_PERFSEL3_VALUE_SRAM3_ACCESS _u(0x2b) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e) +#define BUSCTRL_PERFSEL3_VALUE_SRAM2_ACCESS _u(0x2f) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1_STALL_UPSTREAM _u(0x30) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32) +#define BUSCTRL_PERFSEL3_VALUE_SRAM1_ACCESS _u(0x33) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0_STALL_UPSTREAM _u(0x34) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36) +#define BUSCTRL_PERFSEL3_VALUE_SRAM0_ACCESS _u(0x37) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_ACCESS _u(0x3b) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e) +#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_ACCESS _u(0x3f) +#define BUSCTRL_PERFSEL3_VALUE_ROM_STALL_UPSTREAM _u(0x40) +#define BUSCTRL_PERFSEL3_VALUE_ROM_STALL_DOWNSTREAM _u(0x41) +#define BUSCTRL_PERFSEL3_VALUE_ROM_ACCESS_CONTESTED _u(0x42) +#define BUSCTRL_PERFSEL3_VALUE_ROM_ACCESS _u(0x43) +// ============================================================================= +#endif // _HARDWARE_REGS_BUSCTRL_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/clocks.h b/lib/pico-sdk/rp2350/hardware/regs/clocks.h new file mode 100644 index 000000000000..fd560c9102c6 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/clocks.h @@ -0,0 +1,2764 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : CLOCKS +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_CLOCKS_H +#define _HARDWARE_REGS_CLOCKS_H +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT0_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT0_CTRL_OFFSET _u(0x00000000) +#define CLOCKS_CLK_GPOUT0_CTRL_BITS _u(0x10131de0) +#define CLOCKS_CLK_GPOUT0_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB _u(20) +#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB _u(16) +#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors, can be changed +// on-the-fly +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB _u(12) +#define CLOCKS_CLK_GPOUT0_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_GPOUT0_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> clksrc_pll_usb_primary_ref_opcg +// 0x5 -> rosc_clksrc +// 0x6 -> xosc_clksrc +// 0x7 -> lposc_clksrc +// 0x8 -> clk_sys +// 0x9 -> clk_usb +// 0xa -> clk_adc +// 0xb -> clk_ref +// 0xc -> clk_peri +// 0xd -> clk_hstx +// 0xe -> otp_clk2fc +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x4) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x6) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC _u(0x7) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x8) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB _u(0x9) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC _u(0xa) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF _u(0xb) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_PERI _u(0xc) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_HSTX _u(0xd) +#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_OTP_CLK2FC _u(0xe) +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT0_DIV +#define CLOCKS_CLK_GPOUT0_DIV_OFFSET _u(0x00000004) +#define CLOCKS_CLK_GPOUT0_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT0_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_GPOUT0_DIV_INT_RESET _u(0x0001) +#define CLOCKS_CLK_GPOUT0_DIV_INT_BITS _u(0xffff0000) +#define CLOCKS_CLK_GPOUT0_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT0_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_GPOUT0_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT0_DIV_FRAC +// Description : Fractional component of the divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET _u(0x0000) +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS _u(0x0000ffff) +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB _u(15) +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB _u(0) +#define CLOCKS_CLK_GPOUT0_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT0_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET _u(0x00000008) +#define CLOCKS_CLK_GPOUT0_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_GPOUT0_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT0_SELECTED_MSB _u(0) +#define CLOCKS_CLK_GPOUT0_SELECTED_LSB _u(0) +#define CLOCKS_CLK_GPOUT0_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT1_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT1_CTRL_OFFSET _u(0x0000000c) +#define CLOCKS_CLK_GPOUT1_CTRL_BITS _u(0x10131de0) +#define CLOCKS_CLK_GPOUT1_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB _u(20) +#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB _u(16) +#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors, can be changed +// on-the-fly +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB _u(12) +#define CLOCKS_CLK_GPOUT1_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_GPOUT1_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> clksrc_pll_usb_primary_ref_opcg +// 0x5 -> rosc_clksrc +// 0x6 -> xosc_clksrc +// 0x7 -> lposc_clksrc +// 0x8 -> clk_sys +// 0x9 -> clk_usb +// 0xa -> clk_adc +// 0xb -> clk_ref +// 0xc -> clk_peri +// 0xd -> clk_hstx +// 0xe -> otp_clk2fc +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x4) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x5) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x6) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC _u(0x7) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x8) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB _u(0x9) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC _u(0xa) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF _u(0xb) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_PERI _u(0xc) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_HSTX _u(0xd) +#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_OTP_CLK2FC _u(0xe) +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT1_DIV +#define CLOCKS_CLK_GPOUT1_DIV_OFFSET _u(0x00000010) +#define CLOCKS_CLK_GPOUT1_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT1_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_GPOUT1_DIV_INT_RESET _u(0x0001) +#define CLOCKS_CLK_GPOUT1_DIV_INT_BITS _u(0xffff0000) +#define CLOCKS_CLK_GPOUT1_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT1_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_GPOUT1_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT1_DIV_FRAC +// Description : Fractional component of the divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET _u(0x0000) +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS _u(0x0000ffff) +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB _u(15) +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB _u(0) +#define CLOCKS_CLK_GPOUT1_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT1_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET _u(0x00000014) +#define CLOCKS_CLK_GPOUT1_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_GPOUT1_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT1_SELECTED_MSB _u(0) +#define CLOCKS_CLK_GPOUT1_SELECTED_LSB _u(0) +#define CLOCKS_CLK_GPOUT1_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT2_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT2_CTRL_OFFSET _u(0x00000018) +#define CLOCKS_CLK_GPOUT2_CTRL_BITS _u(0x10131de0) +#define CLOCKS_CLK_GPOUT2_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB _u(20) +#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB _u(16) +#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors, can be changed +// on-the-fly +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB _u(12) +#define CLOCKS_CLK_GPOUT2_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_GPOUT2_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> clksrc_pll_usb_primary_ref_opcg +// 0x5 -> rosc_clksrc_ph +// 0x6 -> xosc_clksrc +// 0x7 -> lposc_clksrc +// 0x8 -> clk_sys +// 0x9 -> clk_usb +// 0xa -> clk_adc +// 0xb -> clk_ref +// 0xc -> clk_peri +// 0xd -> clk_hstx +// 0xe -> otp_clk2fc +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x4) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x5) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x6) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC _u(0x7) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x8) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB _u(0x9) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC _u(0xa) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF _u(0xb) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_PERI _u(0xc) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_HSTX _u(0xd) +#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_OTP_CLK2FC _u(0xe) +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT2_DIV +#define CLOCKS_CLK_GPOUT2_DIV_OFFSET _u(0x0000001c) +#define CLOCKS_CLK_GPOUT2_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT2_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_GPOUT2_DIV_INT_RESET _u(0x0001) +#define CLOCKS_CLK_GPOUT2_DIV_INT_BITS _u(0xffff0000) +#define CLOCKS_CLK_GPOUT2_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT2_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_GPOUT2_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT2_DIV_FRAC +// Description : Fractional component of the divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET _u(0x0000) +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS _u(0x0000ffff) +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB _u(15) +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB _u(0) +#define CLOCKS_CLK_GPOUT2_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT2_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET _u(0x00000020) +#define CLOCKS_CLK_GPOUT2_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_GPOUT2_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT2_SELECTED_MSB _u(0) +#define CLOCKS_CLK_GPOUT2_SELECTED_LSB _u(0) +#define CLOCKS_CLK_GPOUT2_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT3_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_GPOUT3_CTRL_OFFSET _u(0x00000024) +#define CLOCKS_CLK_GPOUT3_CTRL_BITS _u(0x10131de0) +#define CLOCKS_CLK_GPOUT3_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB _u(20) +#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB _u(16) +#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_DC50 +// Description : Enables duty cycle correction for odd divisors, can be changed +// on-the-fly +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS _u(0x00001000) +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB _u(12) +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB _u(12) +#define CLOCKS_CLK_GPOUT3_CTRL_DC50_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_GPOUT3_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb +// 0x4 -> clksrc_pll_usb_primary_ref_opcg +// 0x5 -> rosc_clksrc_ph +// 0x6 -> xosc_clksrc +// 0x7 -> lposc_clksrc +// 0x8 -> clk_sys +// 0x9 -> clk_usb +// 0xa -> clk_adc +// 0xb -> clk_ref +// 0xc -> clk_peri +// 0xd -> clk_hstx +// 0xe -> otp_clk2fc +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS _u(0x000001e0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB _u(8) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x4) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x5) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x6) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_LPOSC_CLKSRC _u(0x7) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x8) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB _u(0x9) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC _u(0xa) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF _u(0xb) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_PERI _u(0xc) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_HSTX _u(0xd) +#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_OTP_CLK2FC _u(0xe) +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT3_DIV +#define CLOCKS_CLK_GPOUT3_DIV_OFFSET _u(0x00000028) +#define CLOCKS_CLK_GPOUT3_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_GPOUT3_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_GPOUT3_DIV_INT_RESET _u(0x0001) +#define CLOCKS_CLK_GPOUT3_DIV_INT_BITS _u(0xffff0000) +#define CLOCKS_CLK_GPOUT3_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_GPOUT3_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_GPOUT3_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_GPOUT3_DIV_FRAC +// Description : Fractional component of the divisor, can be changed on-the-fly +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET _u(0x0000) +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS _u(0x0000ffff) +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB _u(15) +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB _u(0) +#define CLOCKS_CLK_GPOUT3_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_GPOUT3_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET _u(0x0000002c) +#define CLOCKS_CLK_GPOUT3_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_GPOUT3_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_GPOUT3_SELECTED_MSB _u(0) +#define CLOCKS_CLK_GPOUT3_SELECTED_LSB _u(0) +#define CLOCKS_CLK_GPOUT3_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_REF_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_REF_CTRL_OFFSET _u(0x00000030) +#define CLOCKS_CLK_REF_CTRL_BITS _u(0x00000063) +#define CLOCKS_CLK_REF_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_REF_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_usb +// 0x1 -> clksrc_gpin0 +// 0x2 -> clksrc_gpin1 +// 0x3 -> clksrc_pll_usb_primary_ref_opcg +#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS _u(0x00000060) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB _u(6) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2) +#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB_PRIMARY_REF_OPCG _u(0x3) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_REF_CTRL_SRC +// Description : Selects the clock source glitchlessly, can be changed on-the- +// fly +// 0x0 -> rosc_clksrc_ph +// 0x1 -> clksrc_clk_ref_aux +// 0x2 -> xosc_clksrc +// 0x3 -> lposc_clksrc +#define CLOCKS_CLK_REF_CTRL_SRC_RESET "-" +#define CLOCKS_CLK_REF_CTRL_SRC_BITS _u(0x00000003) +#define CLOCKS_CLK_REF_CTRL_SRC_MSB _u(1) +#define CLOCKS_CLK_REF_CTRL_SRC_LSB _u(0) +#define CLOCKS_CLK_REF_CTRL_SRC_ACCESS "RW" +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH _u(0x0) +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX _u(0x1) +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC _u(0x2) +#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_LPOSC_CLKSRC _u(0x3) +// ============================================================================= +// Register : CLOCKS_CLK_REF_DIV +#define CLOCKS_CLK_REF_DIV_OFFSET _u(0x00000034) +#define CLOCKS_CLK_REF_DIV_BITS _u(0x00ff0000) +#define CLOCKS_CLK_REF_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_REF_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_REF_DIV_INT_RESET _u(0x01) +#define CLOCKS_CLK_REF_DIV_INT_BITS _u(0x00ff0000) +#define CLOCKS_CLK_REF_DIV_INT_MSB _u(23) +#define CLOCKS_CLK_REF_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_REF_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_REF_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// The glitchless multiplexer does not switch instantaneously (to +// avoid glitches), so software should poll this register to wait +// for the switch to complete. This register contains one decoded +// bit for each of the clock sources enumerated in the CTRL SRC +// field. At most one of these bits will be set at any time, +// indicating that clock is currently present at the output of the +// glitchless mux. Whilst switching is in progress, this register +// may briefly show all-0s. +#define CLOCKS_CLK_REF_SELECTED_OFFSET _u(0x00000038) +#define CLOCKS_CLK_REF_SELECTED_BITS _u(0x0000000f) +#define CLOCKS_CLK_REF_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_REF_SELECTED_MSB _u(3) +#define CLOCKS_CLK_REF_SELECTED_LSB _u(0) +#define CLOCKS_CLK_REF_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_SYS_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_SYS_CTRL_OFFSET _u(0x0000003c) +#define CLOCKS_CLK_SYS_CTRL_BITS _u(0x000000e1) +#define CLOCKS_CLK_SYS_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_sys +// 0x1 -> clksrc_pll_usb +// 0x2 -> rosc_clksrc +// 0x3 -> xosc_clksrc +// 0x4 -> clksrc_gpin0 +// 0x5 -> clksrc_gpin1 +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x1) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x2) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_CTRL_SRC +// Description : Selects the clock source glitchlessly, can be changed on-the- +// fly +// 0x0 -> clk_ref +// 0x1 -> clksrc_clk_sys_aux +#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _u(0x00000001) +#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _u(0) +#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _u(0) +#define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS "RW" +#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF _u(0x0) +#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX _u(0x1) +// ============================================================================= +// Register : CLOCKS_CLK_SYS_DIV +#define CLOCKS_CLK_SYS_DIV_OFFSET _u(0x00000040) +#define CLOCKS_CLK_SYS_DIV_BITS _u(0xffffffff) +#define CLOCKS_CLK_SYS_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_SYS_DIV_INT_RESET _u(0x0001) +#define CLOCKS_CLK_SYS_DIV_INT_BITS _u(0xffff0000) +#define CLOCKS_CLK_SYS_DIV_INT_MSB _u(31) +#define CLOCKS_CLK_SYS_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_SYS_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_DIV_FRAC +// Description : Fractional component of the divisor, can be changed on-the-fly +#define CLOCKS_CLK_SYS_DIV_FRAC_RESET _u(0x0000) +#define CLOCKS_CLK_SYS_DIV_FRAC_BITS _u(0x0000ffff) +#define CLOCKS_CLK_SYS_DIV_FRAC_MSB _u(15) +#define CLOCKS_CLK_SYS_DIV_FRAC_LSB _u(0) +#define CLOCKS_CLK_SYS_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_SYS_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// The glitchless multiplexer does not switch instantaneously (to +// avoid glitches), so software should poll this register to wait +// for the switch to complete. This register contains one decoded +// bit for each of the clock sources enumerated in the CTRL SRC +// field. At most one of these bits will be set at any time, +// indicating that clock is currently present at the output of the +// glitchless mux. Whilst switching is in progress, this register +// may briefly show all-0s. +#define CLOCKS_CLK_SYS_SELECTED_OFFSET _u(0x00000044) +#define CLOCKS_CLK_SYS_SELECTED_BITS _u(0x00000003) +#define CLOCKS_CLK_SYS_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_SYS_SELECTED_MSB _u(1) +#define CLOCKS_CLK_SYS_SELECTED_LSB _u(0) +#define CLOCKS_CLK_SYS_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_PERI_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_PERI_CTRL_OFFSET _u(0x00000048) +#define CLOCKS_CLK_PERI_CTRL_BITS _u(0x10000ce0) +#define CLOCKS_CLK_PERI_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_PERI_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_PERI_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_PERI_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_PERI_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_PERI_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_PERI_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_PERI_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_PERI_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_PERI_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clk_sys +// 0x1 -> clksrc_pll_sys +// 0x2 -> clksrc_pll_usb +// 0x3 -> rosc_clksrc_ph +// 0x4 -> xosc_clksrc +// 0x5 -> clksrc_gpin0 +// 0x6 -> clksrc_gpin1 +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x3) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x4) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x5) +#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x6) +// ============================================================================= +// Register : CLOCKS_CLK_PERI_DIV +#define CLOCKS_CLK_PERI_DIV_OFFSET _u(0x0000004c) +#define CLOCKS_CLK_PERI_DIV_BITS _u(0x00030000) +#define CLOCKS_CLK_PERI_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_PERI_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_PERI_DIV_INT_RESET _u(0x1) +#define CLOCKS_CLK_PERI_DIV_INT_BITS _u(0x00030000) +#define CLOCKS_CLK_PERI_DIV_INT_MSB _u(17) +#define CLOCKS_CLK_PERI_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_PERI_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_PERI_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_PERI_SELECTED_OFFSET _u(0x00000050) +#define CLOCKS_CLK_PERI_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_PERI_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_PERI_SELECTED_MSB _u(0) +#define CLOCKS_CLK_PERI_SELECTED_LSB _u(0) +#define CLOCKS_CLK_PERI_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_HSTX_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_HSTX_CTRL_OFFSET _u(0x00000054) +#define CLOCKS_CLK_HSTX_CTRL_BITS _u(0x10130ce0) +#define CLOCKS_CLK_HSTX_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_HSTX_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_HSTX_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_HSTX_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_HSTX_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_HSTX_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_HSTX_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_HSTX_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_HSTX_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_HSTX_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_HSTX_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_HSTX_CTRL_NUDGE_LSB _u(20) +#define CLOCKS_CLK_HSTX_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_HSTX_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_HSTX_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_HSTX_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_HSTX_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_HSTX_CTRL_PHASE_LSB _u(16) +#define CLOCKS_CLK_HSTX_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_HSTX_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_HSTX_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_HSTX_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_HSTX_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_HSTX_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_HSTX_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_HSTX_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_HSTX_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_HSTX_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_HSTX_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_HSTX_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_HSTX_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_HSTX_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clk_sys +// 0x1 -> clksrc_pll_sys +// 0x2 -> clksrc_pll_usb +// 0x3 -> clksrc_gpin0 +// 0x4 -> clksrc_gpin1 +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x3) +#define CLOCKS_CLK_HSTX_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x4) +// ============================================================================= +// Register : CLOCKS_CLK_HSTX_DIV +#define CLOCKS_CLK_HSTX_DIV_OFFSET _u(0x00000058) +#define CLOCKS_CLK_HSTX_DIV_BITS _u(0x00030000) +#define CLOCKS_CLK_HSTX_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_HSTX_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_HSTX_DIV_INT_RESET _u(0x1) +#define CLOCKS_CLK_HSTX_DIV_INT_BITS _u(0x00030000) +#define CLOCKS_CLK_HSTX_DIV_INT_MSB _u(17) +#define CLOCKS_CLK_HSTX_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_HSTX_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_HSTX_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_HSTX_SELECTED_OFFSET _u(0x0000005c) +#define CLOCKS_CLK_HSTX_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_HSTX_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_HSTX_SELECTED_MSB _u(0) +#define CLOCKS_CLK_HSTX_SELECTED_LSB _u(0) +#define CLOCKS_CLK_HSTX_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_USB_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_USB_CTRL_OFFSET _u(0x00000060) +#define CLOCKS_CLK_USB_CTRL_BITS _u(0x10130ce0) +#define CLOCKS_CLK_USB_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_USB_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_USB_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_USB_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_USB_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_USB_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_USB_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_USB_CTRL_NUDGE_LSB _u(20) +#define CLOCKS_CLK_USB_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_USB_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_USB_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_USB_CTRL_PHASE_LSB _u(16) +#define CLOCKS_CLK_USB_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_USB_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_USB_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_USB_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_USB_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_USB_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_USB_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_USB_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_USB_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_usb +// 0x1 -> clksrc_pll_sys +// 0x2 -> rosc_clksrc_ph +// 0x3 -> xosc_clksrc +// 0x4 -> clksrc_gpin0 +// 0x5 -> clksrc_gpin1 +#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) +// ============================================================================= +// Register : CLOCKS_CLK_USB_DIV +#define CLOCKS_CLK_USB_DIV_OFFSET _u(0x00000064) +#define CLOCKS_CLK_USB_DIV_BITS _u(0x000f0000) +#define CLOCKS_CLK_USB_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_USB_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_USB_DIV_INT_RESET _u(0x1) +#define CLOCKS_CLK_USB_DIV_INT_BITS _u(0x000f0000) +#define CLOCKS_CLK_USB_DIV_INT_MSB _u(19) +#define CLOCKS_CLK_USB_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_USB_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_USB_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_USB_SELECTED_OFFSET _u(0x00000068) +#define CLOCKS_CLK_USB_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_USB_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_USB_SELECTED_MSB _u(0) +#define CLOCKS_CLK_USB_SELECTED_LSB _u(0) +#define CLOCKS_CLK_USB_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_CLK_ADC_CTRL +// Description : Clock control, can be changed on-the-fly (except for auxsrc) +#define CLOCKS_CLK_ADC_CTRL_OFFSET _u(0x0000006c) +#define CLOCKS_CLK_ADC_CTRL_BITS _u(0x10130ce0) +#define CLOCKS_CLK_ADC_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_ENABLED +// Description : clock generator is enabled +#define CLOCKS_CLK_ADC_CTRL_ENABLED_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_ENABLED_BITS _u(0x10000000) +#define CLOCKS_CLK_ADC_CTRL_ENABLED_MSB _u(28) +#define CLOCKS_CLK_ADC_CTRL_ENABLED_LSB _u(28) +#define CLOCKS_CLK_ADC_CTRL_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_NUDGE +// Description : An edge on this signal shifts the phase of the output by 1 +// cycle of the input clock +// This can be done at any time +#define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS _u(0x00100000) +#define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB _u(20) +#define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB _u(20) +#define CLOCKS_CLK_ADC_CTRL_NUDGE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_PHASE +// Description : This delays the enable signal by up to 3 cycles of the input +// clock +// This must be set before the clock is enabled to have any effect +#define CLOCKS_CLK_ADC_CTRL_PHASE_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_PHASE_BITS _u(0x00030000) +#define CLOCKS_CLK_ADC_CTRL_PHASE_MSB _u(17) +#define CLOCKS_CLK_ADC_CTRL_PHASE_LSB _u(16) +#define CLOCKS_CLK_ADC_CTRL_PHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_ENABLE +// Description : Starts and stops the clock generator cleanly +#define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS _u(0x00000800) +#define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB _u(11) +#define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB _u(11) +#define CLOCKS_CLK_ADC_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_KILL +// Description : Asynchronously kills the clock generator, enable must be set +// low before deasserting kill +#define CLOCKS_CLK_ADC_CTRL_KILL_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_KILL_BITS _u(0x00000400) +#define CLOCKS_CLK_ADC_CTRL_KILL_MSB _u(10) +#define CLOCKS_CLK_ADC_CTRL_KILL_LSB _u(10) +#define CLOCKS_CLK_ADC_CTRL_KILL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_CTRL_AUXSRC +// Description : Selects the auxiliary clock source, will glitch when switching +// 0x0 -> clksrc_pll_usb +// 0x1 -> clksrc_pll_sys +// 0x2 -> rosc_clksrc_ph +// 0x3 -> xosc_clksrc +// 0x4 -> clksrc_gpin0 +// 0x5 -> clksrc_gpin1 +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS _u(0x000000e0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB _u(7) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB _u(5) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS "RW" +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4) +#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5) +// ============================================================================= +// Register : CLOCKS_CLK_ADC_DIV +#define CLOCKS_CLK_ADC_DIV_OFFSET _u(0x00000070) +#define CLOCKS_CLK_ADC_DIV_BITS _u(0x000f0000) +#define CLOCKS_CLK_ADC_DIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_ADC_DIV_INT +// Description : Integer part of clock divisor, 0 -> max+1, can be changed on- +// the-fly +#define CLOCKS_CLK_ADC_DIV_INT_RESET _u(0x1) +#define CLOCKS_CLK_ADC_DIV_INT_BITS _u(0x000f0000) +#define CLOCKS_CLK_ADC_DIV_INT_MSB _u(19) +#define CLOCKS_CLK_ADC_DIV_INT_LSB _u(16) +#define CLOCKS_CLK_ADC_DIV_INT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_ADC_SELECTED +// Description : Indicates which src is currently selected (one-hot) +// This slice does not have a glitchless mux (only the AUX_SRC +// field is present, not SRC) so this register is hardwired to +// 0x1. +#define CLOCKS_CLK_ADC_SELECTED_OFFSET _u(0x00000074) +#define CLOCKS_CLK_ADC_SELECTED_BITS _u(0x00000001) +#define CLOCKS_CLK_ADC_SELECTED_RESET _u(0x00000001) +#define CLOCKS_CLK_ADC_SELECTED_MSB _u(0) +#define CLOCKS_CLK_ADC_SELECTED_LSB _u(0) +#define CLOCKS_CLK_ADC_SELECTED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_DFTCLK_XOSC_CTRL +#define CLOCKS_DFTCLK_XOSC_CTRL_OFFSET _u(0x00000078) +#define CLOCKS_DFTCLK_XOSC_CTRL_BITS _u(0x00000003) +#define CLOCKS_DFTCLK_XOSC_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_DFTCLK_XOSC_CTRL_SRC +// 0x0 -> NULL +// 0x1 -> clksrc_pll_usb_primary +// 0x2 -> clksrc_gpin0 +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_RESET _u(0x0) +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_BITS _u(0x00000003) +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_MSB _u(1) +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_LSB _u(0) +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_ACCESS "RW" +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_VALUE_NULL _u(0x0) +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_VALUE_CLKSRC_PLL_USB_PRIMARY _u(0x1) +#define CLOCKS_DFTCLK_XOSC_CTRL_SRC_VALUE_CLKSRC_GPIN0 _u(0x2) +// ============================================================================= +// Register : CLOCKS_DFTCLK_ROSC_CTRL +#define CLOCKS_DFTCLK_ROSC_CTRL_OFFSET _u(0x0000007c) +#define CLOCKS_DFTCLK_ROSC_CTRL_BITS _u(0x00000003) +#define CLOCKS_DFTCLK_ROSC_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_DFTCLK_ROSC_CTRL_SRC +// 0x0 -> NULL +// 0x1 -> clksrc_pll_sys_primary_rosc +// 0x2 -> clksrc_gpin1 +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_RESET _u(0x0) +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_BITS _u(0x00000003) +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_MSB _u(1) +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_LSB _u(0) +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_ACCESS "RW" +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_VALUE_NULL _u(0x0) +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_VALUE_CLKSRC_PLL_SYS_PRIMARY_ROSC _u(0x1) +#define CLOCKS_DFTCLK_ROSC_CTRL_SRC_VALUE_CLKSRC_GPIN1 _u(0x2) +// ============================================================================= +// Register : CLOCKS_DFTCLK_LPOSC_CTRL +#define CLOCKS_DFTCLK_LPOSC_CTRL_OFFSET _u(0x00000080) +#define CLOCKS_DFTCLK_LPOSC_CTRL_BITS _u(0x00000003) +#define CLOCKS_DFTCLK_LPOSC_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_DFTCLK_LPOSC_CTRL_SRC +// 0x0 -> NULL +// 0x1 -> clksrc_pll_usb_primary_lposc +// 0x2 -> clksrc_gpin1 +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_RESET _u(0x0) +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_BITS _u(0x00000003) +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_MSB _u(1) +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_LSB _u(0) +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_ACCESS "RW" +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_VALUE_NULL _u(0x0) +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_VALUE_CLKSRC_PLL_USB_PRIMARY_LPOSC _u(0x1) +#define CLOCKS_DFTCLK_LPOSC_CTRL_SRC_VALUE_CLKSRC_GPIN1 _u(0x2) +// ============================================================================= +// Register : CLOCKS_CLK_SYS_RESUS_CTRL +#define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET _u(0x00000084) +#define CLOCKS_CLK_SYS_RESUS_CTRL_BITS _u(0x000111ff) +#define CLOCKS_CLK_SYS_RESUS_CTRL_RESET _u(0x000000ff) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR +// Description : For clearing the resus after the fault that triggered it has +// been corrected +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS _u(0x00010000) +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB _u(16) +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB _u(16) +#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_FRCE +// Description : Force a resus, for test purposes only +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS _u(0x00001000) +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB _u(12) +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB _u(12) +#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE +// Description : Enable resus +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS _u(0x00000100) +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB _u(8) +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB _u(8) +#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT +// Description : This is expressed as a number of clk_ref cycles +// and must be >= 2x clk_ref_freq/min_clk_tst_freq +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET _u(0xff) +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS _u(0x000000ff) +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB _u(7) +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB _u(0) +#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_CLK_SYS_RESUS_STATUS +#define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET _u(0x00000088) +#define CLOCKS_CLK_SYS_RESUS_STATUS_BITS _u(0x00000001) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED +// Description : Clock has been resuscitated, correct the error then send +// ctrl_clear=1 +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET _u(0x0) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS _u(0x00000001) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB _u(0) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB _u(0) +#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_FC0_REF_KHZ +// Description : Reference clock frequency in kHz +#define CLOCKS_FC0_REF_KHZ_OFFSET _u(0x0000008c) +#define CLOCKS_FC0_REF_KHZ_BITS _u(0x000fffff) +#define CLOCKS_FC0_REF_KHZ_RESET _u(0x00000000) +#define CLOCKS_FC0_REF_KHZ_MSB _u(19) +#define CLOCKS_FC0_REF_KHZ_LSB _u(0) +#define CLOCKS_FC0_REF_KHZ_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_MIN_KHZ +// Description : Minimum pass frequency in kHz. This is optional. Set to 0 if +// you are not using the pass/fail flags +#define CLOCKS_FC0_MIN_KHZ_OFFSET _u(0x00000090) +#define CLOCKS_FC0_MIN_KHZ_BITS _u(0x01ffffff) +#define CLOCKS_FC0_MIN_KHZ_RESET _u(0x00000000) +#define CLOCKS_FC0_MIN_KHZ_MSB _u(24) +#define CLOCKS_FC0_MIN_KHZ_LSB _u(0) +#define CLOCKS_FC0_MIN_KHZ_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_MAX_KHZ +// Description : Maximum pass frequency in kHz. This is optional. Set to +// 0x1ffffff if you are not using the pass/fail flags +#define CLOCKS_FC0_MAX_KHZ_OFFSET _u(0x00000094) +#define CLOCKS_FC0_MAX_KHZ_BITS _u(0x01ffffff) +#define CLOCKS_FC0_MAX_KHZ_RESET _u(0x01ffffff) +#define CLOCKS_FC0_MAX_KHZ_MSB _u(24) +#define CLOCKS_FC0_MAX_KHZ_LSB _u(0) +#define CLOCKS_FC0_MAX_KHZ_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_DELAY +// Description : Delays the start of frequency counting to allow the mux to +// settle +// Delay is measured in multiples of the reference clock period +#define CLOCKS_FC0_DELAY_OFFSET _u(0x00000098) +#define CLOCKS_FC0_DELAY_BITS _u(0x00000007) +#define CLOCKS_FC0_DELAY_RESET _u(0x00000001) +#define CLOCKS_FC0_DELAY_MSB _u(2) +#define CLOCKS_FC0_DELAY_LSB _u(0) +#define CLOCKS_FC0_DELAY_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_INTERVAL +// Description : The test interval is 0.98us * 2**interval, but let's call it +// 1us * 2**interval +// The default gives a test interval of 250us +#define CLOCKS_FC0_INTERVAL_OFFSET _u(0x0000009c) +#define CLOCKS_FC0_INTERVAL_BITS _u(0x0000000f) +#define CLOCKS_FC0_INTERVAL_RESET _u(0x00000008) +#define CLOCKS_FC0_INTERVAL_MSB _u(3) +#define CLOCKS_FC0_INTERVAL_LSB _u(0) +#define CLOCKS_FC0_INTERVAL_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_FC0_SRC +// Description : Clock sent to frequency counter, set to 0 when not required +// Writing to this register initiates the frequency count +// 0x00 -> NULL +// 0x01 -> pll_sys_clksrc_primary +// 0x02 -> pll_usb_clksrc_primary +// 0x03 -> rosc_clksrc +// 0x04 -> rosc_clksrc_ph +// 0x05 -> xosc_clksrc +// 0x06 -> clksrc_gpin0 +// 0x07 -> clksrc_gpin1 +// 0x08 -> clk_ref +// 0x09 -> clk_sys +// 0x0a -> clk_peri +// 0x0b -> clk_usb +// 0x0c -> clk_adc +// 0x0d -> clk_hstx +// 0x0e -> lposc_clksrc +// 0x0f -> otp_clk2fc +// 0x10 -> pll_usb_clksrc_primary_dft +#define CLOCKS_FC0_SRC_OFFSET _u(0x000000a0) +#define CLOCKS_FC0_SRC_BITS _u(0x000000ff) +#define CLOCKS_FC0_SRC_RESET _u(0x00000000) +#define CLOCKS_FC0_SRC_MSB _u(7) +#define CLOCKS_FC0_SRC_LSB _u(0) +#define CLOCKS_FC0_SRC_ACCESS "RW" +#define CLOCKS_FC0_SRC_VALUE_NULL _u(0x00) +#define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY _u(0x01) +#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY _u(0x02) +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC _u(0x03) +#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH _u(0x04) +#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC _u(0x05) +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 _u(0x06) +#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 _u(0x07) +#define CLOCKS_FC0_SRC_VALUE_CLK_REF _u(0x08) +#define CLOCKS_FC0_SRC_VALUE_CLK_SYS _u(0x09) +#define CLOCKS_FC0_SRC_VALUE_CLK_PERI _u(0x0a) +#define CLOCKS_FC0_SRC_VALUE_CLK_USB _u(0x0b) +#define CLOCKS_FC0_SRC_VALUE_CLK_ADC _u(0x0c) +#define CLOCKS_FC0_SRC_VALUE_CLK_HSTX _u(0x0d) +#define CLOCKS_FC0_SRC_VALUE_LPOSC_CLKSRC _u(0x0e) +#define CLOCKS_FC0_SRC_VALUE_OTP_CLK2FC _u(0x0f) +#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY_DFT _u(0x10) +// ============================================================================= +// Register : CLOCKS_FC0_STATUS +// Description : Frequency counter status +#define CLOCKS_FC0_STATUS_OFFSET _u(0x000000a4) +#define CLOCKS_FC0_STATUS_BITS _u(0x11111111) +#define CLOCKS_FC0_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_DIED +// Description : Test clock stopped during test +#define CLOCKS_FC0_STATUS_DIED_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_DIED_BITS _u(0x10000000) +#define CLOCKS_FC0_STATUS_DIED_MSB _u(28) +#define CLOCKS_FC0_STATUS_DIED_LSB _u(28) +#define CLOCKS_FC0_STATUS_DIED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_FAST +// Description : Test clock faster than expected, only valid when status_done=1 +#define CLOCKS_FC0_STATUS_FAST_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_FAST_BITS _u(0x01000000) +#define CLOCKS_FC0_STATUS_FAST_MSB _u(24) +#define CLOCKS_FC0_STATUS_FAST_LSB _u(24) +#define CLOCKS_FC0_STATUS_FAST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_SLOW +// Description : Test clock slower than expected, only valid when status_done=1 +#define CLOCKS_FC0_STATUS_SLOW_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_SLOW_BITS _u(0x00100000) +#define CLOCKS_FC0_STATUS_SLOW_MSB _u(20) +#define CLOCKS_FC0_STATUS_SLOW_LSB _u(20) +#define CLOCKS_FC0_STATUS_SLOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_FAIL +// Description : Test failed +#define CLOCKS_FC0_STATUS_FAIL_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_FAIL_BITS _u(0x00010000) +#define CLOCKS_FC0_STATUS_FAIL_MSB _u(16) +#define CLOCKS_FC0_STATUS_FAIL_LSB _u(16) +#define CLOCKS_FC0_STATUS_FAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_WAITING +// Description : Waiting for test clock to start +#define CLOCKS_FC0_STATUS_WAITING_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_WAITING_BITS _u(0x00001000) +#define CLOCKS_FC0_STATUS_WAITING_MSB _u(12) +#define CLOCKS_FC0_STATUS_WAITING_LSB _u(12) +#define CLOCKS_FC0_STATUS_WAITING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_RUNNING +// Description : Test running +#define CLOCKS_FC0_STATUS_RUNNING_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_RUNNING_BITS _u(0x00000100) +#define CLOCKS_FC0_STATUS_RUNNING_MSB _u(8) +#define CLOCKS_FC0_STATUS_RUNNING_LSB _u(8) +#define CLOCKS_FC0_STATUS_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_DONE +// Description : Test complete +#define CLOCKS_FC0_STATUS_DONE_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_DONE_BITS _u(0x00000010) +#define CLOCKS_FC0_STATUS_DONE_MSB _u(4) +#define CLOCKS_FC0_STATUS_DONE_LSB _u(4) +#define CLOCKS_FC0_STATUS_DONE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_STATUS_PASS +// Description : Test passed +#define CLOCKS_FC0_STATUS_PASS_RESET _u(0x0) +#define CLOCKS_FC0_STATUS_PASS_BITS _u(0x00000001) +#define CLOCKS_FC0_STATUS_PASS_MSB _u(0) +#define CLOCKS_FC0_STATUS_PASS_LSB _u(0) +#define CLOCKS_FC0_STATUS_PASS_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_FC0_RESULT +// Description : Result of frequency measurement, only valid when status_done=1 +#define CLOCKS_FC0_RESULT_OFFSET _u(0x000000a8) +#define CLOCKS_FC0_RESULT_BITS _u(0x3fffffff) +#define CLOCKS_FC0_RESULT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_RESULT_KHZ +#define CLOCKS_FC0_RESULT_KHZ_RESET _u(0x0000000) +#define CLOCKS_FC0_RESULT_KHZ_BITS _u(0x3fffffe0) +#define CLOCKS_FC0_RESULT_KHZ_MSB _u(29) +#define CLOCKS_FC0_RESULT_KHZ_LSB _u(5) +#define CLOCKS_FC0_RESULT_KHZ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_FC0_RESULT_FRAC +#define CLOCKS_FC0_RESULT_FRAC_RESET _u(0x00) +#define CLOCKS_FC0_RESULT_FRAC_BITS _u(0x0000001f) +#define CLOCKS_FC0_RESULT_FRAC_MSB _u(4) +#define CLOCKS_FC0_RESULT_FRAC_LSB _u(0) +#define CLOCKS_FC0_RESULT_FRAC_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_WAKE_EN0 +// Description : enable clock in wake mode +#define CLOCKS_WAKE_EN0_OFFSET _u(0x000000ac) +#define CLOCKS_WAKE_EN0_BITS _u(0xffffffff) +#define CLOCKS_WAKE_EN0_RESET _u(0xffffffff) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SIO +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS _u(0x80000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB _u(31) +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB _u(31) +#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_SHA256 +#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_BITS _u(0x40000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_MSB _u(30) +#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_LSB _u(30) +#define CLOCKS_WAKE_EN0_CLK_SYS_SHA256_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PSM +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS _u(0x20000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB _u(29) +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB _u(29) +#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROSC +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS _u(0x10000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB _u(28) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB _u(28) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROM +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS _u(0x08000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB _u(27) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB _u(27) +#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_RESETS +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS _u(0x04000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB _u(26) +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB _u(26) +#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PWM +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS _u(0x02000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB _u(25) +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB _u(25) +#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_POWMAN +#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_BITS _u(0x01000000) +#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_MSB _u(24) +#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_LSB _u(24) +#define CLOCKS_WAKE_EN0_CLK_SYS_POWMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_REF_POWMAN +#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_BITS _u(0x00800000) +#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_MSB _u(23) +#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_LSB _u(23) +#define CLOCKS_WAKE_EN0_CLK_REF_POWMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS _u(0x00400000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB _u(22) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB _u(22) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00200000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB _u(21) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB _u(21) +#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO2 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_BITS _u(0x00100000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_MSB _u(20) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_LSB _u(20) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO1 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS _u(0x00080000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB _u(19) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB _u(19) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO0 +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS _u(0x00040000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB _u(18) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB _u(18) +#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_PADS +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS _u(0x00020000) +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB _u(17) +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB _u(17) +#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_OTP +#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_BITS _u(0x00010000) +#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_MSB _u(16) +#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_LSB _u(16) +#define CLOCKS_WAKE_EN0_CLK_SYS_OTP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_REF_OTP +#define CLOCKS_WAKE_EN0_CLK_REF_OTP_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_REF_OTP_BITS _u(0x00008000) +#define CLOCKS_WAKE_EN0_CLK_REF_OTP_MSB _u(15) +#define CLOCKS_WAKE_EN0_CLK_REF_OTP_LSB _u(15) +#define CLOCKS_WAKE_EN0_CLK_REF_OTP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_JTAG +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS _u(0x00004000) +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB _u(14) +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB _u(14) +#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_IO +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS _u(0x00002000) +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB _u(13) +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB _u(13) +#define CLOCKS_WAKE_EN0_CLK_SYS_IO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C1 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS _u(0x00001000) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB _u(12) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB _u(12) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C0 +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS _u(0x00000800) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB _u(11) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB _u(11) +#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_HSTX +#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_BITS _u(0x00000400) +#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_MSB _u(10) +#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_LSB _u(10) +#define CLOCKS_WAKE_EN0_CLK_SYS_HSTX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_HSTX +#define CLOCKS_WAKE_EN0_CLK_HSTX_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_HSTX_BITS _u(0x00000200) +#define CLOCKS_WAKE_EN0_CLK_HSTX_MSB _u(9) +#define CLOCKS_WAKE_EN0_CLK_HSTX_LSB _u(9) +#define CLOCKS_WAKE_EN0_CLK_HSTX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR +#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_BITS _u(0x00000100) +#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_MSB _u(8) +#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_LSB _u(8) +#define CLOCKS_WAKE_EN0_CLK_SYS_GLITCH_DETECTOR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_DMA +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS _u(0x00000080) +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB _u(7) +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB _u(7) +#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000040) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB _u(6) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB _u(6) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000020) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB _u(5) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB _u(5) +#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM +#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_BITS _u(0x00000010) +#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_MSB _u(4) +#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_LSB _u(4) +#define CLOCKS_WAKE_EN0_CLK_SYS_BOOTRAM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_ADC +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS _u(0x00000008) +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB _u(3) +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB _u(3) +#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_ADC +#define CLOCKS_WAKE_EN0_CLK_ADC_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_ADC_BITS _u(0x00000004) +#define CLOCKS_WAKE_EN0_CLK_ADC_MSB _u(2) +#define CLOCKS_WAKE_EN0_CLK_ADC_LSB _u(2) +#define CLOCKS_WAKE_EN0_CLK_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL +#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_BITS _u(0x00000002) +#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_MSB _u(1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_LSB _u(1) +#define CLOCKS_WAKE_EN0_CLK_SYS_ACCESSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB _u(0) +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB _u(0) +#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_WAKE_EN1 +// Description : enable clock in wake mode +#define CLOCKS_WAKE_EN1_OFFSET _u(0x000000b0) +#define CLOCKS_WAKE_EN1_BITS _u(0x7fffffff) +#define CLOCKS_WAKE_EN1_RESET _u(0x7fffffff) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_XOSC +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS _u(0x40000000) +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB _u(30) +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB _u(30) +#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_XIP +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS _u(0x20000000) +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB _u(29) +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB _u(29) +#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS _u(0x10000000) +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB _u(28) +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB _u(28) +#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_USB +#define CLOCKS_WAKE_EN1_CLK_USB_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_USB_BITS _u(0x08000000) +#define CLOCKS_WAKE_EN1_CLK_USB_MSB _u(27) +#define CLOCKS_WAKE_EN1_CLK_USB_LSB _u(27) +#define CLOCKS_WAKE_EN1_CLK_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS _u(0x04000000) +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB _u(26) +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB _u(26) +#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART1 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS _u(0x02000000) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB _u(25) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB _u(25) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART1 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS _u(0x01000000) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB _u(24) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB _u(24) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART0 +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS _u(0x00800000) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB _u(23) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB _u(23) +#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART0 +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS _u(0x00400000) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB _u(22) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB _u(22) +#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_TRNG +#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_BITS _u(0x00200000) +#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_MSB _u(21) +#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_LSB _u(21) +#define CLOCKS_WAKE_EN1_CLK_SYS_TRNG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER1 +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_BITS _u(0x00100000) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_MSB _u(20) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_LSB _u(20) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER0 +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_BITS _u(0x00080000) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_MSB _u(19) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_LSB _u(19) +#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_TICKS +#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_BITS _u(0x00040000) +#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_MSB _u(18) +#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_LSB _u(18) +#define CLOCKS_WAKE_EN1_CLK_SYS_TICKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_REF_TICKS +#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_BITS _u(0x00020000) +#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_MSB _u(17) +#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_LSB _u(17) +#define CLOCKS_WAKE_EN1_CLK_REF_TICKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_TBMAN +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS _u(0x00010000) +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB _u(16) +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB _u(16) +#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS _u(0x00008000) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB _u(15) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB _u(15) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS _u(0x00004000) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB _u(14) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB _u(14) +#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM9 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_BITS _u(0x00002000) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_MSB _u(13) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_LSB _u(13) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM8 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_BITS _u(0x00001000) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_MSB _u(12) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_LSB _u(12) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM7 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_BITS _u(0x00000800) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_MSB _u(11) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_LSB _u(11) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM6 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_BITS _u(0x00000400) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_MSB _u(10) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_LSB _u(10) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM5 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS _u(0x00000200) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB _u(9) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB _u(9) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM4 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS _u(0x00000100) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB _u(8) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB _u(8) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM3 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_BITS _u(0x00000080) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_MSB _u(7) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_LSB _u(7) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM2 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_BITS _u(0x00000040) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_MSB _u(6) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_LSB _u(6) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_BITS _u(0x00000020) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_MSB _u(5) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_LSB _u(5) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM0 +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_BITS _u(0x00000010) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_MSB _u(4) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_LSB _u(4) +#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SPI1 +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_BITS _u(0x00000008) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_MSB _u(3) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_LSB _u(3) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_PERI_SPI1 +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_BITS _u(0x00000004) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_MSB _u(2) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_LSB _u(2) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_SYS_SPI0 +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_BITS _u(0x00000002) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_MSB _u(1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_LSB _u(1) +#define CLOCKS_WAKE_EN1_CLK_SYS_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_WAKE_EN1_CLK_PERI_SPI0 +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_RESET _u(0x1) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_BITS _u(0x00000001) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_MSB _u(0) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_LSB _u(0) +#define CLOCKS_WAKE_EN1_CLK_PERI_SPI0_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_SLEEP_EN0 +// Description : enable clock in sleep mode +#define CLOCKS_SLEEP_EN0_OFFSET _u(0x000000b4) +#define CLOCKS_SLEEP_EN0_BITS _u(0xffffffff) +#define CLOCKS_SLEEP_EN0_RESET _u(0xffffffff) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SIO +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS _u(0x80000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB _u(31) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB _u(31) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SHA256 +#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_BITS _u(0x40000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_MSB _u(30) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_LSB _u(30) +#define CLOCKS_SLEEP_EN0_CLK_SYS_SHA256_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PSM +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS _u(0x20000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB _u(29) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB _u(29) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROSC +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS _u(0x10000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB _u(28) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB _u(28) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROM +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS _u(0x08000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB _u(27) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB _u(27) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_RESETS +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS _u(0x04000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB _u(26) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB _u(26) +#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PWM +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS _u(0x02000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB _u(25) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB _u(25) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN +#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_BITS _u(0x01000000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_MSB _u(24) +#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_LSB _u(24) +#define CLOCKS_SLEEP_EN0_CLK_SYS_POWMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_REF_POWMAN +#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_BITS _u(0x00800000) +#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_MSB _u(23) +#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_LSB _u(23) +#define CLOCKS_SLEEP_EN0_CLK_REF_POWMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS _u(0x00400000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB _u(22) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB _u(22) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00200000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB _u(21) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB _u(21) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO2 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_BITS _u(0x00100000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_MSB _u(20) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_LSB _u(20) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS _u(0x00080000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB _u(19) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB _u(19) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO0 +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS _u(0x00040000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB _u(18) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB _u(18) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PADS +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS _u(0x00020000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB _u(17) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB _u(17) +#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_OTP +#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_BITS _u(0x00010000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_MSB _u(16) +#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_LSB _u(16) +#define CLOCKS_SLEEP_EN0_CLK_SYS_OTP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_REF_OTP +#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_BITS _u(0x00008000) +#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_MSB _u(15) +#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_LSB _u(15) +#define CLOCKS_SLEEP_EN0_CLK_REF_OTP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_JTAG +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS _u(0x00004000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB _u(14) +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB _u(14) +#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_IO +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS _u(0x00002000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB _u(13) +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB _u(13) +#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C1 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS _u(0x00001000) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB _u(12) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB _u(12) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C0 +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS _u(0x00000800) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB _u(11) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB _u(11) +#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_HSTX +#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_BITS _u(0x00000400) +#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_MSB _u(10) +#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_LSB _u(10) +#define CLOCKS_SLEEP_EN0_CLK_SYS_HSTX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_HSTX +#define CLOCKS_SLEEP_EN0_CLK_HSTX_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_HSTX_BITS _u(0x00000200) +#define CLOCKS_SLEEP_EN0_CLK_HSTX_MSB _u(9) +#define CLOCKS_SLEEP_EN0_CLK_HSTX_LSB _u(9) +#define CLOCKS_SLEEP_EN0_CLK_HSTX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR +#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_BITS _u(0x00000100) +#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_MSB _u(8) +#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_LSB _u(8) +#define CLOCKS_SLEEP_EN0_CLK_SYS_GLITCH_DETECTOR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_DMA +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS _u(0x00000080) +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB _u(7) +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB _u(7) +#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000040) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB _u(6) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB _u(6) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000020) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB _u(5) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB _u(5) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM +#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_BITS _u(0x00000010) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_MSB _u(4) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_LSB _u(4) +#define CLOCKS_SLEEP_EN0_CLK_SYS_BOOTRAM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ADC +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS _u(0x00000008) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB _u(3) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB _u(3) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_ADC +#define CLOCKS_SLEEP_EN0_CLK_ADC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_ADC_BITS _u(0x00000004) +#define CLOCKS_SLEEP_EN0_CLK_ADC_MSB _u(2) +#define CLOCKS_SLEEP_EN0_CLK_ADC_LSB _u(2) +#define CLOCKS_SLEEP_EN0_CLK_ADC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL +#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_BITS _u(0x00000002) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_MSB _u(1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_LSB _u(1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_ACCESSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001) +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB _u(0) +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB _u(0) +#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_SLEEP_EN1 +// Description : enable clock in sleep mode +#define CLOCKS_SLEEP_EN1_OFFSET _u(0x000000b8) +#define CLOCKS_SLEEP_EN1_BITS _u(0x7fffffff) +#define CLOCKS_SLEEP_EN1_RESET _u(0x7fffffff) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XOSC +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS _u(0x40000000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB _u(30) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB _u(30) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XIP +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS _u(0x20000000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB _u(29) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB _u(29) +#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS _u(0x10000000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB _u(28) +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB _u(28) +#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_USB +#define CLOCKS_SLEEP_EN1_CLK_USB_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_USB_BITS _u(0x08000000) +#define CLOCKS_SLEEP_EN1_CLK_USB_MSB _u(27) +#define CLOCKS_SLEEP_EN1_CLK_USB_LSB _u(27) +#define CLOCKS_SLEEP_EN1_CLK_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS _u(0x04000000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB _u(26) +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB _u(26) +#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS _u(0x02000000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB _u(25) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB _u(25) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART1 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS _u(0x01000000) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB _u(24) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB _u(24) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART0 +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS _u(0x00800000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB _u(23) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB _u(23) +#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART0 +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS _u(0x00400000) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB _u(22) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB _u(22) +#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TRNG +#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_BITS _u(0x00200000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_MSB _u(21) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_LSB _u(21) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TRNG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_BITS _u(0x00100000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_MSB _u(20) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_LSB _u(20) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0 +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_BITS _u(0x00080000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_MSB _u(19) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_LSB _u(19) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TICKS +#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_BITS _u(0x00040000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_MSB _u(18) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_LSB _u(18) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TICKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_REF_TICKS +#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_BITS _u(0x00020000) +#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_MSB _u(17) +#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_LSB _u(17) +#define CLOCKS_SLEEP_EN1_CLK_REF_TICKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS _u(0x00010000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB _u(16) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB _u(16) +#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS _u(0x00008000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB _u(15) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB _u(15) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS _u(0x00004000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB _u(14) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB _u(14) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_BITS _u(0x00002000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_MSB _u(13) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_LSB _u(13) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_BITS _u(0x00001000) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_MSB _u(12) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_LSB _u(12) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_BITS _u(0x00000800) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_MSB _u(11) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_LSB _u(11) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_BITS _u(0x00000400) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_MSB _u(10) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_LSB _u(10) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS _u(0x00000200) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB _u(9) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB _u(9) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS _u(0x00000100) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB _u(8) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB _u(8) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_BITS _u(0x00000080) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_MSB _u(7) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_LSB _u(7) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_BITS _u(0x00000040) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_MSB _u(6) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_LSB _u(6) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_BITS _u(0x00000020) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_MSB _u(5) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_LSB _u(5) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_BITS _u(0x00000010) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_MSB _u(4) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_LSB _u(4) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SPI1 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_BITS _u(0x00000008) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_MSB _u(3) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_LSB _u(3) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_PERI_SPI1 +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_BITS _u(0x00000004) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_MSB _u(2) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_LSB _u(2) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SPI0 +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_BITS _u(0x00000002) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_MSB _u(1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_LSB _u(1) +#define CLOCKS_SLEEP_EN1_CLK_SYS_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_SLEEP_EN1_CLK_PERI_SPI0 +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_RESET _u(0x1) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_BITS _u(0x00000001) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_MSB _u(0) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_LSB _u(0) +#define CLOCKS_SLEEP_EN1_CLK_PERI_SPI0_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_ENABLED0 +// Description : indicates the state of the clock enable +#define CLOCKS_ENABLED0_OFFSET _u(0x000000bc) +#define CLOCKS_ENABLED0_BITS _u(0xffffffff) +#define CLOCKS_ENABLED0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SIO +#define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS _u(0x80000000) +#define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB _u(31) +#define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB _u(31) +#define CLOCKS_ENABLED0_CLK_SYS_SIO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_SHA256 +#define CLOCKS_ENABLED0_CLK_SYS_SHA256_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_SHA256_BITS _u(0x40000000) +#define CLOCKS_ENABLED0_CLK_SYS_SHA256_MSB _u(30) +#define CLOCKS_ENABLED0_CLK_SYS_SHA256_LSB _u(30) +#define CLOCKS_ENABLED0_CLK_SYS_SHA256_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PSM +#define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS _u(0x20000000) +#define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB _u(29) +#define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB _u(29) +#define CLOCKS_ENABLED0_CLK_SYS_PSM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_ROSC +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS _u(0x10000000) +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB _u(28) +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB _u(28) +#define CLOCKS_ENABLED0_CLK_SYS_ROSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_ROM +#define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS _u(0x08000000) +#define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB _u(27) +#define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB _u(27) +#define CLOCKS_ENABLED0_CLK_SYS_ROM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_RESETS +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS _u(0x04000000) +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB _u(26) +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB _u(26) +#define CLOCKS_ENABLED0_CLK_SYS_RESETS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PWM +#define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS _u(0x02000000) +#define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB _u(25) +#define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB _u(25) +#define CLOCKS_ENABLED0_CLK_SYS_PWM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_POWMAN +#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_BITS _u(0x01000000) +#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_MSB _u(24) +#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_LSB _u(24) +#define CLOCKS_ENABLED0_CLK_SYS_POWMAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_REF_POWMAN +#define CLOCKS_ENABLED0_CLK_REF_POWMAN_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_REF_POWMAN_BITS _u(0x00800000) +#define CLOCKS_ENABLED0_CLK_REF_POWMAN_MSB _u(23) +#define CLOCKS_ENABLED0_CLK_REF_POWMAN_LSB _u(23) +#define CLOCKS_ENABLED0_CLK_REF_POWMAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_USB +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS _u(0x00400000) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB _u(22) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB _u(22) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_SYS +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS _u(0x00200000) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB _u(21) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB _u(21) +#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PIO2 +#define CLOCKS_ENABLED0_CLK_SYS_PIO2_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PIO2_BITS _u(0x00100000) +#define CLOCKS_ENABLED0_CLK_SYS_PIO2_MSB _u(20) +#define CLOCKS_ENABLED0_CLK_SYS_PIO2_LSB _u(20) +#define CLOCKS_ENABLED0_CLK_SYS_PIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PIO1 +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS _u(0x00080000) +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB _u(19) +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB _u(19) +#define CLOCKS_ENABLED0_CLK_SYS_PIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PIO0 +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS _u(0x00040000) +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB _u(18) +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB _u(18) +#define CLOCKS_ENABLED0_CLK_SYS_PIO0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_PADS +#define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS _u(0x00020000) +#define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB _u(17) +#define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB _u(17) +#define CLOCKS_ENABLED0_CLK_SYS_PADS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_OTP +#define CLOCKS_ENABLED0_CLK_SYS_OTP_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_OTP_BITS _u(0x00010000) +#define CLOCKS_ENABLED0_CLK_SYS_OTP_MSB _u(16) +#define CLOCKS_ENABLED0_CLK_SYS_OTP_LSB _u(16) +#define CLOCKS_ENABLED0_CLK_SYS_OTP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_REF_OTP +#define CLOCKS_ENABLED0_CLK_REF_OTP_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_REF_OTP_BITS _u(0x00008000) +#define CLOCKS_ENABLED0_CLK_REF_OTP_MSB _u(15) +#define CLOCKS_ENABLED0_CLK_REF_OTP_LSB _u(15) +#define CLOCKS_ENABLED0_CLK_REF_OTP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_JTAG +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS _u(0x00004000) +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB _u(14) +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB _u(14) +#define CLOCKS_ENABLED0_CLK_SYS_JTAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_IO +#define CLOCKS_ENABLED0_CLK_SYS_IO_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_IO_BITS _u(0x00002000) +#define CLOCKS_ENABLED0_CLK_SYS_IO_MSB _u(13) +#define CLOCKS_ENABLED0_CLK_SYS_IO_LSB _u(13) +#define CLOCKS_ENABLED0_CLK_SYS_IO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_I2C1 +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS _u(0x00001000) +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB _u(12) +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB _u(12) +#define CLOCKS_ENABLED0_CLK_SYS_I2C1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_I2C0 +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS _u(0x00000800) +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB _u(11) +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB _u(11) +#define CLOCKS_ENABLED0_CLK_SYS_I2C0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_HSTX +#define CLOCKS_ENABLED0_CLK_SYS_HSTX_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_HSTX_BITS _u(0x00000400) +#define CLOCKS_ENABLED0_CLK_SYS_HSTX_MSB _u(10) +#define CLOCKS_ENABLED0_CLK_SYS_HSTX_LSB _u(10) +#define CLOCKS_ENABLED0_CLK_SYS_HSTX_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_HSTX +#define CLOCKS_ENABLED0_CLK_HSTX_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_HSTX_BITS _u(0x00000200) +#define CLOCKS_ENABLED0_CLK_HSTX_MSB _u(9) +#define CLOCKS_ENABLED0_CLK_HSTX_LSB _u(9) +#define CLOCKS_ENABLED0_CLK_HSTX_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR +#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_BITS _u(0x00000100) +#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_MSB _u(8) +#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_LSB _u(8) +#define CLOCKS_ENABLED0_CLK_SYS_GLITCH_DETECTOR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_DMA +#define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS _u(0x00000080) +#define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB _u(7) +#define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB _u(7) +#define CLOCKS_ENABLED0_CLK_SYS_DMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS _u(0x00000040) +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB _u(6) +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB _u(6) +#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_BUSCTRL +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS _u(0x00000020) +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB _u(5) +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB _u(5) +#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_BOOTRAM +#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_BITS _u(0x00000010) +#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_MSB _u(4) +#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_LSB _u(4) +#define CLOCKS_ENABLED0_CLK_SYS_BOOTRAM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_ADC +#define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS _u(0x00000008) +#define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB _u(3) +#define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB _u(3) +#define CLOCKS_ENABLED0_CLK_SYS_ADC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_ADC +#define CLOCKS_ENABLED0_CLK_ADC_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_ADC_BITS _u(0x00000004) +#define CLOCKS_ENABLED0_CLK_ADC_MSB _u(2) +#define CLOCKS_ENABLED0_CLK_ADC_LSB _u(2) +#define CLOCKS_ENABLED0_CLK_ADC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL +#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_BITS _u(0x00000002) +#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_MSB _u(1) +#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_LSB _u(1) +#define CLOCKS_ENABLED0_CLK_SYS_ACCESSCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED0_CLK_SYS_CLOCKS +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET _u(0x0) +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS _u(0x00000001) +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB _u(0) +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB _u(0) +#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_ENABLED1 +// Description : indicates the state of the clock enable +#define CLOCKS_ENABLED1_OFFSET _u(0x000000c0) +#define CLOCKS_ENABLED1_BITS _u(0x7fffffff) +#define CLOCKS_ENABLED1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_XOSC +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS _u(0x40000000) +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB _u(30) +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB _u(30) +#define CLOCKS_ENABLED1_CLK_SYS_XOSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_XIP +#define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS _u(0x20000000) +#define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB _u(29) +#define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB _u(29) +#define CLOCKS_ENABLED1_CLK_SYS_XIP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_WATCHDOG +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS _u(0x10000000) +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB _u(28) +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB _u(28) +#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_USB +#define CLOCKS_ENABLED1_CLK_USB_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_USB_BITS _u(0x08000000) +#define CLOCKS_ENABLED1_CLK_USB_MSB _u(27) +#define CLOCKS_ENABLED1_CLK_USB_LSB _u(27) +#define CLOCKS_ENABLED1_CLK_USB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_USBCTRL +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS _u(0x04000000) +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB _u(26) +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB _u(26) +#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_UART1 +#define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS _u(0x02000000) +#define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB _u(25) +#define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB _u(25) +#define CLOCKS_ENABLED1_CLK_SYS_UART1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_PERI_UART1 +#define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS _u(0x01000000) +#define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB _u(24) +#define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB _u(24) +#define CLOCKS_ENABLED1_CLK_PERI_UART1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_UART0 +#define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS _u(0x00800000) +#define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB _u(23) +#define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB _u(23) +#define CLOCKS_ENABLED1_CLK_SYS_UART0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_PERI_UART0 +#define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS _u(0x00400000) +#define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB _u(22) +#define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB _u(22) +#define CLOCKS_ENABLED1_CLK_PERI_UART0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_TRNG +#define CLOCKS_ENABLED1_CLK_SYS_TRNG_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_TRNG_BITS _u(0x00200000) +#define CLOCKS_ENABLED1_CLK_SYS_TRNG_MSB _u(21) +#define CLOCKS_ENABLED1_CLK_SYS_TRNG_LSB _u(21) +#define CLOCKS_ENABLED1_CLK_SYS_TRNG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_TIMER1 +#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_BITS _u(0x00100000) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_MSB _u(20) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_LSB _u(20) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_TIMER0 +#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_BITS _u(0x00080000) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_MSB _u(19) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_LSB _u(19) +#define CLOCKS_ENABLED1_CLK_SYS_TIMER0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_TICKS +#define CLOCKS_ENABLED1_CLK_SYS_TICKS_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_TICKS_BITS _u(0x00040000) +#define CLOCKS_ENABLED1_CLK_SYS_TICKS_MSB _u(18) +#define CLOCKS_ENABLED1_CLK_SYS_TICKS_LSB _u(18) +#define CLOCKS_ENABLED1_CLK_SYS_TICKS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_REF_TICKS +#define CLOCKS_ENABLED1_CLK_REF_TICKS_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_REF_TICKS_BITS _u(0x00020000) +#define CLOCKS_ENABLED1_CLK_REF_TICKS_MSB _u(17) +#define CLOCKS_ENABLED1_CLK_REF_TICKS_LSB _u(17) +#define CLOCKS_ENABLED1_CLK_REF_TICKS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_TBMAN +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS _u(0x00010000) +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB _u(16) +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB _u(16) +#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SYSINFO +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS _u(0x00008000) +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB _u(15) +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB _u(15) +#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SYSCFG +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS _u(0x00004000) +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB _u(14) +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB _u(14) +#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM9 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_BITS _u(0x00002000) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_MSB _u(13) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_LSB _u(13) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM8 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_BITS _u(0x00001000) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_MSB _u(12) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_LSB _u(12) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM7 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_BITS _u(0x00000800) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_MSB _u(11) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_LSB _u(11) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM6 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_BITS _u(0x00000400) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_MSB _u(10) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_LSB _u(10) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM5 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS _u(0x00000200) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB _u(9) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB _u(9) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM4 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS _u(0x00000100) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB _u(8) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB _u(8) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM3 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_BITS _u(0x00000080) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_MSB _u(7) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_LSB _u(7) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM2 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_BITS _u(0x00000040) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_MSB _u(6) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_LSB _u(6) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM1 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_BITS _u(0x00000020) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_MSB _u(5) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_LSB _u(5) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM0 +#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_BITS _u(0x00000010) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_MSB _u(4) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_LSB _u(4) +#define CLOCKS_ENABLED1_CLK_SYS_SRAM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SPI1 +#define CLOCKS_ENABLED1_CLK_SYS_SPI1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SPI1_BITS _u(0x00000008) +#define CLOCKS_ENABLED1_CLK_SYS_SPI1_MSB _u(3) +#define CLOCKS_ENABLED1_CLK_SYS_SPI1_LSB _u(3) +#define CLOCKS_ENABLED1_CLK_SYS_SPI1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_PERI_SPI1 +#define CLOCKS_ENABLED1_CLK_PERI_SPI1_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_PERI_SPI1_BITS _u(0x00000004) +#define CLOCKS_ENABLED1_CLK_PERI_SPI1_MSB _u(2) +#define CLOCKS_ENABLED1_CLK_PERI_SPI1_LSB _u(2) +#define CLOCKS_ENABLED1_CLK_PERI_SPI1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_SYS_SPI0 +#define CLOCKS_ENABLED1_CLK_SYS_SPI0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_SYS_SPI0_BITS _u(0x00000002) +#define CLOCKS_ENABLED1_CLK_SYS_SPI0_MSB _u(1) +#define CLOCKS_ENABLED1_CLK_SYS_SPI0_LSB _u(1) +#define CLOCKS_ENABLED1_CLK_SYS_SPI0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : CLOCKS_ENABLED1_CLK_PERI_SPI0 +#define CLOCKS_ENABLED1_CLK_PERI_SPI0_RESET _u(0x0) +#define CLOCKS_ENABLED1_CLK_PERI_SPI0_BITS _u(0x00000001) +#define CLOCKS_ENABLED1_CLK_PERI_SPI0_MSB _u(0) +#define CLOCKS_ENABLED1_CLK_PERI_SPI0_LSB _u(0) +#define CLOCKS_ENABLED1_CLK_PERI_SPI0_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_INTR +// Description : Raw Interrupts +#define CLOCKS_INTR_OFFSET _u(0x000000c4) +#define CLOCKS_INTR_BITS _u(0x00000001) +#define CLOCKS_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTR_CLK_SYS_RESUS +#define CLOCKS_INTR_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTR_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTR_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTR_CLK_SYS_RESUS_LSB _u(0) +#define CLOCKS_INTR_CLK_SYS_RESUS_ACCESS "RO" +// ============================================================================= +// Register : CLOCKS_INTE +// Description : Interrupt Enable +#define CLOCKS_INTE_OFFSET _u(0x000000c8) +#define CLOCKS_INTE_BITS _u(0x00000001) +#define CLOCKS_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTE_CLK_SYS_RESUS +#define CLOCKS_INTE_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTE_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTE_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTE_CLK_SYS_RESUS_LSB _u(0) +#define CLOCKS_INTE_CLK_SYS_RESUS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_INTF +// Description : Interrupt Force +#define CLOCKS_INTF_OFFSET _u(0x000000cc) +#define CLOCKS_INTF_BITS _u(0x00000001) +#define CLOCKS_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTF_CLK_SYS_RESUS +#define CLOCKS_INTF_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTF_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTF_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTF_CLK_SYS_RESUS_LSB _u(0) +#define CLOCKS_INTF_CLK_SYS_RESUS_ACCESS "RW" +// ============================================================================= +// Register : CLOCKS_INTS +// Description : Interrupt status after masking & forcing +#define CLOCKS_INTS_OFFSET _u(0x000000d0) +#define CLOCKS_INTS_BITS _u(0x00000001) +#define CLOCKS_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CLOCKS_INTS_CLK_SYS_RESUS +#define CLOCKS_INTS_CLK_SYS_RESUS_RESET _u(0x0) +#define CLOCKS_INTS_CLK_SYS_RESUS_BITS _u(0x00000001) +#define CLOCKS_INTS_CLK_SYS_RESUS_MSB _u(0) +#define CLOCKS_INTS_CLK_SYS_RESUS_LSB _u(0) +#define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_CLOCKS_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/coresight_trace.h b/lib/pico-sdk/rp2350/hardware/regs/coresight_trace.h new file mode 100644 index 000000000000..cb4f990d7a12 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/coresight_trace.h @@ -0,0 +1,85 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : CORESIGHT_TRACE +// Version : 1 +// Bus type : ahbl +// Description : Coresight block - RP specific registers +// ============================================================================= +#ifndef _HARDWARE_REGS_CORESIGHT_TRACE_H +#define _HARDWARE_REGS_CORESIGHT_TRACE_H +// ============================================================================= +// Register : CORESIGHT_TRACE_CTRL_STATUS +// Description : Control and status register +#define CORESIGHT_TRACE_CTRL_STATUS_OFFSET _u(0x00000000) +#define CORESIGHT_TRACE_CTRL_STATUS_BITS _u(0x00000003) +#define CORESIGHT_TRACE_CTRL_STATUS_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW +// Description : This status flag is set high when trace data has been dropped +// due to the FIFO being full at the point trace data was sampled. +// Write 1 to acknowledge and clear the bit. +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_RESET _u(0x0) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_BITS _u(0x00000002) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_MSB _u(1) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_LSB _u(1) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH +// Description : Set to 1 to continuously hold the trace FIFO in a flushed state +// and prevent overflow. +// +// Before clearing this flag, configure and start a DMA channel +// with the correct DREQ for the TRACE_CAPTURE_FIFO register. +// +// Clear this flag to begin sampling trace data, and set once +// again once the trace capture buffer is full. You must configure +// the TPIU in order to generate trace packets to be captured, as +// well as components like the ETM further upstream to generate +// the event stream propagated to the TPIU. +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_RESET _u(0x1) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_BITS _u(0x00000001) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_MSB _u(0) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_LSB _u(0) +#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_ACCESS "RW" +// ============================================================================= +// Register : CORESIGHT_TRACE_TRACE_CAPTURE_FIFO +// Description : FIFO for trace data captured from the TPIU +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET _u(0x00000004) +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_BITS _u(0xffffffff) +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA +// Description : Read from an 8 x 32-bit FIFO containing trace data captured +// from the TPIU. +// +// Hardware pushes to the FIFO on rising edges of clk_sys, when +// either of the following is true: +// +// * TPIU TRACECTL output is low (normal trace data) +// +// * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and +// TRACEDATA1 are both low (trigger packet) +// +// These conditions are in accordance with Arm Coresight +// Architecture Spec v3.0 section D3.3.3: Decoding requirements +// for Trace Capture Devices +// +// The data captured into the FIFO is the full 32-bit TRACEDATA +// bus output by the TPIU. Note that the TPIU is a DDR output at +// half of clk_sys, therefore this interface can capture the full +// 32-bit TPIU DDR output bandwidth as it samples once per active +// edge of the TPIU output clock. +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_RESET _u(0x00000000) +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_BITS _u(0xffffffff) +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_MSB _u(31) +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_LSB _u(0) +#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_ACCESS "RF" +// ============================================================================= +#endif // _HARDWARE_REGS_CORESIGHT_TRACE_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/dma.h b/lib/pico-sdk/rp2350/hardware/regs/dma.h new file mode 100644 index 000000000000..00ecde1867e6 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/dma.h @@ -0,0 +1,9914 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : DMA +// Version : 1 +// Bus type : apb +// Description : DMA with separate read and write masters +// ============================================================================= +#ifndef _HARDWARE_REGS_DMA_H +#define _HARDWARE_REGS_DMA_H +// ============================================================================= +// Register : DMA_CH0_READ_ADDR +// Description : DMA Channel 0 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH0_READ_ADDR_OFFSET _u(0x00000000) +#define DMA_CH0_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH0_READ_ADDR_MSB _u(31) +#define DMA_CH0_READ_ADDR_LSB _u(0) +#define DMA_CH0_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_WRITE_ADDR +// Description : DMA Channel 0 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH0_WRITE_ADDR_OFFSET _u(0x00000004) +#define DMA_CH0_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH0_WRITE_ADDR_MSB _u(31) +#define DMA_CH0_WRITE_ADDR_LSB _u(0) +#define DMA_CH0_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_TRANS_COUNT +// Description : DMA Channel 0 Transfer Count +#define DMA_CH0_TRANS_COUNT_OFFSET _u(0x00000008) +#define DMA_CH0_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH0_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH0_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH0_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH0_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH0_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH0_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH0_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH0_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH0_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH0_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH0_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH0_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH0_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH0_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_CTRL_TRIG +// Description : DMA Channel 0 Control and Status +#define DMA_CH0_CTRL_TRIG_OFFSET _u(0x0000000c) +#define DMA_CH0_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH0_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH0_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH0_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH0_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH0_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH0_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH0_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH0_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH0_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH0_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH0_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH0_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH0_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL1_CTRL +// Description : Alias for channel 0 CTRL register +#define DMA_CH0_AL1_CTRL_OFFSET _u(0x00000010) +#define DMA_CH0_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH0_AL1_CTRL_RESET "-" +#define DMA_CH0_AL1_CTRL_MSB _u(31) +#define DMA_CH0_AL1_CTRL_LSB _u(0) +#define DMA_CH0_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL1_READ_ADDR +// Description : Alias for channel 0 READ_ADDR register +#define DMA_CH0_AL1_READ_ADDR_OFFSET _u(0x00000014) +#define DMA_CH0_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_AL1_READ_ADDR_RESET "-" +#define DMA_CH0_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH0_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH0_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL1_WRITE_ADDR +// Description : Alias for channel 0 WRITE_ADDR register +#define DMA_CH0_AL1_WRITE_ADDR_OFFSET _u(0x00000018) +#define DMA_CH0_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH0_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH0_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 0 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000001c) +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL2_CTRL +// Description : Alias for channel 0 CTRL register +#define DMA_CH0_AL2_CTRL_OFFSET _u(0x00000020) +#define DMA_CH0_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH0_AL2_CTRL_RESET "-" +#define DMA_CH0_AL2_CTRL_MSB _u(31) +#define DMA_CH0_AL2_CTRL_LSB _u(0) +#define DMA_CH0_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL2_TRANS_COUNT +// Description : Alias for channel 0 TRANS_COUNT register +#define DMA_CH0_AL2_TRANS_COUNT_OFFSET _u(0x00000024) +#define DMA_CH0_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH0_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH0_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH0_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL2_READ_ADDR +// Description : Alias for channel 0 READ_ADDR register +#define DMA_CH0_AL2_READ_ADDR_OFFSET _u(0x00000028) +#define DMA_CH0_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_AL2_READ_ADDR_RESET "-" +#define DMA_CH0_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH0_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH0_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 0 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000002c) +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL3_CTRL +// Description : Alias for channel 0 CTRL register +#define DMA_CH0_AL3_CTRL_OFFSET _u(0x00000030) +#define DMA_CH0_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH0_AL3_CTRL_RESET "-" +#define DMA_CH0_AL3_CTRL_MSB _u(31) +#define DMA_CH0_AL3_CTRL_LSB _u(0) +#define DMA_CH0_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL3_WRITE_ADDR +// Description : Alias for channel 0 WRITE_ADDR register +#define DMA_CH0_AL3_WRITE_ADDR_OFFSET _u(0x00000034) +#define DMA_CH0_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH0_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH0_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH0_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL3_TRANS_COUNT +// Description : Alias for channel 0 TRANS_COUNT register +#define DMA_CH0_AL3_TRANS_COUNT_OFFSET _u(0x00000038) +#define DMA_CH0_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH0_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH0_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH0_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_AL3_READ_ADDR_TRIG +// Description : Alias for channel 0 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000003c) +#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_READ_ADDR +// Description : DMA Channel 1 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH1_READ_ADDR_OFFSET _u(0x00000040) +#define DMA_CH1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH1_READ_ADDR_MSB _u(31) +#define DMA_CH1_READ_ADDR_LSB _u(0) +#define DMA_CH1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_WRITE_ADDR +// Description : DMA Channel 1 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH1_WRITE_ADDR_OFFSET _u(0x00000044) +#define DMA_CH1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH1_WRITE_ADDR_MSB _u(31) +#define DMA_CH1_WRITE_ADDR_LSB _u(0) +#define DMA_CH1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_TRANS_COUNT +// Description : DMA Channel 1 Transfer Count +#define DMA_CH1_TRANS_COUNT_OFFSET _u(0x00000048) +#define DMA_CH1_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH1_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH1_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH1_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH1_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH1_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH1_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH1_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH1_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH1_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH1_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH1_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH1_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH1_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH1_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_CTRL_TRIG +// Description : DMA Channel 1 Control and Status +#define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c) +#define DMA_CH1_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH1_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH1_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH1_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH1_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH1_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH1_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH1_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH1_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH1_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH1_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH1_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH1_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH1_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL1_CTRL +// Description : Alias for channel 1 CTRL register +#define DMA_CH1_AL1_CTRL_OFFSET _u(0x00000050) +#define DMA_CH1_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH1_AL1_CTRL_RESET "-" +#define DMA_CH1_AL1_CTRL_MSB _u(31) +#define DMA_CH1_AL1_CTRL_LSB _u(0) +#define DMA_CH1_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL1_READ_ADDR +// Description : Alias for channel 1 READ_ADDR register +#define DMA_CH1_AL1_READ_ADDR_OFFSET _u(0x00000054) +#define DMA_CH1_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_AL1_READ_ADDR_RESET "-" +#define DMA_CH1_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH1_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH1_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL1_WRITE_ADDR +// Description : Alias for channel 1 WRITE_ADDR register +#define DMA_CH1_AL1_WRITE_ADDR_OFFSET _u(0x00000058) +#define DMA_CH1_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH1_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH1_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 1 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000005c) +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL2_CTRL +// Description : Alias for channel 1 CTRL register +#define DMA_CH1_AL2_CTRL_OFFSET _u(0x00000060) +#define DMA_CH1_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH1_AL2_CTRL_RESET "-" +#define DMA_CH1_AL2_CTRL_MSB _u(31) +#define DMA_CH1_AL2_CTRL_LSB _u(0) +#define DMA_CH1_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL2_TRANS_COUNT +// Description : Alias for channel 1 TRANS_COUNT register +#define DMA_CH1_AL2_TRANS_COUNT_OFFSET _u(0x00000064) +#define DMA_CH1_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH1_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH1_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH1_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL2_READ_ADDR +// Description : Alias for channel 1 READ_ADDR register +#define DMA_CH1_AL2_READ_ADDR_OFFSET _u(0x00000068) +#define DMA_CH1_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_AL2_READ_ADDR_RESET "-" +#define DMA_CH1_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH1_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH1_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 1 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000006c) +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL3_CTRL +// Description : Alias for channel 1 CTRL register +#define DMA_CH1_AL3_CTRL_OFFSET _u(0x00000070) +#define DMA_CH1_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH1_AL3_CTRL_RESET "-" +#define DMA_CH1_AL3_CTRL_MSB _u(31) +#define DMA_CH1_AL3_CTRL_LSB _u(0) +#define DMA_CH1_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL3_WRITE_ADDR +// Description : Alias for channel 1 WRITE_ADDR register +#define DMA_CH1_AL3_WRITE_ADDR_OFFSET _u(0x00000074) +#define DMA_CH1_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH1_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH1_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH1_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL3_TRANS_COUNT +// Description : Alias for channel 1 TRANS_COUNT register +#define DMA_CH1_AL3_TRANS_COUNT_OFFSET _u(0x00000078) +#define DMA_CH1_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH1_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH1_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH1_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH1_AL3_READ_ADDR_TRIG +// Description : Alias for channel 1 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000007c) +#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_READ_ADDR +// Description : DMA Channel 2 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH2_READ_ADDR_OFFSET _u(0x00000080) +#define DMA_CH2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH2_READ_ADDR_MSB _u(31) +#define DMA_CH2_READ_ADDR_LSB _u(0) +#define DMA_CH2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_WRITE_ADDR +// Description : DMA Channel 2 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH2_WRITE_ADDR_OFFSET _u(0x00000084) +#define DMA_CH2_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH2_WRITE_ADDR_MSB _u(31) +#define DMA_CH2_WRITE_ADDR_LSB _u(0) +#define DMA_CH2_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_TRANS_COUNT +// Description : DMA Channel 2 Transfer Count +#define DMA_CH2_TRANS_COUNT_OFFSET _u(0x00000088) +#define DMA_CH2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH2_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH2_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH2_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH2_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH2_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH2_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH2_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH2_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH2_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH2_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH2_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH2_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH2_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH2_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_CTRL_TRIG +// Description : DMA Channel 2 Control and Status +#define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c) +#define DMA_CH2_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH2_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH2_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH2_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH2_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH2_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH2_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH2_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH2_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH2_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH2_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH2_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH2_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH2_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL1_CTRL +// Description : Alias for channel 2 CTRL register +#define DMA_CH2_AL1_CTRL_OFFSET _u(0x00000090) +#define DMA_CH2_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH2_AL1_CTRL_RESET "-" +#define DMA_CH2_AL1_CTRL_MSB _u(31) +#define DMA_CH2_AL1_CTRL_LSB _u(0) +#define DMA_CH2_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL1_READ_ADDR +// Description : Alias for channel 2 READ_ADDR register +#define DMA_CH2_AL1_READ_ADDR_OFFSET _u(0x00000094) +#define DMA_CH2_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_AL1_READ_ADDR_RESET "-" +#define DMA_CH2_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH2_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH2_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL1_WRITE_ADDR +// Description : Alias for channel 2 WRITE_ADDR register +#define DMA_CH2_AL1_WRITE_ADDR_OFFSET _u(0x00000098) +#define DMA_CH2_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH2_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH2_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 2 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000009c) +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL2_CTRL +// Description : Alias for channel 2 CTRL register +#define DMA_CH2_AL2_CTRL_OFFSET _u(0x000000a0) +#define DMA_CH2_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH2_AL2_CTRL_RESET "-" +#define DMA_CH2_AL2_CTRL_MSB _u(31) +#define DMA_CH2_AL2_CTRL_LSB _u(0) +#define DMA_CH2_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL2_TRANS_COUNT +// Description : Alias for channel 2 TRANS_COUNT register +#define DMA_CH2_AL2_TRANS_COUNT_OFFSET _u(0x000000a4) +#define DMA_CH2_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH2_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH2_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH2_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL2_READ_ADDR +// Description : Alias for channel 2 READ_ADDR register +#define DMA_CH2_AL2_READ_ADDR_OFFSET _u(0x000000a8) +#define DMA_CH2_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_AL2_READ_ADDR_RESET "-" +#define DMA_CH2_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH2_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH2_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 2 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ac) +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL3_CTRL +// Description : Alias for channel 2 CTRL register +#define DMA_CH2_AL3_CTRL_OFFSET _u(0x000000b0) +#define DMA_CH2_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH2_AL3_CTRL_RESET "-" +#define DMA_CH2_AL3_CTRL_MSB _u(31) +#define DMA_CH2_AL3_CTRL_LSB _u(0) +#define DMA_CH2_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL3_WRITE_ADDR +// Description : Alias for channel 2 WRITE_ADDR register +#define DMA_CH2_AL3_WRITE_ADDR_OFFSET _u(0x000000b4) +#define DMA_CH2_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH2_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH2_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH2_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL3_TRANS_COUNT +// Description : Alias for channel 2 TRANS_COUNT register +#define DMA_CH2_AL3_TRANS_COUNT_OFFSET _u(0x000000b8) +#define DMA_CH2_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH2_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH2_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH2_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH2_AL3_READ_ADDR_TRIG +// Description : Alias for channel 2 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000bc) +#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_READ_ADDR +// Description : DMA Channel 3 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH3_READ_ADDR_OFFSET _u(0x000000c0) +#define DMA_CH3_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH3_READ_ADDR_MSB _u(31) +#define DMA_CH3_READ_ADDR_LSB _u(0) +#define DMA_CH3_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_WRITE_ADDR +// Description : DMA Channel 3 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH3_WRITE_ADDR_OFFSET _u(0x000000c4) +#define DMA_CH3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH3_WRITE_ADDR_MSB _u(31) +#define DMA_CH3_WRITE_ADDR_LSB _u(0) +#define DMA_CH3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_TRANS_COUNT +// Description : DMA Channel 3 Transfer Count +#define DMA_CH3_TRANS_COUNT_OFFSET _u(0x000000c8) +#define DMA_CH3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH3_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH3_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH3_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH3_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH3_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH3_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH3_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH3_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH3_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH3_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH3_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH3_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH3_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH3_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_CTRL_TRIG +// Description : DMA Channel 3 Control and Status +#define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc) +#define DMA_CH3_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH3_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH3_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH3_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH3_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH3_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH3_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH3_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH3_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH3_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH3_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH3_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH3_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH3_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL1_CTRL +// Description : Alias for channel 3 CTRL register +#define DMA_CH3_AL1_CTRL_OFFSET _u(0x000000d0) +#define DMA_CH3_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH3_AL1_CTRL_RESET "-" +#define DMA_CH3_AL1_CTRL_MSB _u(31) +#define DMA_CH3_AL1_CTRL_LSB _u(0) +#define DMA_CH3_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL1_READ_ADDR +// Description : Alias for channel 3 READ_ADDR register +#define DMA_CH3_AL1_READ_ADDR_OFFSET _u(0x000000d4) +#define DMA_CH3_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_AL1_READ_ADDR_RESET "-" +#define DMA_CH3_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH3_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH3_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL1_WRITE_ADDR +// Description : Alias for channel 3 WRITE_ADDR register +#define DMA_CH3_AL1_WRITE_ADDR_OFFSET _u(0x000000d8) +#define DMA_CH3_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH3_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH3_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 3 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000000dc) +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL2_CTRL +// Description : Alias for channel 3 CTRL register +#define DMA_CH3_AL2_CTRL_OFFSET _u(0x000000e0) +#define DMA_CH3_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH3_AL2_CTRL_RESET "-" +#define DMA_CH3_AL2_CTRL_MSB _u(31) +#define DMA_CH3_AL2_CTRL_LSB _u(0) +#define DMA_CH3_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL2_TRANS_COUNT +// Description : Alias for channel 3 TRANS_COUNT register +#define DMA_CH3_AL2_TRANS_COUNT_OFFSET _u(0x000000e4) +#define DMA_CH3_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH3_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH3_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH3_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL2_READ_ADDR +// Description : Alias for channel 3 READ_ADDR register +#define DMA_CH3_AL2_READ_ADDR_OFFSET _u(0x000000e8) +#define DMA_CH3_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_AL2_READ_ADDR_RESET "-" +#define DMA_CH3_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH3_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH3_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 3 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ec) +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL3_CTRL +// Description : Alias for channel 3 CTRL register +#define DMA_CH3_AL3_CTRL_OFFSET _u(0x000000f0) +#define DMA_CH3_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH3_AL3_CTRL_RESET "-" +#define DMA_CH3_AL3_CTRL_MSB _u(31) +#define DMA_CH3_AL3_CTRL_LSB _u(0) +#define DMA_CH3_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL3_WRITE_ADDR +// Description : Alias for channel 3 WRITE_ADDR register +#define DMA_CH3_AL3_WRITE_ADDR_OFFSET _u(0x000000f4) +#define DMA_CH3_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH3_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH3_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH3_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL3_TRANS_COUNT +// Description : Alias for channel 3 TRANS_COUNT register +#define DMA_CH3_AL3_TRANS_COUNT_OFFSET _u(0x000000f8) +#define DMA_CH3_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH3_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH3_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH3_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH3_AL3_READ_ADDR_TRIG +// Description : Alias for channel 3 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000fc) +#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_READ_ADDR +// Description : DMA Channel 4 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH4_READ_ADDR_OFFSET _u(0x00000100) +#define DMA_CH4_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH4_READ_ADDR_MSB _u(31) +#define DMA_CH4_READ_ADDR_LSB _u(0) +#define DMA_CH4_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_WRITE_ADDR +// Description : DMA Channel 4 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH4_WRITE_ADDR_OFFSET _u(0x00000104) +#define DMA_CH4_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH4_WRITE_ADDR_MSB _u(31) +#define DMA_CH4_WRITE_ADDR_LSB _u(0) +#define DMA_CH4_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_TRANS_COUNT +// Description : DMA Channel 4 Transfer Count +#define DMA_CH4_TRANS_COUNT_OFFSET _u(0x00000108) +#define DMA_CH4_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH4_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH4_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH4_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH4_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH4_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH4_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH4_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH4_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH4_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH4_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH4_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH4_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH4_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH4_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_CTRL_TRIG +// Description : DMA Channel 4 Control and Status +#define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c) +#define DMA_CH4_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH4_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH4_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH4_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH4_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH4_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH4_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH4_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH4_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH4_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH4_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH4_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH4_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH4_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL1_CTRL +// Description : Alias for channel 4 CTRL register +#define DMA_CH4_AL1_CTRL_OFFSET _u(0x00000110) +#define DMA_CH4_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH4_AL1_CTRL_RESET "-" +#define DMA_CH4_AL1_CTRL_MSB _u(31) +#define DMA_CH4_AL1_CTRL_LSB _u(0) +#define DMA_CH4_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL1_READ_ADDR +// Description : Alias for channel 4 READ_ADDR register +#define DMA_CH4_AL1_READ_ADDR_OFFSET _u(0x00000114) +#define DMA_CH4_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_AL1_READ_ADDR_RESET "-" +#define DMA_CH4_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH4_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH4_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL1_WRITE_ADDR +// Description : Alias for channel 4 WRITE_ADDR register +#define DMA_CH4_AL1_WRITE_ADDR_OFFSET _u(0x00000118) +#define DMA_CH4_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH4_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH4_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 4 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000011c) +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL2_CTRL +// Description : Alias for channel 4 CTRL register +#define DMA_CH4_AL2_CTRL_OFFSET _u(0x00000120) +#define DMA_CH4_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH4_AL2_CTRL_RESET "-" +#define DMA_CH4_AL2_CTRL_MSB _u(31) +#define DMA_CH4_AL2_CTRL_LSB _u(0) +#define DMA_CH4_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL2_TRANS_COUNT +// Description : Alias for channel 4 TRANS_COUNT register +#define DMA_CH4_AL2_TRANS_COUNT_OFFSET _u(0x00000124) +#define DMA_CH4_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH4_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH4_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH4_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL2_READ_ADDR +// Description : Alias for channel 4 READ_ADDR register +#define DMA_CH4_AL2_READ_ADDR_OFFSET _u(0x00000128) +#define DMA_CH4_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_AL2_READ_ADDR_RESET "-" +#define DMA_CH4_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH4_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH4_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 4 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000012c) +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL3_CTRL +// Description : Alias for channel 4 CTRL register +#define DMA_CH4_AL3_CTRL_OFFSET _u(0x00000130) +#define DMA_CH4_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH4_AL3_CTRL_RESET "-" +#define DMA_CH4_AL3_CTRL_MSB _u(31) +#define DMA_CH4_AL3_CTRL_LSB _u(0) +#define DMA_CH4_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL3_WRITE_ADDR +// Description : Alias for channel 4 WRITE_ADDR register +#define DMA_CH4_AL3_WRITE_ADDR_OFFSET _u(0x00000134) +#define DMA_CH4_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH4_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH4_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH4_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL3_TRANS_COUNT +// Description : Alias for channel 4 TRANS_COUNT register +#define DMA_CH4_AL3_TRANS_COUNT_OFFSET _u(0x00000138) +#define DMA_CH4_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH4_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH4_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH4_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH4_AL3_READ_ADDR_TRIG +// Description : Alias for channel 4 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000013c) +#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_READ_ADDR +// Description : DMA Channel 5 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH5_READ_ADDR_OFFSET _u(0x00000140) +#define DMA_CH5_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH5_READ_ADDR_MSB _u(31) +#define DMA_CH5_READ_ADDR_LSB _u(0) +#define DMA_CH5_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_WRITE_ADDR +// Description : DMA Channel 5 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH5_WRITE_ADDR_OFFSET _u(0x00000144) +#define DMA_CH5_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH5_WRITE_ADDR_MSB _u(31) +#define DMA_CH5_WRITE_ADDR_LSB _u(0) +#define DMA_CH5_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_TRANS_COUNT +// Description : DMA Channel 5 Transfer Count +#define DMA_CH5_TRANS_COUNT_OFFSET _u(0x00000148) +#define DMA_CH5_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH5_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH5_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH5_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH5_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH5_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH5_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH5_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH5_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH5_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH5_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH5_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH5_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH5_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH5_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_CTRL_TRIG +// Description : DMA Channel 5 Control and Status +#define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c) +#define DMA_CH5_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH5_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH5_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH5_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH5_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH5_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH5_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH5_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH5_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH5_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH5_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH5_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH5_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH5_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL1_CTRL +// Description : Alias for channel 5 CTRL register +#define DMA_CH5_AL1_CTRL_OFFSET _u(0x00000150) +#define DMA_CH5_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH5_AL1_CTRL_RESET "-" +#define DMA_CH5_AL1_CTRL_MSB _u(31) +#define DMA_CH5_AL1_CTRL_LSB _u(0) +#define DMA_CH5_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL1_READ_ADDR +// Description : Alias for channel 5 READ_ADDR register +#define DMA_CH5_AL1_READ_ADDR_OFFSET _u(0x00000154) +#define DMA_CH5_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_AL1_READ_ADDR_RESET "-" +#define DMA_CH5_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH5_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH5_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL1_WRITE_ADDR +// Description : Alias for channel 5 WRITE_ADDR register +#define DMA_CH5_AL1_WRITE_ADDR_OFFSET _u(0x00000158) +#define DMA_CH5_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH5_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH5_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 5 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000015c) +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL2_CTRL +// Description : Alias for channel 5 CTRL register +#define DMA_CH5_AL2_CTRL_OFFSET _u(0x00000160) +#define DMA_CH5_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH5_AL2_CTRL_RESET "-" +#define DMA_CH5_AL2_CTRL_MSB _u(31) +#define DMA_CH5_AL2_CTRL_LSB _u(0) +#define DMA_CH5_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL2_TRANS_COUNT +// Description : Alias for channel 5 TRANS_COUNT register +#define DMA_CH5_AL2_TRANS_COUNT_OFFSET _u(0x00000164) +#define DMA_CH5_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH5_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH5_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH5_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL2_READ_ADDR +// Description : Alias for channel 5 READ_ADDR register +#define DMA_CH5_AL2_READ_ADDR_OFFSET _u(0x00000168) +#define DMA_CH5_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_AL2_READ_ADDR_RESET "-" +#define DMA_CH5_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH5_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH5_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 5 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000016c) +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL3_CTRL +// Description : Alias for channel 5 CTRL register +#define DMA_CH5_AL3_CTRL_OFFSET _u(0x00000170) +#define DMA_CH5_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH5_AL3_CTRL_RESET "-" +#define DMA_CH5_AL3_CTRL_MSB _u(31) +#define DMA_CH5_AL3_CTRL_LSB _u(0) +#define DMA_CH5_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL3_WRITE_ADDR +// Description : Alias for channel 5 WRITE_ADDR register +#define DMA_CH5_AL3_WRITE_ADDR_OFFSET _u(0x00000174) +#define DMA_CH5_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH5_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH5_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH5_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL3_TRANS_COUNT +// Description : Alias for channel 5 TRANS_COUNT register +#define DMA_CH5_AL3_TRANS_COUNT_OFFSET _u(0x00000178) +#define DMA_CH5_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH5_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH5_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH5_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH5_AL3_READ_ADDR_TRIG +// Description : Alias for channel 5 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000017c) +#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_READ_ADDR +// Description : DMA Channel 6 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH6_READ_ADDR_OFFSET _u(0x00000180) +#define DMA_CH6_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH6_READ_ADDR_MSB _u(31) +#define DMA_CH6_READ_ADDR_LSB _u(0) +#define DMA_CH6_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_WRITE_ADDR +// Description : DMA Channel 6 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH6_WRITE_ADDR_OFFSET _u(0x00000184) +#define DMA_CH6_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH6_WRITE_ADDR_MSB _u(31) +#define DMA_CH6_WRITE_ADDR_LSB _u(0) +#define DMA_CH6_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_TRANS_COUNT +// Description : DMA Channel 6 Transfer Count +#define DMA_CH6_TRANS_COUNT_OFFSET _u(0x00000188) +#define DMA_CH6_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH6_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH6_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH6_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH6_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH6_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH6_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH6_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH6_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH6_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH6_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH6_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH6_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH6_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH6_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_CTRL_TRIG +// Description : DMA Channel 6 Control and Status +#define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c) +#define DMA_CH6_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH6_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH6_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH6_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH6_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH6_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH6_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH6_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH6_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH6_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH6_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH6_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH6_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH6_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL1_CTRL +// Description : Alias for channel 6 CTRL register +#define DMA_CH6_AL1_CTRL_OFFSET _u(0x00000190) +#define DMA_CH6_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH6_AL1_CTRL_RESET "-" +#define DMA_CH6_AL1_CTRL_MSB _u(31) +#define DMA_CH6_AL1_CTRL_LSB _u(0) +#define DMA_CH6_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL1_READ_ADDR +// Description : Alias for channel 6 READ_ADDR register +#define DMA_CH6_AL1_READ_ADDR_OFFSET _u(0x00000194) +#define DMA_CH6_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_AL1_READ_ADDR_RESET "-" +#define DMA_CH6_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH6_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH6_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL1_WRITE_ADDR +// Description : Alias for channel 6 WRITE_ADDR register +#define DMA_CH6_AL1_WRITE_ADDR_OFFSET _u(0x00000198) +#define DMA_CH6_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH6_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH6_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 6 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000019c) +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL2_CTRL +// Description : Alias for channel 6 CTRL register +#define DMA_CH6_AL2_CTRL_OFFSET _u(0x000001a0) +#define DMA_CH6_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH6_AL2_CTRL_RESET "-" +#define DMA_CH6_AL2_CTRL_MSB _u(31) +#define DMA_CH6_AL2_CTRL_LSB _u(0) +#define DMA_CH6_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL2_TRANS_COUNT +// Description : Alias for channel 6 TRANS_COUNT register +#define DMA_CH6_AL2_TRANS_COUNT_OFFSET _u(0x000001a4) +#define DMA_CH6_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH6_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH6_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH6_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL2_READ_ADDR +// Description : Alias for channel 6 READ_ADDR register +#define DMA_CH6_AL2_READ_ADDR_OFFSET _u(0x000001a8) +#define DMA_CH6_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_AL2_READ_ADDR_RESET "-" +#define DMA_CH6_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH6_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH6_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 6 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ac) +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL3_CTRL +// Description : Alias for channel 6 CTRL register +#define DMA_CH6_AL3_CTRL_OFFSET _u(0x000001b0) +#define DMA_CH6_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH6_AL3_CTRL_RESET "-" +#define DMA_CH6_AL3_CTRL_MSB _u(31) +#define DMA_CH6_AL3_CTRL_LSB _u(0) +#define DMA_CH6_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL3_WRITE_ADDR +// Description : Alias for channel 6 WRITE_ADDR register +#define DMA_CH6_AL3_WRITE_ADDR_OFFSET _u(0x000001b4) +#define DMA_CH6_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH6_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH6_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH6_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL3_TRANS_COUNT +// Description : Alias for channel 6 TRANS_COUNT register +#define DMA_CH6_AL3_TRANS_COUNT_OFFSET _u(0x000001b8) +#define DMA_CH6_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH6_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH6_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH6_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH6_AL3_READ_ADDR_TRIG +// Description : Alias for channel 6 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001bc) +#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_READ_ADDR +// Description : DMA Channel 7 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH7_READ_ADDR_OFFSET _u(0x000001c0) +#define DMA_CH7_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH7_READ_ADDR_MSB _u(31) +#define DMA_CH7_READ_ADDR_LSB _u(0) +#define DMA_CH7_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_WRITE_ADDR +// Description : DMA Channel 7 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH7_WRITE_ADDR_OFFSET _u(0x000001c4) +#define DMA_CH7_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH7_WRITE_ADDR_MSB _u(31) +#define DMA_CH7_WRITE_ADDR_LSB _u(0) +#define DMA_CH7_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_TRANS_COUNT +// Description : DMA Channel 7 Transfer Count +#define DMA_CH7_TRANS_COUNT_OFFSET _u(0x000001c8) +#define DMA_CH7_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH7_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH7_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH7_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH7_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH7_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH7_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH7_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH7_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH7_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH7_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH7_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH7_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH7_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH7_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_CTRL_TRIG +// Description : DMA Channel 7 Control and Status +#define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc) +#define DMA_CH7_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH7_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH7_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH7_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH7_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH7_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH7_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH7_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH7_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH7_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH7_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH7_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH7_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH7_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL1_CTRL +// Description : Alias for channel 7 CTRL register +#define DMA_CH7_AL1_CTRL_OFFSET _u(0x000001d0) +#define DMA_CH7_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH7_AL1_CTRL_RESET "-" +#define DMA_CH7_AL1_CTRL_MSB _u(31) +#define DMA_CH7_AL1_CTRL_LSB _u(0) +#define DMA_CH7_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL1_READ_ADDR +// Description : Alias for channel 7 READ_ADDR register +#define DMA_CH7_AL1_READ_ADDR_OFFSET _u(0x000001d4) +#define DMA_CH7_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_AL1_READ_ADDR_RESET "-" +#define DMA_CH7_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH7_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH7_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL1_WRITE_ADDR +// Description : Alias for channel 7 WRITE_ADDR register +#define DMA_CH7_AL1_WRITE_ADDR_OFFSET _u(0x000001d8) +#define DMA_CH7_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH7_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH7_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 7 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000001dc) +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL2_CTRL +// Description : Alias for channel 7 CTRL register +#define DMA_CH7_AL2_CTRL_OFFSET _u(0x000001e0) +#define DMA_CH7_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH7_AL2_CTRL_RESET "-" +#define DMA_CH7_AL2_CTRL_MSB _u(31) +#define DMA_CH7_AL2_CTRL_LSB _u(0) +#define DMA_CH7_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL2_TRANS_COUNT +// Description : Alias for channel 7 TRANS_COUNT register +#define DMA_CH7_AL2_TRANS_COUNT_OFFSET _u(0x000001e4) +#define DMA_CH7_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH7_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH7_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH7_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL2_READ_ADDR +// Description : Alias for channel 7 READ_ADDR register +#define DMA_CH7_AL2_READ_ADDR_OFFSET _u(0x000001e8) +#define DMA_CH7_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_AL2_READ_ADDR_RESET "-" +#define DMA_CH7_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH7_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH7_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 7 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ec) +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL3_CTRL +// Description : Alias for channel 7 CTRL register +#define DMA_CH7_AL3_CTRL_OFFSET _u(0x000001f0) +#define DMA_CH7_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH7_AL3_CTRL_RESET "-" +#define DMA_CH7_AL3_CTRL_MSB _u(31) +#define DMA_CH7_AL3_CTRL_LSB _u(0) +#define DMA_CH7_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL3_WRITE_ADDR +// Description : Alias for channel 7 WRITE_ADDR register +#define DMA_CH7_AL3_WRITE_ADDR_OFFSET _u(0x000001f4) +#define DMA_CH7_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH7_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH7_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH7_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL3_TRANS_COUNT +// Description : Alias for channel 7 TRANS_COUNT register +#define DMA_CH7_AL3_TRANS_COUNT_OFFSET _u(0x000001f8) +#define DMA_CH7_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH7_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH7_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH7_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH7_AL3_READ_ADDR_TRIG +// Description : Alias for channel 7 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001fc) +#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_READ_ADDR +// Description : DMA Channel 8 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH8_READ_ADDR_OFFSET _u(0x00000200) +#define DMA_CH8_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH8_READ_ADDR_MSB _u(31) +#define DMA_CH8_READ_ADDR_LSB _u(0) +#define DMA_CH8_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_WRITE_ADDR +// Description : DMA Channel 8 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH8_WRITE_ADDR_OFFSET _u(0x00000204) +#define DMA_CH8_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH8_WRITE_ADDR_MSB _u(31) +#define DMA_CH8_WRITE_ADDR_LSB _u(0) +#define DMA_CH8_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_TRANS_COUNT +// Description : DMA Channel 8 Transfer Count +#define DMA_CH8_TRANS_COUNT_OFFSET _u(0x00000208) +#define DMA_CH8_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH8_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH8_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH8_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH8_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH8_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH8_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH8_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH8_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH8_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH8_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH8_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH8_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH8_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH8_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_CTRL_TRIG +// Description : DMA Channel 8 Control and Status +#define DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c) +#define DMA_CH8_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH8_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH8_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH8_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH8_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH8_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH8_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH8_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH8_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH8_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH8_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH8_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH8_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH8_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH8_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH8_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL1_CTRL +// Description : Alias for channel 8 CTRL register +#define DMA_CH8_AL1_CTRL_OFFSET _u(0x00000210) +#define DMA_CH8_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH8_AL1_CTRL_RESET "-" +#define DMA_CH8_AL1_CTRL_MSB _u(31) +#define DMA_CH8_AL1_CTRL_LSB _u(0) +#define DMA_CH8_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL1_READ_ADDR +// Description : Alias for channel 8 READ_ADDR register +#define DMA_CH8_AL1_READ_ADDR_OFFSET _u(0x00000214) +#define DMA_CH8_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_AL1_READ_ADDR_RESET "-" +#define DMA_CH8_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH8_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH8_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL1_WRITE_ADDR +// Description : Alias for channel 8 WRITE_ADDR register +#define DMA_CH8_AL1_WRITE_ADDR_OFFSET _u(0x00000218) +#define DMA_CH8_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH8_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH8_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 8 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000021c) +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL2_CTRL +// Description : Alias for channel 8 CTRL register +#define DMA_CH8_AL2_CTRL_OFFSET _u(0x00000220) +#define DMA_CH8_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH8_AL2_CTRL_RESET "-" +#define DMA_CH8_AL2_CTRL_MSB _u(31) +#define DMA_CH8_AL2_CTRL_LSB _u(0) +#define DMA_CH8_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL2_TRANS_COUNT +// Description : Alias for channel 8 TRANS_COUNT register +#define DMA_CH8_AL2_TRANS_COUNT_OFFSET _u(0x00000224) +#define DMA_CH8_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH8_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH8_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH8_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL2_READ_ADDR +// Description : Alias for channel 8 READ_ADDR register +#define DMA_CH8_AL2_READ_ADDR_OFFSET _u(0x00000228) +#define DMA_CH8_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_AL2_READ_ADDR_RESET "-" +#define DMA_CH8_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH8_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH8_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 8 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000022c) +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL3_CTRL +// Description : Alias for channel 8 CTRL register +#define DMA_CH8_AL3_CTRL_OFFSET _u(0x00000230) +#define DMA_CH8_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH8_AL3_CTRL_RESET "-" +#define DMA_CH8_AL3_CTRL_MSB _u(31) +#define DMA_CH8_AL3_CTRL_LSB _u(0) +#define DMA_CH8_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL3_WRITE_ADDR +// Description : Alias for channel 8 WRITE_ADDR register +#define DMA_CH8_AL3_WRITE_ADDR_OFFSET _u(0x00000234) +#define DMA_CH8_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH8_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH8_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH8_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL3_TRANS_COUNT +// Description : Alias for channel 8 TRANS_COUNT register +#define DMA_CH8_AL3_TRANS_COUNT_OFFSET _u(0x00000238) +#define DMA_CH8_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH8_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH8_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH8_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH8_AL3_READ_ADDR_TRIG +// Description : Alias for channel 8 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000023c) +#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_READ_ADDR +// Description : DMA Channel 9 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH9_READ_ADDR_OFFSET _u(0x00000240) +#define DMA_CH9_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH9_READ_ADDR_MSB _u(31) +#define DMA_CH9_READ_ADDR_LSB _u(0) +#define DMA_CH9_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_WRITE_ADDR +// Description : DMA Channel 9 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH9_WRITE_ADDR_OFFSET _u(0x00000244) +#define DMA_CH9_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH9_WRITE_ADDR_MSB _u(31) +#define DMA_CH9_WRITE_ADDR_LSB _u(0) +#define DMA_CH9_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_TRANS_COUNT +// Description : DMA Channel 9 Transfer Count +#define DMA_CH9_TRANS_COUNT_OFFSET _u(0x00000248) +#define DMA_CH9_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH9_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH9_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH9_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH9_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH9_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH9_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH9_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH9_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH9_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH9_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH9_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH9_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH9_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH9_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_CTRL_TRIG +// Description : DMA Channel 9 Control and Status +#define DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c) +#define DMA_CH9_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH9_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH9_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH9_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH9_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH9_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH9_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH9_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH9_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH9_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH9_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH9_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH9_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH9_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH9_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH9_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL1_CTRL +// Description : Alias for channel 9 CTRL register +#define DMA_CH9_AL1_CTRL_OFFSET _u(0x00000250) +#define DMA_CH9_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH9_AL1_CTRL_RESET "-" +#define DMA_CH9_AL1_CTRL_MSB _u(31) +#define DMA_CH9_AL1_CTRL_LSB _u(0) +#define DMA_CH9_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL1_READ_ADDR +// Description : Alias for channel 9 READ_ADDR register +#define DMA_CH9_AL1_READ_ADDR_OFFSET _u(0x00000254) +#define DMA_CH9_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_AL1_READ_ADDR_RESET "-" +#define DMA_CH9_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH9_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH9_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL1_WRITE_ADDR +// Description : Alias for channel 9 WRITE_ADDR register +#define DMA_CH9_AL1_WRITE_ADDR_OFFSET _u(0x00000258) +#define DMA_CH9_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH9_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH9_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 9 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000025c) +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL2_CTRL +// Description : Alias for channel 9 CTRL register +#define DMA_CH9_AL2_CTRL_OFFSET _u(0x00000260) +#define DMA_CH9_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH9_AL2_CTRL_RESET "-" +#define DMA_CH9_AL2_CTRL_MSB _u(31) +#define DMA_CH9_AL2_CTRL_LSB _u(0) +#define DMA_CH9_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL2_TRANS_COUNT +// Description : Alias for channel 9 TRANS_COUNT register +#define DMA_CH9_AL2_TRANS_COUNT_OFFSET _u(0x00000264) +#define DMA_CH9_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH9_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH9_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH9_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL2_READ_ADDR +// Description : Alias for channel 9 READ_ADDR register +#define DMA_CH9_AL2_READ_ADDR_OFFSET _u(0x00000268) +#define DMA_CH9_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_AL2_READ_ADDR_RESET "-" +#define DMA_CH9_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH9_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH9_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 9 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000026c) +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL3_CTRL +// Description : Alias for channel 9 CTRL register +#define DMA_CH9_AL3_CTRL_OFFSET _u(0x00000270) +#define DMA_CH9_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH9_AL3_CTRL_RESET "-" +#define DMA_CH9_AL3_CTRL_MSB _u(31) +#define DMA_CH9_AL3_CTRL_LSB _u(0) +#define DMA_CH9_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL3_WRITE_ADDR +// Description : Alias for channel 9 WRITE_ADDR register +#define DMA_CH9_AL3_WRITE_ADDR_OFFSET _u(0x00000274) +#define DMA_CH9_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH9_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH9_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH9_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL3_TRANS_COUNT +// Description : Alias for channel 9 TRANS_COUNT register +#define DMA_CH9_AL3_TRANS_COUNT_OFFSET _u(0x00000278) +#define DMA_CH9_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH9_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH9_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH9_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH9_AL3_READ_ADDR_TRIG +// Description : Alias for channel 9 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000027c) +#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_READ_ADDR +// Description : DMA Channel 10 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH10_READ_ADDR_OFFSET _u(0x00000280) +#define DMA_CH10_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH10_READ_ADDR_MSB _u(31) +#define DMA_CH10_READ_ADDR_LSB _u(0) +#define DMA_CH10_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_WRITE_ADDR +// Description : DMA Channel 10 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH10_WRITE_ADDR_OFFSET _u(0x00000284) +#define DMA_CH10_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH10_WRITE_ADDR_MSB _u(31) +#define DMA_CH10_WRITE_ADDR_LSB _u(0) +#define DMA_CH10_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_TRANS_COUNT +// Description : DMA Channel 10 Transfer Count +#define DMA_CH10_TRANS_COUNT_OFFSET _u(0x00000288) +#define DMA_CH10_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH10_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH10_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH10_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH10_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH10_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH10_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH10_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH10_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH10_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH10_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH10_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH10_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH10_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH10_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_CTRL_TRIG +// Description : DMA Channel 10 Control and Status +#define DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c) +#define DMA_CH10_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH10_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH10_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH10_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH10_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH10_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH10_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH10_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH10_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH10_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH10_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH10_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH10_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH10_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH10_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH10_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL1_CTRL +// Description : Alias for channel 10 CTRL register +#define DMA_CH10_AL1_CTRL_OFFSET _u(0x00000290) +#define DMA_CH10_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH10_AL1_CTRL_RESET "-" +#define DMA_CH10_AL1_CTRL_MSB _u(31) +#define DMA_CH10_AL1_CTRL_LSB _u(0) +#define DMA_CH10_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL1_READ_ADDR +// Description : Alias for channel 10 READ_ADDR register +#define DMA_CH10_AL1_READ_ADDR_OFFSET _u(0x00000294) +#define DMA_CH10_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_AL1_READ_ADDR_RESET "-" +#define DMA_CH10_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH10_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH10_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL1_WRITE_ADDR +// Description : Alias for channel 10 WRITE_ADDR register +#define DMA_CH10_AL1_WRITE_ADDR_OFFSET _u(0x00000298) +#define DMA_CH10_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH10_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH10_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 10 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000029c) +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL2_CTRL +// Description : Alias for channel 10 CTRL register +#define DMA_CH10_AL2_CTRL_OFFSET _u(0x000002a0) +#define DMA_CH10_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH10_AL2_CTRL_RESET "-" +#define DMA_CH10_AL2_CTRL_MSB _u(31) +#define DMA_CH10_AL2_CTRL_LSB _u(0) +#define DMA_CH10_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL2_TRANS_COUNT +// Description : Alias for channel 10 TRANS_COUNT register +#define DMA_CH10_AL2_TRANS_COUNT_OFFSET _u(0x000002a4) +#define DMA_CH10_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH10_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH10_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH10_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL2_READ_ADDR +// Description : Alias for channel 10 READ_ADDR register +#define DMA_CH10_AL2_READ_ADDR_OFFSET _u(0x000002a8) +#define DMA_CH10_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_AL2_READ_ADDR_RESET "-" +#define DMA_CH10_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH10_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH10_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 10 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ac) +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL3_CTRL +// Description : Alias for channel 10 CTRL register +#define DMA_CH10_AL3_CTRL_OFFSET _u(0x000002b0) +#define DMA_CH10_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH10_AL3_CTRL_RESET "-" +#define DMA_CH10_AL3_CTRL_MSB _u(31) +#define DMA_CH10_AL3_CTRL_LSB _u(0) +#define DMA_CH10_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL3_WRITE_ADDR +// Description : Alias for channel 10 WRITE_ADDR register +#define DMA_CH10_AL3_WRITE_ADDR_OFFSET _u(0x000002b4) +#define DMA_CH10_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH10_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH10_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH10_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL3_TRANS_COUNT +// Description : Alias for channel 10 TRANS_COUNT register +#define DMA_CH10_AL3_TRANS_COUNT_OFFSET _u(0x000002b8) +#define DMA_CH10_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH10_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH10_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH10_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH10_AL3_READ_ADDR_TRIG +// Description : Alias for channel 10 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002bc) +#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_READ_ADDR +// Description : DMA Channel 11 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH11_READ_ADDR_OFFSET _u(0x000002c0) +#define DMA_CH11_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH11_READ_ADDR_MSB _u(31) +#define DMA_CH11_READ_ADDR_LSB _u(0) +#define DMA_CH11_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_WRITE_ADDR +// Description : DMA Channel 11 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH11_WRITE_ADDR_OFFSET _u(0x000002c4) +#define DMA_CH11_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH11_WRITE_ADDR_MSB _u(31) +#define DMA_CH11_WRITE_ADDR_LSB _u(0) +#define DMA_CH11_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_TRANS_COUNT +// Description : DMA Channel 11 Transfer Count +#define DMA_CH11_TRANS_COUNT_OFFSET _u(0x000002c8) +#define DMA_CH11_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH11_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH11_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH11_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH11_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH11_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH11_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH11_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH11_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH11_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH11_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH11_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH11_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH11_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH11_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_CTRL_TRIG +// Description : DMA Channel 11 Control and Status +#define DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc) +#define DMA_CH11_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH11_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH11_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH11_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH11_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH11_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH11_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH11_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH11_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH11_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH11_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH11_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH11_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH11_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH11_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH11_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL1_CTRL +// Description : Alias for channel 11 CTRL register +#define DMA_CH11_AL1_CTRL_OFFSET _u(0x000002d0) +#define DMA_CH11_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH11_AL1_CTRL_RESET "-" +#define DMA_CH11_AL1_CTRL_MSB _u(31) +#define DMA_CH11_AL1_CTRL_LSB _u(0) +#define DMA_CH11_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL1_READ_ADDR +// Description : Alias for channel 11 READ_ADDR register +#define DMA_CH11_AL1_READ_ADDR_OFFSET _u(0x000002d4) +#define DMA_CH11_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_AL1_READ_ADDR_RESET "-" +#define DMA_CH11_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH11_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH11_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL1_WRITE_ADDR +// Description : Alias for channel 11 WRITE_ADDR register +#define DMA_CH11_AL1_WRITE_ADDR_OFFSET _u(0x000002d8) +#define DMA_CH11_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH11_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH11_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 11 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000002dc) +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL2_CTRL +// Description : Alias for channel 11 CTRL register +#define DMA_CH11_AL2_CTRL_OFFSET _u(0x000002e0) +#define DMA_CH11_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH11_AL2_CTRL_RESET "-" +#define DMA_CH11_AL2_CTRL_MSB _u(31) +#define DMA_CH11_AL2_CTRL_LSB _u(0) +#define DMA_CH11_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL2_TRANS_COUNT +// Description : Alias for channel 11 TRANS_COUNT register +#define DMA_CH11_AL2_TRANS_COUNT_OFFSET _u(0x000002e4) +#define DMA_CH11_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH11_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH11_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH11_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL2_READ_ADDR +// Description : Alias for channel 11 READ_ADDR register +#define DMA_CH11_AL2_READ_ADDR_OFFSET _u(0x000002e8) +#define DMA_CH11_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_AL2_READ_ADDR_RESET "-" +#define DMA_CH11_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH11_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH11_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 11 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ec) +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL3_CTRL +// Description : Alias for channel 11 CTRL register +#define DMA_CH11_AL3_CTRL_OFFSET _u(0x000002f0) +#define DMA_CH11_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH11_AL3_CTRL_RESET "-" +#define DMA_CH11_AL3_CTRL_MSB _u(31) +#define DMA_CH11_AL3_CTRL_LSB _u(0) +#define DMA_CH11_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL3_WRITE_ADDR +// Description : Alias for channel 11 WRITE_ADDR register +#define DMA_CH11_AL3_WRITE_ADDR_OFFSET _u(0x000002f4) +#define DMA_CH11_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH11_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH11_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH11_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL3_TRANS_COUNT +// Description : Alias for channel 11 TRANS_COUNT register +#define DMA_CH11_AL3_TRANS_COUNT_OFFSET _u(0x000002f8) +#define DMA_CH11_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH11_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH11_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH11_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH11_AL3_READ_ADDR_TRIG +// Description : Alias for channel 11 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002fc) +#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_READ_ADDR +// Description : DMA Channel 12 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH12_READ_ADDR_OFFSET _u(0x00000300) +#define DMA_CH12_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH12_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH12_READ_ADDR_MSB _u(31) +#define DMA_CH12_READ_ADDR_LSB _u(0) +#define DMA_CH12_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_WRITE_ADDR +// Description : DMA Channel 12 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH12_WRITE_ADDR_OFFSET _u(0x00000304) +#define DMA_CH12_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH12_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH12_WRITE_ADDR_MSB _u(31) +#define DMA_CH12_WRITE_ADDR_LSB _u(0) +#define DMA_CH12_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_TRANS_COUNT +// Description : DMA Channel 12 Transfer Count +#define DMA_CH12_TRANS_COUNT_OFFSET _u(0x00000308) +#define DMA_CH12_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH12_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH12_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH12_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH12_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH12_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH12_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH12_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH12_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH12_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH12_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH12_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH12_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH12_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH12_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_CTRL_TRIG +// Description : DMA Channel 12 Control and Status +#define DMA_CH12_CTRL_TRIG_OFFSET _u(0x0000030c) +#define DMA_CH12_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH12_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH12_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH12_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH12_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH12_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH12_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH12_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH12_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH12_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH12_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH12_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH12_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH12_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH12_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH12_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH12_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH12_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH12_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH12_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH12_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH12_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH12_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH12_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH12_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH12_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH12_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH12_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH12_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH12_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH12_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH12_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH12_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH12_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH12_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH12_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH12_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH12_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH12_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH12_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH12_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH12_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH12_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH12_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH12_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH12_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL1_CTRL +// Description : Alias for channel 12 CTRL register +#define DMA_CH12_AL1_CTRL_OFFSET _u(0x00000310) +#define DMA_CH12_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH12_AL1_CTRL_RESET "-" +#define DMA_CH12_AL1_CTRL_MSB _u(31) +#define DMA_CH12_AL1_CTRL_LSB _u(0) +#define DMA_CH12_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL1_READ_ADDR +// Description : Alias for channel 12 READ_ADDR register +#define DMA_CH12_AL1_READ_ADDR_OFFSET _u(0x00000314) +#define DMA_CH12_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH12_AL1_READ_ADDR_RESET "-" +#define DMA_CH12_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH12_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH12_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL1_WRITE_ADDR +// Description : Alias for channel 12 WRITE_ADDR register +#define DMA_CH12_AL1_WRITE_ADDR_OFFSET _u(0x00000318) +#define DMA_CH12_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH12_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH12_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH12_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH12_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 12 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH12_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000031c) +#define DMA_CH12_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH12_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH12_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH12_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH12_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL2_CTRL +// Description : Alias for channel 12 CTRL register +#define DMA_CH12_AL2_CTRL_OFFSET _u(0x00000320) +#define DMA_CH12_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH12_AL2_CTRL_RESET "-" +#define DMA_CH12_AL2_CTRL_MSB _u(31) +#define DMA_CH12_AL2_CTRL_LSB _u(0) +#define DMA_CH12_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL2_TRANS_COUNT +// Description : Alias for channel 12 TRANS_COUNT register +#define DMA_CH12_AL2_TRANS_COUNT_OFFSET _u(0x00000324) +#define DMA_CH12_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH12_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH12_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH12_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH12_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL2_READ_ADDR +// Description : Alias for channel 12 READ_ADDR register +#define DMA_CH12_AL2_READ_ADDR_OFFSET _u(0x00000328) +#define DMA_CH12_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH12_AL2_READ_ADDR_RESET "-" +#define DMA_CH12_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH12_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH12_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 12 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH12_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000032c) +#define DMA_CH12_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH12_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH12_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH12_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH12_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL3_CTRL +// Description : Alias for channel 12 CTRL register +#define DMA_CH12_AL3_CTRL_OFFSET _u(0x00000330) +#define DMA_CH12_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH12_AL3_CTRL_RESET "-" +#define DMA_CH12_AL3_CTRL_MSB _u(31) +#define DMA_CH12_AL3_CTRL_LSB _u(0) +#define DMA_CH12_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL3_WRITE_ADDR +// Description : Alias for channel 12 WRITE_ADDR register +#define DMA_CH12_AL3_WRITE_ADDR_OFFSET _u(0x00000334) +#define DMA_CH12_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH12_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH12_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH12_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH12_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL3_TRANS_COUNT +// Description : Alias for channel 12 TRANS_COUNT register +#define DMA_CH12_AL3_TRANS_COUNT_OFFSET _u(0x00000338) +#define DMA_CH12_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH12_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH12_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH12_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH12_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH12_AL3_READ_ADDR_TRIG +// Description : Alias for channel 12 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH12_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000033c) +#define DMA_CH12_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH12_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH12_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH12_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH12_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_READ_ADDR +// Description : DMA Channel 13 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH13_READ_ADDR_OFFSET _u(0x00000340) +#define DMA_CH13_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH13_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH13_READ_ADDR_MSB _u(31) +#define DMA_CH13_READ_ADDR_LSB _u(0) +#define DMA_CH13_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_WRITE_ADDR +// Description : DMA Channel 13 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH13_WRITE_ADDR_OFFSET _u(0x00000344) +#define DMA_CH13_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH13_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH13_WRITE_ADDR_MSB _u(31) +#define DMA_CH13_WRITE_ADDR_LSB _u(0) +#define DMA_CH13_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_TRANS_COUNT +// Description : DMA Channel 13 Transfer Count +#define DMA_CH13_TRANS_COUNT_OFFSET _u(0x00000348) +#define DMA_CH13_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH13_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH13_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH13_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH13_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH13_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH13_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH13_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH13_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH13_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH13_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH13_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH13_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH13_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH13_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_CTRL_TRIG +// Description : DMA Channel 13 Control and Status +#define DMA_CH13_CTRL_TRIG_OFFSET _u(0x0000034c) +#define DMA_CH13_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH13_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH13_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH13_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH13_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH13_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH13_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH13_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH13_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH13_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH13_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH13_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH13_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH13_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH13_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH13_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH13_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH13_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH13_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH13_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH13_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH13_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH13_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH13_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH13_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH13_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH13_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH13_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH13_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH13_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH13_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH13_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH13_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH13_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH13_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH13_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH13_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH13_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH13_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH13_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH13_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH13_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH13_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH13_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH13_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH13_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL1_CTRL +// Description : Alias for channel 13 CTRL register +#define DMA_CH13_AL1_CTRL_OFFSET _u(0x00000350) +#define DMA_CH13_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH13_AL1_CTRL_RESET "-" +#define DMA_CH13_AL1_CTRL_MSB _u(31) +#define DMA_CH13_AL1_CTRL_LSB _u(0) +#define DMA_CH13_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL1_READ_ADDR +// Description : Alias for channel 13 READ_ADDR register +#define DMA_CH13_AL1_READ_ADDR_OFFSET _u(0x00000354) +#define DMA_CH13_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH13_AL1_READ_ADDR_RESET "-" +#define DMA_CH13_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH13_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH13_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL1_WRITE_ADDR +// Description : Alias for channel 13 WRITE_ADDR register +#define DMA_CH13_AL1_WRITE_ADDR_OFFSET _u(0x00000358) +#define DMA_CH13_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH13_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH13_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH13_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH13_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 13 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH13_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000035c) +#define DMA_CH13_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH13_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH13_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH13_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH13_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL2_CTRL +// Description : Alias for channel 13 CTRL register +#define DMA_CH13_AL2_CTRL_OFFSET _u(0x00000360) +#define DMA_CH13_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH13_AL2_CTRL_RESET "-" +#define DMA_CH13_AL2_CTRL_MSB _u(31) +#define DMA_CH13_AL2_CTRL_LSB _u(0) +#define DMA_CH13_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL2_TRANS_COUNT +// Description : Alias for channel 13 TRANS_COUNT register +#define DMA_CH13_AL2_TRANS_COUNT_OFFSET _u(0x00000364) +#define DMA_CH13_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH13_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH13_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH13_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH13_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL2_READ_ADDR +// Description : Alias for channel 13 READ_ADDR register +#define DMA_CH13_AL2_READ_ADDR_OFFSET _u(0x00000368) +#define DMA_CH13_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH13_AL2_READ_ADDR_RESET "-" +#define DMA_CH13_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH13_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH13_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 13 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH13_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000036c) +#define DMA_CH13_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH13_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH13_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH13_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH13_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL3_CTRL +// Description : Alias for channel 13 CTRL register +#define DMA_CH13_AL3_CTRL_OFFSET _u(0x00000370) +#define DMA_CH13_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH13_AL3_CTRL_RESET "-" +#define DMA_CH13_AL3_CTRL_MSB _u(31) +#define DMA_CH13_AL3_CTRL_LSB _u(0) +#define DMA_CH13_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL3_WRITE_ADDR +// Description : Alias for channel 13 WRITE_ADDR register +#define DMA_CH13_AL3_WRITE_ADDR_OFFSET _u(0x00000374) +#define DMA_CH13_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH13_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH13_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH13_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH13_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL3_TRANS_COUNT +// Description : Alias for channel 13 TRANS_COUNT register +#define DMA_CH13_AL3_TRANS_COUNT_OFFSET _u(0x00000378) +#define DMA_CH13_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH13_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH13_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH13_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH13_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH13_AL3_READ_ADDR_TRIG +// Description : Alias for channel 13 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH13_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000037c) +#define DMA_CH13_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH13_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH13_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH13_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH13_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_READ_ADDR +// Description : DMA Channel 14 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH14_READ_ADDR_OFFSET _u(0x00000380) +#define DMA_CH14_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH14_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH14_READ_ADDR_MSB _u(31) +#define DMA_CH14_READ_ADDR_LSB _u(0) +#define DMA_CH14_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_WRITE_ADDR +// Description : DMA Channel 14 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH14_WRITE_ADDR_OFFSET _u(0x00000384) +#define DMA_CH14_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH14_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH14_WRITE_ADDR_MSB _u(31) +#define DMA_CH14_WRITE_ADDR_LSB _u(0) +#define DMA_CH14_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_TRANS_COUNT +// Description : DMA Channel 14 Transfer Count +#define DMA_CH14_TRANS_COUNT_OFFSET _u(0x00000388) +#define DMA_CH14_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH14_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH14_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH14_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH14_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH14_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH14_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH14_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH14_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH14_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH14_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH14_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH14_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH14_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH14_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_CTRL_TRIG +// Description : DMA Channel 14 Control and Status +#define DMA_CH14_CTRL_TRIG_OFFSET _u(0x0000038c) +#define DMA_CH14_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH14_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH14_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH14_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH14_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH14_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH14_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH14_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH14_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH14_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH14_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH14_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH14_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH14_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH14_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH14_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH14_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH14_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH14_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH14_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH14_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH14_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH14_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH14_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH14_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH14_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH14_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH14_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH14_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH14_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH14_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH14_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH14_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH14_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH14_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH14_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH14_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH14_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH14_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH14_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH14_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH14_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH14_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH14_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH14_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH14_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL1_CTRL +// Description : Alias for channel 14 CTRL register +#define DMA_CH14_AL1_CTRL_OFFSET _u(0x00000390) +#define DMA_CH14_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH14_AL1_CTRL_RESET "-" +#define DMA_CH14_AL1_CTRL_MSB _u(31) +#define DMA_CH14_AL1_CTRL_LSB _u(0) +#define DMA_CH14_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL1_READ_ADDR +// Description : Alias for channel 14 READ_ADDR register +#define DMA_CH14_AL1_READ_ADDR_OFFSET _u(0x00000394) +#define DMA_CH14_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH14_AL1_READ_ADDR_RESET "-" +#define DMA_CH14_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH14_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH14_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL1_WRITE_ADDR +// Description : Alias for channel 14 WRITE_ADDR register +#define DMA_CH14_AL1_WRITE_ADDR_OFFSET _u(0x00000398) +#define DMA_CH14_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH14_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH14_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH14_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH14_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 14 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH14_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000039c) +#define DMA_CH14_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH14_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH14_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH14_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH14_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL2_CTRL +// Description : Alias for channel 14 CTRL register +#define DMA_CH14_AL2_CTRL_OFFSET _u(0x000003a0) +#define DMA_CH14_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH14_AL2_CTRL_RESET "-" +#define DMA_CH14_AL2_CTRL_MSB _u(31) +#define DMA_CH14_AL2_CTRL_LSB _u(0) +#define DMA_CH14_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL2_TRANS_COUNT +// Description : Alias for channel 14 TRANS_COUNT register +#define DMA_CH14_AL2_TRANS_COUNT_OFFSET _u(0x000003a4) +#define DMA_CH14_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH14_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH14_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH14_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH14_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL2_READ_ADDR +// Description : Alias for channel 14 READ_ADDR register +#define DMA_CH14_AL2_READ_ADDR_OFFSET _u(0x000003a8) +#define DMA_CH14_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH14_AL2_READ_ADDR_RESET "-" +#define DMA_CH14_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH14_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH14_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 14 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH14_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000003ac) +#define DMA_CH14_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH14_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH14_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH14_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH14_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL3_CTRL +// Description : Alias for channel 14 CTRL register +#define DMA_CH14_AL3_CTRL_OFFSET _u(0x000003b0) +#define DMA_CH14_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH14_AL3_CTRL_RESET "-" +#define DMA_CH14_AL3_CTRL_MSB _u(31) +#define DMA_CH14_AL3_CTRL_LSB _u(0) +#define DMA_CH14_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL3_WRITE_ADDR +// Description : Alias for channel 14 WRITE_ADDR register +#define DMA_CH14_AL3_WRITE_ADDR_OFFSET _u(0x000003b4) +#define DMA_CH14_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH14_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH14_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH14_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH14_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL3_TRANS_COUNT +// Description : Alias for channel 14 TRANS_COUNT register +#define DMA_CH14_AL3_TRANS_COUNT_OFFSET _u(0x000003b8) +#define DMA_CH14_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH14_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH14_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH14_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH14_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH14_AL3_READ_ADDR_TRIG +// Description : Alias for channel 14 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH14_AL3_READ_ADDR_TRIG_OFFSET _u(0x000003bc) +#define DMA_CH14_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH14_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH14_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH14_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH14_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_READ_ADDR +// Description : DMA Channel 15 Read Address pointer +// This register updates automatically each time a read completes. +// The current value is the next address to be read by this +// channel. +#define DMA_CH15_READ_ADDR_OFFSET _u(0x000003c0) +#define DMA_CH15_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH15_READ_ADDR_RESET _u(0x00000000) +#define DMA_CH15_READ_ADDR_MSB _u(31) +#define DMA_CH15_READ_ADDR_LSB _u(0) +#define DMA_CH15_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_WRITE_ADDR +// Description : DMA Channel 15 Write Address pointer +// This register updates automatically each time a write +// completes. The current value is the next address to be written +// by this channel. +#define DMA_CH15_WRITE_ADDR_OFFSET _u(0x000003c4) +#define DMA_CH15_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH15_WRITE_ADDR_RESET _u(0x00000000) +#define DMA_CH15_WRITE_ADDR_MSB _u(31) +#define DMA_CH15_WRITE_ADDR_LSB _u(0) +#define DMA_CH15_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_TRANS_COUNT +// Description : DMA Channel 15 Transfer Count +#define DMA_CH15_TRANS_COUNT_OFFSET _u(0x000003c8) +#define DMA_CH15_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH15_TRANS_COUNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_TRANS_COUNT_MODE +// Description : When MODE is 0x0, the transfer count decrements with each +// transfer until 0, and then the channel triggers the next +// channel indicated by CTRL_CHAIN_TO. +// +// When MODE is 0x1, the transfer count decrements with each +// transfer until 0, and then the channel re-triggers itself, in +// addition to the trigger indicated by CTRL_CHAIN_TO. This is +// useful for e.g. an endless ring-buffer DMA with periodic +// interrupts. +// +// When MODE is 0xf, the transfer count does not decrement. The +// DMA channel performs an endless sequence of transfers, never +// triggering other channels or raising interrupts, until an ABORT +// is raised. +// +// All other values are reserved. +// 0x0 -> NORMAL +// 0x1 -> TRIGGER_SELF +// 0xf -> ENDLESS +#define DMA_CH15_TRANS_COUNT_MODE_RESET _u(0x0) +#define DMA_CH15_TRANS_COUNT_MODE_BITS _u(0xf0000000) +#define DMA_CH15_TRANS_COUNT_MODE_MSB _u(31) +#define DMA_CH15_TRANS_COUNT_MODE_LSB _u(28) +#define DMA_CH15_TRANS_COUNT_MODE_ACCESS "RW" +#define DMA_CH15_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0) +#define DMA_CH15_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1) +#define DMA_CH15_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_TRANS_COUNT_COUNT +// Description : 28-bit transfer count (256 million transfers maximum). +// +// Program the number of bus transfers a channel will perform +// before halting. Note that, if transfers are larger than one +// byte in size, this is not equal to the number of bytes +// transferred (see CTRL_DATA_SIZE). +// +// When the channel is active, reading this register shows the +// number of transfers remaining, updating automatically each time +// a write transfer completes. +// +// Writing this register sets the RELOAD value for the transfer +// counter. Each time this channel is triggered, the RELOAD value +// is copied into the live transfer counter. The channel can be +// started multiple times, and will perform the same number of +// transfers each time, as programmed by most recent write. +// +// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT +// is used as a trigger, the written value is used immediately as +// the length of the new transfer sequence, as well as being +// written to RELOAD. +#define DMA_CH15_TRANS_COUNT_COUNT_RESET _u(0x0000000) +#define DMA_CH15_TRANS_COUNT_COUNT_BITS _u(0x0fffffff) +#define DMA_CH15_TRANS_COUNT_COUNT_MSB _u(27) +#define DMA_CH15_TRANS_COUNT_COUNT_LSB _u(0) +#define DMA_CH15_TRANS_COUNT_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_CTRL_TRIG +// Description : DMA Channel 15 Control and Status +#define DMA_CH15_CTRL_TRIG_OFFSET _u(0x000003cc) +#define DMA_CH15_CTRL_TRIG_BITS _u(0xe7ffffff) +#define DMA_CH15_CTRL_TRIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_AHB_ERROR +// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel +// halts when it encounters any bus error, and always raises its +// channel IRQ flag. +#define DMA_CH15_CTRL_TRIG_AHB_ERROR_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000) +#define DMA_CH15_CTRL_TRIG_AHB_ERROR_MSB _u(31) +#define DMA_CH15_CTRL_TRIG_AHB_ERROR_LSB _u(31) +#define DMA_CH15_CTRL_TRIG_AHB_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_READ_ERROR +// Description : If 1, the channel received a read bus error. Write one to +// clear. +// READ_ADDR shows the approximate address where the bus error was +// encountered (will not be earlier, or more than 3 transfers +// later) +#define DMA_CH15_CTRL_TRIG_READ_ERROR_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000) +#define DMA_CH15_CTRL_TRIG_READ_ERROR_MSB _u(30) +#define DMA_CH15_CTRL_TRIG_READ_ERROR_LSB _u(30) +#define DMA_CH15_CTRL_TRIG_READ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_WRITE_ERROR +// Description : If 1, the channel received a write bus error. Write one to +// clear. +// WRITE_ADDR shows the approximate address where the bus error +// was encountered (will not be earlier, or more than 5 transfers +// later) +#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000) +#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_MSB _u(29) +#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_LSB _u(29) +#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_BUSY +// Description : This flag goes high when the channel starts a new transfer +// sequence, and low when the last transfer of that sequence +// completes. Clearing EN while BUSY is high pauses the channel, +// and BUSY will stay high while paused. +// +// To terminate a sequence early (and clear the BUSY flag), see +// CHAN_ABORT. +#define DMA_CH15_CTRL_TRIG_BUSY_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_BUSY_BITS _u(0x04000000) +#define DMA_CH15_CTRL_TRIG_BUSY_MSB _u(26) +#define DMA_CH15_CTRL_TRIG_BUSY_LSB _u(26) +#define DMA_CH15_CTRL_TRIG_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_SNIFF_EN +// Description : If 1, this channel's data transfers are visible to the sniff +// hardware, and each transfer will advance the state of the +// checksum. This only applies if the sniff hardware is enabled, +// and has this channel selected. +// +// This allows checksum to be enabled or disabled on a per- +// control- block basis. +#define DMA_CH15_CTRL_TRIG_SNIFF_EN_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000) +#define DMA_CH15_CTRL_TRIG_SNIFF_EN_MSB _u(25) +#define DMA_CH15_CTRL_TRIG_SNIFF_EN_LSB _u(25) +#define DMA_CH15_CTRL_TRIG_SNIFF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_BSWAP +// Description : Apply byte-swap transformation to DMA data. +// For byte data, this has no effect. For halfword data, the two +// bytes of each halfword are swapped. For word data, the four +// bytes of each word are swapped to reverse order. +#define DMA_CH15_CTRL_TRIG_BSWAP_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_BSWAP_BITS _u(0x01000000) +#define DMA_CH15_CTRL_TRIG_BSWAP_MSB _u(24) +#define DMA_CH15_CTRL_TRIG_BSWAP_LSB _u(24) +#define DMA_CH15_CTRL_TRIG_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_IRQ_QUIET +// Description : In QUIET mode, the channel does not generate IRQs at the end of +// every transfer block. Instead, an IRQ is raised when NULL is +// written to a trigger register, indicating the end of a control +// block chain. +// +// This reduces the number of interrupts to be serviced by the CPU +// when transferring a DMA chain of many small control blocks. +#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000) +#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_MSB _u(23) +#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_LSB _u(23) +#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_TREQ_SEL +// Description : Select a Transfer Request signal. +// The channel uses the transfer request signal to pace its data +// transfer rate. Sources for TREQ signals are internal (TIMERS) +// or external (DREQ, a Data Request from the system). +// 0x0 to 0x3a -> select DREQ n as TREQ +// 0x3b -> Select Timer 0 as TREQ +// 0x3c -> Select Timer 1 as TREQ +// 0x3d -> Select Timer 2 as TREQ (Optional) +// 0x3e -> Select Timer 3 as TREQ (Optional) +// 0x3f -> Permanent request, for unpaced transfers. +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_RESET _u(0x00) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_MSB _u(22) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_LSB _u(17) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_ACCESS "RW" +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e) +#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f) +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_CHAIN_TO +// Description : When this channel completes, it will trigger the channel +// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this +// channel)_. +// +// Note this field resets to 0, so channels 1 and above will chain +// to channel 0 by default. Set this field to avoid this +// behaviour. +#define DMA_CH15_CTRL_TRIG_CHAIN_TO_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000) +#define DMA_CH15_CTRL_TRIG_CHAIN_TO_MSB _u(16) +#define DMA_CH15_CTRL_TRIG_CHAIN_TO_LSB _u(13) +#define DMA_CH15_CTRL_TRIG_CHAIN_TO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_RING_SEL +// Description : Select whether RING_SIZE applies to read or write addresses. +// If 0, read addresses are wrapped on a (1 << RING_SIZE) +// boundary. If 1, write addresses are wrapped. +#define DMA_CH15_CTRL_TRIG_RING_SEL_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_RING_SEL_BITS _u(0x00001000) +#define DMA_CH15_CTRL_TRIG_RING_SEL_MSB _u(12) +#define DMA_CH15_CTRL_TRIG_RING_SEL_LSB _u(12) +#define DMA_CH15_CTRL_TRIG_RING_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_RING_SIZE +// Description : Size of address wrap region. If 0, don't wrap. For values n > +// 0, only the lower n bits of the address will change. This wraps +// the address on a (1 << n) byte boundary, facilitating access to +// naturally-aligned ring buffers. +// +// Ring sizes between 2 and 32768 bytes are possible. This can +// apply to either read or write addresses, based on value of +// RING_SEL. +// 0x0 -> RING_NONE +#define DMA_CH15_CTRL_TRIG_RING_SIZE_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00) +#define DMA_CH15_CTRL_TRIG_RING_SIZE_MSB _u(11) +#define DMA_CH15_CTRL_TRIG_RING_SIZE_LSB _u(8) +#define DMA_CH15_CTRL_TRIG_RING_SIZE_ACCESS "RW" +#define DMA_CH15_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0) +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_INCR_WRITE_REV +// Description : If 1, and INCR_WRITE is 1, the write address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_WRITE is 0, this otherwise-unused combination +// causes the write address to be incremented by twice the +// transfer size, i.e. skipping over alternate addresses. +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_INCR_WRITE +// Description : If 1, the write address increments with each transfer. If 0, +// each write is directed to the same, initial address. +// +// Generally this should be disabled for memory-to-peripheral +// transfers. +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_MSB _u(6) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_LSB _u(6) +#define DMA_CH15_CTRL_TRIG_INCR_WRITE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_INCR_READ_REV +// Description : If 1, and INCR_READ is 1, the read address is decremented +// rather than incremented with each transfer. +// +// If 1, and INCR_READ is 0, this otherwise-unused combination +// causes the read address to be incremented by twice the transfer +// size, i.e. skipping over alternate addresses. +#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020) +#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_MSB _u(5) +#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_LSB _u(5) +#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_INCR_READ +// Description : If 1, the read address increments with each transfer. If 0, +// each read is directed to the same, initial address. +// +// Generally this should be disabled for peripheral-to-memory +// transfers. +#define DMA_CH15_CTRL_TRIG_INCR_READ_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_INCR_READ_BITS _u(0x00000010) +#define DMA_CH15_CTRL_TRIG_INCR_READ_MSB _u(4) +#define DMA_CH15_CTRL_TRIG_INCR_READ_LSB _u(4) +#define DMA_CH15_CTRL_TRIG_INCR_READ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_DATA_SIZE +// Description : Set the size of each bus transfer (byte/halfword/word). +// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) +// with each transfer. +// 0x0 -> SIZE_BYTE +// 0x1 -> SIZE_HALFWORD +// 0x2 -> SIZE_WORD +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c) +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_MSB _u(3) +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_LSB _u(2) +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_ACCESS "RW" +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0) +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1) +#define DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2) +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_HIGH_PRIORITY +// Description : HIGH_PRIORITY gives a channel preferential treatment in issue +// scheduling: in each scheduling round, all high priority +// channels are considered first, and then only a single low +// priority channel, before returning to the high priority +// channels. +// +// This only affects the order in which the DMA schedules +// channels. The DMA's bus priority is not changed. If the DMA is +// not saturated then a low priority channel will see no loss of +// throughput. +#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002) +#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1) +#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1) +#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_CH15_CTRL_TRIG_EN +// Description : DMA Channel Enable. +// When 1, the channel will respond to triggering events, which +// will cause it to become BUSY and start transferring data. When +// 0, the channel will ignore triggers, stop issuing transfers, +// and pause the current transfer sequence (i.e. BUSY will remain +// high if already high) +#define DMA_CH15_CTRL_TRIG_EN_RESET _u(0x0) +#define DMA_CH15_CTRL_TRIG_EN_BITS _u(0x00000001) +#define DMA_CH15_CTRL_TRIG_EN_MSB _u(0) +#define DMA_CH15_CTRL_TRIG_EN_LSB _u(0) +#define DMA_CH15_CTRL_TRIG_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL1_CTRL +// Description : Alias for channel 15 CTRL register +#define DMA_CH15_AL1_CTRL_OFFSET _u(0x000003d0) +#define DMA_CH15_AL1_CTRL_BITS _u(0xffffffff) +#define DMA_CH15_AL1_CTRL_RESET "-" +#define DMA_CH15_AL1_CTRL_MSB _u(31) +#define DMA_CH15_AL1_CTRL_LSB _u(0) +#define DMA_CH15_AL1_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL1_READ_ADDR +// Description : Alias for channel 15 READ_ADDR register +#define DMA_CH15_AL1_READ_ADDR_OFFSET _u(0x000003d4) +#define DMA_CH15_AL1_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH15_AL1_READ_ADDR_RESET "-" +#define DMA_CH15_AL1_READ_ADDR_MSB _u(31) +#define DMA_CH15_AL1_READ_ADDR_LSB _u(0) +#define DMA_CH15_AL1_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL1_WRITE_ADDR +// Description : Alias for channel 15 WRITE_ADDR register +#define DMA_CH15_AL1_WRITE_ADDR_OFFSET _u(0x000003d8) +#define DMA_CH15_AL1_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH15_AL1_WRITE_ADDR_RESET "-" +#define DMA_CH15_AL1_WRITE_ADDR_MSB _u(31) +#define DMA_CH15_AL1_WRITE_ADDR_LSB _u(0) +#define DMA_CH15_AL1_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL1_TRANS_COUNT_TRIG +// Description : Alias for channel 15 TRANS_COUNT register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH15_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000003dc) +#define DMA_CH15_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff) +#define DMA_CH15_AL1_TRANS_COUNT_TRIG_RESET "-" +#define DMA_CH15_AL1_TRANS_COUNT_TRIG_MSB _u(31) +#define DMA_CH15_AL1_TRANS_COUNT_TRIG_LSB _u(0) +#define DMA_CH15_AL1_TRANS_COUNT_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL2_CTRL +// Description : Alias for channel 15 CTRL register +#define DMA_CH15_AL2_CTRL_OFFSET _u(0x000003e0) +#define DMA_CH15_AL2_CTRL_BITS _u(0xffffffff) +#define DMA_CH15_AL2_CTRL_RESET "-" +#define DMA_CH15_AL2_CTRL_MSB _u(31) +#define DMA_CH15_AL2_CTRL_LSB _u(0) +#define DMA_CH15_AL2_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL2_TRANS_COUNT +// Description : Alias for channel 15 TRANS_COUNT register +#define DMA_CH15_AL2_TRANS_COUNT_OFFSET _u(0x000003e4) +#define DMA_CH15_AL2_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH15_AL2_TRANS_COUNT_RESET "-" +#define DMA_CH15_AL2_TRANS_COUNT_MSB _u(31) +#define DMA_CH15_AL2_TRANS_COUNT_LSB _u(0) +#define DMA_CH15_AL2_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL2_READ_ADDR +// Description : Alias for channel 15 READ_ADDR register +#define DMA_CH15_AL2_READ_ADDR_OFFSET _u(0x000003e8) +#define DMA_CH15_AL2_READ_ADDR_BITS _u(0xffffffff) +#define DMA_CH15_AL2_READ_ADDR_RESET "-" +#define DMA_CH15_AL2_READ_ADDR_MSB _u(31) +#define DMA_CH15_AL2_READ_ADDR_LSB _u(0) +#define DMA_CH15_AL2_READ_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL2_WRITE_ADDR_TRIG +// Description : Alias for channel 15 WRITE_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH15_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000003ec) +#define DMA_CH15_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH15_AL2_WRITE_ADDR_TRIG_RESET "-" +#define DMA_CH15_AL2_WRITE_ADDR_TRIG_MSB _u(31) +#define DMA_CH15_AL2_WRITE_ADDR_TRIG_LSB _u(0) +#define DMA_CH15_AL2_WRITE_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL3_CTRL +// Description : Alias for channel 15 CTRL register +#define DMA_CH15_AL3_CTRL_OFFSET _u(0x000003f0) +#define DMA_CH15_AL3_CTRL_BITS _u(0xffffffff) +#define DMA_CH15_AL3_CTRL_RESET "-" +#define DMA_CH15_AL3_CTRL_MSB _u(31) +#define DMA_CH15_AL3_CTRL_LSB _u(0) +#define DMA_CH15_AL3_CTRL_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL3_WRITE_ADDR +// Description : Alias for channel 15 WRITE_ADDR register +#define DMA_CH15_AL3_WRITE_ADDR_OFFSET _u(0x000003f4) +#define DMA_CH15_AL3_WRITE_ADDR_BITS _u(0xffffffff) +#define DMA_CH15_AL3_WRITE_ADDR_RESET "-" +#define DMA_CH15_AL3_WRITE_ADDR_MSB _u(31) +#define DMA_CH15_AL3_WRITE_ADDR_LSB _u(0) +#define DMA_CH15_AL3_WRITE_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL3_TRANS_COUNT +// Description : Alias for channel 15 TRANS_COUNT register +#define DMA_CH15_AL3_TRANS_COUNT_OFFSET _u(0x000003f8) +#define DMA_CH15_AL3_TRANS_COUNT_BITS _u(0xffffffff) +#define DMA_CH15_AL3_TRANS_COUNT_RESET "-" +#define DMA_CH15_AL3_TRANS_COUNT_MSB _u(31) +#define DMA_CH15_AL3_TRANS_COUNT_LSB _u(0) +#define DMA_CH15_AL3_TRANS_COUNT_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH15_AL3_READ_ADDR_TRIG +// Description : Alias for channel 15 READ_ADDR register +// This is a trigger register (0xc). Writing a nonzero value will +// reload the channel counter and start the channel. +#define DMA_CH15_AL3_READ_ADDR_TRIG_OFFSET _u(0x000003fc) +#define DMA_CH15_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff) +#define DMA_CH15_AL3_READ_ADDR_TRIG_RESET "-" +#define DMA_CH15_AL3_READ_ADDR_TRIG_MSB _u(31) +#define DMA_CH15_AL3_READ_ADDR_TRIG_LSB _u(0) +#define DMA_CH15_AL3_READ_ADDR_TRIG_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTR +// Description : Interrupt Status (raw) +// Raw interrupt status for DMA Channels 0..15. Bit n corresponds +// to channel n. Ignores any masking or forcing. Channel +// interrupts can be cleared by writing a bit mask to INTR or +// INTS0/1/2/3. +// +// Channel interrupts can be routed to either of four system-level +// IRQs based on INTE0, INTE1, INTE2 and INTE3. +// +// The multiple system-level interrupts might be used to allow +// NVIC IRQ preemption for more time-critical channels, to spread +// IRQ load across different cores, or to target IRQs to different +// security domains. +// +// It is also valid to ignore the multiple IRQs, and just use +// INTE0/INTS0/IRQ 0. +// +// If this register is accessed at a security/privilege level less +// than that of a given channel (as defined by that channel's +// SECCFG_CHx register), then that channel's interrupt status will +// read as 0, ignore writes. +#define DMA_INTR_OFFSET _u(0x00000400) +#define DMA_INTR_BITS _u(0x0000ffff) +#define DMA_INTR_RESET _u(0x00000000) +#define DMA_INTR_MSB _u(15) +#define DMA_INTR_LSB _u(0) +#define DMA_INTR_ACCESS "WC" +// ============================================================================= +// Register : DMA_INTE0 +// Description : Interrupt Enables for IRQ 0 +// Set bit n to pass interrupts from channel n to DMA IRQ 0. +// +// Note this bit has no effect if the channel security/privilege +// level, defined by SECCFG_CHx, is greater than the IRQ +// security/privilege defined by SECCFG_IRQ0. +#define DMA_INTE0_OFFSET _u(0x00000404) +#define DMA_INTE0_BITS _u(0x0000ffff) +#define DMA_INTE0_RESET _u(0x00000000) +#define DMA_INTE0_MSB _u(15) +#define DMA_INTE0_LSB _u(0) +#define DMA_INTE0_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTF0 +// Description : Force Interrupts +// Write 1s to force the corresponding bits in INTS0. The +// interrupt remains asserted until INTF0 is cleared. +#define DMA_INTF0_OFFSET _u(0x00000408) +#define DMA_INTF0_BITS _u(0x0000ffff) +#define DMA_INTF0_RESET _u(0x00000000) +#define DMA_INTF0_MSB _u(15) +#define DMA_INTF0_LSB _u(0) +#define DMA_INTF0_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTS0 +// Description : Interrupt Status for IRQ 0 +// Indicates active channel interrupt requests which are currently +// causing IRQ 0 to be asserted. +// Channel interrupts can be cleared by writing a bit mask here. +// +// Channels with a security/privilege (SECCFG_CHx) greater +// SECCFG_IRQ0) read as 0 in this register, and ignore writes. +#define DMA_INTS0_OFFSET _u(0x0000040c) +#define DMA_INTS0_BITS _u(0x0000ffff) +#define DMA_INTS0_RESET _u(0x00000000) +#define DMA_INTS0_MSB _u(15) +#define DMA_INTS0_LSB _u(0) +#define DMA_INTS0_ACCESS "WC" +// ============================================================================= +// Register : DMA_INTE1 +// Description : Interrupt Enables for IRQ 1 +// Set bit n to pass interrupts from channel n to DMA IRQ 1. +// +// Note this bit has no effect if the channel security/privilege +// level, defined by SECCFG_CHx, is greater than the IRQ +// security/privilege defined by SECCFG_IRQ1. +#define DMA_INTE1_OFFSET _u(0x00000414) +#define DMA_INTE1_BITS _u(0x0000ffff) +#define DMA_INTE1_RESET _u(0x00000000) +#define DMA_INTE1_MSB _u(15) +#define DMA_INTE1_LSB _u(0) +#define DMA_INTE1_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTF1 +// Description : Force Interrupts +// Write 1s to force the corresponding bits in INTS1. The +// interrupt remains asserted until INTF1 is cleared. +#define DMA_INTF1_OFFSET _u(0x00000418) +#define DMA_INTF1_BITS _u(0x0000ffff) +#define DMA_INTF1_RESET _u(0x00000000) +#define DMA_INTF1_MSB _u(15) +#define DMA_INTF1_LSB _u(0) +#define DMA_INTF1_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTS1 +// Description : Interrupt Status for IRQ 1 +// Indicates active channel interrupt requests which are currently +// causing IRQ 1 to be asserted. +// Channel interrupts can be cleared by writing a bit mask here. +// +// Channels with a security/privilege (SECCFG_CHx) greater +// SECCFG_IRQ1) read as 0 in this register, and ignore writes. +#define DMA_INTS1_OFFSET _u(0x0000041c) +#define DMA_INTS1_BITS _u(0x0000ffff) +#define DMA_INTS1_RESET _u(0x00000000) +#define DMA_INTS1_MSB _u(15) +#define DMA_INTS1_LSB _u(0) +#define DMA_INTS1_ACCESS "WC" +// ============================================================================= +// Register : DMA_INTE2 +// Description : Interrupt Enables for IRQ 2 +// Set bit n to pass interrupts from channel n to DMA IRQ 2. +// +// Note this bit has no effect if the channel security/privilege +// level, defined by SECCFG_CHx, is greater than the IRQ +// security/privilege defined by SECCFG_IRQ2. +#define DMA_INTE2_OFFSET _u(0x00000424) +#define DMA_INTE2_BITS _u(0x0000ffff) +#define DMA_INTE2_RESET _u(0x00000000) +#define DMA_INTE2_MSB _u(15) +#define DMA_INTE2_LSB _u(0) +#define DMA_INTE2_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTF2 +// Description : Force Interrupts +// Write 1s to force the corresponding bits in INTS2. The +// interrupt remains asserted until INTF2 is cleared. +#define DMA_INTF2_OFFSET _u(0x00000428) +#define DMA_INTF2_BITS _u(0x0000ffff) +#define DMA_INTF2_RESET _u(0x00000000) +#define DMA_INTF2_MSB _u(15) +#define DMA_INTF2_LSB _u(0) +#define DMA_INTF2_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTS2 +// Description : Interrupt Status for IRQ 2 +// Indicates active channel interrupt requests which are currently +// causing IRQ 2 to be asserted. +// Channel interrupts can be cleared by writing a bit mask here. +// +// Channels with a security/privilege (SECCFG_CHx) greater +// SECCFG_IRQ2) read as 0 in this register, and ignore writes. +#define DMA_INTS2_OFFSET _u(0x0000042c) +#define DMA_INTS2_BITS _u(0x0000ffff) +#define DMA_INTS2_RESET _u(0x00000000) +#define DMA_INTS2_MSB _u(15) +#define DMA_INTS2_LSB _u(0) +#define DMA_INTS2_ACCESS "WC" +// ============================================================================= +// Register : DMA_INTE3 +// Description : Interrupt Enables for IRQ 3 +// Set bit n to pass interrupts from channel n to DMA IRQ 3. +// +// Note this bit has no effect if the channel security/privilege +// level, defined by SECCFG_CHx, is greater than the IRQ +// security/privilege defined by SECCFG_IRQ3. +#define DMA_INTE3_OFFSET _u(0x00000434) +#define DMA_INTE3_BITS _u(0x0000ffff) +#define DMA_INTE3_RESET _u(0x00000000) +#define DMA_INTE3_MSB _u(15) +#define DMA_INTE3_LSB _u(0) +#define DMA_INTE3_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTF3 +// Description : Force Interrupts +// Write 1s to force the corresponding bits in INTS3. The +// interrupt remains asserted until INTF3 is cleared. +#define DMA_INTF3_OFFSET _u(0x00000438) +#define DMA_INTF3_BITS _u(0x0000ffff) +#define DMA_INTF3_RESET _u(0x00000000) +#define DMA_INTF3_MSB _u(15) +#define DMA_INTF3_LSB _u(0) +#define DMA_INTF3_ACCESS "RW" +// ============================================================================= +// Register : DMA_INTS3 +// Description : Interrupt Status for IRQ 3 +// Indicates active channel interrupt requests which are currently +// causing IRQ 3 to be asserted. +// Channel interrupts can be cleared by writing a bit mask here. +// +// Channels with a security/privilege (SECCFG_CHx) greater +// SECCFG_IRQ3) read as 0 in this register, and ignore writes. +#define DMA_INTS3_OFFSET _u(0x0000043c) +#define DMA_INTS3_BITS _u(0x0000ffff) +#define DMA_INTS3_RESET _u(0x00000000) +#define DMA_INTS3_MSB _u(15) +#define DMA_INTS3_LSB _u(0) +#define DMA_INTS3_ACCESS "WC" +// ============================================================================= +// Register : DMA_TIMER0 +// Description : Pacing (X/Y) fractional timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER0_OFFSET _u(0x00000440) +#define DMA_TIMER0_BITS _u(0xffffffff) +#define DMA_TIMER0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER0_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER0_X_RESET _u(0x0000) +#define DMA_TIMER0_X_BITS _u(0xffff0000) +#define DMA_TIMER0_X_MSB _u(31) +#define DMA_TIMER0_X_LSB _u(16) +#define DMA_TIMER0_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER0_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER0_Y_RESET _u(0x0000) +#define DMA_TIMER0_Y_BITS _u(0x0000ffff) +#define DMA_TIMER0_Y_MSB _u(15) +#define DMA_TIMER0_Y_LSB _u(0) +#define DMA_TIMER0_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_TIMER1 +// Description : Pacing (X/Y) fractional timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER1_OFFSET _u(0x00000444) +#define DMA_TIMER1_BITS _u(0xffffffff) +#define DMA_TIMER1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER1_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER1_X_RESET _u(0x0000) +#define DMA_TIMER1_X_BITS _u(0xffff0000) +#define DMA_TIMER1_X_MSB _u(31) +#define DMA_TIMER1_X_LSB _u(16) +#define DMA_TIMER1_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER1_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER1_Y_RESET _u(0x0000) +#define DMA_TIMER1_Y_BITS _u(0x0000ffff) +#define DMA_TIMER1_Y_MSB _u(15) +#define DMA_TIMER1_Y_LSB _u(0) +#define DMA_TIMER1_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_TIMER2 +// Description : Pacing (X/Y) fractional timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER2_OFFSET _u(0x00000448) +#define DMA_TIMER2_BITS _u(0xffffffff) +#define DMA_TIMER2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER2_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER2_X_RESET _u(0x0000) +#define DMA_TIMER2_X_BITS _u(0xffff0000) +#define DMA_TIMER2_X_MSB _u(31) +#define DMA_TIMER2_X_LSB _u(16) +#define DMA_TIMER2_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER2_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER2_Y_RESET _u(0x0000) +#define DMA_TIMER2_Y_BITS _u(0x0000ffff) +#define DMA_TIMER2_Y_MSB _u(15) +#define DMA_TIMER2_Y_LSB _u(0) +#define DMA_TIMER2_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_TIMER3 +// Description : Pacing (X/Y) fractional timer +// The pacing timer produces TREQ assertions at a rate set by +// ((X/Y) * sys_clk). This equation is evaluated every sys_clk +// cycles and therefore can only generate TREQs at a rate of 1 per +// sys_clk (i.e. permanent TREQ) or less. +#define DMA_TIMER3_OFFSET _u(0x0000044c) +#define DMA_TIMER3_BITS _u(0xffffffff) +#define DMA_TIMER3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER3_X +// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y) +// fractional timer. +#define DMA_TIMER3_X_RESET _u(0x0000) +#define DMA_TIMER3_X_BITS _u(0xffff0000) +#define DMA_TIMER3_X_MSB _u(31) +#define DMA_TIMER3_X_LSB _u(16) +#define DMA_TIMER3_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_TIMER3_Y +// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y) +// fractional timer. +#define DMA_TIMER3_Y_RESET _u(0x0000) +#define DMA_TIMER3_Y_BITS _u(0x0000ffff) +#define DMA_TIMER3_Y_MSB _u(15) +#define DMA_TIMER3_Y_LSB _u(0) +#define DMA_TIMER3_Y_ACCESS "RW" +// ============================================================================= +// Register : DMA_MULTI_CHAN_TRIGGER +// Description : Trigger one or more channels simultaneously +// Each bit in this register corresponds to a DMA channel. Writing +// a 1 to the relevant bit is the same as writing to that +// channel's trigger register; the channel will start if it is +// currently enabled and not already busy. +#define DMA_MULTI_CHAN_TRIGGER_OFFSET _u(0x00000450) +#define DMA_MULTI_CHAN_TRIGGER_BITS _u(0x0000ffff) +#define DMA_MULTI_CHAN_TRIGGER_RESET _u(0x00000000) +#define DMA_MULTI_CHAN_TRIGGER_MSB _u(15) +#define DMA_MULTI_CHAN_TRIGGER_LSB _u(0) +#define DMA_MULTI_CHAN_TRIGGER_ACCESS "SC" +// ============================================================================= +// Register : DMA_SNIFF_CTRL +// Description : Sniffer Control +#define DMA_SNIFF_CTRL_OFFSET _u(0x00000454) +#define DMA_SNIFF_CTRL_BITS _u(0x00000fff) +#define DMA_SNIFF_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_OUT_INV +// Description : If set, the result appears inverted (bitwise complement) when +// read. This does not affect the way the checksum is calculated; +// the result is transformed on-the-fly between the result +// register and the bus. +#define DMA_SNIFF_CTRL_OUT_INV_RESET _u(0x0) +#define DMA_SNIFF_CTRL_OUT_INV_BITS _u(0x00000800) +#define DMA_SNIFF_CTRL_OUT_INV_MSB _u(11) +#define DMA_SNIFF_CTRL_OUT_INV_LSB _u(11) +#define DMA_SNIFF_CTRL_OUT_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_OUT_REV +// Description : If set, the result appears bit-reversed when read. This does +// not affect the way the checksum is calculated; the result is +// transformed on-the-fly between the result register and the bus. +#define DMA_SNIFF_CTRL_OUT_REV_RESET _u(0x0) +#define DMA_SNIFF_CTRL_OUT_REV_BITS _u(0x00000400) +#define DMA_SNIFF_CTRL_OUT_REV_MSB _u(10) +#define DMA_SNIFF_CTRL_OUT_REV_LSB _u(10) +#define DMA_SNIFF_CTRL_OUT_REV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_BSWAP +// Description : Locally perform a byte reverse on the sniffed data, before +// feeding into checksum. +// +// Note that the sniff hardware is downstream of the DMA channel +// byteswap performed in the read master: if channel CTRL_BSWAP +// and SNIFF_CTRL_BSWAP are both enabled, their effects cancel +// from the sniffer's point of view. +#define DMA_SNIFF_CTRL_BSWAP_RESET _u(0x0) +#define DMA_SNIFF_CTRL_BSWAP_BITS _u(0x00000200) +#define DMA_SNIFF_CTRL_BSWAP_MSB _u(9) +#define DMA_SNIFF_CTRL_BSWAP_LSB _u(9) +#define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_CALC +// 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial) +// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data +// 0x2 -> Calculate a CRC-16-CCITT +// 0x3 -> Calculate a CRC-16-CCITT with bit reversed data +// 0xe -> XOR reduction over all data. == 1 if the total 1 population count is odd. +// 0xf -> Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) +#define DMA_SNIFF_CTRL_CALC_RESET _u(0x0) +#define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0) +#define DMA_SNIFF_CTRL_CALC_MSB _u(8) +#define DMA_SNIFF_CTRL_CALC_LSB _u(5) +#define DMA_SNIFF_CTRL_CALC_ACCESS "RW" +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _u(0x0) +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R _u(0x1) +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _u(0x2) +#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R _u(0x3) +#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN _u(0xe) +#define DMA_SNIFF_CTRL_CALC_VALUE_SUM _u(0xf) +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_DMACH +// Description : DMA channel for Sniffer to observe +#define DMA_SNIFF_CTRL_DMACH_RESET _u(0x0) +#define DMA_SNIFF_CTRL_DMACH_BITS _u(0x0000001e) +#define DMA_SNIFF_CTRL_DMACH_MSB _u(4) +#define DMA_SNIFF_CTRL_DMACH_LSB _u(1) +#define DMA_SNIFF_CTRL_DMACH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SNIFF_CTRL_EN +// Description : Enable sniffer +#define DMA_SNIFF_CTRL_EN_RESET _u(0x0) +#define DMA_SNIFF_CTRL_EN_BITS _u(0x00000001) +#define DMA_SNIFF_CTRL_EN_MSB _u(0) +#define DMA_SNIFF_CTRL_EN_LSB _u(0) +#define DMA_SNIFF_CTRL_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_SNIFF_DATA +// Description : Data accumulator for sniff hardware +// Write an initial seed value here before starting a DMA transfer +// on the channel indicated by SNIFF_CTRL_DMACH. The hardware will +// update this register each time it observes a read from the +// indicated channel. Once the channel completes, the final result +// can be read from this register. +#define DMA_SNIFF_DATA_OFFSET _u(0x00000458) +#define DMA_SNIFF_DATA_BITS _u(0xffffffff) +#define DMA_SNIFF_DATA_RESET _u(0x00000000) +#define DMA_SNIFF_DATA_MSB _u(31) +#define DMA_SNIFF_DATA_LSB _u(0) +#define DMA_SNIFF_DATA_ACCESS "RW" +// ============================================================================= +// Register : DMA_FIFO_LEVELS +// Description : Debug RAF, WAF, TDF levels +#define DMA_FIFO_LEVELS_OFFSET _u(0x00000460) +#define DMA_FIFO_LEVELS_BITS _u(0x00ffffff) +#define DMA_FIFO_LEVELS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_FIFO_LEVELS_RAF_LVL +// Description : Current Read-Address-FIFO fill level +#define DMA_FIFO_LEVELS_RAF_LVL_RESET _u(0x00) +#define DMA_FIFO_LEVELS_RAF_LVL_BITS _u(0x00ff0000) +#define DMA_FIFO_LEVELS_RAF_LVL_MSB _u(23) +#define DMA_FIFO_LEVELS_RAF_LVL_LSB _u(16) +#define DMA_FIFO_LEVELS_RAF_LVL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_FIFO_LEVELS_WAF_LVL +// Description : Current Write-Address-FIFO fill level +#define DMA_FIFO_LEVELS_WAF_LVL_RESET _u(0x00) +#define DMA_FIFO_LEVELS_WAF_LVL_BITS _u(0x0000ff00) +#define DMA_FIFO_LEVELS_WAF_LVL_MSB _u(15) +#define DMA_FIFO_LEVELS_WAF_LVL_LSB _u(8) +#define DMA_FIFO_LEVELS_WAF_LVL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : DMA_FIFO_LEVELS_TDF_LVL +// Description : Current Transfer-Data-FIFO fill level +#define DMA_FIFO_LEVELS_TDF_LVL_RESET _u(0x00) +#define DMA_FIFO_LEVELS_TDF_LVL_BITS _u(0x000000ff) +#define DMA_FIFO_LEVELS_TDF_LVL_MSB _u(7) +#define DMA_FIFO_LEVELS_TDF_LVL_LSB _u(0) +#define DMA_FIFO_LEVELS_TDF_LVL_ACCESS "RO" +// ============================================================================= +// Register : DMA_CHAN_ABORT +// Description : Abort an in-progress transfer sequence on one or more channels +// Each bit corresponds to a channel. Writing a 1 aborts whatever +// transfer sequence is in progress on that channel. The bit will +// remain high until any in-flight transfers have been flushed +// through the address and data FIFOs. +// +// After writing, this register must be polled until it returns +// all-zero. Until this point, it is unsafe to restart the +// channel. +#define DMA_CHAN_ABORT_OFFSET _u(0x00000464) +#define DMA_CHAN_ABORT_BITS _u(0x0000ffff) +#define DMA_CHAN_ABORT_RESET _u(0x00000000) +#define DMA_CHAN_ABORT_MSB _u(15) +#define DMA_CHAN_ABORT_LSB _u(0) +#define DMA_CHAN_ABORT_ACCESS "SC" +// ============================================================================= +// Register : DMA_N_CHANNELS +// Description : The number of channels this DMA instance is equipped with. This +// DMA supports up to 16 hardware channels, but can be configured +// with as few as one, to minimise silicon area. +#define DMA_N_CHANNELS_OFFSET _u(0x00000468) +#define DMA_N_CHANNELS_BITS _u(0x0000001f) +#define DMA_N_CHANNELS_RESET "-" +#define DMA_N_CHANNELS_MSB _u(4) +#define DMA_N_CHANNELS_LSB _u(0) +#define DMA_N_CHANNELS_ACCESS "RO" +// ============================================================================= +// Register : DMA_SECCFG_CH0 +// Description : Security configuration for channel 0. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH0_OFFSET _u(0x00000480) +#define DMA_SECCFG_CH0_BITS _u(0x00000007) +#define DMA_SECCFG_CH0_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH0_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH0_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH0_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH0_LOCK_MSB _u(2) +#define DMA_SECCFG_CH0_LOCK_LSB _u(2) +#define DMA_SECCFG_CH0_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH0_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH0_S_RESET _u(0x1) +#define DMA_SECCFG_CH0_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH0_S_MSB _u(1) +#define DMA_SECCFG_CH0_S_LSB _u(1) +#define DMA_SECCFG_CH0_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH0_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH0_P_RESET _u(0x1) +#define DMA_SECCFG_CH0_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH0_P_MSB _u(0) +#define DMA_SECCFG_CH0_P_LSB _u(0) +#define DMA_SECCFG_CH0_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH1 +// Description : Security configuration for channel 1. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH1_OFFSET _u(0x00000484) +#define DMA_SECCFG_CH1_BITS _u(0x00000007) +#define DMA_SECCFG_CH1_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH1_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH1_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH1_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH1_LOCK_MSB _u(2) +#define DMA_SECCFG_CH1_LOCK_LSB _u(2) +#define DMA_SECCFG_CH1_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH1_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH1_S_RESET _u(0x1) +#define DMA_SECCFG_CH1_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH1_S_MSB _u(1) +#define DMA_SECCFG_CH1_S_LSB _u(1) +#define DMA_SECCFG_CH1_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH1_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH1_P_RESET _u(0x1) +#define DMA_SECCFG_CH1_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH1_P_MSB _u(0) +#define DMA_SECCFG_CH1_P_LSB _u(0) +#define DMA_SECCFG_CH1_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH2 +// Description : Security configuration for channel 2. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH2_OFFSET _u(0x00000488) +#define DMA_SECCFG_CH2_BITS _u(0x00000007) +#define DMA_SECCFG_CH2_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH2_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH2_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH2_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH2_LOCK_MSB _u(2) +#define DMA_SECCFG_CH2_LOCK_LSB _u(2) +#define DMA_SECCFG_CH2_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH2_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH2_S_RESET _u(0x1) +#define DMA_SECCFG_CH2_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH2_S_MSB _u(1) +#define DMA_SECCFG_CH2_S_LSB _u(1) +#define DMA_SECCFG_CH2_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH2_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH2_P_RESET _u(0x1) +#define DMA_SECCFG_CH2_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH2_P_MSB _u(0) +#define DMA_SECCFG_CH2_P_LSB _u(0) +#define DMA_SECCFG_CH2_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH3 +// Description : Security configuration for channel 3. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH3_OFFSET _u(0x0000048c) +#define DMA_SECCFG_CH3_BITS _u(0x00000007) +#define DMA_SECCFG_CH3_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH3_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH3_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH3_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH3_LOCK_MSB _u(2) +#define DMA_SECCFG_CH3_LOCK_LSB _u(2) +#define DMA_SECCFG_CH3_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH3_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH3_S_RESET _u(0x1) +#define DMA_SECCFG_CH3_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH3_S_MSB _u(1) +#define DMA_SECCFG_CH3_S_LSB _u(1) +#define DMA_SECCFG_CH3_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH3_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH3_P_RESET _u(0x1) +#define DMA_SECCFG_CH3_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH3_P_MSB _u(0) +#define DMA_SECCFG_CH3_P_LSB _u(0) +#define DMA_SECCFG_CH3_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH4 +// Description : Security configuration for channel 4. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH4_OFFSET _u(0x00000490) +#define DMA_SECCFG_CH4_BITS _u(0x00000007) +#define DMA_SECCFG_CH4_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH4_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH4_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH4_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH4_LOCK_MSB _u(2) +#define DMA_SECCFG_CH4_LOCK_LSB _u(2) +#define DMA_SECCFG_CH4_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH4_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH4_S_RESET _u(0x1) +#define DMA_SECCFG_CH4_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH4_S_MSB _u(1) +#define DMA_SECCFG_CH4_S_LSB _u(1) +#define DMA_SECCFG_CH4_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH4_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH4_P_RESET _u(0x1) +#define DMA_SECCFG_CH4_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH4_P_MSB _u(0) +#define DMA_SECCFG_CH4_P_LSB _u(0) +#define DMA_SECCFG_CH4_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH5 +// Description : Security configuration for channel 5. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH5_OFFSET _u(0x00000494) +#define DMA_SECCFG_CH5_BITS _u(0x00000007) +#define DMA_SECCFG_CH5_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH5_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH5_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH5_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH5_LOCK_MSB _u(2) +#define DMA_SECCFG_CH5_LOCK_LSB _u(2) +#define DMA_SECCFG_CH5_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH5_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH5_S_RESET _u(0x1) +#define DMA_SECCFG_CH5_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH5_S_MSB _u(1) +#define DMA_SECCFG_CH5_S_LSB _u(1) +#define DMA_SECCFG_CH5_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH5_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH5_P_RESET _u(0x1) +#define DMA_SECCFG_CH5_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH5_P_MSB _u(0) +#define DMA_SECCFG_CH5_P_LSB _u(0) +#define DMA_SECCFG_CH5_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH6 +// Description : Security configuration for channel 6. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH6_OFFSET _u(0x00000498) +#define DMA_SECCFG_CH6_BITS _u(0x00000007) +#define DMA_SECCFG_CH6_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH6_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH6_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH6_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH6_LOCK_MSB _u(2) +#define DMA_SECCFG_CH6_LOCK_LSB _u(2) +#define DMA_SECCFG_CH6_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH6_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH6_S_RESET _u(0x1) +#define DMA_SECCFG_CH6_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH6_S_MSB _u(1) +#define DMA_SECCFG_CH6_S_LSB _u(1) +#define DMA_SECCFG_CH6_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH6_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH6_P_RESET _u(0x1) +#define DMA_SECCFG_CH6_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH6_P_MSB _u(0) +#define DMA_SECCFG_CH6_P_LSB _u(0) +#define DMA_SECCFG_CH6_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH7 +// Description : Security configuration for channel 7. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH7_OFFSET _u(0x0000049c) +#define DMA_SECCFG_CH7_BITS _u(0x00000007) +#define DMA_SECCFG_CH7_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH7_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH7_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH7_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH7_LOCK_MSB _u(2) +#define DMA_SECCFG_CH7_LOCK_LSB _u(2) +#define DMA_SECCFG_CH7_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH7_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH7_S_RESET _u(0x1) +#define DMA_SECCFG_CH7_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH7_S_MSB _u(1) +#define DMA_SECCFG_CH7_S_LSB _u(1) +#define DMA_SECCFG_CH7_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH7_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH7_P_RESET _u(0x1) +#define DMA_SECCFG_CH7_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH7_P_MSB _u(0) +#define DMA_SECCFG_CH7_P_LSB _u(0) +#define DMA_SECCFG_CH7_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH8 +// Description : Security configuration for channel 8. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH8_OFFSET _u(0x000004a0) +#define DMA_SECCFG_CH8_BITS _u(0x00000007) +#define DMA_SECCFG_CH8_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH8_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH8_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH8_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH8_LOCK_MSB _u(2) +#define DMA_SECCFG_CH8_LOCK_LSB _u(2) +#define DMA_SECCFG_CH8_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH8_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH8_S_RESET _u(0x1) +#define DMA_SECCFG_CH8_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH8_S_MSB _u(1) +#define DMA_SECCFG_CH8_S_LSB _u(1) +#define DMA_SECCFG_CH8_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH8_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH8_P_RESET _u(0x1) +#define DMA_SECCFG_CH8_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH8_P_MSB _u(0) +#define DMA_SECCFG_CH8_P_LSB _u(0) +#define DMA_SECCFG_CH8_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH9 +// Description : Security configuration for channel 9. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH9_OFFSET _u(0x000004a4) +#define DMA_SECCFG_CH9_BITS _u(0x00000007) +#define DMA_SECCFG_CH9_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH9_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH9_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH9_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH9_LOCK_MSB _u(2) +#define DMA_SECCFG_CH9_LOCK_LSB _u(2) +#define DMA_SECCFG_CH9_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH9_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH9_S_RESET _u(0x1) +#define DMA_SECCFG_CH9_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH9_S_MSB _u(1) +#define DMA_SECCFG_CH9_S_LSB _u(1) +#define DMA_SECCFG_CH9_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH9_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH9_P_RESET _u(0x1) +#define DMA_SECCFG_CH9_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH9_P_MSB _u(0) +#define DMA_SECCFG_CH9_P_LSB _u(0) +#define DMA_SECCFG_CH9_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH10 +// Description : Security configuration for channel 10. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH10_OFFSET _u(0x000004a8) +#define DMA_SECCFG_CH10_BITS _u(0x00000007) +#define DMA_SECCFG_CH10_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH10_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH10_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH10_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH10_LOCK_MSB _u(2) +#define DMA_SECCFG_CH10_LOCK_LSB _u(2) +#define DMA_SECCFG_CH10_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH10_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH10_S_RESET _u(0x1) +#define DMA_SECCFG_CH10_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH10_S_MSB _u(1) +#define DMA_SECCFG_CH10_S_LSB _u(1) +#define DMA_SECCFG_CH10_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH10_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH10_P_RESET _u(0x1) +#define DMA_SECCFG_CH10_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH10_P_MSB _u(0) +#define DMA_SECCFG_CH10_P_LSB _u(0) +#define DMA_SECCFG_CH10_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH11 +// Description : Security configuration for channel 11. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH11_OFFSET _u(0x000004ac) +#define DMA_SECCFG_CH11_BITS _u(0x00000007) +#define DMA_SECCFG_CH11_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH11_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH11_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH11_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH11_LOCK_MSB _u(2) +#define DMA_SECCFG_CH11_LOCK_LSB _u(2) +#define DMA_SECCFG_CH11_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH11_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH11_S_RESET _u(0x1) +#define DMA_SECCFG_CH11_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH11_S_MSB _u(1) +#define DMA_SECCFG_CH11_S_LSB _u(1) +#define DMA_SECCFG_CH11_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH11_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH11_P_RESET _u(0x1) +#define DMA_SECCFG_CH11_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH11_P_MSB _u(0) +#define DMA_SECCFG_CH11_P_LSB _u(0) +#define DMA_SECCFG_CH11_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH12 +// Description : Security configuration for channel 12. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH12_OFFSET _u(0x000004b0) +#define DMA_SECCFG_CH12_BITS _u(0x00000007) +#define DMA_SECCFG_CH12_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH12_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH12_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH12_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH12_LOCK_MSB _u(2) +#define DMA_SECCFG_CH12_LOCK_LSB _u(2) +#define DMA_SECCFG_CH12_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH12_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH12_S_RESET _u(0x1) +#define DMA_SECCFG_CH12_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH12_S_MSB _u(1) +#define DMA_SECCFG_CH12_S_LSB _u(1) +#define DMA_SECCFG_CH12_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH12_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH12_P_RESET _u(0x1) +#define DMA_SECCFG_CH12_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH12_P_MSB _u(0) +#define DMA_SECCFG_CH12_P_LSB _u(0) +#define DMA_SECCFG_CH12_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH13 +// Description : Security configuration for channel 13. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH13_OFFSET _u(0x000004b4) +#define DMA_SECCFG_CH13_BITS _u(0x00000007) +#define DMA_SECCFG_CH13_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH13_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH13_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH13_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH13_LOCK_MSB _u(2) +#define DMA_SECCFG_CH13_LOCK_LSB _u(2) +#define DMA_SECCFG_CH13_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH13_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH13_S_RESET _u(0x1) +#define DMA_SECCFG_CH13_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH13_S_MSB _u(1) +#define DMA_SECCFG_CH13_S_LSB _u(1) +#define DMA_SECCFG_CH13_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH13_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH13_P_RESET _u(0x1) +#define DMA_SECCFG_CH13_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH13_P_MSB _u(0) +#define DMA_SECCFG_CH13_P_LSB _u(0) +#define DMA_SECCFG_CH13_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH14 +// Description : Security configuration for channel 14. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH14_OFFSET _u(0x000004b8) +#define DMA_SECCFG_CH14_BITS _u(0x00000007) +#define DMA_SECCFG_CH14_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH14_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH14_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH14_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH14_LOCK_MSB _u(2) +#define DMA_SECCFG_CH14_LOCK_LSB _u(2) +#define DMA_SECCFG_CH14_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH14_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH14_S_RESET _u(0x1) +#define DMA_SECCFG_CH14_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH14_S_MSB _u(1) +#define DMA_SECCFG_CH14_S_LSB _u(1) +#define DMA_SECCFG_CH14_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH14_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH14_P_RESET _u(0x1) +#define DMA_SECCFG_CH14_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH14_P_MSB _u(0) +#define DMA_SECCFG_CH14_P_LSB _u(0) +#define DMA_SECCFG_CH14_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_CH15 +// Description : Security configuration for channel 15. Control whether this +// channel performs Secure/Non-secure and Privileged/Unprivileged +// bus accesses. +// +// If this channel generates bus accesses of some security level, +// an access of at least that level (in the order S+P > S+U > NS+P +// > NS+U) is required to program, trigger, abort, check the +// status of, interrupt on or acknowledge the interrupt of this +// channel. +// +// This register automatically locks down (becomes read-only) once +// software starts to configure the channel. +// +// This register is world-readable, but is writable only from a +// Secure, Privileged context. +#define DMA_SECCFG_CH15_OFFSET _u(0x000004bc) +#define DMA_SECCFG_CH15_BITS _u(0x00000007) +#define DMA_SECCFG_CH15_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH15_LOCK +// Description : LOCK is 0 at reset, and is set to 1 automatically upon a +// successful write to this channel's control registers. That is, +// a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their +// aliases. +// +// Once its LOCK bit is set, this register becomes read-only. +// +// A failed write, for example due to the write's privilege being +// lower than that specified in the channel's SECCFG register, +// will not set the LOCK bit. +#define DMA_SECCFG_CH15_LOCK_RESET _u(0x0) +#define DMA_SECCFG_CH15_LOCK_BITS _u(0x00000004) +#define DMA_SECCFG_CH15_LOCK_MSB _u(2) +#define DMA_SECCFG_CH15_LOCK_LSB _u(2) +#define DMA_SECCFG_CH15_LOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH15_S +// Description : Secure channel. If 1, this channel performs Secure bus +// accesses. If 0, it performs Non-secure bus accesses. +// +// If 1, this channel is controllable only from a Secure context. +#define DMA_SECCFG_CH15_S_RESET _u(0x1) +#define DMA_SECCFG_CH15_S_BITS _u(0x00000002) +#define DMA_SECCFG_CH15_S_MSB _u(1) +#define DMA_SECCFG_CH15_S_LSB _u(1) +#define DMA_SECCFG_CH15_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_CH15_P +// Description : Privileged channel. If 1, this channel performs Privileged bus +// accesses. If 0, it performs Unprivileged bus accesses. +// +// If 1, this channel is controllable only from a Privileged +// context of the same Secure/Non-secure level, or any context of +// a higher Secure/Non-secure level. +#define DMA_SECCFG_CH15_P_RESET _u(0x1) +#define DMA_SECCFG_CH15_P_BITS _u(0x00000001) +#define DMA_SECCFG_CH15_P_MSB _u(0) +#define DMA_SECCFG_CH15_P_LSB _u(0) +#define DMA_SECCFG_CH15_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_IRQ0 +// Description : Security configuration for IRQ 0. Control whether the IRQ +// permits configuration by Non-secure/Unprivileged contexts, and +// whether it can observe Secure/Privileged channel interrupt +// flags. +#define DMA_SECCFG_IRQ0_OFFSET _u(0x000004c0) +#define DMA_SECCFG_IRQ0_BITS _u(0x00000003) +#define DMA_SECCFG_IRQ0_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ0_S +// Description : Secure IRQ. If 1, this IRQ's control registers can only be +// accessed from a Secure context. +// +// If 0, this IRQ's control registers can be accessed from a Non- +// secure context, but Secure channels (as per SECCFG_CHx) are +// masked from the IRQ status, and this IRQ's registers can not be +// used to acknowledge the channel interrupts of Secure channels. +#define DMA_SECCFG_IRQ0_S_RESET _u(0x1) +#define DMA_SECCFG_IRQ0_S_BITS _u(0x00000002) +#define DMA_SECCFG_IRQ0_S_MSB _u(1) +#define DMA_SECCFG_IRQ0_S_LSB _u(1) +#define DMA_SECCFG_IRQ0_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ0_P +// Description : Privileged IRQ. If 1, this IRQ's control registers can only be +// accessed from a Privileged context. +// +// If 0, this IRQ's control registers can be accessed from an +// Unprivileged context, but Privileged channels (as per +// SECCFG_CHx) are masked from the IRQ status, and this IRQ's +// registers can not be used to acknowledge the channel interrupts +// of Privileged channels. +#define DMA_SECCFG_IRQ0_P_RESET _u(0x1) +#define DMA_SECCFG_IRQ0_P_BITS _u(0x00000001) +#define DMA_SECCFG_IRQ0_P_MSB _u(0) +#define DMA_SECCFG_IRQ0_P_LSB _u(0) +#define DMA_SECCFG_IRQ0_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_IRQ1 +// Description : Security configuration for IRQ 1. Control whether the IRQ +// permits configuration by Non-secure/Unprivileged contexts, and +// whether it can observe Secure/Privileged channel interrupt +// flags. +#define DMA_SECCFG_IRQ1_OFFSET _u(0x000004c4) +#define DMA_SECCFG_IRQ1_BITS _u(0x00000003) +#define DMA_SECCFG_IRQ1_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ1_S +// Description : Secure IRQ. If 1, this IRQ's control registers can only be +// accessed from a Secure context. +// +// If 0, this IRQ's control registers can be accessed from a Non- +// secure context, but Secure channels (as per SECCFG_CHx) are +// masked from the IRQ status, and this IRQ's registers can not be +// used to acknowledge the channel interrupts of Secure channels. +#define DMA_SECCFG_IRQ1_S_RESET _u(0x1) +#define DMA_SECCFG_IRQ1_S_BITS _u(0x00000002) +#define DMA_SECCFG_IRQ1_S_MSB _u(1) +#define DMA_SECCFG_IRQ1_S_LSB _u(1) +#define DMA_SECCFG_IRQ1_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ1_P +// Description : Privileged IRQ. If 1, this IRQ's control registers can only be +// accessed from a Privileged context. +// +// If 0, this IRQ's control registers can be accessed from an +// Unprivileged context, but Privileged channels (as per +// SECCFG_CHx) are masked from the IRQ status, and this IRQ's +// registers can not be used to acknowledge the channel interrupts +// of Privileged channels. +#define DMA_SECCFG_IRQ1_P_RESET _u(0x1) +#define DMA_SECCFG_IRQ1_P_BITS _u(0x00000001) +#define DMA_SECCFG_IRQ1_P_MSB _u(0) +#define DMA_SECCFG_IRQ1_P_LSB _u(0) +#define DMA_SECCFG_IRQ1_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_IRQ2 +// Description : Security configuration for IRQ 2. Control whether the IRQ +// permits configuration by Non-secure/Unprivileged contexts, and +// whether it can observe Secure/Privileged channel interrupt +// flags. +#define DMA_SECCFG_IRQ2_OFFSET _u(0x000004c8) +#define DMA_SECCFG_IRQ2_BITS _u(0x00000003) +#define DMA_SECCFG_IRQ2_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ2_S +// Description : Secure IRQ. If 1, this IRQ's control registers can only be +// accessed from a Secure context. +// +// If 0, this IRQ's control registers can be accessed from a Non- +// secure context, but Secure channels (as per SECCFG_CHx) are +// masked from the IRQ status, and this IRQ's registers can not be +// used to acknowledge the channel interrupts of Secure channels. +#define DMA_SECCFG_IRQ2_S_RESET _u(0x1) +#define DMA_SECCFG_IRQ2_S_BITS _u(0x00000002) +#define DMA_SECCFG_IRQ2_S_MSB _u(1) +#define DMA_SECCFG_IRQ2_S_LSB _u(1) +#define DMA_SECCFG_IRQ2_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ2_P +// Description : Privileged IRQ. If 1, this IRQ's control registers can only be +// accessed from a Privileged context. +// +// If 0, this IRQ's control registers can be accessed from an +// Unprivileged context, but Privileged channels (as per +// SECCFG_CHx) are masked from the IRQ status, and this IRQ's +// registers can not be used to acknowledge the channel interrupts +// of Privileged channels. +#define DMA_SECCFG_IRQ2_P_RESET _u(0x1) +#define DMA_SECCFG_IRQ2_P_BITS _u(0x00000001) +#define DMA_SECCFG_IRQ2_P_MSB _u(0) +#define DMA_SECCFG_IRQ2_P_LSB _u(0) +#define DMA_SECCFG_IRQ2_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_IRQ3 +// Description : Security configuration for IRQ 3. Control whether the IRQ +// permits configuration by Non-secure/Unprivileged contexts, and +// whether it can observe Secure/Privileged channel interrupt +// flags. +#define DMA_SECCFG_IRQ3_OFFSET _u(0x000004cc) +#define DMA_SECCFG_IRQ3_BITS _u(0x00000003) +#define DMA_SECCFG_IRQ3_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ3_S +// Description : Secure IRQ. If 1, this IRQ's control registers can only be +// accessed from a Secure context. +// +// If 0, this IRQ's control registers can be accessed from a Non- +// secure context, but Secure channels (as per SECCFG_CHx) are +// masked from the IRQ status, and this IRQ's registers can not be +// used to acknowledge the channel interrupts of Secure channels. +#define DMA_SECCFG_IRQ3_S_RESET _u(0x1) +#define DMA_SECCFG_IRQ3_S_BITS _u(0x00000002) +#define DMA_SECCFG_IRQ3_S_MSB _u(1) +#define DMA_SECCFG_IRQ3_S_LSB _u(1) +#define DMA_SECCFG_IRQ3_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_IRQ3_P +// Description : Privileged IRQ. If 1, this IRQ's control registers can only be +// accessed from a Privileged context. +// +// If 0, this IRQ's control registers can be accessed from an +// Unprivileged context, but Privileged channels (as per +// SECCFG_CHx) are masked from the IRQ status, and this IRQ's +// registers can not be used to acknowledge the channel interrupts +// of Privileged channels. +#define DMA_SECCFG_IRQ3_P_RESET _u(0x1) +#define DMA_SECCFG_IRQ3_P_BITS _u(0x00000001) +#define DMA_SECCFG_IRQ3_P_MSB _u(0) +#define DMA_SECCFG_IRQ3_P_LSB _u(0) +#define DMA_SECCFG_IRQ3_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_SECCFG_MISC +// Description : Miscellaneous security configuration +#define DMA_SECCFG_MISC_OFFSET _u(0x000004d0) +#define DMA_SECCFG_MISC_BITS _u(0x000003ff) +#define DMA_SECCFG_MISC_RESET _u(0x000003ff) +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER3_S +// Description : If 1, the TIMER3 register is only accessible from a Secure +// context, and timer DREQ 3 is only visible to Secure channels. +#define DMA_SECCFG_MISC_TIMER3_S_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER3_S_BITS _u(0x00000200) +#define DMA_SECCFG_MISC_TIMER3_S_MSB _u(9) +#define DMA_SECCFG_MISC_TIMER3_S_LSB _u(9) +#define DMA_SECCFG_MISC_TIMER3_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER3_P +// Description : If 1, the TIMER3 register is only accessible from a Privileged +// (or more Secure) context, and timer DREQ 3 is only visible to +// Privileged (or more Secure) channels. +#define DMA_SECCFG_MISC_TIMER3_P_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER3_P_BITS _u(0x00000100) +#define DMA_SECCFG_MISC_TIMER3_P_MSB _u(8) +#define DMA_SECCFG_MISC_TIMER3_P_LSB _u(8) +#define DMA_SECCFG_MISC_TIMER3_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER2_S +// Description : If 1, the TIMER2 register is only accessible from a Secure +// context, and timer DREQ 2 is only visible to Secure channels. +#define DMA_SECCFG_MISC_TIMER2_S_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER2_S_BITS _u(0x00000080) +#define DMA_SECCFG_MISC_TIMER2_S_MSB _u(7) +#define DMA_SECCFG_MISC_TIMER2_S_LSB _u(7) +#define DMA_SECCFG_MISC_TIMER2_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER2_P +// Description : If 1, the TIMER2 register is only accessible from a Privileged +// (or more Secure) context, and timer DREQ 2 is only visible to +// Privileged (or more Secure) channels. +#define DMA_SECCFG_MISC_TIMER2_P_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER2_P_BITS _u(0x00000040) +#define DMA_SECCFG_MISC_TIMER2_P_MSB _u(6) +#define DMA_SECCFG_MISC_TIMER2_P_LSB _u(6) +#define DMA_SECCFG_MISC_TIMER2_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER1_S +// Description : If 1, the TIMER1 register is only accessible from a Secure +// context, and timer DREQ 1 is only visible to Secure channels. +#define DMA_SECCFG_MISC_TIMER1_S_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER1_S_BITS _u(0x00000020) +#define DMA_SECCFG_MISC_TIMER1_S_MSB _u(5) +#define DMA_SECCFG_MISC_TIMER1_S_LSB _u(5) +#define DMA_SECCFG_MISC_TIMER1_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER1_P +// Description : If 1, the TIMER1 register is only accessible from a Privileged +// (or more Secure) context, and timer DREQ 1 is only visible to +// Privileged (or more Secure) channels. +#define DMA_SECCFG_MISC_TIMER1_P_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER1_P_BITS _u(0x00000010) +#define DMA_SECCFG_MISC_TIMER1_P_MSB _u(4) +#define DMA_SECCFG_MISC_TIMER1_P_LSB _u(4) +#define DMA_SECCFG_MISC_TIMER1_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER0_S +// Description : If 1, the TIMER0 register is only accessible from a Secure +// context, and timer DREQ 0 is only visible to Secure channels. +#define DMA_SECCFG_MISC_TIMER0_S_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER0_S_BITS _u(0x00000008) +#define DMA_SECCFG_MISC_TIMER0_S_MSB _u(3) +#define DMA_SECCFG_MISC_TIMER0_S_LSB _u(3) +#define DMA_SECCFG_MISC_TIMER0_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_TIMER0_P +// Description : If 1, the TIMER0 register is only accessible from a Privileged +// (or more Secure) context, and timer DREQ 0 is only visible to +// Privileged (or more Secure) channels. +#define DMA_SECCFG_MISC_TIMER0_P_RESET _u(0x1) +#define DMA_SECCFG_MISC_TIMER0_P_BITS _u(0x00000004) +#define DMA_SECCFG_MISC_TIMER0_P_MSB _u(2) +#define DMA_SECCFG_MISC_TIMER0_P_LSB _u(2) +#define DMA_SECCFG_MISC_TIMER0_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_SNIFF_S +// Description : If 1, the sniffer can see data transfers from Secure channels, +// and can itself only be accessed from a Secure context. +// +// If 0, the sniffer can be accessed from either a Secure or Non- +// secure context, but can not see data transfers of Secure +// channels. +#define DMA_SECCFG_MISC_SNIFF_S_RESET _u(0x1) +#define DMA_SECCFG_MISC_SNIFF_S_BITS _u(0x00000002) +#define DMA_SECCFG_MISC_SNIFF_S_MSB _u(1) +#define DMA_SECCFG_MISC_SNIFF_S_LSB _u(1) +#define DMA_SECCFG_MISC_SNIFF_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_SECCFG_MISC_SNIFF_P +// Description : If 1, the sniffer can see data transfers from Privileged +// channels, and can itself only be accessed from a privileged +// context, or from a Secure context when SNIFF_S is 0. +// +// If 0, the sniffer can be accessed from either a Privileged or +// Unprivileged context (with sufficient security level) but can +// not see transfers from Privileged channels. +#define DMA_SECCFG_MISC_SNIFF_P_RESET _u(0x1) +#define DMA_SECCFG_MISC_SNIFF_P_BITS _u(0x00000001) +#define DMA_SECCFG_MISC_SNIFF_P_MSB _u(0) +#define DMA_SECCFG_MISC_SNIFF_P_LSB _u(0) +#define DMA_SECCFG_MISC_SNIFF_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_CTRL +// Description : Control register for DMA MPU. Accessible only from a Privileged +// context. +#define DMA_MPU_CTRL_OFFSET _u(0x00000500) +#define DMA_MPU_CTRL_BITS _u(0x0000000e) +#define DMA_MPU_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_CTRL_NS_HIDE_ADDR +// Description : By default, when a region's S bit is clear, Non-secure- +// Privileged reads can see the region's base address and limit +// address. Set this bit to make the addresses appear as 0 to Non- +// secure reads, even when the region is Non-secure, to avoid +// leaking information about the processor SAU map. +#define DMA_MPU_CTRL_NS_HIDE_ADDR_RESET _u(0x0) +#define DMA_MPU_CTRL_NS_HIDE_ADDR_BITS _u(0x00000008) +#define DMA_MPU_CTRL_NS_HIDE_ADDR_MSB _u(3) +#define DMA_MPU_CTRL_NS_HIDE_ADDR_LSB _u(3) +#define DMA_MPU_CTRL_NS_HIDE_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_CTRL_S +// Description : Determine whether an address not covered by an active MPU +// region is Secure (1) or Non-secure (0) +#define DMA_MPU_CTRL_S_RESET _u(0x0) +#define DMA_MPU_CTRL_S_BITS _u(0x00000004) +#define DMA_MPU_CTRL_S_MSB _u(2) +#define DMA_MPU_CTRL_S_LSB _u(2) +#define DMA_MPU_CTRL_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_CTRL_P +// Description : Determine whether an address not covered by an active MPU +// region is Privileged (1) or Unprivileged (0) +#define DMA_MPU_CTRL_P_RESET _u(0x0) +#define DMA_MPU_CTRL_P_BITS _u(0x00000002) +#define DMA_MPU_CTRL_P_MSB _u(1) +#define DMA_MPU_CTRL_P_LSB _u(1) +#define DMA_MPU_CTRL_P_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR0 +// Description : Base address register for MPU region 0. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR0_OFFSET _u(0x00000504) +#define DMA_MPU_BAR0_BITS _u(0xffffffe0) +#define DMA_MPU_BAR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR0_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR0_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR0_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR0_ADDR_MSB _u(31) +#define DMA_MPU_BAR0_ADDR_LSB _u(5) +#define DMA_MPU_BAR0_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR0 +// Description : Limit address register for MPU region 0. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR0_OFFSET _u(0x00000508) +#define DMA_MPU_LAR0_BITS _u(0xffffffe7) +#define DMA_MPU_LAR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR0_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR0_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR0_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR0_ADDR_MSB _u(31) +#define DMA_MPU_LAR0_ADDR_LSB _u(5) +#define DMA_MPU_LAR0_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR0_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR0_S_RESET _u(0x0) +#define DMA_MPU_LAR0_S_BITS _u(0x00000004) +#define DMA_MPU_LAR0_S_MSB _u(2) +#define DMA_MPU_LAR0_S_LSB _u(2) +#define DMA_MPU_LAR0_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR0_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR0_P_RESET _u(0x0) +#define DMA_MPU_LAR0_P_BITS _u(0x00000002) +#define DMA_MPU_LAR0_P_MSB _u(1) +#define DMA_MPU_LAR0_P_LSB _u(1) +#define DMA_MPU_LAR0_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR0_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR0_EN_RESET _u(0x0) +#define DMA_MPU_LAR0_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR0_EN_MSB _u(0) +#define DMA_MPU_LAR0_EN_LSB _u(0) +#define DMA_MPU_LAR0_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR1 +// Description : Base address register for MPU region 1. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR1_OFFSET _u(0x0000050c) +#define DMA_MPU_BAR1_BITS _u(0xffffffe0) +#define DMA_MPU_BAR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR1_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR1_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR1_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR1_ADDR_MSB _u(31) +#define DMA_MPU_BAR1_ADDR_LSB _u(5) +#define DMA_MPU_BAR1_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR1 +// Description : Limit address register for MPU region 1. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR1_OFFSET _u(0x00000510) +#define DMA_MPU_LAR1_BITS _u(0xffffffe7) +#define DMA_MPU_LAR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR1_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR1_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR1_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR1_ADDR_MSB _u(31) +#define DMA_MPU_LAR1_ADDR_LSB _u(5) +#define DMA_MPU_LAR1_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR1_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR1_S_RESET _u(0x0) +#define DMA_MPU_LAR1_S_BITS _u(0x00000004) +#define DMA_MPU_LAR1_S_MSB _u(2) +#define DMA_MPU_LAR1_S_LSB _u(2) +#define DMA_MPU_LAR1_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR1_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR1_P_RESET _u(0x0) +#define DMA_MPU_LAR1_P_BITS _u(0x00000002) +#define DMA_MPU_LAR1_P_MSB _u(1) +#define DMA_MPU_LAR1_P_LSB _u(1) +#define DMA_MPU_LAR1_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR1_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR1_EN_RESET _u(0x0) +#define DMA_MPU_LAR1_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR1_EN_MSB _u(0) +#define DMA_MPU_LAR1_EN_LSB _u(0) +#define DMA_MPU_LAR1_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR2 +// Description : Base address register for MPU region 2. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR2_OFFSET _u(0x00000514) +#define DMA_MPU_BAR2_BITS _u(0xffffffe0) +#define DMA_MPU_BAR2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR2_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR2_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR2_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR2_ADDR_MSB _u(31) +#define DMA_MPU_BAR2_ADDR_LSB _u(5) +#define DMA_MPU_BAR2_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR2 +// Description : Limit address register for MPU region 2. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR2_OFFSET _u(0x00000518) +#define DMA_MPU_LAR2_BITS _u(0xffffffe7) +#define DMA_MPU_LAR2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR2_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR2_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR2_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR2_ADDR_MSB _u(31) +#define DMA_MPU_LAR2_ADDR_LSB _u(5) +#define DMA_MPU_LAR2_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR2_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR2_S_RESET _u(0x0) +#define DMA_MPU_LAR2_S_BITS _u(0x00000004) +#define DMA_MPU_LAR2_S_MSB _u(2) +#define DMA_MPU_LAR2_S_LSB _u(2) +#define DMA_MPU_LAR2_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR2_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR2_P_RESET _u(0x0) +#define DMA_MPU_LAR2_P_BITS _u(0x00000002) +#define DMA_MPU_LAR2_P_MSB _u(1) +#define DMA_MPU_LAR2_P_LSB _u(1) +#define DMA_MPU_LAR2_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR2_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR2_EN_RESET _u(0x0) +#define DMA_MPU_LAR2_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR2_EN_MSB _u(0) +#define DMA_MPU_LAR2_EN_LSB _u(0) +#define DMA_MPU_LAR2_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR3 +// Description : Base address register for MPU region 3. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR3_OFFSET _u(0x0000051c) +#define DMA_MPU_BAR3_BITS _u(0xffffffe0) +#define DMA_MPU_BAR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR3_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR3_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR3_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR3_ADDR_MSB _u(31) +#define DMA_MPU_BAR3_ADDR_LSB _u(5) +#define DMA_MPU_BAR3_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR3 +// Description : Limit address register for MPU region 3. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR3_OFFSET _u(0x00000520) +#define DMA_MPU_LAR3_BITS _u(0xffffffe7) +#define DMA_MPU_LAR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR3_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR3_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR3_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR3_ADDR_MSB _u(31) +#define DMA_MPU_LAR3_ADDR_LSB _u(5) +#define DMA_MPU_LAR3_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR3_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR3_S_RESET _u(0x0) +#define DMA_MPU_LAR3_S_BITS _u(0x00000004) +#define DMA_MPU_LAR3_S_MSB _u(2) +#define DMA_MPU_LAR3_S_LSB _u(2) +#define DMA_MPU_LAR3_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR3_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR3_P_RESET _u(0x0) +#define DMA_MPU_LAR3_P_BITS _u(0x00000002) +#define DMA_MPU_LAR3_P_MSB _u(1) +#define DMA_MPU_LAR3_P_LSB _u(1) +#define DMA_MPU_LAR3_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR3_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR3_EN_RESET _u(0x0) +#define DMA_MPU_LAR3_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR3_EN_MSB _u(0) +#define DMA_MPU_LAR3_EN_LSB _u(0) +#define DMA_MPU_LAR3_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR4 +// Description : Base address register for MPU region 4. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR4_OFFSET _u(0x00000524) +#define DMA_MPU_BAR4_BITS _u(0xffffffe0) +#define DMA_MPU_BAR4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR4_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR4_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR4_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR4_ADDR_MSB _u(31) +#define DMA_MPU_BAR4_ADDR_LSB _u(5) +#define DMA_MPU_BAR4_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR4 +// Description : Limit address register for MPU region 4. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR4_OFFSET _u(0x00000528) +#define DMA_MPU_LAR4_BITS _u(0xffffffe7) +#define DMA_MPU_LAR4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR4_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR4_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR4_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR4_ADDR_MSB _u(31) +#define DMA_MPU_LAR4_ADDR_LSB _u(5) +#define DMA_MPU_LAR4_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR4_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR4_S_RESET _u(0x0) +#define DMA_MPU_LAR4_S_BITS _u(0x00000004) +#define DMA_MPU_LAR4_S_MSB _u(2) +#define DMA_MPU_LAR4_S_LSB _u(2) +#define DMA_MPU_LAR4_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR4_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR4_P_RESET _u(0x0) +#define DMA_MPU_LAR4_P_BITS _u(0x00000002) +#define DMA_MPU_LAR4_P_MSB _u(1) +#define DMA_MPU_LAR4_P_LSB _u(1) +#define DMA_MPU_LAR4_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR4_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR4_EN_RESET _u(0x0) +#define DMA_MPU_LAR4_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR4_EN_MSB _u(0) +#define DMA_MPU_LAR4_EN_LSB _u(0) +#define DMA_MPU_LAR4_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR5 +// Description : Base address register for MPU region 5. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR5_OFFSET _u(0x0000052c) +#define DMA_MPU_BAR5_BITS _u(0xffffffe0) +#define DMA_MPU_BAR5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR5_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR5_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR5_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR5_ADDR_MSB _u(31) +#define DMA_MPU_BAR5_ADDR_LSB _u(5) +#define DMA_MPU_BAR5_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR5 +// Description : Limit address register for MPU region 5. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR5_OFFSET _u(0x00000530) +#define DMA_MPU_LAR5_BITS _u(0xffffffe7) +#define DMA_MPU_LAR5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR5_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR5_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR5_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR5_ADDR_MSB _u(31) +#define DMA_MPU_LAR5_ADDR_LSB _u(5) +#define DMA_MPU_LAR5_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR5_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR5_S_RESET _u(0x0) +#define DMA_MPU_LAR5_S_BITS _u(0x00000004) +#define DMA_MPU_LAR5_S_MSB _u(2) +#define DMA_MPU_LAR5_S_LSB _u(2) +#define DMA_MPU_LAR5_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR5_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR5_P_RESET _u(0x0) +#define DMA_MPU_LAR5_P_BITS _u(0x00000002) +#define DMA_MPU_LAR5_P_MSB _u(1) +#define DMA_MPU_LAR5_P_LSB _u(1) +#define DMA_MPU_LAR5_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR5_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR5_EN_RESET _u(0x0) +#define DMA_MPU_LAR5_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR5_EN_MSB _u(0) +#define DMA_MPU_LAR5_EN_LSB _u(0) +#define DMA_MPU_LAR5_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR6 +// Description : Base address register for MPU region 6. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR6_OFFSET _u(0x00000534) +#define DMA_MPU_BAR6_BITS _u(0xffffffe0) +#define DMA_MPU_BAR6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR6_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR6_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR6_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR6_ADDR_MSB _u(31) +#define DMA_MPU_BAR6_ADDR_LSB _u(5) +#define DMA_MPU_BAR6_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR6 +// Description : Limit address register for MPU region 6. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR6_OFFSET _u(0x00000538) +#define DMA_MPU_LAR6_BITS _u(0xffffffe7) +#define DMA_MPU_LAR6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR6_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR6_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR6_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR6_ADDR_MSB _u(31) +#define DMA_MPU_LAR6_ADDR_LSB _u(5) +#define DMA_MPU_LAR6_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR6_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR6_S_RESET _u(0x0) +#define DMA_MPU_LAR6_S_BITS _u(0x00000004) +#define DMA_MPU_LAR6_S_MSB _u(2) +#define DMA_MPU_LAR6_S_LSB _u(2) +#define DMA_MPU_LAR6_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR6_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR6_P_RESET _u(0x0) +#define DMA_MPU_LAR6_P_BITS _u(0x00000002) +#define DMA_MPU_LAR6_P_MSB _u(1) +#define DMA_MPU_LAR6_P_LSB _u(1) +#define DMA_MPU_LAR6_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR6_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR6_EN_RESET _u(0x0) +#define DMA_MPU_LAR6_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR6_EN_MSB _u(0) +#define DMA_MPU_LAR6_EN_LSB _u(0) +#define DMA_MPU_LAR6_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_BAR7 +// Description : Base address register for MPU region 7. Writable only from a +// Secure, Privileged context. +#define DMA_MPU_BAR7_OFFSET _u(0x0000053c) +#define DMA_MPU_BAR7_BITS _u(0xffffffe0) +#define DMA_MPU_BAR7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_BAR7_ADDR +// Description : This MPU region matches addresses where addr[31:5] (the 27 most +// significant bits) are greater than or equal to BAR_ADDR, and +// less than or equal to LAR_ADDR. +// +// Readable from any Privileged context, if and only if this +// region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. +// Otherwise readable only from a Secure, Privileged context. +#define DMA_MPU_BAR7_ADDR_RESET _u(0x0000000) +#define DMA_MPU_BAR7_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_BAR7_ADDR_MSB _u(31) +#define DMA_MPU_BAR7_ADDR_LSB _u(5) +#define DMA_MPU_BAR7_ADDR_ACCESS "RW" +// ============================================================================= +// Register : DMA_MPU_LAR7 +// Description : Limit address register for MPU region 7. Writable only from a +// Secure, Privileged context, with the exception of the P bit. +#define DMA_MPU_LAR7_OFFSET _u(0x00000540) +#define DMA_MPU_LAR7_BITS _u(0xffffffe7) +#define DMA_MPU_LAR7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR7_ADDR +// Description : Limit address bits 31:5. Readable from any Privileged context, +// if and only if this region's S bit is clear, and +// MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a +// Secure, Privileged context. +#define DMA_MPU_LAR7_ADDR_RESET _u(0x0000000) +#define DMA_MPU_LAR7_ADDR_BITS _u(0xffffffe0) +#define DMA_MPU_LAR7_ADDR_MSB _u(31) +#define DMA_MPU_LAR7_ADDR_LSB _u(5) +#define DMA_MPU_LAR7_ADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR7_S +// Description : Determines the Secure/Non-secure (=1/0) status of addresses +// matching this region, if this region is enabled. +#define DMA_MPU_LAR7_S_RESET _u(0x0) +#define DMA_MPU_LAR7_S_BITS _u(0x00000004) +#define DMA_MPU_LAR7_S_MSB _u(2) +#define DMA_MPU_LAR7_S_LSB _u(2) +#define DMA_MPU_LAR7_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR7_P +// Description : Determines the Privileged/Unprivileged (=1/0) status of +// addresses matching this region, if this region is enabled. +// Writable from any Privileged context, if and only if the S bit +// is clear. Otherwise, writable only from a Secure, Privileged +// context. +#define DMA_MPU_LAR7_P_RESET _u(0x0) +#define DMA_MPU_LAR7_P_BITS _u(0x00000002) +#define DMA_MPU_LAR7_P_MSB _u(1) +#define DMA_MPU_LAR7_P_LSB _u(1) +#define DMA_MPU_LAR7_P_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : DMA_MPU_LAR7_EN +// Description : Region enable. If 1, any address within range specified by the +// base address (BAR_ADDR) and limit address (LAR_ADDR) has the +// attributes specified by S and P. +#define DMA_MPU_LAR7_EN_RESET _u(0x0) +#define DMA_MPU_LAR7_EN_BITS _u(0x00000001) +#define DMA_MPU_LAR7_EN_MSB _u(0) +#define DMA_MPU_LAR7_EN_LSB _u(0) +#define DMA_MPU_LAR7_EN_ACCESS "RW" +// ============================================================================= +// Register : DMA_CH0_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH0_DBG_CTDREQ_OFFSET _u(0x00000800) +#define DMA_CH0_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH0_DBG_CTDREQ_MSB _u(5) +#define DMA_CH0_DBG_CTDREQ_LSB _u(0) +#define DMA_CH0_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH0_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH0_DBG_TCR_OFFSET _u(0x00000804) +#define DMA_CH0_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH0_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH0_DBG_TCR_MSB _u(31) +#define DMA_CH0_DBG_TCR_LSB _u(0) +#define DMA_CH0_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH1_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH1_DBG_CTDREQ_OFFSET _u(0x00000840) +#define DMA_CH1_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH1_DBG_CTDREQ_MSB _u(5) +#define DMA_CH1_DBG_CTDREQ_LSB _u(0) +#define DMA_CH1_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH1_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH1_DBG_TCR_OFFSET _u(0x00000844) +#define DMA_CH1_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH1_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH1_DBG_TCR_MSB _u(31) +#define DMA_CH1_DBG_TCR_LSB _u(0) +#define DMA_CH1_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH2_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH2_DBG_CTDREQ_OFFSET _u(0x00000880) +#define DMA_CH2_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH2_DBG_CTDREQ_MSB _u(5) +#define DMA_CH2_DBG_CTDREQ_LSB _u(0) +#define DMA_CH2_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH2_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH2_DBG_TCR_OFFSET _u(0x00000884) +#define DMA_CH2_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH2_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH2_DBG_TCR_MSB _u(31) +#define DMA_CH2_DBG_TCR_LSB _u(0) +#define DMA_CH2_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH3_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH3_DBG_CTDREQ_OFFSET _u(0x000008c0) +#define DMA_CH3_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH3_DBG_CTDREQ_MSB _u(5) +#define DMA_CH3_DBG_CTDREQ_LSB _u(0) +#define DMA_CH3_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH3_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH3_DBG_TCR_OFFSET _u(0x000008c4) +#define DMA_CH3_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH3_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH3_DBG_TCR_MSB _u(31) +#define DMA_CH3_DBG_TCR_LSB _u(0) +#define DMA_CH3_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH4_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH4_DBG_CTDREQ_OFFSET _u(0x00000900) +#define DMA_CH4_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH4_DBG_CTDREQ_MSB _u(5) +#define DMA_CH4_DBG_CTDREQ_LSB _u(0) +#define DMA_CH4_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH4_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH4_DBG_TCR_OFFSET _u(0x00000904) +#define DMA_CH4_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH4_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH4_DBG_TCR_MSB _u(31) +#define DMA_CH4_DBG_TCR_LSB _u(0) +#define DMA_CH4_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH5_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH5_DBG_CTDREQ_OFFSET _u(0x00000940) +#define DMA_CH5_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH5_DBG_CTDREQ_MSB _u(5) +#define DMA_CH5_DBG_CTDREQ_LSB _u(0) +#define DMA_CH5_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH5_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH5_DBG_TCR_OFFSET _u(0x00000944) +#define DMA_CH5_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH5_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH5_DBG_TCR_MSB _u(31) +#define DMA_CH5_DBG_TCR_LSB _u(0) +#define DMA_CH5_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH6_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH6_DBG_CTDREQ_OFFSET _u(0x00000980) +#define DMA_CH6_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH6_DBG_CTDREQ_MSB _u(5) +#define DMA_CH6_DBG_CTDREQ_LSB _u(0) +#define DMA_CH6_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH6_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH6_DBG_TCR_OFFSET _u(0x00000984) +#define DMA_CH6_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH6_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH6_DBG_TCR_MSB _u(31) +#define DMA_CH6_DBG_TCR_LSB _u(0) +#define DMA_CH6_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH7_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH7_DBG_CTDREQ_OFFSET _u(0x000009c0) +#define DMA_CH7_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH7_DBG_CTDREQ_MSB _u(5) +#define DMA_CH7_DBG_CTDREQ_LSB _u(0) +#define DMA_CH7_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH7_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH7_DBG_TCR_OFFSET _u(0x000009c4) +#define DMA_CH7_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH7_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH7_DBG_TCR_MSB _u(31) +#define DMA_CH7_DBG_TCR_LSB _u(0) +#define DMA_CH7_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH8_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH8_DBG_CTDREQ_OFFSET _u(0x00000a00) +#define DMA_CH8_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH8_DBG_CTDREQ_MSB _u(5) +#define DMA_CH8_DBG_CTDREQ_LSB _u(0) +#define DMA_CH8_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH8_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH8_DBG_TCR_OFFSET _u(0x00000a04) +#define DMA_CH8_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH8_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH8_DBG_TCR_MSB _u(31) +#define DMA_CH8_DBG_TCR_LSB _u(0) +#define DMA_CH8_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH9_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH9_DBG_CTDREQ_OFFSET _u(0x00000a40) +#define DMA_CH9_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH9_DBG_CTDREQ_MSB _u(5) +#define DMA_CH9_DBG_CTDREQ_LSB _u(0) +#define DMA_CH9_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH9_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH9_DBG_TCR_OFFSET _u(0x00000a44) +#define DMA_CH9_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH9_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH9_DBG_TCR_MSB _u(31) +#define DMA_CH9_DBG_TCR_LSB _u(0) +#define DMA_CH9_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH10_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH10_DBG_CTDREQ_OFFSET _u(0x00000a80) +#define DMA_CH10_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH10_DBG_CTDREQ_MSB _u(5) +#define DMA_CH10_DBG_CTDREQ_LSB _u(0) +#define DMA_CH10_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH10_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH10_DBG_TCR_OFFSET _u(0x00000a84) +#define DMA_CH10_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH10_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH10_DBG_TCR_MSB _u(31) +#define DMA_CH10_DBG_TCR_LSB _u(0) +#define DMA_CH10_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH11_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH11_DBG_CTDREQ_OFFSET _u(0x00000ac0) +#define DMA_CH11_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH11_DBG_CTDREQ_MSB _u(5) +#define DMA_CH11_DBG_CTDREQ_LSB _u(0) +#define DMA_CH11_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH11_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH11_DBG_TCR_OFFSET _u(0x00000ac4) +#define DMA_CH11_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH11_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH11_DBG_TCR_MSB _u(31) +#define DMA_CH11_DBG_TCR_LSB _u(0) +#define DMA_CH11_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH12_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH12_DBG_CTDREQ_OFFSET _u(0x00000b00) +#define DMA_CH12_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH12_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH12_DBG_CTDREQ_MSB _u(5) +#define DMA_CH12_DBG_CTDREQ_LSB _u(0) +#define DMA_CH12_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH12_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH12_DBG_TCR_OFFSET _u(0x00000b04) +#define DMA_CH12_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH12_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH12_DBG_TCR_MSB _u(31) +#define DMA_CH12_DBG_TCR_LSB _u(0) +#define DMA_CH12_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH13_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH13_DBG_CTDREQ_OFFSET _u(0x00000b40) +#define DMA_CH13_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH13_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH13_DBG_CTDREQ_MSB _u(5) +#define DMA_CH13_DBG_CTDREQ_LSB _u(0) +#define DMA_CH13_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH13_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH13_DBG_TCR_OFFSET _u(0x00000b44) +#define DMA_CH13_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH13_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH13_DBG_TCR_MSB _u(31) +#define DMA_CH13_DBG_TCR_LSB _u(0) +#define DMA_CH13_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH14_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH14_DBG_CTDREQ_OFFSET _u(0x00000b80) +#define DMA_CH14_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH14_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH14_DBG_CTDREQ_MSB _u(5) +#define DMA_CH14_DBG_CTDREQ_LSB _u(0) +#define DMA_CH14_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH14_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH14_DBG_TCR_OFFSET _u(0x00000b84) +#define DMA_CH14_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH14_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH14_DBG_TCR_MSB _u(31) +#define DMA_CH14_DBG_TCR_LSB _u(0) +#define DMA_CH14_DBG_TCR_ACCESS "RO" +// ============================================================================= +// Register : DMA_CH15_DBG_CTDREQ +// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA +// expects it can perform on the peripheral without +// overflow/underflow. Write any value: clears the counter, and +// cause channel to re-initiate DREQ handshake. +#define DMA_CH15_DBG_CTDREQ_OFFSET _u(0x00000bc0) +#define DMA_CH15_DBG_CTDREQ_BITS _u(0x0000003f) +#define DMA_CH15_DBG_CTDREQ_RESET _u(0x00000000) +#define DMA_CH15_DBG_CTDREQ_MSB _u(5) +#define DMA_CH15_DBG_CTDREQ_LSB _u(0) +#define DMA_CH15_DBG_CTDREQ_ACCESS "WC" +// ============================================================================= +// Register : DMA_CH15_DBG_TCR +// Description : Read to get channel TRANS_COUNT reload value, i.e. the length +// of the next transfer +#define DMA_CH15_DBG_TCR_OFFSET _u(0x00000bc4) +#define DMA_CH15_DBG_TCR_BITS _u(0xffffffff) +#define DMA_CH15_DBG_TCR_RESET _u(0x00000000) +#define DMA_CH15_DBG_TCR_MSB _u(31) +#define DMA_CH15_DBG_TCR_LSB _u(0) +#define DMA_CH15_DBG_TCR_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_DMA_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/dreq.h b/lib/pico-sdk/rp2350/hardware/regs/dreq.h new file mode 100644 index 000000000000..6d126c0df83e --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/dreq.h @@ -0,0 +1,147 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _DREQ_H +#define _DREQ_H + +/** + * \file rp2350/dreq.h + */ + +#ifdef __ASSEMBLER__ +#define DREQ_PIO0_TX0 0 +#define DREQ_PIO0_TX1 1 +#define DREQ_PIO0_TX2 2 +#define DREQ_PIO0_TX3 3 +#define DREQ_PIO0_RX0 4 +#define DREQ_PIO0_RX1 5 +#define DREQ_PIO0_RX2 6 +#define DREQ_PIO0_RX3 7 +#define DREQ_PIO1_TX0 8 +#define DREQ_PIO1_TX1 9 +#define DREQ_PIO1_TX2 10 +#define DREQ_PIO1_TX3 11 +#define DREQ_PIO1_RX0 12 +#define DREQ_PIO1_RX1 13 +#define DREQ_PIO1_RX2 14 +#define DREQ_PIO1_RX3 15 +#define DREQ_PIO2_TX0 16 +#define DREQ_PIO2_TX1 17 +#define DREQ_PIO2_TX2 18 +#define DREQ_PIO2_TX3 19 +#define DREQ_PIO2_RX0 20 +#define DREQ_PIO2_RX1 21 +#define DREQ_PIO2_RX2 22 +#define DREQ_PIO2_RX3 23 +#define DREQ_SPI0_TX 24 +#define DREQ_SPI0_RX 25 +#define DREQ_SPI1_TX 26 +#define DREQ_SPI1_RX 27 +#define DREQ_UART0_TX 28 +#define DREQ_UART0_RX 29 +#define DREQ_UART1_TX 30 +#define DREQ_UART1_RX 31 +#define DREQ_PWM_WRAP0 32 +#define DREQ_PWM_WRAP1 33 +#define DREQ_PWM_WRAP2 34 +#define DREQ_PWM_WRAP3 35 +#define DREQ_PWM_WRAP4 36 +#define DREQ_PWM_WRAP5 37 +#define DREQ_PWM_WRAP6 38 +#define DREQ_PWM_WRAP7 39 +#define DREQ_PWM_WRAP8 40 +#define DREQ_PWM_WRAP9 41 +#define DREQ_PWM_WRAP10 42 +#define DREQ_PWM_WRAP11 43 +#define DREQ_I2C0_TX 44 +#define DREQ_I2C0_RX 45 +#define DREQ_I2C1_TX 46 +#define DREQ_I2C1_RX 47 +#define DREQ_ADC 48 +#define DREQ_XIP_STREAM 49 +#define DREQ_XIP_QMITX 50 +#define DREQ_XIP_QMIRX 51 +#define DREQ_HSTX 52 +#define DREQ_CORESIGHT 53 +#define DREQ_SHA256 54 +#define DREQ_DMA_TIMER0 59 +#define DREQ_DMA_TIMER1 60 +#define DREQ_DMA_TIMER2 61 +#define DREQ_DMA_TIMER3 62 +#define DREQ_FORCE 63 +#else +/** + * \brief DREQ numbers for DMA pacing on RP2350 (used as typedef \ref dreq_num_t) + * \ingroup hardware_dma + */ +typedef enum dreq_num_rp2350 { + DREQ_PIO0_TX0 = 0, ///< Select PIO0's TX FIFO 0 as DREQ + DREQ_PIO0_TX1 = 1, ///< Select PIO0's TX FIFO 1 as DREQ + DREQ_PIO0_TX2 = 2, ///< Select PIO0's TX FIFO 2 as DREQ + DREQ_PIO0_TX3 = 3, ///< Select PIO0's TX FIFO 3 as DREQ + DREQ_PIO0_RX0 = 4, ///< Select PIO0's RX FIFO 0 as DREQ + DREQ_PIO0_RX1 = 5, ///< Select PIO0's RX FIFO 1 as DREQ + DREQ_PIO0_RX2 = 6, ///< Select PIO0's RX FIFO 2 as DREQ + DREQ_PIO0_RX3 = 7, ///< Select PIO0's RX FIFO 3 as DREQ + DREQ_PIO1_TX0 = 8, ///< Select PIO1's TX FIFO 0 as DREQ + DREQ_PIO1_TX1 = 9, ///< Select PIO1's TX FIFO 1 as DREQ + DREQ_PIO1_TX2 = 10, ///< Select PIO1's TX FIFO 2 as DREQ + DREQ_PIO1_TX3 = 11, ///< Select PIO1's TX FIFO 3 as DREQ + DREQ_PIO1_RX0 = 12, ///< Select PIO1's RX FIFO 0 as DREQ + DREQ_PIO1_RX1 = 13, ///< Select PIO1's RX FIFO 1 as DREQ + DREQ_PIO1_RX2 = 14, ///< Select PIO1's RX FIFO 2 as DREQ + DREQ_PIO1_RX3 = 15, ///< Select PIO1's RX FIFO 3 as DREQ + DREQ_PIO2_TX0 = 16, ///< Select PIO2's TX FIFO 0 as DREQ + DREQ_PIO2_TX1 = 17, ///< Select PIO2's TX FIFO 1 as DREQ + DREQ_PIO2_TX2 = 18, ///< Select PIO2's TX FIFO 2 as DREQ + DREQ_PIO2_TX3 = 19, ///< Select PIO2's TX FIFO 3 as DREQ + DREQ_PIO2_RX0 = 20, ///< Select PIO2's RX FIFO 0 as DREQ + DREQ_PIO2_RX1 = 21, ///< Select PIO2's RX FIFO 1 as DREQ + DREQ_PIO2_RX2 = 22, ///< Select PIO2's RX FIFO 2 as DREQ + DREQ_PIO2_RX3 = 23, ///< Select PIO2's RX FIFO 3 as DREQ + DREQ_SPI0_TX = 24, ///< Select SPI0's TX FIFO as DREQ + DREQ_SPI0_RX = 25, ///< Select SPI0's RX FIFO as DREQ + DREQ_SPI1_TX = 26, ///< Select SPI1's TX FIFO as DREQ + DREQ_SPI1_RX = 27, ///< Select SPI1's RX FIFO as DREQ + DREQ_UART0_TX = 28, ///< Select UART0's TX FIFO as DREQ + DREQ_UART0_RX = 29, ///< Select UART0's RX FIFO as DREQ + DREQ_UART1_TX = 30, ///< Select UART1's TX FIFO as DREQ + DREQ_UART1_RX = 31, ///< Select UART1's RX FIFO as DREQ + DREQ_PWM_WRAP0 = 32, ///< Select PWM Counter 0's Wrap Value as DREQ + DREQ_PWM_WRAP1 = 33, ///< Select PWM Counter 1's Wrap Value as DREQ + DREQ_PWM_WRAP2 = 34, ///< Select PWM Counter 2's Wrap Value as DREQ + DREQ_PWM_WRAP3 = 35, ///< Select PWM Counter 3's Wrap Value as DREQ + DREQ_PWM_WRAP4 = 36, ///< Select PWM Counter 4's Wrap Value as DREQ + DREQ_PWM_WRAP5 = 37, ///< Select PWM Counter 5's Wrap Value as DREQ + DREQ_PWM_WRAP6 = 38, ///< Select PWM Counter 6's Wrap Value as DREQ + DREQ_PWM_WRAP7 = 39, ///< Select PWM Counter 7's Wrap Value as DREQ + DREQ_PWM_WRAP8 = 40, ///< Select PWM Counter 8's Wrap Value as DREQ + DREQ_PWM_WRAP9 = 41, ///< Select PWM Counter 9's Wrap Value as DREQ + DREQ_PWM_WRAP10 = 42, ///< Select PWM Counter 0's Wrap Value as DREQ + DREQ_PWM_WRAP11 = 43, ///< Select PWM Counter 1's Wrap Value as DREQ + DREQ_I2C0_TX = 44, ///< Select I2C0's TX FIFO as DREQ + DREQ_I2C0_RX = 45, ///< Select I2C0's RX FIFO as DREQ + DREQ_I2C1_TX = 46, ///< Select I2C1's TX FIFO as DREQ + DREQ_I2C1_RX = 47, ///< Select I2C1's RX FIFO as DREQ + DREQ_ADC = 48, ///< Select the ADC as DREQ + DREQ_XIP_STREAM = 49, ///< Select the XIP Streaming FIFO as DREQ + DREQ_XIP_QMITX = 50, ///< Select XIP_QMITX as DREQ + DREQ_XIP_QMIRX = 51, ///< Select XIP_QMIRX as DREQ + DREQ_HSTX = 52, ///< Select HSTX as DREQ + DREQ_CORESIGHT = 53, ///< Select CORESIGHT as DREQ + DREQ_SHA256 = 54, ///< Select SHA256 as DREQ + DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ + DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ + DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ + DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ + DREQ_FORCE = 63, ///< Select FORCE as DREQ + DREQ_COUNT +} dreq_num_t; +#endif + +#endif // _DREQ_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/glitch_detector.h b/lib/pico-sdk/rp2350/hardware/regs/glitch_detector.h new file mode 100644 index 000000000000..efdf434b3f02 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/glitch_detector.h @@ -0,0 +1,213 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : GLITCH_DETECTOR +// Version : 1 +// Bus type : apb +// Description : Glitch detector controls +// ============================================================================= +#ifndef _HARDWARE_REGS_GLITCH_DETECTOR_H +#define _HARDWARE_REGS_GLITCH_DETECTOR_H +// ============================================================================= +// Register : GLITCH_DETECTOR_ARM +// Description : Forcibly arm the glitch detectors, if they are not already +// armed by OTP. When armed, any individual detector trigger will +// cause a restart of the switched core power domain's power-on +// reset state machine. +// +// Glitch detector triggers are recorded accumulatively in +// TRIG_STATUS. If the system is reset by a glitch detector +// trigger, this is recorded in POWMAN_CHIP_RESET. +// +// This register is Secure read/write only. +// 0x5bad -> Do not force the glitch detectors to be armed +// 0x0000 -> Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES) +#define GLITCH_DETECTOR_ARM_OFFSET _u(0x00000000) +#define GLITCH_DETECTOR_ARM_BITS _u(0x0000ffff) +#define GLITCH_DETECTOR_ARM_RESET _u(0x00005bad) +#define GLITCH_DETECTOR_ARM_MSB _u(15) +#define GLITCH_DETECTOR_ARM_LSB _u(0) +#define GLITCH_DETECTOR_ARM_ACCESS "RW" +#define GLITCH_DETECTOR_ARM_VALUE_NO _u(0x5bad) +#define GLITCH_DETECTOR_ARM_VALUE_YES _u(0x0000) +// ============================================================================= +// Register : GLITCH_DETECTOR_DISARM +// Description : None +// Forcibly disarm the glitch detectors, if they are armed by OTP. +// Ignored if ARM is YES. +// +// This register is Secure read/write only. +// 0x0000 -> Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO) +// 0xdcaf -> Disarm the glitch detectors +#define GLITCH_DETECTOR_DISARM_OFFSET _u(0x00000004) +#define GLITCH_DETECTOR_DISARM_BITS _u(0x0000ffff) +#define GLITCH_DETECTOR_DISARM_RESET _u(0x00000000) +#define GLITCH_DETECTOR_DISARM_MSB _u(15) +#define GLITCH_DETECTOR_DISARM_LSB _u(0) +#define GLITCH_DETECTOR_DISARM_ACCESS "RW" +#define GLITCH_DETECTOR_DISARM_VALUE_NO _u(0x0000) +#define GLITCH_DETECTOR_DISARM_VALUE_YES _u(0xdcaf) +// ============================================================================= +// Register : GLITCH_DETECTOR_SENSITIVITY +// Description : Adjust the sensitivity of glitch detectors to values other than +// their OTP-provided defaults. +// +// This register is Secure read/write only. +#define GLITCH_DETECTOR_SENSITIVITY_OFFSET _u(0x00000008) +#define GLITCH_DETECTOR_SENSITIVITY_BITS _u(0xff00ffff) +#define GLITCH_DETECTOR_SENSITIVITY_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DEFAULT +// 0x00 -> Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES) +// 0xde -> Do not use the default sensitivity configured in OTP. Instead use the value from this register. +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_RESET _u(0x00) +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_BITS _u(0xff000000) +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_MSB _u(31) +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_LSB _u(24) +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_ACCESS "RW" +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_YES _u(0x00) +#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_NO _u(0xde) +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET3_INV +// Description : Must be the inverse of DET3, else the default value is used. +#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_BITS _u(0x0000c000) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_MSB _u(15) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_LSB _u(14) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET2_INV +// Description : Must be the inverse of DET2, else the default value is used. +#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_BITS _u(0x00003000) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_MSB _u(13) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_LSB _u(12) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET1_INV +// Description : Must be the inverse of DET1, else the default value is used. +#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_BITS _u(0x00000c00) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_MSB _u(11) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_LSB _u(10) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET0_INV +// Description : Must be the inverse of DET0, else the default value is used. +#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_BITS _u(0x00000300) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_MSB _u(9) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_LSB _u(8) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET3 +// Description : Set sensitivity for detector 3. Higher values are more +// sensitive. +#define GLITCH_DETECTOR_SENSITIVITY_DET3_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_BITS _u(0x000000c0) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_MSB _u(7) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_LSB _u(6) +#define GLITCH_DETECTOR_SENSITIVITY_DET3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET2 +// Description : Set sensitivity for detector 2. Higher values are more +// sensitive. +#define GLITCH_DETECTOR_SENSITIVITY_DET2_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_BITS _u(0x00000030) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_MSB _u(5) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_LSB _u(4) +#define GLITCH_DETECTOR_SENSITIVITY_DET2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET1 +// Description : Set sensitivity for detector 1. Higher values are more +// sensitive. +#define GLITCH_DETECTOR_SENSITIVITY_DET1_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_BITS _u(0x0000000c) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_MSB _u(3) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_LSB _u(2) +#define GLITCH_DETECTOR_SENSITIVITY_DET1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_SENSITIVITY_DET0 +// Description : Set sensitivity for detector 0. Higher values are more +// sensitive. +#define GLITCH_DETECTOR_SENSITIVITY_DET0_RESET _u(0x0) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_BITS _u(0x00000003) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_MSB _u(1) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_LSB _u(0) +#define GLITCH_DETECTOR_SENSITIVITY_DET0_ACCESS "RW" +// ============================================================================= +// Register : GLITCH_DETECTOR_LOCK +// Description : None +// Write any nonzero value to disable writes to ARM, DISARM, +// SENSITIVITY and LOCK. This register is Secure read/write only. +#define GLITCH_DETECTOR_LOCK_OFFSET _u(0x0000000c) +#define GLITCH_DETECTOR_LOCK_BITS _u(0x000000ff) +#define GLITCH_DETECTOR_LOCK_RESET _u(0x00000000) +#define GLITCH_DETECTOR_LOCK_MSB _u(7) +#define GLITCH_DETECTOR_LOCK_LSB _u(0) +#define GLITCH_DETECTOR_LOCK_ACCESS "RW" +// ============================================================================= +// Register : GLITCH_DETECTOR_TRIG_STATUS +// Description : Set when a detector output triggers. Write-1-clear. +// +// (May immediately return high if the detector remains in a +// failed state. Detectors can only be cleared by a full reset of +// the switched core power domain.) +// +// This register is Secure read/write only. +#define GLITCH_DETECTOR_TRIG_STATUS_OFFSET _u(0x00000010) +#define GLITCH_DETECTOR_TRIG_STATUS_BITS _u(0x0000000f) +#define GLITCH_DETECTOR_TRIG_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_TRIG_STATUS_DET3 +#define GLITCH_DETECTOR_TRIG_STATUS_DET3_RESET _u(0x0) +#define GLITCH_DETECTOR_TRIG_STATUS_DET3_BITS _u(0x00000008) +#define GLITCH_DETECTOR_TRIG_STATUS_DET3_MSB _u(3) +#define GLITCH_DETECTOR_TRIG_STATUS_DET3_LSB _u(3) +#define GLITCH_DETECTOR_TRIG_STATUS_DET3_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_TRIG_STATUS_DET2 +#define GLITCH_DETECTOR_TRIG_STATUS_DET2_RESET _u(0x0) +#define GLITCH_DETECTOR_TRIG_STATUS_DET2_BITS _u(0x00000004) +#define GLITCH_DETECTOR_TRIG_STATUS_DET2_MSB _u(2) +#define GLITCH_DETECTOR_TRIG_STATUS_DET2_LSB _u(2) +#define GLITCH_DETECTOR_TRIG_STATUS_DET2_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_TRIG_STATUS_DET1 +#define GLITCH_DETECTOR_TRIG_STATUS_DET1_RESET _u(0x0) +#define GLITCH_DETECTOR_TRIG_STATUS_DET1_BITS _u(0x00000002) +#define GLITCH_DETECTOR_TRIG_STATUS_DET1_MSB _u(1) +#define GLITCH_DETECTOR_TRIG_STATUS_DET1_LSB _u(1) +#define GLITCH_DETECTOR_TRIG_STATUS_DET1_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : GLITCH_DETECTOR_TRIG_STATUS_DET0 +#define GLITCH_DETECTOR_TRIG_STATUS_DET0_RESET _u(0x0) +#define GLITCH_DETECTOR_TRIG_STATUS_DET0_BITS _u(0x00000001) +#define GLITCH_DETECTOR_TRIG_STATUS_DET0_MSB _u(0) +#define GLITCH_DETECTOR_TRIG_STATUS_DET0_LSB _u(0) +#define GLITCH_DETECTOR_TRIG_STATUS_DET0_ACCESS "WC" +// ============================================================================= +// Register : GLITCH_DETECTOR_TRIG_FORCE +// Description : Simulate the firing of one or more detectors. Writing ones to +// this register will set the matching bits in STATUS_TRIG. +// +// If the glitch detectors are currently armed, writing ones will +// also immediately reset the switched core power domain, and set +// the reset reason latches in POWMAN_CHIP_RESET to indicate a +// glitch detector resets. +// +// This register is Secure read/write only. +#define GLITCH_DETECTOR_TRIG_FORCE_OFFSET _u(0x00000014) +#define GLITCH_DETECTOR_TRIG_FORCE_BITS _u(0x0000000f) +#define GLITCH_DETECTOR_TRIG_FORCE_RESET _u(0x00000000) +#define GLITCH_DETECTOR_TRIG_FORCE_MSB _u(3) +#define GLITCH_DETECTOR_TRIG_FORCE_LSB _u(0) +#define GLITCH_DETECTOR_TRIG_FORCE_ACCESS "SC" +// ============================================================================= +#endif // _HARDWARE_REGS_GLITCH_DETECTOR_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/hstx_ctrl.h b/lib/pico-sdk/rp2350/hardware/regs/hstx_ctrl.h new file mode 100644 index 000000000000..8f213044510c --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/hstx_ctrl.h @@ -0,0 +1,609 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : HSTX_CTRL +// Version : 0 +// Bus type : apb +// Description : Control interface to HSTX. For FIFO write access and status, +// see the HSTX_FIFO register block. +// ============================================================================= +#ifndef _HARDWARE_REGS_HSTX_CTRL_H +#define _HARDWARE_REGS_HSTX_CTRL_H +// ============================================================================= +// Register : HSTX_CTRL_CSR +#define HSTX_CTRL_CSR_OFFSET _u(0x00000000) +#define HSTX_CTRL_CSR_BITS _u(0xff1f1f73) +#define HSTX_CTRL_CSR_RESET _u(0x10050600) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_CLKDIV +// Description : Clock period of the generated clock, measured in HSTX clock +// cycles. Can be odd or even. The generated clock advances only +// on cycles where the shift register shifts. +// +// For example, a clkdiv of 5 would generate a complete output +// clock period for every 5 HSTX clocks (or every 10 half-clocks). +// +// A CLKDIV value of 0 is mapped to a period of 16 HSTX clock +// cycles. +#define HSTX_CTRL_CSR_CLKDIV_RESET _u(0x1) +#define HSTX_CTRL_CSR_CLKDIV_BITS _u(0xf0000000) +#define HSTX_CTRL_CSR_CLKDIV_MSB _u(31) +#define HSTX_CTRL_CSR_CLKDIV_LSB _u(28) +#define HSTX_CTRL_CSR_CLKDIV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_CLKPHASE +// Description : Set the initial phase of the generated clock. +// +// A CLKPHASE of 0 means the clock is initially low, and the first +// rising edge occurs after one half period of the generated clock +// (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 +// will advance the initial clock phase by one half clk_hstx +// period. For example, if CLKDIV=2 and CLKPHASE=1: +// +// * The clock will be initially low +// +// * The first rising edge will be 0.5 clk_hstx cycles after +// asserting first data +// +// * The first falling edge will be 1.5 clk_hstx cycles after +// asserting first data +// +// This configuration would be suitable for serialising at a bit +// rate of clk_hstx with a centre-aligned DDR clock. +// +// When the HSTX is halted by clearing CSR_EN, the clock generator +// will return to its initial phase as configured by the CLKPHASE +// field. +// +// Note CLKPHASE must be strictly less than double the value of +// CLKDIV (one full period), else its operation is undefined. +#define HSTX_CTRL_CSR_CLKPHASE_RESET _u(0x0) +#define HSTX_CTRL_CSR_CLKPHASE_BITS _u(0x0f000000) +#define HSTX_CTRL_CSR_CLKPHASE_MSB _u(27) +#define HSTX_CTRL_CSR_CLKPHASE_LSB _u(24) +#define HSTX_CTRL_CSR_CLKPHASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_N_SHIFTS +// Description : Number of times to shift the shift register before refilling it +// from the FIFO. (A count of how many times it has been shifted, +// *not* the total shift distance.) +// +// A register value of 0 means shift 32 times. +#define HSTX_CTRL_CSR_N_SHIFTS_RESET _u(0x05) +#define HSTX_CTRL_CSR_N_SHIFTS_BITS _u(0x001f0000) +#define HSTX_CTRL_CSR_N_SHIFTS_MSB _u(20) +#define HSTX_CTRL_CSR_N_SHIFTS_LSB _u(16) +#define HSTX_CTRL_CSR_N_SHIFTS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_SHIFT +// Description : How many bits to right-rotate the shift register by each cycle. +// +// The use of a rotate rather than a shift allows left shifts to +// be emulated, by subtracting the left-shift amount from 32. It +// also allows data to be repeated, when the product of SHIFT and +// N_SHIFTS is greater than 32. +#define HSTX_CTRL_CSR_SHIFT_RESET _u(0x06) +#define HSTX_CTRL_CSR_SHIFT_BITS _u(0x00001f00) +#define HSTX_CTRL_CSR_SHIFT_MSB _u(12) +#define HSTX_CTRL_CSR_SHIFT_LSB _u(8) +#define HSTX_CTRL_CSR_SHIFT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_COUPLED_SEL +// Description : Select which PIO to use for coupled mode operation. +#define HSTX_CTRL_CSR_COUPLED_SEL_RESET _u(0x0) +#define HSTX_CTRL_CSR_COUPLED_SEL_BITS _u(0x00000060) +#define HSTX_CTRL_CSR_COUPLED_SEL_MSB _u(6) +#define HSTX_CTRL_CSR_COUPLED_SEL_LSB _u(5) +#define HSTX_CTRL_CSR_COUPLED_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_COUPLED_MODE +// Description : Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked +// *directly* from the system clock (not just from some other +// clock source of the same frequency) for this synchronous +// interface to function correctly. +// +// When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 +// through 31 will select bits from the 8-bit PIO-to-HSTX path, +// rather than shifter bits. Indices of 0 through 23 will still +// index the shift register as normal. +// +// The PIO outputs connected to the PIO-to-HSTX bus are those same +// outputs that would appear on the HSTX-capable pins if those +// pins' FUNCSELs were set to PIO instead of HSTX. +// +// For example, if HSTX is on GPIOs 12 through 19, then PIO +// outputs 12 through 19 are connected to the HSTX when coupled +// mode is engaged. +#define HSTX_CTRL_CSR_COUPLED_MODE_RESET _u(0x0) +#define HSTX_CTRL_CSR_COUPLED_MODE_BITS _u(0x00000010) +#define HSTX_CTRL_CSR_COUPLED_MODE_MSB _u(4) +#define HSTX_CTRL_CSR_COUPLED_MODE_LSB _u(4) +#define HSTX_CTRL_CSR_COUPLED_MODE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_EXPAND_EN +// Description : Enable the command expander. When 0, raw FIFO data is passed +// directly to the output shift register. When 1, the command +// expander can perform simple operations such as run length +// decoding on data between the FIFO and the shift register. +// +// Do not change CXPD_EN whilst EN is set. It's safe to set +// CXPD_EN simultaneously with setting EN. +#define HSTX_CTRL_CSR_EXPAND_EN_RESET _u(0x0) +#define HSTX_CTRL_CSR_EXPAND_EN_BITS _u(0x00000002) +#define HSTX_CTRL_CSR_EXPAND_EN_MSB _u(1) +#define HSTX_CTRL_CSR_EXPAND_EN_LSB _u(1) +#define HSTX_CTRL_CSR_EXPAND_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_CSR_EN +// Description : When EN is 1, the HSTX will shift out data as it appears in the +// FIFO. As long as there is data, the HSTX shift register will +// shift once per clock cycle, and the frequency of popping from +// the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. +// +// When EN is 0, the FIFO is not popped. The shift counter and +// clock generator are also reset to their initial state for as +// long as EN is low. Note the initial phase of the clock +// generator can be configured by the CLKPHASE field. +// +// Once the HSTX is enabled again, and data is pushed to the FIFO, +// the generated clock's first rising edge will be one half-period +// after the first data is launched. +#define HSTX_CTRL_CSR_EN_RESET _u(0x0) +#define HSTX_CTRL_CSR_EN_BITS _u(0x00000001) +#define HSTX_CTRL_CSR_EN_MSB _u(0) +#define HSTX_CTRL_CSR_EN_LSB _u(0) +#define HSTX_CTRL_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT0 +// Description : Data control register for output bit 0 +#define HSTX_CTRL_BIT0_OFFSET _u(0x00000004) +#define HSTX_CTRL_BIT0_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT0_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT0_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT0_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT0_CLK_MSB _u(17) +#define HSTX_CTRL_BIT0_CLK_LSB _u(17) +#define HSTX_CTRL_BIT0_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT0_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT0_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT0_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT0_INV_MSB _u(16) +#define HSTX_CTRL_BIT0_INV_LSB _u(16) +#define HSTX_CTRL_BIT0_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT0_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT0_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT0_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT0_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT0_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT0_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT0_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT0_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT0_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT0_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT0_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT0_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT1 +// Description : Data control register for output bit 1 +#define HSTX_CTRL_BIT1_OFFSET _u(0x00000008) +#define HSTX_CTRL_BIT1_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT1_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT1_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT1_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT1_CLK_MSB _u(17) +#define HSTX_CTRL_BIT1_CLK_LSB _u(17) +#define HSTX_CTRL_BIT1_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT1_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT1_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT1_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT1_INV_MSB _u(16) +#define HSTX_CTRL_BIT1_INV_LSB _u(16) +#define HSTX_CTRL_BIT1_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT1_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT1_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT1_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT1_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT1_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT1_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT1_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT1_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT1_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT1_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT1_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT1_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT2 +// Description : Data control register for output bit 2 +#define HSTX_CTRL_BIT2_OFFSET _u(0x0000000c) +#define HSTX_CTRL_BIT2_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT2_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT2_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT2_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT2_CLK_MSB _u(17) +#define HSTX_CTRL_BIT2_CLK_LSB _u(17) +#define HSTX_CTRL_BIT2_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT2_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT2_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT2_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT2_INV_MSB _u(16) +#define HSTX_CTRL_BIT2_INV_LSB _u(16) +#define HSTX_CTRL_BIT2_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT2_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT2_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT2_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT2_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT2_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT2_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT2_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT2_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT2_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT2_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT2_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT2_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT3 +// Description : Data control register for output bit 3 +#define HSTX_CTRL_BIT3_OFFSET _u(0x00000010) +#define HSTX_CTRL_BIT3_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT3_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT3_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT3_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT3_CLK_MSB _u(17) +#define HSTX_CTRL_BIT3_CLK_LSB _u(17) +#define HSTX_CTRL_BIT3_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT3_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT3_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT3_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT3_INV_MSB _u(16) +#define HSTX_CTRL_BIT3_INV_LSB _u(16) +#define HSTX_CTRL_BIT3_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT3_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT3_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT3_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT3_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT3_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT3_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT3_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT3_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT3_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT3_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT3_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT3_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT4 +// Description : Data control register for output bit 4 +#define HSTX_CTRL_BIT4_OFFSET _u(0x00000014) +#define HSTX_CTRL_BIT4_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT4_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT4_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT4_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT4_CLK_MSB _u(17) +#define HSTX_CTRL_BIT4_CLK_LSB _u(17) +#define HSTX_CTRL_BIT4_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT4_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT4_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT4_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT4_INV_MSB _u(16) +#define HSTX_CTRL_BIT4_INV_LSB _u(16) +#define HSTX_CTRL_BIT4_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT4_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT4_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT4_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT4_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT4_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT4_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT4_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT4_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT4_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT4_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT4_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT4_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT5 +// Description : Data control register for output bit 5 +#define HSTX_CTRL_BIT5_OFFSET _u(0x00000018) +#define HSTX_CTRL_BIT5_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT5_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT5_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT5_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT5_CLK_MSB _u(17) +#define HSTX_CTRL_BIT5_CLK_LSB _u(17) +#define HSTX_CTRL_BIT5_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT5_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT5_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT5_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT5_INV_MSB _u(16) +#define HSTX_CTRL_BIT5_INV_LSB _u(16) +#define HSTX_CTRL_BIT5_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT5_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT5_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT5_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT5_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT5_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT5_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT5_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT5_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT5_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT5_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT5_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT5_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT6 +// Description : Data control register for output bit 6 +#define HSTX_CTRL_BIT6_OFFSET _u(0x0000001c) +#define HSTX_CTRL_BIT6_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT6_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT6_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT6_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT6_CLK_MSB _u(17) +#define HSTX_CTRL_BIT6_CLK_LSB _u(17) +#define HSTX_CTRL_BIT6_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT6_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT6_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT6_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT6_INV_MSB _u(16) +#define HSTX_CTRL_BIT6_INV_LSB _u(16) +#define HSTX_CTRL_BIT6_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT6_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT6_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT6_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT6_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT6_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT6_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT6_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT6_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT6_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT6_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT6_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT6_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_BIT7 +// Description : Data control register for output bit 7 +#define HSTX_CTRL_BIT7_OFFSET _u(0x00000020) +#define HSTX_CTRL_BIT7_BITS _u(0x00031f1f) +#define HSTX_CTRL_BIT7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT7_CLK +// Description : Connect this output to the generated clock, rather than the +// data shift register. SEL_P and SEL_N are ignored if this bit is +// set, but INV can still be set to generate an antiphase clock. +#define HSTX_CTRL_BIT7_CLK_RESET _u(0x0) +#define HSTX_CTRL_BIT7_CLK_BITS _u(0x00020000) +#define HSTX_CTRL_BIT7_CLK_MSB _u(17) +#define HSTX_CTRL_BIT7_CLK_LSB _u(17) +#define HSTX_CTRL_BIT7_CLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT7_INV +// Description : Invert this data output (logical NOT) +#define HSTX_CTRL_BIT7_INV_RESET _u(0x0) +#define HSTX_CTRL_BIT7_INV_BITS _u(0x00010000) +#define HSTX_CTRL_BIT7_INV_MSB _u(16) +#define HSTX_CTRL_BIT7_INV_LSB _u(16) +#define HSTX_CTRL_BIT7_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT7_SEL_N +// Description : Shift register data bit select for the second half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT7_SEL_N_RESET _u(0x00) +#define HSTX_CTRL_BIT7_SEL_N_BITS _u(0x00001f00) +#define HSTX_CTRL_BIT7_SEL_N_MSB _u(12) +#define HSTX_CTRL_BIT7_SEL_N_LSB _u(8) +#define HSTX_CTRL_BIT7_SEL_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_BIT7_SEL_P +// Description : Shift register data bit select for the first half of the HSTX +// clock cycle +#define HSTX_CTRL_BIT7_SEL_P_RESET _u(0x00) +#define HSTX_CTRL_BIT7_SEL_P_BITS _u(0x0000001f) +#define HSTX_CTRL_BIT7_SEL_P_MSB _u(4) +#define HSTX_CTRL_BIT7_SEL_P_LSB _u(0) +#define HSTX_CTRL_BIT7_SEL_P_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_EXPAND_SHIFT +// Description : Configure the optional shifter inside the command expander +#define HSTX_CTRL_EXPAND_SHIFT_OFFSET _u(0x00000024) +#define HSTX_CTRL_EXPAND_SHIFT_BITS _u(0x1f1f1f1f) +#define HSTX_CTRL_EXPAND_SHIFT_RESET _u(0x01000100) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS +// Description : Number of times to consume from the shift register before +// refilling it from the FIFO, when the current command is an +// encoded data command (e.g. TMDS). A register value of 0 means +// shift 32 times. +#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_RESET _u(0x01) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_BITS _u(0x1f000000) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_MSB _u(28) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_LSB _u(24) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT +// Description : How many bits to right-rotate the shift register by each time +// data is pushed to the output shifter, when the current command +// is an encoded data command (e.g. TMDS). +#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_RESET _u(0x00) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_BITS _u(0x001f0000) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_MSB _u(20) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_LSB _u(16) +#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS +// Description : Number of times to consume from the shift register before +// refilling it from the FIFO, when the current command is a raw +// data command. A register value of 0 means shift 32 times. +#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_RESET _u(0x01) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_BITS _u(0x00001f00) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_MSB _u(12) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_LSB _u(8) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT +// Description : How many bits to right-rotate the shift register by each time +// data is pushed to the output shifter, when the current command +// is a raw data command. +#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_RESET _u(0x00) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_BITS _u(0x0000001f) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_MSB _u(4) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_LSB _u(0) +#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : HSTX_CTRL_EXPAND_TMDS +// Description : Configure the optional TMDS encoder inside the command expander +#define HSTX_CTRL_EXPAND_TMDS_OFFSET _u(0x00000028) +#define HSTX_CTRL_EXPAND_TMDS_BITS _u(0x00ffffff) +#define HSTX_CTRL_EXPAND_TMDS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_TMDS_L2_NBITS +// Description : Number of valid data bits for the lane 2 TMDS encoder, starting +// from bit 7 of the rotated data. Field values of 0 -> 7 encode +// counts of 1 -> 8 bits. +#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_RESET _u(0x0) +#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_BITS _u(0x00e00000) +#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_MSB _u(23) +#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_LSB _u(21) +#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_TMDS_L2_ROT +// Description : Right-rotate applied to the current shifter data before the +// lane 2 TMDS encoder. +#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_RESET _u(0x00) +#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_BITS _u(0x001f0000) +#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_MSB _u(20) +#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_LSB _u(16) +#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_TMDS_L1_NBITS +// Description : Number of valid data bits for the lane 1 TMDS encoder, starting +// from bit 7 of the rotated data. Field values of 0 -> 7 encode +// counts of 1 -> 8 bits. +#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_RESET _u(0x0) +#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_BITS _u(0x0000e000) +#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_MSB _u(15) +#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_LSB _u(13) +#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_TMDS_L1_ROT +// Description : Right-rotate applied to the current shifter data before the +// lane 1 TMDS encoder. +#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_RESET _u(0x00) +#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_BITS _u(0x00001f00) +#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_MSB _u(12) +#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_LSB _u(8) +#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_TMDS_L0_NBITS +// Description : Number of valid data bits for the lane 0 TMDS encoder, starting +// from bit 7 of the rotated data. Field values of 0 -> 7 encode +// counts of 1 -> 8 bits. +#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_RESET _u(0x0) +#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_BITS _u(0x000000e0) +#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_MSB _u(7) +#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_LSB _u(5) +#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : HSTX_CTRL_EXPAND_TMDS_L0_ROT +// Description : Right-rotate applied to the current shifter data before the +// lane 0 TMDS encoder. +#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_RESET _u(0x00) +#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_BITS _u(0x0000001f) +#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_MSB _u(4) +#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_LSB _u(0) +#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_HSTX_CTRL_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/hstx_fifo.h b/lib/pico-sdk/rp2350/hardware/regs/hstx_fifo.h new file mode 100644 index 000000000000..d056447c8baf --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/hstx_fifo.h @@ -0,0 +1,62 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : HSTX_FIFO +// Version : 1 +// Bus type : ahbl +// Description : FIFO status and write access for HSTX +// ============================================================================= +#ifndef _HARDWARE_REGS_HSTX_FIFO_H +#define _HARDWARE_REGS_HSTX_FIFO_H +// ============================================================================= +// Register : HSTX_FIFO_STAT +// Description : FIFO status +#define HSTX_FIFO_STAT_OFFSET _u(0x00000000) +#define HSTX_FIFO_STAT_BITS _u(0x000007ff) +#define HSTX_FIFO_STAT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : HSTX_FIFO_STAT_WOF +// Description : FIFO was written when full. Write 1 to clear. +#define HSTX_FIFO_STAT_WOF_RESET _u(0x0) +#define HSTX_FIFO_STAT_WOF_BITS _u(0x00000400) +#define HSTX_FIFO_STAT_WOF_MSB _u(10) +#define HSTX_FIFO_STAT_WOF_LSB _u(10) +#define HSTX_FIFO_STAT_WOF_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : HSTX_FIFO_STAT_EMPTY +#define HSTX_FIFO_STAT_EMPTY_RESET "-" +#define HSTX_FIFO_STAT_EMPTY_BITS _u(0x00000200) +#define HSTX_FIFO_STAT_EMPTY_MSB _u(9) +#define HSTX_FIFO_STAT_EMPTY_LSB _u(9) +#define HSTX_FIFO_STAT_EMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : HSTX_FIFO_STAT_FULL +#define HSTX_FIFO_STAT_FULL_RESET "-" +#define HSTX_FIFO_STAT_FULL_BITS _u(0x00000100) +#define HSTX_FIFO_STAT_FULL_MSB _u(8) +#define HSTX_FIFO_STAT_FULL_LSB _u(8) +#define HSTX_FIFO_STAT_FULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : HSTX_FIFO_STAT_LEVEL +#define HSTX_FIFO_STAT_LEVEL_RESET _u(0x00) +#define HSTX_FIFO_STAT_LEVEL_BITS _u(0x000000ff) +#define HSTX_FIFO_STAT_LEVEL_MSB _u(7) +#define HSTX_FIFO_STAT_LEVEL_LSB _u(0) +#define HSTX_FIFO_STAT_LEVEL_ACCESS "RO" +// ============================================================================= +// Register : HSTX_FIFO_FIFO +// Description : Write access to FIFO +#define HSTX_FIFO_FIFO_OFFSET _u(0x00000004) +#define HSTX_FIFO_FIFO_BITS _u(0xffffffff) +#define HSTX_FIFO_FIFO_RESET _u(0x00000000) +#define HSTX_FIFO_FIFO_MSB _u(31) +#define HSTX_FIFO_FIFO_LSB _u(0) +#define HSTX_FIFO_FIFO_ACCESS "WF" +// ============================================================================= +#endif // _HARDWARE_REGS_HSTX_FIFO_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/i2c.h b/lib/pico-sdk/rp2350/hardware/regs/i2c.h new file mode 100644 index 000000000000..f44ceb440272 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/i2c.h @@ -0,0 +1,2700 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : I2C +// Version : 1 +// Bus type : apb +// Description : DW_apb_i2c address block +// +// List of configuration constants for the Synopsys I2C +// hardware (you may see references to these in I2C register +// header; these are *fixed* values, set at hardware design +// time): +// +// IC_ULTRA_FAST_MODE ................ 0x0 +// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 +// IC_UFM_SCL_LOW_COUNT .............. 0x0008 +// IC_UFM_SCL_HIGH_COUNT ............. 0x0006 +// IC_TX_TL .......................... 0x0 +// IC_TX_CMD_BLOCK ................... 0x1 +// IC_HAS_DMA ........................ 0x1 +// IC_HAS_ASYNC_FIFO ................. 0x0 +// IC_SMBUS_ARP ...................... 0x0 +// IC_FIRST_DATA_BYTE_STATUS ......... 0x1 +// IC_INTR_IO ........................ 0x1 +// IC_MASTER_MODE .................... 0x1 +// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 +// IC_INTR_POL ....................... 0x1 +// IC_OPTIONAL_SAR ................... 0x0 +// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 +// IC_DEFAULT_SLAVE_ADDR ............. 0x055 +// IC_DEFAULT_HS_SPKLEN .............. 0x1 +// IC_FS_SCL_HIGH_COUNT .............. 0x0006 +// IC_HS_SCL_LOW_COUNT ............... 0x0008 +// IC_DEVICE_ID_VALUE ................ 0x0 +// IC_10BITADDR_MASTER ............... 0x0 +// IC_CLK_FREQ_OPTIMIZATION .......... 0x0 +// IC_DEFAULT_FS_SPKLEN .............. 0x7 +// IC_ADD_ENCODED_PARAMS ............. 0x0 +// IC_DEFAULT_SDA_HOLD ............... 0x000001 +// IC_DEFAULT_SDA_SETUP .............. 0x64 +// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 +// IC_CLOCK_PERIOD ................... 100 +// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 +// IC_RESTART_EN ..................... 0x1 +// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 +// IC_BUS_CLEAR_FEATURE .............. 0x0 +// IC_CAP_LOADING .................... 100 +// IC_FS_SCL_LOW_COUNT ............... 0x000d +// APB_DATA_WIDTH .................... 32 +// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_SLV_DATA_NACK_ONLY ............. 0x1 +// IC_10BITADDR_SLAVE ................ 0x0 +// IC_CLK_TYPE ....................... 0x0 +// IC_SMBUS_UDID_MSB ................. 0x0 +// IC_SMBUS_SUSPEND_ALERT ............ 0x0 +// IC_HS_SCL_HIGH_COUNT .............. 0x0006 +// IC_SLV_RESTART_DET_EN ............. 0x1 +// IC_SMBUS .......................... 0x0 +// IC_OPTIONAL_SAR_DEFAULT ........... 0x0 +// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 +// IC_USE_COUNTS ..................... 0x0 +// IC_RX_BUFFER_DEPTH ................ 16 +// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff +// IC_RX_FULL_HLD_BUS_EN ............. 0x1 +// IC_SLAVE_DISABLE .................. 0x1 +// IC_RX_TL .......................... 0x0 +// IC_DEVICE_ID ...................... 0x0 +// IC_HC_COUNT_VALUES ................ 0x0 +// I2C_DYNAMIC_TAR_UPDATE ............ 0 +// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff +// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff +// IC_HS_MASTER_CODE ................. 0x1 +// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff +// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff +// IC_SS_SCL_HIGH_COUNT .............. 0x0028 +// IC_SS_SCL_LOW_COUNT ............... 0x002f +// IC_MAX_SPEED_MODE ................. 0x2 +// IC_STAT_FOR_CLK_STRETCH ........... 0x0 +// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 +// IC_DEFAULT_UFM_SPKLEN ............. 0x1 +// IC_TX_BUFFER_DEPTH ................ 16 +// ============================================================================= +#ifndef _HARDWARE_REGS_I2C_H +#define _HARDWARE_REGS_I2C_H +// ============================================================================= +// Register : I2C_IC_CON +// Description : I2C Control Register. This register can be written only when +// the DW_apb_i2c is disabled, which corresponds to the +// IC_ENABLE[0] register being set to 0. Writes at other times +// have no effect. +// +// Read/Write Access: - bit 10 is read only. - bit 11 is read only +// - bit 16 is read only - bit 17 is read only - bits 18 and 19 +// are read only. +#define I2C_IC_CON_OFFSET _u(0x00000000) +#define I2C_IC_CON_BITS _u(0x000007ff) +#define I2C_IC_CON_RESET _u(0x00000065) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE +// Description : Master issues the STOP_DET interrupt irrespective of whether +// master is active or not +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET _u(0x0) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS _u(0x00000400) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB _u(10) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB _u(10) +#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL +// Description : This bit controls whether DW_apb_i2c should hold the bus when +// the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as +// described in the IC_RX_FULL_HLD_BUS_EN parameter. +// +// Reset value: 0x0. +// 0x0 -> Overflow when RX_FIFO is full +// 0x1 -> Hold bus when RX_FIFO is full +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET _u(0x0) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS _u(0x00000200) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB _u(9) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB _u(9) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS "RW" +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_TX_EMPTY_CTRL +// Description : This bit controls the generation of the TX_EMPTY interrupt, as +// described in the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0. +// 0x0 -> Default behaviour of TX_EMPTY interrupt +// 0x1 -> Controlled generation of TX_EMPTY interrupt +#define I2C_IC_CON_TX_EMPTY_CTRL_RESET _u(0x0) +#define I2C_IC_CON_TX_EMPTY_CTRL_BITS _u(0x00000100) +#define I2C_IC_CON_TX_EMPTY_CTRL_MSB _u(8) +#define I2C_IC_CON_TX_EMPTY_CTRL_LSB _u(8) +#define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS "RW" +#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_STOP_DET_IFADDRESSED +// Description : In slave mode: - 1'b1: issues the STOP_DET interrupt only when +// it is addressed. - 1'b0: issues the STOP_DET irrespective of +// whether it's addressed or not. Reset value: 0x0 +// +// NOTE: During a general call address, this slave does not issue +// the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if +// the slave responds to the general call address by generating +// ACK. The STOP_DET interrupt is generated only when the +// transmitted address matches the slave address (SAR). +// 0x0 -> slave issues STOP_DET intr always +// 0x1 -> slave issues STOP_DET intr only if addressed +#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET _u(0x0) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS _u(0x00000080) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB _u(7) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB _u(7) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS "RW" +#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_SLAVE_DISABLE +// Description : This bit controls whether I2C has its slave disabled, which +// means once the presetn signal is applied, then this bit is set +// and the slave is disabled. +// +// If this bit is set (slave is disabled), DW_apb_i2c functions +// only as a master and does not perform any action that requires +// a slave. +// +// NOTE: Software should ensure that if this bit is written with +// 0, then bit 0 should also be written with a 0. +// 0x0 -> Slave mode is enabled +// 0x1 -> Slave mode is disabled +#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET _u(0x1) +#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS _u(0x00000040) +#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB _u(6) +#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB _u(6) +#define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS "RW" +#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED _u(0x0) +#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_RESTART_EN +// Description : Determines whether RESTART conditions may be sent when acting +// as a master. Some older slaves do not support handling RESTART +// conditions; however, RESTART conditions are used in several +// DW_apb_i2c operations. When RESTART is disabled, the master is +// prohibited from performing the following functions: - Sending a +// START BYTE - Performing any high-speed mode operation - High- +// speed mode operation - Performing direction changes in combined +// format mode - Performing a read operation with a 10-bit address +// By replacing RESTART condition followed by a STOP and a +// subsequent START condition, split operations are broken down +// into multiple DW_apb_i2c transfers. If the above operations are +// performed, it will result in setting bit 6 (TX_ABRT) of the +// IC_RAW_INTR_STAT register. +// +// Reset value: ENABLED +// 0x0 -> Master restart disabled +// 0x1 -> Master restart enabled +#define I2C_IC_CON_IC_RESTART_EN_RESET _u(0x1) +#define I2C_IC_CON_IC_RESTART_EN_BITS _u(0x00000020) +#define I2C_IC_CON_IC_RESTART_EN_MSB _u(5) +#define I2C_IC_CON_IC_RESTART_EN_LSB _u(5) +#define I2C_IC_CON_IC_RESTART_EN_ACCESS "RW" +#define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_10BITADDR_MASTER +// Description : Controls whether the DW_apb_i2c starts its transfers in 7- or +// 10-bit addressing mode when acting as a master. - 0: 7-bit +// addressing - 1: 10-bit addressing +// 0x0 -> Master 7Bit addressing mode +// 0x1 -> Master 10Bit addressing mode +#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS _u(0x00000010) +#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB _u(4) +#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB _u(4) +#define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS "RW" +#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_IC_10BITADDR_SLAVE +// Description : When acting as a slave, this bit controls whether the +// DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit +// addressing. The DW_apb_i2c ignores transactions that involve +// 10-bit addressing; for 7-bit addressing, only the lower 7 bits +// of the IC_SAR register are compared. - 1: 10-bit addressing. +// The DW_apb_i2c responds to only 10-bit addressing transfers +// that match the full 10 bits of the IC_SAR register. +// 0x0 -> Slave 7Bit addressing +// 0x1 -> Slave 10Bit addressing +#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS _u(0x00000008) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB _u(3) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB _u(3) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS "RW" +#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS _u(0x0) +#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_SPEED +// Description : These bits control at which speed the DW_apb_i2c operates; its +// setting is relevant only if one is operating the DW_apb_i2c in +// master mode. Hardware protects against illegal values being +// programmed by software. These bits must be programmed +// appropriately for slave mode also, as it is used to capture +// correct value of spike filter as per the speed mode. +// +// This register should be programmed only with a value in the +// range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates +// this register with the value of IC_MAX_SPEED_MODE. +// +// 1: standard mode (100 kbit/s) +// +// 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) +// +// 3: high speed mode (3.4 Mbit/s) +// +// Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 +// 0x1 -> Standard Speed mode of operation +// 0x2 -> Fast or Fast Plus mode of operation +// 0x3 -> High Speed mode of operation +#define I2C_IC_CON_SPEED_RESET _u(0x2) +#define I2C_IC_CON_SPEED_BITS _u(0x00000006) +#define I2C_IC_CON_SPEED_MSB _u(2) +#define I2C_IC_CON_SPEED_LSB _u(1) +#define I2C_IC_CON_SPEED_ACCESS "RW" +#define I2C_IC_CON_SPEED_VALUE_STANDARD _u(0x1) +#define I2C_IC_CON_SPEED_VALUE_FAST _u(0x2) +#define I2C_IC_CON_SPEED_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CON_MASTER_MODE +// Description : This bit controls whether the DW_apb_i2c master is enabled. +// +// NOTE: Software should ensure that if this bit is written with +// '1' then bit 6 should also be written with a '1'. +// 0x0 -> Master mode is disabled +// 0x1 -> Master mode is enabled +#define I2C_IC_CON_MASTER_MODE_RESET _u(0x1) +#define I2C_IC_CON_MASTER_MODE_BITS _u(0x00000001) +#define I2C_IC_CON_MASTER_MODE_MSB _u(0) +#define I2C_IC_CON_MASTER_MODE_LSB _u(0) +#define I2C_IC_CON_MASTER_MODE_ACCESS "RW" +#define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED _u(0x0) +#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED _u(0x1) +// ============================================================================= +// Register : I2C_IC_TAR +// Description : I2C Target Address Register +// +// This register is 12 bits wide, and bits 31:12 are reserved. +// This register can be written to only when IC_ENABLE[0] is set +// to 0. +// +// Note: If the software or application is aware that the +// DW_apb_i2c is not using the TAR address for the pending +// commands in the Tx FIFO, then it is possible to update the TAR +// address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - +// It is not necessary to perform any write to this register if +// DW_apb_i2c is enabled as an I2C slave only. +#define I2C_IC_TAR_OFFSET _u(0x00000004) +#define I2C_IC_TAR_BITS _u(0x00000fff) +#define I2C_IC_TAR_RESET _u(0x00000055) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TAR_SPECIAL +// Description : This bit indicates whether software performs a Device-ID or +// General Call or START BYTE command. - 0: ignore bit 10 +// GC_OR_START and use IC_TAR normally - 1: perform special I2C +// command as specified in Device_ID or GC_OR_START bit Reset +// value: 0x0 +// 0x0 -> Disables programming of GENERAL_CALL or START_BYTE transmission +// 0x1 -> Enables programming of GENERAL_CALL or START_BYTE transmission +#define I2C_IC_TAR_SPECIAL_RESET _u(0x0) +#define I2C_IC_TAR_SPECIAL_BITS _u(0x00000800) +#define I2C_IC_TAR_SPECIAL_MSB _u(11) +#define I2C_IC_TAR_SPECIAL_LSB _u(11) +#define I2C_IC_TAR_SPECIAL_ACCESS "RW" +#define I2C_IC_TAR_SPECIAL_VALUE_DISABLED _u(0x0) +#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TAR_GC_OR_START +// Description : If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to +// 0, then this bit indicates whether a General Call or START byte +// command is to be performed by the DW_apb_i2c. - 0: General Call +// Address - after issuing a General Call, only writes may be +// performed. Attempting to issue a read command results in +// setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The +// DW_apb_i2c remains in General Call mode until the SPECIAL bit +// value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 +// 0x0 -> GENERAL_CALL byte transmission +// 0x1 -> START byte transmission +#define I2C_IC_TAR_GC_OR_START_RESET _u(0x0) +#define I2C_IC_TAR_GC_OR_START_BITS _u(0x00000400) +#define I2C_IC_TAR_GC_OR_START_MSB _u(10) +#define I2C_IC_TAR_GC_OR_START_LSB _u(10) +#define I2C_IC_TAR_GC_OR_START_ACCESS "RW" +#define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL _u(0x0) +#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TAR_IC_TAR +// Description : This is the target address for any master transaction. When +// transmitting a General Call, these bits are ignored. To +// generate a START BYTE, the CPU needs to write only once into +// these bits. +// +// If the IC_TAR and IC_SAR are the same, loopback exists but the +// FIFOs are shared between master and slave, so full loopback is +// not feasible. Only one direction loopback mode is supported +// (simplex), not duplex. A master cannot transmit to itself; it +// can transmit to only a slave. +#define I2C_IC_TAR_IC_TAR_RESET _u(0x055) +#define I2C_IC_TAR_IC_TAR_BITS _u(0x000003ff) +#define I2C_IC_TAR_IC_TAR_MSB _u(9) +#define I2C_IC_TAR_IC_TAR_LSB _u(0) +#define I2C_IC_TAR_IC_TAR_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SAR +// Description : I2C Slave Address Register +#define I2C_IC_SAR_OFFSET _u(0x00000008) +#define I2C_IC_SAR_BITS _u(0x000003ff) +#define I2C_IC_SAR_RESET _u(0x00000055) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SAR_IC_SAR +// Description : The IC_SAR holds the slave address when the I2C is operating as +// a slave. For 7-bit addressing, only IC_SAR[6:0] is used. +// +// This register can be written only when the I2C interface is +// disabled, which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// Note: The default values cannot be any of the reserved address +// locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct +// operation of the device is not guaranteed if you program the +// IC_SAR or IC_TAR to a reserved value. Refer to +// <> for a complete list of these +// reserved values. +#define I2C_IC_SAR_IC_SAR_RESET _u(0x055) +#define I2C_IC_SAR_IC_SAR_BITS _u(0x000003ff) +#define I2C_IC_SAR_IC_SAR_MSB _u(9) +#define I2C_IC_SAR_IC_SAR_LSB _u(0) +#define I2C_IC_SAR_IC_SAR_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_DATA_CMD +// Description : I2C Rx/Tx Data Buffer and Command Register; this is the +// register the CPU writes to when filling the TX FIFO and the CPU +// reads from when retrieving bytes from RX FIFO. +// +// The size of the register changes as follows: +// +// Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits +// when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when +// IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when +// IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c +// to continue acknowledging reads, a read command should be +// written for every byte that is to be received; otherwise the +// DW_apb_i2c will stop acknowledging. +#define I2C_IC_DATA_CMD_OFFSET _u(0x00000010) +#define I2C_IC_DATA_CMD_BITS _u(0x00000fff) +#define I2C_IC_DATA_CMD_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_FIRST_DATA_BYTE +// Description : Indicates the first data byte received after the address phase +// for receive transfer in Master receiver or Slave receiver mode. +// +// Reset value : 0x0 +// +// NOTE: In case of APB_DATA_WIDTH=8, +// +// 1. The user has to perform two APB Reads to IC_DATA_CMD in +// order to get status on 11 bit. +// +// 2. In order to read the 11 bit, the user has to perform the +// first data byte read [7:0] (offset 0x10) and then perform the +// second read [15:8] (offset 0x11) in order to know the status of +// 11 bit (whether the data received in previous read is a first +// data byte or not). +// +// 3. The 11th bit is an optional read field, user can ignore 2nd +// byte read [15:8] (offset 0x11) if not interested in +// FIRST_DATA_BYTE status. +// 0x0 -> Sequential data byte received +// 0x1 -> Non sequential data byte received +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET _u(0x0) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS _u(0x00000800) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB _u(11) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB _u(11) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS "RO" +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE _u(0x0) +#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_RESTART +// Description : This bit controls whether a RESTART is issued before the byte +// is sent or received. +// +// 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data +// is sent/received (according to the value of CMD), regardless of +// whether or not the transfer direction is changing from the +// previous command; if IC_RESTART_EN is 0, a STOP followed by a +// START is issued instead. +// +// 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the +// transfer direction is changing from the previous command; if +// IC_RESTART_EN is 0, a STOP followed by a START is issued +// instead. +// +// Reset value: 0x0 +// 0x0 -> Don't Issue RESTART before this command +// 0x1 -> Issue RESTART before this command +#define I2C_IC_DATA_CMD_RESTART_RESET _u(0x0) +#define I2C_IC_DATA_CMD_RESTART_BITS _u(0x00000400) +#define I2C_IC_DATA_CMD_RESTART_MSB _u(10) +#define I2C_IC_DATA_CMD_RESTART_LSB _u(10) +#define I2C_IC_DATA_CMD_RESTART_ACCESS "SC" +#define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE _u(0x0) +#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_STOP +// Description : This bit controls whether a STOP is issued after the byte is +// sent or received. +// +// - 1 - STOP is issued after this byte, regardless of whether or +// not the Tx FIFO is empty. If the Tx FIFO is not empty, the +// master immediately tries to start a new transfer by issuing a +// START and arbitrating for the bus. - 0 - STOP is not issued +// after this byte, regardless of whether or not the Tx FIFO is +// empty. If the Tx FIFO is not empty, the master continues the +// current transfer by sending/receiving data bytes according to +// the value of the CMD bit. If the Tx FIFO is empty, the master +// holds the SCL line low and stalls the bus until a new command +// is available in the Tx FIFO. Reset value: 0x0 +// 0x0 -> Don't Issue STOP after this command +// 0x1 -> Issue STOP after this command +#define I2C_IC_DATA_CMD_STOP_RESET _u(0x0) +#define I2C_IC_DATA_CMD_STOP_BITS _u(0x00000200) +#define I2C_IC_DATA_CMD_STOP_MSB _u(9) +#define I2C_IC_DATA_CMD_STOP_LSB _u(9) +#define I2C_IC_DATA_CMD_STOP_ACCESS "SC" +#define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE _u(0x0) +#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_CMD +// Description : This bit controls whether a read or a write is performed. This +// bit does not control the direction when the DW_apb_i2con acts +// as a slave. It controls only the direction when it acts as a +// master. +// +// When a command is entered in the TX FIFO, this bit +// distinguishes the write and read commands. In slave-receiver +// mode, this bit is a 'don't care' because writes to this +// register are not required. In slave-transmitter mode, a '0' +// indicates that the data in IC_DATA_CMD is to be transmitted. +// +// When programming this bit, you should remember the following: +// attempting to perform a read operation after a General Call +// command has been sent results in a TX_ABRT interrupt (bit 6 of +// the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the +// IC_TAR register has been cleared. If a '1' is written to this +// bit after receiving a RD_REQ interrupt, then a TX_ABRT +// interrupt occurs. +// +// Reset value: 0x0 +// 0x0 -> Master Write Command +// 0x1 -> Master Read Command +#define I2C_IC_DATA_CMD_CMD_RESET _u(0x0) +#define I2C_IC_DATA_CMD_CMD_BITS _u(0x00000100) +#define I2C_IC_DATA_CMD_CMD_MSB _u(8) +#define I2C_IC_DATA_CMD_CMD_LSB _u(8) +#define I2C_IC_DATA_CMD_CMD_ACCESS "SC" +#define I2C_IC_DATA_CMD_CMD_VALUE_WRITE _u(0x0) +#define I2C_IC_DATA_CMD_CMD_VALUE_READ _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DATA_CMD_DAT +// Description : This register contains the data to be transmitted or received +// on the I2C bus. If you are writing to this register and want to +// perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. +// However, when you read this register, these bits return the +// value of data received on the DW_apb_i2c interface. +// +// Reset value: 0x0 +#define I2C_IC_DATA_CMD_DAT_RESET _u(0x00) +#define I2C_IC_DATA_CMD_DAT_BITS _u(0x000000ff) +#define I2C_IC_DATA_CMD_DAT_MSB _u(7) +#define I2C_IC_DATA_CMD_DAT_LSB _u(0) +#define I2C_IC_DATA_CMD_DAT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SS_SCL_HCNT +// Description : Standard Speed I2C Clock SCL High Count Register +#define I2C_IC_SS_SCL_HCNT_OFFSET _u(0x00000014) +#define I2C_IC_SS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_HCNT_RESET _u(0x00000028) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock high-period count for standard speed. For more +// information, refer to 'IC_CLK Frequency Configuration'. +// +// This register can be written only when the I2C interface is +// disabled which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// The minimum valid value is 6; hardware prevents values less +// than this being written, and if attempted results in 6 being +// set. For designs with APB_DATA_WIDTH = 8, the order of +// programming is important to ensure the correct operation of the +// DW_apb_i2c. The lower byte must be programmed first. Then the +// upper byte is programmed. +// +// NOTE: This register must not be programmed to a value higher +// than 65525, because DW_apb_i2c uses a 16-bit counter to flag an +// I2C bus idle condition when this counter reaches a value of +// IC_SS_SCL_HCNT + 10. +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET _u(0x0028) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB _u(15) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB _u(0) +#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SS_SCL_LCNT +// Description : Standard Speed I2C Clock SCL Low Count Register +#define I2C_IC_SS_SCL_LCNT_OFFSET _u(0x00000018) +#define I2C_IC_SS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_LCNT_RESET _u(0x0000002f) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock low period count for standard speed. For more +// information, refer to 'IC_CLK Frequency Configuration' +// +// This register can be written only when the I2C interface is +// disabled which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// The minimum valid value is 8; hardware prevents values less +// than this being written, and if attempted, results in 8 being +// set. For designs with APB_DATA_WIDTH = 8, the order of +// programming is important to ensure the correct operation of +// DW_apb_i2c. The lower byte must be programmed first, and then +// the upper byte is programmed. +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET _u(0x002f) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB _u(15) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB _u(0) +#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_FS_SCL_HCNT +// Description : Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register +#define I2C_IC_FS_SCL_HCNT_OFFSET _u(0x0000001c) +#define I2C_IC_FS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_HCNT_RESET _u(0x00000006) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock high-period count for fast mode or fast mode plus. It +// is used in high-speed mode to send the Master Code and START +// BYTE or General CALL. For more information, refer to 'IC_CLK +// Frequency Configuration'. +// +// This register goes away and becomes read-only returning 0s if +// IC_MAX_SPEED_MODE = standard. This register can be written only +// when the I2C interface is disabled, which corresponds to the +// IC_ENABLE[0] register being set to 0. Writes at other times +// have no effect. +// +// The minimum valid value is 6; hardware prevents values less +// than this being written, and if attempted results in 6 being +// set. For designs with APB_DATA_WIDTH == 8 the order of +// programming is important to ensure the correct operation of the +// DW_apb_i2c. The lower byte must be programmed first. Then the +// upper byte is programmed. +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET _u(0x0006) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB _u(15) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB _u(0) +#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_FS_SCL_LCNT +// Description : Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register +#define I2C_IC_FS_SCL_LCNT_OFFSET _u(0x00000020) +#define I2C_IC_FS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_LCNT_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT +// Description : This register must be set before any I2C bus transaction can +// take place to ensure proper I/O timing. This register sets the +// SCL clock low period count for fast speed. It is used in high- +// speed mode to send the Master Code and START BYTE or General +// CALL. For more information, refer to 'IC_CLK Frequency +// Configuration'. +// +// This register goes away and becomes read-only returning 0s if +// IC_MAX_SPEED_MODE = standard. +// +// This register can be written only when the I2C interface is +// disabled, which corresponds to the IC_ENABLE[0] register being +// set to 0. Writes at other times have no effect. +// +// The minimum valid value is 8; hardware prevents values less +// than this being written, and if attempted results in 8 being +// set. For designs with APB_DATA_WIDTH = 8 the order of +// programming is important to ensure the correct operation of the +// DW_apb_i2c. The lower byte must be programmed first. Then the +// upper byte is programmed. If the value is less than 8 then the +// count value gets changed to 8. +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET _u(0x000d) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS _u(0x0000ffff) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB _u(15) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB _u(0) +#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_INTR_STAT +// Description : I2C Interrupt Status Register +// +// Each bit in this register has a corresponding mask bit in the +// IC_INTR_MASK register. These bits are cleared by reading the +// matching interrupt clear register. The unmasked raw versions of +// these bits are available in the IC_RAW_INTR_STAT register. +#define I2C_IC_INTR_STAT_OFFSET _u(0x0000002c) +#define I2C_IC_INTR_STAT_BITS _u(0x00001fff) +#define I2C_IC_INTR_STAT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RESTART_DET +// Description : See IC_RAW_INTR_STAT for a detailed description of +// R_RESTART_DET bit. +// +// Reset value: 0x0 +// 0x0 -> R_RESTART_DET interrupt is inactive +// 0x1 -> R_RESTART_DET interrupt is active +#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB _u(12) +#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB _u(12) +#define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_GEN_CALL +// Description : See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_GEN_CALL interrupt is inactive +// 0x1 -> R_GEN_CALL interrupt is active +#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB _u(11) +#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB _u(11) +#define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_START_DET +// Description : See IC_RAW_INTR_STAT for a detailed description of R_START_DET +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_START_DET interrupt is inactive +// 0x1 -> R_START_DET interrupt is active +#define I2C_IC_INTR_STAT_R_START_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_START_DET_BITS _u(0x00000400) +#define I2C_IC_INTR_STAT_R_START_DET_MSB _u(10) +#define I2C_IC_INTR_STAT_R_START_DET_LSB _u(10) +#define I2C_IC_INTR_STAT_R_START_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_STOP_DET +// Description : See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_STOP_DET interrupt is inactive +// 0x1 -> R_STOP_DET interrupt is active +#define I2C_IC_INTR_STAT_R_STOP_DET_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_INTR_STAT_R_STOP_DET_MSB _u(9) +#define I2C_IC_INTR_STAT_R_STOP_DET_LSB _u(9) +#define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_ACTIVITY +// Description : See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_ACTIVITY interrupt is inactive +// 0x1 -> R_ACTIVITY interrupt is active +#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB _u(8) +#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB _u(8) +#define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_DONE +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RX_DONE interrupt is inactive +// 0x1 -> R_RX_DONE interrupt is active +#define I2C_IC_INTR_STAT_R_RX_DONE_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_INTR_STAT_R_RX_DONE_MSB _u(7) +#define I2C_IC_INTR_STAT_R_RX_DONE_LSB _u(7) +#define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_TX_ABRT +// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_TX_ABRT interrupt is inactive +// 0x1 -> R_TX_ABRT interrupt is active +#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB _u(6) +#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB _u(6) +#define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RD_REQ +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RD_REQ interrupt is inactive +// 0x1 -> R_RD_REQ interrupt is active +#define I2C_IC_INTR_STAT_R_RD_REQ_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_INTR_STAT_R_RD_REQ_MSB _u(5) +#define I2C_IC_INTR_STAT_R_RD_REQ_LSB _u(5) +#define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_TX_EMPTY +// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_TX_EMPTY interrupt is inactive +// 0x1 -> R_TX_EMPTY interrupt is active +#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB _u(4) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB _u(4) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_TX_OVER +// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_TX_OVER interrupt is inactive +// 0x1 -> R_TX_OVER interrupt is active +#define I2C_IC_INTR_STAT_R_TX_OVER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_INTR_STAT_R_TX_OVER_MSB _u(3) +#define I2C_IC_INTR_STAT_R_TX_OVER_LSB _u(3) +#define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_FULL +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RX_FULL interrupt is inactive +// 0x1 -> R_RX_FULL interrupt is active +#define I2C_IC_INTR_STAT_R_RX_FULL_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_INTR_STAT_R_RX_FULL_MSB _u(2) +#define I2C_IC_INTR_STAT_R_RX_FULL_LSB _u(2) +#define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_OVER +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER +// bit. +// +// Reset value: 0x0 +// 0x0 -> R_RX_OVER interrupt is inactive +// 0x1 -> R_RX_OVER interrupt is active +#define I2C_IC_INTR_STAT_R_RX_OVER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_INTR_STAT_R_RX_OVER_MSB _u(1) +#define I2C_IC_INTR_STAT_R_RX_OVER_LSB _u(1) +#define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_STAT_R_RX_UNDER +// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER +// bit. +// +// Reset value: 0x0 +// 0x0 -> RX_UNDER interrupt is inactive +// 0x1 -> RX_UNDER interrupt is active +#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB _u(0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB _u(0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS "RO" +#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE _u(0x1) +// ============================================================================= +// Register : I2C_IC_INTR_MASK +// Description : I2C Interrupt Mask Register. +// +// These bits mask their corresponding interrupt status bits. This +// register is active low; a value of 0 masks the interrupt, +// whereas a value of 1 unmasks the interrupt. +#define I2C_IC_INTR_MASK_OFFSET _u(0x00000030) +#define I2C_IC_INTR_MASK_BITS _u(0x00001fff) +#define I2C_IC_INTR_MASK_RESET _u(0x000008ff) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RESTART_DET +// Description : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> RESTART_DET interrupt is masked +// 0x1 -> RESTART_DET interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB _u(12) +#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB _u(12) +#define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_GEN_CALL +// Description : This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> GEN_CALL interrupt is masked +// 0x1 -> GEN_CALL interrupt is unmasked +#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB _u(11) +#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB _u(11) +#define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_START_DET +// Description : This bit masks the R_START_DET interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> START_DET interrupt is masked +// 0x1 -> START_DET interrupt is unmasked +#define I2C_IC_INTR_MASK_M_START_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_START_DET_BITS _u(0x00000400) +#define I2C_IC_INTR_MASK_M_START_DET_MSB _u(10) +#define I2C_IC_INTR_MASK_M_START_DET_LSB _u(10) +#define I2C_IC_INTR_MASK_M_START_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_STOP_DET +// Description : This bit masks the R_STOP_DET interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> STOP_DET interrupt is masked +// 0x1 -> STOP_DET interrupt is unmasked +#define I2C_IC_INTR_MASK_M_STOP_DET_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_INTR_MASK_M_STOP_DET_MSB _u(9) +#define I2C_IC_INTR_MASK_M_STOP_DET_LSB _u(9) +#define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_ACTIVITY +// Description : This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x0 +// 0x0 -> ACTIVITY interrupt is masked +// 0x1 -> ACTIVITY interrupt is unmasked +#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET _u(0x0) +#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB _u(8) +#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB _u(8) +#define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_DONE +// Description : This bit masks the R_RX_DONE interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_DONE interrupt is masked +// 0x1 -> RX_DONE interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_DONE_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_INTR_MASK_M_RX_DONE_MSB _u(7) +#define I2C_IC_INTR_MASK_M_RX_DONE_LSB _u(7) +#define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_TX_ABRT +// Description : This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> TX_ABORT interrupt is masked +// 0x1 -> TX_ABORT interrupt is unmasked +#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB _u(6) +#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB _u(6) +#define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RD_REQ +// Description : This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. +// +// Reset value: 0x1 +// 0x0 -> RD_REQ interrupt is masked +// 0x1 -> RD_REQ interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RD_REQ_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_INTR_MASK_M_RD_REQ_MSB _u(5) +#define I2C_IC_INTR_MASK_M_RD_REQ_LSB _u(5) +#define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_TX_EMPTY +// Description : This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> TX_EMPTY interrupt is masked +// 0x1 -> TX_EMPTY interrupt is unmasked +#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB _u(4) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB _u(4) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_TX_OVER +// Description : This bit masks the R_TX_OVER interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> TX_OVER interrupt is masked +// 0x1 -> TX_OVER interrupt is unmasked +#define I2C_IC_INTR_MASK_M_TX_OVER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_INTR_MASK_M_TX_OVER_MSB _u(3) +#define I2C_IC_INTR_MASK_M_TX_OVER_LSB _u(3) +#define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_FULL +// Description : This bit masks the R_RX_FULL interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_FULL interrupt is masked +// 0x1 -> RX_FULL interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_FULL_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_INTR_MASK_M_RX_FULL_MSB _u(2) +#define I2C_IC_INTR_MASK_M_RX_FULL_LSB _u(2) +#define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_OVER +// Description : This bit masks the R_RX_OVER interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_OVER interrupt is masked +// 0x1 -> RX_OVER interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_OVER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_INTR_MASK_M_RX_OVER_MSB _u(1) +#define I2C_IC_INTR_MASK_M_RX_OVER_LSB _u(1) +#define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_INTR_MASK_M_RX_UNDER +// Description : This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT +// register. +// +// Reset value: 0x1 +// 0x0 -> RX_UNDER interrupt is masked +// 0x1 -> RX_UNDER interrupt is unmasked +#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET _u(0x1) +#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB _u(0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB _u(0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS "RW" +#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED _u(0x0) +#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED _u(0x1) +// ============================================================================= +// Register : I2C_IC_RAW_INTR_STAT +// Description : I2C Raw Interrupt Status Register +// +// Unlike the IC_INTR_STAT register, these bits are not masked so +// they always show the true status of the DW_apb_i2c. +#define I2C_IC_RAW_INTR_STAT_OFFSET _u(0x00000034) +#define I2C_IC_RAW_INTR_STAT_BITS _u(0x00001fff) +#define I2C_IC_RAW_INTR_STAT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RESTART_DET +// Description : Indicates whether a RESTART condition has occurred on the I2C +// interface when DW_apb_i2c is operating in Slave mode and the +// slave is being addressed. Enabled only when +// IC_SLV_RESTART_DET_EN=1. +// +// Note: However, in high-speed mode or during a START BYTE +// transfer, the RESTART comes before the address field as per the +// I2C protocol. In this case, the slave is not the addressed +// slave when the RESTART is issued, therefore DW_apb_i2c does not +// generate the RESTART_DET interrupt. +// +// Reset value: 0x0 +// 0x0 -> RESTART_DET interrupt is inactive +// 0x1 -> RESTART_DET interrupt is active +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS _u(0x00001000) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB _u(12) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB _u(12) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_GEN_CALL +// Description : Set only when a General Call address is received and it is +// acknowledged. It stays set until it is cleared either by +// disabling DW_apb_i2c or when the CPU reads bit 0 of the +// IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data +// in the Rx buffer. +// +// Reset value: 0x0 +// 0x0 -> GEN_CALL interrupt is inactive +// 0x1 -> GEN_CALL interrupt is active +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS _u(0x00000800) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB _u(11) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB _u(11) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_START_DET +// Description : Indicates whether a START or RESTART condition has occurred on +// the I2C interface regardless of whether DW_apb_i2c is operating +// in slave or master mode. +// +// Reset value: 0x0 +// 0x0 -> START_DET interrupt is inactive +// 0x1 -> START_DET interrupt is active +#define I2C_IC_RAW_INTR_STAT_START_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_START_DET_BITS _u(0x00000400) +#define I2C_IC_RAW_INTR_STAT_START_DET_MSB _u(10) +#define I2C_IC_RAW_INTR_STAT_START_DET_LSB _u(10) +#define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_STOP_DET +// Description : Indicates whether a STOP condition has occurred on the I2C +// interface regardless of whether DW_apb_i2c is operating in +// slave or master mode. +// +// In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the +// STOP_DET interrupt will be issued only if slave is addressed. +// Note: During a general call address, this slave does not issue +// a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the +// slave responds to the general call address by generating ACK. +// The STOP_DET interrupt is generated only when the transmitted +// address matches the slave address (SAR). - If IC_CON[7]=1'b0 +// (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued +// irrespective of whether it is being addressed. In Master Mode: +// - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET +// interrupt will be issued only if Master is active. - If +// IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt +// will be issued irrespective of whether master is active or not. +// Reset value: 0x0 +// 0x0 -> STOP_DET interrupt is inactive +// 0x1 -> STOP_DET interrupt is active +#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS _u(0x00000200) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB _u(9) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB _u(9) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_ACTIVITY +// Description : This bit captures DW_apb_i2c activity and stays set until it is +// cleared. There are four ways to clear it: - Disabling the +// DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the +// IC_CLR_INTR register - System reset Once this bit is set, it +// stays set unless one of the four methods is used to clear it. +// Even if the DW_apb_i2c module is idle, this bit remains set +// until cleared, indicating that there was activity on the bus. +// +// Reset value: 0x0 +// 0x0 -> RAW_INTR_ACTIVITY interrupt is inactive +// 0x1 -> RAW_INTR_ACTIVITY interrupt is active +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS _u(0x00000100) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB _u(8) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB _u(8) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_DONE +// Description : When the DW_apb_i2c is acting as a slave-transmitter, this bit +// is set to 1 if the master does not acknowledge a transmitted +// byte. This occurs on the last byte of the transmission, +// indicating that the transmission is done. +// +// Reset value: 0x0 +// 0x0 -> RX_DONE interrupt is inactive +// 0x1 -> RX_DONE interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS _u(0x00000080) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB _u(7) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB _u(7) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_TX_ABRT +// Description : This bit indicates if DW_apb_i2c, as an I2C transmitter, is +// unable to complete the intended actions on the contents of the +// transmit FIFO. This situation can occur both as an I2C master +// or an I2C slave, and is referred to as a 'transmit abort'. When +// this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates +// the reason why the transmit abort takes places. +// +// Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and +// RX_FIFO whenever there is a transmit abort caused by any of the +// events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs +// remains in this flushed state until the register IC_CLR_TX_ABRT +// is read. Once this read is performed, the Tx FIFO is then ready +// to accept more data bytes from the APB interface. +// +// Reset value: 0x0 +// 0x0 -> TX_ABRT interrupt is inactive +// 0x1 -> TX_ABRT interrupt is active +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS _u(0x00000040) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB _u(6) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB _u(6) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RD_REQ +// Description : This bit is set to 1 when DW_apb_i2c is acting as a slave and +// another I2C master is attempting to read data from DW_apb_i2c. +// The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until +// this interrupt is serviced, which means that the slave has been +// addressed by a remote master that is asking for data to be +// transferred. The processor must respond to this interrupt and +// then write the requested data to the IC_DATA_CMD register. This +// bit is set to 0 just after the processor reads the +// IC_CLR_RD_REQ register. +// +// Reset value: 0x0 +// 0x0 -> RD_REQ interrupt is inactive +// 0x1 -> RD_REQ interrupt is active +#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS _u(0x00000020) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB _u(5) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB _u(5) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_TX_EMPTY +// Description : The behavior of the TX_EMPTY interrupt status differs based on +// the TX_EMPTY_CTRL selection in the IC_CON register. - When +// TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit +// buffer is at or below the threshold value set in the IC_TX_TL +// register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when +// the transmit buffer is at or below the threshold value set in +// the IC_TX_TL register and the transmission of the address/data +// from the internal shift register for the most recently popped +// command is completed. It is automatically cleared by hardware +// when the buffer level goes above the threshold. When +// IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in +// reset. There the TX FIFO looks like it has no data within it, +// so this bit is set to 1, provided there is activity in the +// master or slave state machines. When there is no longer any +// activity, then with ic_en=0, this bit is set to 0. +// +// Reset value: 0x0. +// 0x0 -> TX_EMPTY interrupt is inactive +// 0x1 -> TX_EMPTY interrupt is active +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS _u(0x00000010) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB _u(4) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB _u(4) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_TX_OVER +// Description : Set during transmit if the transmit buffer is filled to +// IC_TX_BUFFER_DEPTH and the processor attempts to issue another +// I2C command by writing to the IC_DATA_CMD register. When the +// module is disabled, this bit keeps its level until the master +// or slave state machines go into idle, and when ic_en goes to 0, +// this interrupt is cleared. +// +// Reset value: 0x0 +// 0x0 -> TX_OVER interrupt is inactive +// 0x1 -> TX_OVER interrupt is active +#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS _u(0x00000008) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB _u(3) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB _u(3) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_FULL +// Description : Set when the receive buffer reaches or goes above the RX_TL +// threshold in the IC_RX_TL register. It is automatically cleared +// by hardware when buffer level goes below the threshold. If the +// module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and +// held in reset; therefore the RX FIFO is not full. So this bit +// is cleared once the IC_ENABLE bit 0 is programmed with a 0, +// regardless of the activity that continues. +// +// Reset value: 0x0 +// 0x0 -> RX_FULL interrupt is inactive +// 0x1 -> RX_FULL interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS _u(0x00000004) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB _u(2) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB _u(2) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_OVER +// Description : Set if the receive buffer is completely filled to +// IC_RX_BUFFER_DEPTH and an additional byte is received from an +// external I2C device. The DW_apb_i2c acknowledges this, but any +// data bytes received after the FIFO is full are lost. If the +// module is disabled (IC_ENABLE[0]=0), this bit keeps its level +// until the master or slave state machines go into idle, and when +// ic_en goes to 0, this interrupt is cleared. +// +// Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) +// is programmed to HIGH, then the RX_OVER interrupt never occurs, +// because the Rx FIFO never overflows. +// +// Reset value: 0x0 +// 0x0 -> RX_OVER interrupt is inactive +// 0x1 -> RX_OVER interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS _u(0x00000002) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB _u(1) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB _u(1) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RAW_INTR_STAT_RX_UNDER +// Description : Set if the processor attempts to read the receive buffer when +// it is empty by reading from the IC_DATA_CMD register. If the +// module is disabled (IC_ENABLE[0]=0), this bit keeps its level +// until the master or slave state machines go into idle, and when +// ic_en goes to 0, this interrupt is cleared. +// +// Reset value: 0x0 +// 0x0 -> RX_UNDER interrupt is inactive +// 0x1 -> RX_UNDER interrupt is active +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB _u(0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB _u(0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS "RO" +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE _u(0x0) +#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE _u(0x1) +// ============================================================================= +// Register : I2C_IC_RX_TL +// Description : I2C Receive FIFO Threshold Register +#define I2C_IC_RX_TL_OFFSET _u(0x00000038) +#define I2C_IC_RX_TL_BITS _u(0x000000ff) +#define I2C_IC_RX_TL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RX_TL_RX_TL +// Description : Receive FIFO Threshold Level. +// +// Controls the level of entries (or above) that triggers the +// RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The +// valid range is 0-255, with the additional restriction that +// hardware does not allow this value to be set to a value larger +// than the depth of the buffer. If an attempt is made to do that, +// the actual value set will be the maximum depth of the buffer. A +// value of 0 sets the threshold for 1 entry, and a value of 255 +// sets the threshold for 256 entries. +#define I2C_IC_RX_TL_RX_TL_RESET _u(0x00) +#define I2C_IC_RX_TL_RX_TL_BITS _u(0x000000ff) +#define I2C_IC_RX_TL_RX_TL_MSB _u(7) +#define I2C_IC_RX_TL_RX_TL_LSB _u(0) +#define I2C_IC_RX_TL_RX_TL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_TX_TL +// Description : I2C Transmit FIFO Threshold Register +#define I2C_IC_TX_TL_OFFSET _u(0x0000003c) +#define I2C_IC_TX_TL_BITS _u(0x000000ff) +#define I2C_IC_TX_TL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_TL_TX_TL +// Description : Transmit FIFO Threshold Level. +// +// Controls the level of entries (or below) that trigger the +// TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The +// valid range is 0-255, with the additional restriction that it +// may not be set to value larger than the depth of the buffer. If +// an attempt is made to do that, the actual value set will be the +// maximum depth of the buffer. A value of 0 sets the threshold +// for 0 entries, and a value of 255 sets the threshold for 255 +// entries. +#define I2C_IC_TX_TL_TX_TL_RESET _u(0x00) +#define I2C_IC_TX_TL_TX_TL_BITS _u(0x000000ff) +#define I2C_IC_TX_TL_TX_TL_MSB _u(7) +#define I2C_IC_TX_TL_TX_TL_LSB _u(0) +#define I2C_IC_TX_TL_TX_TL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_CLR_INTR +// Description : Clear Combined and Individual Interrupt Register +#define I2C_IC_CLR_INTR_OFFSET _u(0x00000040) +#define I2C_IC_CLR_INTR_BITS _u(0x00000001) +#define I2C_IC_CLR_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_INTR_CLR_INTR +// Description : Read this register to clear the combined interrupt, all +// individual interrupts, and the IC_TX_ABRT_SOURCE register. This +// bit does not clear hardware clearable interrupts but software +// clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE +// register for an exception to clearing IC_TX_ABRT_SOURCE. +// +// Reset value: 0x0 +#define I2C_IC_CLR_INTR_CLR_INTR_RESET _u(0x0) +#define I2C_IC_CLR_INTR_CLR_INTR_BITS _u(0x00000001) +#define I2C_IC_CLR_INTR_CLR_INTR_MSB _u(0) +#define I2C_IC_CLR_INTR_CLR_INTR_LSB _u(0) +#define I2C_IC_CLR_INTR_CLR_INTR_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RX_UNDER +// Description : Clear RX_UNDER Interrupt Register +#define I2C_IC_CLR_RX_UNDER_OFFSET _u(0x00000044) +#define I2C_IC_CLR_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_UNDER_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER +// Description : Read this register to clear the RX_UNDER interrupt (bit 0) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET _u(0x0) +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB _u(0) +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB _u(0) +#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RX_OVER +// Description : Clear RX_OVER Interrupt Register +#define I2C_IC_CLR_RX_OVER_OFFSET _u(0x00000048) +#define I2C_IC_CLR_RX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_OVER_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RX_OVER_CLR_RX_OVER +// Description : Read this register to clear the RX_OVER interrupt (bit 1) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET _u(0x0) +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB _u(0) +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB _u(0) +#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_TX_OVER +// Description : Clear TX_OVER Interrupt Register +#define I2C_IC_CLR_TX_OVER_OFFSET _u(0x0000004c) +#define I2C_IC_CLR_TX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_OVER_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_TX_OVER_CLR_TX_OVER +// Description : Read this register to clear the TX_OVER interrupt (bit 3) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET _u(0x0) +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB _u(0) +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB _u(0) +#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RD_REQ +// Description : Clear RD_REQ Interrupt Register +#define I2C_IC_CLR_RD_REQ_OFFSET _u(0x00000050) +#define I2C_IC_CLR_RD_REQ_BITS _u(0x00000001) +#define I2C_IC_CLR_RD_REQ_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RD_REQ_CLR_RD_REQ +// Description : Read this register to clear the RD_REQ interrupt (bit 5) of the +// IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET _u(0x0) +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_BITS _u(0x00000001) +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB _u(0) +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB _u(0) +#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_TX_ABRT +// Description : Clear TX_ABRT Interrupt Register +#define I2C_IC_CLR_TX_ABRT_OFFSET _u(0x00000054) +#define I2C_IC_CLR_TX_ABRT_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_ABRT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT +// Description : Read this register to clear the TX_ABRT interrupt (bit 6) of +// the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE +// register. This also releases the TX FIFO from the flushed/reset +// state, allowing more writes to the TX FIFO. Refer to Bit 9 of +// the IC_TX_ABRT_SOURCE register for an exception to clearing +// IC_TX_ABRT_SOURCE. +// +// Reset value: 0x0 +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET _u(0x0) +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_BITS _u(0x00000001) +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB _u(0) +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB _u(0) +#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_RX_DONE +// Description : Clear RX_DONE Interrupt Register +#define I2C_IC_CLR_RX_DONE_OFFSET _u(0x00000058) +#define I2C_IC_CLR_RX_DONE_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_DONE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RX_DONE_CLR_RX_DONE +// Description : Read this register to clear the RX_DONE interrupt (bit 7) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET _u(0x0) +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_BITS _u(0x00000001) +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB _u(0) +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB _u(0) +#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_ACTIVITY +// Description : Clear ACTIVITY Interrupt Register +#define I2C_IC_CLR_ACTIVITY_OFFSET _u(0x0000005c) +#define I2C_IC_CLR_ACTIVITY_BITS _u(0x00000001) +#define I2C_IC_CLR_ACTIVITY_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY +// Description : Reading this register clears the ACTIVITY interrupt if the I2C +// is not active anymore. If the I2C module is still active on the +// bus, the ACTIVITY interrupt bit continues to be set. It is +// automatically cleared by hardware if the module is disabled and +// if there is no further activity on the bus. The value read from +// this register to get status of the ACTIVITY interrupt (bit 8) +// of the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET _u(0x0) +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_BITS _u(0x00000001) +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB _u(0) +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB _u(0) +#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_STOP_DET +// Description : Clear STOP_DET Interrupt Register +#define I2C_IC_CLR_STOP_DET_OFFSET _u(0x00000060) +#define I2C_IC_CLR_STOP_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_STOP_DET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_STOP_DET_CLR_STOP_DET +// Description : Read this register to clear the STOP_DET interrupt (bit 9) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET _u(0x0) +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB _u(0) +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB _u(0) +#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_START_DET +// Description : Clear START_DET Interrupt Register +#define I2C_IC_CLR_START_DET_OFFSET _u(0x00000064) +#define I2C_IC_CLR_START_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_START_DET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_START_DET_CLR_START_DET +// Description : Read this register to clear the START_DET interrupt (bit 10) of +// the IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_START_DET_CLR_START_DET_RESET _u(0x0) +#define I2C_IC_CLR_START_DET_CLR_START_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_START_DET_CLR_START_DET_MSB _u(0) +#define I2C_IC_CLR_START_DET_CLR_START_DET_LSB _u(0) +#define I2C_IC_CLR_START_DET_CLR_START_DET_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_CLR_GEN_CALL +// Description : Clear GEN_CALL Interrupt Register +#define I2C_IC_CLR_GEN_CALL_OFFSET _u(0x00000068) +#define I2C_IC_CLR_GEN_CALL_BITS _u(0x00000001) +#define I2C_IC_CLR_GEN_CALL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL +// Description : Read this register to clear the GEN_CALL interrupt (bit 11) of +// IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET _u(0x0) +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_BITS _u(0x00000001) +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB _u(0) +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB _u(0) +#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_ENABLE +// Description : I2C Enable Register +#define I2C_IC_ENABLE_OFFSET _u(0x0000006c) +#define I2C_IC_ENABLE_BITS _u(0x00000007) +#define I2C_IC_ENABLE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_TX_CMD_BLOCK +// Description : In Master mode: - 1'b1: Blocks the transmission of data on I2C +// bus even if Tx FIFO has data to transmit. - 1'b0: The +// transmission of data starts on I2C bus automatically, as soon +// as the first data is available in the Tx FIFO. Note: To block +// the execution of Master commands, set the TX_CMD_BLOCK bit only +// when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle +// state (IC_STATUS[5] == 0). Any further commands put in the Tx +// FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset +// value: IC_TX_CMD_BLOCK_DEFAULT +// 0x0 -> Tx Command execution not blocked +// 0x1 -> Tx Command execution blocked +#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET _u(0x0) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS _u(0x00000004) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB _u(2) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB _u(2) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS "RW" +#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED _u(0x0) +#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_ABORT +// Description : When set, the controller initiates the transfer abort. - 0: +// ABORT not initiated or ABORT done - 1: ABORT operation in +// progress The software can abort the I2C transfer in master mode +// by setting this bit. The software can set this bit only when +// ENABLE is already set; otherwise, the controller ignores any +// write to ABORT bit. The software cannot clear the ABORT bit +// once set. In response to an ABORT, the controller issues a STOP +// and flushes the Tx FIFO after completing the current transfer, +// then sets the TX_ABORT interrupt after the abort operation. The +// ABORT bit is cleared automatically after the abort operation. +// +// For a detailed description on how to abort I2C transfers, refer +// to 'Aborting I2C Transfers'. +// +// Reset value: 0x0 +// 0x0 -> ABORT operation not in progress +// 0x1 -> ABORT operation in progress +#define I2C_IC_ENABLE_ABORT_RESET _u(0x0) +#define I2C_IC_ENABLE_ABORT_BITS _u(0x00000002) +#define I2C_IC_ENABLE_ABORT_MSB _u(1) +#define I2C_IC_ENABLE_ABORT_LSB _u(1) +#define I2C_IC_ENABLE_ABORT_ACCESS "RW" +#define I2C_IC_ENABLE_ABORT_VALUE_DISABLE _u(0x0) +#define I2C_IC_ENABLE_ABORT_VALUE_ENABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_ENABLE +// Description : Controls whether the DW_apb_i2c is enabled. - 0: Disables +// DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: +// Enables DW_apb_i2c Software can disable DW_apb_i2c while it is +// active. However, it is important that care be taken to ensure +// that DW_apb_i2c is disabled properly. A recommended procedure +// is described in 'Disabling DW_apb_i2c'. +// +// When DW_apb_i2c is disabled, the following occurs: - The TX +// FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT +// register are still active until DW_apb_i2c goes into IDLE +// state. If the module is transmitting, it stops as well as +// deletes the contents of the transmit buffer after the current +// transfer is complete. If the module is receiving, the +// DW_apb_i2c stops the current transfer at the end of the current +// byte and does not acknowledge the transfer. +// +// In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE +// parameter set to asynchronous (1), there is a two ic_clk delay +// when enabling or disabling the DW_apb_i2c. For a detailed +// description on how to disable DW_apb_i2c, refer to 'Disabling +// DW_apb_i2c' +// +// Reset value: 0x0 +// 0x0 -> I2C is disabled +// 0x1 -> I2C is enabled +#define I2C_IC_ENABLE_ENABLE_RESET _u(0x0) +#define I2C_IC_ENABLE_ENABLE_BITS _u(0x00000001) +#define I2C_IC_ENABLE_ENABLE_MSB _u(0) +#define I2C_IC_ENABLE_ENABLE_LSB _u(0) +#define I2C_IC_ENABLE_ENABLE_ACCESS "RW" +#define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED _u(0x0) +#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED _u(0x1) +// ============================================================================= +// Register : I2C_IC_STATUS +// Description : I2C Status Register +// +// This is a read-only register used to indicate the current +// transfer status and FIFO status. The status register may be +// read at any time. None of the bits in this register request an +// interrupt. +// +// When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE +// register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set +// to 0 When the master or slave state machines goes to idle and +// ic_en=0: - Bits 5 and 6 are set to 0 +#define I2C_IC_STATUS_OFFSET _u(0x00000070) +#define I2C_IC_STATUS_BITS _u(0x0000007f) +#define I2C_IC_STATUS_RESET _u(0x00000006) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_SLV_ACTIVITY +// Description : Slave FSM Activity Status. When the Slave Finite State Machine +// (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM +// is in IDLE state so the Slave part of DW_apb_i2c is not Active +// - 1: Slave FSM is not in IDLE state so the Slave part of +// DW_apb_i2c is Active Reset value: 0x0 +// 0x0 -> Slave is idle +// 0x1 -> Slave not idle +#define I2C_IC_STATUS_SLV_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_SLV_ACTIVITY_BITS _u(0x00000040) +#define I2C_IC_STATUS_SLV_ACTIVITY_MSB _u(6) +#define I2C_IC_STATUS_SLV_ACTIVITY_LSB _u(6) +#define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE _u(0x0) +#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_MST_ACTIVITY +// Description : Master FSM Activity Status. When the Master Finite State +// Machine (FSM) is not in the IDLE state, this bit is set. - 0: +// Master FSM is in IDLE state so the Master part of DW_apb_i2c is +// not Active - 1: Master FSM is not in IDLE state so the Master +// part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, +// ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. +// +// Reset value: 0x0 +// 0x0 -> Master is idle +// 0x1 -> Master not idle +#define I2C_IC_STATUS_MST_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_MST_ACTIVITY_BITS _u(0x00000020) +#define I2C_IC_STATUS_MST_ACTIVITY_MSB _u(5) +#define I2C_IC_STATUS_MST_ACTIVITY_LSB _u(5) +#define I2C_IC_STATUS_MST_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE _u(0x0) +#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_RFF +// Description : Receive FIFO Completely Full. When the receive FIFO is +// completely full, this bit is set. When the receive FIFO +// contains one or more empty location, this bit is cleared. - 0: +// Receive FIFO is not full - 1: Receive FIFO is full Reset value: +// 0x0 +// 0x0 -> Rx FIFO not full +// 0x1 -> Rx FIFO is full +#define I2C_IC_STATUS_RFF_RESET _u(0x0) +#define I2C_IC_STATUS_RFF_BITS _u(0x00000010) +#define I2C_IC_STATUS_RFF_MSB _u(4) +#define I2C_IC_STATUS_RFF_LSB _u(4) +#define I2C_IC_STATUS_RFF_ACCESS "RO" +#define I2C_IC_STATUS_RFF_VALUE_NOT_FULL _u(0x0) +#define I2C_IC_STATUS_RFF_VALUE_FULL _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_RFNE +// Description : Receive FIFO Not Empty. This bit is set when the receive FIFO +// contains one or more entries; it is cleared when the receive +// FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is +// not empty Reset value: 0x0 +// 0x0 -> Rx FIFO is empty +// 0x1 -> Rx FIFO not empty +#define I2C_IC_STATUS_RFNE_RESET _u(0x0) +#define I2C_IC_STATUS_RFNE_BITS _u(0x00000008) +#define I2C_IC_STATUS_RFNE_MSB _u(3) +#define I2C_IC_STATUS_RFNE_LSB _u(3) +#define I2C_IC_STATUS_RFNE_ACCESS "RO" +#define I2C_IC_STATUS_RFNE_VALUE_EMPTY _u(0x0) +#define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_TFE +// Description : Transmit FIFO Completely Empty. When the transmit FIFO is +// completely empty, this bit is set. When it contains one or more +// valid entries, this bit is cleared. This bit field does not +// request an interrupt. - 0: Transmit FIFO is not empty - 1: +// Transmit FIFO is empty Reset value: 0x1 +// 0x0 -> Tx FIFO not empty +// 0x1 -> Tx FIFO is empty +#define I2C_IC_STATUS_TFE_RESET _u(0x1) +#define I2C_IC_STATUS_TFE_BITS _u(0x00000004) +#define I2C_IC_STATUS_TFE_MSB _u(2) +#define I2C_IC_STATUS_TFE_LSB _u(2) +#define I2C_IC_STATUS_TFE_ACCESS "RO" +#define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY _u(0x0) +#define I2C_IC_STATUS_TFE_VALUE_EMPTY _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_TFNF +// Description : Transmit FIFO Not Full. Set when the transmit FIFO contains one +// or more empty locations, and is cleared when the FIFO is full. +// - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset +// value: 0x1 +// 0x0 -> Tx FIFO is full +// 0x1 -> Tx FIFO not full +#define I2C_IC_STATUS_TFNF_RESET _u(0x1) +#define I2C_IC_STATUS_TFNF_BITS _u(0x00000002) +#define I2C_IC_STATUS_TFNF_MSB _u(1) +#define I2C_IC_STATUS_TFNF_LSB _u(1) +#define I2C_IC_STATUS_TFNF_ACCESS "RO" +#define I2C_IC_STATUS_TFNF_VALUE_FULL _u(0x0) +#define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_STATUS_ACTIVITY +// Description : I2C Activity Status. Reset value: 0x0 +// 0x0 -> I2C is idle +// 0x1 -> I2C is active +#define I2C_IC_STATUS_ACTIVITY_RESET _u(0x0) +#define I2C_IC_STATUS_ACTIVITY_BITS _u(0x00000001) +#define I2C_IC_STATUS_ACTIVITY_MSB _u(0) +#define I2C_IC_STATUS_ACTIVITY_LSB _u(0) +#define I2C_IC_STATUS_ACTIVITY_ACCESS "RO" +#define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE _u(0x1) +// ============================================================================= +// Register : I2C_IC_TXFLR +// Description : I2C Transmit FIFO Level Register This register contains the +// number of valid data entries in the transmit FIFO buffer. It is +// cleared whenever: - The I2C is disabled - There is a transmit +// abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT +// register - The slave bulk transmit mode is aborted The register +// increments whenever data is placed into the transmit FIFO and +// decrements when data is taken from the transmit FIFO. +#define I2C_IC_TXFLR_OFFSET _u(0x00000074) +#define I2C_IC_TXFLR_BITS _u(0x0000001f) +#define I2C_IC_TXFLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TXFLR_TXFLR +// Description : Transmit FIFO Level. Contains the number of valid data entries +// in the transmit FIFO. +// +// Reset value: 0x0 +#define I2C_IC_TXFLR_TXFLR_RESET _u(0x00) +#define I2C_IC_TXFLR_TXFLR_BITS _u(0x0000001f) +#define I2C_IC_TXFLR_TXFLR_MSB _u(4) +#define I2C_IC_TXFLR_TXFLR_LSB _u(0) +#define I2C_IC_TXFLR_TXFLR_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_RXFLR +// Description : I2C Receive FIFO Level Register This register contains the +// number of valid data entries in the receive FIFO buffer. It is +// cleared whenever: - The I2C is disabled - Whenever there is a +// transmit abort caused by any of the events tracked in +// IC_TX_ABRT_SOURCE The register increments whenever data is +// placed into the receive FIFO and decrements when data is taken +// from the receive FIFO. +#define I2C_IC_RXFLR_OFFSET _u(0x00000078) +#define I2C_IC_RXFLR_BITS _u(0x0000001f) +#define I2C_IC_RXFLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_RXFLR_RXFLR +// Description : Receive FIFO Level. Contains the number of valid data entries +// in the receive FIFO. +// +// Reset value: 0x0 +#define I2C_IC_RXFLR_RXFLR_RESET _u(0x00) +#define I2C_IC_RXFLR_RXFLR_BITS _u(0x0000001f) +#define I2C_IC_RXFLR_RXFLR_MSB _u(4) +#define I2C_IC_RXFLR_RXFLR_LSB _u(0) +#define I2C_IC_RXFLR_RXFLR_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_SDA_HOLD +// Description : I2C SDA Hold Time Length Register +// +// The bits [15:0] of this register are used to control the hold +// time of SDA during transmit in both slave and master mode +// (after SCL goes from HIGH to LOW). +// +// The bits [23:16] of this register are used to extend the SDA +// transition (if any) whenever SCL is HIGH in the receiver in +// either master or slave mode. +// +// Writes to this register succeed only when IC_ENABLE[0]=0. +// +// The values in this register are in units of ic_clk period. The +// value programmed in IC_SDA_TX_HOLD must be greater than the +// minimum hold time in each mode (one cycle in master mode, seven +// cycles in slave mode) for the value to be implemented. +// +// The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) +// cannot exceed at any time the duration of the low part of scl. +// Therefore the programmed value cannot be larger than +// N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of +// the scl period measured in ic_clk cycles. +#define I2C_IC_SDA_HOLD_OFFSET _u(0x0000007c) +#define I2C_IC_SDA_HOLD_BITS _u(0x00ffffff) +#define I2C_IC_SDA_HOLD_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD +// Description : Sets the required SDA hold time in units of ic_clk period, when +// DW_apb_i2c acts as a receiver. +// +// Reset value: IC_DEFAULT_SDA_HOLD[23:16]. +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET _u(0x00) +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_BITS _u(0x00ff0000) +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB _u(23) +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB _u(16) +#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD +// Description : Sets the required SDA hold time in units of ic_clk period, when +// DW_apb_i2c acts as a transmitter. +// +// Reset value: IC_DEFAULT_SDA_HOLD[15:0]. +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET _u(0x0001) +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS _u(0x0000ffff) +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB _u(15) +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB _u(0) +#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_TX_ABRT_SOURCE +// Description : I2C Transmit Abort Source Register +// +// This register has 32 bits that indicate the source of the +// TX_ABRT bit. Except for Bit 9, this register is cleared +// whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR +// register is read. To clear Bit 9, the source of the +// ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled +// (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or +// the GC_OR_START bit must be cleared (IC_TAR[10]). +// +// Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this +// bit can be cleared in the same manner as other bits in this +// register. If the source of the ABRT_SBYTE_NORSTRT is not fixed +// before attempting to clear this bit, Bit 9 clears for one cycle +// and is then re-asserted. +#define I2C_IC_TX_ABRT_SOURCE_OFFSET _u(0x00000080) +#define I2C_IC_TX_ABRT_SOURCE_BITS _u(0xff81ffff) +#define I2C_IC_TX_ABRT_SOURCE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT +// Description : This field indicates the number of Tx FIFO Data Commands which +// are flushed due to TX_ABRT interrupt. It is cleared whenever +// I2C is disabled. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET _u(0x000) +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_BITS _u(0xff800000) +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB _u(31) +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB _u(23) +#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT +// Description : This is a master-mode-only bit. Master has detected the +// transfer abort (IC_ENABLE[1]) +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> Transfer abort detected by master- scenario not present +// 0x1 -> Transfer abort detected by master +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS _u(0x00010000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB _u(16) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB _u(16) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX +// Description : 1: When the processor side responds to a slave mode request for +// data to be transmitted to a remote master and user writes a 1 +// in CMD (bit 8) of IC_DATA_CMD register. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Slave-Transmitter +// 0x0 -> Slave trying to transmit to remote master in read mode- scenario not present +// 0x1 -> Slave trying to transmit to remote master in read mode +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB _u(15) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB _u(15) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST +// Description : This field indicates that a Slave has lost the bus while +// transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is +// set at the same time. Note: Even though the slave never 'owns' +// the bus, something could go wrong on the bus. This is a fail +// safe check. For instance, during a data transmission at the +// low-to-high transition of SCL, if what is on the data bus is +// not what is supposed to be transmitted, then DW_apb_i2c no +// longer own the bus. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Slave-Transmitter +// 0x0 -> Slave lost arbitration to remote master- scenario not present +// 0x1 -> Slave lost arbitration to remote master +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS _u(0x00004000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB _u(14) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB _u(14) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO +// Description : This field specifies that the Slave has received a read command +// and some data exists in the TX FIFO, so the slave issues a +// TX_ABRT interrupt to flush old data in TX FIFO. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Slave-Transmitter +// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read command- scenario not present +// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read command +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB _u(13) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ARB_LOST +// Description : This field specifies that the Master has lost arbitration, or +// if IC_TX_ABRT_SOURCE[14] is also set, then the slave +// transmitter has lost arbitration. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter +// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario not present +// 0x1 -> Master or Slave-Transmitter lost arbitration +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB _u(12) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB _u(12) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS +// Description : This field indicates that the User tries to initiate a Master +// operation with the Master mode disabled. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> User initiating master operation when MASTER disabled- scenario not present +// 0x1 -> User initiating master operation when MASTER disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB _u(11) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB _u(11) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT +// Description : This field indicates that the restart is disabled +// (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read +// command in 10-bit addressing mode. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Receiver +// 0x0 -> Master not trying to read in 10Bit addressing mode when RESTART disabled +// 0x1 -> Master trying to read in 10Bit addressing mode when RESTART disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB _u(10) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT +// Description : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be +// fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL +// bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must +// be cleared (IC_TAR[10]). Once the source of the +// ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in +// the same manner as other bits in this register. If the source +// of the ABRT_SBYTE_NORSTRT is not fixed before attempting to +// clear this bit, bit 9 clears for one cycle and then gets +// reasserted. When this field is set to 1, the restart is +// disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is +// trying to send a START Byte. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master +// 0x0 -> User trying to send START byte when RESTART disabled- scenario not present +// 0x1 -> User trying to send START byte when RESTART disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB _u(9) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB _u(9) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT +// Description : This field indicates that the restart is disabled +// (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to +// use the master to transfer data in High Speed mode. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> User trying to switch Master to HS mode when RESTART disabled- scenario not present +// 0x1 -> User trying to switch Master to HS mode when RESTART disabled +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB _u(8) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB _u(8) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET +// Description : This field indicates that the Master has sent a START Byte and +// the START Byte was acknowledged (wrong behavior). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master +// 0x0 -> ACK detected for START byte- scenario not present +// 0x1 -> ACK detected for START byte +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS _u(0x00000080) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB _u(7) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB _u(7) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET +// Description : This field indicates that the Master is in High Speed mode and +// the High Speed Master code was acknowledged (wrong behavior). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master +// 0x0 -> HS Master code ACKed in HS Mode- scenario not present +// 0x1 -> HS Master code ACKed in HS Mode +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS _u(0x00000040) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB _u(6) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB _u(6) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ +// Description : This field indicates that DW_apb_i2c in the master mode has +// sent a General Call but the user programmed the byte following +// the General Call to be a read from the bus (IC_DATA_CMD[9] is +// set to 1). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> GCALL is followed by read from bus-scenario not present +// 0x1 -> GCALL is followed by read from bus +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS _u(0x00000020) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB _u(5) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB _u(5) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK +// Description : This field indicates that DW_apb_i2c in master mode has sent a +// General Call and no slave on the bus acknowledged the General +// Call. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> GCALL not ACKed by any slave-scenario not present +// 0x1 -> GCALL not ACKed by any slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS _u(0x00000010) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB _u(4) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB _u(4) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK +// Description : This field indicates the master-mode only bit. When the master +// receives an acknowledgement for the address, but when it sends +// data byte(s) following the address, it did not receive an +// acknowledge from the remote slave(s). +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter +// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario not present +// 0x1 -> Transmitted data not ACKed by addressed slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB _u(3) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB _u(3) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK +// Description : This field indicates that the Master is in 10-bit address mode +// and that the second address byte of the 10-bit address was not +// acknowledged by any slave. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> This abort is not generated +// 0x1 -> Byte 2 of 10Bit Address not ACKed by any slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS _u(0x00000004) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB _u(2) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB _u(2) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK +// Description : This field indicates that the Master is in 10-bit address mode +// and the first 10-bit address byte was not acknowledged by any +// slave. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> This abort is not generated +// 0x1 -> Byte 1 of 10Bit Address not ACKed by any slave +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS _u(0x00000002) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB _u(1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB _u(1) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK +// Description : This field indicates that the Master is in 7-bit addressing +// mode and the address sent was not acknowledged by any slave. +// +// Reset value: 0x0 +// +// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver +// 0x0 -> This abort is not generated +// 0x1 -> This abort is generated because of NOACK for 7-bit address +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS _u(0x00000001) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB _u(0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB _u(0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS "RO" +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE _u(0x0) +#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE _u(0x1) +// ============================================================================= +// Register : I2C_IC_SLV_DATA_NACK_ONLY +// Description : Generate Slave Data NACK Register +// +// The register is used to generate a NACK for the data part of a +// transfer when DW_apb_i2c is acting as a slave-receiver. This +// register only exists when the IC_SLV_DATA_NACK_ONLY parameter +// is set to 1. When this parameter disabled, this register does +// not exist and writing to the register's address has no effect. +// +// A write can occur on this register if both of the following +// conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) +// - Slave part is inactive (IC_STATUS[6] = 0) Note: The +// IC_STATUS[6] is a register read-back location for the internal +// slv_activity signal; the user should poll this before writing +// the ic_slv_data_nack_only bit. +#define I2C_IC_SLV_DATA_NACK_ONLY_OFFSET _u(0x00000084) +#define I2C_IC_SLV_DATA_NACK_ONLY_BITS _u(0x00000001) +#define I2C_IC_SLV_DATA_NACK_ONLY_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SLV_DATA_NACK_ONLY_NACK +// Description : Generate NACK. This NACK generation only occurs when DW_apb_i2c +// is a slave-receiver. If this register is set to a value of 1, +// it can only generate a NACK after a data byte is received; +// hence, the data transfer is aborted and the data received is +// not pushed to the receive buffer. +// +// When the register is set to a value of 0, it generates +// NACK/ACK, depending on normal criteria. - 1: generate NACK +// after data byte received - 0: generate NACK/ACK normally Reset +// value: 0x0 +// 0x0 -> Slave receiver generates NACK normally +// 0x1 -> Slave receiver generates NACK upon data reception only +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET _u(0x0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS _u(0x00000001) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB _u(0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB _u(0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS "RW" +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED _u(0x0) +#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED _u(0x1) +// ============================================================================= +// Register : I2C_IC_DMA_CR +// Description : DMA Control Register +// +// The register is used to enable the DMA Controller interface +// operation. There is a separate bit for transmit and receive. +// This can be programmed regardless of the state of IC_ENABLE. +#define I2C_IC_DMA_CR_OFFSET _u(0x00000088) +#define I2C_IC_DMA_CR_BITS _u(0x00000003) +#define I2C_IC_DMA_CR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_CR_TDMAE +// Description : Transmit DMA Enable. This bit enables/disables the transmit +// FIFO DMA channel. Reset value: 0x0 +// 0x0 -> transmit FIFO DMA channel disabled +// 0x1 -> Transmit FIFO DMA channel enabled +#define I2C_IC_DMA_CR_TDMAE_RESET _u(0x0) +#define I2C_IC_DMA_CR_TDMAE_BITS _u(0x00000002) +#define I2C_IC_DMA_CR_TDMAE_MSB _u(1) +#define I2C_IC_DMA_CR_TDMAE_LSB _u(1) +#define I2C_IC_DMA_CR_TDMAE_ACCESS "RW" +#define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED _u(0x0) +#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_CR_RDMAE +// Description : Receive DMA Enable. This bit enables/disables the receive FIFO +// DMA channel. Reset value: 0x0 +// 0x0 -> Receive FIFO DMA channel disabled +// 0x1 -> Receive FIFO DMA channel enabled +#define I2C_IC_DMA_CR_RDMAE_RESET _u(0x0) +#define I2C_IC_DMA_CR_RDMAE_BITS _u(0x00000001) +#define I2C_IC_DMA_CR_RDMAE_MSB _u(0) +#define I2C_IC_DMA_CR_RDMAE_LSB _u(0) +#define I2C_IC_DMA_CR_RDMAE_ACCESS "RW" +#define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED _u(0x0) +#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED _u(0x1) +// ============================================================================= +// Register : I2C_IC_DMA_TDLR +// Description : DMA Transmit Data Level Register +#define I2C_IC_DMA_TDLR_OFFSET _u(0x0000008c) +#define I2C_IC_DMA_TDLR_BITS _u(0x0000000f) +#define I2C_IC_DMA_TDLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_TDLR_DMATDL +// Description : Transmit Data Level. This bit field controls the level at which +// a DMA request is made by the transmit logic. It is equal to the +// watermark level; that is, the dma_tx_req signal is generated +// when the number of valid data entries in the transmit FIFO is +// equal to or below this field value, and TDMAE = 1. +// +// Reset value: 0x0 +#define I2C_IC_DMA_TDLR_DMATDL_RESET _u(0x0) +#define I2C_IC_DMA_TDLR_DMATDL_BITS _u(0x0000000f) +#define I2C_IC_DMA_TDLR_DMATDL_MSB _u(3) +#define I2C_IC_DMA_TDLR_DMATDL_LSB _u(0) +#define I2C_IC_DMA_TDLR_DMATDL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_DMA_RDLR +// Description : I2C Receive Data Level Register +#define I2C_IC_DMA_RDLR_OFFSET _u(0x00000090) +#define I2C_IC_DMA_RDLR_BITS _u(0x0000000f) +#define I2C_IC_DMA_RDLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_DMA_RDLR_DMARDL +// Description : Receive Data Level. This bit field controls the level at which +// a DMA request is made by the receive logic. The watermark level +// = DMARDL+1; that is, dma_rx_req is generated when the number of +// valid data entries in the receive FIFO is equal to or more than +// this field value + 1, and RDMAE =1. For instance, when DMARDL +// is 0, then dma_rx_req is asserted when 1 or more data entries +// are present in the receive FIFO. +// +// Reset value: 0x0 +#define I2C_IC_DMA_RDLR_DMARDL_RESET _u(0x0) +#define I2C_IC_DMA_RDLR_DMARDL_BITS _u(0x0000000f) +#define I2C_IC_DMA_RDLR_DMARDL_MSB _u(3) +#define I2C_IC_DMA_RDLR_DMARDL_LSB _u(0) +#define I2C_IC_DMA_RDLR_DMARDL_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_SDA_SETUP +// Description : I2C SDA Setup Register +// +// This register controls the amount of time delay (in terms of +// number of ic_clk clock periods) introduced in the rising edge +// of SCL - relative to SDA changing - when DW_apb_i2c services a +// read request in a slave-transmitter operation. The relevant I2C +// requirement is tSU:DAT (note 4) as detailed in the I2C Bus +// Specification. This register must be programmed with a value +// equal to or greater than 2. +// +// Writes to this register succeed only when IC_ENABLE[0] = 0. +// +// Note: The length of setup time is calculated using +// [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires +// 10 ic_clk periods of setup time, they should program a value of +// 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c +// when operating as a slave transmitter. +#define I2C_IC_SDA_SETUP_OFFSET _u(0x00000094) +#define I2C_IC_SDA_SETUP_BITS _u(0x000000ff) +#define I2C_IC_SDA_SETUP_RESET _u(0x00000064) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_SDA_SETUP_SDA_SETUP +// Description : SDA Setup. It is recommended that if the required delay is +// 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP +// should be programmed to a value of 11. IC_SDA_SETUP must be +// programmed with a minimum value of 2. +#define I2C_IC_SDA_SETUP_SDA_SETUP_RESET _u(0x64) +#define I2C_IC_SDA_SETUP_SDA_SETUP_BITS _u(0x000000ff) +#define I2C_IC_SDA_SETUP_SDA_SETUP_MSB _u(7) +#define I2C_IC_SDA_SETUP_SDA_SETUP_LSB _u(0) +#define I2C_IC_SDA_SETUP_SDA_SETUP_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_ACK_GENERAL_CALL +// Description : I2C ACK General Call Register +// +// The register controls whether DW_apb_i2c responds with a ACK or +// NACK when it receives an I2C General Call address. +// +// This register is applicable only when the DW_apb_i2c is in +// slave mode. +#define I2C_IC_ACK_GENERAL_CALL_OFFSET _u(0x00000098) +#define I2C_IC_ACK_GENERAL_CALL_BITS _u(0x00000001) +#define I2C_IC_ACK_GENERAL_CALL_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL +// Description : ACK General Call. When set to 1, DW_apb_i2c responds with a ACK +// (by asserting ic_data_oe) when it receives a General Call. +// Otherwise, DW_apb_i2c responds with a NACK (by negating +// ic_data_oe). +// 0x0 -> Generate NACK for a General Call +// 0x1 -> Generate ACK for a General Call +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET _u(0x1) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS _u(0x00000001) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB _u(0) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB _u(0) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS "RW" +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED _u(0x0) +#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED _u(0x1) +// ============================================================================= +// Register : I2C_IC_ENABLE_STATUS +// Description : I2C Enable Status Register +// +// The register is used to report the DW_apb_i2c hardware status +// when the IC_ENABLE[0] register is set from 1 to 0; that is, +// when DW_apb_i2c is disabled. +// +// If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, +// and bit 0 is forced to 1. +// +// If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as +// soon as bit 0 is read as '0'. +// +// Note: When IC_ENABLE[0] has been set to 0, a delay occurs for +// bit 0 to be read as 0 because disabling the DW_apb_i2c depends +// on I2C bus activities. +#define I2C_IC_ENABLE_STATUS_OFFSET _u(0x0000009c) +#define I2C_IC_ENABLE_STATUS_BITS _u(0x00000007) +#define I2C_IC_ENABLE_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST +// Description : Slave Received Data Lost. This bit indicates if a Slave- +// Receiver operation has been aborted with at least one data byte +// received from an I2C transfer due to the setting bit 0 of +// IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to +// have been actively engaged in an aborted I2C transfer (with +// matching address) and the data phase of the I2C transfer has +// been entered, even though a data byte has been responded with a +// NACK. +// +// Note: If the remote I2C master terminates the transfer with a +// STOP condition before the DW_apb_i2c has a chance to NACK a +// transfer, and IC_ENABLE[0] has been set to 0, then this bit is +// also set to 1. +// +// When read as 0, DW_apb_i2c is deemed to have been disabled +// without being actively involved in the data phase of a Slave- +// Receiver transfer. +// +// Note: The CPU can safely read this bit when IC_EN (bit 0) is +// read as 0. +// +// Reset value: 0x0 +// 0x0 -> Slave RX Data is not lost +// 0x1 -> Slave RX Data is lost +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS _u(0x00000004) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB _u(2) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB _u(2) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY +// Description : Slave Disabled While Busy (Transmit, Receive). This bit +// indicates if a potential or active Slave operation has been +// aborted due to the setting bit 0 of the IC_ENABLE register from +// 1 to 0. This bit is set when the CPU writes a 0 to the +// IC_ENABLE register while: +// +// (a) DW_apb_i2c is receiving the address byte of the Slave- +// Transmitter operation from a remote master; +// +// OR, +// +// (b) address and data bytes of the Slave-Receiver operation from +// a remote master. +// +// When read as 1, DW_apb_i2c is deemed to have forced a NACK +// during any part of an I2C transfer, irrespective of whether the +// I2C address matches the slave address set in DW_apb_i2c (IC_SAR +// register) OR if the transfer is completed before IC_ENABLE is +// set to 0 but has not taken effect. +// +// Note: If the remote I2C master terminates the transfer with a +// STOP condition before the DW_apb_i2c has a chance to NACK a +// transfer, and IC_ENABLE[0] has been set to 0, then this bit +// will also be set to 1. +// +// When read as 0, DW_apb_i2c is deemed to have been disabled when +// there is master activity, or when the I2C bus is idle. +// +// Note: The CPU can safely read this bit when IC_EN (bit 0) is +// read as 0. +// +// Reset value: 0x0 +// 0x0 -> Slave is disabled when it is idle +// 0x1 -> Slave is disabled when it is active +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS _u(0x00000002) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB _u(1) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB _u(1) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE _u(0x0) +#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_ENABLE_STATUS_IC_EN +// Description : ic_en Status. This bit always reflects the value driven on the +// output port ic_en. - When read as 1, DW_apb_i2c is deemed to be +// in an enabled state. - When read as 0, DW_apb_i2c is deemed +// completely inactive. Note: The CPU can safely read this bit +// anytime. When this bit is read as 0, the CPU can safely read +// SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). +// +// Reset value: 0x0 +// 0x0 -> I2C disabled +// 0x1 -> I2C enabled +#define I2C_IC_ENABLE_STATUS_IC_EN_RESET _u(0x0) +#define I2C_IC_ENABLE_STATUS_IC_EN_BITS _u(0x00000001) +#define I2C_IC_ENABLE_STATUS_IC_EN_MSB _u(0) +#define I2C_IC_ENABLE_STATUS_IC_EN_LSB _u(0) +#define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS "RO" +#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED _u(0x0) +#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED _u(0x1) +// ============================================================================= +// Register : I2C_IC_FS_SPKLEN +// Description : I2C SS, FS or FM+ spike suppression limit +// +// This register is used to store the duration, measured in ic_clk +// cycles, of the longest spike that is filtered out by the spike +// suppression logic when the component is operating in SS, FS or +// FM+ modes. The relevant I2C requirement is tSP (table 4) as +// detailed in the I2C Bus Specification. This register must be +// programmed with a minimum value of 1. +#define I2C_IC_FS_SPKLEN_OFFSET _u(0x000000a0) +#define I2C_IC_FS_SPKLEN_BITS _u(0x000000ff) +#define I2C_IC_FS_SPKLEN_RESET _u(0x00000007) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_FS_SPKLEN_IC_FS_SPKLEN +// Description : This register must be set before any I2C bus transaction can +// take place to ensure stable operation. This register sets the +// duration, measured in ic_clk cycles, of the longest spike in +// the SCL or SDA lines that will be filtered out by the spike +// suppression logic. This register can be written only when the +// I2C interface is disabled which corresponds to the IC_ENABLE[0] +// register being set to 0. Writes at other times have no effect. +// The minimum valid value is 1; hardware prevents values less +// than this being written, and if attempted results in 1 being +// set. or more information, refer to 'Spike Suppression'. +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET _u(0x07) +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_BITS _u(0x000000ff) +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB _u(7) +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB _u(0) +#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_ACCESS "RW" +// ============================================================================= +// Register : I2C_IC_CLR_RESTART_DET +// Description : Clear RESTART_DET Interrupt Register +#define I2C_IC_CLR_RESTART_DET_OFFSET _u(0x000000a8) +#define I2C_IC_CLR_RESTART_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_RESTART_DET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET +// Description : Read this register to clear the RESTART_DET interrupt (bit 12) +// of IC_RAW_INTR_STAT register. +// +// Reset value: 0x0 +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET _u(0x0) +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_BITS _u(0x00000001) +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB _u(0) +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB _u(0) +#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_COMP_PARAM_1 +// Description : Component Parameter Register 1 +// +// Note This register is not implemented and therefore reads as 0. +// If it was implemented it would be a constant read-only register +// that contains encoded information about the component's +// parameter settings. Fields shown below are the settings for +// those parameters +#define I2C_IC_COMP_PARAM_1_OFFSET _u(0x000000f4) +#define I2C_IC_COMP_PARAM_1_BITS _u(0x00ffffff) +#define I2C_IC_COMP_PARAM_1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH +// Description : TX Buffer Depth = 16 +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET _u(0x00) +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_BITS _u(0x00ff0000) +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB _u(23) +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB _u(16) +#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH +// Description : RX Buffer Depth = 16 +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET _u(0x00) +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_BITS _u(0x0000ff00) +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB _u(15) +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB _u(8) +#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS +// Description : Encoded parameters not visible +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_BITS _u(0x00000080) +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB _u(7) +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB _u(7) +#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_HAS_DMA +// Description : DMA handshaking signals are enabled +#define I2C_IC_COMP_PARAM_1_HAS_DMA_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_HAS_DMA_BITS _u(0x00000040) +#define I2C_IC_COMP_PARAM_1_HAS_DMA_MSB _u(6) +#define I2C_IC_COMP_PARAM_1_HAS_DMA_LSB _u(6) +#define I2C_IC_COMP_PARAM_1_HAS_DMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_INTR_IO +// Description : COMBINED Interrupt outputs +#define I2C_IC_COMP_PARAM_1_INTR_IO_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_INTR_IO_BITS _u(0x00000020) +#define I2C_IC_COMP_PARAM_1_INTR_IO_MSB _u(5) +#define I2C_IC_COMP_PARAM_1_INTR_IO_LSB _u(5) +#define I2C_IC_COMP_PARAM_1_INTR_IO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES +// Description : Programmable count values for each mode. +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_BITS _u(0x00000010) +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB _u(4) +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB _u(4) +#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE +// Description : MAX SPEED MODE = FAST MODE +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_BITS _u(0x0000000c) +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB _u(3) +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB _u(2) +#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH +// Description : APB data bus width is 32 bits +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET _u(0x0) +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_BITS _u(0x00000003) +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB _u(1) +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB _u(0) +#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_COMP_VERSION +// Description : I2C Component Version Register +#define I2C_IC_COMP_VERSION_OFFSET _u(0x000000f8) +#define I2C_IC_COMP_VERSION_BITS _u(0xffffffff) +#define I2C_IC_COMP_VERSION_RESET _u(0x3230312a) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_VERSION_IC_COMP_VERSION +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET _u(0x3230312a) +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS _u(0xffffffff) +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB _u(31) +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB _u(0) +#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_ACCESS "RO" +// ============================================================================= +// Register : I2C_IC_COMP_TYPE +// Description : I2C Component Type Register +#define I2C_IC_COMP_TYPE_OFFSET _u(0x000000fc) +#define I2C_IC_COMP_TYPE_BITS _u(0xffffffff) +#define I2C_IC_COMP_TYPE_RESET _u(0x44570140) +// ----------------------------------------------------------------------------- +// Field : I2C_IC_COMP_TYPE_IC_COMP_TYPE +// Description : Designware Component Type number = 0x44_57_01_40. This assigned +// unique hex value is constant and is derived from the two ASCII +// letters 'DW' followed by a 16-bit unsigned number. +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET _u(0x44570140) +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_BITS _u(0xffffffff) +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB _u(31) +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB _u(0) +#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_I2C_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/intctrl.h b/lib/pico-sdk/rp2350/hardware/regs/intctrl.h new file mode 100644 index 000000000000..96ce815e4717 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/intctrl.h @@ -0,0 +1,184 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _INTCTRL_H +#define _INTCTRL_H + +/** + * \file rp2350/intctrl.h + */ + +#ifdef __ASSEMBLER__ +#define TIMER0_IRQ_0 0 +#define TIMER0_IRQ_1 1 +#define TIMER0_IRQ_2 2 +#define TIMER0_IRQ_3 3 +#define TIMER1_IRQ_0 4 +#define TIMER1_IRQ_1 5 +#define TIMER1_IRQ_2 6 +#define TIMER1_IRQ_3 7 +#define PWM_IRQ_WRAP_0 8 +#define PWM_IRQ_WRAP_1 9 +#define DMA_IRQ_0 10 +#define DMA_IRQ_1 11 +#define DMA_IRQ_2 12 +#define DMA_IRQ_3 13 +#define USBCTRL_IRQ 14 +#define PIO0_IRQ_0 15 +#define PIO0_IRQ_1 16 +#define PIO1_IRQ_0 17 +#define PIO1_IRQ_1 18 +#define PIO2_IRQ_0 19 +#define PIO2_IRQ_1 20 +#define IO_IRQ_BANK0 21 +#define IO_IRQ_BANK0_NS 22 +#define IO_IRQ_QSPI 23 +#define IO_IRQ_QSPI_NS 24 +#define SIO_IRQ_FIFO 25 +#define SIO_IRQ_BELL 26 +#define SIO_IRQ_FIFO_NS 27 +#define SIO_IRQ_BELL_NS 28 +#define SIO_IRQ_MTIMECMP 29 +#define CLOCKS_IRQ 30 +#define SPI0_IRQ 31 +#define SPI1_IRQ 32 +#define UART0_IRQ 33 +#define UART1_IRQ 34 +#define ADC_IRQ_FIFO 35 +#define I2C0_IRQ 36 +#define I2C1_IRQ 37 +#define OTP_IRQ 38 +#define TRNG_IRQ 39 +#define PROC0_IRQ_CTI 40 +#define PROC1_IRQ_CTI 41 +#define PLL_SYS_IRQ 42 +#define PLL_USB_IRQ 43 +#define POWMAN_IRQ_POW 44 +#define POWMAN_IRQ_TIMER 45 +#define SPAREIRQ_IRQ_0 46 +#define SPAREIRQ_IRQ_1 47 +#define SPAREIRQ_IRQ_2 48 +#define SPAREIRQ_IRQ_3 49 +#define SPAREIRQ_IRQ_4 50 +#define SPAREIRQ_IRQ_5 51 +#else +/** + * \brief Interrupt numbers on RP2350 (used as typedef \ref irq_num_t) + * \ingroup hardware_irq + */ +typedef enum irq_num_rp2350 { + TIMER0_IRQ_0 = 0, ///< Select TIMER0's IRQ 0 output + TIMER0_IRQ_1 = 1, ///< Select TIMER0's IRQ 1 output + TIMER0_IRQ_2 = 2, ///< Select TIMER0's IRQ 2 output + TIMER0_IRQ_3 = 3, ///< Select TIMER0's IRQ 3 output + TIMER1_IRQ_0 = 4, ///< Select TIMER1's IRQ 0 output + TIMER1_IRQ_1 = 5, ///< Select TIMER1's IRQ 1 output + TIMER1_IRQ_2 = 6, ///< Select TIMER1's IRQ 2 output + TIMER1_IRQ_3 = 7, ///< Select TIMER1's IRQ 3 output + PWM_IRQ_WRAP_0 = 8, ///< Select PWM's IRQ_WRAP 0 output + PWM_IRQ_WRAP_1 = 9, ///< Select PWM's IRQ_WRAP 1 output + DMA_IRQ_0 = 10, ///< Select DMA's IRQ 0 output + DMA_IRQ_1 = 11, ///< Select DMA's IRQ 1 output + DMA_IRQ_2 = 12, ///< Select DMA's IRQ 2 output + DMA_IRQ_3 = 13, ///< Select DMA's IRQ 3 output + USBCTRL_IRQ = 14, ///< Select USBCTRL's IRQ output + PIO0_IRQ_0 = 15, ///< Select PIO0's IRQ 0 output + PIO0_IRQ_1 = 16, ///< Select PIO0's IRQ 1 output + PIO1_IRQ_0 = 17, ///< Select PIO1's IRQ 0 output + PIO1_IRQ_1 = 18, ///< Select PIO1's IRQ 1 output + PIO2_IRQ_0 = 19, ///< Select PIO2's IRQ 0 output + PIO2_IRQ_1 = 20, ///< Select PIO2's IRQ 1 output + IO_IRQ_BANK0 = 21, ///< Select IO_BANK0's IRQ output + IO_IRQ_BANK0_NS = 22, ///< Select IO_BANK0_NS's IRQ output + IO_IRQ_QSPI = 23, ///< Select IO_QSPI's IRQ output + IO_IRQ_QSPI_NS = 24, ///< Select IO_QSPI_NS's IRQ output + SIO_IRQ_FIFO = 25, ///< Select SIO's IRQ_FIFO output + SIO_IRQ_BELL = 26, ///< Select SIO's IRQ_BELL output + SIO_IRQ_FIFO_NS = 27, ///< Select SIO_NS's IRQ_FIFO output + SIO_IRQ_BELL_NS = 28, ///< Select SIO_NS's IRQ_BELL output + SIO_IRQ_MTIMECMP = 29, ///< Select SIO_IRQ_MTIMECMP's IRQ output + CLOCKS_IRQ = 30, ///< Select CLOCKS's IRQ output + SPI0_IRQ = 31, ///< Select SPI0's IRQ output + SPI1_IRQ = 32, ///< Select SPI1's IRQ output + UART0_IRQ = 33, ///< Select UART0's IRQ output + UART1_IRQ = 34, ///< Select UART1's IRQ output + ADC_IRQ_FIFO = 35, ///< Select ADC's IRQ_FIFO output + I2C0_IRQ = 36, ///< Select I2C0's IRQ output + I2C1_IRQ = 37, ///< Select I2C1's IRQ output + OTP_IRQ = 38, ///< Select OTP's IRQ output + TRNG_IRQ = 39, ///< Select TRNG's IRQ output + PROC0_IRQ_CTI = 40, ///< Select PROC0's IRQ_CTI output + PROC1_IRQ_CTI = 41, ///< Select PROC1's IRQ_CTI output + PLL_SYS_IRQ = 42, ///< Select PLL_SYS's IRQ output + PLL_USB_IRQ = 43, ///< Select PLL_USB's IRQ output + POWMAN_IRQ_POW = 44, ///< Select POWMAN's IRQ_POW output + POWMAN_IRQ_TIMER = 45, ///< Select POWMAN's IRQ_TIMER output + SPARE_IRQ_0 = 46, ///< Select SPARE IRQ 0 + SPARE_IRQ_1 = 47, ///< Select SPARE IRQ 1 + SPARE_IRQ_2 = 48, ///< Select SPARE IRQ 2 + SPARE_IRQ_3 = 49, ///< Select SPARE IRQ 3 + SPARE_IRQ_4 = 50, ///< Select SPARE IRQ 4 + SPARE_IRQ_5 = 51, ///< Select SPARE IRQ 5 + IRQ_COUNT +} irq_num_t; +#endif + +#define isr_timer0_0 isr_irq0 +#define isr_timer0_1 isr_irq1 +#define isr_timer0_2 isr_irq2 +#define isr_timer0_3 isr_irq3 +#define isr_timer1_0 isr_irq4 +#define isr_timer1_1 isr_irq5 +#define isr_timer1_2 isr_irq6 +#define isr_timer1_3 isr_irq7 +#define isr_pwm_wrap_0 isr_irq8 +#define isr_pwm_wrap_1 isr_irq9 +#define isr_dma_0 isr_irq10 +#define isr_dma_1 isr_irq11 +#define isr_dma_2 isr_irq12 +#define isr_dma_3 isr_irq13 +#define isr_usbctrl isr_irq14 +#define isr_pio0_0 isr_irq15 +#define isr_pio0_1 isr_irq16 +#define isr_pio1_0 isr_irq17 +#define isr_pio1_1 isr_irq18 +#define isr_pio2_0 isr_irq19 +#define isr_pio2_1 isr_irq20 +#define isr_io_bank0 isr_irq21 +#define isr_io_bank0_ns isr_irq22 +#define isr_io_qspi isr_irq23 +#define isr_io_qspi_ns isr_irq24 +#define isr_sio_fifo isr_irq25 +#define isr_sio_bell isr_irq26 +#define isr_sio_fifo_ns isr_irq27 +#define isr_sio_bell_ns isr_irq28 +#define isr_sio_mtimecmp isr_irq29 +#define isr_clocks isr_irq30 +#define isr_spi0 isr_irq31 +#define isr_spi1 isr_irq32 +#define isr_uart0 isr_irq33 +#define isr_uart1 isr_irq34 +#define isr_adc_fifo isr_irq35 +#define isr_i2c0 isr_irq36 +#define isr_i2c1 isr_irq37 +#define isr_otp isr_irq38 +#define isr_trng isr_irq39 +#define isr_proc0_cti isr_irq40 +#define isr_proc1_cti isr_irq41 +#define isr_pll_sys isr_irq42 +#define isr_pll_usb isr_irq43 +#define isr_powman_pow isr_irq44 +#define isr_powman_timer isr_irq45 +#define isr_spare_0 isr_irq46 +#define isr_spare_1 isr_irq47 +#define isr_spare_2 isr_irq48 +#define isr_spare_3 isr_irq49 +#define isr_spare_4 isr_irq50 +#define isr_spare_5 isr_irq51 + +#endif // _INTCTRL_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/io_bank0.h b/lib/pico-sdk/rp2350/hardware/regs/io_bank0.h new file mode 100644 index 000000000000..6c2f96ecb5d1 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/io_bank0.h @@ -0,0 +1,22339 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : IO_BANK0 +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_IO_BANK0_H +#define _HARDWARE_REGS_IO_BANK0_H +// ============================================================================= +// Register : IO_BANK0_GPIO0_STATUS +#define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000) +#define IO_BANK0_GPIO0_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO0_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO0_CTRL +#define IO_BANK0_GPIO0_CTRL_OFFSET _u(0x00000004) +#define IO_BANK0_GPIO0_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO0_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO0_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tck +// 0x01 -> spi0_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_0 +// 0x05 -> siob_proc_0 +// 0x06 -> pio0_0 +// 0x07 -> pio1_0 +// 0x08 -> pio2_0 +// 0x09 -> xip_ss_n_1 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIOB_PROC_0 _u(0x05) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO2_0 _u(0x08) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO1_STATUS +#define IO_BANK0_GPIO1_STATUS_OFFSET _u(0x00000008) +#define IO_BANK0_GPIO1_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO1_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO1_CTRL +#define IO_BANK0_GPIO1_CTRL_OFFSET _u(0x0000000c) +#define IO_BANK0_GPIO1_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO1_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO1_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tms +// 0x01 -> spi0_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_0 +// 0x05 -> siob_proc_1 +// 0x06 -> pio0_1 +// 0x07 -> pio1_1 +// 0x08 -> pio2_1 +// 0x09 -> coresight_traceclk +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIOB_PROC_1 _u(0x05) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO2_1 _u(0x08) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACECLK _u(0x09) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO2_STATUS +#define IO_BANK0_GPIO2_STATUS_OFFSET _u(0x00000010) +#define IO_BANK0_GPIO2_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO2_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO2_CTRL +#define IO_BANK0_GPIO2_CTRL_OFFSET _u(0x00000014) +#define IO_BANK0_GPIO2_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO2_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO2_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tdi +// 0x01 -> spi0_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_1 +// 0x05 -> siob_proc_2 +// 0x06 -> pio0_2 +// 0x07 -> pio1_2 +// 0x08 -> pio2_2 +// 0x09 -> coresight_tracedata_0 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart0_tx +// 0x1f -> null +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIOB_PROC_2 _u(0x05) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO2_2 _u(0x08) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_0 _u(0x09) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) +#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO3_STATUS +#define IO_BANK0_GPIO3_STATUS_OFFSET _u(0x00000018) +#define IO_BANK0_GPIO3_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO3_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO3_CTRL +#define IO_BANK0_GPIO3_CTRL_OFFSET _u(0x0000001c) +#define IO_BANK0_GPIO3_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO3_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO3_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> jtag_tdo +// 0x01 -> spi0_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_1 +// 0x05 -> siob_proc_3 +// 0x06 -> pio0_3 +// 0x07 -> pio1_3 +// 0x08 -> pio2_3 +// 0x09 -> coresight_tracedata_1 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart0_rx +// 0x1f -> null +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIOB_PROC_3 _u(0x05) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO2_3 _u(0x08) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_1 _u(0x09) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) +#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO4_STATUS +#define IO_BANK0_GPIO4_STATUS_OFFSET _u(0x00000020) +#define IO_BANK0_GPIO4_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO4_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO4_CTRL +#define IO_BANK0_GPIO4_CTRL_OFFSET _u(0x00000024) +#define IO_BANK0_GPIO4_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO4_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO4_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_2 +// 0x05 -> siob_proc_4 +// 0x06 -> pio0_4 +// 0x07 -> pio1_4 +// 0x08 -> pio2_4 +// 0x09 -> coresight_tracedata_2 +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIOB_PROC_4 _u(0x05) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO2_4 _u(0x08) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_2 _u(0x09) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO5_STATUS +#define IO_BANK0_GPIO5_STATUS_OFFSET _u(0x00000028) +#define IO_BANK0_GPIO5_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO5_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO5_CTRL +#define IO_BANK0_GPIO5_CTRL_OFFSET _u(0x0000002c) +#define IO_BANK0_GPIO5_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO5_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO5_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_2 +// 0x05 -> siob_proc_5 +// 0x06 -> pio0_5 +// 0x07 -> pio1_5 +// 0x08 -> pio2_5 +// 0x09 -> coresight_tracedata_3 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIOB_PROC_5 _u(0x05) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO2_5 _u(0x08) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_3 _u(0x09) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO6_STATUS +#define IO_BANK0_GPIO6_STATUS_OFFSET _u(0x00000030) +#define IO_BANK0_GPIO6_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO6_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO6_CTRL +#define IO_BANK0_GPIO6_CTRL_OFFSET _u(0x00000034) +#define IO_BANK0_GPIO6_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO6_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO6_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_3 +// 0x05 -> siob_proc_6 +// 0x06 -> pio0_6 +// 0x07 -> pio1_6 +// 0x08 -> pio2_6 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart1_tx +// 0x1f -> null +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIOB_PROC_6 _u(0x05) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO2_6 _u(0x08) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) +#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO7_STATUS +#define IO_BANK0_GPIO7_STATUS_OFFSET _u(0x00000038) +#define IO_BANK0_GPIO7_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO7_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO7_CTRL +#define IO_BANK0_GPIO7_CTRL_OFFSET _u(0x0000003c) +#define IO_BANK0_GPIO7_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO7_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO7_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_3 +// 0x05 -> siob_proc_7 +// 0x06 -> pio0_7 +// 0x07 -> pio1_7 +// 0x08 -> pio2_7 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart1_rx +// 0x1f -> null +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIOB_PROC_7 _u(0x05) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO2_7 _u(0x08) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) +#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO8_STATUS +#define IO_BANK0_GPIO8_STATUS_OFFSET _u(0x00000040) +#define IO_BANK0_GPIO8_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO8_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO8_CTRL +#define IO_BANK0_GPIO8_CTRL_OFFSET _u(0x00000044) +#define IO_BANK0_GPIO8_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO8_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO8_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_4 +// 0x05 -> siob_proc_8 +// 0x06 -> pio0_8 +// 0x07 -> pio1_8 +// 0x08 -> pio2_8 +// 0x09 -> xip_ss_n_1 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIOB_PROC_8 _u(0x05) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO2_8 _u(0x08) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO9_STATUS +#define IO_BANK0_GPIO9_STATUS_OFFSET _u(0x00000048) +#define IO_BANK0_GPIO9_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO9_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO9_CTRL +#define IO_BANK0_GPIO9_CTRL_OFFSET _u(0x0000004c) +#define IO_BANK0_GPIO9_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO9_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO9_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_4 +// 0x05 -> siob_proc_9 +// 0x06 -> pio0_9 +// 0x07 -> pio1_9 +// 0x08 -> pio2_9 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIOB_PROC_9 _u(0x05) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO2_9 _u(0x08) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO10_STATUS +#define IO_BANK0_GPIO10_STATUS_OFFSET _u(0x00000050) +#define IO_BANK0_GPIO10_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO10_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO10_CTRL +#define IO_BANK0_GPIO10_CTRL_OFFSET _u(0x00000054) +#define IO_BANK0_GPIO10_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO10_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO10_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_5 +// 0x05 -> siob_proc_10 +// 0x06 -> pio0_10 +// 0x07 -> pio1_10 +// 0x08 -> pio2_10 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart1_tx +// 0x1f -> null +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIOB_PROC_10 _u(0x05) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO2_10 _u(0x08) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) +#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO11_STATUS +#define IO_BANK0_GPIO11_STATUS_OFFSET _u(0x00000058) +#define IO_BANK0_GPIO11_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO11_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO11_CTRL +#define IO_BANK0_GPIO11_CTRL_OFFSET _u(0x0000005c) +#define IO_BANK0_GPIO11_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO11_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO11_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_5 +// 0x05 -> siob_proc_11 +// 0x06 -> pio0_11 +// 0x07 -> pio1_11 +// 0x08 -> pio2_11 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart1_rx +// 0x1f -> null +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIOB_PROC_11 _u(0x05) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO2_11 _u(0x08) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) +#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO12_STATUS +#define IO_BANK0_GPIO12_STATUS_OFFSET _u(0x00000060) +#define IO_BANK0_GPIO12_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO12_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO12_CTRL +#define IO_BANK0_GPIO12_CTRL_OFFSET _u(0x00000064) +#define IO_BANK0_GPIO12_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO12_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO12_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_0 +// 0x01 -> spi1_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_6 +// 0x05 -> siob_proc_12 +// 0x06 -> pio0_12 +// 0x07 -> pio1_12 +// 0x08 -> pio2_12 +// 0x09 -> clocks_gpin_0 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_HSTX_0 _u(0x00) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIOB_PROC_12 _u(0x05) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO2_12 _u(0x08) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x09) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO13_STATUS +#define IO_BANK0_GPIO13_STATUS_OFFSET _u(0x00000068) +#define IO_BANK0_GPIO13_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO13_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO13_CTRL +#define IO_BANK0_GPIO13_CTRL_OFFSET _u(0x0000006c) +#define IO_BANK0_GPIO13_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO13_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO13_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_1 +// 0x01 -> spi1_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_6 +// 0x05 -> siob_proc_13 +// 0x06 -> pio0_13 +// 0x07 -> pio1_13 +// 0x08 -> pio2_13 +// 0x09 -> clocks_gpout_0 +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_HSTX_1 _u(0x00) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIOB_PROC_13 _u(0x05) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO2_13 _u(0x08) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x09) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO14_STATUS +#define IO_BANK0_GPIO14_STATUS_OFFSET _u(0x00000070) +#define IO_BANK0_GPIO14_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO14_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO14_CTRL +#define IO_BANK0_GPIO14_CTRL_OFFSET _u(0x00000074) +#define IO_BANK0_GPIO14_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO14_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO14_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_2 +// 0x01 -> spi1_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_7 +// 0x05 -> siob_proc_14 +// 0x06 -> pio0_14 +// 0x07 -> pio1_14 +// 0x08 -> pio2_14 +// 0x09 -> clocks_gpin_1 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart0_tx +// 0x1f -> null +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_HSTX_2 _u(0x00) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIOB_PROC_14 _u(0x05) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO2_14 _u(0x08) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x09) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) +#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO15_STATUS +#define IO_BANK0_GPIO15_STATUS_OFFSET _u(0x00000078) +#define IO_BANK0_GPIO15_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO15_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO15_CTRL +#define IO_BANK0_GPIO15_CTRL_OFFSET _u(0x0000007c) +#define IO_BANK0_GPIO15_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO15_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO15_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_3 +// 0x01 -> spi1_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_7 +// 0x05 -> siob_proc_15 +// 0x06 -> pio0_15 +// 0x07 -> pio1_15 +// 0x08 -> pio2_15 +// 0x09 -> clocks_gpout_1 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart0_rx +// 0x1f -> null +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_HSTX_3 _u(0x00) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIOB_PROC_15 _u(0x05) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO2_15 _u(0x08) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x09) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) +#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO16_STATUS +#define IO_BANK0_GPIO16_STATUS_OFFSET _u(0x00000080) +#define IO_BANK0_GPIO16_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO16_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO16_CTRL +#define IO_BANK0_GPIO16_CTRL_OFFSET _u(0x00000084) +#define IO_BANK0_GPIO16_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO16_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO16_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_4 +// 0x01 -> spi0_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_0 +// 0x05 -> siob_proc_16 +// 0x06 -> pio0_16 +// 0x07 -> pio1_16 +// 0x08 -> pio2_16 +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_HSTX_4 _u(0x00) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIOB_PROC_16 _u(0x05) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO2_16 _u(0x08) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO17_STATUS +#define IO_BANK0_GPIO17_STATUS_OFFSET _u(0x00000088) +#define IO_BANK0_GPIO17_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO17_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO17_CTRL +#define IO_BANK0_GPIO17_CTRL_OFFSET _u(0x0000008c) +#define IO_BANK0_GPIO17_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO17_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO17_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_5 +// 0x01 -> spi0_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_0 +// 0x05 -> siob_proc_17 +// 0x06 -> pio0_17 +// 0x07 -> pio1_17 +// 0x08 -> pio2_17 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_HSTX_5 _u(0x00) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIOB_PROC_17 _u(0x05) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO2_17 _u(0x08) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO18_STATUS +#define IO_BANK0_GPIO18_STATUS_OFFSET _u(0x00000090) +#define IO_BANK0_GPIO18_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO18_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO18_CTRL +#define IO_BANK0_GPIO18_CTRL_OFFSET _u(0x00000094) +#define IO_BANK0_GPIO18_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO18_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO18_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_6 +// 0x01 -> spi0_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_1 +// 0x05 -> siob_proc_18 +// 0x06 -> pio0_18 +// 0x07 -> pio1_18 +// 0x08 -> pio2_18 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart0_tx +// 0x1f -> null +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_HSTX_6 _u(0x00) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIOB_PROC_18 _u(0x05) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO2_18 _u(0x08) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) +#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO19_STATUS +#define IO_BANK0_GPIO19_STATUS_OFFSET _u(0x00000098) +#define IO_BANK0_GPIO19_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO19_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO19_CTRL +#define IO_BANK0_GPIO19_CTRL_OFFSET _u(0x0000009c) +#define IO_BANK0_GPIO19_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO19_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO19_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> hstx_7 +// 0x01 -> spi0_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_1 +// 0x05 -> siob_proc_19 +// 0x06 -> pio0_19 +// 0x07 -> pio1_19 +// 0x08 -> pio2_19 +// 0x09 -> xip_ss_n_1 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart0_rx +// 0x1f -> null +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_HSTX_7 _u(0x00) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIOB_PROC_19 _u(0x05) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO2_19 _u(0x08) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) +#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO20_STATUS +#define IO_BANK0_GPIO20_STATUS_OFFSET _u(0x000000a0) +#define IO_BANK0_GPIO20_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO20_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO20_CTRL +#define IO_BANK0_GPIO20_CTRL_OFFSET _u(0x000000a4) +#define IO_BANK0_GPIO20_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO20_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO20_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_2 +// 0x05 -> siob_proc_20 +// 0x06 -> pio0_20 +// 0x07 -> pio1_20 +// 0x08 -> pio2_20 +// 0x09 -> clocks_gpin_0 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIOB_PROC_20 _u(0x05) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO2_20 _u(0x08) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x09) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO21_STATUS +#define IO_BANK0_GPIO21_STATUS_OFFSET _u(0x000000a8) +#define IO_BANK0_GPIO21_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO21_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO21_CTRL +#define IO_BANK0_GPIO21_CTRL_OFFSET _u(0x000000ac) +#define IO_BANK0_GPIO21_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO21_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO21_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_2 +// 0x05 -> siob_proc_21 +// 0x06 -> pio0_21 +// 0x07 -> pio1_21 +// 0x08 -> pio2_21 +// 0x09 -> clocks_gpout_0 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIOB_PROC_21 _u(0x05) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO2_21 _u(0x08) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x09) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO22_STATUS +#define IO_BANK0_GPIO22_STATUS_OFFSET _u(0x000000b0) +#define IO_BANK0_GPIO22_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO22_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO22_CTRL +#define IO_BANK0_GPIO22_CTRL_OFFSET _u(0x000000b4) +#define IO_BANK0_GPIO22_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO22_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO22_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_3 +// 0x05 -> siob_proc_22 +// 0x06 -> pio0_22 +// 0x07 -> pio1_22 +// 0x08 -> pio2_22 +// 0x09 -> clocks_gpin_1 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart1_tx +// 0x1f -> null +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIOB_PROC_22 _u(0x05) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO2_22 _u(0x08) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x09) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) +#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO23_STATUS +#define IO_BANK0_GPIO23_STATUS_OFFSET _u(0x000000b8) +#define IO_BANK0_GPIO23_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO23_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO23_CTRL +#define IO_BANK0_GPIO23_CTRL_OFFSET _u(0x000000bc) +#define IO_BANK0_GPIO23_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO23_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO23_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_3 +// 0x05 -> siob_proc_23 +// 0x06 -> pio0_23 +// 0x07 -> pio1_23 +// 0x08 -> pio2_23 +// 0x09 -> clocks_gpout_1 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart1_rx +// 0x1f -> null +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIOB_PROC_23 _u(0x05) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO2_23 _u(0x08) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x09) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) +#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO24_STATUS +#define IO_BANK0_GPIO24_STATUS_OFFSET _u(0x000000c0) +#define IO_BANK0_GPIO24_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO24_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO24_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO24_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO24_CTRL +#define IO_BANK0_GPIO24_CTRL_OFFSET _u(0x000000c4) +#define IO_BANK0_GPIO24_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO24_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO24_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO24_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO24_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO24_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_4 +// 0x05 -> siob_proc_24 +// 0x06 -> pio0_24 +// 0x07 -> pio1_24 +// 0x08 -> pio2_24 +// 0x09 -> clocks_gpout_2 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIOB_PROC_24 _u(0x05) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO2_24 _u(0x08) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _u(0x09) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO25_STATUS +#define IO_BANK0_GPIO25_STATUS_OFFSET _u(0x000000c8) +#define IO_BANK0_GPIO25_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO25_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO25_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO25_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO25_CTRL +#define IO_BANK0_GPIO25_CTRL_OFFSET _u(0x000000cc) +#define IO_BANK0_GPIO25_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO25_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO25_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO25_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO25_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO25_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_4 +// 0x05 -> siob_proc_25 +// 0x06 -> pio0_25 +// 0x07 -> pio1_25 +// 0x08 -> pio2_25 +// 0x09 -> clocks_gpout_3 +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIOB_PROC_25 _u(0x05) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO2_25 _u(0x08) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _u(0x09) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO26_STATUS +#define IO_BANK0_GPIO26_STATUS_OFFSET _u(0x000000d0) +#define IO_BANK0_GPIO26_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO26_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO26_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO26_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO26_CTRL +#define IO_BANK0_GPIO26_CTRL_OFFSET _u(0x000000d4) +#define IO_BANK0_GPIO26_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO26_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO26_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO26_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO26_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO26_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_5 +// 0x05 -> siob_proc_26 +// 0x06 -> pio0_26 +// 0x07 -> pio1_26 +// 0x08 -> pio2_26 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart1_tx +// 0x1f -> null +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIOB_PROC_26 _u(0x05) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO2_26 _u(0x08) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) +#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO27_STATUS +#define IO_BANK0_GPIO27_STATUS_OFFSET _u(0x000000d8) +#define IO_BANK0_GPIO27_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO27_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO27_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO27_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO27_CTRL +#define IO_BANK0_GPIO27_CTRL_OFFSET _u(0x000000dc) +#define IO_BANK0_GPIO27_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO27_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO27_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO27_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO27_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO27_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_5 +// 0x05 -> siob_proc_27 +// 0x06 -> pio0_27 +// 0x07 -> pio1_27 +// 0x08 -> pio2_27 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart1_rx +// 0x1f -> null +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIOB_PROC_27 _u(0x05) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO2_27 _u(0x08) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) +#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO28_STATUS +#define IO_BANK0_GPIO28_STATUS_OFFSET _u(0x000000e0) +#define IO_BANK0_GPIO28_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO28_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO28_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO28_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO28_CTRL +#define IO_BANK0_GPIO28_CTRL_OFFSET _u(0x000000e4) +#define IO_BANK0_GPIO28_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO28_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO28_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO28_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO28_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO28_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_6 +// 0x05 -> siob_proc_28 +// 0x06 -> pio0_28 +// 0x07 -> pio1_28 +// 0x08 -> pio2_28 +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIOB_PROC_28 _u(0x05) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO2_28 _u(0x08) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO29_STATUS +#define IO_BANK0_GPIO29_STATUS_OFFSET _u(0x000000e8) +#define IO_BANK0_GPIO29_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO29_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO29_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO29_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO29_CTRL +#define IO_BANK0_GPIO29_CTRL_OFFSET _u(0x000000ec) +#define IO_BANK0_GPIO29_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO29_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO29_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO29_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO29_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO29_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_6 +// 0x05 -> siob_proc_29 +// 0x06 -> pio0_29 +// 0x07 -> pio1_29 +// 0x08 -> pio2_29 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIOB_PROC_29 _u(0x05) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO2_29 _u(0x08) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO30_STATUS +#define IO_BANK0_GPIO30_STATUS_OFFSET _u(0x000000f0) +#define IO_BANK0_GPIO30_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO30_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO30_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO30_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO30_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO30_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO30_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO30_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO30_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO30_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO30_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO30_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO30_CTRL +#define IO_BANK0_GPIO30_CTRL_OFFSET _u(0x000000f4) +#define IO_BANK0_GPIO30_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO30_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO30_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO30_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO30_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO30_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO30_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO30_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO30_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO30_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO30_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO30_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO30_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO30_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO30_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO30_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO30_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO30_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO30_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO30_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO30_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO30_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO30_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_7 +// 0x05 -> siob_proc_30 +// 0x06 -> pio0_30 +// 0x07 -> pio1_30 +// 0x08 -> pio2_30 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart0_tx +// 0x1f -> null +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_SIOB_PROC_30 _u(0x05) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO0_30 _u(0x06) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO1_30 _u(0x07) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO2_30 _u(0x08) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) +#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO31_STATUS +#define IO_BANK0_GPIO31_STATUS_OFFSET _u(0x000000f8) +#define IO_BANK0_GPIO31_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO31_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO31_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO31_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO31_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO31_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO31_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO31_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO31_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO31_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO31_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO31_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO31_CTRL +#define IO_BANK0_GPIO31_CTRL_OFFSET _u(0x000000fc) +#define IO_BANK0_GPIO31_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO31_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO31_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO31_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO31_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO31_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO31_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO31_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO31_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO31_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO31_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO31_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO31_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO31_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO31_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO31_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO31_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO31_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO31_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO31_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO31_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO31_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO31_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_7 +// 0x05 -> siob_proc_31 +// 0x06 -> pio0_31 +// 0x07 -> pio1_31 +// 0x08 -> pio2_31 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart0_rx +// 0x1f -> null +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_SIOB_PROC_31 _u(0x05) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO0_31 _u(0x06) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO1_31 _u(0x07) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO2_31 _u(0x08) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) +#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO32_STATUS +#define IO_BANK0_GPIO32_STATUS_OFFSET _u(0x00000100) +#define IO_BANK0_GPIO32_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO32_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO32_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO32_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO32_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO32_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO32_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO32_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO32_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO32_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO32_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO32_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO32_CTRL +#define IO_BANK0_GPIO32_CTRL_OFFSET _u(0x00000104) +#define IO_BANK0_GPIO32_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO32_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO32_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO32_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO32_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO32_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO32_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO32_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO32_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO32_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO32_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO32_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO32_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO32_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO32_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO32_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO32_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO32_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO32_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO32_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO32_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO32_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO32_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_8 +// 0x05 -> siob_proc_32 +// 0x06 -> pio0_32 +// 0x07 -> pio1_32 +// 0x08 -> pio2_32 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PWM_A_8 _u(0x04) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_SIOB_PROC_32 _u(0x05) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO0_32 _u(0x06) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO1_32 _u(0x07) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO2_32 _u(0x08) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO33_STATUS +#define IO_BANK0_GPIO33_STATUS_OFFSET _u(0x00000108) +#define IO_BANK0_GPIO33_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO33_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO33_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO33_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO33_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO33_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO33_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO33_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO33_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO33_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO33_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO33_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO33_CTRL +#define IO_BANK0_GPIO33_CTRL_OFFSET _u(0x0000010c) +#define IO_BANK0_GPIO33_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO33_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO33_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO33_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO33_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO33_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO33_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO33_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO33_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO33_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO33_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO33_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO33_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO33_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO33_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO33_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO33_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO33_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO33_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO33_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO33_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO33_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO33_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_8 +// 0x05 -> siob_proc_33 +// 0x06 -> pio0_33 +// 0x07 -> pio1_33 +// 0x08 -> pio2_33 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PWM_B_8 _u(0x04) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_SIOB_PROC_33 _u(0x05) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO0_33 _u(0x06) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO1_33 _u(0x07) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO2_33 _u(0x08) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO34_STATUS +#define IO_BANK0_GPIO34_STATUS_OFFSET _u(0x00000110) +#define IO_BANK0_GPIO34_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO34_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO34_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO34_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO34_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO34_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO34_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO34_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO34_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO34_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO34_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO34_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO34_CTRL +#define IO_BANK0_GPIO34_CTRL_OFFSET _u(0x00000114) +#define IO_BANK0_GPIO34_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO34_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO34_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO34_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO34_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO34_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO34_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO34_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO34_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO34_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO34_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO34_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO34_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO34_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO34_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO34_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO34_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO34_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO34_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO34_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO34_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO34_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO34_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_9 +// 0x05 -> siob_proc_34 +// 0x06 -> pio0_34 +// 0x07 -> pio1_34 +// 0x08 -> pio2_34 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart0_tx +// 0x1f -> null +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PWM_A_9 _u(0x04) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_SIOB_PROC_34 _u(0x05) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO0_34 _u(0x06) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO1_34 _u(0x07) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO2_34 _u(0x08) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) +#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO35_STATUS +#define IO_BANK0_GPIO35_STATUS_OFFSET _u(0x00000118) +#define IO_BANK0_GPIO35_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO35_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO35_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO35_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO35_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO35_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO35_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO35_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO35_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO35_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO35_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO35_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO35_CTRL +#define IO_BANK0_GPIO35_CTRL_OFFSET _u(0x0000011c) +#define IO_BANK0_GPIO35_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO35_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO35_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO35_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO35_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO35_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO35_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO35_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO35_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO35_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO35_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO35_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO35_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO35_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO35_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO35_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO35_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO35_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO35_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO35_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO35_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO35_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO35_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_9 +// 0x05 -> siob_proc_35 +// 0x06 -> pio0_35 +// 0x07 -> pio1_35 +// 0x08 -> pio2_35 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart0_rx +// 0x1f -> null +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PWM_B_9 _u(0x04) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_SIOB_PROC_35 _u(0x05) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO0_35 _u(0x06) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO1_35 _u(0x07) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO2_35 _u(0x08) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) +#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO36_STATUS +#define IO_BANK0_GPIO36_STATUS_OFFSET _u(0x00000120) +#define IO_BANK0_GPIO36_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO36_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO36_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO36_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO36_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO36_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO36_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO36_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO36_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO36_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO36_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO36_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO36_CTRL +#define IO_BANK0_GPIO36_CTRL_OFFSET _u(0x00000124) +#define IO_BANK0_GPIO36_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO36_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO36_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO36_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO36_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO36_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO36_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO36_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO36_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO36_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO36_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO36_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO36_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO36_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO36_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO36_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO36_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO36_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO36_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO36_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO36_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO36_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO36_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_10 +// 0x05 -> siob_proc_36 +// 0x06 -> pio0_36 +// 0x07 -> pio1_36 +// 0x08 -> pio2_36 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PWM_A_10 _u(0x04) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_SIOB_PROC_36 _u(0x05) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO0_36 _u(0x06) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO1_36 _u(0x07) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO2_36 _u(0x08) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO37_STATUS +#define IO_BANK0_GPIO37_STATUS_OFFSET _u(0x00000128) +#define IO_BANK0_GPIO37_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO37_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO37_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO37_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO37_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO37_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO37_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO37_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO37_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO37_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO37_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO37_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO37_CTRL +#define IO_BANK0_GPIO37_CTRL_OFFSET _u(0x0000012c) +#define IO_BANK0_GPIO37_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO37_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO37_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO37_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO37_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO37_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO37_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO37_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO37_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO37_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO37_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO37_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO37_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO37_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO37_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO37_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO37_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO37_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO37_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO37_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO37_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO37_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO37_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_10 +// 0x05 -> siob_proc_37 +// 0x06 -> pio0_37 +// 0x07 -> pio1_37 +// 0x08 -> pio2_37 +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PWM_B_10 _u(0x04) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_SIOB_PROC_37 _u(0x05) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO0_37 _u(0x06) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO1_37 _u(0x07) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO2_37 _u(0x08) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO38_STATUS +#define IO_BANK0_GPIO38_STATUS_OFFSET _u(0x00000130) +#define IO_BANK0_GPIO38_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO38_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO38_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO38_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO38_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO38_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO38_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO38_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO38_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO38_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO38_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO38_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO38_CTRL +#define IO_BANK0_GPIO38_CTRL_OFFSET _u(0x00000134) +#define IO_BANK0_GPIO38_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO38_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO38_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO38_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO38_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO38_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO38_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO38_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO38_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO38_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO38_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO38_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO38_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO38_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO38_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO38_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO38_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO38_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO38_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO38_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO38_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO38_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO38_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_11 +// 0x05 -> siob_proc_38 +// 0x06 -> pio0_38 +// 0x07 -> pio1_38 +// 0x08 -> pio2_38 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart1_tx +// 0x1f -> null +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PWM_A_11 _u(0x04) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_SIOB_PROC_38 _u(0x05) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO0_38 _u(0x06) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO1_38 _u(0x07) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO2_38 _u(0x08) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) +#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO39_STATUS +#define IO_BANK0_GPIO39_STATUS_OFFSET _u(0x00000138) +#define IO_BANK0_GPIO39_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO39_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO39_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO39_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO39_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO39_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO39_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO39_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO39_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO39_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO39_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO39_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO39_CTRL +#define IO_BANK0_GPIO39_CTRL_OFFSET _u(0x0000013c) +#define IO_BANK0_GPIO39_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO39_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO39_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO39_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO39_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO39_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO39_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO39_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO39_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO39_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO39_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO39_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO39_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO39_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO39_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO39_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO39_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO39_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO39_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO39_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO39_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO39_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO39_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi0_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_11 +// 0x05 -> siob_proc_39 +// 0x06 -> pio0_39 +// 0x07 -> pio1_39 +// 0x08 -> pio2_39 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart1_rx +// 0x1f -> null +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PWM_B_11 _u(0x04) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_SIOB_PROC_39 _u(0x05) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO0_39 _u(0x06) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO1_39 _u(0x07) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO2_39 _u(0x08) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) +#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO40_STATUS +#define IO_BANK0_GPIO40_STATUS_OFFSET _u(0x00000140) +#define IO_BANK0_GPIO40_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO40_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO40_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO40_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO40_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO40_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO40_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO40_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO40_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO40_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO40_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO40_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO40_CTRL +#define IO_BANK0_GPIO40_CTRL_OFFSET _u(0x00000144) +#define IO_BANK0_GPIO40_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO40_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO40_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO40_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO40_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO40_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO40_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO40_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO40_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO40_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO40_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO40_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO40_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO40_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO40_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO40_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO40_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO40_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO40_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO40_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO40_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO40_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO40_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_8 +// 0x05 -> siob_proc_40 +// 0x06 -> pio0_40 +// 0x07 -> pio1_40 +// 0x08 -> pio2_40 +// 0x0a -> usb_muxing_vbus_detect +// 0x1f -> null +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PWM_A_8 _u(0x04) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_SIOB_PROC_40 _u(0x05) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO0_40 _u(0x06) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO1_40 _u(0x07) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO2_40 _u(0x08) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO41_STATUS +#define IO_BANK0_GPIO41_STATUS_OFFSET _u(0x00000148) +#define IO_BANK0_GPIO41_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO41_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO41_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO41_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO41_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO41_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO41_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO41_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO41_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO41_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO41_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO41_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO41_CTRL +#define IO_BANK0_GPIO41_CTRL_OFFSET _u(0x0000014c) +#define IO_BANK0_GPIO41_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO41_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO41_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO41_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO41_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO41_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO41_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO41_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO41_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO41_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO41_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO41_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO41_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO41_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO41_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO41_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO41_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO41_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO41_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO41_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO41_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO41_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO41_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_8 +// 0x05 -> siob_proc_41 +// 0x06 -> pio0_41 +// 0x07 -> pio1_41 +// 0x08 -> pio2_41 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PWM_B_8 _u(0x04) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_SIOB_PROC_41 _u(0x05) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO0_41 _u(0x06) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO1_41 _u(0x07) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO2_41 _u(0x08) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO42_STATUS +#define IO_BANK0_GPIO42_STATUS_OFFSET _u(0x00000150) +#define IO_BANK0_GPIO42_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO42_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO42_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO42_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO42_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO42_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO42_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO42_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO42_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO42_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO42_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO42_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO42_CTRL +#define IO_BANK0_GPIO42_CTRL_OFFSET _u(0x00000154) +#define IO_BANK0_GPIO42_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO42_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO42_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO42_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO42_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO42_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO42_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO42_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO42_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO42_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO42_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO42_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO42_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO42_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO42_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO42_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO42_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO42_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO42_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO42_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO42_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO42_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO42_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_9 +// 0x05 -> siob_proc_42 +// 0x06 -> pio0_42 +// 0x07 -> pio1_42 +// 0x08 -> pio2_42 +// 0x0a -> usb_muxing_overcurr_detect +// 0x0b -> uart1_tx +// 0x1f -> null +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PWM_A_9 _u(0x04) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_SIOB_PROC_42 _u(0x05) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO0_42 _u(0x06) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO1_42 _u(0x07) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO2_42 _u(0x08) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) +#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO43_STATUS +#define IO_BANK0_GPIO43_STATUS_OFFSET _u(0x00000158) +#define IO_BANK0_GPIO43_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO43_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO43_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO43_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO43_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO43_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO43_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO43_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO43_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO43_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO43_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO43_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO43_CTRL +#define IO_BANK0_GPIO43_CTRL_OFFSET _u(0x0000015c) +#define IO_BANK0_GPIO43_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO43_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO43_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO43_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO43_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO43_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO43_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO43_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO43_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO43_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO43_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO43_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO43_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO43_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO43_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO43_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO43_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO43_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO43_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO43_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO43_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO43_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO43_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_9 +// 0x05 -> siob_proc_43 +// 0x06 -> pio0_43 +// 0x07 -> pio1_43 +// 0x08 -> pio2_43 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart1_rx +// 0x1f -> null +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PWM_B_9 _u(0x04) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_SIOB_PROC_43 _u(0x05) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO0_43 _u(0x06) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO1_43 _u(0x07) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO2_43 _u(0x08) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) +#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO44_STATUS +#define IO_BANK0_GPIO44_STATUS_OFFSET _u(0x00000160) +#define IO_BANK0_GPIO44_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO44_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO44_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO44_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO44_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO44_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO44_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO44_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO44_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO44_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO44_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO44_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO44_CTRL +#define IO_BANK0_GPIO44_CTRL_OFFSET _u(0x00000164) +#define IO_BANK0_GPIO44_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO44_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO44_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO44_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO44_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO44_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO44_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO44_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO44_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO44_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO44_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO44_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO44_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO44_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO44_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO44_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO44_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO44_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO44_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO44_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO44_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO44_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO44_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_rx +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x04 -> pwm_a_10 +// 0x05 -> siob_proc_44 +// 0x06 -> pio0_44 +// 0x07 -> pio1_44 +// 0x08 -> pio2_44 +// 0x0a -> usb_muxing_vbus_en +// 0x1f -> null +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PWM_A_10 _u(0x04) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_SIOB_PROC_44 _u(0x05) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO0_44 _u(0x06) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO1_44 _u(0x07) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO2_44 _u(0x08) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO45_STATUS +#define IO_BANK0_GPIO45_STATUS_OFFSET _u(0x00000168) +#define IO_BANK0_GPIO45_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO45_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO45_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO45_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO45_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO45_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO45_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO45_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO45_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO45_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO45_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO45_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO45_CTRL +#define IO_BANK0_GPIO45_CTRL_OFFSET _u(0x0000016c) +#define IO_BANK0_GPIO45_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO45_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO45_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO45_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO45_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO45_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO45_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO45_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO45_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO45_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO45_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO45_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO45_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO45_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO45_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO45_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO45_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO45_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO45_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO45_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO45_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO45_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO45_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_ss_n +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x04 -> pwm_b_10 +// 0x05 -> siob_proc_45 +// 0x06 -> pio0_45 +// 0x07 -> pio1_45 +// 0x08 -> pio2_45 +// 0x0a -> usb_muxing_overcurr_detect +// 0x1f -> null +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PWM_B_10 _u(0x04) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_SIOB_PROC_45 _u(0x05) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO0_45 _u(0x06) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO1_45 _u(0x07) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO2_45 _u(0x08) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a) +#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO46_STATUS +#define IO_BANK0_GPIO46_STATUS_OFFSET _u(0x00000170) +#define IO_BANK0_GPIO46_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO46_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO46_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO46_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO46_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO46_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO46_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO46_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO46_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO46_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO46_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO46_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO46_CTRL +#define IO_BANK0_GPIO46_CTRL_OFFSET _u(0x00000174) +#define IO_BANK0_GPIO46_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO46_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO46_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO46_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO46_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO46_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO46_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO46_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO46_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO46_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO46_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO46_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO46_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO46_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO46_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO46_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO46_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO46_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO46_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO46_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO46_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO46_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO46_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_sclk +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x04 -> pwm_a_11 +// 0x05 -> siob_proc_46 +// 0x06 -> pio0_46 +// 0x07 -> pio1_46 +// 0x08 -> pio2_46 +// 0x0a -> usb_muxing_vbus_detect +// 0x0b -> uart0_tx +// 0x1f -> null +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PWM_A_11 _u(0x04) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_SIOB_PROC_46 _u(0x05) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO0_46 _u(0x06) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO1_46 _u(0x07) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO2_46 _u(0x08) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) +#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_GPIO47_STATUS +#define IO_BANK0_GPIO47_STATUS_OFFSET _u(0x00000178) +#define IO_BANK0_GPIO47_STATUS_BITS _u(0x04022200) +#define IO_BANK0_GPIO47_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_MSB _u(26) +#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_LSB _u(26) +#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_BANK0_GPIO47_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_BANK0_GPIO47_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_BANK0_GPIO47_STATUS_INFROMPAD_MSB _u(17) +#define IO_BANK0_GPIO47_STATUS_INFROMPAD_LSB _u(17) +#define IO_BANK0_GPIO47_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_BANK0_GPIO47_STATUS_OETOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO47_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_BANK0_GPIO47_STATUS_OETOPAD_MSB _u(13) +#define IO_BANK0_GPIO47_STATUS_OETOPAD_LSB _u(13) +#define IO_BANK0_GPIO47_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_MSB _u(9) +#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_LSB _u(9) +#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_GPIO47_CTRL +#define IO_BANK0_GPIO47_CTRL_OFFSET _u(0x0000017c) +#define IO_BANK0_GPIO47_CTRL_BITS _u(0x3003f01f) +#define IO_BANK0_GPIO47_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_BANK0_GPIO47_CTRL_IRQOVER_RESET _u(0x0) +#define IO_BANK0_GPIO47_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_BANK0_GPIO47_CTRL_IRQOVER_MSB _u(29) +#define IO_BANK0_GPIO47_CTRL_IRQOVER_LSB _u(28) +#define IO_BANK0_GPIO47_CTRL_IRQOVER_ACCESS "RW" +#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_BANK0_GPIO47_CTRL_INOVER_RESET _u(0x0) +#define IO_BANK0_GPIO47_CTRL_INOVER_BITS _u(0x00030000) +#define IO_BANK0_GPIO47_CTRL_INOVER_MSB _u(17) +#define IO_BANK0_GPIO47_CTRL_INOVER_LSB _u(16) +#define IO_BANK0_GPIO47_CTRL_INOVER_ACCESS "RW" +#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_BANK0_GPIO47_CTRL_OEOVER_RESET _u(0x0) +#define IO_BANK0_GPIO47_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_BANK0_GPIO47_CTRL_OEOVER_MSB _u(15) +#define IO_BANK0_GPIO47_CTRL_OEOVER_LSB _u(14) +#define IO_BANK0_GPIO47_CTRL_OEOVER_ACCESS "RW" +#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_BANK0_GPIO47_CTRL_OUTOVER_RESET _u(0x0) +#define IO_BANK0_GPIO47_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_BANK0_GPIO47_CTRL_OUTOVER_MSB _u(13) +#define IO_BANK0_GPIO47_CTRL_OUTOVER_LSB _u(12) +#define IO_BANK0_GPIO47_CTRL_OUTOVER_ACCESS "RW" +#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_GPIO47_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x01 -> spi1_tx +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x04 -> pwm_b_11 +// 0x05 -> siob_proc_47 +// 0x06 -> pio0_47 +// 0x07 -> pio1_47 +// 0x08 -> pio2_47 +// 0x09 -> xip_ss_n_1 +// 0x0a -> usb_muxing_vbus_en +// 0x0b -> uart0_rx +// 0x1f -> null +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_MSB _u(4) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_LSB _u(0) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_ACCESS "RW" +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PWM_B_11 _u(0x04) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_SIOB_PROC_47 _u(0x05) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO0_47 _u(0x06) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO1_47 _u(0x07) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO2_47 _u(0x08) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) +#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC0_SECURE0 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_OFFSET _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_BITS _u(0xffffffff) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_BITS _u(0x80000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_MSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_LSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_BITS _u(0x40000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_MSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_LSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_BITS _u(0x20000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_MSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_LSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_BITS _u(0x10000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_MSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_LSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_BITS _u(0x08000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_MSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_LSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_BITS _u(0x04000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_MSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_LSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_BITS _u(0x02000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_MSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_LSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_BITS _u(0x01000000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_MSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_LSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_BITS _u(0x00800000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_MSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_LSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_BITS _u(0x00400000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_MSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_LSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_BITS _u(0x00200000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_MSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_LSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_BITS _u(0x00100000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_MSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_LSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_BITS _u(0x00080000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_MSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_LSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_BITS _u(0x00040000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_MSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_LSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_BITS _u(0x00020000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_MSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_LSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_BITS _u(0x00010000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_MSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_LSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC0_SECURE1 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_OFFSET _u(0x00000204) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_BITS _u(0x0000ffff) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32 +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_OFFSET _u(0x00000208) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_BITS _u(0xffffffff) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_BITS _u(0x80000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_MSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_LSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_BITS _u(0x40000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_MSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_LSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_BITS _u(0x20000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_MSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_LSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_BITS _u(0x10000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_MSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_LSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_BITS _u(0x08000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_MSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_LSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_BITS _u(0x04000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_MSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_LSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_BITS _u(0x02000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_MSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_LSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_BITS _u(0x01000000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_MSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_LSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_BITS _u(0x00800000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_MSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_LSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_BITS _u(0x00400000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_MSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_LSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_BITS _u(0x00200000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_MSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_LSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_BITS _u(0x00100000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_MSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_LSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_BITS _u(0x00080000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_MSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_LSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_BITS _u(0x00040000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_MSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_LSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_BITS _u(0x00020000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_MSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_LSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_BITS _u(0x00010000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_MSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_LSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_OFFSET _u(0x0000020c) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_BITS _u(0x0000ffff) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32 +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC1_SECURE0 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_OFFSET _u(0x00000210) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_BITS _u(0xffffffff) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_BITS _u(0x80000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_MSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_LSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_BITS _u(0x40000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_MSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_LSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_BITS _u(0x20000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_MSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_LSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_BITS _u(0x10000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_MSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_LSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_BITS _u(0x08000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_MSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_LSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_BITS _u(0x04000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_MSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_LSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_BITS _u(0x02000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_MSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_LSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_BITS _u(0x01000000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_MSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_LSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_BITS _u(0x00800000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_MSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_LSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_BITS _u(0x00400000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_MSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_LSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_BITS _u(0x00200000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_MSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_LSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_BITS _u(0x00100000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_MSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_LSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_BITS _u(0x00080000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_MSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_LSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_BITS _u(0x00040000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_MSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_LSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_BITS _u(0x00020000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_MSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_LSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_BITS _u(0x00010000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_MSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_LSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC1_SECURE1 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_OFFSET _u(0x00000214) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_BITS _u(0x0000ffff) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32 +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_OFFSET _u(0x00000218) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_BITS _u(0xffffffff) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_BITS _u(0x80000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_MSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_LSB _u(31) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_BITS _u(0x40000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_MSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_LSB _u(30) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_BITS _u(0x20000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_MSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_LSB _u(29) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_BITS _u(0x10000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_MSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_LSB _u(28) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_BITS _u(0x08000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_MSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_LSB _u(27) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_BITS _u(0x04000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_MSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_LSB _u(26) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_BITS _u(0x02000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_MSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_LSB _u(25) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_BITS _u(0x01000000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_MSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_LSB _u(24) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_BITS _u(0x00800000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_MSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_LSB _u(23) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_BITS _u(0x00400000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_MSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_LSB _u(22) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_BITS _u(0x00200000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_MSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_LSB _u(21) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_BITS _u(0x00100000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_MSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_LSB _u(20) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_BITS _u(0x00080000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_MSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_LSB _u(19) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_BITS _u(0x00040000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_MSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_LSB _u(18) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_BITS _u(0x00020000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_MSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_LSB _u(17) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_BITS _u(0x00010000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_MSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_LSB _u(16) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_OFFSET _u(0x0000021c) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_BITS _u(0x0000ffff) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32 +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_OFFSET _u(0x00000220) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_BITS _u(0xffffffff) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_BITS _u(0x80000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_MSB _u(31) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_LSB _u(31) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_BITS _u(0x40000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_MSB _u(30) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_LSB _u(30) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_BITS _u(0x20000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_MSB _u(29) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_LSB _u(29) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_BITS _u(0x10000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_MSB _u(28) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_LSB _u(28) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_BITS _u(0x08000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_MSB _u(27) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_LSB _u(27) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_BITS _u(0x04000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_MSB _u(26) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_LSB _u(26) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_BITS _u(0x02000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_MSB _u(25) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_LSB _u(25) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_BITS _u(0x01000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_MSB _u(24) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_LSB _u(24) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_BITS _u(0x00800000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_MSB _u(23) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_LSB _u(23) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_BITS _u(0x00400000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_MSB _u(22) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_LSB _u(22) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_BITS _u(0x00200000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_MSB _u(21) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_LSB _u(21) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_BITS _u(0x00100000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_MSB _u(20) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_LSB _u(20) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_BITS _u(0x00080000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_MSB _u(19) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_LSB _u(19) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_BITS _u(0x00040000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_MSB _u(18) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_LSB _u(18) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_BITS _u(0x00020000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_MSB _u(17) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_LSB _u(17) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_BITS _u(0x00010000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_MSB _u(16) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_LSB _u(16) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_OFFSET _u(0x00000224) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_BITS _u(0x0000ffff) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_OFFSET _u(0x00000228) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_BITS _u(0xffffffff) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_BITS _u(0x80000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_MSB _u(31) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_LSB _u(31) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_BITS _u(0x40000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_MSB _u(30) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_LSB _u(30) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_BITS _u(0x20000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_MSB _u(29) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_LSB _u(29) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_BITS _u(0x10000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_MSB _u(28) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_LSB _u(28) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_BITS _u(0x08000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_MSB _u(27) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_LSB _u(27) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_BITS _u(0x04000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_MSB _u(26) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_LSB _u(26) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_BITS _u(0x02000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_MSB _u(25) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_LSB _u(25) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_BITS _u(0x01000000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_MSB _u(24) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_LSB _u(24) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_BITS _u(0x00800000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_MSB _u(23) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_LSB _u(23) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_BITS _u(0x00400000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_MSB _u(22) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_LSB _u(22) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_BITS _u(0x00200000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_MSB _u(21) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_LSB _u(21) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_BITS _u(0x00100000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_MSB _u(20) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_LSB _u(20) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_BITS _u(0x00080000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_MSB _u(19) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_LSB _u(19) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_BITS _u(0x00040000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_MSB _u(18) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_LSB _u(18) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_BITS _u(0x00020000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_MSB _u(17) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_LSB _u(17) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_BITS _u(0x00010000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_MSB _u(16) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_LSB _u(16) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_OFFSET _u(0x0000022c) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_BITS _u(0x0000ffff) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_BITS _u(0x00008000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_MSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_LSB _u(15) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_BITS _u(0x00004000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_MSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_LSB _u(14) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_BITS _u(0x00002000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_MSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_LSB _u(13) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_BITS _u(0x00001000) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_MSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_LSB _u(12) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_BITS _u(0x00000800) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_MSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_LSB _u(11) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_BITS _u(0x00000400) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_MSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_LSB _u(10) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_BITS _u(0x00000200) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_MSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_LSB _u(9) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_BITS _u(0x00000100) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_MSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_LSB _u(8) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_BITS _u(0x00000080) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_MSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_LSB _u(7) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_BITS _u(0x00000040) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_MSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_LSB _u(6) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_BITS _u(0x00000020) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_MSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_LSB _u(5) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_BITS _u(0x00000010) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_MSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_LSB _u(4) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_BITS _u(0x00000008) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_MSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_LSB _u(3) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_BITS _u(0x00000004) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_MSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_LSB _u(2) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_BITS _u(0x00000002) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_MSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_LSB _u(1) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32 +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_RESET _u(0x0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_BITS _u(0x00000001) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_MSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_LSB _u(0) +#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR0 +// Description : Raw Interrupts +#define IO_BANK0_INTR0_OFFSET _u(0x00000230) +#define IO_BANK0_INTR0_BITS _u(0xffffffff) +#define IO_BANK0_INTR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_EDGE_LOW +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO7_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_EDGE_LOW +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO6_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_EDGE_LOW +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO5_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_EDGE_LOW +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO4_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_EDGE_LOW +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO3_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_EDGE_LOW +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO2_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_EDGE_LOW +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO1_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_EDGE_HIGH +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_EDGE_LOW +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR0_GPIO0_LEVEL_LOW +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR1 +// Description : Raw Interrupts +#define IO_BANK0_INTR1_OFFSET _u(0x00000234) +#define IO_BANK0_INTR1_BITS _u(0xffffffff) +#define IO_BANK0_INTR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_EDGE_LOW +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO15_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_EDGE_LOW +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO14_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_EDGE_LOW +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO13_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_EDGE_LOW +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO12_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_EDGE_LOW +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO11_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_EDGE_LOW +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO10_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_EDGE_LOW +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO9_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_EDGE_HIGH +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_EDGE_LOW +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR1_GPIO8_LEVEL_LOW +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR2 +// Description : Raw Interrupts +#define IO_BANK0_INTR2_OFFSET _u(0x00000238) +#define IO_BANK0_INTR2_BITS _u(0xffffffff) +#define IO_BANK0_INTR2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_EDGE_LOW +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO23_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_EDGE_LOW +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO22_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_EDGE_LOW +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO21_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_EDGE_LOW +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO20_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_EDGE_LOW +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO19_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_EDGE_LOW +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO18_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_EDGE_LOW +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO17_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_EDGE_HIGH +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_EDGE_LOW +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR2_GPIO16_LEVEL_LOW +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR3 +// Description : Raw Interrupts +#define IO_BANK0_INTR3_OFFSET _u(0x0000023c) +#define IO_BANK0_INTR3_BITS _u(0xffffffff) +#define IO_BANK0_INTR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO31_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO31_EDGE_LOW +#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO31_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO31_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO30_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO30_EDGE_LOW +#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO30_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO30_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_EDGE_LOW +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO29_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_EDGE_LOW +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO28_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_EDGE_LOW +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO27_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_EDGE_LOW +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO26_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_EDGE_LOW +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO25_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_EDGE_HIGH +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_EDGE_LOW +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR3_GPIO24_LEVEL_LOW +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR4 +// Description : Raw Interrupts +#define IO_BANK0_INTR4_OFFSET _u(0x00000240) +#define IO_BANK0_INTR4_BITS _u(0xffffffff) +#define IO_BANK0_INTR4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO39_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO39_EDGE_LOW +#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO39_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO39_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO38_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO38_EDGE_LOW +#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO38_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO38_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO37_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO37_EDGE_LOW +#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO37_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO37_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO36_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO36_EDGE_LOW +#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO36_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO36_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO35_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO35_EDGE_LOW +#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO35_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO35_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO34_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO34_EDGE_LOW +#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO34_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO34_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO33_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO33_EDGE_LOW +#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO33_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO33_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO32_EDGE_HIGH +#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO32_EDGE_LOW +#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO32_LEVEL_HIGH +#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR4_GPIO32_LEVEL_LOW +#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_INTR5 +// Description : Raw Interrupts +#define IO_BANK0_INTR5_OFFSET _u(0x00000244) +#define IO_BANK0_INTR5_BITS _u(0xffffffff) +#define IO_BANK0_INTR5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO47_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO47_EDGE_LOW +#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO47_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO47_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO46_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO46_EDGE_LOW +#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO46_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO46_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO45_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO45_EDGE_LOW +#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO45_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO45_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO44_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO44_EDGE_LOW +#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO44_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO44_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO43_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO43_EDGE_LOW +#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO43_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO43_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO42_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO42_EDGE_LOW +#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO42_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO42_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO41_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO41_EDGE_LOW +#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO41_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO41_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO40_EDGE_HIGH +#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO40_EDGE_LOW +#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO40_LEVEL_HIGH +#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_INTR5_GPIO40_LEVEL_LOW +#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE0 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE0_OFFSET _u(0x00000248) +#define IO_BANK0_PROC0_INTE0_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE1 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE1_OFFSET _u(0x0000024c) +#define IO_BANK0_PROC0_INTE1_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE2 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE2_OFFSET _u(0x00000250) +#define IO_BANK0_PROC0_INTE2_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE3 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE3_OFFSET _u(0x00000254) +#define IO_BANK0_PROC0_INTE3_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE4 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE4_OFFSET _u(0x00000258) +#define IO_BANK0_PROC0_INTE4_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTE5 +// Description : Interrupt Enable for proc0 +#define IO_BANK0_PROC0_INTE5_OFFSET _u(0x0000025c) +#define IO_BANK0_PROC0_INTE5_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTE5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF0 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF0_OFFSET _u(0x00000260) +#define IO_BANK0_PROC0_INTF0_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF1 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF1_OFFSET _u(0x00000264) +#define IO_BANK0_PROC0_INTF1_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF2 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF2_OFFSET _u(0x00000268) +#define IO_BANK0_PROC0_INTF2_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF3 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF3_OFFSET _u(0x0000026c) +#define IO_BANK0_PROC0_INTF3_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF4 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF4_OFFSET _u(0x00000270) +#define IO_BANK0_PROC0_INTF4_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTF5 +// Description : Interrupt Force for proc0 +#define IO_BANK0_PROC0_INTF5_OFFSET _u(0x00000274) +#define IO_BANK0_PROC0_INTF5_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTF5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS0 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS0_OFFSET _u(0x00000278) +#define IO_BANK0_PROC0_INTS0_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS1 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS1_OFFSET _u(0x0000027c) +#define IO_BANK0_PROC0_INTS1_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS2 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS2_OFFSET _u(0x00000280) +#define IO_BANK0_PROC0_INTS2_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS3 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS3_OFFSET _u(0x00000284) +#define IO_BANK0_PROC0_INTS3_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS4 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS4_OFFSET _u(0x00000288) +#define IO_BANK0_PROC0_INTS4_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC0_INTS5 +// Description : Interrupt status after masking & forcing for proc0 +#define IO_BANK0_PROC0_INTS5_OFFSET _u(0x0000028c) +#define IO_BANK0_PROC0_INTS5_BITS _u(0xffffffff) +#define IO_BANK0_PROC0_INTS5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE0 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE0_OFFSET _u(0x00000290) +#define IO_BANK0_PROC1_INTE0_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE1 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE1_OFFSET _u(0x00000294) +#define IO_BANK0_PROC1_INTE1_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE2 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE2_OFFSET _u(0x00000298) +#define IO_BANK0_PROC1_INTE2_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE3 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE3_OFFSET _u(0x0000029c) +#define IO_BANK0_PROC1_INTE3_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE4 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE4_OFFSET _u(0x000002a0) +#define IO_BANK0_PROC1_INTE4_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTE5 +// Description : Interrupt Enable for proc1 +#define IO_BANK0_PROC1_INTE5_OFFSET _u(0x000002a4) +#define IO_BANK0_PROC1_INTE5_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTE5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF0 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF0_OFFSET _u(0x000002a8) +#define IO_BANK0_PROC1_INTF0_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF1 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF1_OFFSET _u(0x000002ac) +#define IO_BANK0_PROC1_INTF1_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF2 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF2_OFFSET _u(0x000002b0) +#define IO_BANK0_PROC1_INTF2_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF3 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF3_OFFSET _u(0x000002b4) +#define IO_BANK0_PROC1_INTF3_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF4 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF4_OFFSET _u(0x000002b8) +#define IO_BANK0_PROC1_INTF4_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTF5 +// Description : Interrupt Force for proc1 +#define IO_BANK0_PROC1_INTF5_OFFSET _u(0x000002bc) +#define IO_BANK0_PROC1_INTF5_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTF5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS0 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS0_OFFSET _u(0x000002c0) +#define IO_BANK0_PROC1_INTS0_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS1 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS1_OFFSET _u(0x000002c4) +#define IO_BANK0_PROC1_INTS1_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS2 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS2_OFFSET _u(0x000002c8) +#define IO_BANK0_PROC1_INTS2_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS3 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS3_OFFSET _u(0x000002cc) +#define IO_BANK0_PROC1_INTS3_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS4 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS4_OFFSET _u(0x000002d0) +#define IO_BANK0_PROC1_INTS4_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_PROC1_INTS5 +// Description : Interrupt status after masking & forcing for proc1 +#define IO_BANK0_PROC1_INTS5_OFFSET _u(0x000002d4) +#define IO_BANK0_PROC1_INTS5_BITS _u(0xffffffff) +#define IO_BANK0_PROC1_INTS5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE0 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET _u(0x000002d8) +#define IO_BANK0_DORMANT_WAKE_INTE0_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE1 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET _u(0x000002dc) +#define IO_BANK0_DORMANT_WAKE_INTE1_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE2 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET _u(0x000002e0) +#define IO_BANK0_DORMANT_WAKE_INTE2_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE3 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET _u(0x000002e4) +#define IO_BANK0_DORMANT_WAKE_INTE3_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE4 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE4_OFFSET _u(0x000002e8) +#define IO_BANK0_DORMANT_WAKE_INTE4_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTE5 +// Description : Interrupt Enable for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTE5_OFFSET _u(0x000002ec) +#define IO_BANK0_DORMANT_WAKE_INTE5_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTE5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF0 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET _u(0x000002f0) +#define IO_BANK0_DORMANT_WAKE_INTF0_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF1 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET _u(0x000002f4) +#define IO_BANK0_DORMANT_WAKE_INTF1_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF2 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET _u(0x000002f8) +#define IO_BANK0_DORMANT_WAKE_INTF2_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF3 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET _u(0x000002fc) +#define IO_BANK0_DORMANT_WAKE_INTF3_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF4 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF4_OFFSET _u(0x00000300) +#define IO_BANK0_DORMANT_WAKE_INTF4_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTF5 +// Description : Interrupt Force for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTF5_OFFSET _u(0x00000304) +#define IO_BANK0_DORMANT_WAKE_INTF5_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTF5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS0 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET _u(0x00000308) +#define IO_BANK0_DORMANT_WAKE_INTS0_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS1 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET _u(0x0000030c) +#define IO_BANK0_DORMANT_WAKE_INTS1_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS2 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET _u(0x00000310) +#define IO_BANK0_DORMANT_WAKE_INTS2_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS3 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET _u(0x00000314) +#define IO_BANK0_DORMANT_WAKE_INTS3_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS4 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS4_OFFSET _u(0x00000318) +#define IO_BANK0_DORMANT_WAKE_INTS4_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_BANK0_DORMANT_WAKE_INTS5 +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_BANK0_DORMANT_WAKE_INTS5_OFFSET _u(0x0000031c) +#define IO_BANK0_DORMANT_WAKE_INTS5_BITS _u(0xffffffff) +#define IO_BANK0_DORMANT_WAKE_INTS5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_BITS _u(0x80000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_MSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_LSB _u(31) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_BITS _u(0x40000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_MSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_LSB _u(30) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_MSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_LSB _u(29) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_BITS _u(0x10000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_MSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_LSB _u(28) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_BITS _u(0x08000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_MSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_LSB _u(27) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_BITS _u(0x04000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_MSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_LSB _u(26) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_MSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_LSB _u(25) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_BITS _u(0x01000000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_MSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_LSB _u(24) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_BITS _u(0x00800000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_MSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_LSB _u(23) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_BITS _u(0x00400000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_MSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_LSB _u(22) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_MSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_LSB _u(21) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_BITS _u(0x00100000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_MSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_LSB _u(20) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_BITS _u(0x00080000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_MSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_LSB _u(19) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_BITS _u(0x00040000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_MSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_LSB _u(18) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_MSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_LSB _u(17) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_BITS _u(0x00010000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_MSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_LSB _u(16) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_BITS _u(0x00008000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_MSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_LSB _u(15) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_BITS _u(0x00004000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_MSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_LSB _u(14) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_MSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_LSB _u(13) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_BITS _u(0x00001000) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_MSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_LSB _u(12) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_BITS _u(0x00000800) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_MSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_LSB _u(11) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_BITS _u(0x00000400) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_MSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_LSB _u(10) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_MSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_LSB _u(9) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_BITS _u(0x00000100) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_MSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_LSB _u(8) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_BITS _u(0x00000080) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_MSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_LSB _u(7) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_BITS _u(0x00000040) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_MSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_LSB _u(6) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_MSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_LSB _u(5) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_BITS _u(0x00000010) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_MSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_LSB _u(4) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_BITS _u(0x00000008) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_MSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_LSB _u(3) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_BITS _u(0x00000004) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_MSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_LSB _u(2) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_MSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_LSB _u(1) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_RESET _u(0x0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_BITS _u(0x00000001) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_MSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_LSB _u(0) +#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_IO_BANK0_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/io_qspi.h b/lib/pico-sdk/rp2350/hardware/regs/io_qspi.h new file mode 100644 index 000000000000..668105264005 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/io_qspi.h @@ -0,0 +1,3663 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : IO_QSPI +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_IO_QSPI_H +#define _HARDWARE_REGS_IO_QSPI_H +// ============================================================================= +// Register : IO_QSPI_USBPHY_DP_STATUS +#define IO_QSPI_USBPHY_DP_STATUS_OFFSET _u(0x00000000) +#define IO_QSPI_USBPHY_DP_STATUS_BITS _u(0x04022200) +#define IO_QSPI_USBPHY_DP_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_USBPHY_DP_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_USBPHY_DP_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_USBPHY_DP_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_USBPHY_DP_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_USBPHY_DP_CTRL +#define IO_QSPI_USBPHY_DP_CTRL_OFFSET _u(0x00000004) +#define IO_QSPI_USBPHY_DP_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_USBPHY_DP_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_USBPHY_DP_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_USBPHY_DP_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_USBPHY_DP_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_USBPHY_DP_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DP_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x02 -> uart1_tx +// 0x03 -> i2c0_sda +// 0x05 -> siob_proc_56 +// 0x1f -> null +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_SIOB_PROC_56 _u(0x05) +#define IO_QSPI_USBPHY_DP_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_USBPHY_DM_STATUS +#define IO_QSPI_USBPHY_DM_STATUS_OFFSET _u(0x00000008) +#define IO_QSPI_USBPHY_DM_STATUS_BITS _u(0x04022200) +#define IO_QSPI_USBPHY_DM_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_USBPHY_DM_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_USBPHY_DM_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_USBPHY_DM_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_USBPHY_DM_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_USBPHY_DM_CTRL +#define IO_QSPI_USBPHY_DM_CTRL_OFFSET _u(0x0000000c) +#define IO_QSPI_USBPHY_DM_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_USBPHY_DM_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_USBPHY_DM_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_USBPHY_DM_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_USBPHY_DM_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_USBPHY_DM_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_USBPHY_DM_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x02 -> uart1_rx +// 0x03 -> i2c0_scl +// 0x05 -> siob_proc_57 +// 0x1f -> null +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_SIOB_PROC_57 _u(0x05) +#define IO_QSPI_USBPHY_DM_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SCLK_STATUS +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET _u(0x00000010) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS _u(0x04022200) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SCLK_CTRL +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET _u(0x00000014) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sclk +// 0x02 -> uart1_cts +// 0x03 -> i2c1_sda +// 0x05 -> siob_proc_58 +// 0x0b -> uart1_tx +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _u(0x00) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIOB_PROC_58 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b) +#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SS_STATUS +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET _u(0x00000018) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS _u(0x04022200) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SS_CTRL +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET _u(0x0000001c) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_ss_n_0 +// 0x02 -> uart1_rts +// 0x03 -> i2c1_scl +// 0x05 -> siob_proc_59 +// 0x0b -> uart1_rx +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N_0 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIOB_PROC_59 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b) +#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD0_STATUS +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET _u(0x00000020) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS _u(0x04022200) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD0_CTRL +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET _u(0x00000024) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd0 +// 0x02 -> uart0_tx +// 0x03 -> i2c0_sda +// 0x05 -> siob_proc_60 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIOB_PROC_60 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD1_STATUS +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET _u(0x00000028) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS _u(0x04022200) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD1_CTRL +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET _u(0x0000002c) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd1 +// 0x02 -> uart0_rx +// 0x03 -> i2c0_scl +// 0x05 -> siob_proc_61 +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIOB_PROC_61 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD2_STATUS +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET _u(0x00000030) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS _u(0x04022200) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD2_CTRL +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET _u(0x00000034) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd2 +// 0x02 -> uart0_cts +// 0x03 -> i2c1_sda +// 0x05 -> siob_proc_62 +// 0x0b -> uart0_tx +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIOB_PROC_62 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b) +#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD3_STATUS +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET _u(0x00000038) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS _u(0x04022200) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC +// Description : interrupt to processors, after override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS _u(0x04000000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB _u(26) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD +// Description : input signal from pad, before filtering and override are +// applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS _u(0x00020000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD +// Description : output enable to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS _u(0x00002000) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD +// Description : output signal to pad after register override is applied +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS _u(0x00000200) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB _u(9) +#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_GPIO_QSPI_SD3_CTRL +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET _u(0x0000003c) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS _u(0x3003f01f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET _u(0x0000001f) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER +// 0x0 -> don't invert the interrupt +// 0x1 -> invert the interrupt +// 0x2 -> drive interrupt low +// 0x3 -> drive interrupt high +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS _u(0x30000000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB _u(29) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB _u(28) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER +// 0x0 -> don't invert the peri input +// 0x1 -> invert the peri input +// 0x2 -> drive peri input low +// 0x3 -> drive peri input high +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS _u(0x00030000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB _u(17) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB _u(16) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER +// 0x0 -> drive output enable from peripheral signal selected by funcsel +// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel +// 0x2 -> disable output +// 0x3 -> enable output +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS _u(0x0000c000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB _u(15) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB _u(14) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER +// 0x0 -> drive output from peripheral signal selected by funcsel +// 0x1 -> drive output from inverse of peripheral signal selected by funcsel +// 0x2 -> drive output low +// 0x3 -> drive output high +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS _u(0x00003000) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB _u(13) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB _u(12) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT _u(0x1) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _u(0x2) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _u(0x3) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL +// Description : 0-31 -> selects pin function according to the gpio table +// 31 == NULL +// 0x00 -> xip_sd3 +// 0x02 -> uart0_rts +// 0x03 -> i2c1_scl +// 0x05 -> siob_proc_63 +// 0x0b -> uart0_rx +// 0x1f -> null +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _u(0x1f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS _u(0x0000001f) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB _u(4) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB _u(0) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW" +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _u(0x00) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIOB_PROC_63 _u(0x05) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b) +#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f) +// ============================================================================= +// Register : IO_QSPI_IRQSUMMARY_PROC0_SECURE +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET _u(0x00000200) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_BITS _u(0x000000ff) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3 +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_MSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_LSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2 +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_MSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_LSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1 +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_MSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_LSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0 +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_MSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_LSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SD0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_BITS _u(0x00000008) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_MSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_LSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_MSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_LSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_GPIO_QSPI_SCLK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_BITS _u(0x00000002) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_MSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_LSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_BITS _u(0x00000001) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_MSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_LSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC0_SECURE_USBPHY_DP_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET _u(0x00000204) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_BITS _u(0x000000ff) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3 +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_MSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_LSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2 +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_MSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_LSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1 +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_MSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_LSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0 +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_MSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_LSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SD0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_BITS _u(0x00000008) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_MSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_LSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_MSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_LSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_GPIO_QSPI_SCLK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_BITS _u(0x00000002) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_MSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_LSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_BITS _u(0x00000001) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_MSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_LSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_USBPHY_DP_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_IRQSUMMARY_PROC1_SECURE +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET _u(0x00000208) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_BITS _u(0x000000ff) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3 +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_MSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_LSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2 +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_MSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_LSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1 +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_MSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_LSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0 +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_MSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_LSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SD0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_BITS _u(0x00000008) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_MSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_LSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_MSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_LSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_GPIO_QSPI_SCLK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_BITS _u(0x00000002) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_MSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_LSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_BITS _u(0x00000001) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_MSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_LSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC1_SECURE_USBPHY_DP_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET _u(0x0000020c) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_BITS _u(0x000000ff) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3 +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_MSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_LSB _u(7) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2 +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_MSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_LSB _u(6) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1 +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_MSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_LSB _u(5) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0 +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_MSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_LSB _u(4) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SD0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_BITS _u(0x00000008) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_MSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_LSB _u(3) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_MSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_LSB _u(2) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_GPIO_QSPI_SCLK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_BITS _u(0x00000002) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_MSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_LSB _u(1) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_BITS _u(0x00000001) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_MSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_LSB _u(0) +#define IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_USBPHY_DP_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET _u(0x00000210) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_BITS _u(0x000000ff) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_MSB _u(7) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_LSB _u(7) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_MSB _u(6) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_LSB _u(6) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_MSB _u(5) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_LSB _u(5) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_MSB _u(4) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_LSB _u(4) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SD0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_BITS _u(0x00000008) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_MSB _u(3) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_LSB _u(3) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_MSB _u(2) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_LSB _u(2) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_GPIO_QSPI_SCLK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_BITS _u(0x00000002) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_MSB _u(1) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_LSB _u(1) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_BITS _u(0x00000001) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_MSB _u(0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_LSB _u(0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_USBPHY_DP_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET _u(0x00000214) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_BITS _u(0x000000ff) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_BITS _u(0x00000080) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_MSB _u(7) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_LSB _u(7) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_BITS _u(0x00000040) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_MSB _u(6) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_LSB _u(6) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_BITS _u(0x00000020) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_MSB _u(5) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_LSB _u(5) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0 +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_BITS _u(0x00000010) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_MSB _u(4) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_LSB _u(4) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SD0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_BITS _u(0x00000008) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_MSB _u(3) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_LSB _u(3) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_BITS _u(0x00000004) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_MSB _u(2) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_LSB _u(2) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_GPIO_QSPI_SCLK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_BITS _u(0x00000002) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_MSB _u(1) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_LSB _u(1) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_RESET _u(0x0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_BITS _u(0x00000001) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_MSB _u(0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_LSB _u(0) +#define IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_USBPHY_DP_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_INTR +// Description : Raw Interrupts +#define IO_QSPI_INTR_OFFSET _u(0x00000218) +#define IO_QSPI_INTR_BITS _u(0xffffffff) +#define IO_QSPI_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DM_EDGE_LOW +#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_INTR_USBPHY_DM_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_INTR_USBPHY_DM_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_HIGH_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DP_EDGE_LOW +#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_INTR_USBPHY_DP_EDGE_LOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_INTR_USBPHY_DP_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_PROC0_INTE +// Description : Interrupt Enable for proc0 +#define IO_QSPI_PROC0_INTE_OFFSET _u(0x0000021c) +#define IO_QSPI_PROC0_INTE_BITS _u(0xffffffff) +#define IO_QSPI_PROC0_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_PROC0_INTE_USBPHY_DM_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_PROC0_INTE_USBPHY_DP_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC0_INTF +// Description : Interrupt Force for proc0 +#define IO_QSPI_PROC0_INTF_OFFSET _u(0x00000220) +#define IO_QSPI_PROC0_INTF_BITS _u(0xffffffff) +#define IO_QSPI_PROC0_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_PROC0_INTF_USBPHY_DM_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_PROC0_INTF_USBPHY_DP_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC0_INTS +// Description : Interrupt status after masking & forcing for proc0 +#define IO_QSPI_PROC0_INTS_OFFSET _u(0x00000224) +#define IO_QSPI_PROC0_INTS_BITS _u(0xffffffff) +#define IO_QSPI_PROC0_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_PROC0_INTS_USBPHY_DM_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_PROC0_INTS_USBPHY_DP_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_PROC1_INTE +// Description : Interrupt Enable for proc1 +#define IO_QSPI_PROC1_INTE_OFFSET _u(0x00000228) +#define IO_QSPI_PROC1_INTE_BITS _u(0xffffffff) +#define IO_QSPI_PROC1_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_PROC1_INTE_USBPHY_DM_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_PROC1_INTE_USBPHY_DP_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC1_INTF +// Description : Interrupt Force for proc1 +#define IO_QSPI_PROC1_INTF_OFFSET _u(0x0000022c) +#define IO_QSPI_PROC1_INTF_BITS _u(0xffffffff) +#define IO_QSPI_PROC1_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_PROC1_INTF_USBPHY_DM_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_PROC1_INTF_USBPHY_DP_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_PROC1_INTS +// Description : Interrupt status after masking & forcing for proc1 +#define IO_QSPI_PROC1_INTS_OFFSET _u(0x00000230) +#define IO_QSPI_PROC1_INTS_BITS _u(0xffffffff) +#define IO_QSPI_PROC1_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_PROC1_INTS_USBPHY_DM_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_PROC1_INTS_USBPHY_DP_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +// Register : IO_QSPI_DORMANT_WAKE_INTE +// Description : Interrupt Enable for dormant_wake +#define IO_QSPI_DORMANT_WAKE_INTE_OFFSET _u(0x00000234) +#define IO_QSPI_DORMANT_WAKE_INTE_BITS _u(0xffffffff) +#define IO_QSPI_DORMANT_WAKE_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DM_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTE_USBPHY_DP_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_DORMANT_WAKE_INTF +// Description : Interrupt Force for dormant_wake +#define IO_QSPI_DORMANT_WAKE_INTF_OFFSET _u(0x00000238) +#define IO_QSPI_DORMANT_WAKE_INTF_BITS _u(0xffffffff) +#define IO_QSPI_DORMANT_WAKE_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DM_LEVEL_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_EDGE_LOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_HIGH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTF_USBPHY_DP_LEVEL_LOW_ACCESS "RW" +// ============================================================================= +// Register : IO_QSPI_DORMANT_WAKE_INTS +// Description : Interrupt status after masking & forcing for dormant_wake +#define IO_QSPI_DORMANT_WAKE_INTS_OFFSET _u(0x0000023c) +#define IO_QSPI_DORMANT_WAKE_INTS_BITS _u(0xffffffff) +#define IO_QSPI_DORMANT_WAKE_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x80000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(31) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(31) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x40000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(30) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(30) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x20000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(29) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(29) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x10000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(28) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(28) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x08000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(27) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(27) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x04000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(26) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(26) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x02000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(25) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(25) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x01000000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(24) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(24) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00800000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(23) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00400000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(22) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00200000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(21) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00100000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(20) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00080000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(19) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00040000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(18) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00020000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(17) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00010000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(16) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00008000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(15) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00004000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(14) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00002000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(13) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00001000) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(12) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000800) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(11) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000400) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(10) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000200) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(9) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000100) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(8) +#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_BITS _u(0x00000080) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_MSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_LSB _u(7) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_BITS _u(0x00000040) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_MSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_LSB _u(6) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_BITS _u(0x00000020) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_MSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_LSB _u(5) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_BITS _u(0x00000010) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_MSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_LSB _u(4) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DM_LEVEL_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_BITS _u(0x00000008) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_MSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_LSB _u(3) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_BITS _u(0x00000004) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_MSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_LSB _u(2) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_EDGE_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_BITS _u(0x00000002) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_MSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_LSB _u(1) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_HIGH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_RESET _u(0x0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_BITS _u(0x00000001) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_MSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_LSB _u(0) +#define IO_QSPI_DORMANT_WAKE_INTS_USBPHY_DP_LEVEL_LOW_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_IO_QSPI_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/m33.h b/lib/pico-sdk/rp2350/hardware/regs/m33.h new file mode 100644 index 000000000000..b555317dec6f --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/m33.h @@ -0,0 +1,8988 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : M33 +// Version : 1 +// Bus type : apb +// Description : TEAL registers accessible through the debug interface +// ============================================================================= +#ifndef _HARDWARE_REGS_M33_H +#define _HARDWARE_REGS_M33_H +// ============================================================================= +// Register : M33_ITM_STIM0 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM0_OFFSET _u(0x00000000) +#define M33_ITM_STIM0_BITS _u(0xffffffff) +#define M33_ITM_STIM0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM0_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM0_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM0_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM0_STIMULUS_MSB _u(31) +#define M33_ITM_STIM0_STIMULUS_LSB _u(0) +#define M33_ITM_STIM0_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM1 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM1_OFFSET _u(0x00000004) +#define M33_ITM_STIM1_BITS _u(0xffffffff) +#define M33_ITM_STIM1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM1_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM1_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM1_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM1_STIMULUS_MSB _u(31) +#define M33_ITM_STIM1_STIMULUS_LSB _u(0) +#define M33_ITM_STIM1_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM2 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM2_OFFSET _u(0x00000008) +#define M33_ITM_STIM2_BITS _u(0xffffffff) +#define M33_ITM_STIM2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM2_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM2_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM2_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM2_STIMULUS_MSB _u(31) +#define M33_ITM_STIM2_STIMULUS_LSB _u(0) +#define M33_ITM_STIM2_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM3 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM3_OFFSET _u(0x0000000c) +#define M33_ITM_STIM3_BITS _u(0xffffffff) +#define M33_ITM_STIM3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM3_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM3_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM3_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM3_STIMULUS_MSB _u(31) +#define M33_ITM_STIM3_STIMULUS_LSB _u(0) +#define M33_ITM_STIM3_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM4 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM4_OFFSET _u(0x00000010) +#define M33_ITM_STIM4_BITS _u(0xffffffff) +#define M33_ITM_STIM4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM4_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM4_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM4_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM4_STIMULUS_MSB _u(31) +#define M33_ITM_STIM4_STIMULUS_LSB _u(0) +#define M33_ITM_STIM4_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM5 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM5_OFFSET _u(0x00000014) +#define M33_ITM_STIM5_BITS _u(0xffffffff) +#define M33_ITM_STIM5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM5_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM5_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM5_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM5_STIMULUS_MSB _u(31) +#define M33_ITM_STIM5_STIMULUS_LSB _u(0) +#define M33_ITM_STIM5_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM6 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM6_OFFSET _u(0x00000018) +#define M33_ITM_STIM6_BITS _u(0xffffffff) +#define M33_ITM_STIM6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM6_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM6_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM6_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM6_STIMULUS_MSB _u(31) +#define M33_ITM_STIM6_STIMULUS_LSB _u(0) +#define M33_ITM_STIM6_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM7 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM7_OFFSET _u(0x0000001c) +#define M33_ITM_STIM7_BITS _u(0xffffffff) +#define M33_ITM_STIM7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM7_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM7_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM7_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM7_STIMULUS_MSB _u(31) +#define M33_ITM_STIM7_STIMULUS_LSB _u(0) +#define M33_ITM_STIM7_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM8 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM8_OFFSET _u(0x00000020) +#define M33_ITM_STIM8_BITS _u(0xffffffff) +#define M33_ITM_STIM8_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM8_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM8_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM8_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM8_STIMULUS_MSB _u(31) +#define M33_ITM_STIM8_STIMULUS_LSB _u(0) +#define M33_ITM_STIM8_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM9 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM9_OFFSET _u(0x00000024) +#define M33_ITM_STIM9_BITS _u(0xffffffff) +#define M33_ITM_STIM9_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM9_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM9_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM9_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM9_STIMULUS_MSB _u(31) +#define M33_ITM_STIM9_STIMULUS_LSB _u(0) +#define M33_ITM_STIM9_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM10 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM10_OFFSET _u(0x00000028) +#define M33_ITM_STIM10_BITS _u(0xffffffff) +#define M33_ITM_STIM10_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM10_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM10_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM10_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM10_STIMULUS_MSB _u(31) +#define M33_ITM_STIM10_STIMULUS_LSB _u(0) +#define M33_ITM_STIM10_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM11 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM11_OFFSET _u(0x0000002c) +#define M33_ITM_STIM11_BITS _u(0xffffffff) +#define M33_ITM_STIM11_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM11_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM11_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM11_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM11_STIMULUS_MSB _u(31) +#define M33_ITM_STIM11_STIMULUS_LSB _u(0) +#define M33_ITM_STIM11_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM12 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM12_OFFSET _u(0x00000030) +#define M33_ITM_STIM12_BITS _u(0xffffffff) +#define M33_ITM_STIM12_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM12_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM12_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM12_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM12_STIMULUS_MSB _u(31) +#define M33_ITM_STIM12_STIMULUS_LSB _u(0) +#define M33_ITM_STIM12_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM13 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM13_OFFSET _u(0x00000034) +#define M33_ITM_STIM13_BITS _u(0xffffffff) +#define M33_ITM_STIM13_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM13_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM13_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM13_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM13_STIMULUS_MSB _u(31) +#define M33_ITM_STIM13_STIMULUS_LSB _u(0) +#define M33_ITM_STIM13_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM14 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM14_OFFSET _u(0x00000038) +#define M33_ITM_STIM14_BITS _u(0xffffffff) +#define M33_ITM_STIM14_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM14_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM14_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM14_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM14_STIMULUS_MSB _u(31) +#define M33_ITM_STIM14_STIMULUS_LSB _u(0) +#define M33_ITM_STIM14_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM15 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM15_OFFSET _u(0x0000003c) +#define M33_ITM_STIM15_BITS _u(0xffffffff) +#define M33_ITM_STIM15_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM15_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM15_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM15_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM15_STIMULUS_MSB _u(31) +#define M33_ITM_STIM15_STIMULUS_LSB _u(0) +#define M33_ITM_STIM15_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM16 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM16_OFFSET _u(0x00000040) +#define M33_ITM_STIM16_BITS _u(0xffffffff) +#define M33_ITM_STIM16_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM16_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM16_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM16_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM16_STIMULUS_MSB _u(31) +#define M33_ITM_STIM16_STIMULUS_LSB _u(0) +#define M33_ITM_STIM16_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM17 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM17_OFFSET _u(0x00000044) +#define M33_ITM_STIM17_BITS _u(0xffffffff) +#define M33_ITM_STIM17_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM17_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM17_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM17_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM17_STIMULUS_MSB _u(31) +#define M33_ITM_STIM17_STIMULUS_LSB _u(0) +#define M33_ITM_STIM17_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM18 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM18_OFFSET _u(0x00000048) +#define M33_ITM_STIM18_BITS _u(0xffffffff) +#define M33_ITM_STIM18_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM18_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM18_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM18_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM18_STIMULUS_MSB _u(31) +#define M33_ITM_STIM18_STIMULUS_LSB _u(0) +#define M33_ITM_STIM18_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM19 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM19_OFFSET _u(0x0000004c) +#define M33_ITM_STIM19_BITS _u(0xffffffff) +#define M33_ITM_STIM19_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM19_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM19_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM19_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM19_STIMULUS_MSB _u(31) +#define M33_ITM_STIM19_STIMULUS_LSB _u(0) +#define M33_ITM_STIM19_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM20 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM20_OFFSET _u(0x00000050) +#define M33_ITM_STIM20_BITS _u(0xffffffff) +#define M33_ITM_STIM20_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM20_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM20_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM20_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM20_STIMULUS_MSB _u(31) +#define M33_ITM_STIM20_STIMULUS_LSB _u(0) +#define M33_ITM_STIM20_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM21 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM21_OFFSET _u(0x00000054) +#define M33_ITM_STIM21_BITS _u(0xffffffff) +#define M33_ITM_STIM21_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM21_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM21_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM21_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM21_STIMULUS_MSB _u(31) +#define M33_ITM_STIM21_STIMULUS_LSB _u(0) +#define M33_ITM_STIM21_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM22 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM22_OFFSET _u(0x00000058) +#define M33_ITM_STIM22_BITS _u(0xffffffff) +#define M33_ITM_STIM22_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM22_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM22_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM22_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM22_STIMULUS_MSB _u(31) +#define M33_ITM_STIM22_STIMULUS_LSB _u(0) +#define M33_ITM_STIM22_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM23 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM23_OFFSET _u(0x0000005c) +#define M33_ITM_STIM23_BITS _u(0xffffffff) +#define M33_ITM_STIM23_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM23_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM23_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM23_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM23_STIMULUS_MSB _u(31) +#define M33_ITM_STIM23_STIMULUS_LSB _u(0) +#define M33_ITM_STIM23_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM24 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM24_OFFSET _u(0x00000060) +#define M33_ITM_STIM24_BITS _u(0xffffffff) +#define M33_ITM_STIM24_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM24_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM24_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM24_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM24_STIMULUS_MSB _u(31) +#define M33_ITM_STIM24_STIMULUS_LSB _u(0) +#define M33_ITM_STIM24_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM25 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM25_OFFSET _u(0x00000064) +#define M33_ITM_STIM25_BITS _u(0xffffffff) +#define M33_ITM_STIM25_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM25_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM25_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM25_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM25_STIMULUS_MSB _u(31) +#define M33_ITM_STIM25_STIMULUS_LSB _u(0) +#define M33_ITM_STIM25_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM26 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM26_OFFSET _u(0x00000068) +#define M33_ITM_STIM26_BITS _u(0xffffffff) +#define M33_ITM_STIM26_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM26_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM26_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM26_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM26_STIMULUS_MSB _u(31) +#define M33_ITM_STIM26_STIMULUS_LSB _u(0) +#define M33_ITM_STIM26_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM27 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM27_OFFSET _u(0x0000006c) +#define M33_ITM_STIM27_BITS _u(0xffffffff) +#define M33_ITM_STIM27_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM27_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM27_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM27_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM27_STIMULUS_MSB _u(31) +#define M33_ITM_STIM27_STIMULUS_LSB _u(0) +#define M33_ITM_STIM27_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM28 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM28_OFFSET _u(0x00000070) +#define M33_ITM_STIM28_BITS _u(0xffffffff) +#define M33_ITM_STIM28_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM28_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM28_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM28_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM28_STIMULUS_MSB _u(31) +#define M33_ITM_STIM28_STIMULUS_LSB _u(0) +#define M33_ITM_STIM28_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM29 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM29_OFFSET _u(0x00000074) +#define M33_ITM_STIM29_BITS _u(0xffffffff) +#define M33_ITM_STIM29_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM29_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM29_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM29_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM29_STIMULUS_MSB _u(31) +#define M33_ITM_STIM29_STIMULUS_LSB _u(0) +#define M33_ITM_STIM29_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM30 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM30_OFFSET _u(0x00000078) +#define M33_ITM_STIM30_BITS _u(0xffffffff) +#define M33_ITM_STIM30_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM30_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM30_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM30_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM30_STIMULUS_MSB _u(31) +#define M33_ITM_STIM30_STIMULUS_LSB _u(0) +#define M33_ITM_STIM30_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_STIM31 +// Description : Provides the interface for generating Instrumentation packets +#define M33_ITM_STIM31_OFFSET _u(0x0000007c) +#define M33_ITM_STIM31_BITS _u(0xffffffff) +#define M33_ITM_STIM31_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_STIM31_STIMULUS +// Description : Data to write to the Stimulus Port FIFO, for forwarding as an +// Instrumentation packet. The size of write access determines the +// type of Instrumentation packet generated. +#define M33_ITM_STIM31_STIMULUS_RESET _u(0x00000000) +#define M33_ITM_STIM31_STIMULUS_BITS _u(0xffffffff) +#define M33_ITM_STIM31_STIMULUS_MSB _u(31) +#define M33_ITM_STIM31_STIMULUS_LSB _u(0) +#define M33_ITM_STIM31_STIMULUS_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_TER0 +// Description : Provide an individual enable bit for each ITM_STIM register +#define M33_ITM_TER0_OFFSET _u(0x00000e00) +#define M33_ITM_TER0_BITS _u(0xffffffff) +#define M33_ITM_TER0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TER0_STIMENA +// Description : For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + +// m) is enabled +#define M33_ITM_TER0_STIMENA_RESET _u(0x00000000) +#define M33_ITM_TER0_STIMENA_BITS _u(0xffffffff) +#define M33_ITM_TER0_STIMENA_MSB _u(31) +#define M33_ITM_TER0_STIMENA_LSB _u(0) +#define M33_ITM_TER0_STIMENA_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_TPR +// Description : Controls which stimulus ports can be accessed by unprivileged +// code +#define M33_ITM_TPR_OFFSET _u(0x00000e40) +#define M33_ITM_TPR_BITS _u(0x0000000f) +#define M33_ITM_TPR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TPR_PRIVMASK +// Description : Bit mask to enable tracing on ITM stimulus ports +#define M33_ITM_TPR_PRIVMASK_RESET _u(0x0) +#define M33_ITM_TPR_PRIVMASK_BITS _u(0x0000000f) +#define M33_ITM_TPR_PRIVMASK_MSB _u(3) +#define M33_ITM_TPR_PRIVMASK_LSB _u(0) +#define M33_ITM_TPR_PRIVMASK_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_TCR +// Description : Configures and controls transfers through the ITM interface +#define M33_ITM_TCR_OFFSET _u(0x00000e80) +#define M33_ITM_TCR_BITS _u(0x00ff0f3f) +#define M33_ITM_TCR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_BUSY +// Description : Indicates whether the ITM is currently processing events +#define M33_ITM_TCR_BUSY_RESET _u(0x0) +#define M33_ITM_TCR_BUSY_BITS _u(0x00800000) +#define M33_ITM_TCR_BUSY_MSB _u(23) +#define M33_ITM_TCR_BUSY_LSB _u(23) +#define M33_ITM_TCR_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_TRACEBUSID +// Description : Identifier for multi-source trace stream formatting. If multi- +// source trace is in use, the debugger must write a unique non- +// zero trace ID value to this field +#define M33_ITM_TCR_TRACEBUSID_RESET _u(0x00) +#define M33_ITM_TCR_TRACEBUSID_BITS _u(0x007f0000) +#define M33_ITM_TCR_TRACEBUSID_MSB _u(22) +#define M33_ITM_TCR_TRACEBUSID_LSB _u(16) +#define M33_ITM_TCR_TRACEBUSID_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_GTSFREQ +// Description : Defines how often the ITM generates a global timestamp, based +// on the global timestamp clock frequency, or disables generation +// of global timestamps +#define M33_ITM_TCR_GTSFREQ_RESET _u(0x0) +#define M33_ITM_TCR_GTSFREQ_BITS _u(0x00000c00) +#define M33_ITM_TCR_GTSFREQ_MSB _u(11) +#define M33_ITM_TCR_GTSFREQ_LSB _u(10) +#define M33_ITM_TCR_GTSFREQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_TSPRESCALE +// Description : Local timestamp prescaler, used with the trace packet reference +// clock +#define M33_ITM_TCR_TSPRESCALE_RESET _u(0x0) +#define M33_ITM_TCR_TSPRESCALE_BITS _u(0x00000300) +#define M33_ITM_TCR_TSPRESCALE_MSB _u(9) +#define M33_ITM_TCR_TSPRESCALE_LSB _u(8) +#define M33_ITM_TCR_TSPRESCALE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_STALLENA +// Description : Stall the PE to guarantee delivery of Data Trace packets. +#define M33_ITM_TCR_STALLENA_RESET _u(0x0) +#define M33_ITM_TCR_STALLENA_BITS _u(0x00000020) +#define M33_ITM_TCR_STALLENA_MSB _u(5) +#define M33_ITM_TCR_STALLENA_LSB _u(5) +#define M33_ITM_TCR_STALLENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_SWOENA +// Description : Enables asynchronous clocking of the timestamp counter +#define M33_ITM_TCR_SWOENA_RESET _u(0x0) +#define M33_ITM_TCR_SWOENA_BITS _u(0x00000010) +#define M33_ITM_TCR_SWOENA_MSB _u(4) +#define M33_ITM_TCR_SWOENA_LSB _u(4) +#define M33_ITM_TCR_SWOENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_TXENA +// Description : Enables forwarding of hardware event packet from the DWT unit +// to the ITM for output to the TPIU +#define M33_ITM_TCR_TXENA_RESET _u(0x0) +#define M33_ITM_TCR_TXENA_BITS _u(0x00000008) +#define M33_ITM_TCR_TXENA_MSB _u(3) +#define M33_ITM_TCR_TXENA_LSB _u(3) +#define M33_ITM_TCR_TXENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_SYNCENA +// Description : Enables Synchronization packet transmission for a synchronous +// TPIU +#define M33_ITM_TCR_SYNCENA_RESET _u(0x0) +#define M33_ITM_TCR_SYNCENA_BITS _u(0x00000004) +#define M33_ITM_TCR_SYNCENA_MSB _u(2) +#define M33_ITM_TCR_SYNCENA_LSB _u(2) +#define M33_ITM_TCR_SYNCENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_TSENA +// Description : Enables Local timestamp generation +#define M33_ITM_TCR_TSENA_RESET _u(0x0) +#define M33_ITM_TCR_TSENA_BITS _u(0x00000002) +#define M33_ITM_TCR_TSENA_MSB _u(1) +#define M33_ITM_TCR_TSENA_LSB _u(1) +#define M33_ITM_TCR_TSENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_TCR_ITMENA +// Description : Enables the ITM +#define M33_ITM_TCR_ITMENA_RESET _u(0x0) +#define M33_ITM_TCR_ITMENA_BITS _u(0x00000001) +#define M33_ITM_TCR_ITMENA_MSB _u(0) +#define M33_ITM_TCR_ITMENA_LSB _u(0) +#define M33_ITM_TCR_ITMENA_ACCESS "RW" +// ============================================================================= +// Register : M33_INT_ATREADY +// Description : Integration Mode: Read ATB Ready +#define M33_INT_ATREADY_OFFSET _u(0x00000ef0) +#define M33_INT_ATREADY_BITS _u(0x00000003) +#define M33_INT_ATREADY_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_INT_ATREADY_AFVALID +// Description : A read of this bit returns the value of AFVALID +#define M33_INT_ATREADY_AFVALID_RESET _u(0x0) +#define M33_INT_ATREADY_AFVALID_BITS _u(0x00000002) +#define M33_INT_ATREADY_AFVALID_MSB _u(1) +#define M33_INT_ATREADY_AFVALID_LSB _u(1) +#define M33_INT_ATREADY_AFVALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_INT_ATREADY_ATREADY +// Description : A read of this bit returns the value of ATREADY +#define M33_INT_ATREADY_ATREADY_RESET _u(0x0) +#define M33_INT_ATREADY_ATREADY_BITS _u(0x00000001) +#define M33_INT_ATREADY_ATREADY_MSB _u(0) +#define M33_INT_ATREADY_ATREADY_LSB _u(0) +#define M33_INT_ATREADY_ATREADY_ACCESS "RO" +// ============================================================================= +// Register : M33_INT_ATVALID +// Description : Integration Mode: Write ATB Valid +#define M33_INT_ATVALID_OFFSET _u(0x00000ef8) +#define M33_INT_ATVALID_BITS _u(0x00000003) +#define M33_INT_ATVALID_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_INT_ATVALID_AFREADY +// Description : A write to this bit gives the value of AFREADY +#define M33_INT_ATVALID_AFREADY_RESET _u(0x0) +#define M33_INT_ATVALID_AFREADY_BITS _u(0x00000002) +#define M33_INT_ATVALID_AFREADY_MSB _u(1) +#define M33_INT_ATVALID_AFREADY_LSB _u(1) +#define M33_INT_ATVALID_AFREADY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_INT_ATVALID_ATREADY +// Description : A write to this bit gives the value of ATVALID +#define M33_INT_ATVALID_ATREADY_RESET _u(0x0) +#define M33_INT_ATVALID_ATREADY_BITS _u(0x00000001) +#define M33_INT_ATVALID_ATREADY_MSB _u(0) +#define M33_INT_ATVALID_ATREADY_LSB _u(0) +#define M33_INT_ATVALID_ATREADY_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_ITCTRL +// Description : Integration Mode Control Register +#define M33_ITM_ITCTRL_OFFSET _u(0x00000f00) +#define M33_ITM_ITCTRL_BITS _u(0x00000001) +#define M33_ITM_ITCTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_ITCTRL_IME +// Description : Integration mode enable bit - The possible values are: 0 - The +// trace unit is not in integration mode. 1 - The trace unit is in +// integration mode. This mode enables: A debug agent to perform +// topology detection. SoC test software to perform integration +// testing. +#define M33_ITM_ITCTRL_IME_RESET _u(0x0) +#define M33_ITM_ITCTRL_IME_BITS _u(0x00000001) +#define M33_ITM_ITCTRL_IME_MSB _u(0) +#define M33_ITM_ITCTRL_IME_LSB _u(0) +#define M33_ITM_ITCTRL_IME_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_DEVARCH +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_DEVARCH_OFFSET _u(0x00000fbc) +#define M33_ITM_DEVARCH_BITS _u(0xffffffff) +#define M33_ITM_DEVARCH_RESET _u(0x47701a01) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_DEVARCH_ARCHITECT +// Description : Defines the architect of the component. Bits [31:28] are the +// JEP106 continuation code (JEP106 bank ID, minus 1) and bits +// [27:21] are the JEP106 ID code. +#define M33_ITM_DEVARCH_ARCHITECT_RESET _u(0x23b) +#define M33_ITM_DEVARCH_ARCHITECT_BITS _u(0xffe00000) +#define M33_ITM_DEVARCH_ARCHITECT_MSB _u(31) +#define M33_ITM_DEVARCH_ARCHITECT_LSB _u(21) +#define M33_ITM_DEVARCH_ARCHITECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_DEVARCH_PRESENT +// Description : Defines that the DEVARCH register is present +#define M33_ITM_DEVARCH_PRESENT_RESET _u(0x1) +#define M33_ITM_DEVARCH_PRESENT_BITS _u(0x00100000) +#define M33_ITM_DEVARCH_PRESENT_MSB _u(20) +#define M33_ITM_DEVARCH_PRESENT_LSB _u(20) +#define M33_ITM_DEVARCH_PRESENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_DEVARCH_REVISION +// Description : Defines the architecture revision of the component +#define M33_ITM_DEVARCH_REVISION_RESET _u(0x0) +#define M33_ITM_DEVARCH_REVISION_BITS _u(0x000f0000) +#define M33_ITM_DEVARCH_REVISION_MSB _u(19) +#define M33_ITM_DEVARCH_REVISION_LSB _u(16) +#define M33_ITM_DEVARCH_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_DEVARCH_ARCHVER +// Description : Defines the architecture version of the component +#define M33_ITM_DEVARCH_ARCHVER_RESET _u(0x1) +#define M33_ITM_DEVARCH_ARCHVER_BITS _u(0x0000f000) +#define M33_ITM_DEVARCH_ARCHVER_MSB _u(15) +#define M33_ITM_DEVARCH_ARCHVER_LSB _u(12) +#define M33_ITM_DEVARCH_ARCHVER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_DEVARCH_ARCHPART +// Description : Defines the architecture of the component +#define M33_ITM_DEVARCH_ARCHPART_RESET _u(0xa01) +#define M33_ITM_DEVARCH_ARCHPART_BITS _u(0x00000fff) +#define M33_ITM_DEVARCH_ARCHPART_MSB _u(11) +#define M33_ITM_DEVARCH_ARCHPART_LSB _u(0) +#define M33_ITM_DEVARCH_ARCHPART_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_DEVTYPE +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_DEVTYPE_OFFSET _u(0x00000fcc) +#define M33_ITM_DEVTYPE_BITS _u(0x000000ff) +#define M33_ITM_DEVTYPE_RESET _u(0x00000043) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_DEVTYPE_SUB +// Description : Component sub-type +#define M33_ITM_DEVTYPE_SUB_RESET _u(0x4) +#define M33_ITM_DEVTYPE_SUB_BITS _u(0x000000f0) +#define M33_ITM_DEVTYPE_SUB_MSB _u(7) +#define M33_ITM_DEVTYPE_SUB_LSB _u(4) +#define M33_ITM_DEVTYPE_SUB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_DEVTYPE_MAJOR +// Description : Component major type +#define M33_ITM_DEVTYPE_MAJOR_RESET _u(0x3) +#define M33_ITM_DEVTYPE_MAJOR_BITS _u(0x0000000f) +#define M33_ITM_DEVTYPE_MAJOR_MSB _u(3) +#define M33_ITM_DEVTYPE_MAJOR_LSB _u(0) +#define M33_ITM_DEVTYPE_MAJOR_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_PIDR4 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR4_OFFSET _u(0x00000fd0) +#define M33_ITM_PIDR4_BITS _u(0x000000ff) +#define M33_ITM_PIDR4_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR4_SIZE +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR4_SIZE_RESET _u(0x0) +#define M33_ITM_PIDR4_SIZE_BITS _u(0x000000f0) +#define M33_ITM_PIDR4_SIZE_MSB _u(7) +#define M33_ITM_PIDR4_SIZE_LSB _u(4) +#define M33_ITM_PIDR4_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR4_DES_2 +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR4_DES_2_RESET _u(0x4) +#define M33_ITM_PIDR4_DES_2_BITS _u(0x0000000f) +#define M33_ITM_PIDR4_DES_2_MSB _u(3) +#define M33_ITM_PIDR4_DES_2_LSB _u(0) +#define M33_ITM_PIDR4_DES_2_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_PIDR5 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR5_OFFSET _u(0x00000fd4) +#define M33_ITM_PIDR5_BITS _u(0x00000000) +#define M33_ITM_PIDR5_RESET _u(0x00000000) +#define M33_ITM_PIDR5_MSB _u(31) +#define M33_ITM_PIDR5_LSB _u(0) +#define M33_ITM_PIDR5_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_PIDR6 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR6_OFFSET _u(0x00000fd8) +#define M33_ITM_PIDR6_BITS _u(0x00000000) +#define M33_ITM_PIDR6_RESET _u(0x00000000) +#define M33_ITM_PIDR6_MSB _u(31) +#define M33_ITM_PIDR6_LSB _u(0) +#define M33_ITM_PIDR6_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_PIDR7 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR7_OFFSET _u(0x00000fdc) +#define M33_ITM_PIDR7_BITS _u(0x00000000) +#define M33_ITM_PIDR7_RESET _u(0x00000000) +#define M33_ITM_PIDR7_MSB _u(31) +#define M33_ITM_PIDR7_LSB _u(0) +#define M33_ITM_PIDR7_ACCESS "RW" +// ============================================================================= +// Register : M33_ITM_PIDR0 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR0_OFFSET _u(0x00000fe0) +#define M33_ITM_PIDR0_BITS _u(0x000000ff) +#define M33_ITM_PIDR0_RESET _u(0x00000021) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR0_PART_0 +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR0_PART_0_RESET _u(0x21) +#define M33_ITM_PIDR0_PART_0_BITS _u(0x000000ff) +#define M33_ITM_PIDR0_PART_0_MSB _u(7) +#define M33_ITM_PIDR0_PART_0_LSB _u(0) +#define M33_ITM_PIDR0_PART_0_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_PIDR1 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR1_OFFSET _u(0x00000fe4) +#define M33_ITM_PIDR1_BITS _u(0x000000ff) +#define M33_ITM_PIDR1_RESET _u(0x000000bd) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR1_DES_0 +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR1_DES_0_RESET _u(0xb) +#define M33_ITM_PIDR1_DES_0_BITS _u(0x000000f0) +#define M33_ITM_PIDR1_DES_0_MSB _u(7) +#define M33_ITM_PIDR1_DES_0_LSB _u(4) +#define M33_ITM_PIDR1_DES_0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR1_PART_1 +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR1_PART_1_RESET _u(0xd) +#define M33_ITM_PIDR1_PART_1_BITS _u(0x0000000f) +#define M33_ITM_PIDR1_PART_1_MSB _u(3) +#define M33_ITM_PIDR1_PART_1_LSB _u(0) +#define M33_ITM_PIDR1_PART_1_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_PIDR2 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR2_OFFSET _u(0x00000fe8) +#define M33_ITM_PIDR2_BITS _u(0x000000ff) +#define M33_ITM_PIDR2_RESET _u(0x0000000b) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR2_REVISION +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR2_REVISION_RESET _u(0x0) +#define M33_ITM_PIDR2_REVISION_BITS _u(0x000000f0) +#define M33_ITM_PIDR2_REVISION_MSB _u(7) +#define M33_ITM_PIDR2_REVISION_LSB _u(4) +#define M33_ITM_PIDR2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR2_JEDEC +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR2_JEDEC_RESET _u(0x1) +#define M33_ITM_PIDR2_JEDEC_BITS _u(0x00000008) +#define M33_ITM_PIDR2_JEDEC_MSB _u(3) +#define M33_ITM_PIDR2_JEDEC_LSB _u(3) +#define M33_ITM_PIDR2_JEDEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR2_DES_1 +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR2_DES_1_RESET _u(0x3) +#define M33_ITM_PIDR2_DES_1_BITS _u(0x00000007) +#define M33_ITM_PIDR2_DES_1_MSB _u(2) +#define M33_ITM_PIDR2_DES_1_LSB _u(0) +#define M33_ITM_PIDR2_DES_1_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_PIDR3 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_PIDR3_OFFSET _u(0x00000fec) +#define M33_ITM_PIDR3_BITS _u(0x000000ff) +#define M33_ITM_PIDR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR3_REVAND +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR3_REVAND_RESET _u(0x0) +#define M33_ITM_PIDR3_REVAND_BITS _u(0x000000f0) +#define M33_ITM_PIDR3_REVAND_MSB _u(7) +#define M33_ITM_PIDR3_REVAND_LSB _u(4) +#define M33_ITM_PIDR3_REVAND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_PIDR3_CMOD +// Description : See CoreSight Architecture Specification +#define M33_ITM_PIDR3_CMOD_RESET _u(0x0) +#define M33_ITM_PIDR3_CMOD_BITS _u(0x0000000f) +#define M33_ITM_PIDR3_CMOD_MSB _u(3) +#define M33_ITM_PIDR3_CMOD_LSB _u(0) +#define M33_ITM_PIDR3_CMOD_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_CIDR0 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_CIDR0_OFFSET _u(0x00000ff0) +#define M33_ITM_CIDR0_BITS _u(0x000000ff) +#define M33_ITM_CIDR0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_CIDR0_PRMBL_0 +// Description : See CoreSight Architecture Specification +#define M33_ITM_CIDR0_PRMBL_0_RESET _u(0x0d) +#define M33_ITM_CIDR0_PRMBL_0_BITS _u(0x000000ff) +#define M33_ITM_CIDR0_PRMBL_0_MSB _u(7) +#define M33_ITM_CIDR0_PRMBL_0_LSB _u(0) +#define M33_ITM_CIDR0_PRMBL_0_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_CIDR1 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_CIDR1_OFFSET _u(0x00000ff4) +#define M33_ITM_CIDR1_BITS _u(0x000000ff) +#define M33_ITM_CIDR1_RESET _u(0x00000090) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_CIDR1_CLASS +// Description : See CoreSight Architecture Specification +#define M33_ITM_CIDR1_CLASS_RESET _u(0x9) +#define M33_ITM_CIDR1_CLASS_BITS _u(0x000000f0) +#define M33_ITM_CIDR1_CLASS_MSB _u(7) +#define M33_ITM_CIDR1_CLASS_LSB _u(4) +#define M33_ITM_CIDR1_CLASS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ITM_CIDR1_PRMBL_1 +// Description : See CoreSight Architecture Specification +#define M33_ITM_CIDR1_PRMBL_1_RESET _u(0x0) +#define M33_ITM_CIDR1_PRMBL_1_BITS _u(0x0000000f) +#define M33_ITM_CIDR1_PRMBL_1_MSB _u(3) +#define M33_ITM_CIDR1_PRMBL_1_LSB _u(0) +#define M33_ITM_CIDR1_PRMBL_1_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_CIDR2 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_CIDR2_OFFSET _u(0x00000ff8) +#define M33_ITM_CIDR2_BITS _u(0x000000ff) +#define M33_ITM_CIDR2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_CIDR2_PRMBL_2 +// Description : See CoreSight Architecture Specification +#define M33_ITM_CIDR2_PRMBL_2_RESET _u(0x05) +#define M33_ITM_CIDR2_PRMBL_2_BITS _u(0x000000ff) +#define M33_ITM_CIDR2_PRMBL_2_MSB _u(7) +#define M33_ITM_CIDR2_PRMBL_2_LSB _u(0) +#define M33_ITM_CIDR2_PRMBL_2_ACCESS "RO" +// ============================================================================= +// Register : M33_ITM_CIDR3 +// Description : Provides CoreSight discovery information for the ITM +#define M33_ITM_CIDR3_OFFSET _u(0x00000ffc) +#define M33_ITM_CIDR3_BITS _u(0x000000ff) +#define M33_ITM_CIDR3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : M33_ITM_CIDR3_PRMBL_3 +// Description : See CoreSight Architecture Specification +#define M33_ITM_CIDR3_PRMBL_3_RESET _u(0xb1) +#define M33_ITM_CIDR3_PRMBL_3_BITS _u(0x000000ff) +#define M33_ITM_CIDR3_PRMBL_3_MSB _u(7) +#define M33_ITM_CIDR3_PRMBL_3_LSB _u(0) +#define M33_ITM_CIDR3_PRMBL_3_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_CTRL +// Description : Provides configuration and status information for the DWT unit, +// and used to control features of the unit +#define M33_DWT_CTRL_OFFSET _u(0x00001000) +#define M33_DWT_CTRL_BITS _u(0xffff1fff) +#define M33_DWT_CTRL_RESET _u(0x73741824) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_NUMCOMP +// Description : Number of DWT comparators implemented +#define M33_DWT_CTRL_NUMCOMP_RESET _u(0x7) +#define M33_DWT_CTRL_NUMCOMP_BITS _u(0xf0000000) +#define M33_DWT_CTRL_NUMCOMP_MSB _u(31) +#define M33_DWT_CTRL_NUMCOMP_LSB _u(28) +#define M33_DWT_CTRL_NUMCOMP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_NOTRCPKT +// Description : Indicates whether the implementation does not support trace +#define M33_DWT_CTRL_NOTRCPKT_RESET _u(0x0) +#define M33_DWT_CTRL_NOTRCPKT_BITS _u(0x08000000) +#define M33_DWT_CTRL_NOTRCPKT_MSB _u(27) +#define M33_DWT_CTRL_NOTRCPKT_LSB _u(27) +#define M33_DWT_CTRL_NOTRCPKT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_NOEXTTRIG +// Description : Reserved, RAZ +#define M33_DWT_CTRL_NOEXTTRIG_RESET _u(0x0) +#define M33_DWT_CTRL_NOEXTTRIG_BITS _u(0x04000000) +#define M33_DWT_CTRL_NOEXTTRIG_MSB _u(26) +#define M33_DWT_CTRL_NOEXTTRIG_LSB _u(26) +#define M33_DWT_CTRL_NOEXTTRIG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_NOCYCCNT +// Description : Indicates whether the implementation does not include a cycle +// counter +#define M33_DWT_CTRL_NOCYCCNT_RESET _u(0x1) +#define M33_DWT_CTRL_NOCYCCNT_BITS _u(0x02000000) +#define M33_DWT_CTRL_NOCYCCNT_MSB _u(25) +#define M33_DWT_CTRL_NOCYCCNT_LSB _u(25) +#define M33_DWT_CTRL_NOCYCCNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_NOPRFCNT +// Description : Indicates whether the implementation does not include the +// profiling counters +#define M33_DWT_CTRL_NOPRFCNT_RESET _u(0x1) +#define M33_DWT_CTRL_NOPRFCNT_BITS _u(0x01000000) +#define M33_DWT_CTRL_NOPRFCNT_MSB _u(24) +#define M33_DWT_CTRL_NOPRFCNT_LSB _u(24) +#define M33_DWT_CTRL_NOPRFCNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_CYCDISS +// Description : Controls whether the cycle counter is disabled in Secure state +#define M33_DWT_CTRL_CYCDISS_RESET _u(0x0) +#define M33_DWT_CTRL_CYCDISS_BITS _u(0x00800000) +#define M33_DWT_CTRL_CYCDISS_MSB _u(23) +#define M33_DWT_CTRL_CYCDISS_LSB _u(23) +#define M33_DWT_CTRL_CYCDISS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_CYCEVTENA +// Description : Enables Event Counter packet generation on POSTCNT underflow +#define M33_DWT_CTRL_CYCEVTENA_RESET _u(0x1) +#define M33_DWT_CTRL_CYCEVTENA_BITS _u(0x00400000) +#define M33_DWT_CTRL_CYCEVTENA_MSB _u(22) +#define M33_DWT_CTRL_CYCEVTENA_LSB _u(22) +#define M33_DWT_CTRL_CYCEVTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_FOLDEVTENA +// Description : Enables DWT_FOLDCNT counter +#define M33_DWT_CTRL_FOLDEVTENA_RESET _u(0x1) +#define M33_DWT_CTRL_FOLDEVTENA_BITS _u(0x00200000) +#define M33_DWT_CTRL_FOLDEVTENA_MSB _u(21) +#define M33_DWT_CTRL_FOLDEVTENA_LSB _u(21) +#define M33_DWT_CTRL_FOLDEVTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_LSUEVTENA +// Description : Enables DWT_LSUCNT counter +#define M33_DWT_CTRL_LSUEVTENA_RESET _u(0x1) +#define M33_DWT_CTRL_LSUEVTENA_BITS _u(0x00100000) +#define M33_DWT_CTRL_LSUEVTENA_MSB _u(20) +#define M33_DWT_CTRL_LSUEVTENA_LSB _u(20) +#define M33_DWT_CTRL_LSUEVTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_SLEEPEVTENA +// Description : Enable DWT_SLEEPCNT counter +#define M33_DWT_CTRL_SLEEPEVTENA_RESET _u(0x0) +#define M33_DWT_CTRL_SLEEPEVTENA_BITS _u(0x00080000) +#define M33_DWT_CTRL_SLEEPEVTENA_MSB _u(19) +#define M33_DWT_CTRL_SLEEPEVTENA_LSB _u(19) +#define M33_DWT_CTRL_SLEEPEVTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_EXCEVTENA +// Description : Enables DWT_EXCCNT counter +#define M33_DWT_CTRL_EXCEVTENA_RESET _u(0x1) +#define M33_DWT_CTRL_EXCEVTENA_BITS _u(0x00040000) +#define M33_DWT_CTRL_EXCEVTENA_MSB _u(18) +#define M33_DWT_CTRL_EXCEVTENA_LSB _u(18) +#define M33_DWT_CTRL_EXCEVTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_CPIEVTENA +// Description : Enables DWT_CPICNT counter +#define M33_DWT_CTRL_CPIEVTENA_RESET _u(0x0) +#define M33_DWT_CTRL_CPIEVTENA_BITS _u(0x00020000) +#define M33_DWT_CTRL_CPIEVTENA_MSB _u(17) +#define M33_DWT_CTRL_CPIEVTENA_LSB _u(17) +#define M33_DWT_CTRL_CPIEVTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_EXTTRCENA +// Description : Enables generation of Exception Trace packets +#define M33_DWT_CTRL_EXTTRCENA_RESET _u(0x0) +#define M33_DWT_CTRL_EXTTRCENA_BITS _u(0x00010000) +#define M33_DWT_CTRL_EXTTRCENA_MSB _u(16) +#define M33_DWT_CTRL_EXTTRCENA_LSB _u(16) +#define M33_DWT_CTRL_EXTTRCENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_PCSAMPLENA +// Description : Enables use of POSTCNT counter as a timer for Periodic PC +// Sample packet generation +#define M33_DWT_CTRL_PCSAMPLENA_RESET _u(0x1) +#define M33_DWT_CTRL_PCSAMPLENA_BITS _u(0x00001000) +#define M33_DWT_CTRL_PCSAMPLENA_MSB _u(12) +#define M33_DWT_CTRL_PCSAMPLENA_LSB _u(12) +#define M33_DWT_CTRL_PCSAMPLENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_SYNCTAP +// Description : Selects the position of the synchronization packet counter tap +// on the CYCCNT counter. This determines the Synchronization +// packet rate +#define M33_DWT_CTRL_SYNCTAP_RESET _u(0x2) +#define M33_DWT_CTRL_SYNCTAP_BITS _u(0x00000c00) +#define M33_DWT_CTRL_SYNCTAP_MSB _u(11) +#define M33_DWT_CTRL_SYNCTAP_LSB _u(10) +#define M33_DWT_CTRL_SYNCTAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_CYCTAP +// Description : Selects the position of the POSTCNT tap on the CYCCNT counter +#define M33_DWT_CTRL_CYCTAP_RESET _u(0x0) +#define M33_DWT_CTRL_CYCTAP_BITS _u(0x00000200) +#define M33_DWT_CTRL_CYCTAP_MSB _u(9) +#define M33_DWT_CTRL_CYCTAP_LSB _u(9) +#define M33_DWT_CTRL_CYCTAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_POSTINIT +// Description : Initial value for the POSTCNT counter +#define M33_DWT_CTRL_POSTINIT_RESET _u(0x1) +#define M33_DWT_CTRL_POSTINIT_BITS _u(0x000001e0) +#define M33_DWT_CTRL_POSTINIT_MSB _u(8) +#define M33_DWT_CTRL_POSTINIT_LSB _u(5) +#define M33_DWT_CTRL_POSTINIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_POSTPRESET +// Description : Reload value for the POSTCNT counter +#define M33_DWT_CTRL_POSTPRESET_RESET _u(0x2) +#define M33_DWT_CTRL_POSTPRESET_BITS _u(0x0000001e) +#define M33_DWT_CTRL_POSTPRESET_MSB _u(4) +#define M33_DWT_CTRL_POSTPRESET_LSB _u(1) +#define M33_DWT_CTRL_POSTPRESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CTRL_CYCCNTENA +// Description : Enables CYCCNT +#define M33_DWT_CTRL_CYCCNTENA_RESET _u(0x0) +#define M33_DWT_CTRL_CYCCNTENA_BITS _u(0x00000001) +#define M33_DWT_CTRL_CYCCNTENA_MSB _u(0) +#define M33_DWT_CTRL_CYCCNTENA_LSB _u(0) +#define M33_DWT_CTRL_CYCCNTENA_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_CYCCNT +// Description : Shows or sets the value of the processor cycle counter, CYCCNT +#define M33_DWT_CYCCNT_OFFSET _u(0x00001004) +#define M33_DWT_CYCCNT_BITS _u(0xffffffff) +#define M33_DWT_CYCCNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CYCCNT_CYCCNT +// Description : Increments one on each processor clock cycle when +// DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, +// CYCCNT wraps to zero +#define M33_DWT_CYCCNT_CYCCNT_RESET _u(0x00000000) +#define M33_DWT_CYCCNT_CYCCNT_BITS _u(0xffffffff) +#define M33_DWT_CYCCNT_CYCCNT_MSB _u(31) +#define M33_DWT_CYCCNT_CYCCNT_LSB _u(0) +#define M33_DWT_CYCCNT_CYCCNT_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_EXCCNT +// Description : Counts the total cycles spent in exception processing +#define M33_DWT_EXCCNT_OFFSET _u(0x0000100c) +#define M33_DWT_EXCCNT_BITS _u(0x000000ff) +#define M33_DWT_EXCCNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_EXCCNT_EXCCNT +// Description : Counts one on each cycle when all of the following are true: - +// DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction +// is executed, see DWT_CPICNT. - An exception-entry or exception- +// exit related operation is in progress. - Either +// SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the +// operation is set to Non-secure and NoninvasiveDebugAllowed() == +// TRUE. +#define M33_DWT_EXCCNT_EXCCNT_RESET _u(0x00) +#define M33_DWT_EXCCNT_EXCCNT_BITS _u(0x000000ff) +#define M33_DWT_EXCCNT_EXCCNT_MSB _u(7) +#define M33_DWT_EXCCNT_EXCCNT_LSB _u(0) +#define M33_DWT_EXCCNT_EXCCNT_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_LSUCNT +// Description : Increments on the additional cycles required to execute all +// load or store instructions +#define M33_DWT_LSUCNT_OFFSET _u(0x00001014) +#define M33_DWT_LSUCNT_BITS _u(0x000000ff) +#define M33_DWT_LSUCNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_LSUCNT_LSUCNT +// Description : Counts one on each cycle when all of the following are true: - +// DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction +// is executed, see DWT_CPICNT. - No exception-entry or exception- +// exit operation is in progress, see DWT_EXCCNT. - A load-store +// operation is in progress. - Either +// SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the +// operation is set to Non-secure and NoninvasiveDebugAllowed() == +// TRUE. +#define M33_DWT_LSUCNT_LSUCNT_RESET _u(0x00) +#define M33_DWT_LSUCNT_LSUCNT_BITS _u(0x000000ff) +#define M33_DWT_LSUCNT_LSUCNT_MSB _u(7) +#define M33_DWT_LSUCNT_LSUCNT_LSB _u(0) +#define M33_DWT_LSUCNT_LSUCNT_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_FOLDCNT +// Description : Increments on the additional cycles required to execute all +// load or store instructions +#define M33_DWT_FOLDCNT_OFFSET _u(0x00001018) +#define M33_DWT_FOLDCNT_BITS _u(0x000000ff) +#define M33_DWT_FOLDCNT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FOLDCNT_FOLDCNT +// Description : Counts on each cycle when all of the following are true: - +// DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two +// instructions are executed, see DWT_CPICNT. - Either +// SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non- +// secure state and NoninvasiveDebugAllowed() == TRUE. The counter +// is incremented by the number of instructions executed, minus +// one +#define M33_DWT_FOLDCNT_FOLDCNT_RESET _u(0x00) +#define M33_DWT_FOLDCNT_FOLDCNT_BITS _u(0x000000ff) +#define M33_DWT_FOLDCNT_FOLDCNT_MSB _u(7) +#define M33_DWT_FOLDCNT_FOLDCNT_LSB _u(0) +#define M33_DWT_FOLDCNT_FOLDCNT_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_COMP0 +// Description : Provides a reference value for use by watchpoint comparator 0 +#define M33_DWT_COMP0_OFFSET _u(0x00001020) +#define M33_DWT_COMP0_BITS _u(0xffffffff) +#define M33_DWT_COMP0_RESET _u(0x00000000) +#define M33_DWT_COMP0_MSB _u(31) +#define M33_DWT_COMP0_LSB _u(0) +#define M33_DWT_COMP0_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_FUNCTION0 +// Description : Controls the operation of watchpoint comparator 0 +#define M33_DWT_FUNCTION0_OFFSET _u(0x00001028) +#define M33_DWT_FUNCTION0_BITS _u(0xf9000c3f) +#define M33_DWT_FUNCTION0_RESET _u(0x58000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION0_ID +// Description : Identifies the capabilities for MATCH for comparator *n +#define M33_DWT_FUNCTION0_ID_RESET _u(0x0b) +#define M33_DWT_FUNCTION0_ID_BITS _u(0xf8000000) +#define M33_DWT_FUNCTION0_ID_MSB _u(31) +#define M33_DWT_FUNCTION0_ID_LSB _u(27) +#define M33_DWT_FUNCTION0_ID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION0_MATCHED +// Description : Set to 1 when the comparator matches +#define M33_DWT_FUNCTION0_MATCHED_RESET _u(0x0) +#define M33_DWT_FUNCTION0_MATCHED_BITS _u(0x01000000) +#define M33_DWT_FUNCTION0_MATCHED_MSB _u(24) +#define M33_DWT_FUNCTION0_MATCHED_LSB _u(24) +#define M33_DWT_FUNCTION0_MATCHED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION0_DATAVSIZE +// Description : Defines the size of the object being watched for by Data Value +// and Data Address comparators +#define M33_DWT_FUNCTION0_DATAVSIZE_RESET _u(0x0) +#define M33_DWT_FUNCTION0_DATAVSIZE_BITS _u(0x00000c00) +#define M33_DWT_FUNCTION0_DATAVSIZE_MSB _u(11) +#define M33_DWT_FUNCTION0_DATAVSIZE_LSB _u(10) +#define M33_DWT_FUNCTION0_DATAVSIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION0_ACTION +// Description : Defines the action on a match. This field is ignored and the +// comparator generates no actions if it is disabled by MATCH +#define M33_DWT_FUNCTION0_ACTION_RESET _u(0x0) +#define M33_DWT_FUNCTION0_ACTION_BITS _u(0x00000030) +#define M33_DWT_FUNCTION0_ACTION_MSB _u(5) +#define M33_DWT_FUNCTION0_ACTION_LSB _u(4) +#define M33_DWT_FUNCTION0_ACTION_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION0_MATCH +// Description : Controls the type of match generated by this comparator +#define M33_DWT_FUNCTION0_MATCH_RESET _u(0x0) +#define M33_DWT_FUNCTION0_MATCH_BITS _u(0x0000000f) +#define M33_DWT_FUNCTION0_MATCH_MSB _u(3) +#define M33_DWT_FUNCTION0_MATCH_LSB _u(0) +#define M33_DWT_FUNCTION0_MATCH_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_COMP1 +// Description : Provides a reference value for use by watchpoint comparator 1 +#define M33_DWT_COMP1_OFFSET _u(0x00001030) +#define M33_DWT_COMP1_BITS _u(0xffffffff) +#define M33_DWT_COMP1_RESET _u(0x00000000) +#define M33_DWT_COMP1_MSB _u(31) +#define M33_DWT_COMP1_LSB _u(0) +#define M33_DWT_COMP1_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_FUNCTION1 +// Description : Controls the operation of watchpoint comparator 1 +#define M33_DWT_FUNCTION1_OFFSET _u(0x00001038) +#define M33_DWT_FUNCTION1_BITS _u(0xf9000c3f) +#define M33_DWT_FUNCTION1_RESET _u(0x89000828) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION1_ID +// Description : Identifies the capabilities for MATCH for comparator *n +#define M33_DWT_FUNCTION1_ID_RESET _u(0x11) +#define M33_DWT_FUNCTION1_ID_BITS _u(0xf8000000) +#define M33_DWT_FUNCTION1_ID_MSB _u(31) +#define M33_DWT_FUNCTION1_ID_LSB _u(27) +#define M33_DWT_FUNCTION1_ID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION1_MATCHED +// Description : Set to 1 when the comparator matches +#define M33_DWT_FUNCTION1_MATCHED_RESET _u(0x1) +#define M33_DWT_FUNCTION1_MATCHED_BITS _u(0x01000000) +#define M33_DWT_FUNCTION1_MATCHED_MSB _u(24) +#define M33_DWT_FUNCTION1_MATCHED_LSB _u(24) +#define M33_DWT_FUNCTION1_MATCHED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION1_DATAVSIZE +// Description : Defines the size of the object being watched for by Data Value +// and Data Address comparators +#define M33_DWT_FUNCTION1_DATAVSIZE_RESET _u(0x2) +#define M33_DWT_FUNCTION1_DATAVSIZE_BITS _u(0x00000c00) +#define M33_DWT_FUNCTION1_DATAVSIZE_MSB _u(11) +#define M33_DWT_FUNCTION1_DATAVSIZE_LSB _u(10) +#define M33_DWT_FUNCTION1_DATAVSIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION1_ACTION +// Description : Defines the action on a match. This field is ignored and the +// comparator generates no actions if it is disabled by MATCH +#define M33_DWT_FUNCTION1_ACTION_RESET _u(0x2) +#define M33_DWT_FUNCTION1_ACTION_BITS _u(0x00000030) +#define M33_DWT_FUNCTION1_ACTION_MSB _u(5) +#define M33_DWT_FUNCTION1_ACTION_LSB _u(4) +#define M33_DWT_FUNCTION1_ACTION_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION1_MATCH +// Description : Controls the type of match generated by this comparator +#define M33_DWT_FUNCTION1_MATCH_RESET _u(0x8) +#define M33_DWT_FUNCTION1_MATCH_BITS _u(0x0000000f) +#define M33_DWT_FUNCTION1_MATCH_MSB _u(3) +#define M33_DWT_FUNCTION1_MATCH_LSB _u(0) +#define M33_DWT_FUNCTION1_MATCH_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_COMP2 +// Description : Provides a reference value for use by watchpoint comparator 2 +#define M33_DWT_COMP2_OFFSET _u(0x00001040) +#define M33_DWT_COMP2_BITS _u(0xffffffff) +#define M33_DWT_COMP2_RESET _u(0x00000000) +#define M33_DWT_COMP2_MSB _u(31) +#define M33_DWT_COMP2_LSB _u(0) +#define M33_DWT_COMP2_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_FUNCTION2 +// Description : Controls the operation of watchpoint comparator 2 +#define M33_DWT_FUNCTION2_OFFSET _u(0x00001048) +#define M33_DWT_FUNCTION2_BITS _u(0xf9000c3f) +#define M33_DWT_FUNCTION2_RESET _u(0x50000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION2_ID +// Description : Identifies the capabilities for MATCH for comparator *n +#define M33_DWT_FUNCTION2_ID_RESET _u(0x0a) +#define M33_DWT_FUNCTION2_ID_BITS _u(0xf8000000) +#define M33_DWT_FUNCTION2_ID_MSB _u(31) +#define M33_DWT_FUNCTION2_ID_LSB _u(27) +#define M33_DWT_FUNCTION2_ID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION2_MATCHED +// Description : Set to 1 when the comparator matches +#define M33_DWT_FUNCTION2_MATCHED_RESET _u(0x0) +#define M33_DWT_FUNCTION2_MATCHED_BITS _u(0x01000000) +#define M33_DWT_FUNCTION2_MATCHED_MSB _u(24) +#define M33_DWT_FUNCTION2_MATCHED_LSB _u(24) +#define M33_DWT_FUNCTION2_MATCHED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION2_DATAVSIZE +// Description : Defines the size of the object being watched for by Data Value +// and Data Address comparators +#define M33_DWT_FUNCTION2_DATAVSIZE_RESET _u(0x0) +#define M33_DWT_FUNCTION2_DATAVSIZE_BITS _u(0x00000c00) +#define M33_DWT_FUNCTION2_DATAVSIZE_MSB _u(11) +#define M33_DWT_FUNCTION2_DATAVSIZE_LSB _u(10) +#define M33_DWT_FUNCTION2_DATAVSIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION2_ACTION +// Description : Defines the action on a match. This field is ignored and the +// comparator generates no actions if it is disabled by MATCH +#define M33_DWT_FUNCTION2_ACTION_RESET _u(0x0) +#define M33_DWT_FUNCTION2_ACTION_BITS _u(0x00000030) +#define M33_DWT_FUNCTION2_ACTION_MSB _u(5) +#define M33_DWT_FUNCTION2_ACTION_LSB _u(4) +#define M33_DWT_FUNCTION2_ACTION_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION2_MATCH +// Description : Controls the type of match generated by this comparator +#define M33_DWT_FUNCTION2_MATCH_RESET _u(0x0) +#define M33_DWT_FUNCTION2_MATCH_BITS _u(0x0000000f) +#define M33_DWT_FUNCTION2_MATCH_MSB _u(3) +#define M33_DWT_FUNCTION2_MATCH_LSB _u(0) +#define M33_DWT_FUNCTION2_MATCH_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_COMP3 +// Description : Provides a reference value for use by watchpoint comparator 3 +#define M33_DWT_COMP3_OFFSET _u(0x00001050) +#define M33_DWT_COMP3_BITS _u(0xffffffff) +#define M33_DWT_COMP3_RESET _u(0x00000000) +#define M33_DWT_COMP3_MSB _u(31) +#define M33_DWT_COMP3_LSB _u(0) +#define M33_DWT_COMP3_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_FUNCTION3 +// Description : Controls the operation of watchpoint comparator 3 +#define M33_DWT_FUNCTION3_OFFSET _u(0x00001058) +#define M33_DWT_FUNCTION3_BITS _u(0xf9000c3f) +#define M33_DWT_FUNCTION3_RESET _u(0x20000800) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION3_ID +// Description : Identifies the capabilities for MATCH for comparator *n +#define M33_DWT_FUNCTION3_ID_RESET _u(0x04) +#define M33_DWT_FUNCTION3_ID_BITS _u(0xf8000000) +#define M33_DWT_FUNCTION3_ID_MSB _u(31) +#define M33_DWT_FUNCTION3_ID_LSB _u(27) +#define M33_DWT_FUNCTION3_ID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION3_MATCHED +// Description : Set to 1 when the comparator matches +#define M33_DWT_FUNCTION3_MATCHED_RESET _u(0x0) +#define M33_DWT_FUNCTION3_MATCHED_BITS _u(0x01000000) +#define M33_DWT_FUNCTION3_MATCHED_MSB _u(24) +#define M33_DWT_FUNCTION3_MATCHED_LSB _u(24) +#define M33_DWT_FUNCTION3_MATCHED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION3_DATAVSIZE +// Description : Defines the size of the object being watched for by Data Value +// and Data Address comparators +#define M33_DWT_FUNCTION3_DATAVSIZE_RESET _u(0x2) +#define M33_DWT_FUNCTION3_DATAVSIZE_BITS _u(0x00000c00) +#define M33_DWT_FUNCTION3_DATAVSIZE_MSB _u(11) +#define M33_DWT_FUNCTION3_DATAVSIZE_LSB _u(10) +#define M33_DWT_FUNCTION3_DATAVSIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION3_ACTION +// Description : Defines the action on a match. This field is ignored and the +// comparator generates no actions if it is disabled by MATCH +#define M33_DWT_FUNCTION3_ACTION_RESET _u(0x0) +#define M33_DWT_FUNCTION3_ACTION_BITS _u(0x00000030) +#define M33_DWT_FUNCTION3_ACTION_MSB _u(5) +#define M33_DWT_FUNCTION3_ACTION_LSB _u(4) +#define M33_DWT_FUNCTION3_ACTION_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_FUNCTION3_MATCH +// Description : Controls the type of match generated by this comparator +#define M33_DWT_FUNCTION3_MATCH_RESET _u(0x0) +#define M33_DWT_FUNCTION3_MATCH_BITS _u(0x0000000f) +#define M33_DWT_FUNCTION3_MATCH_MSB _u(3) +#define M33_DWT_FUNCTION3_MATCH_LSB _u(0) +#define M33_DWT_FUNCTION3_MATCH_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_DEVARCH +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_DEVARCH_OFFSET _u(0x00001fbc) +#define M33_DWT_DEVARCH_BITS _u(0xffffffff) +#define M33_DWT_DEVARCH_RESET _u(0x47701a02) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_DEVARCH_ARCHITECT +// Description : Defines the architect of the component. Bits [31:28] are the +// JEP106 continuation code (JEP106 bank ID, minus 1) and bits +// [27:21] are the JEP106 ID code. +#define M33_DWT_DEVARCH_ARCHITECT_RESET _u(0x23b) +#define M33_DWT_DEVARCH_ARCHITECT_BITS _u(0xffe00000) +#define M33_DWT_DEVARCH_ARCHITECT_MSB _u(31) +#define M33_DWT_DEVARCH_ARCHITECT_LSB _u(21) +#define M33_DWT_DEVARCH_ARCHITECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_DEVARCH_PRESENT +// Description : Defines that the DEVARCH register is present +#define M33_DWT_DEVARCH_PRESENT_RESET _u(0x1) +#define M33_DWT_DEVARCH_PRESENT_BITS _u(0x00100000) +#define M33_DWT_DEVARCH_PRESENT_MSB _u(20) +#define M33_DWT_DEVARCH_PRESENT_LSB _u(20) +#define M33_DWT_DEVARCH_PRESENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_DEVARCH_REVISION +// Description : Defines the architecture revision of the component +#define M33_DWT_DEVARCH_REVISION_RESET _u(0x0) +#define M33_DWT_DEVARCH_REVISION_BITS _u(0x000f0000) +#define M33_DWT_DEVARCH_REVISION_MSB _u(19) +#define M33_DWT_DEVARCH_REVISION_LSB _u(16) +#define M33_DWT_DEVARCH_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_DEVARCH_ARCHVER +// Description : Defines the architecture version of the component +#define M33_DWT_DEVARCH_ARCHVER_RESET _u(0x1) +#define M33_DWT_DEVARCH_ARCHVER_BITS _u(0x0000f000) +#define M33_DWT_DEVARCH_ARCHVER_MSB _u(15) +#define M33_DWT_DEVARCH_ARCHVER_LSB _u(12) +#define M33_DWT_DEVARCH_ARCHVER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_DEVARCH_ARCHPART +// Description : Defines the architecture of the component +#define M33_DWT_DEVARCH_ARCHPART_RESET _u(0xa02) +#define M33_DWT_DEVARCH_ARCHPART_BITS _u(0x00000fff) +#define M33_DWT_DEVARCH_ARCHPART_MSB _u(11) +#define M33_DWT_DEVARCH_ARCHPART_LSB _u(0) +#define M33_DWT_DEVARCH_ARCHPART_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_DEVTYPE +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_DEVTYPE_OFFSET _u(0x00001fcc) +#define M33_DWT_DEVTYPE_BITS _u(0x000000ff) +#define M33_DWT_DEVTYPE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_DEVTYPE_SUB +// Description : Component sub-type +#define M33_DWT_DEVTYPE_SUB_RESET _u(0x0) +#define M33_DWT_DEVTYPE_SUB_BITS _u(0x000000f0) +#define M33_DWT_DEVTYPE_SUB_MSB _u(7) +#define M33_DWT_DEVTYPE_SUB_LSB _u(4) +#define M33_DWT_DEVTYPE_SUB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_DEVTYPE_MAJOR +// Description : Component major type +#define M33_DWT_DEVTYPE_MAJOR_RESET _u(0x0) +#define M33_DWT_DEVTYPE_MAJOR_BITS _u(0x0000000f) +#define M33_DWT_DEVTYPE_MAJOR_MSB _u(3) +#define M33_DWT_DEVTYPE_MAJOR_LSB _u(0) +#define M33_DWT_DEVTYPE_MAJOR_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_PIDR4 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR4_OFFSET _u(0x00001fd0) +#define M33_DWT_PIDR4_BITS _u(0x000000ff) +#define M33_DWT_PIDR4_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR4_SIZE +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR4_SIZE_RESET _u(0x0) +#define M33_DWT_PIDR4_SIZE_BITS _u(0x000000f0) +#define M33_DWT_PIDR4_SIZE_MSB _u(7) +#define M33_DWT_PIDR4_SIZE_LSB _u(4) +#define M33_DWT_PIDR4_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR4_DES_2 +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR4_DES_2_RESET _u(0x4) +#define M33_DWT_PIDR4_DES_2_BITS _u(0x0000000f) +#define M33_DWT_PIDR4_DES_2_MSB _u(3) +#define M33_DWT_PIDR4_DES_2_LSB _u(0) +#define M33_DWT_PIDR4_DES_2_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_PIDR5 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR5_OFFSET _u(0x00001fd4) +#define M33_DWT_PIDR5_BITS _u(0x00000000) +#define M33_DWT_PIDR5_RESET _u(0x00000000) +#define M33_DWT_PIDR5_MSB _u(31) +#define M33_DWT_PIDR5_LSB _u(0) +#define M33_DWT_PIDR5_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_PIDR6 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR6_OFFSET _u(0x00001fd8) +#define M33_DWT_PIDR6_BITS _u(0x00000000) +#define M33_DWT_PIDR6_RESET _u(0x00000000) +#define M33_DWT_PIDR6_MSB _u(31) +#define M33_DWT_PIDR6_LSB _u(0) +#define M33_DWT_PIDR6_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_PIDR7 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR7_OFFSET _u(0x00001fdc) +#define M33_DWT_PIDR7_BITS _u(0x00000000) +#define M33_DWT_PIDR7_RESET _u(0x00000000) +#define M33_DWT_PIDR7_MSB _u(31) +#define M33_DWT_PIDR7_LSB _u(0) +#define M33_DWT_PIDR7_ACCESS "RW" +// ============================================================================= +// Register : M33_DWT_PIDR0 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR0_OFFSET _u(0x00001fe0) +#define M33_DWT_PIDR0_BITS _u(0x000000ff) +#define M33_DWT_PIDR0_RESET _u(0x00000021) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR0_PART_0 +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR0_PART_0_RESET _u(0x21) +#define M33_DWT_PIDR0_PART_0_BITS _u(0x000000ff) +#define M33_DWT_PIDR0_PART_0_MSB _u(7) +#define M33_DWT_PIDR0_PART_0_LSB _u(0) +#define M33_DWT_PIDR0_PART_0_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_PIDR1 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR1_OFFSET _u(0x00001fe4) +#define M33_DWT_PIDR1_BITS _u(0x000000ff) +#define M33_DWT_PIDR1_RESET _u(0x000000bd) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR1_DES_0 +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR1_DES_0_RESET _u(0xb) +#define M33_DWT_PIDR1_DES_0_BITS _u(0x000000f0) +#define M33_DWT_PIDR1_DES_0_MSB _u(7) +#define M33_DWT_PIDR1_DES_0_LSB _u(4) +#define M33_DWT_PIDR1_DES_0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR1_PART_1 +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR1_PART_1_RESET _u(0xd) +#define M33_DWT_PIDR1_PART_1_BITS _u(0x0000000f) +#define M33_DWT_PIDR1_PART_1_MSB _u(3) +#define M33_DWT_PIDR1_PART_1_LSB _u(0) +#define M33_DWT_PIDR1_PART_1_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_PIDR2 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR2_OFFSET _u(0x00001fe8) +#define M33_DWT_PIDR2_BITS _u(0x000000ff) +#define M33_DWT_PIDR2_RESET _u(0x0000000b) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR2_REVISION +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR2_REVISION_RESET _u(0x0) +#define M33_DWT_PIDR2_REVISION_BITS _u(0x000000f0) +#define M33_DWT_PIDR2_REVISION_MSB _u(7) +#define M33_DWT_PIDR2_REVISION_LSB _u(4) +#define M33_DWT_PIDR2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR2_JEDEC +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR2_JEDEC_RESET _u(0x1) +#define M33_DWT_PIDR2_JEDEC_BITS _u(0x00000008) +#define M33_DWT_PIDR2_JEDEC_MSB _u(3) +#define M33_DWT_PIDR2_JEDEC_LSB _u(3) +#define M33_DWT_PIDR2_JEDEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR2_DES_1 +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR2_DES_1_RESET _u(0x3) +#define M33_DWT_PIDR2_DES_1_BITS _u(0x00000007) +#define M33_DWT_PIDR2_DES_1_MSB _u(2) +#define M33_DWT_PIDR2_DES_1_LSB _u(0) +#define M33_DWT_PIDR2_DES_1_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_PIDR3 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_PIDR3_OFFSET _u(0x00001fec) +#define M33_DWT_PIDR3_BITS _u(0x000000ff) +#define M33_DWT_PIDR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR3_REVAND +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR3_REVAND_RESET _u(0x0) +#define M33_DWT_PIDR3_REVAND_BITS _u(0x000000f0) +#define M33_DWT_PIDR3_REVAND_MSB _u(7) +#define M33_DWT_PIDR3_REVAND_LSB _u(4) +#define M33_DWT_PIDR3_REVAND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_PIDR3_CMOD +// Description : See CoreSight Architecture Specification +#define M33_DWT_PIDR3_CMOD_RESET _u(0x0) +#define M33_DWT_PIDR3_CMOD_BITS _u(0x0000000f) +#define M33_DWT_PIDR3_CMOD_MSB _u(3) +#define M33_DWT_PIDR3_CMOD_LSB _u(0) +#define M33_DWT_PIDR3_CMOD_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_CIDR0 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_CIDR0_OFFSET _u(0x00001ff0) +#define M33_DWT_CIDR0_BITS _u(0x000000ff) +#define M33_DWT_CIDR0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CIDR0_PRMBL_0 +// Description : See CoreSight Architecture Specification +#define M33_DWT_CIDR0_PRMBL_0_RESET _u(0x0d) +#define M33_DWT_CIDR0_PRMBL_0_BITS _u(0x000000ff) +#define M33_DWT_CIDR0_PRMBL_0_MSB _u(7) +#define M33_DWT_CIDR0_PRMBL_0_LSB _u(0) +#define M33_DWT_CIDR0_PRMBL_0_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_CIDR1 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_CIDR1_OFFSET _u(0x00001ff4) +#define M33_DWT_CIDR1_BITS _u(0x000000ff) +#define M33_DWT_CIDR1_RESET _u(0x00000090) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CIDR1_CLASS +// Description : See CoreSight Architecture Specification +#define M33_DWT_CIDR1_CLASS_RESET _u(0x9) +#define M33_DWT_CIDR1_CLASS_BITS _u(0x000000f0) +#define M33_DWT_CIDR1_CLASS_MSB _u(7) +#define M33_DWT_CIDR1_CLASS_LSB _u(4) +#define M33_DWT_CIDR1_CLASS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CIDR1_PRMBL_1 +// Description : See CoreSight Architecture Specification +#define M33_DWT_CIDR1_PRMBL_1_RESET _u(0x0) +#define M33_DWT_CIDR1_PRMBL_1_BITS _u(0x0000000f) +#define M33_DWT_CIDR1_PRMBL_1_MSB _u(3) +#define M33_DWT_CIDR1_PRMBL_1_LSB _u(0) +#define M33_DWT_CIDR1_PRMBL_1_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_CIDR2 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_CIDR2_OFFSET _u(0x00001ff8) +#define M33_DWT_CIDR2_BITS _u(0x000000ff) +#define M33_DWT_CIDR2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CIDR2_PRMBL_2 +// Description : See CoreSight Architecture Specification +#define M33_DWT_CIDR2_PRMBL_2_RESET _u(0x05) +#define M33_DWT_CIDR2_PRMBL_2_BITS _u(0x000000ff) +#define M33_DWT_CIDR2_PRMBL_2_MSB _u(7) +#define M33_DWT_CIDR2_PRMBL_2_LSB _u(0) +#define M33_DWT_CIDR2_PRMBL_2_ACCESS "RO" +// ============================================================================= +// Register : M33_DWT_CIDR3 +// Description : Provides CoreSight discovery information for the DWT +#define M33_DWT_CIDR3_OFFSET _u(0x00001ffc) +#define M33_DWT_CIDR3_BITS _u(0x000000ff) +#define M33_DWT_CIDR3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : M33_DWT_CIDR3_PRMBL_3 +// Description : See CoreSight Architecture Specification +#define M33_DWT_CIDR3_PRMBL_3_RESET _u(0xb1) +#define M33_DWT_CIDR3_PRMBL_3_BITS _u(0x000000ff) +#define M33_DWT_CIDR3_PRMBL_3_MSB _u(7) +#define M33_DWT_CIDR3_PRMBL_3_LSB _u(0) +#define M33_DWT_CIDR3_PRMBL_3_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_CTRL +// Description : Provides FPB implementation information, and the global enable +// for the FPB unit +#define M33_FP_CTRL_OFFSET _u(0x00002000) +#define M33_FP_CTRL_BITS _u(0xf0007ff3) +#define M33_FP_CTRL_RESET _u(0x60005580) +// ----------------------------------------------------------------------------- +// Field : M33_FP_CTRL_REV +// Description : Flash Patch and Breakpoint Unit architecture revision +#define M33_FP_CTRL_REV_RESET _u(0x6) +#define M33_FP_CTRL_REV_BITS _u(0xf0000000) +#define M33_FP_CTRL_REV_MSB _u(31) +#define M33_FP_CTRL_REV_LSB _u(28) +#define M33_FP_CTRL_REV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_CTRL_NUM_CODE_14_12_ +// Description : Indicates the number of implemented instruction address +// comparators. Zero indicates no Instruction Address comparators +// are implemented. The Instruction Address comparators are +// numbered from 0 to NUM_CODE - 1 +#define M33_FP_CTRL_NUM_CODE_14_12__RESET _u(0x5) +#define M33_FP_CTRL_NUM_CODE_14_12__BITS _u(0x00007000) +#define M33_FP_CTRL_NUM_CODE_14_12__MSB _u(14) +#define M33_FP_CTRL_NUM_CODE_14_12__LSB _u(12) +#define M33_FP_CTRL_NUM_CODE_14_12__ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_CTRL_NUM_LIT +// Description : Indicates the number of implemented literal address +// comparators. The Literal Address comparators are numbered from +// NUM_CODE to NUM_CODE + NUM_LIT - 1 +#define M33_FP_CTRL_NUM_LIT_RESET _u(0x5) +#define M33_FP_CTRL_NUM_LIT_BITS _u(0x00000f00) +#define M33_FP_CTRL_NUM_LIT_MSB _u(11) +#define M33_FP_CTRL_NUM_LIT_LSB _u(8) +#define M33_FP_CTRL_NUM_LIT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_CTRL_NUM_CODE_7_4_ +// Description : Indicates the number of implemented instruction address +// comparators. Zero indicates no Instruction Address comparators +// are implemented. The Instruction Address comparators are +// numbered from 0 to NUM_CODE - 1 +#define M33_FP_CTRL_NUM_CODE_7_4__RESET _u(0x8) +#define M33_FP_CTRL_NUM_CODE_7_4__BITS _u(0x000000f0) +#define M33_FP_CTRL_NUM_CODE_7_4__MSB _u(7) +#define M33_FP_CTRL_NUM_CODE_7_4__LSB _u(4) +#define M33_FP_CTRL_NUM_CODE_7_4__ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_CTRL_KEY +// Description : Writes to the FP_CTRL are ignored unless KEY is concurrently +// written to one +#define M33_FP_CTRL_KEY_RESET _u(0x0) +#define M33_FP_CTRL_KEY_BITS _u(0x00000002) +#define M33_FP_CTRL_KEY_MSB _u(1) +#define M33_FP_CTRL_KEY_LSB _u(1) +#define M33_FP_CTRL_KEY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FP_CTRL_ENABLE +// Description : Enables the FPB +#define M33_FP_CTRL_ENABLE_RESET _u(0x0) +#define M33_FP_CTRL_ENABLE_BITS _u(0x00000001) +#define M33_FP_CTRL_ENABLE_MSB _u(0) +#define M33_FP_CTRL_ENABLE_LSB _u(0) +#define M33_FP_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_REMAP +// Description : Indicates whether the implementation supports Flash Patch remap +// and, if it does, holds the target address for remap +#define M33_FP_REMAP_OFFSET _u(0x00002004) +#define M33_FP_REMAP_BITS _u(0x3fffffe0) +#define M33_FP_REMAP_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_REMAP_RMPSPT +// Description : Indicates whether the FPB unit supports the Flash Patch remap +// function +#define M33_FP_REMAP_RMPSPT_RESET _u(0x0) +#define M33_FP_REMAP_RMPSPT_BITS _u(0x20000000) +#define M33_FP_REMAP_RMPSPT_MSB _u(29) +#define M33_FP_REMAP_RMPSPT_LSB _u(29) +#define M33_FP_REMAP_RMPSPT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_REMAP_REMAP +// Description : Holds the bits[28:5] of the Flash Patch remap address +#define M33_FP_REMAP_REMAP_RESET _u(0x000000) +#define M33_FP_REMAP_REMAP_BITS _u(0x1fffffe0) +#define M33_FP_REMAP_REMAP_MSB _u(28) +#define M33_FP_REMAP_REMAP_LSB _u(5) +#define M33_FP_REMAP_REMAP_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_COMP0 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP0_OFFSET _u(0x00002008) +#define M33_FP_COMP0_BITS _u(0x00000001) +#define M33_FP_COMP0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP0_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP0_BE_RESET _u(0x0) +#define M33_FP_COMP0_BE_BITS _u(0x00000001) +#define M33_FP_COMP0_BE_MSB _u(0) +#define M33_FP_COMP0_BE_LSB _u(0) +#define M33_FP_COMP0_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_COMP1 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP1_OFFSET _u(0x0000200c) +#define M33_FP_COMP1_BITS _u(0x00000001) +#define M33_FP_COMP1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP1_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP1_BE_RESET _u(0x0) +#define M33_FP_COMP1_BE_BITS _u(0x00000001) +#define M33_FP_COMP1_BE_MSB _u(0) +#define M33_FP_COMP1_BE_LSB _u(0) +#define M33_FP_COMP1_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_COMP2 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP2_OFFSET _u(0x00002010) +#define M33_FP_COMP2_BITS _u(0x00000001) +#define M33_FP_COMP2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP2_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP2_BE_RESET _u(0x0) +#define M33_FP_COMP2_BE_BITS _u(0x00000001) +#define M33_FP_COMP2_BE_MSB _u(0) +#define M33_FP_COMP2_BE_LSB _u(0) +#define M33_FP_COMP2_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_COMP3 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP3_OFFSET _u(0x00002014) +#define M33_FP_COMP3_BITS _u(0x00000001) +#define M33_FP_COMP3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP3_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP3_BE_RESET _u(0x0) +#define M33_FP_COMP3_BE_BITS _u(0x00000001) +#define M33_FP_COMP3_BE_MSB _u(0) +#define M33_FP_COMP3_BE_LSB _u(0) +#define M33_FP_COMP3_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_COMP4 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP4_OFFSET _u(0x00002018) +#define M33_FP_COMP4_BITS _u(0x00000001) +#define M33_FP_COMP4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP4_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP4_BE_RESET _u(0x0) +#define M33_FP_COMP4_BE_BITS _u(0x00000001) +#define M33_FP_COMP4_BE_MSB _u(0) +#define M33_FP_COMP4_BE_LSB _u(0) +#define M33_FP_COMP4_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_COMP5 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP5_OFFSET _u(0x0000201c) +#define M33_FP_COMP5_BITS _u(0x00000001) +#define M33_FP_COMP5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP5_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP5_BE_RESET _u(0x0) +#define M33_FP_COMP5_BE_BITS _u(0x00000001) +#define M33_FP_COMP5_BE_MSB _u(0) +#define M33_FP_COMP5_BE_LSB _u(0) +#define M33_FP_COMP5_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_COMP6 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP6_OFFSET _u(0x00002020) +#define M33_FP_COMP6_BITS _u(0x00000001) +#define M33_FP_COMP6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP6_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP6_BE_RESET _u(0x0) +#define M33_FP_COMP6_BE_BITS _u(0x00000001) +#define M33_FP_COMP6_BE_MSB _u(0) +#define M33_FP_COMP6_BE_LSB _u(0) +#define M33_FP_COMP6_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_COMP7 +// Description : Holds an address for comparison. The effect of the match +// depends on the configuration of the FPB and whether the +// comparator is an instruction address comparator or a literal +// address comparator +#define M33_FP_COMP7_OFFSET _u(0x00002024) +#define M33_FP_COMP7_BITS _u(0x00000001) +#define M33_FP_COMP7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_COMP7_BE +// Description : Selects between flashpatch and breakpoint functionality +#define M33_FP_COMP7_BE_RESET _u(0x0) +#define M33_FP_COMP7_BE_BITS _u(0x00000001) +#define M33_FP_COMP7_BE_MSB _u(0) +#define M33_FP_COMP7_BE_LSB _u(0) +#define M33_FP_COMP7_BE_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_DEVARCH +// Description : Provides CoreSight discovery information for the FPB +#define M33_FP_DEVARCH_OFFSET _u(0x00002fbc) +#define M33_FP_DEVARCH_BITS _u(0xffffffff) +#define M33_FP_DEVARCH_RESET _u(0x47701a03) +// ----------------------------------------------------------------------------- +// Field : M33_FP_DEVARCH_ARCHITECT +// Description : Defines the architect of the component. Bits [31:28] are the +// JEP106 continuation code (JEP106 bank ID, minus 1) and bits +// [27:21] are the JEP106 ID code. +#define M33_FP_DEVARCH_ARCHITECT_RESET _u(0x23b) +#define M33_FP_DEVARCH_ARCHITECT_BITS _u(0xffe00000) +#define M33_FP_DEVARCH_ARCHITECT_MSB _u(31) +#define M33_FP_DEVARCH_ARCHITECT_LSB _u(21) +#define M33_FP_DEVARCH_ARCHITECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_DEVARCH_PRESENT +// Description : Defines that the DEVARCH register is present +#define M33_FP_DEVARCH_PRESENT_RESET _u(0x1) +#define M33_FP_DEVARCH_PRESENT_BITS _u(0x00100000) +#define M33_FP_DEVARCH_PRESENT_MSB _u(20) +#define M33_FP_DEVARCH_PRESENT_LSB _u(20) +#define M33_FP_DEVARCH_PRESENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_DEVARCH_REVISION +// Description : Defines the architecture revision of the component +#define M33_FP_DEVARCH_REVISION_RESET _u(0x0) +#define M33_FP_DEVARCH_REVISION_BITS _u(0x000f0000) +#define M33_FP_DEVARCH_REVISION_MSB _u(19) +#define M33_FP_DEVARCH_REVISION_LSB _u(16) +#define M33_FP_DEVARCH_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_DEVARCH_ARCHVER +// Description : Defines the architecture version of the component +#define M33_FP_DEVARCH_ARCHVER_RESET _u(0x1) +#define M33_FP_DEVARCH_ARCHVER_BITS _u(0x0000f000) +#define M33_FP_DEVARCH_ARCHVER_MSB _u(15) +#define M33_FP_DEVARCH_ARCHVER_LSB _u(12) +#define M33_FP_DEVARCH_ARCHVER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_DEVARCH_ARCHPART +// Description : Defines the architecture of the component +#define M33_FP_DEVARCH_ARCHPART_RESET _u(0xa03) +#define M33_FP_DEVARCH_ARCHPART_BITS _u(0x00000fff) +#define M33_FP_DEVARCH_ARCHPART_MSB _u(11) +#define M33_FP_DEVARCH_ARCHPART_LSB _u(0) +#define M33_FP_DEVARCH_ARCHPART_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_DEVTYPE +// Description : Provides CoreSight discovery information for the FPB +#define M33_FP_DEVTYPE_OFFSET _u(0x00002fcc) +#define M33_FP_DEVTYPE_BITS _u(0x000000ff) +#define M33_FP_DEVTYPE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_DEVTYPE_SUB +// Description : Component sub-type +#define M33_FP_DEVTYPE_SUB_RESET _u(0x0) +#define M33_FP_DEVTYPE_SUB_BITS _u(0x000000f0) +#define M33_FP_DEVTYPE_SUB_MSB _u(7) +#define M33_FP_DEVTYPE_SUB_LSB _u(4) +#define M33_FP_DEVTYPE_SUB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_DEVTYPE_MAJOR +// Description : Component major type +#define M33_FP_DEVTYPE_MAJOR_RESET _u(0x0) +#define M33_FP_DEVTYPE_MAJOR_BITS _u(0x0000000f) +#define M33_FP_DEVTYPE_MAJOR_MSB _u(3) +#define M33_FP_DEVTYPE_MAJOR_LSB _u(0) +#define M33_FP_DEVTYPE_MAJOR_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_PIDR4 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR4_OFFSET _u(0x00002fd0) +#define M33_FP_PIDR4_BITS _u(0x000000ff) +#define M33_FP_PIDR4_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR4_SIZE +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR4_SIZE_RESET _u(0x0) +#define M33_FP_PIDR4_SIZE_BITS _u(0x000000f0) +#define M33_FP_PIDR4_SIZE_MSB _u(7) +#define M33_FP_PIDR4_SIZE_LSB _u(4) +#define M33_FP_PIDR4_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR4_DES_2 +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR4_DES_2_RESET _u(0x4) +#define M33_FP_PIDR4_DES_2_BITS _u(0x0000000f) +#define M33_FP_PIDR4_DES_2_MSB _u(3) +#define M33_FP_PIDR4_DES_2_LSB _u(0) +#define M33_FP_PIDR4_DES_2_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_PIDR5 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR5_OFFSET _u(0x00002fd4) +#define M33_FP_PIDR5_BITS _u(0x00000000) +#define M33_FP_PIDR5_RESET _u(0x00000000) +#define M33_FP_PIDR5_MSB _u(31) +#define M33_FP_PIDR5_LSB _u(0) +#define M33_FP_PIDR5_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_PIDR6 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR6_OFFSET _u(0x00002fd8) +#define M33_FP_PIDR6_BITS _u(0x00000000) +#define M33_FP_PIDR6_RESET _u(0x00000000) +#define M33_FP_PIDR6_MSB _u(31) +#define M33_FP_PIDR6_LSB _u(0) +#define M33_FP_PIDR6_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_PIDR7 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR7_OFFSET _u(0x00002fdc) +#define M33_FP_PIDR7_BITS _u(0x00000000) +#define M33_FP_PIDR7_RESET _u(0x00000000) +#define M33_FP_PIDR7_MSB _u(31) +#define M33_FP_PIDR7_LSB _u(0) +#define M33_FP_PIDR7_ACCESS "RW" +// ============================================================================= +// Register : M33_FP_PIDR0 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR0_OFFSET _u(0x00002fe0) +#define M33_FP_PIDR0_BITS _u(0x000000ff) +#define M33_FP_PIDR0_RESET _u(0x00000021) +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR0_PART_0 +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR0_PART_0_RESET _u(0x21) +#define M33_FP_PIDR0_PART_0_BITS _u(0x000000ff) +#define M33_FP_PIDR0_PART_0_MSB _u(7) +#define M33_FP_PIDR0_PART_0_LSB _u(0) +#define M33_FP_PIDR0_PART_0_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_PIDR1 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR1_OFFSET _u(0x00002fe4) +#define M33_FP_PIDR1_BITS _u(0x000000ff) +#define M33_FP_PIDR1_RESET _u(0x000000bd) +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR1_DES_0 +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR1_DES_0_RESET _u(0xb) +#define M33_FP_PIDR1_DES_0_BITS _u(0x000000f0) +#define M33_FP_PIDR1_DES_0_MSB _u(7) +#define M33_FP_PIDR1_DES_0_LSB _u(4) +#define M33_FP_PIDR1_DES_0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR1_PART_1 +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR1_PART_1_RESET _u(0xd) +#define M33_FP_PIDR1_PART_1_BITS _u(0x0000000f) +#define M33_FP_PIDR1_PART_1_MSB _u(3) +#define M33_FP_PIDR1_PART_1_LSB _u(0) +#define M33_FP_PIDR1_PART_1_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_PIDR2 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR2_OFFSET _u(0x00002fe8) +#define M33_FP_PIDR2_BITS _u(0x000000ff) +#define M33_FP_PIDR2_RESET _u(0x0000000b) +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR2_REVISION +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR2_REVISION_RESET _u(0x0) +#define M33_FP_PIDR2_REVISION_BITS _u(0x000000f0) +#define M33_FP_PIDR2_REVISION_MSB _u(7) +#define M33_FP_PIDR2_REVISION_LSB _u(4) +#define M33_FP_PIDR2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR2_JEDEC +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR2_JEDEC_RESET _u(0x1) +#define M33_FP_PIDR2_JEDEC_BITS _u(0x00000008) +#define M33_FP_PIDR2_JEDEC_MSB _u(3) +#define M33_FP_PIDR2_JEDEC_LSB _u(3) +#define M33_FP_PIDR2_JEDEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR2_DES_1 +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR2_DES_1_RESET _u(0x3) +#define M33_FP_PIDR2_DES_1_BITS _u(0x00000007) +#define M33_FP_PIDR2_DES_1_MSB _u(2) +#define M33_FP_PIDR2_DES_1_LSB _u(0) +#define M33_FP_PIDR2_DES_1_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_PIDR3 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_PIDR3_OFFSET _u(0x00002fec) +#define M33_FP_PIDR3_BITS _u(0x000000ff) +#define M33_FP_PIDR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR3_REVAND +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR3_REVAND_RESET _u(0x0) +#define M33_FP_PIDR3_REVAND_BITS _u(0x000000f0) +#define M33_FP_PIDR3_REVAND_MSB _u(7) +#define M33_FP_PIDR3_REVAND_LSB _u(4) +#define M33_FP_PIDR3_REVAND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_PIDR3_CMOD +// Description : See CoreSight Architecture Specification +#define M33_FP_PIDR3_CMOD_RESET _u(0x0) +#define M33_FP_PIDR3_CMOD_BITS _u(0x0000000f) +#define M33_FP_PIDR3_CMOD_MSB _u(3) +#define M33_FP_PIDR3_CMOD_LSB _u(0) +#define M33_FP_PIDR3_CMOD_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_CIDR0 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_CIDR0_OFFSET _u(0x00002ff0) +#define M33_FP_CIDR0_BITS _u(0x000000ff) +#define M33_FP_CIDR0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : M33_FP_CIDR0_PRMBL_0 +// Description : See CoreSight Architecture Specification +#define M33_FP_CIDR0_PRMBL_0_RESET _u(0x0d) +#define M33_FP_CIDR0_PRMBL_0_BITS _u(0x000000ff) +#define M33_FP_CIDR0_PRMBL_0_MSB _u(7) +#define M33_FP_CIDR0_PRMBL_0_LSB _u(0) +#define M33_FP_CIDR0_PRMBL_0_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_CIDR1 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_CIDR1_OFFSET _u(0x00002ff4) +#define M33_FP_CIDR1_BITS _u(0x000000ff) +#define M33_FP_CIDR1_RESET _u(0x00000090) +// ----------------------------------------------------------------------------- +// Field : M33_FP_CIDR1_CLASS +// Description : See CoreSight Architecture Specification +#define M33_FP_CIDR1_CLASS_RESET _u(0x9) +#define M33_FP_CIDR1_CLASS_BITS _u(0x000000f0) +#define M33_FP_CIDR1_CLASS_MSB _u(7) +#define M33_FP_CIDR1_CLASS_LSB _u(4) +#define M33_FP_CIDR1_CLASS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_FP_CIDR1_PRMBL_1 +// Description : See CoreSight Architecture Specification +#define M33_FP_CIDR1_PRMBL_1_RESET _u(0x0) +#define M33_FP_CIDR1_PRMBL_1_BITS _u(0x0000000f) +#define M33_FP_CIDR1_PRMBL_1_MSB _u(3) +#define M33_FP_CIDR1_PRMBL_1_LSB _u(0) +#define M33_FP_CIDR1_PRMBL_1_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_CIDR2 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_CIDR2_OFFSET _u(0x00002ff8) +#define M33_FP_CIDR2_BITS _u(0x000000ff) +#define M33_FP_CIDR2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : M33_FP_CIDR2_PRMBL_2 +// Description : See CoreSight Architecture Specification +#define M33_FP_CIDR2_PRMBL_2_RESET _u(0x05) +#define M33_FP_CIDR2_PRMBL_2_BITS _u(0x000000ff) +#define M33_FP_CIDR2_PRMBL_2_MSB _u(7) +#define M33_FP_CIDR2_PRMBL_2_LSB _u(0) +#define M33_FP_CIDR2_PRMBL_2_ACCESS "RO" +// ============================================================================= +// Register : M33_FP_CIDR3 +// Description : Provides CoreSight discovery information for the FP +#define M33_FP_CIDR3_OFFSET _u(0x00002ffc) +#define M33_FP_CIDR3_BITS _u(0x000000ff) +#define M33_FP_CIDR3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : M33_FP_CIDR3_PRMBL_3 +// Description : See CoreSight Architecture Specification +#define M33_FP_CIDR3_PRMBL_3_RESET _u(0xb1) +#define M33_FP_CIDR3_PRMBL_3_BITS _u(0x000000ff) +#define M33_FP_CIDR3_PRMBL_3_MSB _u(7) +#define M33_FP_CIDR3_PRMBL_3_LSB _u(0) +#define M33_FP_CIDR3_PRMBL_3_ACCESS "RO" +// ============================================================================= +// Register : M33_ICTR +// Description : Provides information about the interrupt controller +#define M33_ICTR_OFFSET _u(0x0000e004) +#define M33_ICTR_BITS _u(0x0000000f) +#define M33_ICTR_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : M33_ICTR_INTLINESNUM +// Description : Indicates the number of the highest implemented register in +// each of the NVIC control register sets, or in the case of +// NVIC_IPR*n, 4×INTLINESNUM +#define M33_ICTR_INTLINESNUM_RESET _u(0x1) +#define M33_ICTR_INTLINESNUM_BITS _u(0x0000000f) +#define M33_ICTR_INTLINESNUM_MSB _u(3) +#define M33_ICTR_INTLINESNUM_LSB _u(0) +#define M33_ICTR_INTLINESNUM_ACCESS "RO" +// ============================================================================= +// Register : M33_ACTLR +// Description : Provides IMPLEMENTATION DEFINED configuration and control +// options +#define M33_ACTLR_OFFSET _u(0x0000e008) +#define M33_ACTLR_BITS _u(0x20001605) +#define M33_ACTLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ACTLR_EXTEXCLALL +// Description : External Exclusives Allowed with no MPU +#define M33_ACTLR_EXTEXCLALL_RESET _u(0x0) +#define M33_ACTLR_EXTEXCLALL_BITS _u(0x20000000) +#define M33_ACTLR_EXTEXCLALL_MSB _u(29) +#define M33_ACTLR_EXTEXCLALL_LSB _u(29) +#define M33_ACTLR_EXTEXCLALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ACTLR_DISITMATBFLUSH +// Description : Disable ATB Flush +#define M33_ACTLR_DISITMATBFLUSH_RESET _u(0x0) +#define M33_ACTLR_DISITMATBFLUSH_BITS _u(0x00001000) +#define M33_ACTLR_DISITMATBFLUSH_MSB _u(12) +#define M33_ACTLR_DISITMATBFLUSH_LSB _u(12) +#define M33_ACTLR_DISITMATBFLUSH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ACTLR_FPEXCODIS +// Description : Disable FPU exception outputs +#define M33_ACTLR_FPEXCODIS_RESET _u(0x0) +#define M33_ACTLR_FPEXCODIS_BITS _u(0x00000400) +#define M33_ACTLR_FPEXCODIS_MSB _u(10) +#define M33_ACTLR_FPEXCODIS_LSB _u(10) +#define M33_ACTLR_FPEXCODIS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ACTLR_DISOOFP +// Description : Disable out-of-order FP instruction completion +#define M33_ACTLR_DISOOFP_RESET _u(0x0) +#define M33_ACTLR_DISOOFP_BITS _u(0x00000200) +#define M33_ACTLR_DISOOFP_MSB _u(9) +#define M33_ACTLR_DISOOFP_LSB _u(9) +#define M33_ACTLR_DISOOFP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ACTLR_DISFOLD +// Description : Disable dual-issue. +#define M33_ACTLR_DISFOLD_RESET _u(0x0) +#define M33_ACTLR_DISFOLD_BITS _u(0x00000004) +#define M33_ACTLR_DISFOLD_MSB _u(2) +#define M33_ACTLR_DISFOLD_LSB _u(2) +#define M33_ACTLR_DISFOLD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ACTLR_DISMCYCINT +// Description : Disable dual-issue. +#define M33_ACTLR_DISMCYCINT_RESET _u(0x0) +#define M33_ACTLR_DISMCYCINT_BITS _u(0x00000001) +#define M33_ACTLR_DISMCYCINT_MSB _u(0) +#define M33_ACTLR_DISMCYCINT_LSB _u(0) +#define M33_ACTLR_DISMCYCINT_ACCESS "RW" +// ============================================================================= +// Register : M33_SYST_CSR +// Description : Use the SysTick Control and Status Register to enable the +// SysTick features. +#define M33_SYST_CSR_OFFSET _u(0x0000e010) +#define M33_SYST_CSR_BITS _u(0x00010007) +#define M33_SYST_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CSR_COUNTFLAG +// Description : Returns 1 if timer counted to 0 since last time this was read. +// Clears on read by application or debugger. +#define M33_SYST_CSR_COUNTFLAG_RESET _u(0x0) +#define M33_SYST_CSR_COUNTFLAG_BITS _u(0x00010000) +#define M33_SYST_CSR_COUNTFLAG_MSB _u(16) +#define M33_SYST_CSR_COUNTFLAG_LSB _u(16) +#define M33_SYST_CSR_COUNTFLAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CSR_CLKSOURCE +// Description : SysTick clock source. Always reads as one if SYST_CALIB reports +// NOREF. +// Selects the SysTick timer clock source: +// 0 = External reference clock. +// 1 = Processor clock. +#define M33_SYST_CSR_CLKSOURCE_RESET _u(0x0) +#define M33_SYST_CSR_CLKSOURCE_BITS _u(0x00000004) +#define M33_SYST_CSR_CLKSOURCE_MSB _u(2) +#define M33_SYST_CSR_CLKSOURCE_LSB _u(2) +#define M33_SYST_CSR_CLKSOURCE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CSR_TICKINT +// Description : Enables SysTick exception request: +// 0 = Counting down to zero does not assert the SysTick exception +// request. +// 1 = Counting down to zero to asserts the SysTick exception +// request. +#define M33_SYST_CSR_TICKINT_RESET _u(0x0) +#define M33_SYST_CSR_TICKINT_BITS _u(0x00000002) +#define M33_SYST_CSR_TICKINT_MSB _u(1) +#define M33_SYST_CSR_TICKINT_LSB _u(1) +#define M33_SYST_CSR_TICKINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CSR_ENABLE +// Description : Enable SysTick counter: +// 0 = Counter disabled. +// 1 = Counter enabled. +#define M33_SYST_CSR_ENABLE_RESET _u(0x0) +#define M33_SYST_CSR_ENABLE_BITS _u(0x00000001) +#define M33_SYST_CSR_ENABLE_MSB _u(0) +#define M33_SYST_CSR_ENABLE_LSB _u(0) +#define M33_SYST_CSR_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : M33_SYST_RVR +// Description : Use the SysTick Reload Value Register to specify the start +// value to load into the current value register when the counter +// reaches 0. It can be any value between 0 and 0x00FFFFFF. A +// start value of 0 is possible, but has no effect because the +// SysTick interrupt and COUNTFLAG are activated when counting +// from 1 to 0. The reset value of this register is UNKNOWN. +// To generate a multi-shot timer with a period of N processor +// clock cycles, use a RELOAD value of N-1. For example, if the +// SysTick interrupt is required every 100 clock pulses, set +// RELOAD to 99. +#define M33_SYST_RVR_OFFSET _u(0x0000e014) +#define M33_SYST_RVR_BITS _u(0x00ffffff) +#define M33_SYST_RVR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SYST_RVR_RELOAD +// Description : Value to load into the SysTick Current Value Register when the +// counter reaches 0. +#define M33_SYST_RVR_RELOAD_RESET _u(0x000000) +#define M33_SYST_RVR_RELOAD_BITS _u(0x00ffffff) +#define M33_SYST_RVR_RELOAD_MSB _u(23) +#define M33_SYST_RVR_RELOAD_LSB _u(0) +#define M33_SYST_RVR_RELOAD_ACCESS "RW" +// ============================================================================= +// Register : M33_SYST_CVR +// Description : Use the SysTick Current Value Register to find the current +// value in the register. The reset value of this register is +// UNKNOWN. +#define M33_SYST_CVR_OFFSET _u(0x0000e018) +#define M33_SYST_CVR_BITS _u(0x00ffffff) +#define M33_SYST_CVR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CVR_CURRENT +// Description : Reads return the current value of the SysTick counter. This +// register is write-clear. Writing to it with any value clears +// the register to 0. Clearing this register also clears the +// COUNTFLAG bit of the SysTick Control and Status Register. +#define M33_SYST_CVR_CURRENT_RESET _u(0x000000) +#define M33_SYST_CVR_CURRENT_BITS _u(0x00ffffff) +#define M33_SYST_CVR_CURRENT_MSB _u(23) +#define M33_SYST_CVR_CURRENT_LSB _u(0) +#define M33_SYST_CVR_CURRENT_ACCESS "RW" +// ============================================================================= +// Register : M33_SYST_CALIB +// Description : Use the SysTick Calibration Value Register to enable software +// to scale to any required speed using divide and multiply. +#define M33_SYST_CALIB_OFFSET _u(0x0000e01c) +#define M33_SYST_CALIB_BITS _u(0xc0ffffff) +#define M33_SYST_CALIB_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CALIB_NOREF +// Description : If reads as 1, the Reference clock is not provided - the +// CLKSOURCE bit of the SysTick Control and Status register will +// be forced to 1 and cannot be cleared to 0. +#define M33_SYST_CALIB_NOREF_RESET _u(0x0) +#define M33_SYST_CALIB_NOREF_BITS _u(0x80000000) +#define M33_SYST_CALIB_NOREF_MSB _u(31) +#define M33_SYST_CALIB_NOREF_LSB _u(31) +#define M33_SYST_CALIB_NOREF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CALIB_SKEW +// Description : If reads as 1, the calibration value for 10ms is inexact (due +// to clock frequency). +#define M33_SYST_CALIB_SKEW_RESET _u(0x0) +#define M33_SYST_CALIB_SKEW_BITS _u(0x40000000) +#define M33_SYST_CALIB_SKEW_MSB _u(30) +#define M33_SYST_CALIB_SKEW_LSB _u(30) +#define M33_SYST_CALIB_SKEW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_SYST_CALIB_TENMS +// Description : An optional Reload value to be used for 10ms (100Hz) timing, +// subject to system clock skew errors. If the value reads as 0, +// the calibration value is not known. +#define M33_SYST_CALIB_TENMS_RESET _u(0x000000) +#define M33_SYST_CALIB_TENMS_BITS _u(0x00ffffff) +#define M33_SYST_CALIB_TENMS_MSB _u(23) +#define M33_SYST_CALIB_TENMS_LSB _u(0) +#define M33_SYST_CALIB_TENMS_ACCESS "RO" +// ============================================================================= +// Register : M33_NVIC_ISER0 +// Description : Enables or reads the enabled state of each group of 32 +// interrupts +#define M33_NVIC_ISER0_OFFSET _u(0x0000e100) +#define M33_NVIC_ISER0_BITS _u(0xffffffff) +#define M33_NVIC_ISER0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ISER0_SETENA +// Description : For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n +// + m is enabled +#define M33_NVIC_ISER0_SETENA_RESET _u(0x00000000) +#define M33_NVIC_ISER0_SETENA_BITS _u(0xffffffff) +#define M33_NVIC_ISER0_SETENA_MSB _u(31) +#define M33_NVIC_ISER0_SETENA_LSB _u(0) +#define M33_NVIC_ISER0_SETENA_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ISER1 +// Description : Enables or reads the enabled state of each group of 32 +// interrupts +#define M33_NVIC_ISER1_OFFSET _u(0x0000e104) +#define M33_NVIC_ISER1_BITS _u(0xffffffff) +#define M33_NVIC_ISER1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ISER1_SETENA +// Description : For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n +// + m is enabled +#define M33_NVIC_ISER1_SETENA_RESET _u(0x00000000) +#define M33_NVIC_ISER1_SETENA_BITS _u(0xffffffff) +#define M33_NVIC_ISER1_SETENA_MSB _u(31) +#define M33_NVIC_ISER1_SETENA_LSB _u(0) +#define M33_NVIC_ISER1_SETENA_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ICER0 +// Description : Clears or reads the enabled state of each group of 32 +// interrupts +#define M33_NVIC_ICER0_OFFSET _u(0x0000e180) +#define M33_NVIC_ICER0_BITS _u(0xffffffff) +#define M33_NVIC_ICER0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ICER0_CLRENA +// Description : For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n +// + m is enabled +#define M33_NVIC_ICER0_CLRENA_RESET _u(0x00000000) +#define M33_NVIC_ICER0_CLRENA_BITS _u(0xffffffff) +#define M33_NVIC_ICER0_CLRENA_MSB _u(31) +#define M33_NVIC_ICER0_CLRENA_LSB _u(0) +#define M33_NVIC_ICER0_CLRENA_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ICER1 +// Description : Clears or reads the enabled state of each group of 32 +// interrupts +#define M33_NVIC_ICER1_OFFSET _u(0x0000e184) +#define M33_NVIC_ICER1_BITS _u(0xffffffff) +#define M33_NVIC_ICER1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ICER1_CLRENA +// Description : For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n +// + m is enabled +#define M33_NVIC_ICER1_CLRENA_RESET _u(0x00000000) +#define M33_NVIC_ICER1_CLRENA_BITS _u(0xffffffff) +#define M33_NVIC_ICER1_CLRENA_MSB _u(31) +#define M33_NVIC_ICER1_CLRENA_LSB _u(0) +#define M33_NVIC_ICER1_CLRENA_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ISPR0 +// Description : Enables or reads the pending state of each group of 32 +// interrupts +#define M33_NVIC_ISPR0_OFFSET _u(0x0000e200) +#define M33_NVIC_ISPR0_BITS _u(0xffffffff) +#define M33_NVIC_ISPR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ISPR0_SETPEND +// Description : For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n +// + m is pending +#define M33_NVIC_ISPR0_SETPEND_RESET _u(0x00000000) +#define M33_NVIC_ISPR0_SETPEND_BITS _u(0xffffffff) +#define M33_NVIC_ISPR0_SETPEND_MSB _u(31) +#define M33_NVIC_ISPR0_SETPEND_LSB _u(0) +#define M33_NVIC_ISPR0_SETPEND_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ISPR1 +// Description : Enables or reads the pending state of each group of 32 +// interrupts +#define M33_NVIC_ISPR1_OFFSET _u(0x0000e204) +#define M33_NVIC_ISPR1_BITS _u(0xffffffff) +#define M33_NVIC_ISPR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ISPR1_SETPEND +// Description : For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n +// + m is pending +#define M33_NVIC_ISPR1_SETPEND_RESET _u(0x00000000) +#define M33_NVIC_ISPR1_SETPEND_BITS _u(0xffffffff) +#define M33_NVIC_ISPR1_SETPEND_MSB _u(31) +#define M33_NVIC_ISPR1_SETPEND_LSB _u(0) +#define M33_NVIC_ISPR1_SETPEND_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ICPR0 +// Description : Clears or reads the pending state of each group of 32 +// interrupts +#define M33_NVIC_ICPR0_OFFSET _u(0x0000e280) +#define M33_NVIC_ICPR0_BITS _u(0xffffffff) +#define M33_NVIC_ICPR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ICPR0_CLRPEND +// Description : For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n +// + m is pending +#define M33_NVIC_ICPR0_CLRPEND_RESET _u(0x00000000) +#define M33_NVIC_ICPR0_CLRPEND_BITS _u(0xffffffff) +#define M33_NVIC_ICPR0_CLRPEND_MSB _u(31) +#define M33_NVIC_ICPR0_CLRPEND_LSB _u(0) +#define M33_NVIC_ICPR0_CLRPEND_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ICPR1 +// Description : Clears or reads the pending state of each group of 32 +// interrupts +#define M33_NVIC_ICPR1_OFFSET _u(0x0000e284) +#define M33_NVIC_ICPR1_BITS _u(0xffffffff) +#define M33_NVIC_ICPR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ICPR1_CLRPEND +// Description : For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n +// + m is pending +#define M33_NVIC_ICPR1_CLRPEND_RESET _u(0x00000000) +#define M33_NVIC_ICPR1_CLRPEND_BITS _u(0xffffffff) +#define M33_NVIC_ICPR1_CLRPEND_MSB _u(31) +#define M33_NVIC_ICPR1_CLRPEND_LSB _u(0) +#define M33_NVIC_ICPR1_CLRPEND_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IABR0 +// Description : For each group of 32 interrupts, shows the active state of each +// interrupt +#define M33_NVIC_IABR0_OFFSET _u(0x0000e300) +#define M33_NVIC_IABR0_BITS _u(0xffffffff) +#define M33_NVIC_IABR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IABR0_ACTIVE +// Description : For ACTIVE[m] in NVIC_IABR*n, indicates the active state for +// interrupt 32*n+m +#define M33_NVIC_IABR0_ACTIVE_RESET _u(0x00000000) +#define M33_NVIC_IABR0_ACTIVE_BITS _u(0xffffffff) +#define M33_NVIC_IABR0_ACTIVE_MSB _u(31) +#define M33_NVIC_IABR0_ACTIVE_LSB _u(0) +#define M33_NVIC_IABR0_ACTIVE_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IABR1 +// Description : For each group of 32 interrupts, shows the active state of each +// interrupt +#define M33_NVIC_IABR1_OFFSET _u(0x0000e304) +#define M33_NVIC_IABR1_BITS _u(0xffffffff) +#define M33_NVIC_IABR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IABR1_ACTIVE +// Description : For ACTIVE[m] in NVIC_IABR*n, indicates the active state for +// interrupt 32*n+m +#define M33_NVIC_IABR1_ACTIVE_RESET _u(0x00000000) +#define M33_NVIC_IABR1_ACTIVE_BITS _u(0xffffffff) +#define M33_NVIC_IABR1_ACTIVE_MSB _u(31) +#define M33_NVIC_IABR1_ACTIVE_LSB _u(0) +#define M33_NVIC_IABR1_ACTIVE_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ITNS0 +// Description : For each group of 32 interrupts, determines whether each +// interrupt targets Non-secure or Secure state +#define M33_NVIC_ITNS0_OFFSET _u(0x0000e380) +#define M33_NVIC_ITNS0_BITS _u(0xffffffff) +#define M33_NVIC_ITNS0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ITNS0_ITNS +// Description : For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state +// for interrupt 32*n+m +#define M33_NVIC_ITNS0_ITNS_RESET _u(0x00000000) +#define M33_NVIC_ITNS0_ITNS_BITS _u(0xffffffff) +#define M33_NVIC_ITNS0_ITNS_MSB _u(31) +#define M33_NVIC_ITNS0_ITNS_LSB _u(0) +#define M33_NVIC_ITNS0_ITNS_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_ITNS1 +// Description : For each group of 32 interrupts, determines whether each +// interrupt targets Non-secure or Secure state +#define M33_NVIC_ITNS1_OFFSET _u(0x0000e384) +#define M33_NVIC_ITNS1_BITS _u(0xffffffff) +#define M33_NVIC_ITNS1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_ITNS1_ITNS +// Description : For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state +// for interrupt 32*n+m +#define M33_NVIC_ITNS1_ITNS_RESET _u(0x00000000) +#define M33_NVIC_ITNS1_ITNS_BITS _u(0xffffffff) +#define M33_NVIC_ITNS1_ITNS_MSB _u(31) +#define M33_NVIC_ITNS1_ITNS_LSB _u(0) +#define M33_NVIC_ITNS1_ITNS_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR0 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR0_OFFSET _u(0x0000e400) +#define M33_NVIC_IPR0_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR0_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR0_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR0_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR0_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR0_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR0_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR0_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR0_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR0_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR0_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR0_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR0_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR0_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR0_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR0_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR0_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR0_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR0_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR0_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR0_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR0_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR0_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR0_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR0_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR1 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR1_OFFSET _u(0x0000e404) +#define M33_NVIC_IPR1_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR1_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR1_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR1_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR1_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR1_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR1_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR1_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR1_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR1_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR1_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR1_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR1_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR1_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR1_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR1_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR1_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR1_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR1_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR1_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR1_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR1_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR1_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR1_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR1_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR2 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR2_OFFSET _u(0x0000e408) +#define M33_NVIC_IPR2_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR2_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR2_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR2_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR2_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR2_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR2_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR2_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR2_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR2_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR2_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR2_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR2_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR2_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR2_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR2_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR2_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR2_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR2_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR2_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR2_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR2_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR2_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR2_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR2_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR3 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR3_OFFSET _u(0x0000e40c) +#define M33_NVIC_IPR3_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR3_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR3_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR3_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR3_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR3_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR3_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR3_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR3_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR3_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR3_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR3_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR3_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR3_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR3_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR3_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR3_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR3_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR3_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR3_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR3_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR3_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR3_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR3_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR3_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR4 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR4_OFFSET _u(0x0000e410) +#define M33_NVIC_IPR4_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR4_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR4_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR4_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR4_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR4_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR4_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR4_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR4_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR4_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR4_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR4_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR4_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR4_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR4_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR4_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR4_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR4_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR4_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR4_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR4_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR4_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR4_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR4_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR4_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR5 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR5_OFFSET _u(0x0000e414) +#define M33_NVIC_IPR5_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR5_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR5_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR5_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR5_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR5_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR5_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR5_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR5_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR5_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR5_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR5_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR5_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR5_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR5_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR5_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR5_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR5_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR5_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR5_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR5_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR5_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR5_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR5_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR5_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR6 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR6_OFFSET _u(0x0000e418) +#define M33_NVIC_IPR6_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR6_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR6_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR6_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR6_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR6_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR6_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR6_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR6_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR6_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR6_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR6_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR6_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR6_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR6_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR6_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR6_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR6_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR6_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR6_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR6_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR6_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR6_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR6_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR6_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR7 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR7_OFFSET _u(0x0000e41c) +#define M33_NVIC_IPR7_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR7_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR7_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR7_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR7_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR7_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR7_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR7_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR7_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR7_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR7_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR7_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR7_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR7_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR7_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR7_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR7_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR7_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR7_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR7_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR7_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR7_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR7_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR7_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR7_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR8 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR8_OFFSET _u(0x0000e420) +#define M33_NVIC_IPR8_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR8_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR8_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR8_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR8_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR8_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR8_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR8_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR8_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR8_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR8_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR8_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR8_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR8_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR8_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR8_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR8_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR8_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR8_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR8_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR8_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR8_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR8_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR8_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR8_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR8_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR9 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR9_OFFSET _u(0x0000e424) +#define M33_NVIC_IPR9_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR9_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR9_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR9_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR9_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR9_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR9_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR9_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR9_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR9_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR9_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR9_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR9_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR9_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR9_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR9_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR9_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR9_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR9_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR9_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR9_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR9_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR9_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR9_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR9_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR9_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR10 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR10_OFFSET _u(0x0000e428) +#define M33_NVIC_IPR10_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR10_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR10_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR10_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR10_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR10_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR10_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR10_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR10_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR10_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR10_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR10_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR10_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR10_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR10_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR10_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR10_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR10_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR10_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR10_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR10_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR10_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR10_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR10_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR10_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR10_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR11 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR11_OFFSET _u(0x0000e42c) +#define M33_NVIC_IPR11_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR11_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR11_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR11_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR11_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR11_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR11_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR11_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR11_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR11_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR11_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR11_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR11_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR11_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR11_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR11_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR11_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR11_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR11_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR11_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR11_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR11_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR11_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR11_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR11_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR11_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR12 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR12_OFFSET _u(0x0000e430) +#define M33_NVIC_IPR12_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR12_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR12_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR12_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR12_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR12_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR12_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR12_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR12_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR12_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR12_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR12_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR12_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR12_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR12_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR12_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR12_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR12_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR12_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR12_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR12_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR12_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR12_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR12_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR12_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR12_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR13 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR13_OFFSET _u(0x0000e434) +#define M33_NVIC_IPR13_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR13_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR13_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR13_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR13_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR13_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR13_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR13_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR13_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR13_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR13_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR13_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR13_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR13_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR13_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR13_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR13_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR13_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR13_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR13_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR13_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR13_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR13_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR13_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR13_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR13_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR14 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR14_OFFSET _u(0x0000e438) +#define M33_NVIC_IPR14_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR14_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR14_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR14_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR14_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR14_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR14_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR14_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR14_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR14_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR14_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR14_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR14_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR14_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR14_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR14_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR14_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR14_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR14_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR14_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR14_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR14_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR14_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR14_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR14_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR14_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_NVIC_IPR15 +// Description : Sets or reads interrupt priorities +#define M33_NVIC_IPR15_OFFSET _u(0x0000e43c) +#define M33_NVIC_IPR15_BITS _u(0xf0f0f0f0) +#define M33_NVIC_IPR15_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR15_PRI_N3 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+3, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR15_PRI_N3_RESET _u(0x0) +#define M33_NVIC_IPR15_PRI_N3_BITS _u(0xf0000000) +#define M33_NVIC_IPR15_PRI_N3_MSB _u(31) +#define M33_NVIC_IPR15_PRI_N3_LSB _u(28) +#define M33_NVIC_IPR15_PRI_N3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR15_PRI_N2 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+2, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR15_PRI_N2_RESET _u(0x0) +#define M33_NVIC_IPR15_PRI_N2_BITS _u(0x00f00000) +#define M33_NVIC_IPR15_PRI_N2_MSB _u(23) +#define M33_NVIC_IPR15_PRI_N2_LSB _u(20) +#define M33_NVIC_IPR15_PRI_N2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR15_PRI_N1 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+1, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR15_PRI_N1_RESET _u(0x0) +#define M33_NVIC_IPR15_PRI_N1_BITS _u(0x0000f000) +#define M33_NVIC_IPR15_PRI_N1_MSB _u(15) +#define M33_NVIC_IPR15_PRI_N1_LSB _u(12) +#define M33_NVIC_IPR15_PRI_N1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NVIC_IPR15_PRI_N0 +// Description : For register NVIC_IPRn, the priority of interrupt number 4*n+0, +// or RES0 if the PE does not implement this interrupt +#define M33_NVIC_IPR15_PRI_N0_RESET _u(0x0) +#define M33_NVIC_IPR15_PRI_N0_BITS _u(0x000000f0) +#define M33_NVIC_IPR15_PRI_N0_MSB _u(7) +#define M33_NVIC_IPR15_PRI_N0_LSB _u(4) +#define M33_NVIC_IPR15_PRI_N0_ACCESS "RW" +// ============================================================================= +// Register : M33_CPUID +// Description : Provides identification information for the PE, including an +// implementer code for the device and a device ID number +#define M33_CPUID_OFFSET _u(0x0000ed00) +#define M33_CPUID_BITS _u(0xffffffff) +#define M33_CPUID_RESET _u(0x411fd210) +// ----------------------------------------------------------------------------- +// Field : M33_CPUID_IMPLEMENTER +// Description : This field must hold an implementer code that has been assigned +// by ARM +#define M33_CPUID_IMPLEMENTER_RESET _u(0x41) +#define M33_CPUID_IMPLEMENTER_BITS _u(0xff000000) +#define M33_CPUID_IMPLEMENTER_MSB _u(31) +#define M33_CPUID_IMPLEMENTER_LSB _u(24) +#define M33_CPUID_IMPLEMENTER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CPUID_VARIANT +// Description : IMPLEMENTATION DEFINED variant number. Typically, this field is +// used to distinguish between different product variants, or +// major revisions of a product +#define M33_CPUID_VARIANT_RESET _u(0x1) +#define M33_CPUID_VARIANT_BITS _u(0x00f00000) +#define M33_CPUID_VARIANT_MSB _u(23) +#define M33_CPUID_VARIANT_LSB _u(20) +#define M33_CPUID_VARIANT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CPUID_ARCHITECTURE +// Description : Defines the Architecture implemented by the PE +#define M33_CPUID_ARCHITECTURE_RESET _u(0xf) +#define M33_CPUID_ARCHITECTURE_BITS _u(0x000f0000) +#define M33_CPUID_ARCHITECTURE_MSB _u(19) +#define M33_CPUID_ARCHITECTURE_LSB _u(16) +#define M33_CPUID_ARCHITECTURE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CPUID_PARTNO +// Description : IMPLEMENTATION DEFINED primary part number for the device +#define M33_CPUID_PARTNO_RESET _u(0xd21) +#define M33_CPUID_PARTNO_BITS _u(0x0000fff0) +#define M33_CPUID_PARTNO_MSB _u(15) +#define M33_CPUID_PARTNO_LSB _u(4) +#define M33_CPUID_PARTNO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CPUID_REVISION +// Description : IMPLEMENTATION DEFINED revision number for the device +#define M33_CPUID_REVISION_RESET _u(0x0) +#define M33_CPUID_REVISION_BITS _u(0x0000000f) +#define M33_CPUID_REVISION_MSB _u(3) +#define M33_CPUID_REVISION_LSB _u(0) +#define M33_CPUID_REVISION_ACCESS "RO" +// ============================================================================= +// Register : M33_ICSR +// Description : Controls and provides status information for NMI, PendSV, +// SysTick and interrupts +#define M33_ICSR_OFFSET _u(0x0000ed04) +#define M33_ICSR_BITS _u(0xdfdff9ff) +#define M33_ICSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_PENDNMISET +// Description : Indicates whether the NMI exception is pending +#define M33_ICSR_PENDNMISET_RESET _u(0x0) +#define M33_ICSR_PENDNMISET_BITS _u(0x80000000) +#define M33_ICSR_PENDNMISET_MSB _u(31) +#define M33_ICSR_PENDNMISET_LSB _u(31) +#define M33_ICSR_PENDNMISET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_PENDNMICLR +// Description : Allows the NMI exception pend state to be cleared +#define M33_ICSR_PENDNMICLR_RESET _u(0x0) +#define M33_ICSR_PENDNMICLR_BITS _u(0x40000000) +#define M33_ICSR_PENDNMICLR_MSB _u(30) +#define M33_ICSR_PENDNMICLR_LSB _u(30) +#define M33_ICSR_PENDNMICLR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_PENDSVSET +// Description : Indicates whether the PendSV `FTSSS exception is pending +#define M33_ICSR_PENDSVSET_RESET _u(0x0) +#define M33_ICSR_PENDSVSET_BITS _u(0x10000000) +#define M33_ICSR_PENDSVSET_MSB _u(28) +#define M33_ICSR_PENDSVSET_LSB _u(28) +#define M33_ICSR_PENDSVSET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_PENDSVCLR +// Description : Allows the PendSV exception pend state to be cleared `FTSSS +#define M33_ICSR_PENDSVCLR_RESET _u(0x0) +#define M33_ICSR_PENDSVCLR_BITS _u(0x08000000) +#define M33_ICSR_PENDSVCLR_MSB _u(27) +#define M33_ICSR_PENDSVCLR_LSB _u(27) +#define M33_ICSR_PENDSVCLR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_PENDSTSET +// Description : Indicates whether the SysTick `FTSSS exception is pending +#define M33_ICSR_PENDSTSET_RESET _u(0x0) +#define M33_ICSR_PENDSTSET_BITS _u(0x04000000) +#define M33_ICSR_PENDSTSET_MSB _u(26) +#define M33_ICSR_PENDSTSET_LSB _u(26) +#define M33_ICSR_PENDSTSET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_PENDSTCLR +// Description : Allows the SysTick exception pend state to be cleared `FTSSS +#define M33_ICSR_PENDSTCLR_RESET _u(0x0) +#define M33_ICSR_PENDSTCLR_BITS _u(0x02000000) +#define M33_ICSR_PENDSTCLR_MSB _u(25) +#define M33_ICSR_PENDSTCLR_LSB _u(25) +#define M33_ICSR_PENDSTCLR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_STTNS +// Description : Controls whether in a single SysTick implementation, the +// SysTick is Secure or Non-secure +#define M33_ICSR_STTNS_RESET _u(0x0) +#define M33_ICSR_STTNS_BITS _u(0x01000000) +#define M33_ICSR_STTNS_MSB _u(24) +#define M33_ICSR_STTNS_LSB _u(24) +#define M33_ICSR_STTNS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_ISRPREEMPT +// Description : Indicates whether a pending exception will be serviced on exit +// from debug halt state +#define M33_ICSR_ISRPREEMPT_RESET _u(0x0) +#define M33_ICSR_ISRPREEMPT_BITS _u(0x00800000) +#define M33_ICSR_ISRPREEMPT_MSB _u(23) +#define M33_ICSR_ISRPREEMPT_LSB _u(23) +#define M33_ICSR_ISRPREEMPT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_ISRPENDING +// Description : Indicates whether an external interrupt, generated by the NVIC, +// is pending +#define M33_ICSR_ISRPENDING_RESET _u(0x0) +#define M33_ICSR_ISRPENDING_BITS _u(0x00400000) +#define M33_ICSR_ISRPENDING_MSB _u(22) +#define M33_ICSR_ISRPENDING_LSB _u(22) +#define M33_ICSR_ISRPENDING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_VECTPENDING +// Description : The exception number of the highest priority pending and +// enabled interrupt +#define M33_ICSR_VECTPENDING_RESET _u(0x000) +#define M33_ICSR_VECTPENDING_BITS _u(0x001ff000) +#define M33_ICSR_VECTPENDING_MSB _u(20) +#define M33_ICSR_VECTPENDING_LSB _u(12) +#define M33_ICSR_VECTPENDING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_RETTOBASE +// Description : In Handler mode, indicates whether there is more than one +// active exception +#define M33_ICSR_RETTOBASE_RESET _u(0x0) +#define M33_ICSR_RETTOBASE_BITS _u(0x00000800) +#define M33_ICSR_RETTOBASE_MSB _u(11) +#define M33_ICSR_RETTOBASE_LSB _u(11) +#define M33_ICSR_RETTOBASE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ICSR_VECTACTIVE +// Description : The exception number of the current executing exception +#define M33_ICSR_VECTACTIVE_RESET _u(0x000) +#define M33_ICSR_VECTACTIVE_BITS _u(0x000001ff) +#define M33_ICSR_VECTACTIVE_MSB _u(8) +#define M33_ICSR_VECTACTIVE_LSB _u(0) +#define M33_ICSR_VECTACTIVE_ACCESS "RO" +// ============================================================================= +// Register : M33_VTOR +// Description : The VTOR indicates the offset of the vector table base address +// from memory address 0x00000000. +#define M33_VTOR_OFFSET _u(0x0000ed08) +#define M33_VTOR_BITS _u(0xffffff80) +#define M33_VTOR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_VTOR_TBLOFF +// Description : Vector table base offset field. It contains bits[31:7] of the +// offset of the table base from the bottom of the memory map. +#define M33_VTOR_TBLOFF_RESET _u(0x0000000) +#define M33_VTOR_TBLOFF_BITS _u(0xffffff80) +#define M33_VTOR_TBLOFF_MSB _u(31) +#define M33_VTOR_TBLOFF_LSB _u(7) +#define M33_VTOR_TBLOFF_ACCESS "RW" +// ============================================================================= +// Register : M33_AIRCR +// Description : Use the Application Interrupt and Reset Control Register to: +// determine data endianness, clear all active state information +// from debug halt mode, request a system reset. +#define M33_AIRCR_OFFSET _u(0x0000ed0c) +#define M33_AIRCR_BITS _u(0xffffe70e) +#define M33_AIRCR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_VECTKEY +// Description : Register key: +// Reads as Unknown +// On writes, write 0x05FA to VECTKEY, otherwise the write is +// ignored. +#define M33_AIRCR_VECTKEY_RESET _u(0x0000) +#define M33_AIRCR_VECTKEY_BITS _u(0xffff0000) +#define M33_AIRCR_VECTKEY_MSB _u(31) +#define M33_AIRCR_VECTKEY_LSB _u(16) +#define M33_AIRCR_VECTKEY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_ENDIANESS +// Description : Data endianness implemented: +// 0 = Little-endian. +#define M33_AIRCR_ENDIANESS_RESET _u(0x0) +#define M33_AIRCR_ENDIANESS_BITS _u(0x00008000) +#define M33_AIRCR_ENDIANESS_MSB _u(15) +#define M33_AIRCR_ENDIANESS_LSB _u(15) +#define M33_AIRCR_ENDIANESS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_PRIS +// Description : Prioritize Secure exceptions. The value of this bit defines +// whether Secure exception priority boosting is enabled. +// 0 Priority ranges of Secure and Non-secure exceptions are +// identical. +// 1 Non-secure exceptions are de-prioritized. +#define M33_AIRCR_PRIS_RESET _u(0x0) +#define M33_AIRCR_PRIS_BITS _u(0x00004000) +#define M33_AIRCR_PRIS_MSB _u(14) +#define M33_AIRCR_PRIS_LSB _u(14) +#define M33_AIRCR_PRIS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_BFHFNMINS +// Description : BusFault, HardFault, and NMI Non-secure enable. +// 0 BusFault, HardFault, and NMI are Secure. +// 1 BusFault and NMI are Non-secure and exceptions can target +// Non-secure HardFault. +#define M33_AIRCR_BFHFNMINS_RESET _u(0x0) +#define M33_AIRCR_BFHFNMINS_BITS _u(0x00002000) +#define M33_AIRCR_BFHFNMINS_MSB _u(13) +#define M33_AIRCR_BFHFNMINS_LSB _u(13) +#define M33_AIRCR_BFHFNMINS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_PRIGROUP +// Description : Interrupt priority grouping field. This field determines the +// split of group priority from subpriority. +// See https://developer.arm.com/documentation/100235/0004/the- +// cortex-m33-peripherals/system-control-block/application- +// interrupt-and-reset-control-register?lang=en +#define M33_AIRCR_PRIGROUP_RESET _u(0x0) +#define M33_AIRCR_PRIGROUP_BITS _u(0x00000700) +#define M33_AIRCR_PRIGROUP_MSB _u(10) +#define M33_AIRCR_PRIGROUP_LSB _u(8) +#define M33_AIRCR_PRIGROUP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_SYSRESETREQS +// Description : System reset request, Secure state only. +// 0 SYSRESETREQ functionality is available to both Security +// states. +// 1 SYSRESETREQ functionality is only available to Secure state. +#define M33_AIRCR_SYSRESETREQS_RESET _u(0x0) +#define M33_AIRCR_SYSRESETREQS_BITS _u(0x00000008) +#define M33_AIRCR_SYSRESETREQS_MSB _u(3) +#define M33_AIRCR_SYSRESETREQS_LSB _u(3) +#define M33_AIRCR_SYSRESETREQS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_SYSRESETREQ +// Description : Writing 1 to this bit causes the SYSRESETREQ signal to the +// outer system to be asserted to request a reset. The intention +// is to force a large system reset of all major components except +// for debug. The C_HALT bit in the DHCSR is cleared as a result +// of the system reset requested. The debugger does not lose +// contact with the device. +#define M33_AIRCR_SYSRESETREQ_RESET _u(0x0) +#define M33_AIRCR_SYSRESETREQ_BITS _u(0x00000004) +#define M33_AIRCR_SYSRESETREQ_MSB _u(2) +#define M33_AIRCR_SYSRESETREQ_LSB _u(2) +#define M33_AIRCR_SYSRESETREQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_AIRCR_VECTCLRACTIVE +// Description : Clears all active state information for fixed and configurable +// exceptions. This bit: is self-clearing, can only be set by the +// DAP when the core is halted. When set: clears all active +// exception status of the processor, forces a return to Thread +// mode, forces an IPSR of 0. A debugger must re-initialize the +// stack. +#define M33_AIRCR_VECTCLRACTIVE_RESET _u(0x0) +#define M33_AIRCR_VECTCLRACTIVE_BITS _u(0x00000002) +#define M33_AIRCR_VECTCLRACTIVE_MSB _u(1) +#define M33_AIRCR_VECTCLRACTIVE_LSB _u(1) +#define M33_AIRCR_VECTCLRACTIVE_ACCESS "RW" +// ============================================================================= +// Register : M33_SCR +// Description : System Control Register. Use the System Control Register for +// power-management functions: signal to the system when the +// processor can enter a low power state, control how the +// processor enters and exits low power states. +#define M33_SCR_OFFSET _u(0x0000ed10) +#define M33_SCR_BITS _u(0x0000001e) +#define M33_SCR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SCR_SEVONPEND +// Description : Send Event on Pending bit: +// 0 = Only enabled interrupts or events can wakeup the processor, +// disabled interrupts are excluded. +// 1 = Enabled events and all interrupts, including disabled +// interrupts, can wakeup the processor. +// When an event or interrupt becomes pending, the event signal +// wakes up the processor from WFE. If the +// processor is not waiting for an event, the event is registered +// and affects the next WFE. +// The processor also wakes up on execution of an SEV instruction +// or an external event. +#define M33_SCR_SEVONPEND_RESET _u(0x0) +#define M33_SCR_SEVONPEND_BITS _u(0x00000010) +#define M33_SCR_SEVONPEND_MSB _u(4) +#define M33_SCR_SEVONPEND_LSB _u(4) +#define M33_SCR_SEVONPEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SCR_SLEEPDEEPS +// Description : 0 SLEEPDEEP is available to both security states +// 1 SLEEPDEEP is only available to Secure state +#define M33_SCR_SLEEPDEEPS_RESET _u(0x0) +#define M33_SCR_SLEEPDEEPS_BITS _u(0x00000008) +#define M33_SCR_SLEEPDEEPS_MSB _u(3) +#define M33_SCR_SLEEPDEEPS_LSB _u(3) +#define M33_SCR_SLEEPDEEPS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SCR_SLEEPDEEP +// Description : Controls whether the processor uses sleep or deep sleep as its +// low power mode: +// 0 = Sleep. +// 1 = Deep sleep. +#define M33_SCR_SLEEPDEEP_RESET _u(0x0) +#define M33_SCR_SLEEPDEEP_BITS _u(0x00000004) +#define M33_SCR_SLEEPDEEP_MSB _u(2) +#define M33_SCR_SLEEPDEEP_LSB _u(2) +#define M33_SCR_SLEEPDEEP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SCR_SLEEPONEXIT +// Description : Indicates sleep-on-exit when returning from Handler mode to +// Thread mode: +// 0 = Do not sleep when returning to Thread mode. +// 1 = Enter sleep, or deep sleep, on return from an ISR to Thread +// mode. +// Setting this bit to 1 enables an interrupt driven application +// to avoid returning to an empty main application. +#define M33_SCR_SLEEPONEXIT_RESET _u(0x0) +#define M33_SCR_SLEEPONEXIT_BITS _u(0x00000002) +#define M33_SCR_SLEEPONEXIT_MSB _u(1) +#define M33_SCR_SLEEPONEXIT_LSB _u(1) +#define M33_SCR_SLEEPONEXIT_ACCESS "RW" +// ============================================================================= +// Register : M33_CCR +// Description : Sets or returns configuration and control data +#define M33_CCR_OFFSET _u(0x0000ed14) +#define M33_CCR_BITS _u(0x0007071b) +#define M33_CCR_RESET _u(0x00000201) +// ----------------------------------------------------------------------------- +// Field : M33_CCR_BP +// Description : Enables program flow prediction `FTSSS +#define M33_CCR_BP_RESET _u(0x0) +#define M33_CCR_BP_BITS _u(0x00040000) +#define M33_CCR_BP_MSB _u(18) +#define M33_CCR_BP_LSB _u(18) +#define M33_CCR_BP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_IC +// Description : This is a global enable bit for instruction caches in the +// selected Security state +#define M33_CCR_IC_RESET _u(0x0) +#define M33_CCR_IC_BITS _u(0x00020000) +#define M33_CCR_IC_MSB _u(17) +#define M33_CCR_IC_LSB _u(17) +#define M33_CCR_IC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_DC +// Description : Enables data caching of all data accesses to Normal memory +// `FTSSS +#define M33_CCR_DC_RESET _u(0x0) +#define M33_CCR_DC_BITS _u(0x00010000) +#define M33_CCR_DC_MSB _u(16) +#define M33_CCR_DC_LSB _u(16) +#define M33_CCR_DC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_STKOFHFNMIGN +// Description : Controls the effect of a stack limit violation while executing +// at a requested priority less than 0 +#define M33_CCR_STKOFHFNMIGN_RESET _u(0x0) +#define M33_CCR_STKOFHFNMIGN_BITS _u(0x00000400) +#define M33_CCR_STKOFHFNMIGN_MSB _u(10) +#define M33_CCR_STKOFHFNMIGN_LSB _u(10) +#define M33_CCR_STKOFHFNMIGN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_RES1 +// Description : Reserved, RES1 +#define M33_CCR_RES1_RESET _u(0x1) +#define M33_CCR_RES1_BITS _u(0x00000200) +#define M33_CCR_RES1_MSB _u(9) +#define M33_CCR_RES1_LSB _u(9) +#define M33_CCR_RES1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_BFHFNMIGN +// Description : Determines the effect of precise BusFaults on handlers running +// at a requested priority less than 0 +#define M33_CCR_BFHFNMIGN_RESET _u(0x0) +#define M33_CCR_BFHFNMIGN_BITS _u(0x00000100) +#define M33_CCR_BFHFNMIGN_MSB _u(8) +#define M33_CCR_BFHFNMIGN_LSB _u(8) +#define M33_CCR_BFHFNMIGN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_DIV_0_TRP +// Description : Controls the generation of a DIVBYZERO UsageFault when +// attempting to perform integer division by zero +#define M33_CCR_DIV_0_TRP_RESET _u(0x0) +#define M33_CCR_DIV_0_TRP_BITS _u(0x00000010) +#define M33_CCR_DIV_0_TRP_MSB _u(4) +#define M33_CCR_DIV_0_TRP_LSB _u(4) +#define M33_CCR_DIV_0_TRP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_UNALIGN_TRP +// Description : Controls the trapping of unaligned word or halfword accesses +#define M33_CCR_UNALIGN_TRP_RESET _u(0x0) +#define M33_CCR_UNALIGN_TRP_BITS _u(0x00000008) +#define M33_CCR_UNALIGN_TRP_MSB _u(3) +#define M33_CCR_UNALIGN_TRP_LSB _u(3) +#define M33_CCR_UNALIGN_TRP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_USERSETMPEND +// Description : Determines whether unprivileged accesses are permitted to pend +// interrupts via the STIR +#define M33_CCR_USERSETMPEND_RESET _u(0x0) +#define M33_CCR_USERSETMPEND_BITS _u(0x00000002) +#define M33_CCR_USERSETMPEND_MSB _u(1) +#define M33_CCR_USERSETMPEND_LSB _u(1) +#define M33_CCR_USERSETMPEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CCR_RES1_1 +// Description : Reserved, RES1 +#define M33_CCR_RES1_1_RESET _u(0x1) +#define M33_CCR_RES1_1_BITS _u(0x00000001) +#define M33_CCR_RES1_1_MSB _u(0) +#define M33_CCR_RES1_1_LSB _u(0) +#define M33_CCR_RES1_1_ACCESS "RO" +// ============================================================================= +// Register : M33_SHPR1 +// Description : Sets or returns priority for system handlers 4 - 7 +#define M33_SHPR1_OFFSET _u(0x0000ed18) +#define M33_SHPR1_BITS _u(0xe0e0e0e0) +#define M33_SHPR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SHPR1_PRI_7_3 +// Description : Priority of system handler 7, SecureFault +#define M33_SHPR1_PRI_7_3_RESET _u(0x0) +#define M33_SHPR1_PRI_7_3_BITS _u(0xe0000000) +#define M33_SHPR1_PRI_7_3_MSB _u(31) +#define M33_SHPR1_PRI_7_3_LSB _u(29) +#define M33_SHPR1_PRI_7_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR1_PRI_6_3 +// Description : Priority of system handler 6, SecureFault +#define M33_SHPR1_PRI_6_3_RESET _u(0x0) +#define M33_SHPR1_PRI_6_3_BITS _u(0x00e00000) +#define M33_SHPR1_PRI_6_3_MSB _u(23) +#define M33_SHPR1_PRI_6_3_LSB _u(21) +#define M33_SHPR1_PRI_6_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR1_PRI_5_3 +// Description : Priority of system handler 5, SecureFault +#define M33_SHPR1_PRI_5_3_RESET _u(0x0) +#define M33_SHPR1_PRI_5_3_BITS _u(0x0000e000) +#define M33_SHPR1_PRI_5_3_MSB _u(15) +#define M33_SHPR1_PRI_5_3_LSB _u(13) +#define M33_SHPR1_PRI_5_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR1_PRI_4_3 +// Description : Priority of system handler 4, SecureFault +#define M33_SHPR1_PRI_4_3_RESET _u(0x0) +#define M33_SHPR1_PRI_4_3_BITS _u(0x000000e0) +#define M33_SHPR1_PRI_4_3_MSB _u(7) +#define M33_SHPR1_PRI_4_3_LSB _u(5) +#define M33_SHPR1_PRI_4_3_ACCESS "RW" +// ============================================================================= +// Register : M33_SHPR2 +// Description : Sets or returns priority for system handlers 8 - 11 +#define M33_SHPR2_OFFSET _u(0x0000ed1c) +#define M33_SHPR2_BITS _u(0xe0ffffff) +#define M33_SHPR2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SHPR2_PRI_11_3 +// Description : Priority of system handler 11, SecureFault +#define M33_SHPR2_PRI_11_3_RESET _u(0x0) +#define M33_SHPR2_PRI_11_3_BITS _u(0xe0000000) +#define M33_SHPR2_PRI_11_3_MSB _u(31) +#define M33_SHPR2_PRI_11_3_LSB _u(29) +#define M33_SHPR2_PRI_11_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR2_PRI_10 +// Description : Reserved, RES0 +#define M33_SHPR2_PRI_10_RESET _u(0x00) +#define M33_SHPR2_PRI_10_BITS _u(0x00ff0000) +#define M33_SHPR2_PRI_10_MSB _u(23) +#define M33_SHPR2_PRI_10_LSB _u(16) +#define M33_SHPR2_PRI_10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR2_PRI_9 +// Description : Reserved, RES0 +#define M33_SHPR2_PRI_9_RESET _u(0x00) +#define M33_SHPR2_PRI_9_BITS _u(0x0000ff00) +#define M33_SHPR2_PRI_9_MSB _u(15) +#define M33_SHPR2_PRI_9_LSB _u(8) +#define M33_SHPR2_PRI_9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR2_PRI_8 +// Description : Reserved, RES0 +#define M33_SHPR2_PRI_8_RESET _u(0x00) +#define M33_SHPR2_PRI_8_BITS _u(0x000000ff) +#define M33_SHPR2_PRI_8_MSB _u(7) +#define M33_SHPR2_PRI_8_LSB _u(0) +#define M33_SHPR2_PRI_8_ACCESS "RO" +// ============================================================================= +// Register : M33_SHPR3 +// Description : Sets or returns priority for system handlers 12 - 15 +#define M33_SHPR3_OFFSET _u(0x0000ed20) +#define M33_SHPR3_BITS _u(0xe0e0ffe0) +#define M33_SHPR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SHPR3_PRI_15_3 +// Description : Priority of system handler 15, SecureFault +#define M33_SHPR3_PRI_15_3_RESET _u(0x0) +#define M33_SHPR3_PRI_15_3_BITS _u(0xe0000000) +#define M33_SHPR3_PRI_15_3_MSB _u(31) +#define M33_SHPR3_PRI_15_3_LSB _u(29) +#define M33_SHPR3_PRI_15_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR3_PRI_14_3 +// Description : Priority of system handler 14, SecureFault +#define M33_SHPR3_PRI_14_3_RESET _u(0x0) +#define M33_SHPR3_PRI_14_3_BITS _u(0x00e00000) +#define M33_SHPR3_PRI_14_3_MSB _u(23) +#define M33_SHPR3_PRI_14_3_LSB _u(21) +#define M33_SHPR3_PRI_14_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR3_PRI_13 +// Description : Reserved, RES0 +#define M33_SHPR3_PRI_13_RESET _u(0x00) +#define M33_SHPR3_PRI_13_BITS _u(0x0000ff00) +#define M33_SHPR3_PRI_13_MSB _u(15) +#define M33_SHPR3_PRI_13_LSB _u(8) +#define M33_SHPR3_PRI_13_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_SHPR3_PRI_12_3 +// Description : Priority of system handler 12, SecureFault +#define M33_SHPR3_PRI_12_3_RESET _u(0x0) +#define M33_SHPR3_PRI_12_3_BITS _u(0x000000e0) +#define M33_SHPR3_PRI_12_3_MSB _u(7) +#define M33_SHPR3_PRI_12_3_LSB _u(5) +#define M33_SHPR3_PRI_12_3_ACCESS "RW" +// ============================================================================= +// Register : M33_SHCSR +// Description : Provides access to the active and pending status of system +// exceptions +#define M33_SHCSR_OFFSET _u(0x0000ed24) +#define M33_SHCSR_BITS _u(0x003ffdbf) +#define M33_SHCSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_HARDFAULTPENDED +// Description : `IAAMO the pending state of the HardFault exception `CTTSSS +#define M33_SHCSR_HARDFAULTPENDED_RESET _u(0x0) +#define M33_SHCSR_HARDFAULTPENDED_BITS _u(0x00200000) +#define M33_SHCSR_HARDFAULTPENDED_MSB _u(21) +#define M33_SHCSR_HARDFAULTPENDED_LSB _u(21) +#define M33_SHCSR_HARDFAULTPENDED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_SECUREFAULTPENDED +// Description : `IAAMO the pending state of the SecureFault exception +#define M33_SHCSR_SECUREFAULTPENDED_RESET _u(0x0) +#define M33_SHCSR_SECUREFAULTPENDED_BITS _u(0x00100000) +#define M33_SHCSR_SECUREFAULTPENDED_MSB _u(20) +#define M33_SHCSR_SECUREFAULTPENDED_LSB _u(20) +#define M33_SHCSR_SECUREFAULTPENDED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_SECUREFAULTENA +// Description : `DW the SecureFault exception is enabled +#define M33_SHCSR_SECUREFAULTENA_RESET _u(0x0) +#define M33_SHCSR_SECUREFAULTENA_BITS _u(0x00080000) +#define M33_SHCSR_SECUREFAULTENA_MSB _u(19) +#define M33_SHCSR_SECUREFAULTENA_LSB _u(19) +#define M33_SHCSR_SECUREFAULTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_USGFAULTENA +// Description : `DW the UsageFault exception is enabled `FTSSS +#define M33_SHCSR_USGFAULTENA_RESET _u(0x0) +#define M33_SHCSR_USGFAULTENA_BITS _u(0x00040000) +#define M33_SHCSR_USGFAULTENA_MSB _u(18) +#define M33_SHCSR_USGFAULTENA_LSB _u(18) +#define M33_SHCSR_USGFAULTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_BUSFAULTENA +// Description : `DW the BusFault exception is enabled +#define M33_SHCSR_BUSFAULTENA_RESET _u(0x0) +#define M33_SHCSR_BUSFAULTENA_BITS _u(0x00020000) +#define M33_SHCSR_BUSFAULTENA_MSB _u(17) +#define M33_SHCSR_BUSFAULTENA_LSB _u(17) +#define M33_SHCSR_BUSFAULTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_MEMFAULTENA +// Description : `DW the MemManage exception is enabled `FTSSS +#define M33_SHCSR_MEMFAULTENA_RESET _u(0x0) +#define M33_SHCSR_MEMFAULTENA_BITS _u(0x00010000) +#define M33_SHCSR_MEMFAULTENA_MSB _u(16) +#define M33_SHCSR_MEMFAULTENA_LSB _u(16) +#define M33_SHCSR_MEMFAULTENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_SVCALLPENDED +// Description : `IAAMO the pending state of the SVCall exception `FTSSS +#define M33_SHCSR_SVCALLPENDED_RESET _u(0x0) +#define M33_SHCSR_SVCALLPENDED_BITS _u(0x00008000) +#define M33_SHCSR_SVCALLPENDED_MSB _u(15) +#define M33_SHCSR_SVCALLPENDED_LSB _u(15) +#define M33_SHCSR_SVCALLPENDED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_BUSFAULTPENDED +// Description : `IAAMO the pending state of the BusFault exception +#define M33_SHCSR_BUSFAULTPENDED_RESET _u(0x0) +#define M33_SHCSR_BUSFAULTPENDED_BITS _u(0x00004000) +#define M33_SHCSR_BUSFAULTPENDED_MSB _u(14) +#define M33_SHCSR_BUSFAULTPENDED_LSB _u(14) +#define M33_SHCSR_BUSFAULTPENDED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_MEMFAULTPENDED +// Description : `IAAMO the pending state of the MemManage exception `FTSSS +#define M33_SHCSR_MEMFAULTPENDED_RESET _u(0x0) +#define M33_SHCSR_MEMFAULTPENDED_BITS _u(0x00002000) +#define M33_SHCSR_MEMFAULTPENDED_MSB _u(13) +#define M33_SHCSR_MEMFAULTPENDED_LSB _u(13) +#define M33_SHCSR_MEMFAULTPENDED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_USGFAULTPENDED +// Description : The UsageFault exception is banked between Security states, +// `IAAMO the pending state of the UsageFault exception `FTSSS +#define M33_SHCSR_USGFAULTPENDED_RESET _u(0x0) +#define M33_SHCSR_USGFAULTPENDED_BITS _u(0x00001000) +#define M33_SHCSR_USGFAULTPENDED_MSB _u(12) +#define M33_SHCSR_USGFAULTPENDED_LSB _u(12) +#define M33_SHCSR_USGFAULTPENDED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_SYSTICKACT +// Description : `IAAMO the active state of the SysTick exception `FTSSS +#define M33_SHCSR_SYSTICKACT_RESET _u(0x0) +#define M33_SHCSR_SYSTICKACT_BITS _u(0x00000800) +#define M33_SHCSR_SYSTICKACT_MSB _u(11) +#define M33_SHCSR_SYSTICKACT_LSB _u(11) +#define M33_SHCSR_SYSTICKACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_PENDSVACT +// Description : `IAAMO the active state of the PendSV exception `FTSSS +#define M33_SHCSR_PENDSVACT_RESET _u(0x0) +#define M33_SHCSR_PENDSVACT_BITS _u(0x00000400) +#define M33_SHCSR_PENDSVACT_MSB _u(10) +#define M33_SHCSR_PENDSVACT_LSB _u(10) +#define M33_SHCSR_PENDSVACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_MONITORACT +// Description : `IAAMO the active state of the DebugMonitor exception +#define M33_SHCSR_MONITORACT_RESET _u(0x0) +#define M33_SHCSR_MONITORACT_BITS _u(0x00000100) +#define M33_SHCSR_MONITORACT_MSB _u(8) +#define M33_SHCSR_MONITORACT_LSB _u(8) +#define M33_SHCSR_MONITORACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_SVCALLACT +// Description : `IAAMO the active state of the SVCall exception `FTSSS +#define M33_SHCSR_SVCALLACT_RESET _u(0x0) +#define M33_SHCSR_SVCALLACT_BITS _u(0x00000080) +#define M33_SHCSR_SVCALLACT_MSB _u(7) +#define M33_SHCSR_SVCALLACT_LSB _u(7) +#define M33_SHCSR_SVCALLACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_NMIACT +// Description : `IAAMO the active state of the NMI exception +#define M33_SHCSR_NMIACT_RESET _u(0x0) +#define M33_SHCSR_NMIACT_BITS _u(0x00000020) +#define M33_SHCSR_NMIACT_MSB _u(5) +#define M33_SHCSR_NMIACT_LSB _u(5) +#define M33_SHCSR_NMIACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_SECUREFAULTACT +// Description : `IAAMO the active state of the SecureFault exception +#define M33_SHCSR_SECUREFAULTACT_RESET _u(0x0) +#define M33_SHCSR_SECUREFAULTACT_BITS _u(0x00000010) +#define M33_SHCSR_SECUREFAULTACT_MSB _u(4) +#define M33_SHCSR_SECUREFAULTACT_LSB _u(4) +#define M33_SHCSR_SECUREFAULTACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_USGFAULTACT +// Description : `IAAMO the active state of the UsageFault exception `FTSSS +#define M33_SHCSR_USGFAULTACT_RESET _u(0x0) +#define M33_SHCSR_USGFAULTACT_BITS _u(0x00000008) +#define M33_SHCSR_USGFAULTACT_MSB _u(3) +#define M33_SHCSR_USGFAULTACT_LSB _u(3) +#define M33_SHCSR_USGFAULTACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_HARDFAULTACT +// Description : Indicates and allows limited modification of the active state +// of the HardFault exception `FTSSS +#define M33_SHCSR_HARDFAULTACT_RESET _u(0x0) +#define M33_SHCSR_HARDFAULTACT_BITS _u(0x00000004) +#define M33_SHCSR_HARDFAULTACT_MSB _u(2) +#define M33_SHCSR_HARDFAULTACT_LSB _u(2) +#define M33_SHCSR_HARDFAULTACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_BUSFAULTACT +// Description : `IAAMO the active state of the BusFault exception +#define M33_SHCSR_BUSFAULTACT_RESET _u(0x0) +#define M33_SHCSR_BUSFAULTACT_BITS _u(0x00000002) +#define M33_SHCSR_BUSFAULTACT_MSB _u(1) +#define M33_SHCSR_BUSFAULTACT_LSB _u(1) +#define M33_SHCSR_BUSFAULTACT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SHCSR_MEMFAULTACT +// Description : `IAAMO the active state of the MemManage exception `FTSSS +#define M33_SHCSR_MEMFAULTACT_RESET _u(0x0) +#define M33_SHCSR_MEMFAULTACT_BITS _u(0x00000001) +#define M33_SHCSR_MEMFAULTACT_MSB _u(0) +#define M33_SHCSR_MEMFAULTACT_LSB _u(0) +#define M33_SHCSR_MEMFAULTACT_ACCESS "RW" +// ============================================================================= +// Register : M33_CFSR +// Description : Contains the three Configurable Fault Status Registers. +// +// 31:16 UFSR: Provides information on UsageFault exceptions +// +// 15:8 BFSR: Provides information on BusFault exceptions +// +// 7:0 MMFSR: Provides information on MemManage exceptions +#define M33_CFSR_OFFSET _u(0x0000ed28) +#define M33_CFSR_BITS _u(0x031fbfff) +#define M33_CFSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_UFSR_DIVBYZERO +// Description : Sticky flag indicating whether an integer division by zero +// error has occurred +#define M33_CFSR_UFSR_DIVBYZERO_RESET _u(0x0) +#define M33_CFSR_UFSR_DIVBYZERO_BITS _u(0x02000000) +#define M33_CFSR_UFSR_DIVBYZERO_MSB _u(25) +#define M33_CFSR_UFSR_DIVBYZERO_LSB _u(25) +#define M33_CFSR_UFSR_DIVBYZERO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_UFSR_UNALIGNED +// Description : Sticky flag indicating whether an unaligned access error has +// occurred +#define M33_CFSR_UFSR_UNALIGNED_RESET _u(0x0) +#define M33_CFSR_UFSR_UNALIGNED_BITS _u(0x01000000) +#define M33_CFSR_UFSR_UNALIGNED_MSB _u(24) +#define M33_CFSR_UFSR_UNALIGNED_LSB _u(24) +#define M33_CFSR_UFSR_UNALIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_UFSR_STKOF +// Description : Sticky flag indicating whether a stack overflow error has +// occurred +#define M33_CFSR_UFSR_STKOF_RESET _u(0x0) +#define M33_CFSR_UFSR_STKOF_BITS _u(0x00100000) +#define M33_CFSR_UFSR_STKOF_MSB _u(20) +#define M33_CFSR_UFSR_STKOF_LSB _u(20) +#define M33_CFSR_UFSR_STKOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_UFSR_NOCP +// Description : Sticky flag indicating whether a coprocessor disabled or not +// present error has occurred +#define M33_CFSR_UFSR_NOCP_RESET _u(0x0) +#define M33_CFSR_UFSR_NOCP_BITS _u(0x00080000) +#define M33_CFSR_UFSR_NOCP_MSB _u(19) +#define M33_CFSR_UFSR_NOCP_LSB _u(19) +#define M33_CFSR_UFSR_NOCP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_UFSR_INVPC +// Description : Sticky flag indicating whether an integrity check error has +// occurred +#define M33_CFSR_UFSR_INVPC_RESET _u(0x0) +#define M33_CFSR_UFSR_INVPC_BITS _u(0x00040000) +#define M33_CFSR_UFSR_INVPC_MSB _u(18) +#define M33_CFSR_UFSR_INVPC_LSB _u(18) +#define M33_CFSR_UFSR_INVPC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_UFSR_INVSTATE +// Description : Sticky flag indicating whether an EPSR.T or EPSR.IT validity +// error has occurred +#define M33_CFSR_UFSR_INVSTATE_RESET _u(0x0) +#define M33_CFSR_UFSR_INVSTATE_BITS _u(0x00020000) +#define M33_CFSR_UFSR_INVSTATE_MSB _u(17) +#define M33_CFSR_UFSR_INVSTATE_LSB _u(17) +#define M33_CFSR_UFSR_INVSTATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_UFSR_UNDEFINSTR +// Description : Sticky flag indicating whether an undefined instruction error +// has occurred +#define M33_CFSR_UFSR_UNDEFINSTR_RESET _u(0x0) +#define M33_CFSR_UFSR_UNDEFINSTR_BITS _u(0x00010000) +#define M33_CFSR_UFSR_UNDEFINSTR_MSB _u(16) +#define M33_CFSR_UFSR_UNDEFINSTR_LSB _u(16) +#define M33_CFSR_UFSR_UNDEFINSTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_BFSR_BFARVALID +// Description : Indicates validity of the contents of the BFAR register +#define M33_CFSR_BFSR_BFARVALID_RESET _u(0x0) +#define M33_CFSR_BFSR_BFARVALID_BITS _u(0x00008000) +#define M33_CFSR_BFSR_BFARVALID_MSB _u(15) +#define M33_CFSR_BFSR_BFARVALID_LSB _u(15) +#define M33_CFSR_BFSR_BFARVALID_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_BFSR_LSPERR +// Description : Records whether a BusFault occurred during FP lazy state +// preservation +#define M33_CFSR_BFSR_LSPERR_RESET _u(0x0) +#define M33_CFSR_BFSR_LSPERR_BITS _u(0x00002000) +#define M33_CFSR_BFSR_LSPERR_MSB _u(13) +#define M33_CFSR_BFSR_LSPERR_LSB _u(13) +#define M33_CFSR_BFSR_LSPERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_BFSR_STKERR +// Description : Records whether a derived BusFault occurred during exception +// entry stacking +#define M33_CFSR_BFSR_STKERR_RESET _u(0x0) +#define M33_CFSR_BFSR_STKERR_BITS _u(0x00001000) +#define M33_CFSR_BFSR_STKERR_MSB _u(12) +#define M33_CFSR_BFSR_STKERR_LSB _u(12) +#define M33_CFSR_BFSR_STKERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_BFSR_UNSTKERR +// Description : Records whether a derived BusFault occurred during exception +// return unstacking +#define M33_CFSR_BFSR_UNSTKERR_RESET _u(0x0) +#define M33_CFSR_BFSR_UNSTKERR_BITS _u(0x00000800) +#define M33_CFSR_BFSR_UNSTKERR_MSB _u(11) +#define M33_CFSR_BFSR_UNSTKERR_LSB _u(11) +#define M33_CFSR_BFSR_UNSTKERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_BFSR_IMPRECISERR +// Description : Records whether an imprecise data access error has occurred +#define M33_CFSR_BFSR_IMPRECISERR_RESET _u(0x0) +#define M33_CFSR_BFSR_IMPRECISERR_BITS _u(0x00000400) +#define M33_CFSR_BFSR_IMPRECISERR_MSB _u(10) +#define M33_CFSR_BFSR_IMPRECISERR_LSB _u(10) +#define M33_CFSR_BFSR_IMPRECISERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_BFSR_PRECISERR +// Description : Records whether a precise data access error has occurred +#define M33_CFSR_BFSR_PRECISERR_RESET _u(0x0) +#define M33_CFSR_BFSR_PRECISERR_BITS _u(0x00000200) +#define M33_CFSR_BFSR_PRECISERR_MSB _u(9) +#define M33_CFSR_BFSR_PRECISERR_LSB _u(9) +#define M33_CFSR_BFSR_PRECISERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_BFSR_IBUSERR +// Description : Records whether a BusFault on an instruction prefetch has +// occurred +#define M33_CFSR_BFSR_IBUSERR_RESET _u(0x0) +#define M33_CFSR_BFSR_IBUSERR_BITS _u(0x00000100) +#define M33_CFSR_BFSR_IBUSERR_MSB _u(8) +#define M33_CFSR_BFSR_IBUSERR_LSB _u(8) +#define M33_CFSR_BFSR_IBUSERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CFSR_MMFSR +// Description : Provides information on MemManage exceptions +#define M33_CFSR_MMFSR_RESET _u(0x00) +#define M33_CFSR_MMFSR_BITS _u(0x000000ff) +#define M33_CFSR_MMFSR_MSB _u(7) +#define M33_CFSR_MMFSR_LSB _u(0) +#define M33_CFSR_MMFSR_ACCESS "RW" +// ============================================================================= +// Register : M33_HFSR +// Description : Shows the cause of any HardFaults +#define M33_HFSR_OFFSET _u(0x0000ed2c) +#define M33_HFSR_BITS _u(0xc0000002) +#define M33_HFSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_HFSR_DEBUGEVT +// Description : Indicates when a Debug event has occurred +#define M33_HFSR_DEBUGEVT_RESET _u(0x0) +#define M33_HFSR_DEBUGEVT_BITS _u(0x80000000) +#define M33_HFSR_DEBUGEVT_MSB _u(31) +#define M33_HFSR_DEBUGEVT_LSB _u(31) +#define M33_HFSR_DEBUGEVT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_HFSR_FORCED +// Description : Indicates that a fault with configurable priority has been +// escalated to a HardFault exception, because it could not be +// made active, because of priority, or because it was disabled +#define M33_HFSR_FORCED_RESET _u(0x0) +#define M33_HFSR_FORCED_BITS _u(0x40000000) +#define M33_HFSR_FORCED_MSB _u(30) +#define M33_HFSR_FORCED_LSB _u(30) +#define M33_HFSR_FORCED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_HFSR_VECTTBL +// Description : Indicates when a fault has occurred because of a vector table +// read error on exception processing +#define M33_HFSR_VECTTBL_RESET _u(0x0) +#define M33_HFSR_VECTTBL_BITS _u(0x00000002) +#define M33_HFSR_VECTTBL_MSB _u(1) +#define M33_HFSR_VECTTBL_LSB _u(1) +#define M33_HFSR_VECTTBL_ACCESS "RW" +// ============================================================================= +// Register : M33_DFSR +// Description : Shows which debug event occurred +#define M33_DFSR_OFFSET _u(0x0000ed30) +#define M33_DFSR_BITS _u(0x0000001f) +#define M33_DFSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DFSR_EXTERNAL +// Description : Sticky flag indicating whether an External debug request debug +// event has occurred +#define M33_DFSR_EXTERNAL_RESET _u(0x0) +#define M33_DFSR_EXTERNAL_BITS _u(0x00000010) +#define M33_DFSR_EXTERNAL_MSB _u(4) +#define M33_DFSR_EXTERNAL_LSB _u(4) +#define M33_DFSR_EXTERNAL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DFSR_VCATCH +// Description : Sticky flag indicating whether a Vector catch debug event has +// occurred +#define M33_DFSR_VCATCH_RESET _u(0x0) +#define M33_DFSR_VCATCH_BITS _u(0x00000008) +#define M33_DFSR_VCATCH_MSB _u(3) +#define M33_DFSR_VCATCH_LSB _u(3) +#define M33_DFSR_VCATCH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DFSR_DWTTRAP +// Description : Sticky flag indicating whether a Watchpoint debug event has +// occurred +#define M33_DFSR_DWTTRAP_RESET _u(0x0) +#define M33_DFSR_DWTTRAP_BITS _u(0x00000004) +#define M33_DFSR_DWTTRAP_MSB _u(2) +#define M33_DFSR_DWTTRAP_LSB _u(2) +#define M33_DFSR_DWTTRAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DFSR_BKPT +// Description : Sticky flag indicating whether a Breakpoint debug event has +// occurred +#define M33_DFSR_BKPT_RESET _u(0x0) +#define M33_DFSR_BKPT_BITS _u(0x00000002) +#define M33_DFSR_BKPT_MSB _u(1) +#define M33_DFSR_BKPT_LSB _u(1) +#define M33_DFSR_BKPT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DFSR_HALTED +// Description : Sticky flag indicating that a Halt request debug event or Step +// debug event has occurred +#define M33_DFSR_HALTED_RESET _u(0x0) +#define M33_DFSR_HALTED_BITS _u(0x00000001) +#define M33_DFSR_HALTED_MSB _u(0) +#define M33_DFSR_HALTED_LSB _u(0) +#define M33_DFSR_HALTED_ACCESS "RW" +// ============================================================================= +// Register : M33_MMFAR +// Description : Shows the address of the memory location that caused an MPU +// fault +#define M33_MMFAR_OFFSET _u(0x0000ed34) +#define M33_MMFAR_BITS _u(0xffffffff) +#define M33_MMFAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MMFAR_ADDRESS +// Description : This register is updated with the address of a location that +// produced a MemManage fault. The MMFSR shows the cause of the +// fault, and whether this field is valid. This field is valid +// only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN +#define M33_MMFAR_ADDRESS_RESET _u(0x00000000) +#define M33_MMFAR_ADDRESS_BITS _u(0xffffffff) +#define M33_MMFAR_ADDRESS_MSB _u(31) +#define M33_MMFAR_ADDRESS_LSB _u(0) +#define M33_MMFAR_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : M33_BFAR +// Description : Shows the address associated with a precise data access +// BusFault +#define M33_BFAR_OFFSET _u(0x0000ed38) +#define M33_BFAR_BITS _u(0xffffffff) +#define M33_BFAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_BFAR_ADDRESS +// Description : This register is updated with the address of a location that +// produced a BusFault. The BFSR shows the reason for the fault. +// This field is valid only when BFSR.BFARVALID is set, otherwise +// it is UNKNOWN +#define M33_BFAR_ADDRESS_RESET _u(0x00000000) +#define M33_BFAR_ADDRESS_BITS _u(0xffffffff) +#define M33_BFAR_ADDRESS_MSB _u(31) +#define M33_BFAR_ADDRESS_LSB _u(0) +#define M33_BFAR_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : M33_ID_PFR0 +// Description : Gives top-level information about the instruction set supported +// by the PE +#define M33_ID_PFR0_OFFSET _u(0x0000ed40) +#define M33_ID_PFR0_BITS _u(0x000000ff) +#define M33_ID_PFR0_RESET _u(0x00000030) +// ----------------------------------------------------------------------------- +// Field : M33_ID_PFR0_STATE1 +// Description : T32 instruction set support +#define M33_ID_PFR0_STATE1_RESET _u(0x3) +#define M33_ID_PFR0_STATE1_BITS _u(0x000000f0) +#define M33_ID_PFR0_STATE1_MSB _u(7) +#define M33_ID_PFR0_STATE1_LSB _u(4) +#define M33_ID_PFR0_STATE1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_PFR0_STATE0 +// Description : A32 instruction set support +#define M33_ID_PFR0_STATE0_RESET _u(0x0) +#define M33_ID_PFR0_STATE0_BITS _u(0x0000000f) +#define M33_ID_PFR0_STATE0_MSB _u(3) +#define M33_ID_PFR0_STATE0_LSB _u(0) +#define M33_ID_PFR0_STATE0_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_PFR1 +// Description : Gives information about the programmers' model and Extensions +// support +#define M33_ID_PFR1_OFFSET _u(0x0000ed44) +#define M33_ID_PFR1_BITS _u(0x00000ff0) +#define M33_ID_PFR1_RESET _u(0x00000520) +// ----------------------------------------------------------------------------- +// Field : M33_ID_PFR1_MPROGMOD +// Description : Identifies support for the M-Profile programmers' model support +#define M33_ID_PFR1_MPROGMOD_RESET _u(0x5) +#define M33_ID_PFR1_MPROGMOD_BITS _u(0x00000f00) +#define M33_ID_PFR1_MPROGMOD_MSB _u(11) +#define M33_ID_PFR1_MPROGMOD_LSB _u(8) +#define M33_ID_PFR1_MPROGMOD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_PFR1_SECURITY +// Description : Identifies whether the Security Extension is implemented +#define M33_ID_PFR1_SECURITY_RESET _u(0x2) +#define M33_ID_PFR1_SECURITY_BITS _u(0x000000f0) +#define M33_ID_PFR1_SECURITY_MSB _u(7) +#define M33_ID_PFR1_SECURITY_LSB _u(4) +#define M33_ID_PFR1_SECURITY_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_DFR0 +// Description : Provides top level information about the debug system +#define M33_ID_DFR0_OFFSET _u(0x0000ed48) +#define M33_ID_DFR0_BITS _u(0x00f00000) +#define M33_ID_DFR0_RESET _u(0x00200000) +// ----------------------------------------------------------------------------- +// Field : M33_ID_DFR0_MPROFDBG +// Description : Indicates the supported M-profile debug architecture +#define M33_ID_DFR0_MPROFDBG_RESET _u(0x2) +#define M33_ID_DFR0_MPROFDBG_BITS _u(0x00f00000) +#define M33_ID_DFR0_MPROFDBG_MSB _u(23) +#define M33_ID_DFR0_MPROFDBG_LSB _u(20) +#define M33_ID_DFR0_MPROFDBG_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_AFR0 +// Description : Provides information about the IMPLEMENTATION DEFINED features +// of the PE +#define M33_ID_AFR0_OFFSET _u(0x0000ed4c) +#define M33_ID_AFR0_BITS _u(0x0000ffff) +#define M33_ID_AFR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ID_AFR0_IMPDEF3 +// Description : IMPLEMENTATION DEFINED meaning +#define M33_ID_AFR0_IMPDEF3_RESET _u(0x0) +#define M33_ID_AFR0_IMPDEF3_BITS _u(0x0000f000) +#define M33_ID_AFR0_IMPDEF3_MSB _u(15) +#define M33_ID_AFR0_IMPDEF3_LSB _u(12) +#define M33_ID_AFR0_IMPDEF3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_AFR0_IMPDEF2 +// Description : IMPLEMENTATION DEFINED meaning +#define M33_ID_AFR0_IMPDEF2_RESET _u(0x0) +#define M33_ID_AFR0_IMPDEF2_BITS _u(0x00000f00) +#define M33_ID_AFR0_IMPDEF2_MSB _u(11) +#define M33_ID_AFR0_IMPDEF2_LSB _u(8) +#define M33_ID_AFR0_IMPDEF2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_AFR0_IMPDEF1 +// Description : IMPLEMENTATION DEFINED meaning +#define M33_ID_AFR0_IMPDEF1_RESET _u(0x0) +#define M33_ID_AFR0_IMPDEF1_BITS _u(0x000000f0) +#define M33_ID_AFR0_IMPDEF1_MSB _u(7) +#define M33_ID_AFR0_IMPDEF1_LSB _u(4) +#define M33_ID_AFR0_IMPDEF1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_AFR0_IMPDEF0 +// Description : IMPLEMENTATION DEFINED meaning +#define M33_ID_AFR0_IMPDEF0_RESET _u(0x0) +#define M33_ID_AFR0_IMPDEF0_BITS _u(0x0000000f) +#define M33_ID_AFR0_IMPDEF0_MSB _u(3) +#define M33_ID_AFR0_IMPDEF0_LSB _u(0) +#define M33_ID_AFR0_IMPDEF0_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_MMFR0 +// Description : Provides information about the implemented memory model and +// memory management support +#define M33_ID_MMFR0_OFFSET _u(0x0000ed50) +#define M33_ID_MMFR0_BITS _u(0x00fffff0) +#define M33_ID_MMFR0_RESET _u(0x00101f40) +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR0_AUXREG +// Description : Indicates support for Auxiliary Control Registers +#define M33_ID_MMFR0_AUXREG_RESET _u(0x1) +#define M33_ID_MMFR0_AUXREG_BITS _u(0x00f00000) +#define M33_ID_MMFR0_AUXREG_MSB _u(23) +#define M33_ID_MMFR0_AUXREG_LSB _u(20) +#define M33_ID_MMFR0_AUXREG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR0_TCM +// Description : Indicates support for tightly coupled memories (TCMs) +#define M33_ID_MMFR0_TCM_RESET _u(0x0) +#define M33_ID_MMFR0_TCM_BITS _u(0x000f0000) +#define M33_ID_MMFR0_TCM_MSB _u(19) +#define M33_ID_MMFR0_TCM_LSB _u(16) +#define M33_ID_MMFR0_TCM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR0_SHARELVL +// Description : Indicates the number of shareability levels implemented +#define M33_ID_MMFR0_SHARELVL_RESET _u(0x1) +#define M33_ID_MMFR0_SHARELVL_BITS _u(0x0000f000) +#define M33_ID_MMFR0_SHARELVL_MSB _u(15) +#define M33_ID_MMFR0_SHARELVL_LSB _u(12) +#define M33_ID_MMFR0_SHARELVL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR0_OUTERSHR +// Description : Indicates the outermost shareability domain implemented +#define M33_ID_MMFR0_OUTERSHR_RESET _u(0xf) +#define M33_ID_MMFR0_OUTERSHR_BITS _u(0x00000f00) +#define M33_ID_MMFR0_OUTERSHR_MSB _u(11) +#define M33_ID_MMFR0_OUTERSHR_LSB _u(8) +#define M33_ID_MMFR0_OUTERSHR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR0_PMSA +// Description : Indicates support for the protected memory system architecture +// (PMSA) +#define M33_ID_MMFR0_PMSA_RESET _u(0x4) +#define M33_ID_MMFR0_PMSA_BITS _u(0x000000f0) +#define M33_ID_MMFR0_PMSA_MSB _u(7) +#define M33_ID_MMFR0_PMSA_LSB _u(4) +#define M33_ID_MMFR0_PMSA_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_MMFR1 +// Description : Provides information about the implemented memory model and +// memory management support +#define M33_ID_MMFR1_OFFSET _u(0x0000ed54) +#define M33_ID_MMFR1_BITS _u(0x00000000) +#define M33_ID_MMFR1_RESET _u(0x00000000) +#define M33_ID_MMFR1_MSB _u(31) +#define M33_ID_MMFR1_LSB _u(0) +#define M33_ID_MMFR1_ACCESS "RW" +// ============================================================================= +// Register : M33_ID_MMFR2 +// Description : Provides information about the implemented memory model and +// memory management support +#define M33_ID_MMFR2_OFFSET _u(0x0000ed58) +#define M33_ID_MMFR2_BITS _u(0x0f000000) +#define M33_ID_MMFR2_RESET _u(0x01000000) +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR2_WFISTALL +// Description : Indicates the support for Wait For Interrupt (WFI) stalling +#define M33_ID_MMFR2_WFISTALL_RESET _u(0x1) +#define M33_ID_MMFR2_WFISTALL_BITS _u(0x0f000000) +#define M33_ID_MMFR2_WFISTALL_MSB _u(27) +#define M33_ID_MMFR2_WFISTALL_LSB _u(24) +#define M33_ID_MMFR2_WFISTALL_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_MMFR3 +// Description : Provides information about the implemented memory model and +// memory management support +#define M33_ID_MMFR3_OFFSET _u(0x0000ed5c) +#define M33_ID_MMFR3_BITS _u(0x00000fff) +#define M33_ID_MMFR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR3_BPMAINT +// Description : Indicates the supported branch predictor maintenance +#define M33_ID_MMFR3_BPMAINT_RESET _u(0x0) +#define M33_ID_MMFR3_BPMAINT_BITS _u(0x00000f00) +#define M33_ID_MMFR3_BPMAINT_MSB _u(11) +#define M33_ID_MMFR3_BPMAINT_LSB _u(8) +#define M33_ID_MMFR3_BPMAINT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR3_CMAINTSW +// Description : Indicates the supported cache maintenance operations by set/way +#define M33_ID_MMFR3_CMAINTSW_RESET _u(0x0) +#define M33_ID_MMFR3_CMAINTSW_BITS _u(0x000000f0) +#define M33_ID_MMFR3_CMAINTSW_MSB _u(7) +#define M33_ID_MMFR3_CMAINTSW_LSB _u(4) +#define M33_ID_MMFR3_CMAINTSW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_MMFR3_CMAINTVA +// Description : Indicates the supported cache maintenance operations by address +#define M33_ID_MMFR3_CMAINTVA_RESET _u(0x0) +#define M33_ID_MMFR3_CMAINTVA_BITS _u(0x0000000f) +#define M33_ID_MMFR3_CMAINTVA_MSB _u(3) +#define M33_ID_MMFR3_CMAINTVA_LSB _u(0) +#define M33_ID_MMFR3_CMAINTVA_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_ISAR0 +// Description : Provides information about the instruction set implemented by +// the PE +#define M33_ID_ISAR0_OFFSET _u(0x0000ed60) +#define M33_ID_ISAR0_BITS _u(0x0ffffff0) +#define M33_ID_ISAR0_RESET _u(0x08092300) +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR0_DIVIDE +// Description : Indicates the supported Divide instructions +#define M33_ID_ISAR0_DIVIDE_RESET _u(0x8) +#define M33_ID_ISAR0_DIVIDE_BITS _u(0x0f000000) +#define M33_ID_ISAR0_DIVIDE_MSB _u(27) +#define M33_ID_ISAR0_DIVIDE_LSB _u(24) +#define M33_ID_ISAR0_DIVIDE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR0_DEBUG +// Description : Indicates the implemented Debug instructions +#define M33_ID_ISAR0_DEBUG_RESET _u(0x0) +#define M33_ID_ISAR0_DEBUG_BITS _u(0x00f00000) +#define M33_ID_ISAR0_DEBUG_MSB _u(23) +#define M33_ID_ISAR0_DEBUG_LSB _u(20) +#define M33_ID_ISAR0_DEBUG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR0_COPROC +// Description : Indicates the supported Coprocessor instructions +#define M33_ID_ISAR0_COPROC_RESET _u(0x9) +#define M33_ID_ISAR0_COPROC_BITS _u(0x000f0000) +#define M33_ID_ISAR0_COPROC_MSB _u(19) +#define M33_ID_ISAR0_COPROC_LSB _u(16) +#define M33_ID_ISAR0_COPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR0_CMPBRANCH +// Description : Indicates the supported combined Compare and Branch +// instructions +#define M33_ID_ISAR0_CMPBRANCH_RESET _u(0x2) +#define M33_ID_ISAR0_CMPBRANCH_BITS _u(0x0000f000) +#define M33_ID_ISAR0_CMPBRANCH_MSB _u(15) +#define M33_ID_ISAR0_CMPBRANCH_LSB _u(12) +#define M33_ID_ISAR0_CMPBRANCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR0_BITFIELD +// Description : Indicates the supported bit field instructions +#define M33_ID_ISAR0_BITFIELD_RESET _u(0x3) +#define M33_ID_ISAR0_BITFIELD_BITS _u(0x00000f00) +#define M33_ID_ISAR0_BITFIELD_MSB _u(11) +#define M33_ID_ISAR0_BITFIELD_LSB _u(8) +#define M33_ID_ISAR0_BITFIELD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR0_BITCOUNT +// Description : Indicates the supported bit count instructions +#define M33_ID_ISAR0_BITCOUNT_RESET _u(0x0) +#define M33_ID_ISAR0_BITCOUNT_BITS _u(0x000000f0) +#define M33_ID_ISAR0_BITCOUNT_MSB _u(7) +#define M33_ID_ISAR0_BITCOUNT_LSB _u(4) +#define M33_ID_ISAR0_BITCOUNT_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_ISAR1 +// Description : Provides information about the instruction set implemented by +// the PE +#define M33_ID_ISAR1_OFFSET _u(0x0000ed64) +#define M33_ID_ISAR1_BITS _u(0x0ffff000) +#define M33_ID_ISAR1_RESET _u(0x05725000) +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR1_INTERWORK +// Description : Indicates the implemented Interworking instructions +#define M33_ID_ISAR1_INTERWORK_RESET _u(0x5) +#define M33_ID_ISAR1_INTERWORK_BITS _u(0x0f000000) +#define M33_ID_ISAR1_INTERWORK_MSB _u(27) +#define M33_ID_ISAR1_INTERWORK_LSB _u(24) +#define M33_ID_ISAR1_INTERWORK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR1_IMMEDIATE +// Description : Indicates the implemented for data-processing instructions with +// long immediates +#define M33_ID_ISAR1_IMMEDIATE_RESET _u(0x7) +#define M33_ID_ISAR1_IMMEDIATE_BITS _u(0x00f00000) +#define M33_ID_ISAR1_IMMEDIATE_MSB _u(23) +#define M33_ID_ISAR1_IMMEDIATE_LSB _u(20) +#define M33_ID_ISAR1_IMMEDIATE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR1_IFTHEN +// Description : Indicates the implemented If-Then instructions +#define M33_ID_ISAR1_IFTHEN_RESET _u(0x2) +#define M33_ID_ISAR1_IFTHEN_BITS _u(0x000f0000) +#define M33_ID_ISAR1_IFTHEN_MSB _u(19) +#define M33_ID_ISAR1_IFTHEN_LSB _u(16) +#define M33_ID_ISAR1_IFTHEN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR1_EXTEND +// Description : Indicates the implemented Extend instructions +#define M33_ID_ISAR1_EXTEND_RESET _u(0x5) +#define M33_ID_ISAR1_EXTEND_BITS _u(0x0000f000) +#define M33_ID_ISAR1_EXTEND_MSB _u(15) +#define M33_ID_ISAR1_EXTEND_LSB _u(12) +#define M33_ID_ISAR1_EXTEND_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_ISAR2 +// Description : Provides information about the instruction set implemented by +// the PE +#define M33_ID_ISAR2_OFFSET _u(0x0000ed68) +#define M33_ID_ISAR2_BITS _u(0xf0ffffff) +#define M33_ID_ISAR2_RESET _u(0x30173426) +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR2_REVERSAL +// Description : Indicates the implemented Reversal instructions +#define M33_ID_ISAR2_REVERSAL_RESET _u(0x3) +#define M33_ID_ISAR2_REVERSAL_BITS _u(0xf0000000) +#define M33_ID_ISAR2_REVERSAL_MSB _u(31) +#define M33_ID_ISAR2_REVERSAL_LSB _u(28) +#define M33_ID_ISAR2_REVERSAL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR2_MULTU +// Description : Indicates the implemented advanced unsigned Multiply +// instructions +#define M33_ID_ISAR2_MULTU_RESET _u(0x1) +#define M33_ID_ISAR2_MULTU_BITS _u(0x00f00000) +#define M33_ID_ISAR2_MULTU_MSB _u(23) +#define M33_ID_ISAR2_MULTU_LSB _u(20) +#define M33_ID_ISAR2_MULTU_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR2_MULTS +// Description : Indicates the implemented advanced signed Multiply instructions +#define M33_ID_ISAR2_MULTS_RESET _u(0x7) +#define M33_ID_ISAR2_MULTS_BITS _u(0x000f0000) +#define M33_ID_ISAR2_MULTS_MSB _u(19) +#define M33_ID_ISAR2_MULTS_LSB _u(16) +#define M33_ID_ISAR2_MULTS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR2_MULT +// Description : Indicates the implemented additional Multiply instructions +#define M33_ID_ISAR2_MULT_RESET _u(0x3) +#define M33_ID_ISAR2_MULT_BITS _u(0x0000f000) +#define M33_ID_ISAR2_MULT_MSB _u(15) +#define M33_ID_ISAR2_MULT_LSB _u(12) +#define M33_ID_ISAR2_MULT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR2_MULTIACCESSINT +// Description : Indicates the support for interruptible multi-access +// instructions +#define M33_ID_ISAR2_MULTIACCESSINT_RESET _u(0x4) +#define M33_ID_ISAR2_MULTIACCESSINT_BITS _u(0x00000f00) +#define M33_ID_ISAR2_MULTIACCESSINT_MSB _u(11) +#define M33_ID_ISAR2_MULTIACCESSINT_LSB _u(8) +#define M33_ID_ISAR2_MULTIACCESSINT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR2_MEMHINT +// Description : Indicates the implemented Memory Hint instructions +#define M33_ID_ISAR2_MEMHINT_RESET _u(0x2) +#define M33_ID_ISAR2_MEMHINT_BITS _u(0x000000f0) +#define M33_ID_ISAR2_MEMHINT_MSB _u(7) +#define M33_ID_ISAR2_MEMHINT_LSB _u(4) +#define M33_ID_ISAR2_MEMHINT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR2_LOADSTORE +// Description : Indicates the implemented additional load/store instructions +#define M33_ID_ISAR2_LOADSTORE_RESET _u(0x6) +#define M33_ID_ISAR2_LOADSTORE_BITS _u(0x0000000f) +#define M33_ID_ISAR2_LOADSTORE_MSB _u(3) +#define M33_ID_ISAR2_LOADSTORE_LSB _u(0) +#define M33_ID_ISAR2_LOADSTORE_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_ISAR3 +// Description : Provides information about the instruction set implemented by +// the PE +#define M33_ID_ISAR3_OFFSET _u(0x0000ed6c) +#define M33_ID_ISAR3_BITS _u(0x0fffffff) +#define M33_ID_ISAR3_RESET _u(0x07895729) +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR3_TRUENOP +// Description : Indicates the implemented true NOP instructions +#define M33_ID_ISAR3_TRUENOP_RESET _u(0x7) +#define M33_ID_ISAR3_TRUENOP_BITS _u(0x0f000000) +#define M33_ID_ISAR3_TRUENOP_MSB _u(27) +#define M33_ID_ISAR3_TRUENOP_LSB _u(24) +#define M33_ID_ISAR3_TRUENOP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR3_T32COPY +// Description : Indicates the support for T32 non flag-setting MOV instructions +#define M33_ID_ISAR3_T32COPY_RESET _u(0x8) +#define M33_ID_ISAR3_T32COPY_BITS _u(0x00f00000) +#define M33_ID_ISAR3_T32COPY_MSB _u(23) +#define M33_ID_ISAR3_T32COPY_LSB _u(20) +#define M33_ID_ISAR3_T32COPY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR3_TABBRANCH +// Description : Indicates the implemented Table Branch instructions +#define M33_ID_ISAR3_TABBRANCH_RESET _u(0x9) +#define M33_ID_ISAR3_TABBRANCH_BITS _u(0x000f0000) +#define M33_ID_ISAR3_TABBRANCH_MSB _u(19) +#define M33_ID_ISAR3_TABBRANCH_LSB _u(16) +#define M33_ID_ISAR3_TABBRANCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR3_SYNCHPRIM +// Description : Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate +// the implemented Synchronization Primitive instructions +#define M33_ID_ISAR3_SYNCHPRIM_RESET _u(0x5) +#define M33_ID_ISAR3_SYNCHPRIM_BITS _u(0x0000f000) +#define M33_ID_ISAR3_SYNCHPRIM_MSB _u(15) +#define M33_ID_ISAR3_SYNCHPRIM_LSB _u(12) +#define M33_ID_ISAR3_SYNCHPRIM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR3_SVC +// Description : Indicates the implemented SVC instructions +#define M33_ID_ISAR3_SVC_RESET _u(0x7) +#define M33_ID_ISAR3_SVC_BITS _u(0x00000f00) +#define M33_ID_ISAR3_SVC_MSB _u(11) +#define M33_ID_ISAR3_SVC_LSB _u(8) +#define M33_ID_ISAR3_SVC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR3_SIMD +// Description : Indicates the implemented SIMD instructions +#define M33_ID_ISAR3_SIMD_RESET _u(0x2) +#define M33_ID_ISAR3_SIMD_BITS _u(0x000000f0) +#define M33_ID_ISAR3_SIMD_MSB _u(7) +#define M33_ID_ISAR3_SIMD_LSB _u(4) +#define M33_ID_ISAR3_SIMD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR3_SATURATE +// Description : Indicates the implemented saturating instructions +#define M33_ID_ISAR3_SATURATE_RESET _u(0x9) +#define M33_ID_ISAR3_SATURATE_BITS _u(0x0000000f) +#define M33_ID_ISAR3_SATURATE_MSB _u(3) +#define M33_ID_ISAR3_SATURATE_LSB _u(0) +#define M33_ID_ISAR3_SATURATE_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_ISAR4 +// Description : Provides information about the instruction set implemented by +// the PE +#define M33_ID_ISAR4_OFFSET _u(0x0000ed70) +#define M33_ID_ISAR4_BITS _u(0x0fff0fff) +#define M33_ID_ISAR4_RESET _u(0x01310132) +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR4_PSR_M +// Description : Indicates the implemented M profile instructions to modify the +// PSRs +#define M33_ID_ISAR4_PSR_M_RESET _u(0x1) +#define M33_ID_ISAR4_PSR_M_BITS _u(0x0f000000) +#define M33_ID_ISAR4_PSR_M_MSB _u(27) +#define M33_ID_ISAR4_PSR_M_LSB _u(24) +#define M33_ID_ISAR4_PSR_M_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR4_SYNCPRIM_FRAC +// Description : Used in conjunction with ID_ISAR3.SynchPrim to indicate the +// implemented Synchronization Primitive instructions +#define M33_ID_ISAR4_SYNCPRIM_FRAC_RESET _u(0x3) +#define M33_ID_ISAR4_SYNCPRIM_FRAC_BITS _u(0x00f00000) +#define M33_ID_ISAR4_SYNCPRIM_FRAC_MSB _u(23) +#define M33_ID_ISAR4_SYNCPRIM_FRAC_LSB _u(20) +#define M33_ID_ISAR4_SYNCPRIM_FRAC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR4_BARRIER +// Description : Indicates the implemented Barrier instructions +#define M33_ID_ISAR4_BARRIER_RESET _u(0x1) +#define M33_ID_ISAR4_BARRIER_BITS _u(0x000f0000) +#define M33_ID_ISAR4_BARRIER_MSB _u(19) +#define M33_ID_ISAR4_BARRIER_LSB _u(16) +#define M33_ID_ISAR4_BARRIER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR4_WRITEBACK +// Description : Indicates the support for writeback addressing modes +#define M33_ID_ISAR4_WRITEBACK_RESET _u(0x1) +#define M33_ID_ISAR4_WRITEBACK_BITS _u(0x00000f00) +#define M33_ID_ISAR4_WRITEBACK_MSB _u(11) +#define M33_ID_ISAR4_WRITEBACK_LSB _u(8) +#define M33_ID_ISAR4_WRITEBACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR4_WITHSHIFTS +// Description : Indicates the support for writeback addressing modes +#define M33_ID_ISAR4_WITHSHIFTS_RESET _u(0x3) +#define M33_ID_ISAR4_WITHSHIFTS_BITS _u(0x000000f0) +#define M33_ID_ISAR4_WITHSHIFTS_MSB _u(7) +#define M33_ID_ISAR4_WITHSHIFTS_LSB _u(4) +#define M33_ID_ISAR4_WITHSHIFTS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_ID_ISAR4_UNPRIV +// Description : Indicates the implemented unprivileged instructions +#define M33_ID_ISAR4_UNPRIV_RESET _u(0x2) +#define M33_ID_ISAR4_UNPRIV_BITS _u(0x0000000f) +#define M33_ID_ISAR4_UNPRIV_MSB _u(3) +#define M33_ID_ISAR4_UNPRIV_LSB _u(0) +#define M33_ID_ISAR4_UNPRIV_ACCESS "RO" +// ============================================================================= +// Register : M33_ID_ISAR5 +// Description : Provides information about the instruction set implemented by +// the PE +#define M33_ID_ISAR5_OFFSET _u(0x0000ed74) +#define M33_ID_ISAR5_BITS _u(0x00000000) +#define M33_ID_ISAR5_RESET _u(0x00000000) +#define M33_ID_ISAR5_MSB _u(31) +#define M33_ID_ISAR5_LSB _u(0) +#define M33_ID_ISAR5_ACCESS "RW" +// ============================================================================= +// Register : M33_CTR +// Description : Provides information about the architecture of the caches. CTR +// is RES0 if CLIDR is zero. +#define M33_CTR_OFFSET _u(0x0000ed7c) +#define M33_CTR_BITS _u(0x8fffc00f) +#define M33_CTR_RESET _u(0x8000c000) +// ----------------------------------------------------------------------------- +// Field : M33_CTR_RES1 +// Description : Reserved, RES1 +#define M33_CTR_RES1_RESET _u(0x1) +#define M33_CTR_RES1_BITS _u(0x80000000) +#define M33_CTR_RES1_MSB _u(31) +#define M33_CTR_RES1_LSB _u(31) +#define M33_CTR_RES1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CTR_CWG +// Description : Log2 of the number of words of the maximum size of memory that +// can be overwritten as a result of the eviction of a cache entry +// that has had a memory location in it modified +#define M33_CTR_CWG_RESET _u(0x0) +#define M33_CTR_CWG_BITS _u(0x0f000000) +#define M33_CTR_CWG_MSB _u(27) +#define M33_CTR_CWG_LSB _u(24) +#define M33_CTR_CWG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CTR_ERG +// Description : Log2 of the number of words of the maximum size of the +// reservation granule that has been implemented for the Load- +// Exclusive and Store-Exclusive instructions +#define M33_CTR_ERG_RESET _u(0x0) +#define M33_CTR_ERG_BITS _u(0x00f00000) +#define M33_CTR_ERG_MSB _u(23) +#define M33_CTR_ERG_LSB _u(20) +#define M33_CTR_ERG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CTR_DMINLINE +// Description : Log2 of the number of words in the smallest cache line of all +// the data caches and unified caches that are controlled by the +// PE +#define M33_CTR_DMINLINE_RESET _u(0x0) +#define M33_CTR_DMINLINE_BITS _u(0x000f0000) +#define M33_CTR_DMINLINE_MSB _u(19) +#define M33_CTR_DMINLINE_LSB _u(16) +#define M33_CTR_DMINLINE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CTR_RES1_1 +// Description : Reserved, RES1 +#define M33_CTR_RES1_1_RESET _u(0x3) +#define M33_CTR_RES1_1_BITS _u(0x0000c000) +#define M33_CTR_RES1_1_MSB _u(15) +#define M33_CTR_RES1_1_LSB _u(14) +#define M33_CTR_RES1_1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CTR_IMINLINE +// Description : Log2 of the number of words in the smallest cache line of all +// the instruction caches that are controlled by the PE +#define M33_CTR_IMINLINE_RESET _u(0x0) +#define M33_CTR_IMINLINE_BITS _u(0x0000000f) +#define M33_CTR_IMINLINE_MSB _u(3) +#define M33_CTR_IMINLINE_LSB _u(0) +#define M33_CTR_IMINLINE_ACCESS "RO" +// ============================================================================= +// Register : M33_CPACR +// Description : Specifies the access privileges for coprocessors and the FP +// Extension +#define M33_CPACR_OFFSET _u(0x0000ed88) +#define M33_CPACR_BITS _u(0x00f0ffff) +#define M33_CPACR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP11 +// Description : The value in this field is ignored. If the implementation does +// not include the FP Extension, this field is RAZ/WI. If the +// value of this bit is not programmed to the same value as the +// CP10 field, then the value is UNKNOWN +#define M33_CPACR_CP11_RESET _u(0x0) +#define M33_CPACR_CP11_BITS _u(0x00c00000) +#define M33_CPACR_CP11_MSB _u(23) +#define M33_CPACR_CP11_LSB _u(22) +#define M33_CPACR_CP11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP10 +// Description : Defines the access rights for the floating-point functionality +#define M33_CPACR_CP10_RESET _u(0x0) +#define M33_CPACR_CP10_BITS _u(0x00300000) +#define M33_CPACR_CP10_MSB _u(21) +#define M33_CPACR_CP10_LSB _u(20) +#define M33_CPACR_CP10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP7 +// Description : Controls access privileges for coprocessor 7 +#define M33_CPACR_CP7_RESET _u(0x0) +#define M33_CPACR_CP7_BITS _u(0x0000c000) +#define M33_CPACR_CP7_MSB _u(15) +#define M33_CPACR_CP7_LSB _u(14) +#define M33_CPACR_CP7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP6 +// Description : Controls access privileges for coprocessor 6 +#define M33_CPACR_CP6_RESET _u(0x0) +#define M33_CPACR_CP6_BITS _u(0x00003000) +#define M33_CPACR_CP6_MSB _u(13) +#define M33_CPACR_CP6_LSB _u(12) +#define M33_CPACR_CP6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP5 +// Description : Controls access privileges for coprocessor 5 +#define M33_CPACR_CP5_RESET _u(0x0) +#define M33_CPACR_CP5_BITS _u(0x00000c00) +#define M33_CPACR_CP5_MSB _u(11) +#define M33_CPACR_CP5_LSB _u(10) +#define M33_CPACR_CP5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP4 +// Description : Controls access privileges for coprocessor 4 +#define M33_CPACR_CP4_RESET _u(0x0) +#define M33_CPACR_CP4_BITS _u(0x00000300) +#define M33_CPACR_CP4_MSB _u(9) +#define M33_CPACR_CP4_LSB _u(8) +#define M33_CPACR_CP4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP3 +// Description : Controls access privileges for coprocessor 3 +#define M33_CPACR_CP3_RESET _u(0x0) +#define M33_CPACR_CP3_BITS _u(0x000000c0) +#define M33_CPACR_CP3_MSB _u(7) +#define M33_CPACR_CP3_LSB _u(6) +#define M33_CPACR_CP3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP2 +// Description : Controls access privileges for coprocessor 2 +#define M33_CPACR_CP2_RESET _u(0x0) +#define M33_CPACR_CP2_BITS _u(0x00000030) +#define M33_CPACR_CP2_MSB _u(5) +#define M33_CPACR_CP2_LSB _u(4) +#define M33_CPACR_CP2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP1 +// Description : Controls access privileges for coprocessor 1 +#define M33_CPACR_CP1_RESET _u(0x0) +#define M33_CPACR_CP1_BITS _u(0x0000000c) +#define M33_CPACR_CP1_MSB _u(3) +#define M33_CPACR_CP1_LSB _u(2) +#define M33_CPACR_CP1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CPACR_CP0 +// Description : Controls access privileges for coprocessor 0 +#define M33_CPACR_CP0_RESET _u(0x0) +#define M33_CPACR_CP0_BITS _u(0x00000003) +#define M33_CPACR_CP0_MSB _u(1) +#define M33_CPACR_CP0_LSB _u(0) +#define M33_CPACR_CP0_ACCESS "RW" +// ============================================================================= +// Register : M33_NSACR +// Description : Defines the Non-secure access permissions for both the FP +// Extension and coprocessors CP0 to CP7 +#define M33_NSACR_OFFSET _u(0x0000ed8c) +#define M33_NSACR_BITS _u(0x00000cff) +#define M33_NSACR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP11 +// Description : Enables Non-secure access to the Floating-point Extension +#define M33_NSACR_CP11_RESET _u(0x0) +#define M33_NSACR_CP11_BITS _u(0x00000800) +#define M33_NSACR_CP11_MSB _u(11) +#define M33_NSACR_CP11_LSB _u(11) +#define M33_NSACR_CP11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP10 +// Description : Enables Non-secure access to the Floating-point Extension +#define M33_NSACR_CP10_RESET _u(0x0) +#define M33_NSACR_CP10_BITS _u(0x00000400) +#define M33_NSACR_CP10_MSB _u(10) +#define M33_NSACR_CP10_LSB _u(10) +#define M33_NSACR_CP10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP7 +// Description : Enables Non-secure access to coprocessor CP7 +#define M33_NSACR_CP7_RESET _u(0x0) +#define M33_NSACR_CP7_BITS _u(0x00000080) +#define M33_NSACR_CP7_MSB _u(7) +#define M33_NSACR_CP7_LSB _u(7) +#define M33_NSACR_CP7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP6 +// Description : Enables Non-secure access to coprocessor CP6 +#define M33_NSACR_CP6_RESET _u(0x0) +#define M33_NSACR_CP6_BITS _u(0x00000040) +#define M33_NSACR_CP6_MSB _u(6) +#define M33_NSACR_CP6_LSB _u(6) +#define M33_NSACR_CP6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP5 +// Description : Enables Non-secure access to coprocessor CP5 +#define M33_NSACR_CP5_RESET _u(0x0) +#define M33_NSACR_CP5_BITS _u(0x00000020) +#define M33_NSACR_CP5_MSB _u(5) +#define M33_NSACR_CP5_LSB _u(5) +#define M33_NSACR_CP5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP4 +// Description : Enables Non-secure access to coprocessor CP4 +#define M33_NSACR_CP4_RESET _u(0x0) +#define M33_NSACR_CP4_BITS _u(0x00000010) +#define M33_NSACR_CP4_MSB _u(4) +#define M33_NSACR_CP4_LSB _u(4) +#define M33_NSACR_CP4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP3 +// Description : Enables Non-secure access to coprocessor CP3 +#define M33_NSACR_CP3_RESET _u(0x0) +#define M33_NSACR_CP3_BITS _u(0x00000008) +#define M33_NSACR_CP3_MSB _u(3) +#define M33_NSACR_CP3_LSB _u(3) +#define M33_NSACR_CP3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP2 +// Description : Enables Non-secure access to coprocessor CP2 +#define M33_NSACR_CP2_RESET _u(0x0) +#define M33_NSACR_CP2_BITS _u(0x00000004) +#define M33_NSACR_CP2_MSB _u(2) +#define M33_NSACR_CP2_LSB _u(2) +#define M33_NSACR_CP2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP1 +// Description : Enables Non-secure access to coprocessor CP1 +#define M33_NSACR_CP1_RESET _u(0x0) +#define M33_NSACR_CP1_BITS _u(0x00000002) +#define M33_NSACR_CP1_MSB _u(1) +#define M33_NSACR_CP1_LSB _u(1) +#define M33_NSACR_CP1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_NSACR_CP0 +// Description : Enables Non-secure access to coprocessor CP0 +#define M33_NSACR_CP0_RESET _u(0x0) +#define M33_NSACR_CP0_BITS _u(0x00000001) +#define M33_NSACR_CP0_MSB _u(0) +#define M33_NSACR_CP0_LSB _u(0) +#define M33_NSACR_CP0_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_TYPE +// Description : The MPU Type Register indicates how many regions the MPU `FTSSS +// supports +#define M33_MPU_TYPE_OFFSET _u(0x0000ed90) +#define M33_MPU_TYPE_BITS _u(0x0000ff01) +#define M33_MPU_TYPE_RESET _u(0x00000800) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_TYPE_DREGION +// Description : Number of regions supported by the MPU +#define M33_MPU_TYPE_DREGION_RESET _u(0x08) +#define M33_MPU_TYPE_DREGION_BITS _u(0x0000ff00) +#define M33_MPU_TYPE_DREGION_MSB _u(15) +#define M33_MPU_TYPE_DREGION_LSB _u(8) +#define M33_MPU_TYPE_DREGION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_TYPE_SEPARATE +// Description : Indicates support for separate instructions and data address +// regions +#define M33_MPU_TYPE_SEPARATE_RESET _u(0x0) +#define M33_MPU_TYPE_SEPARATE_BITS _u(0x00000001) +#define M33_MPU_TYPE_SEPARATE_MSB _u(0) +#define M33_MPU_TYPE_SEPARATE_LSB _u(0) +#define M33_MPU_TYPE_SEPARATE_ACCESS "RO" +// ============================================================================= +// Register : M33_MPU_CTRL +// Description : Enables the MPU and, when the MPU is enabled, controls whether +// the default memory map is enabled as a background region for +// privileged accesses, and whether the MPU is enabled for +// HardFaults, NMIs, and exception handlers when FAULTMASK is set +// to 1 +#define M33_MPU_CTRL_OFFSET _u(0x0000ed94) +#define M33_MPU_CTRL_BITS _u(0x00000007) +#define M33_MPU_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_CTRL_PRIVDEFENA +// Description : Controls whether the default memory map is enabled for +// privileged software +#define M33_MPU_CTRL_PRIVDEFENA_RESET _u(0x0) +#define M33_MPU_CTRL_PRIVDEFENA_BITS _u(0x00000004) +#define M33_MPU_CTRL_PRIVDEFENA_MSB _u(2) +#define M33_MPU_CTRL_PRIVDEFENA_LSB _u(2) +#define M33_MPU_CTRL_PRIVDEFENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_CTRL_HFNMIENA +// Description : Controls whether handlers executing with priority less than 0 +// access memory with the MPU enabled or disabled. This applies to +// HardFaults, NMIs, and exception handlers when FAULTMASK is set +// to 1 +#define M33_MPU_CTRL_HFNMIENA_RESET _u(0x0) +#define M33_MPU_CTRL_HFNMIENA_BITS _u(0x00000002) +#define M33_MPU_CTRL_HFNMIENA_MSB _u(1) +#define M33_MPU_CTRL_HFNMIENA_LSB _u(1) +#define M33_MPU_CTRL_HFNMIENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_CTRL_ENABLE +// Description : Enables the MPU +#define M33_MPU_CTRL_ENABLE_RESET _u(0x0) +#define M33_MPU_CTRL_ENABLE_BITS _u(0x00000001) +#define M33_MPU_CTRL_ENABLE_MSB _u(0) +#define M33_MPU_CTRL_ENABLE_LSB _u(0) +#define M33_MPU_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RNR +// Description : Selects the region currently accessed by MPU_RBAR and MPU_RLAR +#define M33_MPU_RNR_OFFSET _u(0x0000ed98) +#define M33_MPU_RNR_BITS _u(0x00000007) +#define M33_MPU_RNR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RNR_REGION +// Description : Indicates the memory region accessed by MPU_RBAR and MPU_RLAR +#define M33_MPU_RNR_REGION_RESET _u(0x0) +#define M33_MPU_RNR_REGION_BITS _u(0x00000007) +#define M33_MPU_RNR_REGION_MSB _u(2) +#define M33_MPU_RNR_REGION_LSB _u(0) +#define M33_MPU_RNR_REGION_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RBAR +// Description : Provides indirect read and write access to the base address of +// the currently selected MPU region `FTSSS +#define M33_MPU_RBAR_OFFSET _u(0x0000ed9c) +#define M33_MPU_RBAR_BITS _u(0xffffffff) +#define M33_MPU_RBAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_BASE +// Description : Contains bits [31:5] of the lower inclusive limit of the +// selected MPU memory region. This value is zero extended to +// provide the base address to be checked against +#define M33_MPU_RBAR_BASE_RESET _u(0x0000000) +#define M33_MPU_RBAR_BASE_BITS _u(0xffffffe0) +#define M33_MPU_RBAR_BASE_MSB _u(31) +#define M33_MPU_RBAR_BASE_LSB _u(5) +#define M33_MPU_RBAR_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_SH +// Description : Defines the Shareability domain of this region for Normal +// memory +#define M33_MPU_RBAR_SH_RESET _u(0x0) +#define M33_MPU_RBAR_SH_BITS _u(0x00000018) +#define M33_MPU_RBAR_SH_MSB _u(4) +#define M33_MPU_RBAR_SH_LSB _u(3) +#define M33_MPU_RBAR_SH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_AP +// Description : Defines the access permissions for this region +#define M33_MPU_RBAR_AP_RESET _u(0x0) +#define M33_MPU_RBAR_AP_BITS _u(0x00000006) +#define M33_MPU_RBAR_AP_MSB _u(2) +#define M33_MPU_RBAR_AP_LSB _u(1) +#define M33_MPU_RBAR_AP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_XN +// Description : Defines whether code can be executed from this region +#define M33_MPU_RBAR_XN_RESET _u(0x0) +#define M33_MPU_RBAR_XN_BITS _u(0x00000001) +#define M33_MPU_RBAR_XN_MSB _u(0) +#define M33_MPU_RBAR_XN_LSB _u(0) +#define M33_MPU_RBAR_XN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RLAR +// Description : Provides indirect read and write access to the limit address of +// the currently selected MPU region `FTSSS +#define M33_MPU_RLAR_OFFSET _u(0x0000eda0) +#define M33_MPU_RLAR_BITS _u(0xffffffef) +#define M33_MPU_RLAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_LIMIT +// Description : Contains bits [31:5] of the upper inclusive limit of the +// selected MPU memory region. This value is postfixed with 0x1F +// to provide the limit address to be checked against +#define M33_MPU_RLAR_LIMIT_RESET _u(0x0000000) +#define M33_MPU_RLAR_LIMIT_BITS _u(0xffffffe0) +#define M33_MPU_RLAR_LIMIT_MSB _u(31) +#define M33_MPU_RLAR_LIMIT_LSB _u(5) +#define M33_MPU_RLAR_LIMIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_ATTRINDX +// Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 +// fields +#define M33_MPU_RLAR_ATTRINDX_RESET _u(0x0) +#define M33_MPU_RLAR_ATTRINDX_BITS _u(0x0000000e) +#define M33_MPU_RLAR_ATTRINDX_MSB _u(3) +#define M33_MPU_RLAR_ATTRINDX_LSB _u(1) +#define M33_MPU_RLAR_ATTRINDX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_EN +// Description : Region enable +#define M33_MPU_RLAR_EN_RESET _u(0x0) +#define M33_MPU_RLAR_EN_BITS _u(0x00000001) +#define M33_MPU_RLAR_EN_MSB _u(0) +#define M33_MPU_RLAR_EN_LSB _u(0) +#define M33_MPU_RLAR_EN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RBAR_A1 +// Description : Provides indirect read and write access to the base address of +// the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS +#define M33_MPU_RBAR_A1_OFFSET _u(0x0000eda4) +#define M33_MPU_RBAR_A1_BITS _u(0xffffffff) +#define M33_MPU_RBAR_A1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A1_BASE +// Description : Contains bits [31:5] of the lower inclusive limit of the +// selected MPU memory region. This value is zero extended to +// provide the base address to be checked against +#define M33_MPU_RBAR_A1_BASE_RESET _u(0x0000000) +#define M33_MPU_RBAR_A1_BASE_BITS _u(0xffffffe0) +#define M33_MPU_RBAR_A1_BASE_MSB _u(31) +#define M33_MPU_RBAR_A1_BASE_LSB _u(5) +#define M33_MPU_RBAR_A1_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A1_SH +// Description : Defines the Shareability domain of this region for Normal +// memory +#define M33_MPU_RBAR_A1_SH_RESET _u(0x0) +#define M33_MPU_RBAR_A1_SH_BITS _u(0x00000018) +#define M33_MPU_RBAR_A1_SH_MSB _u(4) +#define M33_MPU_RBAR_A1_SH_LSB _u(3) +#define M33_MPU_RBAR_A1_SH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A1_AP +// Description : Defines the access permissions for this region +#define M33_MPU_RBAR_A1_AP_RESET _u(0x0) +#define M33_MPU_RBAR_A1_AP_BITS _u(0x00000006) +#define M33_MPU_RBAR_A1_AP_MSB _u(2) +#define M33_MPU_RBAR_A1_AP_LSB _u(1) +#define M33_MPU_RBAR_A1_AP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A1_XN +// Description : Defines whether code can be executed from this region +#define M33_MPU_RBAR_A1_XN_RESET _u(0x0) +#define M33_MPU_RBAR_A1_XN_BITS _u(0x00000001) +#define M33_MPU_RBAR_A1_XN_MSB _u(0) +#define M33_MPU_RBAR_A1_XN_LSB _u(0) +#define M33_MPU_RBAR_A1_XN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RLAR_A1 +// Description : Provides indirect read and write access to the limit address of +// the currently selected MPU region selected by +// MPU_RNR[7:2]:(1[1:0]) `FTSSS +#define M33_MPU_RLAR_A1_OFFSET _u(0x0000eda8) +#define M33_MPU_RLAR_A1_BITS _u(0xffffffef) +#define M33_MPU_RLAR_A1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A1_LIMIT +// Description : Contains bits [31:5] of the upper inclusive limit of the +// selected MPU memory region. This value is postfixed with 0x1F +// to provide the limit address to be checked against +#define M33_MPU_RLAR_A1_LIMIT_RESET _u(0x0000000) +#define M33_MPU_RLAR_A1_LIMIT_BITS _u(0xffffffe0) +#define M33_MPU_RLAR_A1_LIMIT_MSB _u(31) +#define M33_MPU_RLAR_A1_LIMIT_LSB _u(5) +#define M33_MPU_RLAR_A1_LIMIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A1_ATTRINDX +// Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 +// fields +#define M33_MPU_RLAR_A1_ATTRINDX_RESET _u(0x0) +#define M33_MPU_RLAR_A1_ATTRINDX_BITS _u(0x0000000e) +#define M33_MPU_RLAR_A1_ATTRINDX_MSB _u(3) +#define M33_MPU_RLAR_A1_ATTRINDX_LSB _u(1) +#define M33_MPU_RLAR_A1_ATTRINDX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A1_EN +// Description : Region enable +#define M33_MPU_RLAR_A1_EN_RESET _u(0x0) +#define M33_MPU_RLAR_A1_EN_BITS _u(0x00000001) +#define M33_MPU_RLAR_A1_EN_MSB _u(0) +#define M33_MPU_RLAR_A1_EN_LSB _u(0) +#define M33_MPU_RLAR_A1_EN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RBAR_A2 +// Description : Provides indirect read and write access to the base address of +// the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS +#define M33_MPU_RBAR_A2_OFFSET _u(0x0000edac) +#define M33_MPU_RBAR_A2_BITS _u(0xffffffff) +#define M33_MPU_RBAR_A2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A2_BASE +// Description : Contains bits [31:5] of the lower inclusive limit of the +// selected MPU memory region. This value is zero extended to +// provide the base address to be checked against +#define M33_MPU_RBAR_A2_BASE_RESET _u(0x0000000) +#define M33_MPU_RBAR_A2_BASE_BITS _u(0xffffffe0) +#define M33_MPU_RBAR_A2_BASE_MSB _u(31) +#define M33_MPU_RBAR_A2_BASE_LSB _u(5) +#define M33_MPU_RBAR_A2_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A2_SH +// Description : Defines the Shareability domain of this region for Normal +// memory +#define M33_MPU_RBAR_A2_SH_RESET _u(0x0) +#define M33_MPU_RBAR_A2_SH_BITS _u(0x00000018) +#define M33_MPU_RBAR_A2_SH_MSB _u(4) +#define M33_MPU_RBAR_A2_SH_LSB _u(3) +#define M33_MPU_RBAR_A2_SH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A2_AP +// Description : Defines the access permissions for this region +#define M33_MPU_RBAR_A2_AP_RESET _u(0x0) +#define M33_MPU_RBAR_A2_AP_BITS _u(0x00000006) +#define M33_MPU_RBAR_A2_AP_MSB _u(2) +#define M33_MPU_RBAR_A2_AP_LSB _u(1) +#define M33_MPU_RBAR_A2_AP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A2_XN +// Description : Defines whether code can be executed from this region +#define M33_MPU_RBAR_A2_XN_RESET _u(0x0) +#define M33_MPU_RBAR_A2_XN_BITS _u(0x00000001) +#define M33_MPU_RBAR_A2_XN_MSB _u(0) +#define M33_MPU_RBAR_A2_XN_LSB _u(0) +#define M33_MPU_RBAR_A2_XN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RLAR_A2 +// Description : Provides indirect read and write access to the limit address of +// the currently selected MPU region selected by +// MPU_RNR[7:2]:(2[1:0]) `FTSSS +#define M33_MPU_RLAR_A2_OFFSET _u(0x0000edb0) +#define M33_MPU_RLAR_A2_BITS _u(0xffffffef) +#define M33_MPU_RLAR_A2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A2_LIMIT +// Description : Contains bits [31:5] of the upper inclusive limit of the +// selected MPU memory region. This value is postfixed with 0x1F +// to provide the limit address to be checked against +#define M33_MPU_RLAR_A2_LIMIT_RESET _u(0x0000000) +#define M33_MPU_RLAR_A2_LIMIT_BITS _u(0xffffffe0) +#define M33_MPU_RLAR_A2_LIMIT_MSB _u(31) +#define M33_MPU_RLAR_A2_LIMIT_LSB _u(5) +#define M33_MPU_RLAR_A2_LIMIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A2_ATTRINDX +// Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 +// fields +#define M33_MPU_RLAR_A2_ATTRINDX_RESET _u(0x0) +#define M33_MPU_RLAR_A2_ATTRINDX_BITS _u(0x0000000e) +#define M33_MPU_RLAR_A2_ATTRINDX_MSB _u(3) +#define M33_MPU_RLAR_A2_ATTRINDX_LSB _u(1) +#define M33_MPU_RLAR_A2_ATTRINDX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A2_EN +// Description : Region enable +#define M33_MPU_RLAR_A2_EN_RESET _u(0x0) +#define M33_MPU_RLAR_A2_EN_BITS _u(0x00000001) +#define M33_MPU_RLAR_A2_EN_MSB _u(0) +#define M33_MPU_RLAR_A2_EN_LSB _u(0) +#define M33_MPU_RLAR_A2_EN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RBAR_A3 +// Description : Provides indirect read and write access to the base address of +// the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS +#define M33_MPU_RBAR_A3_OFFSET _u(0x0000edb4) +#define M33_MPU_RBAR_A3_BITS _u(0xffffffff) +#define M33_MPU_RBAR_A3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A3_BASE +// Description : Contains bits [31:5] of the lower inclusive limit of the +// selected MPU memory region. This value is zero extended to +// provide the base address to be checked against +#define M33_MPU_RBAR_A3_BASE_RESET _u(0x0000000) +#define M33_MPU_RBAR_A3_BASE_BITS _u(0xffffffe0) +#define M33_MPU_RBAR_A3_BASE_MSB _u(31) +#define M33_MPU_RBAR_A3_BASE_LSB _u(5) +#define M33_MPU_RBAR_A3_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A3_SH +// Description : Defines the Shareability domain of this region for Normal +// memory +#define M33_MPU_RBAR_A3_SH_RESET _u(0x0) +#define M33_MPU_RBAR_A3_SH_BITS _u(0x00000018) +#define M33_MPU_RBAR_A3_SH_MSB _u(4) +#define M33_MPU_RBAR_A3_SH_LSB _u(3) +#define M33_MPU_RBAR_A3_SH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A3_AP +// Description : Defines the access permissions for this region +#define M33_MPU_RBAR_A3_AP_RESET _u(0x0) +#define M33_MPU_RBAR_A3_AP_BITS _u(0x00000006) +#define M33_MPU_RBAR_A3_AP_MSB _u(2) +#define M33_MPU_RBAR_A3_AP_LSB _u(1) +#define M33_MPU_RBAR_A3_AP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RBAR_A3_XN +// Description : Defines whether code can be executed from this region +#define M33_MPU_RBAR_A3_XN_RESET _u(0x0) +#define M33_MPU_RBAR_A3_XN_BITS _u(0x00000001) +#define M33_MPU_RBAR_A3_XN_MSB _u(0) +#define M33_MPU_RBAR_A3_XN_LSB _u(0) +#define M33_MPU_RBAR_A3_XN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_RLAR_A3 +// Description : Provides indirect read and write access to the limit address of +// the currently selected MPU region selected by +// MPU_RNR[7:2]:(3[1:0]) `FTSSS +#define M33_MPU_RLAR_A3_OFFSET _u(0x0000edb8) +#define M33_MPU_RLAR_A3_BITS _u(0xffffffef) +#define M33_MPU_RLAR_A3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A3_LIMIT +// Description : Contains bits [31:5] of the upper inclusive limit of the +// selected MPU memory region. This value is postfixed with 0x1F +// to provide the limit address to be checked against +#define M33_MPU_RLAR_A3_LIMIT_RESET _u(0x0000000) +#define M33_MPU_RLAR_A3_LIMIT_BITS _u(0xffffffe0) +#define M33_MPU_RLAR_A3_LIMIT_MSB _u(31) +#define M33_MPU_RLAR_A3_LIMIT_LSB _u(5) +#define M33_MPU_RLAR_A3_LIMIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A3_ATTRINDX +// Description : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 +// fields +#define M33_MPU_RLAR_A3_ATTRINDX_RESET _u(0x0) +#define M33_MPU_RLAR_A3_ATTRINDX_BITS _u(0x0000000e) +#define M33_MPU_RLAR_A3_ATTRINDX_MSB _u(3) +#define M33_MPU_RLAR_A3_ATTRINDX_LSB _u(1) +#define M33_MPU_RLAR_A3_ATTRINDX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_RLAR_A3_EN +// Description : Region enable +#define M33_MPU_RLAR_A3_EN_RESET _u(0x0) +#define M33_MPU_RLAR_A3_EN_BITS _u(0x00000001) +#define M33_MPU_RLAR_A3_EN_MSB _u(0) +#define M33_MPU_RLAR_A3_EN_LSB _u(0) +#define M33_MPU_RLAR_A3_EN_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_MAIR0 +// Description : Along with MPU_MAIR1, provides the memory attribute encodings +// corresponding to the AttrIndex values +#define M33_MPU_MAIR0_OFFSET _u(0x0000edc0) +#define M33_MPU_MAIR0_BITS _u(0xffffffff) +#define M33_MPU_MAIR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR0_ATTR3 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 3 +#define M33_MPU_MAIR0_ATTR3_RESET _u(0x00) +#define M33_MPU_MAIR0_ATTR3_BITS _u(0xff000000) +#define M33_MPU_MAIR0_ATTR3_MSB _u(31) +#define M33_MPU_MAIR0_ATTR3_LSB _u(24) +#define M33_MPU_MAIR0_ATTR3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR0_ATTR2 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 2 +#define M33_MPU_MAIR0_ATTR2_RESET _u(0x00) +#define M33_MPU_MAIR0_ATTR2_BITS _u(0x00ff0000) +#define M33_MPU_MAIR0_ATTR2_MSB _u(23) +#define M33_MPU_MAIR0_ATTR2_LSB _u(16) +#define M33_MPU_MAIR0_ATTR2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR0_ATTR1 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 1 +#define M33_MPU_MAIR0_ATTR1_RESET _u(0x00) +#define M33_MPU_MAIR0_ATTR1_BITS _u(0x0000ff00) +#define M33_MPU_MAIR0_ATTR1_MSB _u(15) +#define M33_MPU_MAIR0_ATTR1_LSB _u(8) +#define M33_MPU_MAIR0_ATTR1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR0_ATTR0 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 0 +#define M33_MPU_MAIR0_ATTR0_RESET _u(0x00) +#define M33_MPU_MAIR0_ATTR0_BITS _u(0x000000ff) +#define M33_MPU_MAIR0_ATTR0_MSB _u(7) +#define M33_MPU_MAIR0_ATTR0_LSB _u(0) +#define M33_MPU_MAIR0_ATTR0_ACCESS "RW" +// ============================================================================= +// Register : M33_MPU_MAIR1 +// Description : Along with MPU_MAIR0, provides the memory attribute encodings +// corresponding to the AttrIndex values +#define M33_MPU_MAIR1_OFFSET _u(0x0000edc4) +#define M33_MPU_MAIR1_BITS _u(0xffffffff) +#define M33_MPU_MAIR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR1_ATTR7 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 7 +#define M33_MPU_MAIR1_ATTR7_RESET _u(0x00) +#define M33_MPU_MAIR1_ATTR7_BITS _u(0xff000000) +#define M33_MPU_MAIR1_ATTR7_MSB _u(31) +#define M33_MPU_MAIR1_ATTR7_LSB _u(24) +#define M33_MPU_MAIR1_ATTR7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR1_ATTR6 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 6 +#define M33_MPU_MAIR1_ATTR6_RESET _u(0x00) +#define M33_MPU_MAIR1_ATTR6_BITS _u(0x00ff0000) +#define M33_MPU_MAIR1_ATTR6_MSB _u(23) +#define M33_MPU_MAIR1_ATTR6_LSB _u(16) +#define M33_MPU_MAIR1_ATTR6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR1_ATTR5 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 5 +#define M33_MPU_MAIR1_ATTR5_RESET _u(0x00) +#define M33_MPU_MAIR1_ATTR5_BITS _u(0x0000ff00) +#define M33_MPU_MAIR1_ATTR5_MSB _u(15) +#define M33_MPU_MAIR1_ATTR5_LSB _u(8) +#define M33_MPU_MAIR1_ATTR5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_MPU_MAIR1_ATTR4 +// Description : Memory attribute encoding for MPU regions with an AttrIndex of +// 4 +#define M33_MPU_MAIR1_ATTR4_RESET _u(0x00) +#define M33_MPU_MAIR1_ATTR4_BITS _u(0x000000ff) +#define M33_MPU_MAIR1_ATTR4_MSB _u(7) +#define M33_MPU_MAIR1_ATTR4_LSB _u(0) +#define M33_MPU_MAIR1_ATTR4_ACCESS "RW" +// ============================================================================= +// Register : M33_SAU_CTRL +// Description : Allows enabling of the Security Attribution Unit +#define M33_SAU_CTRL_OFFSET _u(0x0000edd0) +#define M33_SAU_CTRL_BITS _u(0x00000003) +#define M33_SAU_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SAU_CTRL_ALLNS +// Description : When SAU_CTRL.ENABLE is 0 this bit controls if the memory is +// marked as Non-secure or Secure +#define M33_SAU_CTRL_ALLNS_RESET _u(0x0) +#define M33_SAU_CTRL_ALLNS_BITS _u(0x00000002) +#define M33_SAU_CTRL_ALLNS_MSB _u(1) +#define M33_SAU_CTRL_ALLNS_LSB _u(1) +#define M33_SAU_CTRL_ALLNS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SAU_CTRL_ENABLE +// Description : Enables the SAU +#define M33_SAU_CTRL_ENABLE_RESET _u(0x0) +#define M33_SAU_CTRL_ENABLE_BITS _u(0x00000001) +#define M33_SAU_CTRL_ENABLE_MSB _u(0) +#define M33_SAU_CTRL_ENABLE_LSB _u(0) +#define M33_SAU_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : M33_SAU_TYPE +// Description : Indicates the number of regions implemented by the Security +// Attribution Unit +#define M33_SAU_TYPE_OFFSET _u(0x0000edd4) +#define M33_SAU_TYPE_BITS _u(0x000000ff) +#define M33_SAU_TYPE_RESET _u(0x00000008) +// ----------------------------------------------------------------------------- +// Field : M33_SAU_TYPE_SREGION +// Description : The number of implemented SAU regions +#define M33_SAU_TYPE_SREGION_RESET _u(0x08) +#define M33_SAU_TYPE_SREGION_BITS _u(0x000000ff) +#define M33_SAU_TYPE_SREGION_MSB _u(7) +#define M33_SAU_TYPE_SREGION_LSB _u(0) +#define M33_SAU_TYPE_SREGION_ACCESS "RO" +// ============================================================================= +// Register : M33_SAU_RNR +// Description : Selects the region currently accessed by SAU_RBAR and SAU_RLAR +#define M33_SAU_RNR_OFFSET _u(0x0000edd8) +#define M33_SAU_RNR_BITS _u(0x000000ff) +#define M33_SAU_RNR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SAU_RNR_REGION +// Description : Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR +#define M33_SAU_RNR_REGION_RESET _u(0x00) +#define M33_SAU_RNR_REGION_BITS _u(0x000000ff) +#define M33_SAU_RNR_REGION_MSB _u(7) +#define M33_SAU_RNR_REGION_LSB _u(0) +#define M33_SAU_RNR_REGION_ACCESS "RW" +// ============================================================================= +// Register : M33_SAU_RBAR +// Description : Provides indirect read and write access to the base address of +// the currently selected SAU region +#define M33_SAU_RBAR_OFFSET _u(0x0000eddc) +#define M33_SAU_RBAR_BITS _u(0xffffffe0) +#define M33_SAU_RBAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SAU_RBAR_BADDR +// Description : Holds bits [31:5] of the base address for the selected SAU +// region +#define M33_SAU_RBAR_BADDR_RESET _u(0x0000000) +#define M33_SAU_RBAR_BADDR_BITS _u(0xffffffe0) +#define M33_SAU_RBAR_BADDR_MSB _u(31) +#define M33_SAU_RBAR_BADDR_LSB _u(5) +#define M33_SAU_RBAR_BADDR_ACCESS "RW" +// ============================================================================= +// Register : M33_SAU_RLAR +// Description : Provides indirect read and write access to the limit address of +// the currently selected SAU region +#define M33_SAU_RLAR_OFFSET _u(0x0000ede0) +#define M33_SAU_RLAR_BITS _u(0xffffffe3) +#define M33_SAU_RLAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SAU_RLAR_LADDR +// Description : Holds bits [31:5] of the limit address for the selected SAU +// region +#define M33_SAU_RLAR_LADDR_RESET _u(0x0000000) +#define M33_SAU_RLAR_LADDR_BITS _u(0xffffffe0) +#define M33_SAU_RLAR_LADDR_MSB _u(31) +#define M33_SAU_RLAR_LADDR_LSB _u(5) +#define M33_SAU_RLAR_LADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SAU_RLAR_NSC +// Description : Controls whether Non-secure state is permitted to execute an SG +// instruction from this region +#define M33_SAU_RLAR_NSC_RESET _u(0x0) +#define M33_SAU_RLAR_NSC_BITS _u(0x00000002) +#define M33_SAU_RLAR_NSC_MSB _u(1) +#define M33_SAU_RLAR_NSC_LSB _u(1) +#define M33_SAU_RLAR_NSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SAU_RLAR_ENABLE +// Description : SAU region enable +#define M33_SAU_RLAR_ENABLE_RESET _u(0x0) +#define M33_SAU_RLAR_ENABLE_BITS _u(0x00000001) +#define M33_SAU_RLAR_ENABLE_MSB _u(0) +#define M33_SAU_RLAR_ENABLE_LSB _u(0) +#define M33_SAU_RLAR_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : M33_SFSR +// Description : Provides information about any security related faults +#define M33_SFSR_OFFSET _u(0x0000ede4) +#define M33_SFSR_BITS _u(0x000000ff) +#define M33_SFSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_LSERR +// Description : Sticky flag indicating that an error occurred during lazy state +// activation or deactivation +#define M33_SFSR_LSERR_RESET _u(0x0) +#define M33_SFSR_LSERR_BITS _u(0x00000080) +#define M33_SFSR_LSERR_MSB _u(7) +#define M33_SFSR_LSERR_LSB _u(7) +#define M33_SFSR_LSERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_SFARVALID +// Description : This bit is set when the SFAR register contains a valid value. +// As with similar fields, such as BFSR.BFARVALID and +// MMFSR.MMARVALID, this bit can be cleared by other exceptions, +// such as BusFault +#define M33_SFSR_SFARVALID_RESET _u(0x0) +#define M33_SFSR_SFARVALID_BITS _u(0x00000040) +#define M33_SFSR_SFARVALID_MSB _u(6) +#define M33_SFSR_SFARVALID_LSB _u(6) +#define M33_SFSR_SFARVALID_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_LSPERR +// Description : Stick flag indicating that an SAU or IDAU violation occurred +// during the lazy preservation of floating-point state +#define M33_SFSR_LSPERR_RESET _u(0x0) +#define M33_SFSR_LSPERR_BITS _u(0x00000020) +#define M33_SFSR_LSPERR_MSB _u(5) +#define M33_SFSR_LSPERR_LSB _u(5) +#define M33_SFSR_LSPERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_INVTRAN +// Description : Sticky flag indicating that an exception was raised due to a +// branch that was not flagged as being domain crossing causing a +// transition from Secure to Non-secure memory +#define M33_SFSR_INVTRAN_RESET _u(0x0) +#define M33_SFSR_INVTRAN_BITS _u(0x00000010) +#define M33_SFSR_INVTRAN_MSB _u(4) +#define M33_SFSR_INVTRAN_LSB _u(4) +#define M33_SFSR_INVTRAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_AUVIOL +// Description : Sticky flag indicating that an attempt was made to access parts +// of the address space that are marked as Secure with NS-Req for +// the transaction set to Non-secure. This bit is not set if the +// violation occurred during lazy state preservation. See LSPERR +#define M33_SFSR_AUVIOL_RESET _u(0x0) +#define M33_SFSR_AUVIOL_BITS _u(0x00000008) +#define M33_SFSR_AUVIOL_MSB _u(3) +#define M33_SFSR_AUVIOL_LSB _u(3) +#define M33_SFSR_AUVIOL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_INVER +// Description : This can be caused by EXC_RETURN.DCRS being set to 0 when +// returning from an exception in the Non-secure state, or by +// EXC_RETURN.ES being set to 1 when returning from an exception +// in the Non-secure state +#define M33_SFSR_INVER_RESET _u(0x0) +#define M33_SFSR_INVER_BITS _u(0x00000004) +#define M33_SFSR_INVER_MSB _u(2) +#define M33_SFSR_INVER_LSB _u(2) +#define M33_SFSR_INVER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_INVIS +// Description : This bit is set if the integrity signature in an exception +// stack frame is found to be invalid during the unstacking +// operation +#define M33_SFSR_INVIS_RESET _u(0x0) +#define M33_SFSR_INVIS_BITS _u(0x00000002) +#define M33_SFSR_INVIS_MSB _u(1) +#define M33_SFSR_INVIS_LSB _u(1) +#define M33_SFSR_INVIS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_SFSR_INVEP +// Description : This bit is set if a function call from the Non-secure state or +// exception targets a non-SG instruction in the Secure state. +// This bit is also set if the target address is a SG instruction, +// but there is no matching SAU/IDAU region with the NSC flag set +#define M33_SFSR_INVEP_RESET _u(0x0) +#define M33_SFSR_INVEP_BITS _u(0x00000001) +#define M33_SFSR_INVEP_MSB _u(0) +#define M33_SFSR_INVEP_LSB _u(0) +#define M33_SFSR_INVEP_ACCESS "RW" +// ============================================================================= +// Register : M33_SFAR +// Description : Shows the address of the memory location that caused a Security +// violation +#define M33_SFAR_OFFSET _u(0x0000ede8) +#define M33_SFAR_BITS _u(0xffffffff) +#define M33_SFAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_SFAR_ADDRESS +// Description : The address of an access that caused a attribution unit +// violation. This field is only valid when SFSR.SFARVALID is set. +// This allows the actual flip flops associated with this register +// to be shared with other fault address registers. If an +// implementation chooses to share the storage in this way, care +// must be taken to not leak Secure address information to the +// Non-secure state. One way of achieving this is to share the +// SFAR register with the MMFAR_S register, which is not +// accessible to the Non-secure state +#define M33_SFAR_ADDRESS_RESET _u(0x00000000) +#define M33_SFAR_ADDRESS_BITS _u(0xffffffff) +#define M33_SFAR_ADDRESS_MSB _u(31) +#define M33_SFAR_ADDRESS_LSB _u(0) +#define M33_SFAR_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : M33_DHCSR +// Description : Controls halting debug +#define M33_DHCSR_OFFSET _u(0x0000edf0) +#define M33_DHCSR_BITS _u(0x071f002f) +#define M33_DHCSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_RESTART_ST +// Description : Indicates the PE has processed a request to clear DHCSR.C_HALT +// to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT +// from 1 to 0, or an External Restart Request +#define M33_DHCSR_S_RESTART_ST_RESET _u(0x0) +#define M33_DHCSR_S_RESTART_ST_BITS _u(0x04000000) +#define M33_DHCSR_S_RESTART_ST_MSB _u(26) +#define M33_DHCSR_S_RESTART_ST_LSB _u(26) +#define M33_DHCSR_S_RESTART_ST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_RESET_ST +// Description : Indicates whether the PE has been reset since the last read of +// the DHCSR +#define M33_DHCSR_S_RESET_ST_RESET _u(0x0) +#define M33_DHCSR_S_RESET_ST_BITS _u(0x02000000) +#define M33_DHCSR_S_RESET_ST_MSB _u(25) +#define M33_DHCSR_S_RESET_ST_LSB _u(25) +#define M33_DHCSR_S_RESET_ST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_RETIRE_ST +// Description : Set to 1 every time the PE retires one of more instructions +#define M33_DHCSR_S_RETIRE_ST_RESET _u(0x0) +#define M33_DHCSR_S_RETIRE_ST_BITS _u(0x01000000) +#define M33_DHCSR_S_RETIRE_ST_MSB _u(24) +#define M33_DHCSR_S_RETIRE_ST_LSB _u(24) +#define M33_DHCSR_S_RETIRE_ST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_SDE +// Description : Indicates whether Secure invasive debug is allowed +#define M33_DHCSR_S_SDE_RESET _u(0x0) +#define M33_DHCSR_S_SDE_BITS _u(0x00100000) +#define M33_DHCSR_S_SDE_MSB _u(20) +#define M33_DHCSR_S_SDE_LSB _u(20) +#define M33_DHCSR_S_SDE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_LOCKUP +// Description : Indicates whether the PE is in Lockup state +#define M33_DHCSR_S_LOCKUP_RESET _u(0x0) +#define M33_DHCSR_S_LOCKUP_BITS _u(0x00080000) +#define M33_DHCSR_S_LOCKUP_MSB _u(19) +#define M33_DHCSR_S_LOCKUP_LSB _u(19) +#define M33_DHCSR_S_LOCKUP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_SLEEP +// Description : Indicates whether the PE is sleeping +#define M33_DHCSR_S_SLEEP_RESET _u(0x0) +#define M33_DHCSR_S_SLEEP_BITS _u(0x00040000) +#define M33_DHCSR_S_SLEEP_MSB _u(18) +#define M33_DHCSR_S_SLEEP_LSB _u(18) +#define M33_DHCSR_S_SLEEP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_HALT +// Description : Indicates whether the PE is in Debug state +#define M33_DHCSR_S_HALT_RESET _u(0x0) +#define M33_DHCSR_S_HALT_BITS _u(0x00020000) +#define M33_DHCSR_S_HALT_MSB _u(17) +#define M33_DHCSR_S_HALT_LSB _u(17) +#define M33_DHCSR_S_HALT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_S_REGRDY +// Description : Handshake flag to transfers through the DCRDR +#define M33_DHCSR_S_REGRDY_RESET _u(0x0) +#define M33_DHCSR_S_REGRDY_BITS _u(0x00010000) +#define M33_DHCSR_S_REGRDY_MSB _u(16) +#define M33_DHCSR_S_REGRDY_LSB _u(16) +#define M33_DHCSR_S_REGRDY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_C_SNAPSTALL +// Description : Allow imprecise entry to Debug state +#define M33_DHCSR_C_SNAPSTALL_RESET _u(0x0) +#define M33_DHCSR_C_SNAPSTALL_BITS _u(0x00000020) +#define M33_DHCSR_C_SNAPSTALL_MSB _u(5) +#define M33_DHCSR_C_SNAPSTALL_LSB _u(5) +#define M33_DHCSR_C_SNAPSTALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_C_MASKINTS +// Description : When debug is enabled, the debugger can write to this bit to +// mask PendSV, SysTick and external configurable interrupts +#define M33_DHCSR_C_MASKINTS_RESET _u(0x0) +#define M33_DHCSR_C_MASKINTS_BITS _u(0x00000008) +#define M33_DHCSR_C_MASKINTS_MSB _u(3) +#define M33_DHCSR_C_MASKINTS_LSB _u(3) +#define M33_DHCSR_C_MASKINTS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_C_STEP +// Description : Enable single instruction step +#define M33_DHCSR_C_STEP_RESET _u(0x0) +#define M33_DHCSR_C_STEP_BITS _u(0x00000004) +#define M33_DHCSR_C_STEP_MSB _u(2) +#define M33_DHCSR_C_STEP_LSB _u(2) +#define M33_DHCSR_C_STEP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_C_HALT +// Description : PE enter Debug state halt request +#define M33_DHCSR_C_HALT_RESET _u(0x0) +#define M33_DHCSR_C_HALT_BITS _u(0x00000002) +#define M33_DHCSR_C_HALT_MSB _u(1) +#define M33_DHCSR_C_HALT_LSB _u(1) +#define M33_DHCSR_C_HALT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DHCSR_C_DEBUGEN +// Description : Enable Halting debug +#define M33_DHCSR_C_DEBUGEN_RESET _u(0x0) +#define M33_DHCSR_C_DEBUGEN_BITS _u(0x00000001) +#define M33_DHCSR_C_DEBUGEN_MSB _u(0) +#define M33_DHCSR_C_DEBUGEN_LSB _u(0) +#define M33_DHCSR_C_DEBUGEN_ACCESS "RW" +// ============================================================================= +// Register : M33_DCRSR +// Description : With the DCRDR, provides debug access to the general-purpose +// registers, special-purpose registers, and the FP extension +// registers. A write to the DCRSR specifies the register to +// transfer, whether the transfer is a read or write, and starts +// the transfer +#define M33_DCRSR_OFFSET _u(0x0000edf4) +#define M33_DCRSR_BITS _u(0x0001007f) +#define M33_DCRSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DCRSR_REGWNR +// Description : Specifies the access type for the transfer +#define M33_DCRSR_REGWNR_RESET _u(0x0) +#define M33_DCRSR_REGWNR_BITS _u(0x00010000) +#define M33_DCRSR_REGWNR_MSB _u(16) +#define M33_DCRSR_REGWNR_LSB _u(16) +#define M33_DCRSR_REGWNR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DCRSR_REGSEL +// Description : Specifies the general-purpose register, special-purpose +// register, or FP register to transfer +#define M33_DCRSR_REGSEL_RESET _u(0x00) +#define M33_DCRSR_REGSEL_BITS _u(0x0000007f) +#define M33_DCRSR_REGSEL_MSB _u(6) +#define M33_DCRSR_REGSEL_LSB _u(0) +#define M33_DCRSR_REGSEL_ACCESS "RW" +// ============================================================================= +// Register : M33_DCRDR +// Description : With the DCRSR, provides debug access to the general-purpose +// registers, special-purpose registers, and the FP Extension +// registers. If the Main Extension is implemented, it can also be +// used for message passing between an external debugger and a +// debug agent running on the PE +#define M33_DCRDR_OFFSET _u(0x0000edf8) +#define M33_DCRDR_BITS _u(0xffffffff) +#define M33_DCRDR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DCRDR_DBGTMP +// Description : Provides debug access for reading and writing the general- +// purpose registers, special-purpose registers, and Floating- +// point Extension registers +#define M33_DCRDR_DBGTMP_RESET _u(0x00000000) +#define M33_DCRDR_DBGTMP_BITS _u(0xffffffff) +#define M33_DCRDR_DBGTMP_MSB _u(31) +#define M33_DCRDR_DBGTMP_LSB _u(0) +#define M33_DCRDR_DBGTMP_ACCESS "RW" +// ============================================================================= +// Register : M33_DEMCR +// Description : Manages vector catch behavior and DebugMonitor handling when +// debugging +#define M33_DEMCR_OFFSET _u(0x0000edfc) +#define M33_DEMCR_BITS _u(0x011f0ff1) +#define M33_DEMCR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_TRCENA +// Description : Global enable for all DWT and ITM features +#define M33_DEMCR_TRCENA_RESET _u(0x0) +#define M33_DEMCR_TRCENA_BITS _u(0x01000000) +#define M33_DEMCR_TRCENA_MSB _u(24) +#define M33_DEMCR_TRCENA_LSB _u(24) +#define M33_DEMCR_TRCENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_SDME +// Description : Indicates whether the DebugMonitor targets the Secure or the +// Non-secure state and whether debug events are allowed in Secure +// state +#define M33_DEMCR_SDME_RESET _u(0x0) +#define M33_DEMCR_SDME_BITS _u(0x00100000) +#define M33_DEMCR_SDME_MSB _u(20) +#define M33_DEMCR_SDME_LSB _u(20) +#define M33_DEMCR_SDME_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_MON_REQ +// Description : DebugMonitor semaphore bit +#define M33_DEMCR_MON_REQ_RESET _u(0x0) +#define M33_DEMCR_MON_REQ_BITS _u(0x00080000) +#define M33_DEMCR_MON_REQ_MSB _u(19) +#define M33_DEMCR_MON_REQ_LSB _u(19) +#define M33_DEMCR_MON_REQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_MON_STEP +// Description : Enable DebugMonitor stepping +#define M33_DEMCR_MON_STEP_RESET _u(0x0) +#define M33_DEMCR_MON_STEP_BITS _u(0x00040000) +#define M33_DEMCR_MON_STEP_MSB _u(18) +#define M33_DEMCR_MON_STEP_LSB _u(18) +#define M33_DEMCR_MON_STEP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_MON_PEND +// Description : Sets or clears the pending state of the DebugMonitor exception +#define M33_DEMCR_MON_PEND_RESET _u(0x0) +#define M33_DEMCR_MON_PEND_BITS _u(0x00020000) +#define M33_DEMCR_MON_PEND_MSB _u(17) +#define M33_DEMCR_MON_PEND_LSB _u(17) +#define M33_DEMCR_MON_PEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_MON_EN +// Description : Enable the DebugMonitor exception +#define M33_DEMCR_MON_EN_RESET _u(0x0) +#define M33_DEMCR_MON_EN_BITS _u(0x00010000) +#define M33_DEMCR_MON_EN_MSB _u(16) +#define M33_DEMCR_MON_EN_LSB _u(16) +#define M33_DEMCR_MON_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_SFERR +// Description : SecureFault exception halting debug vector catch enable +#define M33_DEMCR_VC_SFERR_RESET _u(0x0) +#define M33_DEMCR_VC_SFERR_BITS _u(0x00000800) +#define M33_DEMCR_VC_SFERR_MSB _u(11) +#define M33_DEMCR_VC_SFERR_LSB _u(11) +#define M33_DEMCR_VC_SFERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_HARDERR +// Description : HardFault exception halting debug vector catch enable +#define M33_DEMCR_VC_HARDERR_RESET _u(0x0) +#define M33_DEMCR_VC_HARDERR_BITS _u(0x00000400) +#define M33_DEMCR_VC_HARDERR_MSB _u(10) +#define M33_DEMCR_VC_HARDERR_LSB _u(10) +#define M33_DEMCR_VC_HARDERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_INTERR +// Description : Enable halting debug vector catch for faults during exception +// entry and return +#define M33_DEMCR_VC_INTERR_RESET _u(0x0) +#define M33_DEMCR_VC_INTERR_BITS _u(0x00000200) +#define M33_DEMCR_VC_INTERR_MSB _u(9) +#define M33_DEMCR_VC_INTERR_LSB _u(9) +#define M33_DEMCR_VC_INTERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_BUSERR +// Description : BusFault exception halting debug vector catch enable +#define M33_DEMCR_VC_BUSERR_RESET _u(0x0) +#define M33_DEMCR_VC_BUSERR_BITS _u(0x00000100) +#define M33_DEMCR_VC_BUSERR_MSB _u(8) +#define M33_DEMCR_VC_BUSERR_LSB _u(8) +#define M33_DEMCR_VC_BUSERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_STATERR +// Description : Enable halting debug trap on a UsageFault exception caused by a +// state information error, for example an Undefined Instruction +// exception +#define M33_DEMCR_VC_STATERR_RESET _u(0x0) +#define M33_DEMCR_VC_STATERR_BITS _u(0x00000080) +#define M33_DEMCR_VC_STATERR_MSB _u(7) +#define M33_DEMCR_VC_STATERR_LSB _u(7) +#define M33_DEMCR_VC_STATERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_CHKERR +// Description : Enable halting debug trap on a UsageFault exception caused by a +// checking error, for example an alignment check error +#define M33_DEMCR_VC_CHKERR_RESET _u(0x0) +#define M33_DEMCR_VC_CHKERR_BITS _u(0x00000040) +#define M33_DEMCR_VC_CHKERR_MSB _u(6) +#define M33_DEMCR_VC_CHKERR_LSB _u(6) +#define M33_DEMCR_VC_CHKERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_NOCPERR +// Description : Enable halting debug trap on a UsageFault caused by an access +// to a coprocessor +#define M33_DEMCR_VC_NOCPERR_RESET _u(0x0) +#define M33_DEMCR_VC_NOCPERR_BITS _u(0x00000020) +#define M33_DEMCR_VC_NOCPERR_MSB _u(5) +#define M33_DEMCR_VC_NOCPERR_LSB _u(5) +#define M33_DEMCR_VC_NOCPERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_MMERR +// Description : Enable halting debug trap on a MemManage exception +#define M33_DEMCR_VC_MMERR_RESET _u(0x0) +#define M33_DEMCR_VC_MMERR_BITS _u(0x00000010) +#define M33_DEMCR_VC_MMERR_MSB _u(4) +#define M33_DEMCR_VC_MMERR_LSB _u(4) +#define M33_DEMCR_VC_MMERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DEMCR_VC_CORERESET +// Description : Enable Reset Vector Catch. This causes a warm reset to halt a +// running system +#define M33_DEMCR_VC_CORERESET_RESET _u(0x0) +#define M33_DEMCR_VC_CORERESET_BITS _u(0x00000001) +#define M33_DEMCR_VC_CORERESET_MSB _u(0) +#define M33_DEMCR_VC_CORERESET_LSB _u(0) +#define M33_DEMCR_VC_CORERESET_ACCESS "RW" +// ============================================================================= +// Register : M33_DSCSR +// Description : Provides control and status information for Secure debug +#define M33_DSCSR_OFFSET _u(0x0000ee08) +#define M33_DSCSR_BITS _u(0x00030003) +#define M33_DSCSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DSCSR_CDSKEY +// Description : Writes to the CDS bit are ignored unless CDSKEY is concurrently +// written to zero +#define M33_DSCSR_CDSKEY_RESET _u(0x0) +#define M33_DSCSR_CDSKEY_BITS _u(0x00020000) +#define M33_DSCSR_CDSKEY_MSB _u(17) +#define M33_DSCSR_CDSKEY_LSB _u(17) +#define M33_DSCSR_CDSKEY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DSCSR_CDS +// Description : This field indicates the current Security state of the +// processor +#define M33_DSCSR_CDS_RESET _u(0x0) +#define M33_DSCSR_CDS_BITS _u(0x00010000) +#define M33_DSCSR_CDS_MSB _u(16) +#define M33_DSCSR_CDS_LSB _u(16) +#define M33_DSCSR_CDS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DSCSR_SBRSEL +// Description : If SBRSELEN is 1 this bit selects whether the Non-secure or the +// Secure version of the memory-mapped Banked registers are +// accessible to the debugger +#define M33_DSCSR_SBRSEL_RESET _u(0x0) +#define M33_DSCSR_SBRSEL_BITS _u(0x00000002) +#define M33_DSCSR_SBRSEL_MSB _u(1) +#define M33_DSCSR_SBRSEL_LSB _u(1) +#define M33_DSCSR_SBRSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_DSCSR_SBRSELEN +// Description : Controls whether the SBRSEL field or the current Security state +// of the processor selects which version of the memory-mapped +// Banked registers are accessed to the debugger +#define M33_DSCSR_SBRSELEN_RESET _u(0x0) +#define M33_DSCSR_SBRSELEN_BITS _u(0x00000001) +#define M33_DSCSR_SBRSELEN_MSB _u(0) +#define M33_DSCSR_SBRSELEN_LSB _u(0) +#define M33_DSCSR_SBRSELEN_ACCESS "RW" +// ============================================================================= +// Register : M33_STIR +// Description : Provides a mechanism for software to generate an interrupt +#define M33_STIR_OFFSET _u(0x0000ef00) +#define M33_STIR_BITS _u(0x000001ff) +#define M33_STIR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_STIR_INTID +// Description : Indicates the interrupt to be pended. The value written is +// (ExceptionNumber - 16) +#define M33_STIR_INTID_RESET _u(0x000) +#define M33_STIR_INTID_BITS _u(0x000001ff) +#define M33_STIR_INTID_MSB _u(8) +#define M33_STIR_INTID_LSB _u(0) +#define M33_STIR_INTID_ACCESS "RW" +// ============================================================================= +// Register : M33_FPCCR +// Description : Holds control data for the Floating-point extension +#define M33_FPCCR_OFFSET _u(0x0000ef34) +#define M33_FPCCR_BITS _u(0xfc0007ff) +#define M33_FPCCR_RESET _u(0x20000472) +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_ASPEN +// Description : When this bit is set to 1, execution of a floating-point +// instruction sets the CONTROL.FPCA bit to 1 +#define M33_FPCCR_ASPEN_RESET _u(0x0) +#define M33_FPCCR_ASPEN_BITS _u(0x80000000) +#define M33_FPCCR_ASPEN_MSB _u(31) +#define M33_FPCCR_ASPEN_LSB _u(31) +#define M33_FPCCR_ASPEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_LSPEN +// Description : Enables lazy context save of floating-point state +#define M33_FPCCR_LSPEN_RESET _u(0x0) +#define M33_FPCCR_LSPEN_BITS _u(0x40000000) +#define M33_FPCCR_LSPEN_MSB _u(30) +#define M33_FPCCR_LSPEN_LSB _u(30) +#define M33_FPCCR_LSPEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_LSPENS +// Description : This bit controls whether the LSPEN bit is writeable from the +// Non-secure state +#define M33_FPCCR_LSPENS_RESET _u(0x1) +#define M33_FPCCR_LSPENS_BITS _u(0x20000000) +#define M33_FPCCR_LSPENS_MSB _u(29) +#define M33_FPCCR_LSPENS_LSB _u(29) +#define M33_FPCCR_LSPENS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_CLRONRET +// Description : Clear floating-point caller saved registers on exception return +#define M33_FPCCR_CLRONRET_RESET _u(0x0) +#define M33_FPCCR_CLRONRET_BITS _u(0x10000000) +#define M33_FPCCR_CLRONRET_MSB _u(28) +#define M33_FPCCR_CLRONRET_LSB _u(28) +#define M33_FPCCR_CLRONRET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_CLRONRETS +// Description : This bit controls whether the CLRONRET bit is writeable from +// the Non-secure state +#define M33_FPCCR_CLRONRETS_RESET _u(0x0) +#define M33_FPCCR_CLRONRETS_BITS _u(0x08000000) +#define M33_FPCCR_CLRONRETS_MSB _u(27) +#define M33_FPCCR_CLRONRETS_LSB _u(27) +#define M33_FPCCR_CLRONRETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_TS +// Description : Treat floating-point registers as Secure enable +#define M33_FPCCR_TS_RESET _u(0x0) +#define M33_FPCCR_TS_BITS _u(0x04000000) +#define M33_FPCCR_TS_MSB _u(26) +#define M33_FPCCR_TS_LSB _u(26) +#define M33_FPCCR_TS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_UFRDY +// Description : Indicates whether the software executing when the PE allocated +// the floating-point stack frame was able to set the UsageFault +// exception to pending +#define M33_FPCCR_UFRDY_RESET _u(0x1) +#define M33_FPCCR_UFRDY_BITS _u(0x00000400) +#define M33_FPCCR_UFRDY_MSB _u(10) +#define M33_FPCCR_UFRDY_LSB _u(10) +#define M33_FPCCR_UFRDY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_SPLIMVIOL +// Description : This bit is banked between the Security states and indicates +// whether the floating-point context violates the stack pointer +// limit that was active when lazy state preservation was +// activated. SPLIMVIOL modifies the lazy floating-point state +// preservation behavior +#define M33_FPCCR_SPLIMVIOL_RESET _u(0x0) +#define M33_FPCCR_SPLIMVIOL_BITS _u(0x00000200) +#define M33_FPCCR_SPLIMVIOL_MSB _u(9) +#define M33_FPCCR_SPLIMVIOL_LSB _u(9) +#define M33_FPCCR_SPLIMVIOL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_MONRDY +// Description : Indicates whether the software executing when the PE allocated +// the floating-point stack frame was able to set the DebugMonitor +// exception to pending +#define M33_FPCCR_MONRDY_RESET _u(0x0) +#define M33_FPCCR_MONRDY_BITS _u(0x00000100) +#define M33_FPCCR_MONRDY_MSB _u(8) +#define M33_FPCCR_MONRDY_LSB _u(8) +#define M33_FPCCR_MONRDY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_SFRDY +// Description : Indicates whether the software executing when the PE allocated +// the floating-point stack frame was able to set the SecureFault +// exception to pending. This bit is only present in the Secure +// version of the register, and behaves as RAZ/WI when accessed +// from the Non-secure state +#define M33_FPCCR_SFRDY_RESET _u(0x0) +#define M33_FPCCR_SFRDY_BITS _u(0x00000080) +#define M33_FPCCR_SFRDY_MSB _u(7) +#define M33_FPCCR_SFRDY_LSB _u(7) +#define M33_FPCCR_SFRDY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_BFRDY +// Description : Indicates whether the software executing when the PE allocated +// the floating-point stack frame was able to set the BusFault +// exception to pending +#define M33_FPCCR_BFRDY_RESET _u(0x1) +#define M33_FPCCR_BFRDY_BITS _u(0x00000040) +#define M33_FPCCR_BFRDY_MSB _u(6) +#define M33_FPCCR_BFRDY_LSB _u(6) +#define M33_FPCCR_BFRDY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_MMRDY +// Description : Indicates whether the software executing when the PE allocated +// the floating-point stack frame was able to set the MemManage +// exception to pending +#define M33_FPCCR_MMRDY_RESET _u(0x1) +#define M33_FPCCR_MMRDY_BITS _u(0x00000020) +#define M33_FPCCR_MMRDY_MSB _u(5) +#define M33_FPCCR_MMRDY_LSB _u(5) +#define M33_FPCCR_MMRDY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_HFRDY +// Description : Indicates whether the software executing when the PE allocated +// the floating-point stack frame was able to set the HardFault +// exception to pending +#define M33_FPCCR_HFRDY_RESET _u(0x1) +#define M33_FPCCR_HFRDY_BITS _u(0x00000010) +#define M33_FPCCR_HFRDY_MSB _u(4) +#define M33_FPCCR_HFRDY_LSB _u(4) +#define M33_FPCCR_HFRDY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_THREAD +// Description : Indicates the PE mode when it allocated the floating-point +// stack frame +#define M33_FPCCR_THREAD_RESET _u(0x0) +#define M33_FPCCR_THREAD_BITS _u(0x00000008) +#define M33_FPCCR_THREAD_MSB _u(3) +#define M33_FPCCR_THREAD_LSB _u(3) +#define M33_FPCCR_THREAD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_S +// Description : Security status of the floating-point context. This bit is only +// present in the Secure version of the register, and behaves as +// RAZ/WI when accessed from the Non-secure state. This bit is +// updated whenever lazy state preservation is activated, or when +// a floating-point instruction is executed +#define M33_FPCCR_S_RESET _u(0x0) +#define M33_FPCCR_S_BITS _u(0x00000004) +#define M33_FPCCR_S_MSB _u(2) +#define M33_FPCCR_S_LSB _u(2) +#define M33_FPCCR_S_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_USER +// Description : Indicates the privilege level of the software executing when +// the PE allocated the floating-point stack frame +#define M33_FPCCR_USER_RESET _u(0x1) +#define M33_FPCCR_USER_BITS _u(0x00000002) +#define M33_FPCCR_USER_MSB _u(1) +#define M33_FPCCR_USER_LSB _u(1) +#define M33_FPCCR_USER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPCCR_LSPACT +// Description : Indicates whether lazy preservation of the floating-point state +// is active +#define M33_FPCCR_LSPACT_RESET _u(0x0) +#define M33_FPCCR_LSPACT_BITS _u(0x00000001) +#define M33_FPCCR_LSPACT_MSB _u(0) +#define M33_FPCCR_LSPACT_LSB _u(0) +#define M33_FPCCR_LSPACT_ACCESS "RW" +// ============================================================================= +// Register : M33_FPCAR +// Description : Holds the location of the unpopulated floating-point register +// space allocated on an exception stack frame +#define M33_FPCAR_OFFSET _u(0x0000ef38) +#define M33_FPCAR_BITS _u(0xfffffff8) +#define M33_FPCAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FPCAR_ADDRESS +// Description : The location of the unpopulated floating-point register space +// allocated on an exception stack frame +#define M33_FPCAR_ADDRESS_RESET _u(0x00000000) +#define M33_FPCAR_ADDRESS_BITS _u(0xfffffff8) +#define M33_FPCAR_ADDRESS_MSB _u(31) +#define M33_FPCAR_ADDRESS_LSB _u(3) +#define M33_FPCAR_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : M33_FPDSCR +// Description : Holds the default values for the floating-point status control +// data that the PE assigns to the FPSCR when it creates a new +// floating-point context +#define M33_FPDSCR_OFFSET _u(0x0000ef3c) +#define M33_FPDSCR_BITS _u(0x07c00000) +#define M33_FPDSCR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_FPDSCR_AHP +// Description : Default value for FPSCR.AHP +#define M33_FPDSCR_AHP_RESET _u(0x0) +#define M33_FPDSCR_AHP_BITS _u(0x04000000) +#define M33_FPDSCR_AHP_MSB _u(26) +#define M33_FPDSCR_AHP_LSB _u(26) +#define M33_FPDSCR_AHP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPDSCR_DN +// Description : Default value for FPSCR.DN +#define M33_FPDSCR_DN_RESET _u(0x0) +#define M33_FPDSCR_DN_BITS _u(0x02000000) +#define M33_FPDSCR_DN_MSB _u(25) +#define M33_FPDSCR_DN_LSB _u(25) +#define M33_FPDSCR_DN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPDSCR_FZ +// Description : Default value for FPSCR.FZ +#define M33_FPDSCR_FZ_RESET _u(0x0) +#define M33_FPDSCR_FZ_BITS _u(0x01000000) +#define M33_FPDSCR_FZ_MSB _u(24) +#define M33_FPDSCR_FZ_LSB _u(24) +#define M33_FPDSCR_FZ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_FPDSCR_RMODE +// Description : Default value for FPSCR.RMode +#define M33_FPDSCR_RMODE_RESET _u(0x0) +#define M33_FPDSCR_RMODE_BITS _u(0x00c00000) +#define M33_FPDSCR_RMODE_MSB _u(23) +#define M33_FPDSCR_RMODE_LSB _u(22) +#define M33_FPDSCR_RMODE_ACCESS "RW" +// ============================================================================= +// Register : M33_MVFR0 +// Description : Describes the features provided by the Floating-point Extension +#define M33_MVFR0_OFFSET _u(0x0000ef40) +#define M33_MVFR0_BITS _u(0xf0ff0fff) +#define M33_MVFR0_RESET _u(0x60540601) +// ----------------------------------------------------------------------------- +// Field : M33_MVFR0_FPROUND +// Description : Indicates the rounding modes supported by the FP Extension +#define M33_MVFR0_FPROUND_RESET _u(0x6) +#define M33_MVFR0_FPROUND_BITS _u(0xf0000000) +#define M33_MVFR0_FPROUND_MSB _u(31) +#define M33_MVFR0_FPROUND_LSB _u(28) +#define M33_MVFR0_FPROUND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR0_FPSQRT +// Description : Indicates the support for FP square root operations +#define M33_MVFR0_FPSQRT_RESET _u(0x5) +#define M33_MVFR0_FPSQRT_BITS _u(0x00f00000) +#define M33_MVFR0_FPSQRT_MSB _u(23) +#define M33_MVFR0_FPSQRT_LSB _u(20) +#define M33_MVFR0_FPSQRT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR0_FPDIVIDE +// Description : Indicates the support for FP divide operations +#define M33_MVFR0_FPDIVIDE_RESET _u(0x4) +#define M33_MVFR0_FPDIVIDE_BITS _u(0x000f0000) +#define M33_MVFR0_FPDIVIDE_MSB _u(19) +#define M33_MVFR0_FPDIVIDE_LSB _u(16) +#define M33_MVFR0_FPDIVIDE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR0_FPDP +// Description : Indicates support for FP double-precision operations +#define M33_MVFR0_FPDP_RESET _u(0x6) +#define M33_MVFR0_FPDP_BITS _u(0x00000f00) +#define M33_MVFR0_FPDP_MSB _u(11) +#define M33_MVFR0_FPDP_LSB _u(8) +#define M33_MVFR0_FPDP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR0_FPSP +// Description : Indicates support for FP single-precision operations +#define M33_MVFR0_FPSP_RESET _u(0x0) +#define M33_MVFR0_FPSP_BITS _u(0x000000f0) +#define M33_MVFR0_FPSP_MSB _u(7) +#define M33_MVFR0_FPSP_LSB _u(4) +#define M33_MVFR0_FPSP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR0_SIMDREG +// Description : Indicates size of FP register file +#define M33_MVFR0_SIMDREG_RESET _u(0x1) +#define M33_MVFR0_SIMDREG_BITS _u(0x0000000f) +#define M33_MVFR0_SIMDREG_MSB _u(3) +#define M33_MVFR0_SIMDREG_LSB _u(0) +#define M33_MVFR0_SIMDREG_ACCESS "RO" +// ============================================================================= +// Register : M33_MVFR1 +// Description : Describes the features provided by the Floating-point Extension +#define M33_MVFR1_OFFSET _u(0x0000ef44) +#define M33_MVFR1_BITS _u(0xff0000ff) +#define M33_MVFR1_RESET _u(0x85000089) +// ----------------------------------------------------------------------------- +// Field : M33_MVFR1_FMAC +// Description : Indicates whether the FP Extension implements the fused +// multiply accumulate instructions +#define M33_MVFR1_FMAC_RESET _u(0x8) +#define M33_MVFR1_FMAC_BITS _u(0xf0000000) +#define M33_MVFR1_FMAC_MSB _u(31) +#define M33_MVFR1_FMAC_LSB _u(28) +#define M33_MVFR1_FMAC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR1_FPHP +// Description : Indicates whether the FP Extension implements half-precision FP +// conversion instructions +#define M33_MVFR1_FPHP_RESET _u(0x5) +#define M33_MVFR1_FPHP_BITS _u(0x0f000000) +#define M33_MVFR1_FPHP_MSB _u(27) +#define M33_MVFR1_FPHP_LSB _u(24) +#define M33_MVFR1_FPHP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR1_FPDNAN +// Description : Indicates whether the FP hardware implementation supports NaN +// propagation +#define M33_MVFR1_FPDNAN_RESET _u(0x8) +#define M33_MVFR1_FPDNAN_BITS _u(0x000000f0) +#define M33_MVFR1_FPDNAN_MSB _u(7) +#define M33_MVFR1_FPDNAN_LSB _u(4) +#define M33_MVFR1_FPDNAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_MVFR1_FPFTZ +// Description : Indicates whether subnormals are always flushed-to-zero +#define M33_MVFR1_FPFTZ_RESET _u(0x9) +#define M33_MVFR1_FPFTZ_BITS _u(0x0000000f) +#define M33_MVFR1_FPFTZ_MSB _u(3) +#define M33_MVFR1_FPFTZ_LSB _u(0) +#define M33_MVFR1_FPFTZ_ACCESS "RO" +// ============================================================================= +// Register : M33_MVFR2 +// Description : Describes the features provided by the Floating-point Extension +#define M33_MVFR2_OFFSET _u(0x0000ef48) +#define M33_MVFR2_BITS _u(0x000000f0) +#define M33_MVFR2_RESET _u(0x00000060) +// ----------------------------------------------------------------------------- +// Field : M33_MVFR2_FPMISC +// Description : Indicates support for miscellaneous FP features +#define M33_MVFR2_FPMISC_RESET _u(0x6) +#define M33_MVFR2_FPMISC_BITS _u(0x000000f0) +#define M33_MVFR2_FPMISC_MSB _u(7) +#define M33_MVFR2_FPMISC_LSB _u(4) +#define M33_MVFR2_FPMISC_ACCESS "RO" +// ============================================================================= +// Register : M33_DDEVARCH +// Description : Provides CoreSight discovery information for the SCS +#define M33_DDEVARCH_OFFSET _u(0x0000efbc) +#define M33_DDEVARCH_BITS _u(0xffffffff) +#define M33_DDEVARCH_RESET _u(0x47702a04) +// ----------------------------------------------------------------------------- +// Field : M33_DDEVARCH_ARCHITECT +// Description : Defines the architect of the component. Bits [31:28] are the +// JEP106 continuation code (JEP106 bank ID, minus 1) and bits +// [27:21] are the JEP106 ID code. +#define M33_DDEVARCH_ARCHITECT_RESET _u(0x23b) +#define M33_DDEVARCH_ARCHITECT_BITS _u(0xffe00000) +#define M33_DDEVARCH_ARCHITECT_MSB _u(31) +#define M33_DDEVARCH_ARCHITECT_LSB _u(21) +#define M33_DDEVARCH_ARCHITECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DDEVARCH_PRESENT +// Description : Defines that the DEVARCH register is present +#define M33_DDEVARCH_PRESENT_RESET _u(0x1) +#define M33_DDEVARCH_PRESENT_BITS _u(0x00100000) +#define M33_DDEVARCH_PRESENT_MSB _u(20) +#define M33_DDEVARCH_PRESENT_LSB _u(20) +#define M33_DDEVARCH_PRESENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DDEVARCH_REVISION +// Description : Defines the architecture revision of the component +#define M33_DDEVARCH_REVISION_RESET _u(0x0) +#define M33_DDEVARCH_REVISION_BITS _u(0x000f0000) +#define M33_DDEVARCH_REVISION_MSB _u(19) +#define M33_DDEVARCH_REVISION_LSB _u(16) +#define M33_DDEVARCH_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DDEVARCH_ARCHVER +// Description : Defines the architecture version of the component +#define M33_DDEVARCH_ARCHVER_RESET _u(0x2) +#define M33_DDEVARCH_ARCHVER_BITS _u(0x0000f000) +#define M33_DDEVARCH_ARCHVER_MSB _u(15) +#define M33_DDEVARCH_ARCHVER_LSB _u(12) +#define M33_DDEVARCH_ARCHVER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DDEVARCH_ARCHPART +// Description : Defines the architecture of the component +#define M33_DDEVARCH_ARCHPART_RESET _u(0xa04) +#define M33_DDEVARCH_ARCHPART_BITS _u(0x00000fff) +#define M33_DDEVARCH_ARCHPART_MSB _u(11) +#define M33_DDEVARCH_ARCHPART_LSB _u(0) +#define M33_DDEVARCH_ARCHPART_ACCESS "RO" +// ============================================================================= +// Register : M33_DDEVTYPE +// Description : Provides CoreSight discovery information for the SCS +#define M33_DDEVTYPE_OFFSET _u(0x0000efcc) +#define M33_DDEVTYPE_BITS _u(0x000000ff) +#define M33_DDEVTYPE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DDEVTYPE_SUB +// Description : Component sub-type +#define M33_DDEVTYPE_SUB_RESET _u(0x0) +#define M33_DDEVTYPE_SUB_BITS _u(0x000000f0) +#define M33_DDEVTYPE_SUB_MSB _u(7) +#define M33_DDEVTYPE_SUB_LSB _u(4) +#define M33_DDEVTYPE_SUB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DDEVTYPE_MAJOR +// Description : CoreSight major type +#define M33_DDEVTYPE_MAJOR_RESET _u(0x0) +#define M33_DDEVTYPE_MAJOR_BITS _u(0x0000000f) +#define M33_DDEVTYPE_MAJOR_MSB _u(3) +#define M33_DDEVTYPE_MAJOR_LSB _u(0) +#define M33_DDEVTYPE_MAJOR_ACCESS "RO" +// ============================================================================= +// Register : M33_DPIDR4 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR4_OFFSET _u(0x0000efd0) +#define M33_DPIDR4_BITS _u(0x000000ff) +#define M33_DPIDR4_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR4_SIZE +// Description : See CoreSight Architecture Specification +#define M33_DPIDR4_SIZE_RESET _u(0x0) +#define M33_DPIDR4_SIZE_BITS _u(0x000000f0) +#define M33_DPIDR4_SIZE_MSB _u(7) +#define M33_DPIDR4_SIZE_LSB _u(4) +#define M33_DPIDR4_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR4_DES_2 +// Description : See CoreSight Architecture Specification +#define M33_DPIDR4_DES_2_RESET _u(0x4) +#define M33_DPIDR4_DES_2_BITS _u(0x0000000f) +#define M33_DPIDR4_DES_2_MSB _u(3) +#define M33_DPIDR4_DES_2_LSB _u(0) +#define M33_DPIDR4_DES_2_ACCESS "RO" +// ============================================================================= +// Register : M33_DPIDR5 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR5_OFFSET _u(0x0000efd4) +#define M33_DPIDR5_BITS _u(0x00000000) +#define M33_DPIDR5_RESET _u(0x00000000) +#define M33_DPIDR5_MSB _u(31) +#define M33_DPIDR5_LSB _u(0) +#define M33_DPIDR5_ACCESS "RW" +// ============================================================================= +// Register : M33_DPIDR6 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR6_OFFSET _u(0x0000efd8) +#define M33_DPIDR6_BITS _u(0x00000000) +#define M33_DPIDR6_RESET _u(0x00000000) +#define M33_DPIDR6_MSB _u(31) +#define M33_DPIDR6_LSB _u(0) +#define M33_DPIDR6_ACCESS "RW" +// ============================================================================= +// Register : M33_DPIDR7 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR7_OFFSET _u(0x0000efdc) +#define M33_DPIDR7_BITS _u(0x00000000) +#define M33_DPIDR7_RESET _u(0x00000000) +#define M33_DPIDR7_MSB _u(31) +#define M33_DPIDR7_LSB _u(0) +#define M33_DPIDR7_ACCESS "RW" +// ============================================================================= +// Register : M33_DPIDR0 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR0_OFFSET _u(0x0000efe0) +#define M33_DPIDR0_BITS _u(0x000000ff) +#define M33_DPIDR0_RESET _u(0x00000021) +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR0_PART_0 +// Description : See CoreSight Architecture Specification +#define M33_DPIDR0_PART_0_RESET _u(0x21) +#define M33_DPIDR0_PART_0_BITS _u(0x000000ff) +#define M33_DPIDR0_PART_0_MSB _u(7) +#define M33_DPIDR0_PART_0_LSB _u(0) +#define M33_DPIDR0_PART_0_ACCESS "RO" +// ============================================================================= +// Register : M33_DPIDR1 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR1_OFFSET _u(0x0000efe4) +#define M33_DPIDR1_BITS _u(0x000000ff) +#define M33_DPIDR1_RESET _u(0x000000bd) +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR1_DES_0 +// Description : See CoreSight Architecture Specification +#define M33_DPIDR1_DES_0_RESET _u(0xb) +#define M33_DPIDR1_DES_0_BITS _u(0x000000f0) +#define M33_DPIDR1_DES_0_MSB _u(7) +#define M33_DPIDR1_DES_0_LSB _u(4) +#define M33_DPIDR1_DES_0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR1_PART_1 +// Description : See CoreSight Architecture Specification +#define M33_DPIDR1_PART_1_RESET _u(0xd) +#define M33_DPIDR1_PART_1_BITS _u(0x0000000f) +#define M33_DPIDR1_PART_1_MSB _u(3) +#define M33_DPIDR1_PART_1_LSB _u(0) +#define M33_DPIDR1_PART_1_ACCESS "RO" +// ============================================================================= +// Register : M33_DPIDR2 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR2_OFFSET _u(0x0000efe8) +#define M33_DPIDR2_BITS _u(0x000000ff) +#define M33_DPIDR2_RESET _u(0x0000000b) +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR2_REVISION +// Description : See CoreSight Architecture Specification +#define M33_DPIDR2_REVISION_RESET _u(0x0) +#define M33_DPIDR2_REVISION_BITS _u(0x000000f0) +#define M33_DPIDR2_REVISION_MSB _u(7) +#define M33_DPIDR2_REVISION_LSB _u(4) +#define M33_DPIDR2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR2_JEDEC +// Description : See CoreSight Architecture Specification +#define M33_DPIDR2_JEDEC_RESET _u(0x1) +#define M33_DPIDR2_JEDEC_BITS _u(0x00000008) +#define M33_DPIDR2_JEDEC_MSB _u(3) +#define M33_DPIDR2_JEDEC_LSB _u(3) +#define M33_DPIDR2_JEDEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR2_DES_1 +// Description : See CoreSight Architecture Specification +#define M33_DPIDR2_DES_1_RESET _u(0x3) +#define M33_DPIDR2_DES_1_BITS _u(0x00000007) +#define M33_DPIDR2_DES_1_MSB _u(2) +#define M33_DPIDR2_DES_1_LSB _u(0) +#define M33_DPIDR2_DES_1_ACCESS "RO" +// ============================================================================= +// Register : M33_DPIDR3 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DPIDR3_OFFSET _u(0x0000efec) +#define M33_DPIDR3_BITS _u(0x000000ff) +#define M33_DPIDR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR3_REVAND +// Description : See CoreSight Architecture Specification +#define M33_DPIDR3_REVAND_RESET _u(0x0) +#define M33_DPIDR3_REVAND_BITS _u(0x000000f0) +#define M33_DPIDR3_REVAND_MSB _u(7) +#define M33_DPIDR3_REVAND_LSB _u(4) +#define M33_DPIDR3_REVAND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DPIDR3_CMOD +// Description : See CoreSight Architecture Specification +#define M33_DPIDR3_CMOD_RESET _u(0x0) +#define M33_DPIDR3_CMOD_BITS _u(0x0000000f) +#define M33_DPIDR3_CMOD_MSB _u(3) +#define M33_DPIDR3_CMOD_LSB _u(0) +#define M33_DPIDR3_CMOD_ACCESS "RO" +// ============================================================================= +// Register : M33_DCIDR0 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DCIDR0_OFFSET _u(0x0000eff0) +#define M33_DCIDR0_BITS _u(0x000000ff) +#define M33_DCIDR0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : M33_DCIDR0_PRMBL_0 +// Description : See CoreSight Architecture Specification +#define M33_DCIDR0_PRMBL_0_RESET _u(0x0d) +#define M33_DCIDR0_PRMBL_0_BITS _u(0x000000ff) +#define M33_DCIDR0_PRMBL_0_MSB _u(7) +#define M33_DCIDR0_PRMBL_0_LSB _u(0) +#define M33_DCIDR0_PRMBL_0_ACCESS "RO" +// ============================================================================= +// Register : M33_DCIDR1 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DCIDR1_OFFSET _u(0x0000eff4) +#define M33_DCIDR1_BITS _u(0x000000ff) +#define M33_DCIDR1_RESET _u(0x00000090) +// ----------------------------------------------------------------------------- +// Field : M33_DCIDR1_CLASS +// Description : See CoreSight Architecture Specification +#define M33_DCIDR1_CLASS_RESET _u(0x9) +#define M33_DCIDR1_CLASS_BITS _u(0x000000f0) +#define M33_DCIDR1_CLASS_MSB _u(7) +#define M33_DCIDR1_CLASS_LSB _u(4) +#define M33_DCIDR1_CLASS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DCIDR1_PRMBL_1 +// Description : See CoreSight Architecture Specification +#define M33_DCIDR1_PRMBL_1_RESET _u(0x0) +#define M33_DCIDR1_PRMBL_1_BITS _u(0x0000000f) +#define M33_DCIDR1_PRMBL_1_MSB _u(3) +#define M33_DCIDR1_PRMBL_1_LSB _u(0) +#define M33_DCIDR1_PRMBL_1_ACCESS "RO" +// ============================================================================= +// Register : M33_DCIDR2 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DCIDR2_OFFSET _u(0x0000eff8) +#define M33_DCIDR2_BITS _u(0x000000ff) +#define M33_DCIDR2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : M33_DCIDR2_PRMBL_2 +// Description : See CoreSight Architecture Specification +#define M33_DCIDR2_PRMBL_2_RESET _u(0x05) +#define M33_DCIDR2_PRMBL_2_BITS _u(0x000000ff) +#define M33_DCIDR2_PRMBL_2_MSB _u(7) +#define M33_DCIDR2_PRMBL_2_LSB _u(0) +#define M33_DCIDR2_PRMBL_2_ACCESS "RO" +// ============================================================================= +// Register : M33_DCIDR3 +// Description : Provides CoreSight discovery information for the SCS +#define M33_DCIDR3_OFFSET _u(0x0000effc) +#define M33_DCIDR3_BITS _u(0x000000ff) +#define M33_DCIDR3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : M33_DCIDR3_PRMBL_3 +// Description : See CoreSight Architecture Specification +#define M33_DCIDR3_PRMBL_3_RESET _u(0xb1) +#define M33_DCIDR3_PRMBL_3_BITS _u(0x000000ff) +#define M33_DCIDR3_PRMBL_3_MSB _u(7) +#define M33_DCIDR3_PRMBL_3_LSB _u(0) +#define M33_DCIDR3_PRMBL_3_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCPRGCTLR +// Description : Programming Control Register +#define M33_TRCPRGCTLR_OFFSET _u(0x00041004) +#define M33_TRCPRGCTLR_BITS _u(0x00000001) +#define M33_TRCPRGCTLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPRGCTLR_EN +// Description : Trace Unit Enable +#define M33_TRCPRGCTLR_EN_RESET _u(0x0) +#define M33_TRCPRGCTLR_EN_BITS _u(0x00000001) +#define M33_TRCPRGCTLR_EN_MSB _u(0) +#define M33_TRCPRGCTLR_EN_LSB _u(0) +#define M33_TRCPRGCTLR_EN_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCSTATR +// Description : The TRCSTATR indicates the ETM-Teal status +#define M33_TRCSTATR_OFFSET _u(0x0004100c) +#define M33_TRCSTATR_BITS _u(0x00000003) +#define M33_TRCSTATR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCSTATR_PMSTABLE +// Description : Indicates whether the ETM-Teal registers are stable and can be +// read +#define M33_TRCSTATR_PMSTABLE_RESET _u(0x0) +#define M33_TRCSTATR_PMSTABLE_BITS _u(0x00000002) +#define M33_TRCSTATR_PMSTABLE_MSB _u(1) +#define M33_TRCSTATR_PMSTABLE_LSB _u(1) +#define M33_TRCSTATR_PMSTABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCSTATR_IDLE +// Description : Indicates that the trace unit is inactive +#define M33_TRCSTATR_IDLE_RESET _u(0x0) +#define M33_TRCSTATR_IDLE_BITS _u(0x00000001) +#define M33_TRCSTATR_IDLE_MSB _u(0) +#define M33_TRCSTATR_IDLE_LSB _u(0) +#define M33_TRCSTATR_IDLE_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCCONFIGR +// Description : The TRCCONFIGR sets the basic tracing options for the trace +// unit +#define M33_TRCCONFIGR_OFFSET _u(0x00041010) +#define M33_TRCCONFIGR_BITS _u(0x00001ff8) +#define M33_TRCCONFIGR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCONFIGR_RS +// Description : Return stack enable +#define M33_TRCCONFIGR_RS_RESET _u(0x0) +#define M33_TRCCONFIGR_RS_BITS _u(0x00001000) +#define M33_TRCCONFIGR_RS_MSB _u(12) +#define M33_TRCCONFIGR_RS_LSB _u(12) +#define M33_TRCCONFIGR_RS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCONFIGR_TS +// Description : Global timestamp tracing +#define M33_TRCCONFIGR_TS_RESET _u(0x0) +#define M33_TRCCONFIGR_TS_BITS _u(0x00000800) +#define M33_TRCCONFIGR_TS_MSB _u(11) +#define M33_TRCCONFIGR_TS_LSB _u(11) +#define M33_TRCCONFIGR_TS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCONFIGR_COND +// Description : Conditional instruction tracing +#define M33_TRCCONFIGR_COND_RESET _u(0x00) +#define M33_TRCCONFIGR_COND_BITS _u(0x000007e0) +#define M33_TRCCONFIGR_COND_MSB _u(10) +#define M33_TRCCONFIGR_COND_LSB _u(5) +#define M33_TRCCONFIGR_COND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCONFIGR_CCI +// Description : Cycle counting in instruction trace +#define M33_TRCCONFIGR_CCI_RESET _u(0x0) +#define M33_TRCCONFIGR_CCI_BITS _u(0x00000010) +#define M33_TRCCONFIGR_CCI_MSB _u(4) +#define M33_TRCCONFIGR_CCI_LSB _u(4) +#define M33_TRCCONFIGR_CCI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCONFIGR_BB +// Description : Branch broadcast mode +#define M33_TRCCONFIGR_BB_RESET _u(0x0) +#define M33_TRCCONFIGR_BB_BITS _u(0x00000008) +#define M33_TRCCONFIGR_BB_MSB _u(3) +#define M33_TRCCONFIGR_BB_LSB _u(3) +#define M33_TRCCONFIGR_BB_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCEVENTCTL0R +// Description : The TRCEVENTCTL0R controls the tracing of events in the trace +// stream. The events also drive the ETM-Teal external outputs. +#define M33_TRCEVENTCTL0R_OFFSET _u(0x00041020) +#define M33_TRCEVENTCTL0R_BITS _u(0x00008787) +#define M33_TRCEVENTCTL0R_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL0R_TYPE1 +// Description : Selects the resource type for event 1 +#define M33_TRCEVENTCTL0R_TYPE1_RESET _u(0x0) +#define M33_TRCEVENTCTL0R_TYPE1_BITS _u(0x00008000) +#define M33_TRCEVENTCTL0R_TYPE1_MSB _u(15) +#define M33_TRCEVENTCTL0R_TYPE1_LSB _u(15) +#define M33_TRCEVENTCTL0R_TYPE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL0R_SEL1 +// Description : Selects the resource number, based on the value of TYPE1: When +// TYPE1 is 0, selects a single selected resource from 0-15 +// defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean +// combined resource pair from 0-7 defined by SEL1[2:0] +#define M33_TRCEVENTCTL0R_SEL1_RESET _u(0x0) +#define M33_TRCEVENTCTL0R_SEL1_BITS _u(0x00000700) +#define M33_TRCEVENTCTL0R_SEL1_MSB _u(10) +#define M33_TRCEVENTCTL0R_SEL1_LSB _u(8) +#define M33_TRCEVENTCTL0R_SEL1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL0R_TYPE0 +// Description : Selects the resource type for event 0 +#define M33_TRCEVENTCTL0R_TYPE0_RESET _u(0x0) +#define M33_TRCEVENTCTL0R_TYPE0_BITS _u(0x00000080) +#define M33_TRCEVENTCTL0R_TYPE0_MSB _u(7) +#define M33_TRCEVENTCTL0R_TYPE0_LSB _u(7) +#define M33_TRCEVENTCTL0R_TYPE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL0R_SEL0 +// Description : Selects the resource number, based on the value of TYPE0: When +// TYPE1 is 0, selects a single selected resource from 0-15 +// defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean +// combined resource pair from 0-7 defined by SEL0[2:0] +#define M33_TRCEVENTCTL0R_SEL0_RESET _u(0x0) +#define M33_TRCEVENTCTL0R_SEL0_BITS _u(0x00000007) +#define M33_TRCEVENTCTL0R_SEL0_MSB _u(2) +#define M33_TRCEVENTCTL0R_SEL0_LSB _u(0) +#define M33_TRCEVENTCTL0R_SEL0_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCEVENTCTL1R +// Description : The TRCEVENTCTL1R controls how the events selected by +// TRCEVENTCTL0R behave +#define M33_TRCEVENTCTL1R_OFFSET _u(0x00041024) +#define M33_TRCEVENTCTL1R_BITS _u(0x00001803) +#define M33_TRCEVENTCTL1R_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL1R_LPOVERRIDE +// Description : Low power state behavior override +#define M33_TRCEVENTCTL1R_LPOVERRIDE_RESET _u(0x0) +#define M33_TRCEVENTCTL1R_LPOVERRIDE_BITS _u(0x00001000) +#define M33_TRCEVENTCTL1R_LPOVERRIDE_MSB _u(12) +#define M33_TRCEVENTCTL1R_LPOVERRIDE_LSB _u(12) +#define M33_TRCEVENTCTL1R_LPOVERRIDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL1R_ATB +// Description : ATB enabled +#define M33_TRCEVENTCTL1R_ATB_RESET _u(0x0) +#define M33_TRCEVENTCTL1R_ATB_BITS _u(0x00000800) +#define M33_TRCEVENTCTL1R_ATB_MSB _u(11) +#define M33_TRCEVENTCTL1R_ATB_LSB _u(11) +#define M33_TRCEVENTCTL1R_ATB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL1R_INSTEN1 +// Description : One bit per event, to enable generation of an event element in +// the instruction trace stream when the selected event occurs +#define M33_TRCEVENTCTL1R_INSTEN1_RESET _u(0x0) +#define M33_TRCEVENTCTL1R_INSTEN1_BITS _u(0x00000002) +#define M33_TRCEVENTCTL1R_INSTEN1_MSB _u(1) +#define M33_TRCEVENTCTL1R_INSTEN1_LSB _u(1) +#define M33_TRCEVENTCTL1R_INSTEN1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCEVENTCTL1R_INSTEN0 +// Description : One bit per event, to enable generation of an event element in +// the instruction trace stream when the selected event occurs +#define M33_TRCEVENTCTL1R_INSTEN0_RESET _u(0x0) +#define M33_TRCEVENTCTL1R_INSTEN0_BITS _u(0x00000001) +#define M33_TRCEVENTCTL1R_INSTEN0_MSB _u(0) +#define M33_TRCEVENTCTL1R_INSTEN0_LSB _u(0) +#define M33_TRCEVENTCTL1R_INSTEN0_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCSTALLCTLR +// Description : The TRCSTALLCTLR enables ETM-Teal to stall the processor if the +// ETM-Teal FIFO goes over the programmed level to minimize risk +// of overflow +#define M33_TRCSTALLCTLR_OFFSET _u(0x0004102c) +#define M33_TRCSTALLCTLR_BITS _u(0x0000050c) +#define M33_TRCSTALLCTLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCSTALLCTLR_INSTPRIORITY +// Description : Reserved, RES0 +#define M33_TRCSTALLCTLR_INSTPRIORITY_RESET _u(0x0) +#define M33_TRCSTALLCTLR_INSTPRIORITY_BITS _u(0x00000400) +#define M33_TRCSTALLCTLR_INSTPRIORITY_MSB _u(10) +#define M33_TRCSTALLCTLR_INSTPRIORITY_LSB _u(10) +#define M33_TRCSTALLCTLR_INSTPRIORITY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCSTALLCTLR_ISTALL +// Description : Stall processor based on instruction trace buffer space +#define M33_TRCSTALLCTLR_ISTALL_RESET _u(0x0) +#define M33_TRCSTALLCTLR_ISTALL_BITS _u(0x00000100) +#define M33_TRCSTALLCTLR_ISTALL_MSB _u(8) +#define M33_TRCSTALLCTLR_ISTALL_LSB _u(8) +#define M33_TRCSTALLCTLR_ISTALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCSTALLCTLR_LEVEL +// Description : Threshold at which stalling becomes active. This provides four +// levels. This level can be varied to optimize the level of +// invasion caused by stalling, balanced against the risk of a +// FIFO overflow +#define M33_TRCSTALLCTLR_LEVEL_RESET _u(0x0) +#define M33_TRCSTALLCTLR_LEVEL_BITS _u(0x0000000c) +#define M33_TRCSTALLCTLR_LEVEL_MSB _u(3) +#define M33_TRCSTALLCTLR_LEVEL_LSB _u(2) +#define M33_TRCSTALLCTLR_LEVEL_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCTSCTLR +// Description : The TRCTSCTLR controls the insertion of global timestamps into +// the trace stream. A timestamp is always inserted into the +// instruction trace stream +#define M33_TRCTSCTLR_OFFSET _u(0x00041030) +#define M33_TRCTSCTLR_BITS _u(0x00000083) +#define M33_TRCTSCTLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCTSCTLR_TYPE0 +// Description : Selects the resource type for event 0 +#define M33_TRCTSCTLR_TYPE0_RESET _u(0x0) +#define M33_TRCTSCTLR_TYPE0_BITS _u(0x00000080) +#define M33_TRCTSCTLR_TYPE0_MSB _u(7) +#define M33_TRCTSCTLR_TYPE0_LSB _u(7) +#define M33_TRCTSCTLR_TYPE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCTSCTLR_SEL0 +// Description : Selects the resource number, based on the value of TYPE0: When +// TYPE1 is 0, selects a single selected resource from 0-15 +// defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean +// combined resource pair from 0-7 defined by SEL0[2:0] +#define M33_TRCTSCTLR_SEL0_RESET _u(0x0) +#define M33_TRCTSCTLR_SEL0_BITS _u(0x00000003) +#define M33_TRCTSCTLR_SEL0_MSB _u(1) +#define M33_TRCTSCTLR_SEL0_LSB _u(0) +#define M33_TRCTSCTLR_SEL0_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCSYNCPR +// Description : The TRCSYNCPR specifies the period of trace synchronization of +// the trace streams. TRCSYNCPR defines a number of bytes of trace +// between requests for trace synchronization. This value is +// always a power of two +#define M33_TRCSYNCPR_OFFSET _u(0x00041034) +#define M33_TRCSYNCPR_BITS _u(0x0000001f) +#define M33_TRCSYNCPR_RESET _u(0x0000000a) +// ----------------------------------------------------------------------------- +// Field : M33_TRCSYNCPR_PERIOD +// Description : Defines the number of bytes of trace between trace +// synchronization requests as a total of the number of bytes +// generated by the instruction stream. The number of bytes is 2N +// where N is the value of this field: - A value of zero disables +// these periodic trace synchronization requests, but does not +// disable other trace synchronization requests. - The minimum +// value that can be programmed, other than zero, is 8, providing +// a minimum trace synchronization period of 256 bytes. - The +// maximum value is 20, providing a maximum trace synchronization +// period of 2^20 bytes +#define M33_TRCSYNCPR_PERIOD_RESET _u(0x0a) +#define M33_TRCSYNCPR_PERIOD_BITS _u(0x0000001f) +#define M33_TRCSYNCPR_PERIOD_MSB _u(4) +#define M33_TRCSYNCPR_PERIOD_LSB _u(0) +#define M33_TRCSYNCPR_PERIOD_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCCCCTLR +// Description : The TRCCCCTLR sets the threshold value for instruction trace +// cycle counting. The threshold represents the minimum interval +// between cycle count trace packets +#define M33_TRCCCCTLR_OFFSET _u(0x00041038) +#define M33_TRCCCCTLR_BITS _u(0x00000fff) +#define M33_TRCCCCTLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCCCTLR_THRESHOLD +// Description : Instruction trace cycle count threshold +#define M33_TRCCCCTLR_THRESHOLD_RESET _u(0x000) +#define M33_TRCCCCTLR_THRESHOLD_BITS _u(0x00000fff) +#define M33_TRCCCCTLR_THRESHOLD_MSB _u(11) +#define M33_TRCCCCTLR_THRESHOLD_LSB _u(0) +#define M33_TRCCCCTLR_THRESHOLD_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCVICTLR +// Description : The TRCVICTLR controls instruction trace filtering +#define M33_TRCVICTLR_OFFSET _u(0x00041080) +#define M33_TRCVICTLR_BITS _u(0x00090e83) +#define M33_TRCVICTLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCVICTLR_EXLEVEL_S3 +// Description : In Secure state, each bit controls whether instruction tracing +// is enabled for the corresponding exception level +#define M33_TRCVICTLR_EXLEVEL_S3_RESET _u(0x0) +#define M33_TRCVICTLR_EXLEVEL_S3_BITS _u(0x00080000) +#define M33_TRCVICTLR_EXLEVEL_S3_MSB _u(19) +#define M33_TRCVICTLR_EXLEVEL_S3_LSB _u(19) +#define M33_TRCVICTLR_EXLEVEL_S3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCVICTLR_EXLEVEL_S0 +// Description : In Secure state, each bit controls whether instruction tracing +// is enabled for the corresponding exception level +#define M33_TRCVICTLR_EXLEVEL_S0_RESET _u(0x0) +#define M33_TRCVICTLR_EXLEVEL_S0_BITS _u(0x00010000) +#define M33_TRCVICTLR_EXLEVEL_S0_MSB _u(16) +#define M33_TRCVICTLR_EXLEVEL_S0_LSB _u(16) +#define M33_TRCVICTLR_EXLEVEL_S0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCVICTLR_TRCERR +// Description : Selects whether a system error exception must always be traced +#define M33_TRCVICTLR_TRCERR_RESET _u(0x0) +#define M33_TRCVICTLR_TRCERR_BITS _u(0x00000800) +#define M33_TRCVICTLR_TRCERR_MSB _u(11) +#define M33_TRCVICTLR_TRCERR_LSB _u(11) +#define M33_TRCVICTLR_TRCERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCVICTLR_TRCRESET +// Description : Selects whether a reset exception must always be traced +#define M33_TRCVICTLR_TRCRESET_RESET _u(0x0) +#define M33_TRCVICTLR_TRCRESET_BITS _u(0x00000400) +#define M33_TRCVICTLR_TRCRESET_MSB _u(10) +#define M33_TRCVICTLR_TRCRESET_LSB _u(10) +#define M33_TRCVICTLR_TRCRESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCVICTLR_SSSTATUS +// Description : Indicates the current status of the start/stop logic +#define M33_TRCVICTLR_SSSTATUS_RESET _u(0x0) +#define M33_TRCVICTLR_SSSTATUS_BITS _u(0x00000200) +#define M33_TRCVICTLR_SSSTATUS_MSB _u(9) +#define M33_TRCVICTLR_SSSTATUS_LSB _u(9) +#define M33_TRCVICTLR_SSSTATUS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCVICTLR_TYPE0 +// Description : Selects the resource type for event 0 +#define M33_TRCVICTLR_TYPE0_RESET _u(0x0) +#define M33_TRCVICTLR_TYPE0_BITS _u(0x00000080) +#define M33_TRCVICTLR_TYPE0_MSB _u(7) +#define M33_TRCVICTLR_TYPE0_LSB _u(7) +#define M33_TRCVICTLR_TYPE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCVICTLR_SEL0 +// Description : Selects the resource number, based on the value of TYPE0: When +// TYPE1 is 0, selects a single selected resource from 0-15 +// defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean +// combined resource pair from 0-7 defined by SEL0[2:0] +#define M33_TRCVICTLR_SEL0_RESET _u(0x0) +#define M33_TRCVICTLR_SEL0_BITS _u(0x00000003) +#define M33_TRCVICTLR_SEL0_MSB _u(1) +#define M33_TRCVICTLR_SEL0_LSB _u(0) +#define M33_TRCVICTLR_SEL0_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCCNTRLDVR0 +// Description : The TRCCNTRLDVR defines the reload value for the reduced +// function counter +#define M33_TRCCNTRLDVR0_OFFSET _u(0x00041140) +#define M33_TRCCNTRLDVR0_BITS _u(0x0000ffff) +#define M33_TRCCNTRLDVR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCNTRLDVR0_VALUE +// Description : Defines the reload value for the counter. This value is loaded +// into the counter each time the reload event occurs +#define M33_TRCCNTRLDVR0_VALUE_RESET _u(0x0000) +#define M33_TRCCNTRLDVR0_VALUE_BITS _u(0x0000ffff) +#define M33_TRCCNTRLDVR0_VALUE_MSB _u(15) +#define M33_TRCCNTRLDVR0_VALUE_LSB _u(0) +#define M33_TRCCNTRLDVR0_VALUE_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCIDR8 +// Description : TRCIDR8 +#define M33_TRCIDR8_OFFSET _u(0x00041180) +#define M33_TRCIDR8_BITS _u(0xffffffff) +#define M33_TRCIDR8_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR8_MAXSPEC +// Description : reads as `ImpDef +#define M33_TRCIDR8_MAXSPEC_RESET _u(0x00000000) +#define M33_TRCIDR8_MAXSPEC_BITS _u(0xffffffff) +#define M33_TRCIDR8_MAXSPEC_MSB _u(31) +#define M33_TRCIDR8_MAXSPEC_LSB _u(0) +#define M33_TRCIDR8_MAXSPEC_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR9 +// Description : TRCIDR9 +#define M33_TRCIDR9_OFFSET _u(0x00041184) +#define M33_TRCIDR9_BITS _u(0xffffffff) +#define M33_TRCIDR9_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR9_NUMP0KEY +// Description : reads as `ImpDef +#define M33_TRCIDR9_NUMP0KEY_RESET _u(0x00000000) +#define M33_TRCIDR9_NUMP0KEY_BITS _u(0xffffffff) +#define M33_TRCIDR9_NUMP0KEY_MSB _u(31) +#define M33_TRCIDR9_NUMP0KEY_LSB _u(0) +#define M33_TRCIDR9_NUMP0KEY_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR10 +// Description : TRCIDR10 +#define M33_TRCIDR10_OFFSET _u(0x00041188) +#define M33_TRCIDR10_BITS _u(0xffffffff) +#define M33_TRCIDR10_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR10_NUMP1KEY +// Description : reads as `ImpDef +#define M33_TRCIDR10_NUMP1KEY_RESET _u(0x00000000) +#define M33_TRCIDR10_NUMP1KEY_BITS _u(0xffffffff) +#define M33_TRCIDR10_NUMP1KEY_MSB _u(31) +#define M33_TRCIDR10_NUMP1KEY_LSB _u(0) +#define M33_TRCIDR10_NUMP1KEY_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR11 +// Description : TRCIDR11 +#define M33_TRCIDR11_OFFSET _u(0x0004118c) +#define M33_TRCIDR11_BITS _u(0xffffffff) +#define M33_TRCIDR11_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR11_NUMP1SPC +// Description : reads as `ImpDef +#define M33_TRCIDR11_NUMP1SPC_RESET _u(0x00000000) +#define M33_TRCIDR11_NUMP1SPC_BITS _u(0xffffffff) +#define M33_TRCIDR11_NUMP1SPC_MSB _u(31) +#define M33_TRCIDR11_NUMP1SPC_LSB _u(0) +#define M33_TRCIDR11_NUMP1SPC_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR12 +// Description : TRCIDR12 +#define M33_TRCIDR12_OFFSET _u(0x00041190) +#define M33_TRCIDR12_BITS _u(0xffffffff) +#define M33_TRCIDR12_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR12_NUMCONDKEY +// Description : reads as `ImpDef +#define M33_TRCIDR12_NUMCONDKEY_RESET _u(0x00000001) +#define M33_TRCIDR12_NUMCONDKEY_BITS _u(0xffffffff) +#define M33_TRCIDR12_NUMCONDKEY_MSB _u(31) +#define M33_TRCIDR12_NUMCONDKEY_LSB _u(0) +#define M33_TRCIDR12_NUMCONDKEY_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR13 +// Description : TRCIDR13 +#define M33_TRCIDR13_OFFSET _u(0x00041194) +#define M33_TRCIDR13_BITS _u(0xffffffff) +#define M33_TRCIDR13_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR13_NUMCONDSPC +// Description : reads as `ImpDef +#define M33_TRCIDR13_NUMCONDSPC_RESET _u(0x00000000) +#define M33_TRCIDR13_NUMCONDSPC_BITS _u(0xffffffff) +#define M33_TRCIDR13_NUMCONDSPC_MSB _u(31) +#define M33_TRCIDR13_NUMCONDSPC_LSB _u(0) +#define M33_TRCIDR13_NUMCONDSPC_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIMSPEC +// Description : The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC +// features, and enables any features that are provided +#define M33_TRCIMSPEC_OFFSET _u(0x000411c0) +#define M33_TRCIMSPEC_BITS _u(0x0000000f) +#define M33_TRCIMSPEC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIMSPEC_SUPPORT +// Description : Reserved, RES0 +#define M33_TRCIMSPEC_SUPPORT_RESET _u(0x0) +#define M33_TRCIMSPEC_SUPPORT_BITS _u(0x0000000f) +#define M33_TRCIMSPEC_SUPPORT_MSB _u(3) +#define M33_TRCIMSPEC_SUPPORT_LSB _u(0) +#define M33_TRCIMSPEC_SUPPORT_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR0 +// Description : TRCIDR0 +#define M33_TRCIDR0_OFFSET _u(0x000411e0) +#define M33_TRCIDR0_BITS _u(0x3f03feff) +#define M33_TRCIDR0_RESET _u(0x280006e1) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_COMMOPT +// Description : reads as `ImpDef +#define M33_TRCIDR0_COMMOPT_RESET _u(0x1) +#define M33_TRCIDR0_COMMOPT_BITS _u(0x20000000) +#define M33_TRCIDR0_COMMOPT_MSB _u(29) +#define M33_TRCIDR0_COMMOPT_LSB _u(29) +#define M33_TRCIDR0_COMMOPT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_TSSIZE +// Description : reads as `ImpDef +#define M33_TRCIDR0_TSSIZE_RESET _u(0x08) +#define M33_TRCIDR0_TSSIZE_BITS _u(0x1f000000) +#define M33_TRCIDR0_TSSIZE_MSB _u(28) +#define M33_TRCIDR0_TSSIZE_LSB _u(24) +#define M33_TRCIDR0_TSSIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_TRCEXDATA +// Description : reads as `ImpDef +#define M33_TRCIDR0_TRCEXDATA_RESET _u(0x0) +#define M33_TRCIDR0_TRCEXDATA_BITS _u(0x00020000) +#define M33_TRCIDR0_TRCEXDATA_MSB _u(17) +#define M33_TRCIDR0_TRCEXDATA_LSB _u(17) +#define M33_TRCIDR0_TRCEXDATA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_QSUPP +// Description : reads as `ImpDef +#define M33_TRCIDR0_QSUPP_RESET _u(0x0) +#define M33_TRCIDR0_QSUPP_BITS _u(0x00018000) +#define M33_TRCIDR0_QSUPP_MSB _u(16) +#define M33_TRCIDR0_QSUPP_LSB _u(15) +#define M33_TRCIDR0_QSUPP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_QFILT +// Description : reads as `ImpDef +#define M33_TRCIDR0_QFILT_RESET _u(0x0) +#define M33_TRCIDR0_QFILT_BITS _u(0x00004000) +#define M33_TRCIDR0_QFILT_MSB _u(14) +#define M33_TRCIDR0_QFILT_LSB _u(14) +#define M33_TRCIDR0_QFILT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_CONDTYPE +// Description : reads as `ImpDef +#define M33_TRCIDR0_CONDTYPE_RESET _u(0x0) +#define M33_TRCIDR0_CONDTYPE_BITS _u(0x00003000) +#define M33_TRCIDR0_CONDTYPE_MSB _u(13) +#define M33_TRCIDR0_CONDTYPE_LSB _u(12) +#define M33_TRCIDR0_CONDTYPE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_NUMEVENT +// Description : reads as `ImpDef +#define M33_TRCIDR0_NUMEVENT_RESET _u(0x1) +#define M33_TRCIDR0_NUMEVENT_BITS _u(0x00000c00) +#define M33_TRCIDR0_NUMEVENT_MSB _u(11) +#define M33_TRCIDR0_NUMEVENT_LSB _u(10) +#define M33_TRCIDR0_NUMEVENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_RETSTACK +// Description : reads as `ImpDef +#define M33_TRCIDR0_RETSTACK_RESET _u(0x1) +#define M33_TRCIDR0_RETSTACK_BITS _u(0x00000200) +#define M33_TRCIDR0_RETSTACK_MSB _u(9) +#define M33_TRCIDR0_RETSTACK_LSB _u(9) +#define M33_TRCIDR0_RETSTACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_TRCCCI +// Description : reads as `ImpDef +#define M33_TRCIDR0_TRCCCI_RESET _u(0x1) +#define M33_TRCIDR0_TRCCCI_BITS _u(0x00000080) +#define M33_TRCIDR0_TRCCCI_MSB _u(7) +#define M33_TRCIDR0_TRCCCI_LSB _u(7) +#define M33_TRCIDR0_TRCCCI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_TRCCOND +// Description : reads as `ImpDef +#define M33_TRCIDR0_TRCCOND_RESET _u(0x1) +#define M33_TRCIDR0_TRCCOND_BITS _u(0x00000040) +#define M33_TRCIDR0_TRCCOND_MSB _u(6) +#define M33_TRCIDR0_TRCCOND_LSB _u(6) +#define M33_TRCIDR0_TRCCOND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_TRCBB +// Description : reads as `ImpDef +#define M33_TRCIDR0_TRCBB_RESET _u(0x1) +#define M33_TRCIDR0_TRCBB_BITS _u(0x00000020) +#define M33_TRCIDR0_TRCBB_MSB _u(5) +#define M33_TRCIDR0_TRCBB_LSB _u(5) +#define M33_TRCIDR0_TRCBB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_TRCDATA +// Description : reads as `ImpDef +#define M33_TRCIDR0_TRCDATA_RESET _u(0x0) +#define M33_TRCIDR0_TRCDATA_BITS _u(0x00000018) +#define M33_TRCIDR0_TRCDATA_MSB _u(4) +#define M33_TRCIDR0_TRCDATA_LSB _u(3) +#define M33_TRCIDR0_TRCDATA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_INSTP0 +// Description : reads as `ImpDef +#define M33_TRCIDR0_INSTP0_RESET _u(0x0) +#define M33_TRCIDR0_INSTP0_BITS _u(0x00000006) +#define M33_TRCIDR0_INSTP0_MSB _u(2) +#define M33_TRCIDR0_INSTP0_LSB _u(1) +#define M33_TRCIDR0_INSTP0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR0_RES1 +// Description : Reserved, RES1 +#define M33_TRCIDR0_RES1_RESET _u(0x1) +#define M33_TRCIDR0_RES1_BITS _u(0x00000001) +#define M33_TRCIDR0_RES1_MSB _u(0) +#define M33_TRCIDR0_RES1_LSB _u(0) +#define M33_TRCIDR0_RES1_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR1 +// Description : TRCIDR1 +#define M33_TRCIDR1_OFFSET _u(0x000411e4) +#define M33_TRCIDR1_BITS _u(0xff00ffff) +#define M33_TRCIDR1_RESET _u(0x4100f421) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR1_DESIGNER +// Description : reads as `ImpDef +#define M33_TRCIDR1_DESIGNER_RESET _u(0x41) +#define M33_TRCIDR1_DESIGNER_BITS _u(0xff000000) +#define M33_TRCIDR1_DESIGNER_MSB _u(31) +#define M33_TRCIDR1_DESIGNER_LSB _u(24) +#define M33_TRCIDR1_DESIGNER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR1_RES1 +// Description : Reserved, RES1 +#define M33_TRCIDR1_RES1_RESET _u(0xf) +#define M33_TRCIDR1_RES1_BITS _u(0x0000f000) +#define M33_TRCIDR1_RES1_MSB _u(15) +#define M33_TRCIDR1_RES1_LSB _u(12) +#define M33_TRCIDR1_RES1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR1_TRCARCHMAJ +// Description : reads as 0b0100 +#define M33_TRCIDR1_TRCARCHMAJ_RESET _u(0x4) +#define M33_TRCIDR1_TRCARCHMAJ_BITS _u(0x00000f00) +#define M33_TRCIDR1_TRCARCHMAJ_MSB _u(11) +#define M33_TRCIDR1_TRCARCHMAJ_LSB _u(8) +#define M33_TRCIDR1_TRCARCHMAJ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR1_TRCARCHMIN +// Description : reads as 0b0000 +#define M33_TRCIDR1_TRCARCHMIN_RESET _u(0x2) +#define M33_TRCIDR1_TRCARCHMIN_BITS _u(0x000000f0) +#define M33_TRCIDR1_TRCARCHMIN_MSB _u(7) +#define M33_TRCIDR1_TRCARCHMIN_LSB _u(4) +#define M33_TRCIDR1_TRCARCHMIN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR1_REVISION +// Description : reads as `ImpDef +#define M33_TRCIDR1_REVISION_RESET _u(0x1) +#define M33_TRCIDR1_REVISION_BITS _u(0x0000000f) +#define M33_TRCIDR1_REVISION_MSB _u(3) +#define M33_TRCIDR1_REVISION_LSB _u(0) +#define M33_TRCIDR1_REVISION_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR2 +// Description : TRCIDR2 +#define M33_TRCIDR2_OFFSET _u(0x000411e8) +#define M33_TRCIDR2_BITS _u(0x1fffffff) +#define M33_TRCIDR2_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR2_CCSIZE +// Description : reads as `ImpDef +#define M33_TRCIDR2_CCSIZE_RESET _u(0x0) +#define M33_TRCIDR2_CCSIZE_BITS _u(0x1e000000) +#define M33_TRCIDR2_CCSIZE_MSB _u(28) +#define M33_TRCIDR2_CCSIZE_LSB _u(25) +#define M33_TRCIDR2_CCSIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR2_DVSIZE +// Description : reads as `ImpDef +#define M33_TRCIDR2_DVSIZE_RESET _u(0x00) +#define M33_TRCIDR2_DVSIZE_BITS _u(0x01f00000) +#define M33_TRCIDR2_DVSIZE_MSB _u(24) +#define M33_TRCIDR2_DVSIZE_LSB _u(20) +#define M33_TRCIDR2_DVSIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR2_DASIZE +// Description : reads as `ImpDef +#define M33_TRCIDR2_DASIZE_RESET _u(0x00) +#define M33_TRCIDR2_DASIZE_BITS _u(0x000f8000) +#define M33_TRCIDR2_DASIZE_MSB _u(19) +#define M33_TRCIDR2_DASIZE_LSB _u(15) +#define M33_TRCIDR2_DASIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR2_VMIDSIZE +// Description : reads as `ImpDef +#define M33_TRCIDR2_VMIDSIZE_RESET _u(0x00) +#define M33_TRCIDR2_VMIDSIZE_BITS _u(0x00007c00) +#define M33_TRCIDR2_VMIDSIZE_MSB _u(14) +#define M33_TRCIDR2_VMIDSIZE_LSB _u(10) +#define M33_TRCIDR2_VMIDSIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR2_CIDSIZE +// Description : reads as `ImpDef +#define M33_TRCIDR2_CIDSIZE_RESET _u(0x00) +#define M33_TRCIDR2_CIDSIZE_BITS _u(0x000003e0) +#define M33_TRCIDR2_CIDSIZE_MSB _u(9) +#define M33_TRCIDR2_CIDSIZE_LSB _u(5) +#define M33_TRCIDR2_CIDSIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR2_IASIZE +// Description : reads as `ImpDef +#define M33_TRCIDR2_IASIZE_RESET _u(0x04) +#define M33_TRCIDR2_IASIZE_BITS _u(0x0000001f) +#define M33_TRCIDR2_IASIZE_MSB _u(4) +#define M33_TRCIDR2_IASIZE_LSB _u(0) +#define M33_TRCIDR2_IASIZE_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR3 +// Description : TRCIDR3 +#define M33_TRCIDR3_OFFSET _u(0x000411ec) +#define M33_TRCIDR3_BITS _u(0xffff0fff) +#define M33_TRCIDR3_RESET _u(0x0f090004) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_NOOVERFLOW +// Description : reads as `ImpDef +#define M33_TRCIDR3_NOOVERFLOW_RESET _u(0x0) +#define M33_TRCIDR3_NOOVERFLOW_BITS _u(0x80000000) +#define M33_TRCIDR3_NOOVERFLOW_MSB _u(31) +#define M33_TRCIDR3_NOOVERFLOW_LSB _u(31) +#define M33_TRCIDR3_NOOVERFLOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_NUMPROC +// Description : reads as `ImpDef +#define M33_TRCIDR3_NUMPROC_RESET _u(0x0) +#define M33_TRCIDR3_NUMPROC_BITS _u(0x70000000) +#define M33_TRCIDR3_NUMPROC_MSB _u(30) +#define M33_TRCIDR3_NUMPROC_LSB _u(28) +#define M33_TRCIDR3_NUMPROC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_SYSSTALL +// Description : reads as `ImpDef +#define M33_TRCIDR3_SYSSTALL_RESET _u(0x1) +#define M33_TRCIDR3_SYSSTALL_BITS _u(0x08000000) +#define M33_TRCIDR3_SYSSTALL_MSB _u(27) +#define M33_TRCIDR3_SYSSTALL_LSB _u(27) +#define M33_TRCIDR3_SYSSTALL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_STALLCTL +// Description : reads as `ImpDef +#define M33_TRCIDR3_STALLCTL_RESET _u(0x1) +#define M33_TRCIDR3_STALLCTL_BITS _u(0x04000000) +#define M33_TRCIDR3_STALLCTL_MSB _u(26) +#define M33_TRCIDR3_STALLCTL_LSB _u(26) +#define M33_TRCIDR3_STALLCTL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_SYNCPR +// Description : reads as `ImpDef +#define M33_TRCIDR3_SYNCPR_RESET _u(0x1) +#define M33_TRCIDR3_SYNCPR_BITS _u(0x02000000) +#define M33_TRCIDR3_SYNCPR_MSB _u(25) +#define M33_TRCIDR3_SYNCPR_LSB _u(25) +#define M33_TRCIDR3_SYNCPR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_TRCERR +// Description : reads as `ImpDef +#define M33_TRCIDR3_TRCERR_RESET _u(0x1) +#define M33_TRCIDR3_TRCERR_BITS _u(0x01000000) +#define M33_TRCIDR3_TRCERR_MSB _u(24) +#define M33_TRCIDR3_TRCERR_LSB _u(24) +#define M33_TRCIDR3_TRCERR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_EXLEVEL_NS +// Description : reads as `ImpDef +#define M33_TRCIDR3_EXLEVEL_NS_RESET _u(0x0) +#define M33_TRCIDR3_EXLEVEL_NS_BITS _u(0x00f00000) +#define M33_TRCIDR3_EXLEVEL_NS_MSB _u(23) +#define M33_TRCIDR3_EXLEVEL_NS_LSB _u(20) +#define M33_TRCIDR3_EXLEVEL_NS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_EXLEVEL_S +// Description : reads as `ImpDef +#define M33_TRCIDR3_EXLEVEL_S_RESET _u(0x9) +#define M33_TRCIDR3_EXLEVEL_S_BITS _u(0x000f0000) +#define M33_TRCIDR3_EXLEVEL_S_MSB _u(19) +#define M33_TRCIDR3_EXLEVEL_S_LSB _u(16) +#define M33_TRCIDR3_EXLEVEL_S_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR3_CCITMIN +// Description : reads as `ImpDef +#define M33_TRCIDR3_CCITMIN_RESET _u(0x004) +#define M33_TRCIDR3_CCITMIN_BITS _u(0x00000fff) +#define M33_TRCIDR3_CCITMIN_MSB _u(11) +#define M33_TRCIDR3_CCITMIN_LSB _u(0) +#define M33_TRCIDR3_CCITMIN_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR4 +// Description : TRCIDR4 +#define M33_TRCIDR4_OFFSET _u(0x000411f0) +#define M33_TRCIDR4_BITS _u(0xfffff1ff) +#define M33_TRCIDR4_RESET _u(0x00114000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_NUMVMIDC +// Description : reads as `ImpDef +#define M33_TRCIDR4_NUMVMIDC_RESET _u(0x0) +#define M33_TRCIDR4_NUMVMIDC_BITS _u(0xf0000000) +#define M33_TRCIDR4_NUMVMIDC_MSB _u(31) +#define M33_TRCIDR4_NUMVMIDC_LSB _u(28) +#define M33_TRCIDR4_NUMVMIDC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_NUMCIDC +// Description : reads as `ImpDef +#define M33_TRCIDR4_NUMCIDC_RESET _u(0x0) +#define M33_TRCIDR4_NUMCIDC_BITS _u(0x0f000000) +#define M33_TRCIDR4_NUMCIDC_MSB _u(27) +#define M33_TRCIDR4_NUMCIDC_LSB _u(24) +#define M33_TRCIDR4_NUMCIDC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_NUMSSCC +// Description : reads as `ImpDef +#define M33_TRCIDR4_NUMSSCC_RESET _u(0x1) +#define M33_TRCIDR4_NUMSSCC_BITS _u(0x00f00000) +#define M33_TRCIDR4_NUMSSCC_MSB _u(23) +#define M33_TRCIDR4_NUMSSCC_LSB _u(20) +#define M33_TRCIDR4_NUMSSCC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_NUMRSPAIR +// Description : reads as `ImpDef +#define M33_TRCIDR4_NUMRSPAIR_RESET _u(0x1) +#define M33_TRCIDR4_NUMRSPAIR_BITS _u(0x000f0000) +#define M33_TRCIDR4_NUMRSPAIR_MSB _u(19) +#define M33_TRCIDR4_NUMRSPAIR_LSB _u(16) +#define M33_TRCIDR4_NUMRSPAIR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_NUMPC +// Description : reads as `ImpDef +#define M33_TRCIDR4_NUMPC_RESET _u(0x4) +#define M33_TRCIDR4_NUMPC_BITS _u(0x0000f000) +#define M33_TRCIDR4_NUMPC_MSB _u(15) +#define M33_TRCIDR4_NUMPC_LSB _u(12) +#define M33_TRCIDR4_NUMPC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_SUPPDAC +// Description : reads as `ImpDef +#define M33_TRCIDR4_SUPPDAC_RESET _u(0x0) +#define M33_TRCIDR4_SUPPDAC_BITS _u(0x00000100) +#define M33_TRCIDR4_SUPPDAC_MSB _u(8) +#define M33_TRCIDR4_SUPPDAC_LSB _u(8) +#define M33_TRCIDR4_SUPPDAC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_NUMDVC +// Description : reads as `ImpDef +#define M33_TRCIDR4_NUMDVC_RESET _u(0x0) +#define M33_TRCIDR4_NUMDVC_BITS _u(0x000000f0) +#define M33_TRCIDR4_NUMDVC_MSB _u(7) +#define M33_TRCIDR4_NUMDVC_LSB _u(4) +#define M33_TRCIDR4_NUMDVC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR4_NUMACPAIRS +// Description : reads as `ImpDef +#define M33_TRCIDR4_NUMACPAIRS_RESET _u(0x0) +#define M33_TRCIDR4_NUMACPAIRS_BITS _u(0x0000000f) +#define M33_TRCIDR4_NUMACPAIRS_MSB _u(3) +#define M33_TRCIDR4_NUMACPAIRS_LSB _u(0) +#define M33_TRCIDR4_NUMACPAIRS_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR5 +// Description : TRCIDR5 +#define M33_TRCIDR5_OFFSET _u(0x000411f4) +#define M33_TRCIDR5_BITS _u(0xfeff0fff) +#define M33_TRCIDR5_RESET _u(0x90c70004) +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_REDFUNCNTR +// Description : reads as `ImpDef +#define M33_TRCIDR5_REDFUNCNTR_RESET _u(0x1) +#define M33_TRCIDR5_REDFUNCNTR_BITS _u(0x80000000) +#define M33_TRCIDR5_REDFUNCNTR_MSB _u(31) +#define M33_TRCIDR5_REDFUNCNTR_LSB _u(31) +#define M33_TRCIDR5_REDFUNCNTR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_NUMCNTR +// Description : reads as `ImpDef +#define M33_TRCIDR5_NUMCNTR_RESET _u(0x1) +#define M33_TRCIDR5_NUMCNTR_BITS _u(0x70000000) +#define M33_TRCIDR5_NUMCNTR_MSB _u(30) +#define M33_TRCIDR5_NUMCNTR_LSB _u(28) +#define M33_TRCIDR5_NUMCNTR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_NUMSEQSTATE +// Description : reads as `ImpDef +#define M33_TRCIDR5_NUMSEQSTATE_RESET _u(0x0) +#define M33_TRCIDR5_NUMSEQSTATE_BITS _u(0x0e000000) +#define M33_TRCIDR5_NUMSEQSTATE_MSB _u(27) +#define M33_TRCIDR5_NUMSEQSTATE_LSB _u(25) +#define M33_TRCIDR5_NUMSEQSTATE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_LPOVERRIDE +// Description : reads as `ImpDef +#define M33_TRCIDR5_LPOVERRIDE_RESET _u(0x1) +#define M33_TRCIDR5_LPOVERRIDE_BITS _u(0x00800000) +#define M33_TRCIDR5_LPOVERRIDE_MSB _u(23) +#define M33_TRCIDR5_LPOVERRIDE_LSB _u(23) +#define M33_TRCIDR5_LPOVERRIDE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_ATBTRIG +// Description : reads as `ImpDef +#define M33_TRCIDR5_ATBTRIG_RESET _u(0x1) +#define M33_TRCIDR5_ATBTRIG_BITS _u(0x00400000) +#define M33_TRCIDR5_ATBTRIG_MSB _u(22) +#define M33_TRCIDR5_ATBTRIG_LSB _u(22) +#define M33_TRCIDR5_ATBTRIG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_TRACEIDSIZE +// Description : reads as 0x07 +#define M33_TRCIDR5_TRACEIDSIZE_RESET _u(0x07) +#define M33_TRCIDR5_TRACEIDSIZE_BITS _u(0x003f0000) +#define M33_TRCIDR5_TRACEIDSIZE_MSB _u(21) +#define M33_TRCIDR5_TRACEIDSIZE_LSB _u(16) +#define M33_TRCIDR5_TRACEIDSIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_NUMEXTINSEL +// Description : reads as `ImpDef +#define M33_TRCIDR5_NUMEXTINSEL_RESET _u(0x0) +#define M33_TRCIDR5_NUMEXTINSEL_BITS _u(0x00000e00) +#define M33_TRCIDR5_NUMEXTINSEL_MSB _u(11) +#define M33_TRCIDR5_NUMEXTINSEL_LSB _u(9) +#define M33_TRCIDR5_NUMEXTINSEL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCIDR5_NUMEXTIN +// Description : reads as `ImpDef +#define M33_TRCIDR5_NUMEXTIN_RESET _u(0x004) +#define M33_TRCIDR5_NUMEXTIN_BITS _u(0x000001ff) +#define M33_TRCIDR5_NUMEXTIN_MSB _u(8) +#define M33_TRCIDR5_NUMEXTIN_LSB _u(0) +#define M33_TRCIDR5_NUMEXTIN_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCIDR6 +// Description : TRCIDR6 +#define M33_TRCIDR6_OFFSET _u(0x000411f8) +#define M33_TRCIDR6_BITS _u(0x00000000) +#define M33_TRCIDR6_RESET _u(0x00000000) +#define M33_TRCIDR6_MSB _u(31) +#define M33_TRCIDR6_LSB _u(0) +#define M33_TRCIDR6_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCIDR7 +// Description : TRCIDR7 +#define M33_TRCIDR7_OFFSET _u(0x000411fc) +#define M33_TRCIDR7_BITS _u(0x00000000) +#define M33_TRCIDR7_RESET _u(0x00000000) +#define M33_TRCIDR7_MSB _u(31) +#define M33_TRCIDR7_LSB _u(0) +#define M33_TRCIDR7_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCRSCTLR2 +// Description : The TRCRSCTLR controls the trace resources +#define M33_TRCRSCTLR2_OFFSET _u(0x00041208) +#define M33_TRCRSCTLR2_BITS _u(0x003700ff) +#define M33_TRCRSCTLR2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR2_PAIRINV +// Description : Inverts the result of a combined pair of resources. This bit +// is only implemented on the lower register for a pair of +// resource selectors +#define M33_TRCRSCTLR2_PAIRINV_RESET _u(0x0) +#define M33_TRCRSCTLR2_PAIRINV_BITS _u(0x00200000) +#define M33_TRCRSCTLR2_PAIRINV_MSB _u(21) +#define M33_TRCRSCTLR2_PAIRINV_LSB _u(21) +#define M33_TRCRSCTLR2_PAIRINV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR2_INV +// Description : Inverts the selected resources +#define M33_TRCRSCTLR2_INV_RESET _u(0x0) +#define M33_TRCRSCTLR2_INV_BITS _u(0x00100000) +#define M33_TRCRSCTLR2_INV_MSB _u(20) +#define M33_TRCRSCTLR2_INV_LSB _u(20) +#define M33_TRCRSCTLR2_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR2_GROUP +// Description : Selects a group of resource +#define M33_TRCRSCTLR2_GROUP_RESET _u(0x0) +#define M33_TRCRSCTLR2_GROUP_BITS _u(0x00070000) +#define M33_TRCRSCTLR2_GROUP_MSB _u(18) +#define M33_TRCRSCTLR2_GROUP_LSB _u(16) +#define M33_TRCRSCTLR2_GROUP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR2_SELECT +// Description : Selects one or more resources from the wanted group. One bit is +// provided per resource from the group +#define M33_TRCRSCTLR2_SELECT_RESET _u(0x00) +#define M33_TRCRSCTLR2_SELECT_BITS _u(0x000000ff) +#define M33_TRCRSCTLR2_SELECT_MSB _u(7) +#define M33_TRCRSCTLR2_SELECT_LSB _u(0) +#define M33_TRCRSCTLR2_SELECT_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCRSCTLR3 +// Description : The TRCRSCTLR controls the trace resources +#define M33_TRCRSCTLR3_OFFSET _u(0x0004120c) +#define M33_TRCRSCTLR3_BITS _u(0x003700ff) +#define M33_TRCRSCTLR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR3_PAIRINV +// Description : Inverts the result of a combined pair of resources. This bit +// is only implemented on the lower register for a pair of +// resource selectors +#define M33_TRCRSCTLR3_PAIRINV_RESET _u(0x0) +#define M33_TRCRSCTLR3_PAIRINV_BITS _u(0x00200000) +#define M33_TRCRSCTLR3_PAIRINV_MSB _u(21) +#define M33_TRCRSCTLR3_PAIRINV_LSB _u(21) +#define M33_TRCRSCTLR3_PAIRINV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR3_INV +// Description : Inverts the selected resources +#define M33_TRCRSCTLR3_INV_RESET _u(0x0) +#define M33_TRCRSCTLR3_INV_BITS _u(0x00100000) +#define M33_TRCRSCTLR3_INV_MSB _u(20) +#define M33_TRCRSCTLR3_INV_LSB _u(20) +#define M33_TRCRSCTLR3_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR3_GROUP +// Description : Selects a group of resource +#define M33_TRCRSCTLR3_GROUP_RESET _u(0x0) +#define M33_TRCRSCTLR3_GROUP_BITS _u(0x00070000) +#define M33_TRCRSCTLR3_GROUP_MSB _u(18) +#define M33_TRCRSCTLR3_GROUP_LSB _u(16) +#define M33_TRCRSCTLR3_GROUP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCRSCTLR3_SELECT +// Description : Selects one or more resources from the wanted group. One bit is +// provided per resource from the group +#define M33_TRCRSCTLR3_SELECT_RESET _u(0x00) +#define M33_TRCRSCTLR3_SELECT_BITS _u(0x000000ff) +#define M33_TRCRSCTLR3_SELECT_MSB _u(7) +#define M33_TRCRSCTLR3_SELECT_LSB _u(0) +#define M33_TRCRSCTLR3_SELECT_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCSSCSR +// Description : Controls the corresponding single-shot comparator resource +#define M33_TRCSSCSR_OFFSET _u(0x000412a0) +#define M33_TRCSSCSR_BITS _u(0x8000000f) +#define M33_TRCSSCSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCSSCSR_STATUS +// Description : Single-shot status bit. Indicates if any of the comparators, +// that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched +#define M33_TRCSSCSR_STATUS_RESET _u(0x0) +#define M33_TRCSSCSR_STATUS_BITS _u(0x80000000) +#define M33_TRCSSCSR_STATUS_MSB _u(31) +#define M33_TRCSSCSR_STATUS_LSB _u(31) +#define M33_TRCSSCSR_STATUS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCSSCSR_PC +// Description : Reserved, RES1 +#define M33_TRCSSCSR_PC_RESET _u(0x0) +#define M33_TRCSSCSR_PC_BITS _u(0x00000008) +#define M33_TRCSSCSR_PC_MSB _u(3) +#define M33_TRCSSCSR_PC_LSB _u(3) +#define M33_TRCSSCSR_PC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCSSCSR_DV +// Description : Reserved, RES0 +#define M33_TRCSSCSR_DV_RESET _u(0x0) +#define M33_TRCSSCSR_DV_BITS _u(0x00000004) +#define M33_TRCSSCSR_DV_MSB _u(2) +#define M33_TRCSSCSR_DV_LSB _u(2) +#define M33_TRCSSCSR_DV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCSSCSR_DA +// Description : Reserved, RES0 +#define M33_TRCSSCSR_DA_RESET _u(0x0) +#define M33_TRCSSCSR_DA_BITS _u(0x00000002) +#define M33_TRCSSCSR_DA_MSB _u(1) +#define M33_TRCSSCSR_DA_LSB _u(1) +#define M33_TRCSSCSR_DA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCSSCSR_INST +// Description : Reserved, RES0 +#define M33_TRCSSCSR_INST_RESET _u(0x0) +#define M33_TRCSSCSR_INST_BITS _u(0x00000001) +#define M33_TRCSSCSR_INST_MSB _u(0) +#define M33_TRCSSCSR_INST_LSB _u(0) +#define M33_TRCSSCSR_INST_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCSSPCICR +// Description : Selects the PE comparator inputs for Single-shot control +#define M33_TRCSSPCICR_OFFSET _u(0x000412c0) +#define M33_TRCSSPCICR_BITS _u(0x0000000f) +#define M33_TRCSSPCICR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCSSPCICR_PC +// Description : Selects one or more PE comparator inputs for Single-shot +// control. TRCIDR4.NUMPC defines the size of the PC field. 1 +// bit is provided for each implemented PE comparator input. For +// example, if bit[1] == 1 this selects PE comparator input 1 for +// Single-shot control +#define M33_TRCSSPCICR_PC_RESET _u(0x0) +#define M33_TRCSSPCICR_PC_BITS _u(0x0000000f) +#define M33_TRCSSPCICR_PC_MSB _u(3) +#define M33_TRCSSPCICR_PC_LSB _u(0) +#define M33_TRCSSPCICR_PC_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCPDCR +// Description : Requests the system to provide power to the trace unit +#define M33_TRCPDCR_OFFSET _u(0x00041310) +#define M33_TRCPDCR_BITS _u(0x00000008) +#define M33_TRCPDCR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPDCR_PU +// Description : Powerup request bit: +#define M33_TRCPDCR_PU_RESET _u(0x0) +#define M33_TRCPDCR_PU_BITS _u(0x00000008) +#define M33_TRCPDCR_PU_MSB _u(3) +#define M33_TRCPDCR_PU_LSB _u(3) +#define M33_TRCPDCR_PU_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCPDSR +// Description : Returns the following information about the trace unit: - OS +// Lock status. - Core power domain status. - Power interruption +// status +#define M33_TRCPDSR_OFFSET _u(0x00041314) +#define M33_TRCPDSR_BITS _u(0x00000023) +#define M33_TRCPDSR_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPDSR_OSLK +// Description : OS Lock status bit: +#define M33_TRCPDSR_OSLK_RESET _u(0x0) +#define M33_TRCPDSR_OSLK_BITS _u(0x00000020) +#define M33_TRCPDSR_OSLK_MSB _u(5) +#define M33_TRCPDSR_OSLK_LSB _u(5) +#define M33_TRCPDSR_OSLK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCPDSR_STICKYPD +// Description : Sticky powerdown status bit. Indicates whether the trace +// register state is valid: +#define M33_TRCPDSR_STICKYPD_RESET _u(0x1) +#define M33_TRCPDSR_STICKYPD_BITS _u(0x00000002) +#define M33_TRCPDSR_STICKYPD_MSB _u(1) +#define M33_TRCPDSR_STICKYPD_LSB _u(1) +#define M33_TRCPDSR_STICKYPD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCPDSR_POWER +// Description : Power status bit: +#define M33_TRCPDSR_POWER_RESET _u(0x1) +#define M33_TRCPDSR_POWER_BITS _u(0x00000001) +#define M33_TRCPDSR_POWER_MSB _u(0) +#define M33_TRCPDSR_POWER_LSB _u(0) +#define M33_TRCPDSR_POWER_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCITATBIDR +// Description : Trace Integration ATB Identification Register +#define M33_TRCITATBIDR_OFFSET _u(0x00041ee4) +#define M33_TRCITATBIDR_BITS _u(0x0000007f) +#define M33_TRCITATBIDR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCITATBIDR_ID +// Description : Trace ID +#define M33_TRCITATBIDR_ID_RESET _u(0x00) +#define M33_TRCITATBIDR_ID_BITS _u(0x0000007f) +#define M33_TRCITATBIDR_ID_MSB _u(6) +#define M33_TRCITATBIDR_ID_LSB _u(0) +#define M33_TRCITATBIDR_ID_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCITIATBINR +// Description : Trace Integration Instruction ATB In Register +#define M33_TRCITIATBINR_OFFSET _u(0x00041ef4) +#define M33_TRCITIATBINR_BITS _u(0x00000003) +#define M33_TRCITIATBINR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCITIATBINR_AFVALIDM +// Description : Integration Mode instruction AFVALIDM in +#define M33_TRCITIATBINR_AFVALIDM_RESET _u(0x0) +#define M33_TRCITIATBINR_AFVALIDM_BITS _u(0x00000002) +#define M33_TRCITIATBINR_AFVALIDM_MSB _u(1) +#define M33_TRCITIATBINR_AFVALIDM_LSB _u(1) +#define M33_TRCITIATBINR_AFVALIDM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCITIATBINR_ATREADYM +// Description : Integration Mode instruction ATREADYM in +#define M33_TRCITIATBINR_ATREADYM_RESET _u(0x0) +#define M33_TRCITIATBINR_ATREADYM_BITS _u(0x00000001) +#define M33_TRCITIATBINR_ATREADYM_MSB _u(0) +#define M33_TRCITIATBINR_ATREADYM_LSB _u(0) +#define M33_TRCITIATBINR_ATREADYM_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCITIATBOUTR +// Description : Trace Integration Instruction ATB Out Register +#define M33_TRCITIATBOUTR_OFFSET _u(0x00041efc) +#define M33_TRCITIATBOUTR_BITS _u(0x00000003) +#define M33_TRCITIATBOUTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCITIATBOUTR_AFREADY +// Description : Integration Mode instruction AFREADY out +#define M33_TRCITIATBOUTR_AFREADY_RESET _u(0x0) +#define M33_TRCITIATBOUTR_AFREADY_BITS _u(0x00000002) +#define M33_TRCITIATBOUTR_AFREADY_MSB _u(1) +#define M33_TRCITIATBOUTR_AFREADY_LSB _u(1) +#define M33_TRCITIATBOUTR_AFREADY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCITIATBOUTR_ATVALID +// Description : Integration Mode instruction ATVALID out +#define M33_TRCITIATBOUTR_ATVALID_RESET _u(0x0) +#define M33_TRCITIATBOUTR_ATVALID_BITS _u(0x00000001) +#define M33_TRCITIATBOUTR_ATVALID_MSB _u(0) +#define M33_TRCITIATBOUTR_ATVALID_LSB _u(0) +#define M33_TRCITIATBOUTR_ATVALID_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCCLAIMSET +// Description : Claim Tag Set Register +#define M33_TRCCLAIMSET_OFFSET _u(0x00041fa0) +#define M33_TRCCLAIMSET_BITS _u(0x0000000f) +#define M33_TRCCLAIMSET_RESET _u(0x0000000f) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMSET_SET3 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMSET_SET3_RESET _u(0x1) +#define M33_TRCCLAIMSET_SET3_BITS _u(0x00000008) +#define M33_TRCCLAIMSET_SET3_MSB _u(3) +#define M33_TRCCLAIMSET_SET3_LSB _u(3) +#define M33_TRCCLAIMSET_SET3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMSET_SET2 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMSET_SET2_RESET _u(0x1) +#define M33_TRCCLAIMSET_SET2_BITS _u(0x00000004) +#define M33_TRCCLAIMSET_SET2_MSB _u(2) +#define M33_TRCCLAIMSET_SET2_LSB _u(2) +#define M33_TRCCLAIMSET_SET2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMSET_SET1 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMSET_SET1_RESET _u(0x1) +#define M33_TRCCLAIMSET_SET1_BITS _u(0x00000002) +#define M33_TRCCLAIMSET_SET1_MSB _u(1) +#define M33_TRCCLAIMSET_SET1_LSB _u(1) +#define M33_TRCCLAIMSET_SET1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMSET_SET0 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMSET_SET0_RESET _u(0x1) +#define M33_TRCCLAIMSET_SET0_BITS _u(0x00000001) +#define M33_TRCCLAIMSET_SET0_MSB _u(0) +#define M33_TRCCLAIMSET_SET0_LSB _u(0) +#define M33_TRCCLAIMSET_SET0_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCCLAIMCLR +// Description : Claim Tag Clear Register +#define M33_TRCCLAIMCLR_OFFSET _u(0x00041fa4) +#define M33_TRCCLAIMCLR_BITS _u(0x0000000f) +#define M33_TRCCLAIMCLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMCLR_CLR3 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMCLR_CLR3_RESET _u(0x0) +#define M33_TRCCLAIMCLR_CLR3_BITS _u(0x00000008) +#define M33_TRCCLAIMCLR_CLR3_MSB _u(3) +#define M33_TRCCLAIMCLR_CLR3_LSB _u(3) +#define M33_TRCCLAIMCLR_CLR3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMCLR_CLR2 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMCLR_CLR2_RESET _u(0x0) +#define M33_TRCCLAIMCLR_CLR2_BITS _u(0x00000004) +#define M33_TRCCLAIMCLR_CLR2_MSB _u(2) +#define M33_TRCCLAIMCLR_CLR2_LSB _u(2) +#define M33_TRCCLAIMCLR_CLR2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMCLR_CLR1 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMCLR_CLR1_RESET _u(0x0) +#define M33_TRCCLAIMCLR_CLR1_BITS _u(0x00000002) +#define M33_TRCCLAIMCLR_CLR1_MSB _u(1) +#define M33_TRCCLAIMCLR_CLR1_LSB _u(1) +#define M33_TRCCLAIMCLR_CLR1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCLAIMCLR_CLR0 +// Description : When a write to one of these bits occurs, with the value: +#define M33_TRCCLAIMCLR_CLR0_RESET _u(0x0) +#define M33_TRCCLAIMCLR_CLR0_BITS _u(0x00000001) +#define M33_TRCCLAIMCLR_CLR0_MSB _u(0) +#define M33_TRCCLAIMCLR_CLR0_LSB _u(0) +#define M33_TRCCLAIMCLR_CLR0_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCAUTHSTATUS +// Description : Returns the level of tracing that the trace unit can support +#define M33_TRCAUTHSTATUS_OFFSET _u(0x00041fb8) +#define M33_TRCAUTHSTATUS_BITS _u(0x000000ff) +#define M33_TRCAUTHSTATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCAUTHSTATUS_SNID +// Description : Indicates whether the system enables the trace unit to support +// Secure non-invasive debug: +#define M33_TRCAUTHSTATUS_SNID_RESET _u(0x0) +#define M33_TRCAUTHSTATUS_SNID_BITS _u(0x000000c0) +#define M33_TRCAUTHSTATUS_SNID_MSB _u(7) +#define M33_TRCAUTHSTATUS_SNID_LSB _u(6) +#define M33_TRCAUTHSTATUS_SNID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCAUTHSTATUS_SID +// Description : Indicates whether the trace unit supports Secure invasive +// debug: +#define M33_TRCAUTHSTATUS_SID_RESET _u(0x0) +#define M33_TRCAUTHSTATUS_SID_BITS _u(0x00000030) +#define M33_TRCAUTHSTATUS_SID_MSB _u(5) +#define M33_TRCAUTHSTATUS_SID_LSB _u(4) +#define M33_TRCAUTHSTATUS_SID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCAUTHSTATUS_NSNID +// Description : Indicates whether the system enables the trace unit to support +// Non-secure non-invasive debug: +#define M33_TRCAUTHSTATUS_NSNID_RESET _u(0x0) +#define M33_TRCAUTHSTATUS_NSNID_BITS _u(0x0000000c) +#define M33_TRCAUTHSTATUS_NSNID_MSB _u(3) +#define M33_TRCAUTHSTATUS_NSNID_LSB _u(2) +#define M33_TRCAUTHSTATUS_NSNID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCAUTHSTATUS_NSID +// Description : Indicates whether the trace unit supports Non-secure invasive +// debug: +#define M33_TRCAUTHSTATUS_NSID_RESET _u(0x0) +#define M33_TRCAUTHSTATUS_NSID_BITS _u(0x00000003) +#define M33_TRCAUTHSTATUS_NSID_MSB _u(1) +#define M33_TRCAUTHSTATUS_NSID_LSB _u(0) +#define M33_TRCAUTHSTATUS_NSID_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCDEVARCH +// Description : TRCDEVARCH +#define M33_TRCDEVARCH_OFFSET _u(0x00041fbc) +#define M33_TRCDEVARCH_BITS _u(0xffffffff) +#define M33_TRCDEVARCH_RESET _u(0x47724a13) +// ----------------------------------------------------------------------------- +// Field : M33_TRCDEVARCH_ARCHITECT +// Description : reads as 0b01000111011 +#define M33_TRCDEVARCH_ARCHITECT_RESET _u(0x23b) +#define M33_TRCDEVARCH_ARCHITECT_BITS _u(0xffe00000) +#define M33_TRCDEVARCH_ARCHITECT_MSB _u(31) +#define M33_TRCDEVARCH_ARCHITECT_LSB _u(21) +#define M33_TRCDEVARCH_ARCHITECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCDEVARCH_PRESENT +// Description : reads as 0b1 +#define M33_TRCDEVARCH_PRESENT_RESET _u(0x1) +#define M33_TRCDEVARCH_PRESENT_BITS _u(0x00100000) +#define M33_TRCDEVARCH_PRESENT_MSB _u(20) +#define M33_TRCDEVARCH_PRESENT_LSB _u(20) +#define M33_TRCDEVARCH_PRESENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCDEVARCH_REVISION +// Description : reads as 0b0000 +#define M33_TRCDEVARCH_REVISION_RESET _u(0x2) +#define M33_TRCDEVARCH_REVISION_BITS _u(0x000f0000) +#define M33_TRCDEVARCH_REVISION_MSB _u(19) +#define M33_TRCDEVARCH_REVISION_LSB _u(16) +#define M33_TRCDEVARCH_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCDEVARCH_ARCHID +// Description : reads as 0b0100101000010011 +#define M33_TRCDEVARCH_ARCHID_RESET _u(0x4a13) +#define M33_TRCDEVARCH_ARCHID_BITS _u(0x0000ffff) +#define M33_TRCDEVARCH_ARCHID_MSB _u(15) +#define M33_TRCDEVARCH_ARCHID_LSB _u(0) +#define M33_TRCDEVARCH_ARCHID_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCDEVID +// Description : TRCDEVID +#define M33_TRCDEVID_OFFSET _u(0x00041fc8) +#define M33_TRCDEVID_BITS _u(0x00000000) +#define M33_TRCDEVID_RESET _u(0x00000000) +#define M33_TRCDEVID_MSB _u(31) +#define M33_TRCDEVID_LSB _u(0) +#define M33_TRCDEVID_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCDEVTYPE +// Description : TRCDEVTYPE +#define M33_TRCDEVTYPE_OFFSET _u(0x00041fcc) +#define M33_TRCDEVTYPE_BITS _u(0x000000ff) +#define M33_TRCDEVTYPE_RESET _u(0x00000013) +// ----------------------------------------------------------------------------- +// Field : M33_TRCDEVTYPE_SUB +// Description : reads as 0b0001 +#define M33_TRCDEVTYPE_SUB_RESET _u(0x1) +#define M33_TRCDEVTYPE_SUB_BITS _u(0x000000f0) +#define M33_TRCDEVTYPE_SUB_MSB _u(7) +#define M33_TRCDEVTYPE_SUB_LSB _u(4) +#define M33_TRCDEVTYPE_SUB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCDEVTYPE_MAJOR +// Description : reads as 0b0011 +#define M33_TRCDEVTYPE_MAJOR_RESET _u(0x3) +#define M33_TRCDEVTYPE_MAJOR_BITS _u(0x0000000f) +#define M33_TRCDEVTYPE_MAJOR_MSB _u(3) +#define M33_TRCDEVTYPE_MAJOR_LSB _u(0) +#define M33_TRCDEVTYPE_MAJOR_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCPIDR4 +// Description : TRCPIDR4 +#define M33_TRCPIDR4_OFFSET _u(0x00041fd0) +#define M33_TRCPIDR4_BITS _u(0x000000ff) +#define M33_TRCPIDR4_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR4_SIZE +// Description : reads as `ImpDef +#define M33_TRCPIDR4_SIZE_RESET _u(0x0) +#define M33_TRCPIDR4_SIZE_BITS _u(0x000000f0) +#define M33_TRCPIDR4_SIZE_MSB _u(7) +#define M33_TRCPIDR4_SIZE_LSB _u(4) +#define M33_TRCPIDR4_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR4_DES_2 +// Description : reads as `ImpDef +#define M33_TRCPIDR4_DES_2_RESET _u(0x4) +#define M33_TRCPIDR4_DES_2_BITS _u(0x0000000f) +#define M33_TRCPIDR4_DES_2_MSB _u(3) +#define M33_TRCPIDR4_DES_2_LSB _u(0) +#define M33_TRCPIDR4_DES_2_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCPIDR5 +// Description : TRCPIDR5 +#define M33_TRCPIDR5_OFFSET _u(0x00041fd4) +#define M33_TRCPIDR5_BITS _u(0x00000000) +#define M33_TRCPIDR5_RESET _u(0x00000000) +#define M33_TRCPIDR5_MSB _u(31) +#define M33_TRCPIDR5_LSB _u(0) +#define M33_TRCPIDR5_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCPIDR6 +// Description : TRCPIDR6 +#define M33_TRCPIDR6_OFFSET _u(0x00041fd8) +#define M33_TRCPIDR6_BITS _u(0x00000000) +#define M33_TRCPIDR6_RESET _u(0x00000000) +#define M33_TRCPIDR6_MSB _u(31) +#define M33_TRCPIDR6_LSB _u(0) +#define M33_TRCPIDR6_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCPIDR7 +// Description : TRCPIDR7 +#define M33_TRCPIDR7_OFFSET _u(0x00041fdc) +#define M33_TRCPIDR7_BITS _u(0x00000000) +#define M33_TRCPIDR7_RESET _u(0x00000000) +#define M33_TRCPIDR7_MSB _u(31) +#define M33_TRCPIDR7_LSB _u(0) +#define M33_TRCPIDR7_ACCESS "RW" +// ============================================================================= +// Register : M33_TRCPIDR0 +// Description : TRCPIDR0 +#define M33_TRCPIDR0_OFFSET _u(0x00041fe0) +#define M33_TRCPIDR0_BITS _u(0x000000ff) +#define M33_TRCPIDR0_RESET _u(0x00000021) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR0_PART_0 +// Description : reads as `ImpDef +#define M33_TRCPIDR0_PART_0_RESET _u(0x21) +#define M33_TRCPIDR0_PART_0_BITS _u(0x000000ff) +#define M33_TRCPIDR0_PART_0_MSB _u(7) +#define M33_TRCPIDR0_PART_0_LSB _u(0) +#define M33_TRCPIDR0_PART_0_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCPIDR1 +// Description : TRCPIDR1 +#define M33_TRCPIDR1_OFFSET _u(0x00041fe4) +#define M33_TRCPIDR1_BITS _u(0x000000ff) +#define M33_TRCPIDR1_RESET _u(0x000000bd) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR1_DES_0 +// Description : reads as `ImpDef +#define M33_TRCPIDR1_DES_0_RESET _u(0xb) +#define M33_TRCPIDR1_DES_0_BITS _u(0x000000f0) +#define M33_TRCPIDR1_DES_0_MSB _u(7) +#define M33_TRCPIDR1_DES_0_LSB _u(4) +#define M33_TRCPIDR1_DES_0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR1_PART_0 +// Description : reads as `ImpDef +#define M33_TRCPIDR1_PART_0_RESET _u(0xd) +#define M33_TRCPIDR1_PART_0_BITS _u(0x0000000f) +#define M33_TRCPIDR1_PART_0_MSB _u(3) +#define M33_TRCPIDR1_PART_0_LSB _u(0) +#define M33_TRCPIDR1_PART_0_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCPIDR2 +// Description : TRCPIDR2 +#define M33_TRCPIDR2_OFFSET _u(0x00041fe8) +#define M33_TRCPIDR2_BITS _u(0x000000ff) +#define M33_TRCPIDR2_RESET _u(0x0000002b) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR2_REVISION +// Description : reads as `ImpDef +#define M33_TRCPIDR2_REVISION_RESET _u(0x2) +#define M33_TRCPIDR2_REVISION_BITS _u(0x000000f0) +#define M33_TRCPIDR2_REVISION_MSB _u(7) +#define M33_TRCPIDR2_REVISION_LSB _u(4) +#define M33_TRCPIDR2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR2_JEDEC +// Description : reads as 0b1 +#define M33_TRCPIDR2_JEDEC_RESET _u(0x1) +#define M33_TRCPIDR2_JEDEC_BITS _u(0x00000008) +#define M33_TRCPIDR2_JEDEC_MSB _u(3) +#define M33_TRCPIDR2_JEDEC_LSB _u(3) +#define M33_TRCPIDR2_JEDEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR2_DES_0 +// Description : reads as `ImpDef +#define M33_TRCPIDR2_DES_0_RESET _u(0x3) +#define M33_TRCPIDR2_DES_0_BITS _u(0x00000007) +#define M33_TRCPIDR2_DES_0_MSB _u(2) +#define M33_TRCPIDR2_DES_0_LSB _u(0) +#define M33_TRCPIDR2_DES_0_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCPIDR3 +// Description : TRCPIDR3 +#define M33_TRCPIDR3_OFFSET _u(0x00041fec) +#define M33_TRCPIDR3_BITS _u(0x000000ff) +#define M33_TRCPIDR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR3_REVAND +// Description : reads as `ImpDef +#define M33_TRCPIDR3_REVAND_RESET _u(0x0) +#define M33_TRCPIDR3_REVAND_BITS _u(0x000000f0) +#define M33_TRCPIDR3_REVAND_MSB _u(7) +#define M33_TRCPIDR3_REVAND_LSB _u(4) +#define M33_TRCPIDR3_REVAND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCPIDR3_CMOD +// Description : reads as `ImpDef +#define M33_TRCPIDR3_CMOD_RESET _u(0x0) +#define M33_TRCPIDR3_CMOD_BITS _u(0x0000000f) +#define M33_TRCPIDR3_CMOD_MSB _u(3) +#define M33_TRCPIDR3_CMOD_LSB _u(0) +#define M33_TRCPIDR3_CMOD_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCCIDR0 +// Description : TRCCIDR0 +#define M33_TRCCIDR0_OFFSET _u(0x00041ff0) +#define M33_TRCCIDR0_BITS _u(0x000000ff) +#define M33_TRCCIDR0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCIDR0_PRMBL_0 +// Description : reads as 0b00001101 +#define M33_TRCCIDR0_PRMBL_0_RESET _u(0x0d) +#define M33_TRCCIDR0_PRMBL_0_BITS _u(0x000000ff) +#define M33_TRCCIDR0_PRMBL_0_MSB _u(7) +#define M33_TRCCIDR0_PRMBL_0_LSB _u(0) +#define M33_TRCCIDR0_PRMBL_0_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCCIDR1 +// Description : TRCCIDR1 +#define M33_TRCCIDR1_OFFSET _u(0x00041ff4) +#define M33_TRCCIDR1_BITS _u(0x000000ff) +#define M33_TRCCIDR1_RESET _u(0x00000090) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCIDR1_CLASS +// Description : reads as 0b1001 +#define M33_TRCCIDR1_CLASS_RESET _u(0x9) +#define M33_TRCCIDR1_CLASS_BITS _u(0x000000f0) +#define M33_TRCCIDR1_CLASS_MSB _u(7) +#define M33_TRCCIDR1_CLASS_LSB _u(4) +#define M33_TRCCIDR1_CLASS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_TRCCIDR1_PRMBL_1 +// Description : reads as 0b0000 +#define M33_TRCCIDR1_PRMBL_1_RESET _u(0x0) +#define M33_TRCCIDR1_PRMBL_1_BITS _u(0x0000000f) +#define M33_TRCCIDR1_PRMBL_1_MSB _u(3) +#define M33_TRCCIDR1_PRMBL_1_LSB _u(0) +#define M33_TRCCIDR1_PRMBL_1_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCCIDR2 +// Description : TRCCIDR2 +#define M33_TRCCIDR2_OFFSET _u(0x00041ff8) +#define M33_TRCCIDR2_BITS _u(0x000000ff) +#define M33_TRCCIDR2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCIDR2_PRMBL_2 +// Description : reads as 0b00000101 +#define M33_TRCCIDR2_PRMBL_2_RESET _u(0x05) +#define M33_TRCCIDR2_PRMBL_2_BITS _u(0x000000ff) +#define M33_TRCCIDR2_PRMBL_2_MSB _u(7) +#define M33_TRCCIDR2_PRMBL_2_LSB _u(0) +#define M33_TRCCIDR2_PRMBL_2_ACCESS "RO" +// ============================================================================= +// Register : M33_TRCCIDR3 +// Description : TRCCIDR3 +#define M33_TRCCIDR3_OFFSET _u(0x00041ffc) +#define M33_TRCCIDR3_BITS _u(0x000000ff) +#define M33_TRCCIDR3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : M33_TRCCIDR3_PRMBL_3 +// Description : reads as 0b10110001 +#define M33_TRCCIDR3_PRMBL_3_RESET _u(0xb1) +#define M33_TRCCIDR3_PRMBL_3_BITS _u(0x000000ff) +#define M33_TRCCIDR3_PRMBL_3_MSB _u(7) +#define M33_TRCCIDR3_PRMBL_3_LSB _u(0) +#define M33_TRCCIDR3_PRMBL_3_ACCESS "RO" +// ============================================================================= +// Register : M33_CTICONTROL +// Description : CTI Control Register +#define M33_CTICONTROL_OFFSET _u(0x00042000) +#define M33_CTICONTROL_BITS _u(0x00000001) +#define M33_CTICONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTICONTROL_GLBEN +// Description : Enables or disables the CTI +#define M33_CTICONTROL_GLBEN_RESET _u(0x0) +#define M33_CTICONTROL_GLBEN_BITS _u(0x00000001) +#define M33_CTICONTROL_GLBEN_MSB _u(0) +#define M33_CTICONTROL_GLBEN_LSB _u(0) +#define M33_CTICONTROL_GLBEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINTACK +// Description : CTI Interrupt Acknowledge Register +#define M33_CTIINTACK_OFFSET _u(0x00042010) +#define M33_CTIINTACK_BITS _u(0x000000ff) +#define M33_CTIINTACK_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINTACK_INTACK +// Description : Acknowledges the corresponding ctitrigout output. There is one +// bit of the register for each ctitrigout output. When a 1 is +// written to a bit in this register, the corresponding ctitrigout +// is acknowledged, causing it to be cleared. +#define M33_CTIINTACK_INTACK_RESET _u(0x00) +#define M33_CTIINTACK_INTACK_BITS _u(0x000000ff) +#define M33_CTIINTACK_INTACK_MSB _u(7) +#define M33_CTIINTACK_INTACK_LSB _u(0) +#define M33_CTIINTACK_INTACK_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIAPPSET +// Description : CTI Application Trigger Set Register +#define M33_CTIAPPSET_OFFSET _u(0x00042014) +#define M33_CTIAPPSET_BITS _u(0x0000000f) +#define M33_CTIAPPSET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIAPPSET_APPSET +// Description : Setting a bit HIGH generates a channel event for the selected +// channel. There is one bit of the register for each channel +#define M33_CTIAPPSET_APPSET_RESET _u(0x0) +#define M33_CTIAPPSET_APPSET_BITS _u(0x0000000f) +#define M33_CTIAPPSET_APPSET_MSB _u(3) +#define M33_CTIAPPSET_APPSET_LSB _u(0) +#define M33_CTIAPPSET_APPSET_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIAPPCLEAR +// Description : CTI Application Trigger Clear Register +#define M33_CTIAPPCLEAR_OFFSET _u(0x00042018) +#define M33_CTIAPPCLEAR_BITS _u(0x0000000f) +#define M33_CTIAPPCLEAR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIAPPCLEAR_APPCLEAR +// Description : Sets the corresponding bits in the CTIAPPSET to 0. There is one +// bit of the register for each channel. +#define M33_CTIAPPCLEAR_APPCLEAR_RESET _u(0x0) +#define M33_CTIAPPCLEAR_APPCLEAR_BITS _u(0x0000000f) +#define M33_CTIAPPCLEAR_APPCLEAR_MSB _u(3) +#define M33_CTIAPPCLEAR_APPCLEAR_LSB _u(0) +#define M33_CTIAPPCLEAR_APPCLEAR_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIAPPPULSE +// Description : CTI Application Pulse Register +#define M33_CTIAPPPULSE_OFFSET _u(0x0004201c) +#define M33_CTIAPPPULSE_BITS _u(0x0000000f) +#define M33_CTIAPPPULSE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIAPPPULSE_APPULSE +// Description : Setting a bit HIGH generates a channel event pulse for the +// selected channel. There is one bit of the register for each +// channel. +#define M33_CTIAPPPULSE_APPULSE_RESET _u(0x0) +#define M33_CTIAPPPULSE_APPULSE_BITS _u(0x0000000f) +#define M33_CTIAPPPULSE_APPULSE_MSB _u(3) +#define M33_CTIAPPPULSE_APPULSE_LSB _u(0) +#define M33_CTIAPPPULSE_APPULSE_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN0 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN0_OFFSET _u(0x00042020) +#define M33_CTIINEN0_BITS _u(0x0000000f) +#define M33_CTIINEN0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN0_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN0_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN0_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN0_TRIGINEN_MSB _u(3) +#define M33_CTIINEN0_TRIGINEN_LSB _u(0) +#define M33_CTIINEN0_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN1 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN1_OFFSET _u(0x00042024) +#define M33_CTIINEN1_BITS _u(0x0000000f) +#define M33_CTIINEN1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN1_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN1_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN1_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN1_TRIGINEN_MSB _u(3) +#define M33_CTIINEN1_TRIGINEN_LSB _u(0) +#define M33_CTIINEN1_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN2 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN2_OFFSET _u(0x00042028) +#define M33_CTIINEN2_BITS _u(0x0000000f) +#define M33_CTIINEN2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN2_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN2_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN2_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN2_TRIGINEN_MSB _u(3) +#define M33_CTIINEN2_TRIGINEN_LSB _u(0) +#define M33_CTIINEN2_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN3 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN3_OFFSET _u(0x0004202c) +#define M33_CTIINEN3_BITS _u(0x0000000f) +#define M33_CTIINEN3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN3_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN3_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN3_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN3_TRIGINEN_MSB _u(3) +#define M33_CTIINEN3_TRIGINEN_LSB _u(0) +#define M33_CTIINEN3_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN4 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN4_OFFSET _u(0x00042030) +#define M33_CTIINEN4_BITS _u(0x0000000f) +#define M33_CTIINEN4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN4_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN4_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN4_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN4_TRIGINEN_MSB _u(3) +#define M33_CTIINEN4_TRIGINEN_LSB _u(0) +#define M33_CTIINEN4_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN5 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN5_OFFSET _u(0x00042034) +#define M33_CTIINEN5_BITS _u(0x0000000f) +#define M33_CTIINEN5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN5_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN5_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN5_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN5_TRIGINEN_MSB _u(3) +#define M33_CTIINEN5_TRIGINEN_LSB _u(0) +#define M33_CTIINEN5_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN6 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN6_OFFSET _u(0x00042038) +#define M33_CTIINEN6_BITS _u(0x0000000f) +#define M33_CTIINEN6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN6_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN6_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN6_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN6_TRIGINEN_MSB _u(3) +#define M33_CTIINEN6_TRIGINEN_LSB _u(0) +#define M33_CTIINEN6_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIINEN7 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIINEN7_OFFSET _u(0x0004203c) +#define M33_CTIINEN7_BITS _u(0x0000000f) +#define M33_CTIINEN7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIINEN7_TRIGINEN +// Description : Enables a cross trigger event to the corresponding channel when +// a ctitrigin input is activated. There is one bit of the field +// for each of the four channels +#define M33_CTIINEN7_TRIGINEN_RESET _u(0x0) +#define M33_CTIINEN7_TRIGINEN_BITS _u(0x0000000f) +#define M33_CTIINEN7_TRIGINEN_MSB _u(3) +#define M33_CTIINEN7_TRIGINEN_LSB _u(0) +#define M33_CTIINEN7_TRIGINEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN0 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN0_OFFSET _u(0x000420a0) +#define M33_CTIOUTEN0_BITS _u(0x0000000f) +#define M33_CTIOUTEN0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN0_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN0_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN0_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN0_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN0_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN0_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN1 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN1_OFFSET _u(0x000420a4) +#define M33_CTIOUTEN1_BITS _u(0x0000000f) +#define M33_CTIOUTEN1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN1_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN1_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN1_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN1_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN1_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN1_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN2 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN2_OFFSET _u(0x000420a8) +#define M33_CTIOUTEN2_BITS _u(0x0000000f) +#define M33_CTIOUTEN2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN2_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN2_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN2_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN2_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN2_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN2_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN3 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN3_OFFSET _u(0x000420ac) +#define M33_CTIOUTEN3_BITS _u(0x0000000f) +#define M33_CTIOUTEN3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN3_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN3_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN3_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN3_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN3_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN3_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN4 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN4_OFFSET _u(0x000420b0) +#define M33_CTIOUTEN4_BITS _u(0x0000000f) +#define M33_CTIOUTEN4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN4_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN4_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN4_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN4_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN4_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN4_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN5 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN5_OFFSET _u(0x000420b4) +#define M33_CTIOUTEN5_BITS _u(0x0000000f) +#define M33_CTIOUTEN5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN5_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN5_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN5_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN5_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN5_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN5_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN6 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN6_OFFSET _u(0x000420b8) +#define M33_CTIOUTEN6_BITS _u(0x0000000f) +#define M33_CTIOUTEN6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN6_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN6_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN6_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN6_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN6_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN6_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTIOUTEN7 +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTIOUTEN7_OFFSET _u(0x000420bc) +#define M33_CTIOUTEN7_BITS _u(0x0000000f) +#define M33_CTIOUTEN7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTIOUTEN7_TRIGOUTEN +// Description : Enables a cross trigger event to ctitrigout when the +// corresponding channel is activated. There is one bit of the +// field for each of the four channels. +#define M33_CTIOUTEN7_TRIGOUTEN_RESET _u(0x0) +#define M33_CTIOUTEN7_TRIGOUTEN_BITS _u(0x0000000f) +#define M33_CTIOUTEN7_TRIGOUTEN_MSB _u(3) +#define M33_CTIOUTEN7_TRIGOUTEN_LSB _u(0) +#define M33_CTIOUTEN7_TRIGOUTEN_ACCESS "RW" +// ============================================================================= +// Register : M33_CTITRIGINSTATUS +// Description : CTI Trigger to Channel Enable Registers +#define M33_CTITRIGINSTATUS_OFFSET _u(0x00042130) +#define M33_CTITRIGINSTATUS_BITS _u(0x000000ff) +#define M33_CTITRIGINSTATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTITRIGINSTATUS_TRIGINSTATUS +// Description : Shows the status of the ctitrigin inputs. There is one bit of +// the field for each trigger input.Because the register provides +// a view of the raw ctitrigin inputs, the reset value is UNKNOWN. +#define M33_CTITRIGINSTATUS_TRIGINSTATUS_RESET _u(0x00) +#define M33_CTITRIGINSTATUS_TRIGINSTATUS_BITS _u(0x000000ff) +#define M33_CTITRIGINSTATUS_TRIGINSTATUS_MSB _u(7) +#define M33_CTITRIGINSTATUS_TRIGINSTATUS_LSB _u(0) +#define M33_CTITRIGINSTATUS_TRIGINSTATUS_ACCESS "RO" +// ============================================================================= +// Register : M33_CTITRIGOUTSTATUS +// Description : CTI Trigger In Status Register +#define M33_CTITRIGOUTSTATUS_OFFSET _u(0x00042134) +#define M33_CTITRIGOUTSTATUS_BITS _u(0x000000ff) +#define M33_CTITRIGOUTSTATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS +// Description : Shows the status of the ctitrigout outputs. There is one bit of +// the field for each trigger output. +#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_RESET _u(0x00) +#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_BITS _u(0x000000ff) +#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_MSB _u(7) +#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_LSB _u(0) +#define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_ACCESS "RO" +// ============================================================================= +// Register : M33_CTICHINSTATUS +// Description : CTI Channel In Status Register +#define M33_CTICHINSTATUS_OFFSET _u(0x00042138) +#define M33_CTICHINSTATUS_BITS _u(0x0000000f) +#define M33_CTICHINSTATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_CTICHINSTATUS_CTICHOUTSTATUS +// Description : Shows the status of the ctichout outputs. There is one bit of +// the field for each channel output +#define M33_CTICHINSTATUS_CTICHOUTSTATUS_RESET _u(0x0) +#define M33_CTICHINSTATUS_CTICHOUTSTATUS_BITS _u(0x0000000f) +#define M33_CTICHINSTATUS_CTICHOUTSTATUS_MSB _u(3) +#define M33_CTICHINSTATUS_CTICHOUTSTATUS_LSB _u(0) +#define M33_CTICHINSTATUS_CTICHOUTSTATUS_ACCESS "RO" +// ============================================================================= +// Register : M33_CTIGATE +// Description : Enable CTI Channel Gate register +#define M33_CTIGATE_OFFSET _u(0x00042140) +#define M33_CTIGATE_BITS _u(0x0000000f) +#define M33_CTIGATE_RESET _u(0x0000000f) +// ----------------------------------------------------------------------------- +// Field : M33_CTIGATE_CTIGATEEN3 +// Description : Enable ctichout3. Set to 0 to disable channel propagation. +#define M33_CTIGATE_CTIGATEEN3_RESET _u(0x1) +#define M33_CTIGATE_CTIGATEEN3_BITS _u(0x00000008) +#define M33_CTIGATE_CTIGATEEN3_MSB _u(3) +#define M33_CTIGATE_CTIGATEEN3_LSB _u(3) +#define M33_CTIGATE_CTIGATEEN3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CTIGATE_CTIGATEEN2 +// Description : Enable ctichout2. Set to 0 to disable channel propagation. +#define M33_CTIGATE_CTIGATEEN2_RESET _u(0x1) +#define M33_CTIGATE_CTIGATEEN2_BITS _u(0x00000004) +#define M33_CTIGATE_CTIGATEEN2_MSB _u(2) +#define M33_CTIGATE_CTIGATEEN2_LSB _u(2) +#define M33_CTIGATE_CTIGATEEN2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CTIGATE_CTIGATEEN1 +// Description : Enable ctichout1. Set to 0 to disable channel propagation. +#define M33_CTIGATE_CTIGATEEN1_RESET _u(0x1) +#define M33_CTIGATE_CTIGATEEN1_BITS _u(0x00000002) +#define M33_CTIGATE_CTIGATEEN1_MSB _u(1) +#define M33_CTIGATE_CTIGATEEN1_LSB _u(1) +#define M33_CTIGATE_CTIGATEEN1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_CTIGATE_CTIGATEEN0 +// Description : Enable ctichout0. Set to 0 to disable channel propagation. +#define M33_CTIGATE_CTIGATEEN0_RESET _u(0x1) +#define M33_CTIGATE_CTIGATEEN0_BITS _u(0x00000001) +#define M33_CTIGATE_CTIGATEEN0_MSB _u(0) +#define M33_CTIGATE_CTIGATEEN0_LSB _u(0) +#define M33_CTIGATE_CTIGATEEN0_ACCESS "RW" +// ============================================================================= +// Register : M33_ASICCTL +// Description : External Multiplexer Control register +#define M33_ASICCTL_OFFSET _u(0x00042144) +#define M33_ASICCTL_BITS _u(0x00000000) +#define M33_ASICCTL_RESET _u(0x00000000) +#define M33_ASICCTL_MSB _u(31) +#define M33_ASICCTL_LSB _u(0) +#define M33_ASICCTL_ACCESS "RW" +// ============================================================================= +// Register : M33_ITCHOUT +// Description : Integration Test Channel Output register +#define M33_ITCHOUT_OFFSET _u(0x00042ee4) +#define M33_ITCHOUT_BITS _u(0x0000000f) +#define M33_ITCHOUT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITCHOUT_CTCHOUT +// Description : Sets the value of the ctichout outputs +#define M33_ITCHOUT_CTCHOUT_RESET _u(0x0) +#define M33_ITCHOUT_CTCHOUT_BITS _u(0x0000000f) +#define M33_ITCHOUT_CTCHOUT_MSB _u(3) +#define M33_ITCHOUT_CTCHOUT_LSB _u(0) +#define M33_ITCHOUT_CTCHOUT_ACCESS "RW" +// ============================================================================= +// Register : M33_ITTRIGOUT +// Description : Integration Test Trigger Output register +#define M33_ITTRIGOUT_OFFSET _u(0x00042ee8) +#define M33_ITTRIGOUT_BITS _u(0x000000ff) +#define M33_ITTRIGOUT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITTRIGOUT_CTTRIGOUT +// Description : Sets the value of the ctitrigout outputs +#define M33_ITTRIGOUT_CTTRIGOUT_RESET _u(0x00) +#define M33_ITTRIGOUT_CTTRIGOUT_BITS _u(0x000000ff) +#define M33_ITTRIGOUT_CTTRIGOUT_MSB _u(7) +#define M33_ITTRIGOUT_CTTRIGOUT_LSB _u(0) +#define M33_ITTRIGOUT_CTTRIGOUT_ACCESS "RW" +// ============================================================================= +// Register : M33_ITCHIN +// Description : Integration Test Channel Input register +#define M33_ITCHIN_OFFSET _u(0x00042ef4) +#define M33_ITCHIN_BITS _u(0x0000000f) +#define M33_ITCHIN_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITCHIN_CTCHIN +// Description : Reads the value of the ctichin inputs. +#define M33_ITCHIN_CTCHIN_RESET _u(0x0) +#define M33_ITCHIN_CTCHIN_BITS _u(0x0000000f) +#define M33_ITCHIN_CTCHIN_MSB _u(3) +#define M33_ITCHIN_CTCHIN_LSB _u(0) +#define M33_ITCHIN_CTCHIN_ACCESS "RO" +// ============================================================================= +// Register : M33_ITCTRL +// Description : Integration Mode Control register +#define M33_ITCTRL_OFFSET _u(0x00042f00) +#define M33_ITCTRL_BITS _u(0x00000001) +#define M33_ITCTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_ITCTRL_IME +// Description : Integration Mode Enable +#define M33_ITCTRL_IME_RESET _u(0x0) +#define M33_ITCTRL_IME_BITS _u(0x00000001) +#define M33_ITCTRL_IME_MSB _u(0) +#define M33_ITCTRL_IME_LSB _u(0) +#define M33_ITCTRL_IME_ACCESS "RW" +// ============================================================================= +// Register : M33_DEVARCH +// Description : Device Architecture register +#define M33_DEVARCH_OFFSET _u(0x00042fbc) +#define M33_DEVARCH_BITS _u(0xffffffff) +#define M33_DEVARCH_RESET _u(0x47701a14) +// ----------------------------------------------------------------------------- +// Field : M33_DEVARCH_ARCHITECT +// Description : Indicates the component architect +#define M33_DEVARCH_ARCHITECT_RESET _u(0x23b) +#define M33_DEVARCH_ARCHITECT_BITS _u(0xffe00000) +#define M33_DEVARCH_ARCHITECT_MSB _u(31) +#define M33_DEVARCH_ARCHITECT_LSB _u(21) +#define M33_DEVARCH_ARCHITECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DEVARCH_PRESENT +// Description : Indicates whether the DEVARCH register is present +#define M33_DEVARCH_PRESENT_RESET _u(0x1) +#define M33_DEVARCH_PRESENT_BITS _u(0x00100000) +#define M33_DEVARCH_PRESENT_MSB _u(20) +#define M33_DEVARCH_PRESENT_LSB _u(20) +#define M33_DEVARCH_PRESENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DEVARCH_REVISION +// Description : Indicates the architecture revision +#define M33_DEVARCH_REVISION_RESET _u(0x0) +#define M33_DEVARCH_REVISION_BITS _u(0x000f0000) +#define M33_DEVARCH_REVISION_MSB _u(19) +#define M33_DEVARCH_REVISION_LSB _u(16) +#define M33_DEVARCH_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DEVARCH_ARCHID +// Description : Indicates the component +#define M33_DEVARCH_ARCHID_RESET _u(0x1a14) +#define M33_DEVARCH_ARCHID_BITS _u(0x0000ffff) +#define M33_DEVARCH_ARCHID_MSB _u(15) +#define M33_DEVARCH_ARCHID_LSB _u(0) +#define M33_DEVARCH_ARCHID_ACCESS "RO" +// ============================================================================= +// Register : M33_DEVID +// Description : Device Configuration register +#define M33_DEVID_OFFSET _u(0x00042fc8) +#define M33_DEVID_BITS _u(0x000fff1f) +#define M33_DEVID_RESET _u(0x00040800) +// ----------------------------------------------------------------------------- +// Field : M33_DEVID_NUMCH +// Description : Number of ECT channels available +#define M33_DEVID_NUMCH_RESET _u(0x4) +#define M33_DEVID_NUMCH_BITS _u(0x000f0000) +#define M33_DEVID_NUMCH_MSB _u(19) +#define M33_DEVID_NUMCH_LSB _u(16) +#define M33_DEVID_NUMCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DEVID_NUMTRIG +// Description : Number of ECT triggers available. +#define M33_DEVID_NUMTRIG_RESET _u(0x08) +#define M33_DEVID_NUMTRIG_BITS _u(0x0000ff00) +#define M33_DEVID_NUMTRIG_MSB _u(15) +#define M33_DEVID_NUMTRIG_LSB _u(8) +#define M33_DEVID_NUMTRIG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DEVID_EXTMUXNUM +// Description : Indicates the number of multiplexers available on Trigger +// Inputs and Trigger Outputs that are using asicctl. The default +// value of 0b00000 indicates that no multiplexing is present. +// This value of this bit depends on the Verilog define EXTMUXNUM +// that you must change accordingly. +#define M33_DEVID_EXTMUXNUM_RESET _u(0x00) +#define M33_DEVID_EXTMUXNUM_BITS _u(0x0000001f) +#define M33_DEVID_EXTMUXNUM_MSB _u(4) +#define M33_DEVID_EXTMUXNUM_LSB _u(0) +#define M33_DEVID_EXTMUXNUM_ACCESS "RO" +// ============================================================================= +// Register : M33_DEVTYPE +// Description : Device Type Identifier register +#define M33_DEVTYPE_OFFSET _u(0x00042fcc) +#define M33_DEVTYPE_BITS _u(0x000000ff) +#define M33_DEVTYPE_RESET _u(0x00000014) +// ----------------------------------------------------------------------------- +// Field : M33_DEVTYPE_SUB +// Description : Sub-classification of the type of the debug component as +// specified in the ARM Architecture Specification within the +// major classification as specified in the MAJOR field. +#define M33_DEVTYPE_SUB_RESET _u(0x1) +#define M33_DEVTYPE_SUB_BITS _u(0x000000f0) +#define M33_DEVTYPE_SUB_MSB _u(7) +#define M33_DEVTYPE_SUB_LSB _u(4) +#define M33_DEVTYPE_SUB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_DEVTYPE_MAJOR +// Description : Major classification of the type of the debug component as +// specified in the ARM Architecture Specification for this debug +// and trace component. +#define M33_DEVTYPE_MAJOR_RESET _u(0x4) +#define M33_DEVTYPE_MAJOR_BITS _u(0x0000000f) +#define M33_DEVTYPE_MAJOR_MSB _u(3) +#define M33_DEVTYPE_MAJOR_LSB _u(0) +#define M33_DEVTYPE_MAJOR_ACCESS "RO" +// ============================================================================= +// Register : M33_PIDR4 +// Description : CoreSight Peripheral ID4 +#define M33_PIDR4_OFFSET _u(0x00042fd0) +#define M33_PIDR4_BITS _u(0x000000ff) +#define M33_PIDR4_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : M33_PIDR4_SIZE +// Description : Always 0b0000. Indicates that the device only occupies 4KB of +// memory +#define M33_PIDR4_SIZE_RESET _u(0x0) +#define M33_PIDR4_SIZE_BITS _u(0x000000f0) +#define M33_PIDR4_SIZE_MSB _u(7) +#define M33_PIDR4_SIZE_LSB _u(4) +#define M33_PIDR4_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_PIDR4_DES_2 +// Description : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify +// the designer of the component. +#define M33_PIDR4_DES_2_RESET _u(0x4) +#define M33_PIDR4_DES_2_BITS _u(0x0000000f) +#define M33_PIDR4_DES_2_MSB _u(3) +#define M33_PIDR4_DES_2_LSB _u(0) +#define M33_PIDR4_DES_2_ACCESS "RO" +// ============================================================================= +// Register : M33_PIDR5 +// Description : CoreSight Peripheral ID5 +#define M33_PIDR5_OFFSET _u(0x00042fd4) +#define M33_PIDR5_BITS _u(0x00000000) +#define M33_PIDR5_RESET _u(0x00000000) +#define M33_PIDR5_MSB _u(31) +#define M33_PIDR5_LSB _u(0) +#define M33_PIDR5_ACCESS "RW" +// ============================================================================= +// Register : M33_PIDR6 +// Description : CoreSight Peripheral ID6 +#define M33_PIDR6_OFFSET _u(0x00042fd8) +#define M33_PIDR6_BITS _u(0x00000000) +#define M33_PIDR6_RESET _u(0x00000000) +#define M33_PIDR6_MSB _u(31) +#define M33_PIDR6_LSB _u(0) +#define M33_PIDR6_ACCESS "RW" +// ============================================================================= +// Register : M33_PIDR7 +// Description : CoreSight Peripheral ID7 +#define M33_PIDR7_OFFSET _u(0x00042fdc) +#define M33_PIDR7_BITS _u(0x00000000) +#define M33_PIDR7_RESET _u(0x00000000) +#define M33_PIDR7_MSB _u(31) +#define M33_PIDR7_LSB _u(0) +#define M33_PIDR7_ACCESS "RW" +// ============================================================================= +// Register : M33_PIDR0 +// Description : CoreSight Peripheral ID0 +#define M33_PIDR0_OFFSET _u(0x00042fe0) +#define M33_PIDR0_BITS _u(0x000000ff) +#define M33_PIDR0_RESET _u(0x00000021) +// ----------------------------------------------------------------------------- +// Field : M33_PIDR0_PART_0 +// Description : Bits[7:0] of the 12-bit part number of the component. The +// designer of the component assigns this part number. +#define M33_PIDR0_PART_0_RESET _u(0x21) +#define M33_PIDR0_PART_0_BITS _u(0x000000ff) +#define M33_PIDR0_PART_0_MSB _u(7) +#define M33_PIDR0_PART_0_LSB _u(0) +#define M33_PIDR0_PART_0_ACCESS "RO" +// ============================================================================= +// Register : M33_PIDR1 +// Description : CoreSight Peripheral ID1 +#define M33_PIDR1_OFFSET _u(0x00042fe4) +#define M33_PIDR1_BITS _u(0x000000ff) +#define M33_PIDR1_RESET _u(0x000000bd) +// ----------------------------------------------------------------------------- +// Field : M33_PIDR1_DES_0 +// Description : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify +// the designer of the component. +#define M33_PIDR1_DES_0_RESET _u(0xb) +#define M33_PIDR1_DES_0_BITS _u(0x000000f0) +#define M33_PIDR1_DES_0_MSB _u(7) +#define M33_PIDR1_DES_0_LSB _u(4) +#define M33_PIDR1_DES_0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_PIDR1_PART_1 +// Description : Bits[11:8] of the 12-bit part number of the component. The +// designer of the component assigns this part number. +#define M33_PIDR1_PART_1_RESET _u(0xd) +#define M33_PIDR1_PART_1_BITS _u(0x0000000f) +#define M33_PIDR1_PART_1_MSB _u(3) +#define M33_PIDR1_PART_1_LSB _u(0) +#define M33_PIDR1_PART_1_ACCESS "RO" +// ============================================================================= +// Register : M33_PIDR2 +// Description : CoreSight Peripheral ID2 +#define M33_PIDR2_OFFSET _u(0x00042fe8) +#define M33_PIDR2_BITS _u(0x000000ff) +#define M33_PIDR2_RESET _u(0x0000000b) +// ----------------------------------------------------------------------------- +// Field : M33_PIDR2_REVISION +// Description : This device is at r1p0 +#define M33_PIDR2_REVISION_RESET _u(0x0) +#define M33_PIDR2_REVISION_BITS _u(0x000000f0) +#define M33_PIDR2_REVISION_MSB _u(7) +#define M33_PIDR2_REVISION_LSB _u(4) +#define M33_PIDR2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_PIDR2_JEDEC +// Description : Always 1. Indicates that the JEDEC-assigned designer ID is +// used. +#define M33_PIDR2_JEDEC_RESET _u(0x1) +#define M33_PIDR2_JEDEC_BITS _u(0x00000008) +#define M33_PIDR2_JEDEC_MSB _u(3) +#define M33_PIDR2_JEDEC_LSB _u(3) +#define M33_PIDR2_JEDEC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_PIDR2_DES_1 +// Description : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify +// the designer of the component. +#define M33_PIDR2_DES_1_RESET _u(0x3) +#define M33_PIDR2_DES_1_BITS _u(0x00000007) +#define M33_PIDR2_DES_1_MSB _u(2) +#define M33_PIDR2_DES_1_LSB _u(0) +#define M33_PIDR2_DES_1_ACCESS "RO" +// ============================================================================= +// Register : M33_PIDR3 +// Description : CoreSight Peripheral ID3 +#define M33_PIDR3_OFFSET _u(0x00042fec) +#define M33_PIDR3_BITS _u(0x000000ff) +#define M33_PIDR3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : M33_PIDR3_REVAND +// Description : Indicates minor errata fixes specific to the revision of the +// component being used, for example metal fixes after +// implementation. In most cases, this field is 0b0000. ARM +// recommends that the component designers ensure that a metal fix +// can change this field if required, for example, by driving it +// from registers that reset to 0b0000. +#define M33_PIDR3_REVAND_RESET _u(0x0) +#define M33_PIDR3_REVAND_BITS _u(0x000000f0) +#define M33_PIDR3_REVAND_MSB _u(7) +#define M33_PIDR3_REVAND_LSB _u(4) +#define M33_PIDR3_REVAND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_PIDR3_CMOD +// Description : Customer Modified. Indicates whether the customer has modified +// the behavior of the component. In most cases, this field is +// 0b0000. Customers change this value when they make authorized +// modifications to this component. +#define M33_PIDR3_CMOD_RESET _u(0x0) +#define M33_PIDR3_CMOD_BITS _u(0x0000000f) +#define M33_PIDR3_CMOD_MSB _u(3) +#define M33_PIDR3_CMOD_LSB _u(0) +#define M33_PIDR3_CMOD_ACCESS "RO" +// ============================================================================= +// Register : M33_CIDR0 +// Description : CoreSight Component ID0 +#define M33_CIDR0_OFFSET _u(0x00042ff0) +#define M33_CIDR0_BITS _u(0x000000ff) +#define M33_CIDR0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : M33_CIDR0_PRMBL_0 +// Description : Preamble[0]. Contains bits[7:0] of the component identification +// code +#define M33_CIDR0_PRMBL_0_RESET _u(0x0d) +#define M33_CIDR0_PRMBL_0_BITS _u(0x000000ff) +#define M33_CIDR0_PRMBL_0_MSB _u(7) +#define M33_CIDR0_PRMBL_0_LSB _u(0) +#define M33_CIDR0_PRMBL_0_ACCESS "RO" +// ============================================================================= +// Register : M33_CIDR1 +// Description : CoreSight Component ID1 +#define M33_CIDR1_OFFSET _u(0x00042ff4) +#define M33_CIDR1_BITS _u(0x000000ff) +#define M33_CIDR1_RESET _u(0x00000090) +// ----------------------------------------------------------------------------- +// Field : M33_CIDR1_CLASS +// Description : Class of the component, for example, whether the component is a +// ROM table or a generic CoreSight component. Contains +// bits[15:12] of the component identification code. +#define M33_CIDR1_CLASS_RESET _u(0x9) +#define M33_CIDR1_CLASS_BITS _u(0x000000f0) +#define M33_CIDR1_CLASS_MSB _u(7) +#define M33_CIDR1_CLASS_LSB _u(4) +#define M33_CIDR1_CLASS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_CIDR1_PRMBL_1 +// Description : Preamble[1]. Contains bits[11:8] of the component +// identification code. +#define M33_CIDR1_PRMBL_1_RESET _u(0x0) +#define M33_CIDR1_PRMBL_1_BITS _u(0x0000000f) +#define M33_CIDR1_PRMBL_1_MSB _u(3) +#define M33_CIDR1_PRMBL_1_LSB _u(0) +#define M33_CIDR1_PRMBL_1_ACCESS "RO" +// ============================================================================= +// Register : M33_CIDR2 +// Description : CoreSight Component ID2 +#define M33_CIDR2_OFFSET _u(0x00042ff8) +#define M33_CIDR2_BITS _u(0x000000ff) +#define M33_CIDR2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : M33_CIDR2_PRMBL_2 +// Description : Preamble[2]. Contains bits[23:16] of the component +// identification code. +#define M33_CIDR2_PRMBL_2_RESET _u(0x05) +#define M33_CIDR2_PRMBL_2_BITS _u(0x000000ff) +#define M33_CIDR2_PRMBL_2_MSB _u(7) +#define M33_CIDR2_PRMBL_2_LSB _u(0) +#define M33_CIDR2_PRMBL_2_ACCESS "RO" +// ============================================================================= +// Register : M33_CIDR3 +// Description : CoreSight Component ID3 +#define M33_CIDR3_OFFSET _u(0x00042ffc) +#define M33_CIDR3_BITS _u(0x000000ff) +#define M33_CIDR3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : M33_CIDR3_PRMBL_3 +// Description : Preamble[3]. Contains bits[31:24] of the component +// identification code. +#define M33_CIDR3_PRMBL_3_RESET _u(0xb1) +#define M33_CIDR3_PRMBL_3_BITS _u(0x000000ff) +#define M33_CIDR3_PRMBL_3_MSB _u(7) +#define M33_CIDR3_PRMBL_3_LSB _u(0) +#define M33_CIDR3_PRMBL_3_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_M33_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/m33_eppb.h b/lib/pico-sdk/rp2350/hardware/regs/m33_eppb.h new file mode 100644 index 000000000000..93b5143b2c3c --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/m33_eppb.h @@ -0,0 +1,80 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : M33_EPPB +// Version : 1 +// Bus type : apb +// Description : Cortex-M33 EPPB vendor register block for RP2350 +// ============================================================================= +#ifndef _HARDWARE_REGS_M33_EPPB_H +#define _HARDWARE_REGS_M33_EPPB_H +// ============================================================================= +// Register : M33_EPPB_NMI_MASK0 +// Description : NMI mask for IRQs 0 through 31. This register is core-local, +// and is reset by a processor warm reset. +#define M33_EPPB_NMI_MASK0_OFFSET _u(0x00000000) +#define M33_EPPB_NMI_MASK0_BITS _u(0xffffffff) +#define M33_EPPB_NMI_MASK0_RESET _u(0x00000000) +#define M33_EPPB_NMI_MASK0_MSB _u(31) +#define M33_EPPB_NMI_MASK0_LSB _u(0) +#define M33_EPPB_NMI_MASK0_ACCESS "RW" +// ============================================================================= +// Register : M33_EPPB_NMI_MASK1 +// Description : NMI mask for IRQs 0 though 51. This register is core-local, and +// is reset by a processor warm reset. +#define M33_EPPB_NMI_MASK1_OFFSET _u(0x00000004) +#define M33_EPPB_NMI_MASK1_BITS _u(0x000fffff) +#define M33_EPPB_NMI_MASK1_RESET _u(0x00000000) +#define M33_EPPB_NMI_MASK1_MSB _u(19) +#define M33_EPPB_NMI_MASK1_LSB _u(0) +#define M33_EPPB_NMI_MASK1_ACCESS "RW" +// ============================================================================= +// Register : M33_EPPB_SLEEPCTRL +// Description : Nonstandard sleep control register +#define M33_EPPB_SLEEPCTRL_OFFSET _u(0x00000008) +#define M33_EPPB_SLEEPCTRL_BITS _u(0x00000007) +#define M33_EPPB_SLEEPCTRL_RESET _u(0x00000002) +// ----------------------------------------------------------------------------- +// Field : M33_EPPB_SLEEPCTRL_WICENACK +// Description : Status signal from the processor's interrupt controller. +// Changes to WICENREQ are eventually reflected in WICENACK. +#define M33_EPPB_SLEEPCTRL_WICENACK_RESET _u(0x0) +#define M33_EPPB_SLEEPCTRL_WICENACK_BITS _u(0x00000004) +#define M33_EPPB_SLEEPCTRL_WICENACK_MSB _u(2) +#define M33_EPPB_SLEEPCTRL_WICENACK_LSB _u(2) +#define M33_EPPB_SLEEPCTRL_WICENACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : M33_EPPB_SLEEPCTRL_WICENREQ +// Description : Request that the next processor deep sleep is a WIC sleep. +// After setting this bit, before sleeping, poll WICENACK to +// ensure the processor interrupt controller has acknowledged the +// change. +#define M33_EPPB_SLEEPCTRL_WICENREQ_RESET _u(0x1) +#define M33_EPPB_SLEEPCTRL_WICENREQ_BITS _u(0x00000002) +#define M33_EPPB_SLEEPCTRL_WICENREQ_MSB _u(1) +#define M33_EPPB_SLEEPCTRL_WICENREQ_LSB _u(1) +#define M33_EPPB_SLEEPCTRL_WICENREQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : M33_EPPB_SLEEPCTRL_LIGHT_SLEEP +// Description : By default, any processor sleep will deassert the system-level +// clock request. Reenabling the clocks incurs 5 cycles of +// additional latency on wakeup. +// +// Setting LIGHT_SLEEP to 1 keeps the clock request asserted +// during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster +// wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not +// affected, and will always deassert the system-level clock +// request. +#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_RESET _u(0x0) +#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_BITS _u(0x00000001) +#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_MSB _u(0) +#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_LSB _u(0) +#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_M33_EPPB_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/otp.h b/lib/pico-sdk/rp2350/hardware/regs/otp.h new file mode 100644 index 000000000000..cd9c6e85e2c3 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/otp.h @@ -0,0 +1,3467 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : OTP +// Version : 1 +// Bus type : apb +// Description : SNPS OTP control IF (SBPI and RPi wrapper control) +// ============================================================================= +#ifndef _HARDWARE_REGS_OTP_H +#define _HARDWARE_REGS_OTP_H +// ============================================================================= +// Register : OTP_SW_LOCK0 +// Description : Software lock register for page 0. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK0_OFFSET _u(0x00000000) +#define OTP_SW_LOCK0_BITS _u(0x0000000f) +#define OTP_SW_LOCK0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK0_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK0_NSEC_RESET "-" +#define OTP_SW_LOCK0_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK0_NSEC_MSB _u(3) +#define OTP_SW_LOCK0_NSEC_LSB _u(2) +#define OTP_SW_LOCK0_NSEC_ACCESS "RW" +#define OTP_SW_LOCK0_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK0_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK0_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK0_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK0_SEC_RESET "-" +#define OTP_SW_LOCK0_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK0_SEC_MSB _u(1) +#define OTP_SW_LOCK0_SEC_LSB _u(0) +#define OTP_SW_LOCK0_SEC_ACCESS "RW" +#define OTP_SW_LOCK0_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK0_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK0_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK1 +// Description : Software lock register for page 1. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK1_OFFSET _u(0x00000004) +#define OTP_SW_LOCK1_BITS _u(0x0000000f) +#define OTP_SW_LOCK1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK1_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK1_NSEC_RESET "-" +#define OTP_SW_LOCK1_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK1_NSEC_MSB _u(3) +#define OTP_SW_LOCK1_NSEC_LSB _u(2) +#define OTP_SW_LOCK1_NSEC_ACCESS "RW" +#define OTP_SW_LOCK1_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK1_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK1_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK1_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK1_SEC_RESET "-" +#define OTP_SW_LOCK1_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK1_SEC_MSB _u(1) +#define OTP_SW_LOCK1_SEC_LSB _u(0) +#define OTP_SW_LOCK1_SEC_ACCESS "RW" +#define OTP_SW_LOCK1_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK1_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK1_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK2 +// Description : Software lock register for page 2. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK2_OFFSET _u(0x00000008) +#define OTP_SW_LOCK2_BITS _u(0x0000000f) +#define OTP_SW_LOCK2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK2_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK2_NSEC_RESET "-" +#define OTP_SW_LOCK2_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK2_NSEC_MSB _u(3) +#define OTP_SW_LOCK2_NSEC_LSB _u(2) +#define OTP_SW_LOCK2_NSEC_ACCESS "RW" +#define OTP_SW_LOCK2_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK2_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK2_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK2_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK2_SEC_RESET "-" +#define OTP_SW_LOCK2_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK2_SEC_MSB _u(1) +#define OTP_SW_LOCK2_SEC_LSB _u(0) +#define OTP_SW_LOCK2_SEC_ACCESS "RW" +#define OTP_SW_LOCK2_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK2_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK2_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK3 +// Description : Software lock register for page 3. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK3_OFFSET _u(0x0000000c) +#define OTP_SW_LOCK3_BITS _u(0x0000000f) +#define OTP_SW_LOCK3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK3_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK3_NSEC_RESET "-" +#define OTP_SW_LOCK3_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK3_NSEC_MSB _u(3) +#define OTP_SW_LOCK3_NSEC_LSB _u(2) +#define OTP_SW_LOCK3_NSEC_ACCESS "RW" +#define OTP_SW_LOCK3_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK3_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK3_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK3_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK3_SEC_RESET "-" +#define OTP_SW_LOCK3_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK3_SEC_MSB _u(1) +#define OTP_SW_LOCK3_SEC_LSB _u(0) +#define OTP_SW_LOCK3_SEC_ACCESS "RW" +#define OTP_SW_LOCK3_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK3_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK3_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK4 +// Description : Software lock register for page 4. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK4_OFFSET _u(0x00000010) +#define OTP_SW_LOCK4_BITS _u(0x0000000f) +#define OTP_SW_LOCK4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK4_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK4_NSEC_RESET "-" +#define OTP_SW_LOCK4_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK4_NSEC_MSB _u(3) +#define OTP_SW_LOCK4_NSEC_LSB _u(2) +#define OTP_SW_LOCK4_NSEC_ACCESS "RW" +#define OTP_SW_LOCK4_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK4_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK4_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK4_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK4_SEC_RESET "-" +#define OTP_SW_LOCK4_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK4_SEC_MSB _u(1) +#define OTP_SW_LOCK4_SEC_LSB _u(0) +#define OTP_SW_LOCK4_SEC_ACCESS "RW" +#define OTP_SW_LOCK4_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK4_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK4_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK5 +// Description : Software lock register for page 5. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK5_OFFSET _u(0x00000014) +#define OTP_SW_LOCK5_BITS _u(0x0000000f) +#define OTP_SW_LOCK5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK5_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK5_NSEC_RESET "-" +#define OTP_SW_LOCK5_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK5_NSEC_MSB _u(3) +#define OTP_SW_LOCK5_NSEC_LSB _u(2) +#define OTP_SW_LOCK5_NSEC_ACCESS "RW" +#define OTP_SW_LOCK5_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK5_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK5_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK5_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK5_SEC_RESET "-" +#define OTP_SW_LOCK5_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK5_SEC_MSB _u(1) +#define OTP_SW_LOCK5_SEC_LSB _u(0) +#define OTP_SW_LOCK5_SEC_ACCESS "RW" +#define OTP_SW_LOCK5_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK5_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK5_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK6 +// Description : Software lock register for page 6. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK6_OFFSET _u(0x00000018) +#define OTP_SW_LOCK6_BITS _u(0x0000000f) +#define OTP_SW_LOCK6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK6_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK6_NSEC_RESET "-" +#define OTP_SW_LOCK6_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK6_NSEC_MSB _u(3) +#define OTP_SW_LOCK6_NSEC_LSB _u(2) +#define OTP_SW_LOCK6_NSEC_ACCESS "RW" +#define OTP_SW_LOCK6_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK6_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK6_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK6_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK6_SEC_RESET "-" +#define OTP_SW_LOCK6_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK6_SEC_MSB _u(1) +#define OTP_SW_LOCK6_SEC_LSB _u(0) +#define OTP_SW_LOCK6_SEC_ACCESS "RW" +#define OTP_SW_LOCK6_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK6_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK6_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK7 +// Description : Software lock register for page 7. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK7_OFFSET _u(0x0000001c) +#define OTP_SW_LOCK7_BITS _u(0x0000000f) +#define OTP_SW_LOCK7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK7_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK7_NSEC_RESET "-" +#define OTP_SW_LOCK7_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK7_NSEC_MSB _u(3) +#define OTP_SW_LOCK7_NSEC_LSB _u(2) +#define OTP_SW_LOCK7_NSEC_ACCESS "RW" +#define OTP_SW_LOCK7_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK7_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK7_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK7_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK7_SEC_RESET "-" +#define OTP_SW_LOCK7_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK7_SEC_MSB _u(1) +#define OTP_SW_LOCK7_SEC_LSB _u(0) +#define OTP_SW_LOCK7_SEC_ACCESS "RW" +#define OTP_SW_LOCK7_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK7_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK7_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK8 +// Description : Software lock register for page 8. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK8_OFFSET _u(0x00000020) +#define OTP_SW_LOCK8_BITS _u(0x0000000f) +#define OTP_SW_LOCK8_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK8_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK8_NSEC_RESET "-" +#define OTP_SW_LOCK8_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK8_NSEC_MSB _u(3) +#define OTP_SW_LOCK8_NSEC_LSB _u(2) +#define OTP_SW_LOCK8_NSEC_ACCESS "RW" +#define OTP_SW_LOCK8_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK8_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK8_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK8_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK8_SEC_RESET "-" +#define OTP_SW_LOCK8_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK8_SEC_MSB _u(1) +#define OTP_SW_LOCK8_SEC_LSB _u(0) +#define OTP_SW_LOCK8_SEC_ACCESS "RW" +#define OTP_SW_LOCK8_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK8_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK8_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK9 +// Description : Software lock register for page 9. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK9_OFFSET _u(0x00000024) +#define OTP_SW_LOCK9_BITS _u(0x0000000f) +#define OTP_SW_LOCK9_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK9_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK9_NSEC_RESET "-" +#define OTP_SW_LOCK9_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK9_NSEC_MSB _u(3) +#define OTP_SW_LOCK9_NSEC_LSB _u(2) +#define OTP_SW_LOCK9_NSEC_ACCESS "RW" +#define OTP_SW_LOCK9_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK9_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK9_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK9_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK9_SEC_RESET "-" +#define OTP_SW_LOCK9_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK9_SEC_MSB _u(1) +#define OTP_SW_LOCK9_SEC_LSB _u(0) +#define OTP_SW_LOCK9_SEC_ACCESS "RW" +#define OTP_SW_LOCK9_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK9_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK9_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK10 +// Description : Software lock register for page 10. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK10_OFFSET _u(0x00000028) +#define OTP_SW_LOCK10_BITS _u(0x0000000f) +#define OTP_SW_LOCK10_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK10_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK10_NSEC_RESET "-" +#define OTP_SW_LOCK10_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK10_NSEC_MSB _u(3) +#define OTP_SW_LOCK10_NSEC_LSB _u(2) +#define OTP_SW_LOCK10_NSEC_ACCESS "RW" +#define OTP_SW_LOCK10_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK10_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK10_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK10_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK10_SEC_RESET "-" +#define OTP_SW_LOCK10_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK10_SEC_MSB _u(1) +#define OTP_SW_LOCK10_SEC_LSB _u(0) +#define OTP_SW_LOCK10_SEC_ACCESS "RW" +#define OTP_SW_LOCK10_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK10_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK10_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK11 +// Description : Software lock register for page 11. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK11_OFFSET _u(0x0000002c) +#define OTP_SW_LOCK11_BITS _u(0x0000000f) +#define OTP_SW_LOCK11_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK11_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK11_NSEC_RESET "-" +#define OTP_SW_LOCK11_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK11_NSEC_MSB _u(3) +#define OTP_SW_LOCK11_NSEC_LSB _u(2) +#define OTP_SW_LOCK11_NSEC_ACCESS "RW" +#define OTP_SW_LOCK11_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK11_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK11_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK11_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK11_SEC_RESET "-" +#define OTP_SW_LOCK11_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK11_SEC_MSB _u(1) +#define OTP_SW_LOCK11_SEC_LSB _u(0) +#define OTP_SW_LOCK11_SEC_ACCESS "RW" +#define OTP_SW_LOCK11_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK11_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK11_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK12 +// Description : Software lock register for page 12. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK12_OFFSET _u(0x00000030) +#define OTP_SW_LOCK12_BITS _u(0x0000000f) +#define OTP_SW_LOCK12_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK12_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK12_NSEC_RESET "-" +#define OTP_SW_LOCK12_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK12_NSEC_MSB _u(3) +#define OTP_SW_LOCK12_NSEC_LSB _u(2) +#define OTP_SW_LOCK12_NSEC_ACCESS "RW" +#define OTP_SW_LOCK12_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK12_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK12_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK12_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK12_SEC_RESET "-" +#define OTP_SW_LOCK12_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK12_SEC_MSB _u(1) +#define OTP_SW_LOCK12_SEC_LSB _u(0) +#define OTP_SW_LOCK12_SEC_ACCESS "RW" +#define OTP_SW_LOCK12_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK12_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK12_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK13 +// Description : Software lock register for page 13. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK13_OFFSET _u(0x00000034) +#define OTP_SW_LOCK13_BITS _u(0x0000000f) +#define OTP_SW_LOCK13_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK13_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK13_NSEC_RESET "-" +#define OTP_SW_LOCK13_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK13_NSEC_MSB _u(3) +#define OTP_SW_LOCK13_NSEC_LSB _u(2) +#define OTP_SW_LOCK13_NSEC_ACCESS "RW" +#define OTP_SW_LOCK13_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK13_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK13_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK13_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK13_SEC_RESET "-" +#define OTP_SW_LOCK13_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK13_SEC_MSB _u(1) +#define OTP_SW_LOCK13_SEC_LSB _u(0) +#define OTP_SW_LOCK13_SEC_ACCESS "RW" +#define OTP_SW_LOCK13_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK13_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK13_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK14 +// Description : Software lock register for page 14. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK14_OFFSET _u(0x00000038) +#define OTP_SW_LOCK14_BITS _u(0x0000000f) +#define OTP_SW_LOCK14_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK14_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK14_NSEC_RESET "-" +#define OTP_SW_LOCK14_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK14_NSEC_MSB _u(3) +#define OTP_SW_LOCK14_NSEC_LSB _u(2) +#define OTP_SW_LOCK14_NSEC_ACCESS "RW" +#define OTP_SW_LOCK14_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK14_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK14_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK14_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK14_SEC_RESET "-" +#define OTP_SW_LOCK14_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK14_SEC_MSB _u(1) +#define OTP_SW_LOCK14_SEC_LSB _u(0) +#define OTP_SW_LOCK14_SEC_ACCESS "RW" +#define OTP_SW_LOCK14_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK14_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK14_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK15 +// Description : Software lock register for page 15. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK15_OFFSET _u(0x0000003c) +#define OTP_SW_LOCK15_BITS _u(0x0000000f) +#define OTP_SW_LOCK15_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK15_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK15_NSEC_RESET "-" +#define OTP_SW_LOCK15_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK15_NSEC_MSB _u(3) +#define OTP_SW_LOCK15_NSEC_LSB _u(2) +#define OTP_SW_LOCK15_NSEC_ACCESS "RW" +#define OTP_SW_LOCK15_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK15_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK15_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK15_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK15_SEC_RESET "-" +#define OTP_SW_LOCK15_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK15_SEC_MSB _u(1) +#define OTP_SW_LOCK15_SEC_LSB _u(0) +#define OTP_SW_LOCK15_SEC_ACCESS "RW" +#define OTP_SW_LOCK15_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK15_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK15_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK16 +// Description : Software lock register for page 16. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK16_OFFSET _u(0x00000040) +#define OTP_SW_LOCK16_BITS _u(0x0000000f) +#define OTP_SW_LOCK16_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK16_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK16_NSEC_RESET "-" +#define OTP_SW_LOCK16_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK16_NSEC_MSB _u(3) +#define OTP_SW_LOCK16_NSEC_LSB _u(2) +#define OTP_SW_LOCK16_NSEC_ACCESS "RW" +#define OTP_SW_LOCK16_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK16_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK16_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK16_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK16_SEC_RESET "-" +#define OTP_SW_LOCK16_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK16_SEC_MSB _u(1) +#define OTP_SW_LOCK16_SEC_LSB _u(0) +#define OTP_SW_LOCK16_SEC_ACCESS "RW" +#define OTP_SW_LOCK16_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK16_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK16_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK17 +// Description : Software lock register for page 17. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK17_OFFSET _u(0x00000044) +#define OTP_SW_LOCK17_BITS _u(0x0000000f) +#define OTP_SW_LOCK17_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK17_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK17_NSEC_RESET "-" +#define OTP_SW_LOCK17_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK17_NSEC_MSB _u(3) +#define OTP_SW_LOCK17_NSEC_LSB _u(2) +#define OTP_SW_LOCK17_NSEC_ACCESS "RW" +#define OTP_SW_LOCK17_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK17_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK17_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK17_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK17_SEC_RESET "-" +#define OTP_SW_LOCK17_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK17_SEC_MSB _u(1) +#define OTP_SW_LOCK17_SEC_LSB _u(0) +#define OTP_SW_LOCK17_SEC_ACCESS "RW" +#define OTP_SW_LOCK17_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK17_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK17_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK18 +// Description : Software lock register for page 18. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK18_OFFSET _u(0x00000048) +#define OTP_SW_LOCK18_BITS _u(0x0000000f) +#define OTP_SW_LOCK18_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK18_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK18_NSEC_RESET "-" +#define OTP_SW_LOCK18_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK18_NSEC_MSB _u(3) +#define OTP_SW_LOCK18_NSEC_LSB _u(2) +#define OTP_SW_LOCK18_NSEC_ACCESS "RW" +#define OTP_SW_LOCK18_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK18_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK18_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK18_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK18_SEC_RESET "-" +#define OTP_SW_LOCK18_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK18_SEC_MSB _u(1) +#define OTP_SW_LOCK18_SEC_LSB _u(0) +#define OTP_SW_LOCK18_SEC_ACCESS "RW" +#define OTP_SW_LOCK18_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK18_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK18_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK19 +// Description : Software lock register for page 19. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK19_OFFSET _u(0x0000004c) +#define OTP_SW_LOCK19_BITS _u(0x0000000f) +#define OTP_SW_LOCK19_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK19_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK19_NSEC_RESET "-" +#define OTP_SW_LOCK19_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK19_NSEC_MSB _u(3) +#define OTP_SW_LOCK19_NSEC_LSB _u(2) +#define OTP_SW_LOCK19_NSEC_ACCESS "RW" +#define OTP_SW_LOCK19_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK19_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK19_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK19_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK19_SEC_RESET "-" +#define OTP_SW_LOCK19_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK19_SEC_MSB _u(1) +#define OTP_SW_LOCK19_SEC_LSB _u(0) +#define OTP_SW_LOCK19_SEC_ACCESS "RW" +#define OTP_SW_LOCK19_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK19_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK19_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK20 +// Description : Software lock register for page 20. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK20_OFFSET _u(0x00000050) +#define OTP_SW_LOCK20_BITS _u(0x0000000f) +#define OTP_SW_LOCK20_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK20_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK20_NSEC_RESET "-" +#define OTP_SW_LOCK20_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK20_NSEC_MSB _u(3) +#define OTP_SW_LOCK20_NSEC_LSB _u(2) +#define OTP_SW_LOCK20_NSEC_ACCESS "RW" +#define OTP_SW_LOCK20_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK20_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK20_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK20_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK20_SEC_RESET "-" +#define OTP_SW_LOCK20_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK20_SEC_MSB _u(1) +#define OTP_SW_LOCK20_SEC_LSB _u(0) +#define OTP_SW_LOCK20_SEC_ACCESS "RW" +#define OTP_SW_LOCK20_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK20_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK20_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK21 +// Description : Software lock register for page 21. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK21_OFFSET _u(0x00000054) +#define OTP_SW_LOCK21_BITS _u(0x0000000f) +#define OTP_SW_LOCK21_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK21_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK21_NSEC_RESET "-" +#define OTP_SW_LOCK21_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK21_NSEC_MSB _u(3) +#define OTP_SW_LOCK21_NSEC_LSB _u(2) +#define OTP_SW_LOCK21_NSEC_ACCESS "RW" +#define OTP_SW_LOCK21_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK21_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK21_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK21_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK21_SEC_RESET "-" +#define OTP_SW_LOCK21_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK21_SEC_MSB _u(1) +#define OTP_SW_LOCK21_SEC_LSB _u(0) +#define OTP_SW_LOCK21_SEC_ACCESS "RW" +#define OTP_SW_LOCK21_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK21_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK21_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK22 +// Description : Software lock register for page 22. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK22_OFFSET _u(0x00000058) +#define OTP_SW_LOCK22_BITS _u(0x0000000f) +#define OTP_SW_LOCK22_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK22_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK22_NSEC_RESET "-" +#define OTP_SW_LOCK22_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK22_NSEC_MSB _u(3) +#define OTP_SW_LOCK22_NSEC_LSB _u(2) +#define OTP_SW_LOCK22_NSEC_ACCESS "RW" +#define OTP_SW_LOCK22_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK22_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK22_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK22_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK22_SEC_RESET "-" +#define OTP_SW_LOCK22_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK22_SEC_MSB _u(1) +#define OTP_SW_LOCK22_SEC_LSB _u(0) +#define OTP_SW_LOCK22_SEC_ACCESS "RW" +#define OTP_SW_LOCK22_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK22_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK22_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK23 +// Description : Software lock register for page 23. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK23_OFFSET _u(0x0000005c) +#define OTP_SW_LOCK23_BITS _u(0x0000000f) +#define OTP_SW_LOCK23_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK23_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK23_NSEC_RESET "-" +#define OTP_SW_LOCK23_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK23_NSEC_MSB _u(3) +#define OTP_SW_LOCK23_NSEC_LSB _u(2) +#define OTP_SW_LOCK23_NSEC_ACCESS "RW" +#define OTP_SW_LOCK23_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK23_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK23_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK23_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK23_SEC_RESET "-" +#define OTP_SW_LOCK23_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK23_SEC_MSB _u(1) +#define OTP_SW_LOCK23_SEC_LSB _u(0) +#define OTP_SW_LOCK23_SEC_ACCESS "RW" +#define OTP_SW_LOCK23_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK23_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK23_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK24 +// Description : Software lock register for page 24. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK24_OFFSET _u(0x00000060) +#define OTP_SW_LOCK24_BITS _u(0x0000000f) +#define OTP_SW_LOCK24_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK24_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK24_NSEC_RESET "-" +#define OTP_SW_LOCK24_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK24_NSEC_MSB _u(3) +#define OTP_SW_LOCK24_NSEC_LSB _u(2) +#define OTP_SW_LOCK24_NSEC_ACCESS "RW" +#define OTP_SW_LOCK24_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK24_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK24_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK24_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK24_SEC_RESET "-" +#define OTP_SW_LOCK24_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK24_SEC_MSB _u(1) +#define OTP_SW_LOCK24_SEC_LSB _u(0) +#define OTP_SW_LOCK24_SEC_ACCESS "RW" +#define OTP_SW_LOCK24_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK24_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK24_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK25 +// Description : Software lock register for page 25. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK25_OFFSET _u(0x00000064) +#define OTP_SW_LOCK25_BITS _u(0x0000000f) +#define OTP_SW_LOCK25_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK25_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK25_NSEC_RESET "-" +#define OTP_SW_LOCK25_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK25_NSEC_MSB _u(3) +#define OTP_SW_LOCK25_NSEC_LSB _u(2) +#define OTP_SW_LOCK25_NSEC_ACCESS "RW" +#define OTP_SW_LOCK25_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK25_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK25_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK25_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK25_SEC_RESET "-" +#define OTP_SW_LOCK25_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK25_SEC_MSB _u(1) +#define OTP_SW_LOCK25_SEC_LSB _u(0) +#define OTP_SW_LOCK25_SEC_ACCESS "RW" +#define OTP_SW_LOCK25_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK25_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK25_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK26 +// Description : Software lock register for page 26. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK26_OFFSET _u(0x00000068) +#define OTP_SW_LOCK26_BITS _u(0x0000000f) +#define OTP_SW_LOCK26_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK26_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK26_NSEC_RESET "-" +#define OTP_SW_LOCK26_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK26_NSEC_MSB _u(3) +#define OTP_SW_LOCK26_NSEC_LSB _u(2) +#define OTP_SW_LOCK26_NSEC_ACCESS "RW" +#define OTP_SW_LOCK26_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK26_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK26_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK26_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK26_SEC_RESET "-" +#define OTP_SW_LOCK26_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK26_SEC_MSB _u(1) +#define OTP_SW_LOCK26_SEC_LSB _u(0) +#define OTP_SW_LOCK26_SEC_ACCESS "RW" +#define OTP_SW_LOCK26_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK26_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK26_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK27 +// Description : Software lock register for page 27. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK27_OFFSET _u(0x0000006c) +#define OTP_SW_LOCK27_BITS _u(0x0000000f) +#define OTP_SW_LOCK27_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK27_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK27_NSEC_RESET "-" +#define OTP_SW_LOCK27_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK27_NSEC_MSB _u(3) +#define OTP_SW_LOCK27_NSEC_LSB _u(2) +#define OTP_SW_LOCK27_NSEC_ACCESS "RW" +#define OTP_SW_LOCK27_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK27_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK27_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK27_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK27_SEC_RESET "-" +#define OTP_SW_LOCK27_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK27_SEC_MSB _u(1) +#define OTP_SW_LOCK27_SEC_LSB _u(0) +#define OTP_SW_LOCK27_SEC_ACCESS "RW" +#define OTP_SW_LOCK27_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK27_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK27_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK28 +// Description : Software lock register for page 28. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK28_OFFSET _u(0x00000070) +#define OTP_SW_LOCK28_BITS _u(0x0000000f) +#define OTP_SW_LOCK28_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK28_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK28_NSEC_RESET "-" +#define OTP_SW_LOCK28_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK28_NSEC_MSB _u(3) +#define OTP_SW_LOCK28_NSEC_LSB _u(2) +#define OTP_SW_LOCK28_NSEC_ACCESS "RW" +#define OTP_SW_LOCK28_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK28_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK28_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK28_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK28_SEC_RESET "-" +#define OTP_SW_LOCK28_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK28_SEC_MSB _u(1) +#define OTP_SW_LOCK28_SEC_LSB _u(0) +#define OTP_SW_LOCK28_SEC_ACCESS "RW" +#define OTP_SW_LOCK28_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK28_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK28_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK29 +// Description : Software lock register for page 29. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK29_OFFSET _u(0x00000074) +#define OTP_SW_LOCK29_BITS _u(0x0000000f) +#define OTP_SW_LOCK29_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK29_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK29_NSEC_RESET "-" +#define OTP_SW_LOCK29_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK29_NSEC_MSB _u(3) +#define OTP_SW_LOCK29_NSEC_LSB _u(2) +#define OTP_SW_LOCK29_NSEC_ACCESS "RW" +#define OTP_SW_LOCK29_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK29_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK29_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK29_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK29_SEC_RESET "-" +#define OTP_SW_LOCK29_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK29_SEC_MSB _u(1) +#define OTP_SW_LOCK29_SEC_LSB _u(0) +#define OTP_SW_LOCK29_SEC_ACCESS "RW" +#define OTP_SW_LOCK29_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK29_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK29_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK30 +// Description : Software lock register for page 30. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK30_OFFSET _u(0x00000078) +#define OTP_SW_LOCK30_BITS _u(0x0000000f) +#define OTP_SW_LOCK30_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK30_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK30_NSEC_RESET "-" +#define OTP_SW_LOCK30_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK30_NSEC_MSB _u(3) +#define OTP_SW_LOCK30_NSEC_LSB _u(2) +#define OTP_SW_LOCK30_NSEC_ACCESS "RW" +#define OTP_SW_LOCK30_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK30_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK30_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK30_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK30_SEC_RESET "-" +#define OTP_SW_LOCK30_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK30_SEC_MSB _u(1) +#define OTP_SW_LOCK30_SEC_LSB _u(0) +#define OTP_SW_LOCK30_SEC_ACCESS "RW" +#define OTP_SW_LOCK30_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK30_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK30_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK31 +// Description : Software lock register for page 31. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK31_OFFSET _u(0x0000007c) +#define OTP_SW_LOCK31_BITS _u(0x0000000f) +#define OTP_SW_LOCK31_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK31_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK31_NSEC_RESET "-" +#define OTP_SW_LOCK31_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK31_NSEC_MSB _u(3) +#define OTP_SW_LOCK31_NSEC_LSB _u(2) +#define OTP_SW_LOCK31_NSEC_ACCESS "RW" +#define OTP_SW_LOCK31_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK31_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK31_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK31_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK31_SEC_RESET "-" +#define OTP_SW_LOCK31_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK31_SEC_MSB _u(1) +#define OTP_SW_LOCK31_SEC_LSB _u(0) +#define OTP_SW_LOCK31_SEC_ACCESS "RW" +#define OTP_SW_LOCK31_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK31_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK31_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK32 +// Description : Software lock register for page 32. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK32_OFFSET _u(0x00000080) +#define OTP_SW_LOCK32_BITS _u(0x0000000f) +#define OTP_SW_LOCK32_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK32_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK32_NSEC_RESET "-" +#define OTP_SW_LOCK32_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK32_NSEC_MSB _u(3) +#define OTP_SW_LOCK32_NSEC_LSB _u(2) +#define OTP_SW_LOCK32_NSEC_ACCESS "RW" +#define OTP_SW_LOCK32_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK32_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK32_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK32_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK32_SEC_RESET "-" +#define OTP_SW_LOCK32_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK32_SEC_MSB _u(1) +#define OTP_SW_LOCK32_SEC_LSB _u(0) +#define OTP_SW_LOCK32_SEC_ACCESS "RW" +#define OTP_SW_LOCK32_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK32_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK32_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK33 +// Description : Software lock register for page 33. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK33_OFFSET _u(0x00000084) +#define OTP_SW_LOCK33_BITS _u(0x0000000f) +#define OTP_SW_LOCK33_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK33_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK33_NSEC_RESET "-" +#define OTP_SW_LOCK33_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK33_NSEC_MSB _u(3) +#define OTP_SW_LOCK33_NSEC_LSB _u(2) +#define OTP_SW_LOCK33_NSEC_ACCESS "RW" +#define OTP_SW_LOCK33_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK33_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK33_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK33_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK33_SEC_RESET "-" +#define OTP_SW_LOCK33_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK33_SEC_MSB _u(1) +#define OTP_SW_LOCK33_SEC_LSB _u(0) +#define OTP_SW_LOCK33_SEC_ACCESS "RW" +#define OTP_SW_LOCK33_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK33_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK33_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK34 +// Description : Software lock register for page 34. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK34_OFFSET _u(0x00000088) +#define OTP_SW_LOCK34_BITS _u(0x0000000f) +#define OTP_SW_LOCK34_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK34_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK34_NSEC_RESET "-" +#define OTP_SW_LOCK34_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK34_NSEC_MSB _u(3) +#define OTP_SW_LOCK34_NSEC_LSB _u(2) +#define OTP_SW_LOCK34_NSEC_ACCESS "RW" +#define OTP_SW_LOCK34_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK34_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK34_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK34_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK34_SEC_RESET "-" +#define OTP_SW_LOCK34_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK34_SEC_MSB _u(1) +#define OTP_SW_LOCK34_SEC_LSB _u(0) +#define OTP_SW_LOCK34_SEC_ACCESS "RW" +#define OTP_SW_LOCK34_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK34_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK34_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK35 +// Description : Software lock register for page 35. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK35_OFFSET _u(0x0000008c) +#define OTP_SW_LOCK35_BITS _u(0x0000000f) +#define OTP_SW_LOCK35_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK35_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK35_NSEC_RESET "-" +#define OTP_SW_LOCK35_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK35_NSEC_MSB _u(3) +#define OTP_SW_LOCK35_NSEC_LSB _u(2) +#define OTP_SW_LOCK35_NSEC_ACCESS "RW" +#define OTP_SW_LOCK35_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK35_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK35_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK35_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK35_SEC_RESET "-" +#define OTP_SW_LOCK35_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK35_SEC_MSB _u(1) +#define OTP_SW_LOCK35_SEC_LSB _u(0) +#define OTP_SW_LOCK35_SEC_ACCESS "RW" +#define OTP_SW_LOCK35_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK35_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK35_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK36 +// Description : Software lock register for page 36. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK36_OFFSET _u(0x00000090) +#define OTP_SW_LOCK36_BITS _u(0x0000000f) +#define OTP_SW_LOCK36_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK36_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK36_NSEC_RESET "-" +#define OTP_SW_LOCK36_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK36_NSEC_MSB _u(3) +#define OTP_SW_LOCK36_NSEC_LSB _u(2) +#define OTP_SW_LOCK36_NSEC_ACCESS "RW" +#define OTP_SW_LOCK36_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK36_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK36_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK36_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK36_SEC_RESET "-" +#define OTP_SW_LOCK36_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK36_SEC_MSB _u(1) +#define OTP_SW_LOCK36_SEC_LSB _u(0) +#define OTP_SW_LOCK36_SEC_ACCESS "RW" +#define OTP_SW_LOCK36_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK36_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK36_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK37 +// Description : Software lock register for page 37. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK37_OFFSET _u(0x00000094) +#define OTP_SW_LOCK37_BITS _u(0x0000000f) +#define OTP_SW_LOCK37_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK37_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK37_NSEC_RESET "-" +#define OTP_SW_LOCK37_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK37_NSEC_MSB _u(3) +#define OTP_SW_LOCK37_NSEC_LSB _u(2) +#define OTP_SW_LOCK37_NSEC_ACCESS "RW" +#define OTP_SW_LOCK37_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK37_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK37_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK37_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK37_SEC_RESET "-" +#define OTP_SW_LOCK37_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK37_SEC_MSB _u(1) +#define OTP_SW_LOCK37_SEC_LSB _u(0) +#define OTP_SW_LOCK37_SEC_ACCESS "RW" +#define OTP_SW_LOCK37_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK37_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK37_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK38 +// Description : Software lock register for page 38. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK38_OFFSET _u(0x00000098) +#define OTP_SW_LOCK38_BITS _u(0x0000000f) +#define OTP_SW_LOCK38_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK38_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK38_NSEC_RESET "-" +#define OTP_SW_LOCK38_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK38_NSEC_MSB _u(3) +#define OTP_SW_LOCK38_NSEC_LSB _u(2) +#define OTP_SW_LOCK38_NSEC_ACCESS "RW" +#define OTP_SW_LOCK38_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK38_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK38_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK38_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK38_SEC_RESET "-" +#define OTP_SW_LOCK38_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK38_SEC_MSB _u(1) +#define OTP_SW_LOCK38_SEC_LSB _u(0) +#define OTP_SW_LOCK38_SEC_ACCESS "RW" +#define OTP_SW_LOCK38_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK38_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK38_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK39 +// Description : Software lock register for page 39. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK39_OFFSET _u(0x0000009c) +#define OTP_SW_LOCK39_BITS _u(0x0000000f) +#define OTP_SW_LOCK39_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK39_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK39_NSEC_RESET "-" +#define OTP_SW_LOCK39_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK39_NSEC_MSB _u(3) +#define OTP_SW_LOCK39_NSEC_LSB _u(2) +#define OTP_SW_LOCK39_NSEC_ACCESS "RW" +#define OTP_SW_LOCK39_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK39_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK39_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK39_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK39_SEC_RESET "-" +#define OTP_SW_LOCK39_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK39_SEC_MSB _u(1) +#define OTP_SW_LOCK39_SEC_LSB _u(0) +#define OTP_SW_LOCK39_SEC_ACCESS "RW" +#define OTP_SW_LOCK39_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK39_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK39_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK40 +// Description : Software lock register for page 40. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK40_OFFSET _u(0x000000a0) +#define OTP_SW_LOCK40_BITS _u(0x0000000f) +#define OTP_SW_LOCK40_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK40_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK40_NSEC_RESET "-" +#define OTP_SW_LOCK40_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK40_NSEC_MSB _u(3) +#define OTP_SW_LOCK40_NSEC_LSB _u(2) +#define OTP_SW_LOCK40_NSEC_ACCESS "RW" +#define OTP_SW_LOCK40_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK40_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK40_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK40_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK40_SEC_RESET "-" +#define OTP_SW_LOCK40_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK40_SEC_MSB _u(1) +#define OTP_SW_LOCK40_SEC_LSB _u(0) +#define OTP_SW_LOCK40_SEC_ACCESS "RW" +#define OTP_SW_LOCK40_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK40_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK40_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK41 +// Description : Software lock register for page 41. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK41_OFFSET _u(0x000000a4) +#define OTP_SW_LOCK41_BITS _u(0x0000000f) +#define OTP_SW_LOCK41_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK41_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK41_NSEC_RESET "-" +#define OTP_SW_LOCK41_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK41_NSEC_MSB _u(3) +#define OTP_SW_LOCK41_NSEC_LSB _u(2) +#define OTP_SW_LOCK41_NSEC_ACCESS "RW" +#define OTP_SW_LOCK41_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK41_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK41_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK41_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK41_SEC_RESET "-" +#define OTP_SW_LOCK41_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK41_SEC_MSB _u(1) +#define OTP_SW_LOCK41_SEC_LSB _u(0) +#define OTP_SW_LOCK41_SEC_ACCESS "RW" +#define OTP_SW_LOCK41_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK41_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK41_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK42 +// Description : Software lock register for page 42. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK42_OFFSET _u(0x000000a8) +#define OTP_SW_LOCK42_BITS _u(0x0000000f) +#define OTP_SW_LOCK42_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK42_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK42_NSEC_RESET "-" +#define OTP_SW_LOCK42_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK42_NSEC_MSB _u(3) +#define OTP_SW_LOCK42_NSEC_LSB _u(2) +#define OTP_SW_LOCK42_NSEC_ACCESS "RW" +#define OTP_SW_LOCK42_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK42_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK42_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK42_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK42_SEC_RESET "-" +#define OTP_SW_LOCK42_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK42_SEC_MSB _u(1) +#define OTP_SW_LOCK42_SEC_LSB _u(0) +#define OTP_SW_LOCK42_SEC_ACCESS "RW" +#define OTP_SW_LOCK42_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK42_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK42_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK43 +// Description : Software lock register for page 43. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK43_OFFSET _u(0x000000ac) +#define OTP_SW_LOCK43_BITS _u(0x0000000f) +#define OTP_SW_LOCK43_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK43_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK43_NSEC_RESET "-" +#define OTP_SW_LOCK43_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK43_NSEC_MSB _u(3) +#define OTP_SW_LOCK43_NSEC_LSB _u(2) +#define OTP_SW_LOCK43_NSEC_ACCESS "RW" +#define OTP_SW_LOCK43_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK43_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK43_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK43_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK43_SEC_RESET "-" +#define OTP_SW_LOCK43_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK43_SEC_MSB _u(1) +#define OTP_SW_LOCK43_SEC_LSB _u(0) +#define OTP_SW_LOCK43_SEC_ACCESS "RW" +#define OTP_SW_LOCK43_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK43_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK43_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK44 +// Description : Software lock register for page 44. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK44_OFFSET _u(0x000000b0) +#define OTP_SW_LOCK44_BITS _u(0x0000000f) +#define OTP_SW_LOCK44_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK44_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK44_NSEC_RESET "-" +#define OTP_SW_LOCK44_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK44_NSEC_MSB _u(3) +#define OTP_SW_LOCK44_NSEC_LSB _u(2) +#define OTP_SW_LOCK44_NSEC_ACCESS "RW" +#define OTP_SW_LOCK44_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK44_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK44_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK44_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK44_SEC_RESET "-" +#define OTP_SW_LOCK44_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK44_SEC_MSB _u(1) +#define OTP_SW_LOCK44_SEC_LSB _u(0) +#define OTP_SW_LOCK44_SEC_ACCESS "RW" +#define OTP_SW_LOCK44_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK44_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK44_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK45 +// Description : Software lock register for page 45. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK45_OFFSET _u(0x000000b4) +#define OTP_SW_LOCK45_BITS _u(0x0000000f) +#define OTP_SW_LOCK45_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK45_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK45_NSEC_RESET "-" +#define OTP_SW_LOCK45_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK45_NSEC_MSB _u(3) +#define OTP_SW_LOCK45_NSEC_LSB _u(2) +#define OTP_SW_LOCK45_NSEC_ACCESS "RW" +#define OTP_SW_LOCK45_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK45_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK45_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK45_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK45_SEC_RESET "-" +#define OTP_SW_LOCK45_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK45_SEC_MSB _u(1) +#define OTP_SW_LOCK45_SEC_LSB _u(0) +#define OTP_SW_LOCK45_SEC_ACCESS "RW" +#define OTP_SW_LOCK45_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK45_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK45_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK46 +// Description : Software lock register for page 46. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK46_OFFSET _u(0x000000b8) +#define OTP_SW_LOCK46_BITS _u(0x0000000f) +#define OTP_SW_LOCK46_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK46_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK46_NSEC_RESET "-" +#define OTP_SW_LOCK46_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK46_NSEC_MSB _u(3) +#define OTP_SW_LOCK46_NSEC_LSB _u(2) +#define OTP_SW_LOCK46_NSEC_ACCESS "RW" +#define OTP_SW_LOCK46_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK46_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK46_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK46_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK46_SEC_RESET "-" +#define OTP_SW_LOCK46_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK46_SEC_MSB _u(1) +#define OTP_SW_LOCK46_SEC_LSB _u(0) +#define OTP_SW_LOCK46_SEC_ACCESS "RW" +#define OTP_SW_LOCK46_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK46_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK46_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK47 +// Description : Software lock register for page 47. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK47_OFFSET _u(0x000000bc) +#define OTP_SW_LOCK47_BITS _u(0x0000000f) +#define OTP_SW_LOCK47_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK47_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK47_NSEC_RESET "-" +#define OTP_SW_LOCK47_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK47_NSEC_MSB _u(3) +#define OTP_SW_LOCK47_NSEC_LSB _u(2) +#define OTP_SW_LOCK47_NSEC_ACCESS "RW" +#define OTP_SW_LOCK47_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK47_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK47_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK47_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK47_SEC_RESET "-" +#define OTP_SW_LOCK47_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK47_SEC_MSB _u(1) +#define OTP_SW_LOCK47_SEC_LSB _u(0) +#define OTP_SW_LOCK47_SEC_ACCESS "RW" +#define OTP_SW_LOCK47_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK47_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK47_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK48 +// Description : Software lock register for page 48. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK48_OFFSET _u(0x000000c0) +#define OTP_SW_LOCK48_BITS _u(0x0000000f) +#define OTP_SW_LOCK48_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK48_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK48_NSEC_RESET "-" +#define OTP_SW_LOCK48_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK48_NSEC_MSB _u(3) +#define OTP_SW_LOCK48_NSEC_LSB _u(2) +#define OTP_SW_LOCK48_NSEC_ACCESS "RW" +#define OTP_SW_LOCK48_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK48_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK48_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK48_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK48_SEC_RESET "-" +#define OTP_SW_LOCK48_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK48_SEC_MSB _u(1) +#define OTP_SW_LOCK48_SEC_LSB _u(0) +#define OTP_SW_LOCK48_SEC_ACCESS "RW" +#define OTP_SW_LOCK48_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK48_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK48_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK49 +// Description : Software lock register for page 49. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK49_OFFSET _u(0x000000c4) +#define OTP_SW_LOCK49_BITS _u(0x0000000f) +#define OTP_SW_LOCK49_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK49_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK49_NSEC_RESET "-" +#define OTP_SW_LOCK49_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK49_NSEC_MSB _u(3) +#define OTP_SW_LOCK49_NSEC_LSB _u(2) +#define OTP_SW_LOCK49_NSEC_ACCESS "RW" +#define OTP_SW_LOCK49_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK49_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK49_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK49_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK49_SEC_RESET "-" +#define OTP_SW_LOCK49_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK49_SEC_MSB _u(1) +#define OTP_SW_LOCK49_SEC_LSB _u(0) +#define OTP_SW_LOCK49_SEC_ACCESS "RW" +#define OTP_SW_LOCK49_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK49_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK49_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK50 +// Description : Software lock register for page 50. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK50_OFFSET _u(0x000000c8) +#define OTP_SW_LOCK50_BITS _u(0x0000000f) +#define OTP_SW_LOCK50_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK50_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK50_NSEC_RESET "-" +#define OTP_SW_LOCK50_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK50_NSEC_MSB _u(3) +#define OTP_SW_LOCK50_NSEC_LSB _u(2) +#define OTP_SW_LOCK50_NSEC_ACCESS "RW" +#define OTP_SW_LOCK50_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK50_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK50_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK50_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK50_SEC_RESET "-" +#define OTP_SW_LOCK50_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK50_SEC_MSB _u(1) +#define OTP_SW_LOCK50_SEC_LSB _u(0) +#define OTP_SW_LOCK50_SEC_ACCESS "RW" +#define OTP_SW_LOCK50_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK50_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK50_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK51 +// Description : Software lock register for page 51. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK51_OFFSET _u(0x000000cc) +#define OTP_SW_LOCK51_BITS _u(0x0000000f) +#define OTP_SW_LOCK51_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK51_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK51_NSEC_RESET "-" +#define OTP_SW_LOCK51_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK51_NSEC_MSB _u(3) +#define OTP_SW_LOCK51_NSEC_LSB _u(2) +#define OTP_SW_LOCK51_NSEC_ACCESS "RW" +#define OTP_SW_LOCK51_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK51_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK51_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK51_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK51_SEC_RESET "-" +#define OTP_SW_LOCK51_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK51_SEC_MSB _u(1) +#define OTP_SW_LOCK51_SEC_LSB _u(0) +#define OTP_SW_LOCK51_SEC_ACCESS "RW" +#define OTP_SW_LOCK51_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK51_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK51_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK52 +// Description : Software lock register for page 52. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK52_OFFSET _u(0x000000d0) +#define OTP_SW_LOCK52_BITS _u(0x0000000f) +#define OTP_SW_LOCK52_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK52_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK52_NSEC_RESET "-" +#define OTP_SW_LOCK52_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK52_NSEC_MSB _u(3) +#define OTP_SW_LOCK52_NSEC_LSB _u(2) +#define OTP_SW_LOCK52_NSEC_ACCESS "RW" +#define OTP_SW_LOCK52_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK52_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK52_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK52_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK52_SEC_RESET "-" +#define OTP_SW_LOCK52_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK52_SEC_MSB _u(1) +#define OTP_SW_LOCK52_SEC_LSB _u(0) +#define OTP_SW_LOCK52_SEC_ACCESS "RW" +#define OTP_SW_LOCK52_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK52_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK52_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK53 +// Description : Software lock register for page 53. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK53_OFFSET _u(0x000000d4) +#define OTP_SW_LOCK53_BITS _u(0x0000000f) +#define OTP_SW_LOCK53_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK53_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK53_NSEC_RESET "-" +#define OTP_SW_LOCK53_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK53_NSEC_MSB _u(3) +#define OTP_SW_LOCK53_NSEC_LSB _u(2) +#define OTP_SW_LOCK53_NSEC_ACCESS "RW" +#define OTP_SW_LOCK53_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK53_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK53_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK53_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK53_SEC_RESET "-" +#define OTP_SW_LOCK53_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK53_SEC_MSB _u(1) +#define OTP_SW_LOCK53_SEC_LSB _u(0) +#define OTP_SW_LOCK53_SEC_ACCESS "RW" +#define OTP_SW_LOCK53_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK53_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK53_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK54 +// Description : Software lock register for page 54. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK54_OFFSET _u(0x000000d8) +#define OTP_SW_LOCK54_BITS _u(0x0000000f) +#define OTP_SW_LOCK54_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK54_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK54_NSEC_RESET "-" +#define OTP_SW_LOCK54_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK54_NSEC_MSB _u(3) +#define OTP_SW_LOCK54_NSEC_LSB _u(2) +#define OTP_SW_LOCK54_NSEC_ACCESS "RW" +#define OTP_SW_LOCK54_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK54_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK54_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK54_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK54_SEC_RESET "-" +#define OTP_SW_LOCK54_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK54_SEC_MSB _u(1) +#define OTP_SW_LOCK54_SEC_LSB _u(0) +#define OTP_SW_LOCK54_SEC_ACCESS "RW" +#define OTP_SW_LOCK54_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK54_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK54_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK55 +// Description : Software lock register for page 55. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK55_OFFSET _u(0x000000dc) +#define OTP_SW_LOCK55_BITS _u(0x0000000f) +#define OTP_SW_LOCK55_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK55_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK55_NSEC_RESET "-" +#define OTP_SW_LOCK55_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK55_NSEC_MSB _u(3) +#define OTP_SW_LOCK55_NSEC_LSB _u(2) +#define OTP_SW_LOCK55_NSEC_ACCESS "RW" +#define OTP_SW_LOCK55_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK55_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK55_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK55_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK55_SEC_RESET "-" +#define OTP_SW_LOCK55_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK55_SEC_MSB _u(1) +#define OTP_SW_LOCK55_SEC_LSB _u(0) +#define OTP_SW_LOCK55_SEC_ACCESS "RW" +#define OTP_SW_LOCK55_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK55_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK55_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK56 +// Description : Software lock register for page 56. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK56_OFFSET _u(0x000000e0) +#define OTP_SW_LOCK56_BITS _u(0x0000000f) +#define OTP_SW_LOCK56_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK56_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK56_NSEC_RESET "-" +#define OTP_SW_LOCK56_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK56_NSEC_MSB _u(3) +#define OTP_SW_LOCK56_NSEC_LSB _u(2) +#define OTP_SW_LOCK56_NSEC_ACCESS "RW" +#define OTP_SW_LOCK56_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK56_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK56_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK56_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK56_SEC_RESET "-" +#define OTP_SW_LOCK56_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK56_SEC_MSB _u(1) +#define OTP_SW_LOCK56_SEC_LSB _u(0) +#define OTP_SW_LOCK56_SEC_ACCESS "RW" +#define OTP_SW_LOCK56_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK56_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK56_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK57 +// Description : Software lock register for page 57. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK57_OFFSET _u(0x000000e4) +#define OTP_SW_LOCK57_BITS _u(0x0000000f) +#define OTP_SW_LOCK57_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK57_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK57_NSEC_RESET "-" +#define OTP_SW_LOCK57_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK57_NSEC_MSB _u(3) +#define OTP_SW_LOCK57_NSEC_LSB _u(2) +#define OTP_SW_LOCK57_NSEC_ACCESS "RW" +#define OTP_SW_LOCK57_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK57_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK57_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK57_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK57_SEC_RESET "-" +#define OTP_SW_LOCK57_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK57_SEC_MSB _u(1) +#define OTP_SW_LOCK57_SEC_LSB _u(0) +#define OTP_SW_LOCK57_SEC_ACCESS "RW" +#define OTP_SW_LOCK57_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK57_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK57_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK58 +// Description : Software lock register for page 58. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK58_OFFSET _u(0x000000e8) +#define OTP_SW_LOCK58_BITS _u(0x0000000f) +#define OTP_SW_LOCK58_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK58_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK58_NSEC_RESET "-" +#define OTP_SW_LOCK58_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK58_NSEC_MSB _u(3) +#define OTP_SW_LOCK58_NSEC_LSB _u(2) +#define OTP_SW_LOCK58_NSEC_ACCESS "RW" +#define OTP_SW_LOCK58_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK58_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK58_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK58_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK58_SEC_RESET "-" +#define OTP_SW_LOCK58_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK58_SEC_MSB _u(1) +#define OTP_SW_LOCK58_SEC_LSB _u(0) +#define OTP_SW_LOCK58_SEC_ACCESS "RW" +#define OTP_SW_LOCK58_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK58_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK58_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK59 +// Description : Software lock register for page 59. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK59_OFFSET _u(0x000000ec) +#define OTP_SW_LOCK59_BITS _u(0x0000000f) +#define OTP_SW_LOCK59_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK59_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK59_NSEC_RESET "-" +#define OTP_SW_LOCK59_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK59_NSEC_MSB _u(3) +#define OTP_SW_LOCK59_NSEC_LSB _u(2) +#define OTP_SW_LOCK59_NSEC_ACCESS "RW" +#define OTP_SW_LOCK59_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK59_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK59_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK59_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK59_SEC_RESET "-" +#define OTP_SW_LOCK59_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK59_SEC_MSB _u(1) +#define OTP_SW_LOCK59_SEC_LSB _u(0) +#define OTP_SW_LOCK59_SEC_ACCESS "RW" +#define OTP_SW_LOCK59_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK59_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK59_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK60 +// Description : Software lock register for page 60. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK60_OFFSET _u(0x000000f0) +#define OTP_SW_LOCK60_BITS _u(0x0000000f) +#define OTP_SW_LOCK60_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK60_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK60_NSEC_RESET "-" +#define OTP_SW_LOCK60_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK60_NSEC_MSB _u(3) +#define OTP_SW_LOCK60_NSEC_LSB _u(2) +#define OTP_SW_LOCK60_NSEC_ACCESS "RW" +#define OTP_SW_LOCK60_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK60_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK60_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK60_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK60_SEC_RESET "-" +#define OTP_SW_LOCK60_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK60_SEC_MSB _u(1) +#define OTP_SW_LOCK60_SEC_LSB _u(0) +#define OTP_SW_LOCK60_SEC_ACCESS "RW" +#define OTP_SW_LOCK60_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK60_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK60_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK61 +// Description : Software lock register for page 61. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK61_OFFSET _u(0x000000f4) +#define OTP_SW_LOCK61_BITS _u(0x0000000f) +#define OTP_SW_LOCK61_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK61_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK61_NSEC_RESET "-" +#define OTP_SW_LOCK61_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK61_NSEC_MSB _u(3) +#define OTP_SW_LOCK61_NSEC_LSB _u(2) +#define OTP_SW_LOCK61_NSEC_ACCESS "RW" +#define OTP_SW_LOCK61_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK61_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK61_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK61_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK61_SEC_RESET "-" +#define OTP_SW_LOCK61_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK61_SEC_MSB _u(1) +#define OTP_SW_LOCK61_SEC_LSB _u(0) +#define OTP_SW_LOCK61_SEC_ACCESS "RW" +#define OTP_SW_LOCK61_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK61_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK61_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK62 +// Description : Software lock register for page 62. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK62_OFFSET _u(0x000000f8) +#define OTP_SW_LOCK62_BITS _u(0x0000000f) +#define OTP_SW_LOCK62_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK62_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK62_NSEC_RESET "-" +#define OTP_SW_LOCK62_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK62_NSEC_MSB _u(3) +#define OTP_SW_LOCK62_NSEC_LSB _u(2) +#define OTP_SW_LOCK62_NSEC_ACCESS "RW" +#define OTP_SW_LOCK62_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK62_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK62_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK62_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK62_SEC_RESET "-" +#define OTP_SW_LOCK62_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK62_SEC_MSB _u(1) +#define OTP_SW_LOCK62_SEC_LSB _u(0) +#define OTP_SW_LOCK62_SEC_ACCESS "RW" +#define OTP_SW_LOCK62_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK62_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK62_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SW_LOCK63 +// Description : Software lock register for page 63. +// +// Locks are initialised from the OTP lock pages at reset. This +// register can be written to further advance the lock state of +// each page (until next reset), and read to check the current +// lock state of a page. +#define OTP_SW_LOCK63_OFFSET _u(0x000000fc) +#define OTP_SW_LOCK63_BITS _u(0x0000000f) +#define OTP_SW_LOCK63_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK63_NSEC +// Description : Non-secure lock status. Writes are OR'd with the current value. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK63_NSEC_RESET "-" +#define OTP_SW_LOCK63_NSEC_BITS _u(0x0000000c) +#define OTP_SW_LOCK63_NSEC_MSB _u(3) +#define OTP_SW_LOCK63_NSEC_LSB _u(2) +#define OTP_SW_LOCK63_NSEC_ACCESS "RW" +#define OTP_SW_LOCK63_NSEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK63_NSEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK63_NSEC_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_SW_LOCK63_SEC +// Description : Secure lock status. Writes are OR'd with the current value. +// This field is read-only to Non-secure code. +// 0x0 -> read_write +// 0x1 -> read_only +// 0x3 -> inaccessible +#define OTP_SW_LOCK63_SEC_RESET "-" +#define OTP_SW_LOCK63_SEC_BITS _u(0x00000003) +#define OTP_SW_LOCK63_SEC_MSB _u(1) +#define OTP_SW_LOCK63_SEC_LSB _u(0) +#define OTP_SW_LOCK63_SEC_ACCESS "RW" +#define OTP_SW_LOCK63_SEC_VALUE_READ_WRITE _u(0x0) +#define OTP_SW_LOCK63_SEC_VALUE_READ_ONLY _u(0x1) +#define OTP_SW_LOCK63_SEC_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_SBPI_INSTR +// Description : Dispatch instructions to the SBPI interface, used for +// programming the OTP fuses. +#define OTP_SBPI_INSTR_OFFSET _u(0x00000100) +#define OTP_SBPI_INSTR_BITS _u(0x7fffffff) +#define OTP_SBPI_INSTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_INSTR_EXEC +// Description : Execute instruction +#define OTP_SBPI_INSTR_EXEC_RESET _u(0x0) +#define OTP_SBPI_INSTR_EXEC_BITS _u(0x40000000) +#define OTP_SBPI_INSTR_EXEC_MSB _u(30) +#define OTP_SBPI_INSTR_EXEC_LSB _u(30) +#define OTP_SBPI_INSTR_EXEC_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_INSTR_IS_WR +// Description : Payload type is write +#define OTP_SBPI_INSTR_IS_WR_RESET _u(0x0) +#define OTP_SBPI_INSTR_IS_WR_BITS _u(0x20000000) +#define OTP_SBPI_INSTR_IS_WR_MSB _u(29) +#define OTP_SBPI_INSTR_IS_WR_LSB _u(29) +#define OTP_SBPI_INSTR_IS_WR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_INSTR_HAS_PAYLOAD +// Description : Instruction has payload (data to be written or to be read) +#define OTP_SBPI_INSTR_HAS_PAYLOAD_RESET _u(0x0) +#define OTP_SBPI_INSTR_HAS_PAYLOAD_BITS _u(0x10000000) +#define OTP_SBPI_INSTR_HAS_PAYLOAD_MSB _u(28) +#define OTP_SBPI_INSTR_HAS_PAYLOAD_LSB _u(28) +#define OTP_SBPI_INSTR_HAS_PAYLOAD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_INSTR_PAYLOAD_SIZE_M1 +// Description : Instruction payload size in bytes minus 1 +#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_RESET _u(0x0) +#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_BITS _u(0x0f000000) +#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_MSB _u(27) +#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_LSB _u(24) +#define OTP_SBPI_INSTR_PAYLOAD_SIZE_M1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_INSTR_TARGET +// Description : Instruction target, it can be PMC (0x3a) or DAP (0x02) +#define OTP_SBPI_INSTR_TARGET_RESET _u(0x00) +#define OTP_SBPI_INSTR_TARGET_BITS _u(0x00ff0000) +#define OTP_SBPI_INSTR_TARGET_MSB _u(23) +#define OTP_SBPI_INSTR_TARGET_LSB _u(16) +#define OTP_SBPI_INSTR_TARGET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_INSTR_CMD +#define OTP_SBPI_INSTR_CMD_RESET _u(0x00) +#define OTP_SBPI_INSTR_CMD_BITS _u(0x0000ff00) +#define OTP_SBPI_INSTR_CMD_MSB _u(15) +#define OTP_SBPI_INSTR_CMD_LSB _u(8) +#define OTP_SBPI_INSTR_CMD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_INSTR_SHORT_WDATA +// Description : wdata to be used only when payload_size_m1=0 +#define OTP_SBPI_INSTR_SHORT_WDATA_RESET _u(0x00) +#define OTP_SBPI_INSTR_SHORT_WDATA_BITS _u(0x000000ff) +#define OTP_SBPI_INSTR_SHORT_WDATA_MSB _u(7) +#define OTP_SBPI_INSTR_SHORT_WDATA_LSB _u(0) +#define OTP_SBPI_INSTR_SHORT_WDATA_ACCESS "RW" +// ============================================================================= +// Register : OTP_SBPI_WDATA_0 +// Description : SBPI write payload bytes 3..0 +#define OTP_SBPI_WDATA_0_OFFSET _u(0x00000104) +#define OTP_SBPI_WDATA_0_BITS _u(0xffffffff) +#define OTP_SBPI_WDATA_0_RESET _u(0x00000000) +#define OTP_SBPI_WDATA_0_MSB _u(31) +#define OTP_SBPI_WDATA_0_LSB _u(0) +#define OTP_SBPI_WDATA_0_ACCESS "RW" +// ============================================================================= +// Register : OTP_SBPI_WDATA_1 +// Description : SBPI write payload bytes 7..4 +#define OTP_SBPI_WDATA_1_OFFSET _u(0x00000108) +#define OTP_SBPI_WDATA_1_BITS _u(0xffffffff) +#define OTP_SBPI_WDATA_1_RESET _u(0x00000000) +#define OTP_SBPI_WDATA_1_MSB _u(31) +#define OTP_SBPI_WDATA_1_LSB _u(0) +#define OTP_SBPI_WDATA_1_ACCESS "RW" +// ============================================================================= +// Register : OTP_SBPI_WDATA_2 +// Description : SBPI write payload bytes 11..8 +#define OTP_SBPI_WDATA_2_OFFSET _u(0x0000010c) +#define OTP_SBPI_WDATA_2_BITS _u(0xffffffff) +#define OTP_SBPI_WDATA_2_RESET _u(0x00000000) +#define OTP_SBPI_WDATA_2_MSB _u(31) +#define OTP_SBPI_WDATA_2_LSB _u(0) +#define OTP_SBPI_WDATA_2_ACCESS "RW" +// ============================================================================= +// Register : OTP_SBPI_WDATA_3 +// Description : SBPI write payload bytes 15..12 +#define OTP_SBPI_WDATA_3_OFFSET _u(0x00000110) +#define OTP_SBPI_WDATA_3_BITS _u(0xffffffff) +#define OTP_SBPI_WDATA_3_RESET _u(0x00000000) +#define OTP_SBPI_WDATA_3_MSB _u(31) +#define OTP_SBPI_WDATA_3_LSB _u(0) +#define OTP_SBPI_WDATA_3_ACCESS "RW" +// ============================================================================= +// Register : OTP_SBPI_RDATA_0 +// Description : Read payload bytes 3..0. Once read, the data in the register +// will automatically clear to 0. +#define OTP_SBPI_RDATA_0_OFFSET _u(0x00000114) +#define OTP_SBPI_RDATA_0_BITS _u(0xffffffff) +#define OTP_SBPI_RDATA_0_RESET _u(0x00000000) +#define OTP_SBPI_RDATA_0_MSB _u(31) +#define OTP_SBPI_RDATA_0_LSB _u(0) +#define OTP_SBPI_RDATA_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_SBPI_RDATA_1 +// Description : Read payload bytes 7..4. Once read, the data in the register +// will automatically clear to 0. +#define OTP_SBPI_RDATA_1_OFFSET _u(0x00000118) +#define OTP_SBPI_RDATA_1_BITS _u(0xffffffff) +#define OTP_SBPI_RDATA_1_RESET _u(0x00000000) +#define OTP_SBPI_RDATA_1_MSB _u(31) +#define OTP_SBPI_RDATA_1_LSB _u(0) +#define OTP_SBPI_RDATA_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_SBPI_RDATA_2 +// Description : Read payload bytes 11..8. Once read, the data in the register +// will automatically clear to 0. +#define OTP_SBPI_RDATA_2_OFFSET _u(0x0000011c) +#define OTP_SBPI_RDATA_2_BITS _u(0xffffffff) +#define OTP_SBPI_RDATA_2_RESET _u(0x00000000) +#define OTP_SBPI_RDATA_2_MSB _u(31) +#define OTP_SBPI_RDATA_2_LSB _u(0) +#define OTP_SBPI_RDATA_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_SBPI_RDATA_3 +// Description : Read payload bytes 15..12. Once read, the data in the register +// will automatically clear to 0. +#define OTP_SBPI_RDATA_3_OFFSET _u(0x00000120) +#define OTP_SBPI_RDATA_3_BITS _u(0xffffffff) +#define OTP_SBPI_RDATA_3_RESET _u(0x00000000) +#define OTP_SBPI_RDATA_3_MSB _u(31) +#define OTP_SBPI_RDATA_3_LSB _u(0) +#define OTP_SBPI_RDATA_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_SBPI_STATUS +#define OTP_SBPI_STATUS_OFFSET _u(0x00000124) +#define OTP_SBPI_STATUS_BITS _u(0x00ff1111) +#define OTP_SBPI_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_STATUS_MISO +// Description : SBPI MISO (master in - slave out): response from SBPI +#define OTP_SBPI_STATUS_MISO_RESET "-" +#define OTP_SBPI_STATUS_MISO_BITS _u(0x00ff0000) +#define OTP_SBPI_STATUS_MISO_MSB _u(23) +#define OTP_SBPI_STATUS_MISO_LSB _u(16) +#define OTP_SBPI_STATUS_MISO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_STATUS_FLAG +// Description : SBPI flag +#define OTP_SBPI_STATUS_FLAG_RESET "-" +#define OTP_SBPI_STATUS_FLAG_BITS _u(0x00001000) +#define OTP_SBPI_STATUS_FLAG_MSB _u(12) +#define OTP_SBPI_STATUS_FLAG_LSB _u(12) +#define OTP_SBPI_STATUS_FLAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_STATUS_INSTR_MISS +// Description : Last instruction missed (dropped), as the previous has not +// finished running +#define OTP_SBPI_STATUS_INSTR_MISS_RESET _u(0x0) +#define OTP_SBPI_STATUS_INSTR_MISS_BITS _u(0x00000100) +#define OTP_SBPI_STATUS_INSTR_MISS_MSB _u(8) +#define OTP_SBPI_STATUS_INSTR_MISS_LSB _u(8) +#define OTP_SBPI_STATUS_INSTR_MISS_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_STATUS_INSTR_DONE +// Description : Last instruction done +#define OTP_SBPI_STATUS_INSTR_DONE_RESET _u(0x0) +#define OTP_SBPI_STATUS_INSTR_DONE_BITS _u(0x00000010) +#define OTP_SBPI_STATUS_INSTR_DONE_MSB _u(4) +#define OTP_SBPI_STATUS_INSTR_DONE_LSB _u(4) +#define OTP_SBPI_STATUS_INSTR_DONE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : OTP_SBPI_STATUS_RDATA_VLD +// Description : Read command has returned data +#define OTP_SBPI_STATUS_RDATA_VLD_RESET _u(0x0) +#define OTP_SBPI_STATUS_RDATA_VLD_BITS _u(0x00000001) +#define OTP_SBPI_STATUS_RDATA_VLD_MSB _u(0) +#define OTP_SBPI_STATUS_RDATA_VLD_LSB _u(0) +#define OTP_SBPI_STATUS_RDATA_VLD_ACCESS "WC" +// ============================================================================= +// Register : OTP_USR +// Description : Controls for APB data read interface (USER interface) +#define OTP_USR_OFFSET _u(0x00000128) +#define OTP_USR_BITS _u(0x00000011) +#define OTP_USR_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : OTP_USR_PD +// Description : Power-down; 1 disables current reference. Must be 0 to read +// data from the OTP. +#define OTP_USR_PD_RESET _u(0x0) +#define OTP_USR_PD_BITS _u(0x00000010) +#define OTP_USR_PD_MSB _u(4) +#define OTP_USR_PD_LSB _u(4) +#define OTP_USR_PD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_USR_DCTRL +// Description : 1 enables USER interface; 0 disables USER interface (enables +// SBPI). +// +// This bit must be cleared before performing any SBPI access, +// such as when programming the OTP. The APB data read interface +// (USER interface) will be inaccessible during this time, and +// will return a bus error if any read is attempted. +#define OTP_USR_DCTRL_RESET _u(0x1) +#define OTP_USR_DCTRL_BITS _u(0x00000001) +#define OTP_USR_DCTRL_MSB _u(0) +#define OTP_USR_DCTRL_LSB _u(0) +#define OTP_USR_DCTRL_ACCESS "RW" +// ============================================================================= +// Register : OTP_DBG +// Description : Debug for OTP power-on state machine +#define OTP_DBG_OFFSET _u(0x0000012c) +#define OTP_DBG_BITS _u(0x000010ff) +#define OTP_DBG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_DBG_CUSTOMER_RMA_FLAG +// Description : The chip is in RMA mode +#define OTP_DBG_CUSTOMER_RMA_FLAG_RESET "-" +#define OTP_DBG_CUSTOMER_RMA_FLAG_BITS _u(0x00001000) +#define OTP_DBG_CUSTOMER_RMA_FLAG_MSB _u(12) +#define OTP_DBG_CUSTOMER_RMA_FLAG_LSB _u(12) +#define OTP_DBG_CUSTOMER_RMA_FLAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DBG_PSM_STATE +// Description : Monitor the PSM FSM's state +#define OTP_DBG_PSM_STATE_RESET "-" +#define OTP_DBG_PSM_STATE_BITS _u(0x000000f0) +#define OTP_DBG_PSM_STATE_MSB _u(7) +#define OTP_DBG_PSM_STATE_LSB _u(4) +#define OTP_DBG_PSM_STATE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DBG_ROSC_UP +// Description : Ring oscillator is up and running +#define OTP_DBG_ROSC_UP_RESET "-" +#define OTP_DBG_ROSC_UP_BITS _u(0x00000008) +#define OTP_DBG_ROSC_UP_MSB _u(3) +#define OTP_DBG_ROSC_UP_LSB _u(3) +#define OTP_DBG_ROSC_UP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DBG_ROSC_UP_SEEN +// Description : Ring oscillator was seen up and running +#define OTP_DBG_ROSC_UP_SEEN_RESET _u(0x0) +#define OTP_DBG_ROSC_UP_SEEN_BITS _u(0x00000004) +#define OTP_DBG_ROSC_UP_SEEN_MSB _u(2) +#define OTP_DBG_ROSC_UP_SEEN_LSB _u(2) +#define OTP_DBG_ROSC_UP_SEEN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : OTP_DBG_BOOT_DONE +// Description : PSM boot done status flag +#define OTP_DBG_BOOT_DONE_RESET "-" +#define OTP_DBG_BOOT_DONE_BITS _u(0x00000002) +#define OTP_DBG_BOOT_DONE_MSB _u(1) +#define OTP_DBG_BOOT_DONE_LSB _u(1) +#define OTP_DBG_BOOT_DONE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DBG_PSM_DONE +// Description : PSM done status flag +#define OTP_DBG_PSM_DONE_RESET "-" +#define OTP_DBG_PSM_DONE_BITS _u(0x00000001) +#define OTP_DBG_PSM_DONE_MSB _u(0) +#define OTP_DBG_PSM_DONE_LSB _u(0) +#define OTP_DBG_PSM_DONE_ACCESS "RO" +// ============================================================================= +// Register : OTP_BIST +// Description : During BIST, count address locations that have at least one +// leaky bit +#define OTP_BIST_OFFSET _u(0x00000134) +#define OTP_BIST_BITS _u(0x7fff1fff) +#define OTP_BIST_RESET _u(0x0fff0000) +// ----------------------------------------------------------------------------- +// Field : OTP_BIST_CNT_FAIL +// Description : Flag if the count of address locations with at least one leaky +// bit exceeds cnt_max +#define OTP_BIST_CNT_FAIL_RESET "-" +#define OTP_BIST_CNT_FAIL_BITS _u(0x40000000) +#define OTP_BIST_CNT_FAIL_MSB _u(30) +#define OTP_BIST_CNT_FAIL_LSB _u(30) +#define OTP_BIST_CNT_FAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_BIST_CNT_CLR +// Description : Clear counter before use +#define OTP_BIST_CNT_CLR_RESET _u(0x0) +#define OTP_BIST_CNT_CLR_BITS _u(0x20000000) +#define OTP_BIST_CNT_CLR_MSB _u(29) +#define OTP_BIST_CNT_CLR_LSB _u(29) +#define OTP_BIST_CNT_CLR_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : OTP_BIST_CNT_ENA +// Description : Enable the counter before the BIST function is initiated +#define OTP_BIST_CNT_ENA_RESET _u(0x0) +#define OTP_BIST_CNT_ENA_BITS _u(0x10000000) +#define OTP_BIST_CNT_ENA_MSB _u(28) +#define OTP_BIST_CNT_ENA_LSB _u(28) +#define OTP_BIST_CNT_ENA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_BIST_CNT_MAX +// Description : The cnt_fail flag will be set if the number of leaky locations +// exceeds this number +#define OTP_BIST_CNT_MAX_RESET _u(0xfff) +#define OTP_BIST_CNT_MAX_BITS _u(0x0fff0000) +#define OTP_BIST_CNT_MAX_MSB _u(27) +#define OTP_BIST_CNT_MAX_LSB _u(16) +#define OTP_BIST_CNT_MAX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_BIST_CNT +// Description : Number of locations that have at least one leaky bit. Note: +// This count is true only if the BIST was initiated without the +// fix option. +#define OTP_BIST_CNT_RESET "-" +#define OTP_BIST_CNT_BITS _u(0x00001fff) +#define OTP_BIST_CNT_MSB _u(12) +#define OTP_BIST_CNT_LSB _u(0) +#define OTP_BIST_CNT_ACCESS "RO" +// ============================================================================= +// Register : OTP_CRT_KEY_W0 +// Description : Word 0 (bits 31..0) of the key. Write only, read returns 0x0 +#define OTP_CRT_KEY_W0_OFFSET _u(0x00000138) +#define OTP_CRT_KEY_W0_BITS _u(0xffffffff) +#define OTP_CRT_KEY_W0_RESET _u(0x00000000) +#define OTP_CRT_KEY_W0_MSB _u(31) +#define OTP_CRT_KEY_W0_LSB _u(0) +#define OTP_CRT_KEY_W0_ACCESS "WO" +// ============================================================================= +// Register : OTP_CRT_KEY_W1 +// Description : Word 1 (bits 63..32) of the key. Write only, read returns 0x0 +#define OTP_CRT_KEY_W1_OFFSET _u(0x0000013c) +#define OTP_CRT_KEY_W1_BITS _u(0xffffffff) +#define OTP_CRT_KEY_W1_RESET _u(0x00000000) +#define OTP_CRT_KEY_W1_MSB _u(31) +#define OTP_CRT_KEY_W1_LSB _u(0) +#define OTP_CRT_KEY_W1_ACCESS "WO" +// ============================================================================= +// Register : OTP_CRT_KEY_W2 +// Description : Word 2 (bits 95..64) of the key. Write only, read returns 0x0 +#define OTP_CRT_KEY_W2_OFFSET _u(0x00000140) +#define OTP_CRT_KEY_W2_BITS _u(0xffffffff) +#define OTP_CRT_KEY_W2_RESET _u(0x00000000) +#define OTP_CRT_KEY_W2_MSB _u(31) +#define OTP_CRT_KEY_W2_LSB _u(0) +#define OTP_CRT_KEY_W2_ACCESS "WO" +// ============================================================================= +// Register : OTP_CRT_KEY_W3 +// Description : Word 3 (bits 127..96) of the key. Write only, read returns 0x0 +#define OTP_CRT_KEY_W3_OFFSET _u(0x00000144) +#define OTP_CRT_KEY_W3_BITS _u(0xffffffff) +#define OTP_CRT_KEY_W3_RESET _u(0x00000000) +#define OTP_CRT_KEY_W3_MSB _u(31) +#define OTP_CRT_KEY_W3_LSB _u(0) +#define OTP_CRT_KEY_W3_ACCESS "WO" +// ============================================================================= +// Register : OTP_CRITICAL +// Description : Quickly check values of critical flags read during boot up +#define OTP_CRITICAL_OFFSET _u(0x00000148) +#define OTP_CRITICAL_BITS _u(0x0003007f) +#define OTP_CRITICAL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_RISCV_DISABLE +#define OTP_CRITICAL_RISCV_DISABLE_RESET _u(0x0) +#define OTP_CRITICAL_RISCV_DISABLE_BITS _u(0x00020000) +#define OTP_CRITICAL_RISCV_DISABLE_MSB _u(17) +#define OTP_CRITICAL_RISCV_DISABLE_LSB _u(17) +#define OTP_CRITICAL_RISCV_DISABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_ARM_DISABLE +#define OTP_CRITICAL_ARM_DISABLE_RESET _u(0x0) +#define OTP_CRITICAL_ARM_DISABLE_BITS _u(0x00010000) +#define OTP_CRITICAL_ARM_DISABLE_MSB _u(16) +#define OTP_CRITICAL_ARM_DISABLE_LSB _u(16) +#define OTP_CRITICAL_ARM_DISABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_GLITCH_DETECTOR_SENS +#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_RESET _u(0x0) +#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_BITS _u(0x00000060) +#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_MSB _u(6) +#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_LSB _u(5) +#define OTP_CRITICAL_GLITCH_DETECTOR_SENS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_GLITCH_DETECTOR_ENABLE +#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_RESET _u(0x0) +#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_BITS _u(0x00000010) +#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_MSB _u(4) +#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_LSB _u(4) +#define OTP_CRITICAL_GLITCH_DETECTOR_ENABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_DEFAULT_ARCHSEL +#define OTP_CRITICAL_DEFAULT_ARCHSEL_RESET _u(0x0) +#define OTP_CRITICAL_DEFAULT_ARCHSEL_BITS _u(0x00000008) +#define OTP_CRITICAL_DEFAULT_ARCHSEL_MSB _u(3) +#define OTP_CRITICAL_DEFAULT_ARCHSEL_LSB _u(3) +#define OTP_CRITICAL_DEFAULT_ARCHSEL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_DEBUG_DISABLE +#define OTP_CRITICAL_DEBUG_DISABLE_RESET _u(0x0) +#define OTP_CRITICAL_DEBUG_DISABLE_BITS _u(0x00000004) +#define OTP_CRITICAL_DEBUG_DISABLE_MSB _u(2) +#define OTP_CRITICAL_DEBUG_DISABLE_LSB _u(2) +#define OTP_CRITICAL_DEBUG_DISABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_SECURE_DEBUG_DISABLE +#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_RESET _u(0x0) +#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_BITS _u(0x00000002) +#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_MSB _u(1) +#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_LSB _u(1) +#define OTP_CRITICAL_SECURE_DEBUG_DISABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_CRITICAL_SECURE_BOOT_ENABLE +#define OTP_CRITICAL_SECURE_BOOT_ENABLE_RESET _u(0x0) +#define OTP_CRITICAL_SECURE_BOOT_ENABLE_BITS _u(0x00000001) +#define OTP_CRITICAL_SECURE_BOOT_ENABLE_MSB _u(0) +#define OTP_CRITICAL_SECURE_BOOT_ENABLE_LSB _u(0) +#define OTP_CRITICAL_SECURE_BOOT_ENABLE_ACCESS "RO" +// ============================================================================= +// Register : OTP_KEY_VALID +// Description : Which keys were valid (enrolled) at boot time +#define OTP_KEY_VALID_OFFSET _u(0x0000014c) +#define OTP_KEY_VALID_BITS _u(0x000000ff) +#define OTP_KEY_VALID_RESET _u(0x00000000) +#define OTP_KEY_VALID_MSB _u(7) +#define OTP_KEY_VALID_LSB _u(0) +#define OTP_KEY_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DEBUGEN +// Description : Enable a debug feature that has been disabled. Debug features +// are disabled if one of the relevant critical boot flags is set +// in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug +// key is marked valid in OTP, and the matching key value has not +// been supplied over SWD. +// +// Specifically: +// +// - The DEBUG_DISABLE flag disables all debug features. This can +// be fully overridden by setting all bits of this register. +// +// - The SECURE_DEBUG_DISABLE flag disables secure processor +// debug. This can be fully overridden by setting the PROC0_SECURE +// and PROC1_SECURE bits of this register. +// +// - If a single debug key has been registered, and no matching +// key value has been supplied over SWD, then all debug features +// are disabled. This can be fully overridden by setting all bits +// of this register. +// +// - If both debug keys have been registered, and the Non-secure +// key's value (key 6) has been supplied over SWD, secure +// processor debug is disabled. This can be fully overridden by +// setting the PROC0_SECURE and PROC1_SECURE bits of this +// register. +// +// - If both debug keys have been registered, and the Secure key's +// value (key 5) has been supplied over SWD, then no debug +// features are disabled by the key mechanism. However, note that +// in this case debug features may still be disabled by the +// critical boot flags. +#define OTP_DEBUGEN_OFFSET _u(0x00000150) +#define OTP_DEBUGEN_BITS _u(0x0000010f) +#define OTP_DEBUGEN_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_MISC +// Description : Enable other debug components. Specifically, the CTI, and the +// APB-AP used to access the RISC-V Debug Module. +// +// These components are disabled by default if either of the debug +// disable critical flags is set, or if at least one debug key has +// been enrolled and the least secure of these enrolled key values +// has not been provided over SWD. +#define OTP_DEBUGEN_MISC_RESET _u(0x0) +#define OTP_DEBUGEN_MISC_BITS _u(0x00000100) +#define OTP_DEBUGEN_MISC_MSB _u(8) +#define OTP_DEBUGEN_MISC_LSB _u(8) +#define OTP_DEBUGEN_MISC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_PROC1_SECURE +// Description : Permit core 1's Mem-AP to generate Secure accesses, assuming it +// is enabled at all. Also enable secure debug of core 1 (SPIDEN +// and SPNIDEN). +// +// Secure debug of core 1 is disabled by default if the secure +// debug disable critical flag is set, or if at least one debug +// key has been enrolled and the most secure of these enrolled key +// values not yet provided over SWD. +#define OTP_DEBUGEN_PROC1_SECURE_RESET _u(0x0) +#define OTP_DEBUGEN_PROC1_SECURE_BITS _u(0x00000008) +#define OTP_DEBUGEN_PROC1_SECURE_MSB _u(3) +#define OTP_DEBUGEN_PROC1_SECURE_LSB _u(3) +#define OTP_DEBUGEN_PROC1_SECURE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_PROC1 +// Description : Enable core 1's Mem-AP if it is currently disabled. +// +// The Mem-AP is disabled by default if either of the debug +// disable critical flags is set, or if at least one debug key has +// been enrolled and the least secure of these enrolled key values +// has not been provided over SWD. +#define OTP_DEBUGEN_PROC1_RESET _u(0x0) +#define OTP_DEBUGEN_PROC1_BITS _u(0x00000004) +#define OTP_DEBUGEN_PROC1_MSB _u(2) +#define OTP_DEBUGEN_PROC1_LSB _u(2) +#define OTP_DEBUGEN_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_PROC0_SECURE +// Description : Permit core 0's Mem-AP to generate Secure accesses, assuming it +// is enabled at all. Also enable secure debug of core 0 (SPIDEN +// and SPNIDEN). +// +// Secure debug of core 0 is disabled by default if the secure +// debug disable critical flag is set, or if at least one debug +// key has been enrolled and the most secure of these enrolled key +// values not yet provided over SWD. +// +// Note also that core Mem-APs are unconditionally disabled when a +// core is switched to RISC-V mode (by setting the ARCHSEL bit and +// performing a warm reset of the core). +#define OTP_DEBUGEN_PROC0_SECURE_RESET _u(0x0) +#define OTP_DEBUGEN_PROC0_SECURE_BITS _u(0x00000002) +#define OTP_DEBUGEN_PROC0_SECURE_MSB _u(1) +#define OTP_DEBUGEN_PROC0_SECURE_LSB _u(1) +#define OTP_DEBUGEN_PROC0_SECURE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_PROC0 +// Description : Enable core 0's Mem-AP if it is currently disabled. +// +// The Mem-AP is disabled by default if either of the debug +// disable critical flags is set, or if at least one debug key has +// been enrolled and the least secure of these enrolled key values +// has not been provided over SWD. +// +// Note also that core Mem-APs are unconditionally disabled when a +// core is switched to RISC-V mode (by setting the ARCHSEL bit and +// performing a warm reset of the core). +#define OTP_DEBUGEN_PROC0_RESET _u(0x0) +#define OTP_DEBUGEN_PROC0_BITS _u(0x00000001) +#define OTP_DEBUGEN_PROC0_MSB _u(0) +#define OTP_DEBUGEN_PROC0_LSB _u(0) +#define OTP_DEBUGEN_PROC0_ACCESS "RW" +// ============================================================================= +// Register : OTP_DEBUGEN_LOCK +// Description : Write 1s to lock corresponding bits in DEBUGEN. This register +// is reset by the processor cold reset. +#define OTP_DEBUGEN_LOCK_OFFSET _u(0x00000154) +#define OTP_DEBUGEN_LOCK_BITS _u(0x0000010f) +#define OTP_DEBUGEN_LOCK_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_LOCK_MISC +// Description : Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once +// set. +#define OTP_DEBUGEN_LOCK_MISC_RESET _u(0x0) +#define OTP_DEBUGEN_LOCK_MISC_BITS _u(0x00000100) +#define OTP_DEBUGEN_LOCK_MISC_MSB _u(8) +#define OTP_DEBUGEN_LOCK_MISC_LSB _u(8) +#define OTP_DEBUGEN_LOCK_MISC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_LOCK_PROC1_SECURE +// Description : Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be +// cleared once set. +#define OTP_DEBUGEN_LOCK_PROC1_SECURE_RESET _u(0x0) +#define OTP_DEBUGEN_LOCK_PROC1_SECURE_BITS _u(0x00000008) +#define OTP_DEBUGEN_LOCK_PROC1_SECURE_MSB _u(3) +#define OTP_DEBUGEN_LOCK_PROC1_SECURE_LSB _u(3) +#define OTP_DEBUGEN_LOCK_PROC1_SECURE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_LOCK_PROC1 +// Description : Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once +// set. +#define OTP_DEBUGEN_LOCK_PROC1_RESET _u(0x0) +#define OTP_DEBUGEN_LOCK_PROC1_BITS _u(0x00000004) +#define OTP_DEBUGEN_LOCK_PROC1_MSB _u(2) +#define OTP_DEBUGEN_LOCK_PROC1_LSB _u(2) +#define OTP_DEBUGEN_LOCK_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_LOCK_PROC0_SECURE +// Description : Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be +// cleared once set. +#define OTP_DEBUGEN_LOCK_PROC0_SECURE_RESET _u(0x0) +#define OTP_DEBUGEN_LOCK_PROC0_SECURE_BITS _u(0x00000002) +#define OTP_DEBUGEN_LOCK_PROC0_SECURE_MSB _u(1) +#define OTP_DEBUGEN_LOCK_PROC0_SECURE_LSB _u(1) +#define OTP_DEBUGEN_LOCK_PROC0_SECURE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_DEBUGEN_LOCK_PROC0 +// Description : Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once +// set. +#define OTP_DEBUGEN_LOCK_PROC0_RESET _u(0x0) +#define OTP_DEBUGEN_LOCK_PROC0_BITS _u(0x00000001) +#define OTP_DEBUGEN_LOCK_PROC0_MSB _u(0) +#define OTP_DEBUGEN_LOCK_PROC0_LSB _u(0) +#define OTP_DEBUGEN_LOCK_PROC0_ACCESS "RW" +// ============================================================================= +// Register : OTP_ARCHSEL +// Description : Architecture select (Arm/RISC-V). The default and allowable +// values of this register are constrained by the critical boot +// flags. +// +// This register is reset by the earliest reset in the switched +// core power domain (before a processor cold reset). +// +// Cores sample their architecture select signal on a warm reset. +// The source of the warm reset could be the system power-up state +// machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V +// hartresetreq. +// +// Note that when an Arm core is deselected, its cold reset domain +// is also held in reset, since in particular the SYSRESETREQ bit +// becomes inaccessible once the core is deselected. Note also the +// RISC-V cores do not have a cold reset domain, since their +// corresponding controls are located in the Debug Module. +#define OTP_ARCHSEL_OFFSET _u(0x00000158) +#define OTP_ARCHSEL_BITS _u(0x00000003) +#define OTP_ARCHSEL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_ARCHSEL_CORE1 +// Description : Select architecture for core 1. +// 0x0 -> Switch core 1 to Arm (Cortex-M33) +// 0x1 -> Switch core 1 to RISC-V (Hazard3) +#define OTP_ARCHSEL_CORE1_RESET _u(0x0) +#define OTP_ARCHSEL_CORE1_BITS _u(0x00000002) +#define OTP_ARCHSEL_CORE1_MSB _u(1) +#define OTP_ARCHSEL_CORE1_LSB _u(1) +#define OTP_ARCHSEL_CORE1_ACCESS "RW" +#define OTP_ARCHSEL_CORE1_VALUE_ARM _u(0x0) +#define OTP_ARCHSEL_CORE1_VALUE_RISCV _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_ARCHSEL_CORE0 +// Description : Select architecture for core 0. +// 0x0 -> Switch core 0 to Arm (Cortex-M33) +// 0x1 -> Switch core 0 to RISC-V (Hazard3) +#define OTP_ARCHSEL_CORE0_RESET _u(0x0) +#define OTP_ARCHSEL_CORE0_BITS _u(0x00000001) +#define OTP_ARCHSEL_CORE0_MSB _u(0) +#define OTP_ARCHSEL_CORE0_LSB _u(0) +#define OTP_ARCHSEL_CORE0_ACCESS "RW" +#define OTP_ARCHSEL_CORE0_VALUE_ARM _u(0x0) +#define OTP_ARCHSEL_CORE0_VALUE_RISCV _u(0x1) +// ============================================================================= +// Register : OTP_ARCHSEL_STATUS +// Description : Get the current architecture select state of each core. Cores +// sample the current value of the ARCHSEL register when their +// warm reset is released, at which point the corresponding bit in +// this register will also update. +#define OTP_ARCHSEL_STATUS_OFFSET _u(0x0000015c) +#define OTP_ARCHSEL_STATUS_BITS _u(0x00000003) +#define OTP_ARCHSEL_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_ARCHSEL_STATUS_CORE1 +// Description : Current architecture for core 0. Updated on processor warm +// reset. +// 0x0 -> Core 1 is currently Arm (Cortex-M33) +// 0x1 -> Core 1 is currently RISC-V (Hazard3) +#define OTP_ARCHSEL_STATUS_CORE1_RESET _u(0x0) +#define OTP_ARCHSEL_STATUS_CORE1_BITS _u(0x00000002) +#define OTP_ARCHSEL_STATUS_CORE1_MSB _u(1) +#define OTP_ARCHSEL_STATUS_CORE1_LSB _u(1) +#define OTP_ARCHSEL_STATUS_CORE1_ACCESS "RO" +#define OTP_ARCHSEL_STATUS_CORE1_VALUE_ARM _u(0x0) +#define OTP_ARCHSEL_STATUS_CORE1_VALUE_RISCV _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_ARCHSEL_STATUS_CORE0 +// Description : Current architecture for core 0. Updated on processor warm +// reset. +// 0x0 -> Core 0 is currently Arm (Cortex-M33) +// 0x1 -> Core 0 is currently RISC-V (Hazard3) +#define OTP_ARCHSEL_STATUS_CORE0_RESET _u(0x0) +#define OTP_ARCHSEL_STATUS_CORE0_BITS _u(0x00000001) +#define OTP_ARCHSEL_STATUS_CORE0_MSB _u(0) +#define OTP_ARCHSEL_STATUS_CORE0_LSB _u(0) +#define OTP_ARCHSEL_STATUS_CORE0_ACCESS "RO" +#define OTP_ARCHSEL_STATUS_CORE0_VALUE_ARM _u(0x0) +#define OTP_ARCHSEL_STATUS_CORE0_VALUE_RISCV _u(0x1) +// ============================================================================= +// Register : OTP_BOOTDIS +// Description : Tell the bootrom to ignore scratch register boot vectors (both +// power manager and watchdog) on the next power up. +// +// If an early boot stage has soft-locked some OTP pages in order +// to protect their contents from later stages, there is a risk +// that Secure code running at a later stage can unlock the pages +// by performing a watchdog reset that resets the OTP. +// +// This register can be used to ensure that the bootloader runs as +// normal on the next power up, preventing Secure code at a later +// stage from accessing OTP in its unlocked state. +// +// Should be used in conjunction with the power manager BOOTDIS +// register. +#define OTP_BOOTDIS_OFFSET _u(0x00000160) +#define OTP_BOOTDIS_BITS _u(0x00000003) +#define OTP_BOOTDIS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_BOOTDIS_NEXT +// Description : This flag always ORs writes into its current contents. It can +// be set but not cleared by software. +// +// The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the +// core is powered down. Simultaneously, the BOOTDIS_NEXT bit is +// cleared. Setting this bit means that the boot scratch registers +// will be ignored following the next core power down. +// +// This flag should be set by an early boot stage that has soft- +// locked OTP pages, to prevent later stages from unlocking it via +// watchdog reset. +#define OTP_BOOTDIS_NEXT_RESET _u(0x0) +#define OTP_BOOTDIS_NEXT_BITS _u(0x00000002) +#define OTP_BOOTDIS_NEXT_MSB _u(1) +#define OTP_BOOTDIS_NEXT_LSB _u(1) +#define OTP_BOOTDIS_NEXT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_BOOTDIS_NOW +// Description : When the core is powered down, the current value of +// BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is +// cleared. +// +// The bootrom checks this flag before reading the boot scratch +// registers. If it is set, the bootrom clears it, and ignores the +// BOOT registers. This prevents Secure software from diverting +// the boot path before a bootloader has had the chance to soft +// lock OTP pages containing sensitive data. +#define OTP_BOOTDIS_NOW_RESET _u(0x0) +#define OTP_BOOTDIS_NOW_BITS _u(0x00000001) +#define OTP_BOOTDIS_NOW_MSB _u(0) +#define OTP_BOOTDIS_NOW_LSB _u(0) +#define OTP_BOOTDIS_NOW_ACCESS "WC" +// ============================================================================= +// Register : OTP_INTR +// Description : Raw Interrupts +#define OTP_INTR_OFFSET _u(0x00000164) +#define OTP_INTR_BITS _u(0x0000001f) +#define OTP_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_INTR_APB_RD_NSEC_FAIL +#define OTP_INTR_APB_RD_NSEC_FAIL_RESET _u(0x0) +#define OTP_INTR_APB_RD_NSEC_FAIL_BITS _u(0x00000010) +#define OTP_INTR_APB_RD_NSEC_FAIL_MSB _u(4) +#define OTP_INTR_APB_RD_NSEC_FAIL_LSB _u(4) +#define OTP_INTR_APB_RD_NSEC_FAIL_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : OTP_INTR_APB_RD_SEC_FAIL +#define OTP_INTR_APB_RD_SEC_FAIL_RESET _u(0x0) +#define OTP_INTR_APB_RD_SEC_FAIL_BITS _u(0x00000008) +#define OTP_INTR_APB_RD_SEC_FAIL_MSB _u(3) +#define OTP_INTR_APB_RD_SEC_FAIL_LSB _u(3) +#define OTP_INTR_APB_RD_SEC_FAIL_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : OTP_INTR_APB_DCTRL_FAIL +#define OTP_INTR_APB_DCTRL_FAIL_RESET _u(0x0) +#define OTP_INTR_APB_DCTRL_FAIL_BITS _u(0x00000004) +#define OTP_INTR_APB_DCTRL_FAIL_MSB _u(2) +#define OTP_INTR_APB_DCTRL_FAIL_LSB _u(2) +#define OTP_INTR_APB_DCTRL_FAIL_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : OTP_INTR_SBPI_WR_FAIL +#define OTP_INTR_SBPI_WR_FAIL_RESET _u(0x0) +#define OTP_INTR_SBPI_WR_FAIL_BITS _u(0x00000002) +#define OTP_INTR_SBPI_WR_FAIL_MSB _u(1) +#define OTP_INTR_SBPI_WR_FAIL_LSB _u(1) +#define OTP_INTR_SBPI_WR_FAIL_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : OTP_INTR_SBPI_FLAG_N +#define OTP_INTR_SBPI_FLAG_N_RESET _u(0x0) +#define OTP_INTR_SBPI_FLAG_N_BITS _u(0x00000001) +#define OTP_INTR_SBPI_FLAG_N_MSB _u(0) +#define OTP_INTR_SBPI_FLAG_N_LSB _u(0) +#define OTP_INTR_SBPI_FLAG_N_ACCESS "RO" +// ============================================================================= +// Register : OTP_INTE +// Description : Interrupt Enable +#define OTP_INTE_OFFSET _u(0x00000168) +#define OTP_INTE_BITS _u(0x0000001f) +#define OTP_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_INTE_APB_RD_NSEC_FAIL +#define OTP_INTE_APB_RD_NSEC_FAIL_RESET _u(0x0) +#define OTP_INTE_APB_RD_NSEC_FAIL_BITS _u(0x00000010) +#define OTP_INTE_APB_RD_NSEC_FAIL_MSB _u(4) +#define OTP_INTE_APB_RD_NSEC_FAIL_LSB _u(4) +#define OTP_INTE_APB_RD_NSEC_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTE_APB_RD_SEC_FAIL +#define OTP_INTE_APB_RD_SEC_FAIL_RESET _u(0x0) +#define OTP_INTE_APB_RD_SEC_FAIL_BITS _u(0x00000008) +#define OTP_INTE_APB_RD_SEC_FAIL_MSB _u(3) +#define OTP_INTE_APB_RD_SEC_FAIL_LSB _u(3) +#define OTP_INTE_APB_RD_SEC_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTE_APB_DCTRL_FAIL +#define OTP_INTE_APB_DCTRL_FAIL_RESET _u(0x0) +#define OTP_INTE_APB_DCTRL_FAIL_BITS _u(0x00000004) +#define OTP_INTE_APB_DCTRL_FAIL_MSB _u(2) +#define OTP_INTE_APB_DCTRL_FAIL_LSB _u(2) +#define OTP_INTE_APB_DCTRL_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTE_SBPI_WR_FAIL +#define OTP_INTE_SBPI_WR_FAIL_RESET _u(0x0) +#define OTP_INTE_SBPI_WR_FAIL_BITS _u(0x00000002) +#define OTP_INTE_SBPI_WR_FAIL_MSB _u(1) +#define OTP_INTE_SBPI_WR_FAIL_LSB _u(1) +#define OTP_INTE_SBPI_WR_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTE_SBPI_FLAG_N +#define OTP_INTE_SBPI_FLAG_N_RESET _u(0x0) +#define OTP_INTE_SBPI_FLAG_N_BITS _u(0x00000001) +#define OTP_INTE_SBPI_FLAG_N_MSB _u(0) +#define OTP_INTE_SBPI_FLAG_N_LSB _u(0) +#define OTP_INTE_SBPI_FLAG_N_ACCESS "RW" +// ============================================================================= +// Register : OTP_INTF +// Description : Interrupt Force +#define OTP_INTF_OFFSET _u(0x0000016c) +#define OTP_INTF_BITS _u(0x0000001f) +#define OTP_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_INTF_APB_RD_NSEC_FAIL +#define OTP_INTF_APB_RD_NSEC_FAIL_RESET _u(0x0) +#define OTP_INTF_APB_RD_NSEC_FAIL_BITS _u(0x00000010) +#define OTP_INTF_APB_RD_NSEC_FAIL_MSB _u(4) +#define OTP_INTF_APB_RD_NSEC_FAIL_LSB _u(4) +#define OTP_INTF_APB_RD_NSEC_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTF_APB_RD_SEC_FAIL +#define OTP_INTF_APB_RD_SEC_FAIL_RESET _u(0x0) +#define OTP_INTF_APB_RD_SEC_FAIL_BITS _u(0x00000008) +#define OTP_INTF_APB_RD_SEC_FAIL_MSB _u(3) +#define OTP_INTF_APB_RD_SEC_FAIL_LSB _u(3) +#define OTP_INTF_APB_RD_SEC_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTF_APB_DCTRL_FAIL +#define OTP_INTF_APB_DCTRL_FAIL_RESET _u(0x0) +#define OTP_INTF_APB_DCTRL_FAIL_BITS _u(0x00000004) +#define OTP_INTF_APB_DCTRL_FAIL_MSB _u(2) +#define OTP_INTF_APB_DCTRL_FAIL_LSB _u(2) +#define OTP_INTF_APB_DCTRL_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTF_SBPI_WR_FAIL +#define OTP_INTF_SBPI_WR_FAIL_RESET _u(0x0) +#define OTP_INTF_SBPI_WR_FAIL_BITS _u(0x00000002) +#define OTP_INTF_SBPI_WR_FAIL_MSB _u(1) +#define OTP_INTF_SBPI_WR_FAIL_LSB _u(1) +#define OTP_INTF_SBPI_WR_FAIL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : OTP_INTF_SBPI_FLAG_N +#define OTP_INTF_SBPI_FLAG_N_RESET _u(0x0) +#define OTP_INTF_SBPI_FLAG_N_BITS _u(0x00000001) +#define OTP_INTF_SBPI_FLAG_N_MSB _u(0) +#define OTP_INTF_SBPI_FLAG_N_LSB _u(0) +#define OTP_INTF_SBPI_FLAG_N_ACCESS "RW" +// ============================================================================= +// Register : OTP_INTS +// Description : Interrupt status after masking & forcing +#define OTP_INTS_OFFSET _u(0x00000170) +#define OTP_INTS_BITS _u(0x0000001f) +#define OTP_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : OTP_INTS_APB_RD_NSEC_FAIL +#define OTP_INTS_APB_RD_NSEC_FAIL_RESET _u(0x0) +#define OTP_INTS_APB_RD_NSEC_FAIL_BITS _u(0x00000010) +#define OTP_INTS_APB_RD_NSEC_FAIL_MSB _u(4) +#define OTP_INTS_APB_RD_NSEC_FAIL_LSB _u(4) +#define OTP_INTS_APB_RD_NSEC_FAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_INTS_APB_RD_SEC_FAIL +#define OTP_INTS_APB_RD_SEC_FAIL_RESET _u(0x0) +#define OTP_INTS_APB_RD_SEC_FAIL_BITS _u(0x00000008) +#define OTP_INTS_APB_RD_SEC_FAIL_MSB _u(3) +#define OTP_INTS_APB_RD_SEC_FAIL_LSB _u(3) +#define OTP_INTS_APB_RD_SEC_FAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_INTS_APB_DCTRL_FAIL +#define OTP_INTS_APB_DCTRL_FAIL_RESET _u(0x0) +#define OTP_INTS_APB_DCTRL_FAIL_BITS _u(0x00000004) +#define OTP_INTS_APB_DCTRL_FAIL_MSB _u(2) +#define OTP_INTS_APB_DCTRL_FAIL_LSB _u(2) +#define OTP_INTS_APB_DCTRL_FAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_INTS_SBPI_WR_FAIL +#define OTP_INTS_SBPI_WR_FAIL_RESET _u(0x0) +#define OTP_INTS_SBPI_WR_FAIL_BITS _u(0x00000002) +#define OTP_INTS_SBPI_WR_FAIL_MSB _u(1) +#define OTP_INTS_SBPI_WR_FAIL_LSB _u(1) +#define OTP_INTS_SBPI_WR_FAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_INTS_SBPI_FLAG_N +#define OTP_INTS_SBPI_FLAG_N_RESET _u(0x0) +#define OTP_INTS_SBPI_FLAG_N_BITS _u(0x00000001) +#define OTP_INTS_SBPI_FLAG_N_MSB _u(0) +#define OTP_INTS_SBPI_FLAG_N_LSB _u(0) +#define OTP_INTS_SBPI_FLAG_N_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_OTP_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/otp_data.h b/lib/pico-sdk/rp2350/hardware/regs/otp_data.h new file mode 100644 index 000000000000..57d1d47d8f05 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/otp_data.h @@ -0,0 +1,12373 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : OTP_DATA +// Version : 1 +// Bus type : apb +// Description : Predefined OTP data layout for RP2350 +// ============================================================================= +#ifndef _HARDWARE_REGS_OTP_DATA_H +#define _HARDWARE_REGS_OTP_DATA_H +// ============================================================================= +// Register : OTP_DATA_CHIPID0 +// Description : Bits 15:0 of public device ID. (ECC) +// +// The CHIPID0..3 rows contain a 64-bit random identifier for this +// chip, which can be read from the USB bootloader PICOBOOT +// interface or from the get_sys_info ROM API. +// +// The number of random bits makes the occurrence of twins +// exceedingly unlikely: for example, a fleet of a hundred million +// devices has a 99.97% probability of no twinned IDs. This is +// estimated to be lower than the occurrence of process errors in +// the assignment of sequential random IDs, and for practical +// purposes CHIPID may be treated as unique. +#define OTP_DATA_CHIPID0_ROW _u(0x00000000) +#define OTP_DATA_CHIPID0_BITS _u(0x0000ffff) +#define OTP_DATA_CHIPID0_RESET "-" +#define OTP_DATA_CHIPID0_WIDTH _u(16) +#define OTP_DATA_CHIPID0_MSB _u(15) +#define OTP_DATA_CHIPID0_LSB _u(0) +#define OTP_DATA_CHIPID0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CHIPID1 +// Description : Bits 31:16 of public device ID (ECC) +#define OTP_DATA_CHIPID1_ROW _u(0x00000001) +#define OTP_DATA_CHIPID1_BITS _u(0x0000ffff) +#define OTP_DATA_CHIPID1_RESET "-" +#define OTP_DATA_CHIPID1_WIDTH _u(16) +#define OTP_DATA_CHIPID1_MSB _u(15) +#define OTP_DATA_CHIPID1_LSB _u(0) +#define OTP_DATA_CHIPID1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CHIPID2 +// Description : Bits 47:32 of public device ID (ECC) +#define OTP_DATA_CHIPID2_ROW _u(0x00000002) +#define OTP_DATA_CHIPID2_BITS _u(0x0000ffff) +#define OTP_DATA_CHIPID2_RESET "-" +#define OTP_DATA_CHIPID2_WIDTH _u(16) +#define OTP_DATA_CHIPID2_MSB _u(15) +#define OTP_DATA_CHIPID2_LSB _u(0) +#define OTP_DATA_CHIPID2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CHIPID3 +// Description : Bits 63:48 of public device ID (ECC) +#define OTP_DATA_CHIPID3_ROW _u(0x00000003) +#define OTP_DATA_CHIPID3_BITS _u(0x0000ffff) +#define OTP_DATA_CHIPID3_RESET "-" +#define OTP_DATA_CHIPID3_WIDTH _u(16) +#define OTP_DATA_CHIPID3_MSB _u(15) +#define OTP_DATA_CHIPID3_LSB _u(0) +#define OTP_DATA_CHIPID3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID0 +// Description : Bits 15:0 of private per-device random number (ECC) +// +// The RANDID0..7 rows form a 128-bit random number generated +// during device test. +// +// This ID is not exposed through the USB PICOBOOT GET_INFO +// command or the ROM `get_sys_info()` API. However note that the +// USB PICOBOOT OTP access point can read the entirety of page 0, +// so this value is not meaningfully private unless the USB +// PICOBOOT interface is disabled via the +// DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. +#define OTP_DATA_RANDID0_ROW _u(0x00000004) +#define OTP_DATA_RANDID0_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID0_RESET "-" +#define OTP_DATA_RANDID0_WIDTH _u(16) +#define OTP_DATA_RANDID0_MSB _u(15) +#define OTP_DATA_RANDID0_LSB _u(0) +#define OTP_DATA_RANDID0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID1 +// Description : Bits 31:16 of private per-device random number (ECC) +#define OTP_DATA_RANDID1_ROW _u(0x00000005) +#define OTP_DATA_RANDID1_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID1_RESET "-" +#define OTP_DATA_RANDID1_WIDTH _u(16) +#define OTP_DATA_RANDID1_MSB _u(15) +#define OTP_DATA_RANDID1_LSB _u(0) +#define OTP_DATA_RANDID1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID2 +// Description : Bits 47:32 of private per-device random number (ECC) +#define OTP_DATA_RANDID2_ROW _u(0x00000006) +#define OTP_DATA_RANDID2_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID2_RESET "-" +#define OTP_DATA_RANDID2_WIDTH _u(16) +#define OTP_DATA_RANDID2_MSB _u(15) +#define OTP_DATA_RANDID2_LSB _u(0) +#define OTP_DATA_RANDID2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID3 +// Description : Bits 63:48 of private per-device random number (ECC) +#define OTP_DATA_RANDID3_ROW _u(0x00000007) +#define OTP_DATA_RANDID3_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID3_RESET "-" +#define OTP_DATA_RANDID3_WIDTH _u(16) +#define OTP_DATA_RANDID3_MSB _u(15) +#define OTP_DATA_RANDID3_LSB _u(0) +#define OTP_DATA_RANDID3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID4 +// Description : Bits 79:64 of private per-device random number (ECC) +#define OTP_DATA_RANDID4_ROW _u(0x00000008) +#define OTP_DATA_RANDID4_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID4_RESET "-" +#define OTP_DATA_RANDID4_WIDTH _u(16) +#define OTP_DATA_RANDID4_MSB _u(15) +#define OTP_DATA_RANDID4_LSB _u(0) +#define OTP_DATA_RANDID4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID5 +// Description : Bits 95:80 of private per-device random number (ECC) +#define OTP_DATA_RANDID5_ROW _u(0x00000009) +#define OTP_DATA_RANDID5_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID5_RESET "-" +#define OTP_DATA_RANDID5_WIDTH _u(16) +#define OTP_DATA_RANDID5_MSB _u(15) +#define OTP_DATA_RANDID5_LSB _u(0) +#define OTP_DATA_RANDID5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID6 +// Description : Bits 111:96 of private per-device random number (ECC) +#define OTP_DATA_RANDID6_ROW _u(0x0000000a) +#define OTP_DATA_RANDID6_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID6_RESET "-" +#define OTP_DATA_RANDID6_WIDTH _u(16) +#define OTP_DATA_RANDID6_MSB _u(15) +#define OTP_DATA_RANDID6_LSB _u(0) +#define OTP_DATA_RANDID6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_RANDID7 +// Description : Bits 127:112 of private per-device random number (ECC) +#define OTP_DATA_RANDID7_ROW _u(0x0000000b) +#define OTP_DATA_RANDID7_BITS _u(0x0000ffff) +#define OTP_DATA_RANDID7_RESET "-" +#define OTP_DATA_RANDID7_WIDTH _u(16) +#define OTP_DATA_RANDID7_MSB _u(15) +#define OTP_DATA_RANDID7_LSB _u(0) +#define OTP_DATA_RANDID7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_ROSC_CALIB +// Description : Ring oscillator frequency in kHz, measured during manufacturing +// (ECC) +// +// This is measured at 1.1 V, at room temperature, with the ROSC +// configuration registers in their reset state. +#define OTP_DATA_ROSC_CALIB_ROW _u(0x00000010) +#define OTP_DATA_ROSC_CALIB_BITS _u(0x0000ffff) +#define OTP_DATA_ROSC_CALIB_RESET "-" +#define OTP_DATA_ROSC_CALIB_WIDTH _u(16) +#define OTP_DATA_ROSC_CALIB_MSB _u(15) +#define OTP_DATA_ROSC_CALIB_LSB _u(0) +#define OTP_DATA_ROSC_CALIB_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_LPOSC_CALIB +// Description : Low-power oscillator frequency in Hz, measured during +// manufacturing (ECC) +// +// This is measured at 1.1V, at room temperature, with the LPOSC +// trim register in its reset state. +#define OTP_DATA_LPOSC_CALIB_ROW _u(0x00000011) +#define OTP_DATA_LPOSC_CALIB_BITS _u(0x0000ffff) +#define OTP_DATA_LPOSC_CALIB_RESET "-" +#define OTP_DATA_LPOSC_CALIB_WIDTH _u(16) +#define OTP_DATA_LPOSC_CALIB_MSB _u(15) +#define OTP_DATA_LPOSC_CALIB_LSB _u(0) +#define OTP_DATA_LPOSC_CALIB_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_NUM_GPIOS +// Description : The number of main user GPIOs (bank 0). Should read 48 in the +// QFN80 package, and 30 in the QFN60 package. (ECC) +#define OTP_DATA_NUM_GPIOS_ROW _u(0x00000018) +#define OTP_DATA_NUM_GPIOS_BITS _u(0x000000ff) +#define OTP_DATA_NUM_GPIOS_RESET "-" +#define OTP_DATA_NUM_GPIOS_WIDTH _u(16) +#define OTP_DATA_NUM_GPIOS_MSB _u(7) +#define OTP_DATA_NUM_GPIOS_LSB _u(0) +#define OTP_DATA_NUM_GPIOS_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_INFO_CRC0 +// Description : Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b +// (polynomial 0x4c11db7, input reflected, output reflected, seed +// all-ones, final XOR all-ones) (ECC) +#define OTP_DATA_INFO_CRC0_ROW _u(0x00000036) +#define OTP_DATA_INFO_CRC0_BITS _u(0x0000ffff) +#define OTP_DATA_INFO_CRC0_RESET "-" +#define OTP_DATA_INFO_CRC0_WIDTH _u(16) +#define OTP_DATA_INFO_CRC0_MSB _u(15) +#define OTP_DATA_INFO_CRC0_LSB _u(0) +#define OTP_DATA_INFO_CRC0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_INFO_CRC1 +// Description : Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) +#define OTP_DATA_INFO_CRC1_ROW _u(0x00000037) +#define OTP_DATA_INFO_CRC1_BITS _u(0x0000ffff) +#define OTP_DATA_INFO_CRC1_RESET "-" +#define OTP_DATA_INFO_CRC1_WIDTH _u(16) +#define OTP_DATA_INFO_CRC1_MSB _u(15) +#define OTP_DATA_INFO_CRC1_LSB _u(0) +#define OTP_DATA_INFO_CRC1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0 +// Description : Page 0 critical boot flags (RBIT-8) +#define OTP_DATA_CRIT0_ROW _u(0x00000038) +#define OTP_DATA_CRIT0_BITS _u(0x00000003) +#define OTP_DATA_CRIT0_RESET _u(0x00000000) +#define OTP_DATA_CRIT0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT0_RISCV_DISABLE +// Description : Permanently disable RISC-V processors (Hazard3) +#define OTP_DATA_CRIT0_RISCV_DISABLE_RESET "-" +#define OTP_DATA_CRIT0_RISCV_DISABLE_BITS _u(0x00000002) +#define OTP_DATA_CRIT0_RISCV_DISABLE_MSB _u(1) +#define OTP_DATA_CRIT0_RISCV_DISABLE_LSB _u(1) +#define OTP_DATA_CRIT0_RISCV_DISABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT0_ARM_DISABLE +// Description : Permanently disable ARM processors (Cortex-M33) +#define OTP_DATA_CRIT0_ARM_DISABLE_RESET "-" +#define OTP_DATA_CRIT0_ARM_DISABLE_BITS _u(0x00000001) +#define OTP_DATA_CRIT0_ARM_DISABLE_MSB _u(0) +#define OTP_DATA_CRIT0_ARM_DISABLE_LSB _u(0) +#define OTP_DATA_CRIT0_ARM_DISABLE_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0_R1 +// Description : Redundant copy of CRIT0 +#define OTP_DATA_CRIT0_R1_ROW _u(0x00000039) +#define OTP_DATA_CRIT0_R1_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT0_R1_RESET "-" +#define OTP_DATA_CRIT0_R1_WIDTH _u(24) +#define OTP_DATA_CRIT0_R1_MSB _u(23) +#define OTP_DATA_CRIT0_R1_LSB _u(0) +#define OTP_DATA_CRIT0_R1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0_R2 +// Description : Redundant copy of CRIT0 +#define OTP_DATA_CRIT0_R2_ROW _u(0x0000003a) +#define OTP_DATA_CRIT0_R2_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT0_R2_RESET "-" +#define OTP_DATA_CRIT0_R2_WIDTH _u(24) +#define OTP_DATA_CRIT0_R2_MSB _u(23) +#define OTP_DATA_CRIT0_R2_LSB _u(0) +#define OTP_DATA_CRIT0_R2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0_R3 +// Description : Redundant copy of CRIT0 +#define OTP_DATA_CRIT0_R3_ROW _u(0x0000003b) +#define OTP_DATA_CRIT0_R3_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT0_R3_RESET "-" +#define OTP_DATA_CRIT0_R3_WIDTH _u(24) +#define OTP_DATA_CRIT0_R3_MSB _u(23) +#define OTP_DATA_CRIT0_R3_LSB _u(0) +#define OTP_DATA_CRIT0_R3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0_R4 +// Description : Redundant copy of CRIT0 +#define OTP_DATA_CRIT0_R4_ROW _u(0x0000003c) +#define OTP_DATA_CRIT0_R4_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT0_R4_RESET "-" +#define OTP_DATA_CRIT0_R4_WIDTH _u(24) +#define OTP_DATA_CRIT0_R4_MSB _u(23) +#define OTP_DATA_CRIT0_R4_LSB _u(0) +#define OTP_DATA_CRIT0_R4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0_R5 +// Description : Redundant copy of CRIT0 +#define OTP_DATA_CRIT0_R5_ROW _u(0x0000003d) +#define OTP_DATA_CRIT0_R5_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT0_R5_RESET "-" +#define OTP_DATA_CRIT0_R5_WIDTH _u(24) +#define OTP_DATA_CRIT0_R5_MSB _u(23) +#define OTP_DATA_CRIT0_R5_LSB _u(0) +#define OTP_DATA_CRIT0_R5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0_R6 +// Description : Redundant copy of CRIT0 +#define OTP_DATA_CRIT0_R6_ROW _u(0x0000003e) +#define OTP_DATA_CRIT0_R6_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT0_R6_RESET "-" +#define OTP_DATA_CRIT0_R6_WIDTH _u(24) +#define OTP_DATA_CRIT0_R6_MSB _u(23) +#define OTP_DATA_CRIT0_R6_LSB _u(0) +#define OTP_DATA_CRIT0_R6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT0_R7 +// Description : Redundant copy of CRIT0 +#define OTP_DATA_CRIT0_R7_ROW _u(0x0000003f) +#define OTP_DATA_CRIT0_R7_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT0_R7_RESET "-" +#define OTP_DATA_CRIT0_R7_WIDTH _u(24) +#define OTP_DATA_CRIT0_R7_MSB _u(23) +#define OTP_DATA_CRIT0_R7_LSB _u(0) +#define OTP_DATA_CRIT0_R7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1 +// Description : Page 1 critical boot flags (RBIT-8) +#define OTP_DATA_CRIT1_ROW _u(0x00000040) +#define OTP_DATA_CRIT1_BITS _u(0x0000007f) +#define OTP_DATA_CRIT1_RESET _u(0x00000000) +#define OTP_DATA_CRIT1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS +// Description : Increase the sensitivity of the glitch detectors from their +// default. +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_RESET "-" +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_BITS _u(0x00000060) +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_MSB _u(6) +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_LSB _u(5) +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_SENS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE +// Description : Arm the glitch detectors to reset the system if an abnormal +// clock/power event is observed. +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_RESET "-" +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_BITS _u(0x00000010) +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_MSB _u(4) +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_LSB _u(4) +#define OTP_DATA_CRIT1_GLITCH_DETECTOR_ENABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT1_BOOT_ARCH +// Description : Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if +// ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set. +#define OTP_DATA_CRIT1_BOOT_ARCH_RESET "-" +#define OTP_DATA_CRIT1_BOOT_ARCH_BITS _u(0x00000008) +#define OTP_DATA_CRIT1_BOOT_ARCH_MSB _u(3) +#define OTP_DATA_CRIT1_BOOT_ARCH_LSB _u(3) +#define OTP_DATA_CRIT1_BOOT_ARCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT1_DEBUG_DISABLE +// Description : Disable all debug access +#define OTP_DATA_CRIT1_DEBUG_DISABLE_RESET "-" +#define OTP_DATA_CRIT1_DEBUG_DISABLE_BITS _u(0x00000004) +#define OTP_DATA_CRIT1_DEBUG_DISABLE_MSB _u(2) +#define OTP_DATA_CRIT1_DEBUG_DISABLE_LSB _u(2) +#define OTP_DATA_CRIT1_DEBUG_DISABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE +// Description : Disable Secure debug access +#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_RESET "-" +#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_BITS _u(0x00000002) +#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_MSB _u(1) +#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_LSB _u(1) +#define OTP_DATA_CRIT1_SECURE_DEBUG_DISABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_CRIT1_SECURE_BOOT_ENABLE +// Description : Enable boot signature enforcement, and permanently disable the +// RISC-V cores. +#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_RESET "-" +#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_BITS _u(0x00000001) +#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_MSB _u(0) +#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_LSB _u(0) +#define OTP_DATA_CRIT1_SECURE_BOOT_ENABLE_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1_R1 +// Description : Redundant copy of CRIT1 +#define OTP_DATA_CRIT1_R1_ROW _u(0x00000041) +#define OTP_DATA_CRIT1_R1_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT1_R1_RESET "-" +#define OTP_DATA_CRIT1_R1_WIDTH _u(24) +#define OTP_DATA_CRIT1_R1_MSB _u(23) +#define OTP_DATA_CRIT1_R1_LSB _u(0) +#define OTP_DATA_CRIT1_R1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1_R2 +// Description : Redundant copy of CRIT1 +#define OTP_DATA_CRIT1_R2_ROW _u(0x00000042) +#define OTP_DATA_CRIT1_R2_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT1_R2_RESET "-" +#define OTP_DATA_CRIT1_R2_WIDTH _u(24) +#define OTP_DATA_CRIT1_R2_MSB _u(23) +#define OTP_DATA_CRIT1_R2_LSB _u(0) +#define OTP_DATA_CRIT1_R2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1_R3 +// Description : Redundant copy of CRIT1 +#define OTP_DATA_CRIT1_R3_ROW _u(0x00000043) +#define OTP_DATA_CRIT1_R3_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT1_R3_RESET "-" +#define OTP_DATA_CRIT1_R3_WIDTH _u(24) +#define OTP_DATA_CRIT1_R3_MSB _u(23) +#define OTP_DATA_CRIT1_R3_LSB _u(0) +#define OTP_DATA_CRIT1_R3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1_R4 +// Description : Redundant copy of CRIT1 +#define OTP_DATA_CRIT1_R4_ROW _u(0x00000044) +#define OTP_DATA_CRIT1_R4_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT1_R4_RESET "-" +#define OTP_DATA_CRIT1_R4_WIDTH _u(24) +#define OTP_DATA_CRIT1_R4_MSB _u(23) +#define OTP_DATA_CRIT1_R4_LSB _u(0) +#define OTP_DATA_CRIT1_R4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1_R5 +// Description : Redundant copy of CRIT1 +#define OTP_DATA_CRIT1_R5_ROW _u(0x00000045) +#define OTP_DATA_CRIT1_R5_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT1_R5_RESET "-" +#define OTP_DATA_CRIT1_R5_WIDTH _u(24) +#define OTP_DATA_CRIT1_R5_MSB _u(23) +#define OTP_DATA_CRIT1_R5_LSB _u(0) +#define OTP_DATA_CRIT1_R5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1_R6 +// Description : Redundant copy of CRIT1 +#define OTP_DATA_CRIT1_R6_ROW _u(0x00000046) +#define OTP_DATA_CRIT1_R6_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT1_R6_RESET "-" +#define OTP_DATA_CRIT1_R6_WIDTH _u(24) +#define OTP_DATA_CRIT1_R6_MSB _u(23) +#define OTP_DATA_CRIT1_R6_LSB _u(0) +#define OTP_DATA_CRIT1_R6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_CRIT1_R7 +// Description : Redundant copy of CRIT1 +#define OTP_DATA_CRIT1_R7_ROW _u(0x00000047) +#define OTP_DATA_CRIT1_R7_BITS _u(0x00ffffff) +#define OTP_DATA_CRIT1_R7_RESET "-" +#define OTP_DATA_CRIT1_R7_WIDTH _u(24) +#define OTP_DATA_CRIT1_R7_MSB _u(23) +#define OTP_DATA_CRIT1_R7_LSB _u(0) +#define OTP_DATA_CRIT1_R7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOT_FLAGS0 +// Description : Disable/Enable boot paths/features in the RP2350 mask ROM. +// Disables always supersede enables. Enables are provided where +// there are other configurations in OTP that must be valid. +// (RBIT-3) +#define OTP_DATA_BOOT_FLAGS0_ROW _u(0x00000048) +#define OTP_DATA_BOOT_FLAGS0_BITS _u(0x003fffff) +#define OTP_DATA_BOOT_FLAGS0_RESET _u(0x00000000) +#define OTP_DATA_BOOT_FLAGS0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT +#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_BITS _u(0x00200000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_MSB _u(21) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_LSB _u(21) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_SRAM_WINDOW_BOOT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY +// Description : Disable all access to XIP after entering an SRAM binary. +// +// Note that this will cause bootrom APIs that access XIP to fail, +// including APIs that interact with the partition table. +#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_BITS _u(0x00100000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_MSB _u(20) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_LSB _u(20) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_XIP_ACCESS_ON_SRAM_ENTRY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_BITS _u(0x00080000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_MSB _u(19) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_LSB _u(19) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_UART_BOOT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_BITS _u(0x00040000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_MSB _u(18) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_LSB _u(18) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_PICOBOOT_IFC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_BITS _u(0x00020000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_MSB _u(17) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_LSB _u(17) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_USB_MSD_IFC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH +#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_BITS _u(0x00010000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_MSB _u(16) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_LSB _u(16) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_WATCHDOG_SCRATCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH +#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_BITS _u(0x00008000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_MSB _u(15) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_LSB _u(15) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_POWER_SCRATCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT +// Description : Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN +// will be loaded, starting from OTPBOOT_SRC, into the SRAM +// location specified by OTPBOOT_DST1 and OTPBOOT_DST0. +// +// The loaded program image is stored with ECC, 16 bits per row, +// and must contain a valid IMAGE_DEF. Do not set this bit without +// first programming an image into OTP and configuring +// OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. +// +// Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of +// OTP rows. Equivalently, the image must be a multiple of 32 bits +// in size, and must start at a 32-bit-aligned address in the ECC +// read data address window. +#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_BITS _u(0x00004000) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_MSB _u(14) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_LSB _u(14) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_OTP_BOOT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT +// Description : Takes precedence over ENABLE_OTP_BOOT. +#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_BITS _u(0x00002000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_MSB _u(13) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_LSB _u(13) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_OTP_BOOT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT +#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_BITS _u(0x00001000) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_MSB _u(12) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_LSB _u(12) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_FLASH_BOOT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED +// Description : Require binaries to have a rollback version. Set automatically +// the first time a binary with a rollback version is booted. +#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_BITS _u(0x00000800) +#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_MSB _u(11) +#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_LSB _u(11) +#define OTP_DATA_BOOT_FLAGS0_ROLLBACK_REQUIRED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE +// Description : Require a partition table to be hashed (if not signed) +#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_BITS _u(0x00000400) +#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_MSB _u(10) +#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_LSB _u(10) +#define OTP_DATA_BOOT_FLAGS0_HASHED_PARTITION_TABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE +// Description : Require a partition table to be signed +#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_BITS _u(0x00000200) +#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_MSB _u(9) +#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_LSB _u(9) +#define OTP_DATA_BOOT_FLAGS0_SECURE_PARTITION_TABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH +// Description : Disable auto-switch of CPU architecture on boot when the (only) +// binary to be booted is for the other Arm/RISC-V architecture +// and both architectures are enabled +#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_BITS _u(0x00000100) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_MSB _u(8) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_LSB _u(8) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_AUTO_SWITCH_ARCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY +// Description : Restrict flash boot path to use of a single binary at the start +// of flash +#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_BITS _u(0x00000080) +#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_MSB _u(7) +#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_LSB _u(7) +#define OTP_DATA_BOOT_FLAGS0_SINGLE_FLASH_BINARY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE +// Description : Override the limit for default flash metadata scanning. +// +// The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure +// FLASH_PARTITION_SLOT_SIZE is valid before setting this bit +#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_BITS _u(0x00000040) +#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_MSB _u(6) +#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_LSB _u(6) +#define OTP_DATA_BOOT_FLAGS0_OVERRIDE_FLASH_PARTITION_SLOT_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE +// Description : Mark FLASH_DEVINFO as containing valid, ECC'd data which +// describes external flash devices. +#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_BITS _u(0x00000020) +#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_MSB _u(5) +#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_LSB _u(5) +#define OTP_DATA_BOOT_FLAGS0_FLASH_DEVINFO_ENABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV +// Description : Enable quartering of ROSC divisor during signature check, to +// reduce secure boot time +#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_BITS _u(0x00000010) +#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_MSB _u(4) +#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_LSB _u(4) +#define OTP_DATA_BOOT_FLAGS0_FAST_SIGCHECK_ROSC_DIV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8 +// Description : If 1, configure the QSPI pads for 1.8 V operation when +// accessing flash for the first time from the bootrom, using the +// VOLTAGE_SELECT register for the QSPI pads bank. This slightly +// improves the input timing of the pads at low voltages, but does +// not affect their output characteristics. +// +// If 0, leave VOLTAGE_SELECT in its reset state (suitable for +// operation at and above 2.5 V) +#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_BITS _u(0x00000008) +#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_MSB _u(3) +#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_LSB _u(3) +#define OTP_DATA_BOOT_FLAGS0_FLASH_IO_VOLTAGE_1V8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG +// Description : Enable loading of the non-default XOSC and PLL configuration +// before entering BOOTSEL mode. +// +// Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly +// programmed before setting this bit. +// +// If this bit is set, user software may use the contents of +// BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based +// on the fixed USB boot frequency of 48 MHz. +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_BITS _u(0x00000004) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_MSB _u(2) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_LSB _u(2) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED +// Description : Enable bootloader activity LED. If set, bootsel_led_cfg is +// assumed to be valid +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_BITS _u(0x00000002) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_MSB _u(1) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_LSB _u(1) +#define OTP_DATA_BOOT_FLAGS0_ENABLE_BOOTSEL_LED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2 +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_BITS _u(0x00000001) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_MSB _u(0) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_LSB _u(0) +#define OTP_DATA_BOOT_FLAGS0_DISABLE_BOOTSEL_EXEC2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOT_FLAGS0_R1 +// Description : Redundant copy of BOOT_FLAGS0 +#define OTP_DATA_BOOT_FLAGS0_R1_ROW _u(0x00000049) +#define OTP_DATA_BOOT_FLAGS0_R1_BITS _u(0x00ffffff) +#define OTP_DATA_BOOT_FLAGS0_R1_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_R1_WIDTH _u(24) +#define OTP_DATA_BOOT_FLAGS0_R1_MSB _u(23) +#define OTP_DATA_BOOT_FLAGS0_R1_LSB _u(0) +#define OTP_DATA_BOOT_FLAGS0_R1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOT_FLAGS0_R2 +// Description : Redundant copy of BOOT_FLAGS0 +#define OTP_DATA_BOOT_FLAGS0_R2_ROW _u(0x0000004a) +#define OTP_DATA_BOOT_FLAGS0_R2_BITS _u(0x00ffffff) +#define OTP_DATA_BOOT_FLAGS0_R2_RESET "-" +#define OTP_DATA_BOOT_FLAGS0_R2_WIDTH _u(24) +#define OTP_DATA_BOOT_FLAGS0_R2_MSB _u(23) +#define OTP_DATA_BOOT_FLAGS0_R2_LSB _u(0) +#define OTP_DATA_BOOT_FLAGS0_R2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOT_FLAGS1 +// Description : Disable/Enable boot paths/features in the RP2350 mask ROM. +// Disables always supersede enables. Enables are provided where +// there are other configurations in OTP that must be valid. +// (RBIT-3) +#define OTP_DATA_BOOT_FLAGS1_ROW _u(0x0000004b) +#define OTP_DATA_BOOT_FLAGS1_BITS _u(0x000f0f0f) +#define OTP_DATA_BOOT_FLAGS1_RESET _u(0x00000000) +#define OTP_DATA_BOOT_FLAGS1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP +// Description : Enable entering BOOTSEL mode via double-tap of the RUN/RSTn +// pin. Adds a significant delay to boot time, as configured by +// DOUBLE_TAP_DELAY. +// +// This functions by waiting at startup (i.e. following a reset) +// to see if a second reset is applied soon afterward. The second +// reset is detected by the bootrom with help of the +// POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the +// external reset pin, and the bootrom enters BOOTSEL mode +// (NSBOOT) to await further instruction over USB or UART. +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_RESET "-" +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_BITS _u(0x00080000) +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_MSB _u(19) +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_LSB _u(19) +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY +// Description : Adjust how long to wait for a second reset when double tap +// BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 +// milliseconds, and each unit of this field adds an additional 50 +// milliseconds. +// +// For example, settings this field to its maximum value of 7 will +// cause the chip to wait for 400 milliseconds at boot to check +// for a second reset which requests entry to BOOTSEL mode. +// +// 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate +// value. +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_RESET "-" +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_BITS _u(0x00070000) +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_MSB _u(18) +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_LSB _u(16) +#define OTP_DATA_BOOT_FLAGS1_DOUBLE_TAP_DELAY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS1_KEY_INVALID +// Description : Mark a boot key as invalid, or prevent it from ever becoming +// valid. The bootrom will ignore any boot key marked as invalid +// during secure boot signature checks. +// +// Each bit in this field corresponds to one of the four 256-bit +// boot key hashes that may be stored in page 2 of the OTP. +// +// When provisioning boot keys, it's recommended to mark any boot +// key slots you don't intend to use as KEY_INVALID, so that +// spurious keys can not be installed at a later time. +#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_RESET "-" +#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_BITS _u(0x00000f00) +#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_MSB _u(11) +#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_LSB _u(8) +#define OTP_DATA_BOOT_FLAGS1_KEY_INVALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOT_FLAGS1_KEY_VALID +// Description : Mark each of the possible boot keys as valid. The bootrom will +// check signatures against all valid boot keys, and ignore +// invalid boot keys. +// +// Each bit in this field corresponds to one of the four 256-bit +// boot key hashes that may be stored in page 2 of the OTP. +// +// A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit +// is set. Boot keys are considered valid only when KEY_VALID is +// set and KEY_INVALID is clear. +// +// Do not mark a boot key as KEY_VALID if it does not contain a +// valid SHA-256 hash of your secp256k1 public key. Verify keys +// after programming, before setting the KEY_VALID bits -- a boot +// key with uncorrectable ECC faults will render your device +// unbootable if secure boot is enabled. +// +// Do not enable secure boot without first installing a valid key. +// This will render your device unbootable. +#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_RESET "-" +#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_BITS _u(0x0000000f) +#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_MSB _u(3) +#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_LSB _u(0) +#define OTP_DATA_BOOT_FLAGS1_KEY_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOT_FLAGS1_R1 +// Description : Redundant copy of BOOT_FLAGS1 +#define OTP_DATA_BOOT_FLAGS1_R1_ROW _u(0x0000004c) +#define OTP_DATA_BOOT_FLAGS1_R1_BITS _u(0x00ffffff) +#define OTP_DATA_BOOT_FLAGS1_R1_RESET "-" +#define OTP_DATA_BOOT_FLAGS1_R1_WIDTH _u(24) +#define OTP_DATA_BOOT_FLAGS1_R1_MSB _u(23) +#define OTP_DATA_BOOT_FLAGS1_R1_LSB _u(0) +#define OTP_DATA_BOOT_FLAGS1_R1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOT_FLAGS1_R2 +// Description : Redundant copy of BOOT_FLAGS1 +#define OTP_DATA_BOOT_FLAGS1_R2_ROW _u(0x0000004d) +#define OTP_DATA_BOOT_FLAGS1_R2_BITS _u(0x00ffffff) +#define OTP_DATA_BOOT_FLAGS1_R2_RESET "-" +#define OTP_DATA_BOOT_FLAGS1_R2_WIDTH _u(24) +#define OTP_DATA_BOOT_FLAGS1_R2_MSB _u(23) +#define OTP_DATA_BOOT_FLAGS1_R2_LSB _u(0) +#define OTP_DATA_BOOT_FLAGS1_R2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_DEFAULT_BOOT_VERSION0 +// Description : Default boot version thermometer counter, bits 23:0 (RBIT-3) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_ROW _u(0x0000004e) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_BITS _u(0x00ffffff) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_RESET "-" +#define OTP_DATA_DEFAULT_BOOT_VERSION0_WIDTH _u(24) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_MSB _u(23) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_LSB _u(0) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_DEFAULT_BOOT_VERSION0_R1 +// Description : Redundant copy of DEFAULT_BOOT_VERSION0 +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_ROW _u(0x0000004f) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_BITS _u(0x00ffffff) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_RESET "-" +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_WIDTH _u(24) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_MSB _u(23) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_LSB _u(0) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_DEFAULT_BOOT_VERSION0_R2 +// Description : Redundant copy of DEFAULT_BOOT_VERSION0 +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_ROW _u(0x00000050) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_BITS _u(0x00ffffff) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_RESET "-" +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_WIDTH _u(24) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_MSB _u(23) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_LSB _u(0) +#define OTP_DATA_DEFAULT_BOOT_VERSION0_R2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_DEFAULT_BOOT_VERSION1 +// Description : Default boot version thermometer counter, bits 47:24 (RBIT-3) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_ROW _u(0x00000051) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_BITS _u(0x00ffffff) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_RESET "-" +#define OTP_DATA_DEFAULT_BOOT_VERSION1_WIDTH _u(24) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_MSB _u(23) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_LSB _u(0) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_DEFAULT_BOOT_VERSION1_R1 +// Description : Redundant copy of DEFAULT_BOOT_VERSION1 +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_ROW _u(0x00000052) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_BITS _u(0x00ffffff) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_RESET "-" +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_WIDTH _u(24) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_MSB _u(23) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_LSB _u(0) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_DEFAULT_BOOT_VERSION1_R2 +// Description : Redundant copy of DEFAULT_BOOT_VERSION1 +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_ROW _u(0x00000053) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_BITS _u(0x00ffffff) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_RESET "-" +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_WIDTH _u(24) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_MSB _u(23) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_LSB _u(0) +#define OTP_DATA_DEFAULT_BOOT_VERSION1_R2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_FLASH_DEVINFO +// Description : Stores information about external flash device(s). (ECC) +// +// Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. +#define OTP_DATA_FLASH_DEVINFO_ROW _u(0x00000054) +#define OTP_DATA_FLASH_DEVINFO_BITS _u(0x0000ffbf) +#define OTP_DATA_FLASH_DEVINFO_RESET _u(0x00000000) +#define OTP_DATA_FLASH_DEVINFO_WIDTH _u(16) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_FLASH_DEVINFO_CS1_SIZE +// Description : The size of the flash/PSRAM device on chip select 1 +// (addressable at 0x11000000 through 0x11ffffff). +// +// A value of zero is decoded as a size of zero (no device). +// Nonzero values are decoded as 4kiB << CS1_SIZE. For example, +// four megabytes is encoded with a CS1_SIZE value of 10, and 16 +// megabytes is encoded with a CS1_SIZE value of 12. +// +// When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of +// zero is used. +// 0x0 -> NONE +// 0x1 -> 8K +// 0x2 -> 16K +// 0x3 -> 32K +// 0x4 -> 64k +// 0x5 -> 128K +// 0x6 -> 256K +// 0x7 -> 512K +// 0x8 -> 1M +// 0x9 -> 2M +// 0xa -> 4M +// 0xb -> 8M +// 0xc -> 16M +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_RESET "-" +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_BITS _u(0x0000f000) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_MSB _u(15) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_LSB _u(12) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_ACCESS "RO" +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_NONE _u(0x0) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_8K _u(0x1) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_16K _u(0x2) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_32K _u(0x3) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_64K _u(0x4) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_128K _u(0x5) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_256K _u(0x6) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_512K _u(0x7) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_1M _u(0x8) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_2M _u(0x9) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_4M _u(0xa) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_8M _u(0xb) +#define OTP_DATA_FLASH_DEVINFO_CS1_SIZE_VALUE_16M _u(0xc) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_FLASH_DEVINFO_CS0_SIZE +// Description : The size of the flash/PSRAM device on chip select 0 +// (addressable at 0x10000000 through 0x10ffffff). +// +// A value of zero is decoded as a size of zero (no device). +// Nonzero values are decoded as 4kiB << CS0_SIZE. For example, +// four megabytes is encoded with a CS0_SIZE value of 10, and 16 +// megabytes is encoded with a CS0_SIZE value of 12. +// +// When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of +// 12 (16 MiB) is used. +// 0x0 -> NONE +// 0x1 -> 8K +// 0x2 -> 16K +// 0x3 -> 32K +// 0x4 -> 64k +// 0x5 -> 128K +// 0x6 -> 256K +// 0x7 -> 512K +// 0x8 -> 1M +// 0x9 -> 2M +// 0xa -> 4M +// 0xb -> 8M +// 0xc -> 16M +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_RESET "-" +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_BITS _u(0x00000f00) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_MSB _u(11) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_LSB _u(8) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_ACCESS "RO" +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_NONE _u(0x0) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_8K _u(0x1) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_16K _u(0x2) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_32K _u(0x3) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_64K _u(0x4) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_128K _u(0x5) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_256K _u(0x6) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_512K _u(0x7) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_1M _u(0x8) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_2M _u(0x9) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_4M _u(0xa) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_8M _u(0xb) +#define OTP_DATA_FLASH_DEVINFO_CS0_SIZE_VALUE_16M _u(0xc) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED +// Description : If true, all attached devices are assumed to support (or +// ignore, in the case of PSRAM) a block erase command with a +// command prefix of D8h, an erase size of 64 kiB, and a 24-bit +// address. Almost all 25-series flash devices support this +// command. +// +// If set, the bootrom will use the D8h erase command where it is +// able, to accelerate bulk erase operations. This makes flash +// programming faster. +// +// When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field +// defaults to false. +#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_RESET "-" +#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_BITS _u(0x00000080) +#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_MSB _u(7) +#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_LSB _u(7) +#define OTP_DATA_FLASH_DEVINFO_D8H_ERASE_SUPPORTED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_FLASH_DEVINFO_CS1_GPIO +// Description : Indicate a GPIO number to be used for the secondary flash chip +// select (CS1), which selects the external QSPI device mapped at +// system addresses 0x11000000 through 0x11ffffff. There is no +// such configuration for CS0, as the primary chip select has a +// dedicated pin. +// +// On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. +// +// Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the +// bootrom will automatically configure this GPIO as a second chip +// select upon entering the flash boot path, or entering any other +// path that may use the QSPI flash interface, such as BOOTSEL +// mode (nsboot). +#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_RESET "-" +#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_BITS _u(0x0000003f) +#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_MSB _u(5) +#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_LSB _u(0) +#define OTP_DATA_FLASH_DEVINFO_CS1_GPIO_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_FLASH_PARTITION_SLOT_SIZE +// Description : Gap between partition table slot 0 and slot 1 at the start of +// flash (the default size is 4096 bytes) (ECC) Enabled by the +// OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size +// is 4096 * (value + 1) +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_ROW _u(0x00000055) +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_BITS _u(0x0000ffff) +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_RESET "-" +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_WIDTH _u(16) +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_MSB _u(15) +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_LSB _u(0) +#define OTP_DATA_FLASH_PARTITION_SLOT_SIZE_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTSEL_LED_CFG +// Description : Pin configuration for LED status, used by USB bootloader. (ECC) +// Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. +#define OTP_DATA_BOOTSEL_LED_CFG_ROW _u(0x00000056) +#define OTP_DATA_BOOTSEL_LED_CFG_BITS _u(0x0000013f) +#define OTP_DATA_BOOTSEL_LED_CFG_RESET _u(0x00000000) +#define OTP_DATA_BOOTSEL_LED_CFG_WIDTH _u(16) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW +// Description : LED is active-low. (Default: active-high.) +#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_RESET "-" +#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_BITS _u(0x00000100) +#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_MSB _u(8) +#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_LSB _u(8) +#define OTP_DATA_BOOTSEL_LED_CFG_ACTIVELOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_LED_CFG_PIN +// Description : GPIO index to use for bootloader activity LED. +#define OTP_DATA_BOOTSEL_LED_CFG_PIN_RESET "-" +#define OTP_DATA_BOOTSEL_LED_CFG_PIN_BITS _u(0x0000003f) +#define OTP_DATA_BOOTSEL_LED_CFG_PIN_MSB _u(5) +#define OTP_DATA_BOOTSEL_LED_CFG_PIN_LSB _u(0) +#define OTP_DATA_BOOTSEL_LED_CFG_PIN_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTSEL_PLL_CFG +// Description : Optional PLL configuration for BOOTSEL mode. (ECC) +// +// This should be configured to produce an exact 48 MHz based on +// the crystal oscillator frequency. User mode software may also +// use this value to calculate the expected crystal frequency +// based on an assumed 48 MHz PLL output. +// +// If no configuration is given, the crystal is assumed to be 12 +// MHz. +// +// The PLL frequency can be calculated as: +// +// PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x +// POSTDIV2) +// +// Conversely the crystal frequency can be calculated as: +// +// XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / +// FBDIV +// +// (Note the +1 on REFDIV is because the value stored in this OTP +// location is the actual divisor value minus one.) +// +// Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is +// set in BOOT_FLAGS0. That bit should be set only after this row +// and BOOTSEL_XOSC_CFG are both correctly programmed. +#define OTP_DATA_BOOTSEL_PLL_CFG_ROW _u(0x00000057) +#define OTP_DATA_BOOTSEL_PLL_CFG_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTSEL_PLL_CFG_RESET _u(0x00000000) +#define OTP_DATA_BOOTSEL_PLL_CFG_WIDTH _u(16) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_PLL_CFG_REFDIV +// Description : PLL reference divisor, minus one. +// +// Programming a value of 0 means a reference divisor of 1. +// Programming a value of 1 means a reference divisor of 2 (for +// exceptionally fast XIN inputs) +#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_RESET "-" +#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_BITS _u(0x00008000) +#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_MSB _u(15) +#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_LSB _u(15) +#define OTP_DATA_BOOTSEL_PLL_CFG_REFDIV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2 +// Description : PLL post-divide 2 divisor, in the range 1..7 inclusive. +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_RESET "-" +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_BITS _u(0x00007000) +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_MSB _u(14) +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_LSB _u(12) +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1 +// Description : PLL post-divide 1 divisor, in the range 1..7 inclusive. +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_RESET "-" +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_BITS _u(0x00000e00) +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_MSB _u(11) +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_LSB _u(9) +#define OTP_DATA_BOOTSEL_PLL_CFG_POSTDIV1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_PLL_CFG_FBDIV +// Description : PLL feedback divisor, in the range 16..320 inclusive. +#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_RESET "-" +#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_BITS _u(0x000001ff) +#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_MSB _u(8) +#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_LSB _u(0) +#define OTP_DATA_BOOTSEL_PLL_CFG_FBDIV_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTSEL_XOSC_CFG +// Description : Non-default crystal oscillator configuration for the USB +// bootloader. (ECC) +// +// These values may also be used by user code configuring the +// crystal oscillator. +// +// Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is +// set in BOOT_FLAGS0. That bit should be set only after this row +// and BOOTSEL_PLL_CFG are both correctly programmed. +#define OTP_DATA_BOOTSEL_XOSC_CFG_ROW _u(0x00000058) +#define OTP_DATA_BOOTSEL_XOSC_CFG_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTSEL_XOSC_CFG_RESET _u(0x00000000) +#define OTP_DATA_BOOTSEL_XOSC_CFG_WIDTH _u(16) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_XOSC_CFG_RANGE +// Description : Value of the XOSC_CTRL_FREQ_RANGE register. +// 0x0 -> 1_15MHZ +// 0x1 -> 10_30MHZ +// 0x2 -> 25_60MHZ +// 0x3 -> 40_100MHZ +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_RESET "-" +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_BITS _u(0x0000c000) +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_MSB _u(15) +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_LSB _u(14) +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_ACCESS "RO" +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_VALUE_1_15MHZ _u(0x0) +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_VALUE_10_30MHZ _u(0x1) +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_VALUE_25_60MHZ _u(0x2) +#define OTP_DATA_BOOTSEL_XOSC_CFG_RANGE_VALUE_40_100MHZ _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP +// Description : Value of the XOSC_STARTUP register +#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_RESET "-" +#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_BITS _u(0x00003fff) +#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_MSB _u(13) +#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_LSB _u(0) +#define OTP_DATA_BOOTSEL_XOSC_CFG_STARTUP_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_USB_BOOT_FLAGS +// Description : USB boot specific feature flags (RBIT-3) +#define OTP_DATA_USB_BOOT_FLAGS_ROW _u(0x00000059) +#define OTP_DATA_USB_BOOT_FLAGS_BITS _u(0x00c0ffff) +#define OTP_DATA_USB_BOOT_FLAGS_RESET _u(0x00000000) +#define OTP_DATA_USB_BOOT_FLAGS_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP +// Description : Swap DM/DP during USB boot, to support board layouts with +// mirrored USB routing (deliberate or accidental). +#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_BITS _u(0x00800000) +#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_MSB _u(23) +#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_LSB _u(23) +#define OTP_DATA_USB_BOOT_FLAGS_DP_DM_SWAP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID +// Description : valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the +// USB_WHITE_LABEL struct (index 15) +#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_BITS _u(0x00400000) +#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_MSB _u(22) +#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_LSB _u(22) +#define OTP_DATA_USB_BOOT_FLAGS_WHITE_LABEL_ADDR_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID +// Description : valid flag for the USB_WHITE_LABEL_ADDR field +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_BITS _u(0x00008000) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_MSB _u(15) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_LSB _u(15) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID +// Description : valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the +// USB_WHITE_LABEL struct (index 14) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_BITS _u(0x00004000) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_MSB _u(14) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_LSB _u(14) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INFO_UF2_TXT_MODEL_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID +// Description : valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the +// USB_WHITE_LABEL struct (index 13) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_BITS _u(0x00002000) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_MSB _u(13) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_LSB _u(13) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID +// Description : valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the +// USB_WHITE_LABEL struct (index 12) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_BITS _u(0x00001000) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_MSB _u(12) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_LSB _u(12) +#define OTP_DATA_USB_BOOT_FLAGS_WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID +// Description : valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the +// USB_WHITE_LABEL struct (index 11) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_BITS _u(0x00000800) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_MSB _u(11) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_LSB _u(11) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VERSION_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID +// Description : valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the +// USB_WHITE_LABEL struct (index 10) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_BITS _u(0x00000400) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_MSB _u(10) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_LSB _u(10) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID +// Description : valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the +// USB_WHITE_LABEL struct (index 9) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_BITS _u(0x00000200) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_MSB _u(9) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_LSB _u(9) +#define OTP_DATA_USB_BOOT_FLAGS_WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID +// Description : valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL +// struct (index 8) +#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_BITS _u(0x00000100) +#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_MSB _u(8) +#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_LSB _u(8) +#define OTP_DATA_USB_BOOT_FLAGS_WL_VOLUME_LABEL_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID +// Description : valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of +// the USB_WHITE_LABEL struct (index 7) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_BITS _u(0x00000080) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_MSB _u(7) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_LSB _u(7) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID +// Description : valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the +// USB_WHITE_LABEL struct (index 6) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_BITS _u(0x00000040) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_MSB _u(6) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_LSB _u(6) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID +// Description : valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the +// USB_WHITE_LABEL struct (index 5) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_BITS _u(0x00000020) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_MSB _u(5) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_LSB _u(5) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PRODUCT_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID +// Description : valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the +// USB_WHITE_LABEL struct (index 4) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_BITS _u(0x00000010) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_MSB _u(4) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_LSB _u(4) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID +// Description : valid flag for USB_DEVICE_LANG_ID_VALUE entry of the +// USB_WHITE_LABEL struct (index 3) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_BITS _u(0x00000008) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_MSB _u(3) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_LSB _u(3) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_LANG_ID_VALUE_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID +// Description : valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the +// USB_WHITE_LABEL struct (index 2) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_BITS _u(0x00000004) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_MSB _u(2) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_LSB _u(2) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID +// Description : valid flag for USB_DEVICE_PID_VALUE entry of the +// USB_WHITE_LABEL struct (index 1) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_BITS _u(0x00000002) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_MSB _u(1) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_LSB _u(1) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_PID_VALUE_VALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID +// Description : valid flag for USB_DEVICE_VID_VALUE entry of the +// USB_WHITE_LABEL struct (index 0) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_BITS _u(0x00000001) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_MSB _u(0) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_LSB _u(0) +#define OTP_DATA_USB_BOOT_FLAGS_WL_USB_DEVICE_VID_VALUE_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_USB_BOOT_FLAGS_R1 +// Description : Redundant copy of USB_BOOT_FLAGS +#define OTP_DATA_USB_BOOT_FLAGS_R1_ROW _u(0x0000005a) +#define OTP_DATA_USB_BOOT_FLAGS_R1_BITS _u(0x00ffffff) +#define OTP_DATA_USB_BOOT_FLAGS_R1_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_R1_WIDTH _u(24) +#define OTP_DATA_USB_BOOT_FLAGS_R1_MSB _u(23) +#define OTP_DATA_USB_BOOT_FLAGS_R1_LSB _u(0) +#define OTP_DATA_USB_BOOT_FLAGS_R1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_USB_BOOT_FLAGS_R2 +// Description : Redundant copy of USB_BOOT_FLAGS +#define OTP_DATA_USB_BOOT_FLAGS_R2_ROW _u(0x0000005b) +#define OTP_DATA_USB_BOOT_FLAGS_R2_BITS _u(0x00ffffff) +#define OTP_DATA_USB_BOOT_FLAGS_R2_RESET "-" +#define OTP_DATA_USB_BOOT_FLAGS_R2_WIDTH _u(24) +#define OTP_DATA_USB_BOOT_FLAGS_R2_MSB _u(23) +#define OTP_DATA_USB_BOOT_FLAGS_R2_LSB _u(0) +#define OTP_DATA_USB_BOOT_FLAGS_R2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_USB_WHITE_LABEL_ADDR +// Description : Row index of the USB_WHITE_LABEL structure within OTP (ECC) +// +// The table has 16 rows, each of which are also ECC and marked +// valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). +// +// The entries are either _VALUEs where the 16 bit value is used +// as is, or _STRDEFs which acts as a pointers to a string value. +// +// The value stored in a _STRDEF is two separate bytes: The low +// seven bits of the first (LSB) byte indicates the number of +// characters in the string, and the top bit of the first (LSB) +// byte if set to indicate that each character in the string is +// two bytes (Unicode) versus one byte if unset. The second (MSB) +// byte represents the location of the string data, and is encoded +// as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the +// row of the start of the string is USB_WHITE_LABEL_ADDR value + +// msb_byte. +// +// In each case, the corresponding valid bit enables replacing the +// default value for the corresponding item provided by the boot +// rom. +// +// Note that Unicode _STRDEFs are only supported for +// USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and +// USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored +// if specified for other fields, and non-unicode values for these +// three items will be converted to Unicode characters by setting +// the upper 8 bits to zero. +// +// Note that if the USB_WHITE_LABEL structure or the corresponding +// strings are not readable by BOOTSEL mode based on OTP +// permissions, or if alignment requirements are not met, then the +// corresponding default values are used. +// +// The index values indicate where each field is located (row +// USB_WHITE_LABEL_ADDR value + index): +// 0x0000 -> INDEX_USB_DEVICE_VID_VALUE +// 0x0001 -> INDEX_USB_DEVICE_PID_VALUE +// 0x0002 -> INDEX_USB_DEVICE_BCD_DEVICE_VALUE +// 0x0003 -> INDEX_USB_DEVICE_LANG_ID_VALUE +// 0x0004 -> INDEX_USB_DEVICE_MANUFACTURER_STRDEF +// 0x0005 -> INDEX_USB_DEVICE_PRODUCT_STRDEF +// 0x0006 -> INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF +// 0x0007 -> INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES +// 0x0008 -> INDEX_VOLUME_LABEL_STRDEF +// 0x0009 -> INDEX_SCSI_INQUIRY_VENDOR_STRDEF +// 0x000a -> INDEX_SCSI_INQUIRY_PRODUCT_STRDEF +// 0x000b -> INDEX_SCSI_INQUIRY_VERSION_STRDEF +// 0x000c -> INDEX_INDEX_HTM_REDIRECT_URL_STRDEF +// 0x000d -> INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF +// 0x000e -> INDEX_INFO_UF2_TXT_MODEL_STRDEF +// 0x000f -> INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF +#define OTP_DATA_USB_WHITE_LABEL_ADDR_ROW _u(0x0000005c) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_BITS _u(0x0000ffff) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_RESET "-" +#define OTP_DATA_USB_WHITE_LABEL_ADDR_WIDTH _u(16) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_MSB _u(15) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_LSB _u(0) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_ACCESS "RO" +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_VID_VALUE _u(0x0000) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_PID_VALUE _u(0x0001) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_BCD_DEVICE_VALUE _u(0x0002) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_LANG_ID_VALUE _u(0x0003) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_MANUFACTURER_STRDEF _u(0x0004) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_PRODUCT_STRDEF _u(0x0005) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF _u(0x0006) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES _u(0x0007) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_VOLUME_LABEL_STRDEF _u(0x0008) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_SCSI_INQUIRY_VENDOR_STRDEF _u(0x0009) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_SCSI_INQUIRY_PRODUCT_STRDEF _u(0x000a) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_SCSI_INQUIRY_VERSION_STRDEF _u(0x000b) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_INDEX_HTM_REDIRECT_URL_STRDEF _u(0x000c) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF _u(0x000d) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_INFO_UF2_TXT_MODEL_STRDEF _u(0x000e) +#define OTP_DATA_USB_WHITE_LABEL_ADDR_VALUE_INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF _u(0x000f) +// ============================================================================= +// Register : OTP_DATA_OTPBOOT_SRC +// Description : OTP start row for the OTP boot image. (ECC) +// +// If OTP boot is enabled, the bootrom will load from this +// location into SRAM and then directly enter the loaded image. +// Note that the image must be signed if SECURE_BOOT_ENABLE is +// set. The image itself is assumed to be ECC-protected. +// +// This must be an even number. Equivalently, the OTP boot image +// must start at a word-aligned location in the ECC read data +// address window. +#define OTP_DATA_OTPBOOT_SRC_ROW _u(0x0000005e) +#define OTP_DATA_OTPBOOT_SRC_BITS _u(0x0000ffff) +#define OTP_DATA_OTPBOOT_SRC_RESET "-" +#define OTP_DATA_OTPBOOT_SRC_WIDTH _u(16) +#define OTP_DATA_OTPBOOT_SRC_MSB _u(15) +#define OTP_DATA_OTPBOOT_SRC_LSB _u(0) +#define OTP_DATA_OTPBOOT_SRC_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_OTPBOOT_LEN +// Description : Length in rows of the OTP boot image. (ECC) +// +// OTPBOOT_LEN must be even. The total image size must be a +// multiple of 4 bytes (32 bits). +#define OTP_DATA_OTPBOOT_LEN_ROW _u(0x0000005f) +#define OTP_DATA_OTPBOOT_LEN_BITS _u(0x0000ffff) +#define OTP_DATA_OTPBOOT_LEN_RESET "-" +#define OTP_DATA_OTPBOOT_LEN_WIDTH _u(16) +#define OTP_DATA_OTPBOOT_LEN_MSB _u(15) +#define OTP_DATA_OTPBOOT_LEN_LSB _u(0) +#define OTP_DATA_OTPBOOT_LEN_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_OTPBOOT_DST0 +// Description : Bits 15:0 of the OTP boot image load destination (and entry +// point). (ECC) +// +// This must be a location in main SRAM (main SRAM is addresses +// 0x20000000 through 0x20082000) and must be word-aligned. +#define OTP_DATA_OTPBOOT_DST0_ROW _u(0x00000060) +#define OTP_DATA_OTPBOOT_DST0_BITS _u(0x0000ffff) +#define OTP_DATA_OTPBOOT_DST0_RESET "-" +#define OTP_DATA_OTPBOOT_DST0_WIDTH _u(16) +#define OTP_DATA_OTPBOOT_DST0_MSB _u(15) +#define OTP_DATA_OTPBOOT_DST0_LSB _u(0) +#define OTP_DATA_OTPBOOT_DST0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_OTPBOOT_DST1 +// Description : Bits 31:16 of the OTP boot image load destination (and entry +// point). (ECC) +// +// This must be a location in main SRAM (main SRAM is addresses +// 0x20000000 through 0x20082000) and must be word-aligned. +#define OTP_DATA_OTPBOOT_DST1_ROW _u(0x00000061) +#define OTP_DATA_OTPBOOT_DST1_BITS _u(0x0000ffff) +#define OTP_DATA_OTPBOOT_DST1_RESET "-" +#define OTP_DATA_OTPBOOT_DST1_WIDTH _u(16) +#define OTP_DATA_OTPBOOT_DST1_MSB _u(15) +#define OTP_DATA_OTPBOOT_DST1_LSB _u(0) +#define OTP_DATA_OTPBOOT_DST1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_0 +// Description : Bits 15:0 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_0_ROW _u(0x00000080) +#define OTP_DATA_BOOTKEY0_0_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_0_RESET "-" +#define OTP_DATA_BOOTKEY0_0_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_0_MSB _u(15) +#define OTP_DATA_BOOTKEY0_0_LSB _u(0) +#define OTP_DATA_BOOTKEY0_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_1 +// Description : Bits 31:16 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_1_ROW _u(0x00000081) +#define OTP_DATA_BOOTKEY0_1_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_1_RESET "-" +#define OTP_DATA_BOOTKEY0_1_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_1_MSB _u(15) +#define OTP_DATA_BOOTKEY0_1_LSB _u(0) +#define OTP_DATA_BOOTKEY0_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_2 +// Description : Bits 47:32 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_2_ROW _u(0x00000082) +#define OTP_DATA_BOOTKEY0_2_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_2_RESET "-" +#define OTP_DATA_BOOTKEY0_2_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_2_MSB _u(15) +#define OTP_DATA_BOOTKEY0_2_LSB _u(0) +#define OTP_DATA_BOOTKEY0_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_3 +// Description : Bits 63:48 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_3_ROW _u(0x00000083) +#define OTP_DATA_BOOTKEY0_3_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_3_RESET "-" +#define OTP_DATA_BOOTKEY0_3_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_3_MSB _u(15) +#define OTP_DATA_BOOTKEY0_3_LSB _u(0) +#define OTP_DATA_BOOTKEY0_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_4 +// Description : Bits 79:64 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_4_ROW _u(0x00000084) +#define OTP_DATA_BOOTKEY0_4_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_4_RESET "-" +#define OTP_DATA_BOOTKEY0_4_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_4_MSB _u(15) +#define OTP_DATA_BOOTKEY0_4_LSB _u(0) +#define OTP_DATA_BOOTKEY0_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_5 +// Description : Bits 95:80 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_5_ROW _u(0x00000085) +#define OTP_DATA_BOOTKEY0_5_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_5_RESET "-" +#define OTP_DATA_BOOTKEY0_5_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_5_MSB _u(15) +#define OTP_DATA_BOOTKEY0_5_LSB _u(0) +#define OTP_DATA_BOOTKEY0_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_6 +// Description : Bits 111:96 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_6_ROW _u(0x00000086) +#define OTP_DATA_BOOTKEY0_6_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_6_RESET "-" +#define OTP_DATA_BOOTKEY0_6_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_6_MSB _u(15) +#define OTP_DATA_BOOTKEY0_6_LSB _u(0) +#define OTP_DATA_BOOTKEY0_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_7 +// Description : Bits 127:112 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_7_ROW _u(0x00000087) +#define OTP_DATA_BOOTKEY0_7_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_7_RESET "-" +#define OTP_DATA_BOOTKEY0_7_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_7_MSB _u(15) +#define OTP_DATA_BOOTKEY0_7_LSB _u(0) +#define OTP_DATA_BOOTKEY0_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_8 +// Description : Bits 143:128 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_8_ROW _u(0x00000088) +#define OTP_DATA_BOOTKEY0_8_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_8_RESET "-" +#define OTP_DATA_BOOTKEY0_8_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_8_MSB _u(15) +#define OTP_DATA_BOOTKEY0_8_LSB _u(0) +#define OTP_DATA_BOOTKEY0_8_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_9 +// Description : Bits 159:144 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_9_ROW _u(0x00000089) +#define OTP_DATA_BOOTKEY0_9_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_9_RESET "-" +#define OTP_DATA_BOOTKEY0_9_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_9_MSB _u(15) +#define OTP_DATA_BOOTKEY0_9_LSB _u(0) +#define OTP_DATA_BOOTKEY0_9_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_10 +// Description : Bits 175:160 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_10_ROW _u(0x0000008a) +#define OTP_DATA_BOOTKEY0_10_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_10_RESET "-" +#define OTP_DATA_BOOTKEY0_10_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_10_MSB _u(15) +#define OTP_DATA_BOOTKEY0_10_LSB _u(0) +#define OTP_DATA_BOOTKEY0_10_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_11 +// Description : Bits 191:176 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_11_ROW _u(0x0000008b) +#define OTP_DATA_BOOTKEY0_11_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_11_RESET "-" +#define OTP_DATA_BOOTKEY0_11_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_11_MSB _u(15) +#define OTP_DATA_BOOTKEY0_11_LSB _u(0) +#define OTP_DATA_BOOTKEY0_11_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_12 +// Description : Bits 207:192 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_12_ROW _u(0x0000008c) +#define OTP_DATA_BOOTKEY0_12_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_12_RESET "-" +#define OTP_DATA_BOOTKEY0_12_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_12_MSB _u(15) +#define OTP_DATA_BOOTKEY0_12_LSB _u(0) +#define OTP_DATA_BOOTKEY0_12_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_13 +// Description : Bits 223:208 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_13_ROW _u(0x0000008d) +#define OTP_DATA_BOOTKEY0_13_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_13_RESET "-" +#define OTP_DATA_BOOTKEY0_13_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_13_MSB _u(15) +#define OTP_DATA_BOOTKEY0_13_LSB _u(0) +#define OTP_DATA_BOOTKEY0_13_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_14 +// Description : Bits 239:224 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_14_ROW _u(0x0000008e) +#define OTP_DATA_BOOTKEY0_14_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_14_RESET "-" +#define OTP_DATA_BOOTKEY0_14_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_14_MSB _u(15) +#define OTP_DATA_BOOTKEY0_14_LSB _u(0) +#define OTP_DATA_BOOTKEY0_14_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY0_15 +// Description : Bits 255:240 of SHA-256 hash of boot key 0 (ECC) +#define OTP_DATA_BOOTKEY0_15_ROW _u(0x0000008f) +#define OTP_DATA_BOOTKEY0_15_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY0_15_RESET "-" +#define OTP_DATA_BOOTKEY0_15_WIDTH _u(16) +#define OTP_DATA_BOOTKEY0_15_MSB _u(15) +#define OTP_DATA_BOOTKEY0_15_LSB _u(0) +#define OTP_DATA_BOOTKEY0_15_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_0 +// Description : Bits 15:0 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_0_ROW _u(0x00000090) +#define OTP_DATA_BOOTKEY1_0_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_0_RESET "-" +#define OTP_DATA_BOOTKEY1_0_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_0_MSB _u(15) +#define OTP_DATA_BOOTKEY1_0_LSB _u(0) +#define OTP_DATA_BOOTKEY1_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_1 +// Description : Bits 31:16 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_1_ROW _u(0x00000091) +#define OTP_DATA_BOOTKEY1_1_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_1_RESET "-" +#define OTP_DATA_BOOTKEY1_1_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_1_MSB _u(15) +#define OTP_DATA_BOOTKEY1_1_LSB _u(0) +#define OTP_DATA_BOOTKEY1_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_2 +// Description : Bits 47:32 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_2_ROW _u(0x00000092) +#define OTP_DATA_BOOTKEY1_2_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_2_RESET "-" +#define OTP_DATA_BOOTKEY1_2_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_2_MSB _u(15) +#define OTP_DATA_BOOTKEY1_2_LSB _u(0) +#define OTP_DATA_BOOTKEY1_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_3 +// Description : Bits 63:48 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_3_ROW _u(0x00000093) +#define OTP_DATA_BOOTKEY1_3_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_3_RESET "-" +#define OTP_DATA_BOOTKEY1_3_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_3_MSB _u(15) +#define OTP_DATA_BOOTKEY1_3_LSB _u(0) +#define OTP_DATA_BOOTKEY1_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_4 +// Description : Bits 79:64 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_4_ROW _u(0x00000094) +#define OTP_DATA_BOOTKEY1_4_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_4_RESET "-" +#define OTP_DATA_BOOTKEY1_4_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_4_MSB _u(15) +#define OTP_DATA_BOOTKEY1_4_LSB _u(0) +#define OTP_DATA_BOOTKEY1_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_5 +// Description : Bits 95:80 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_5_ROW _u(0x00000095) +#define OTP_DATA_BOOTKEY1_5_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_5_RESET "-" +#define OTP_DATA_BOOTKEY1_5_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_5_MSB _u(15) +#define OTP_DATA_BOOTKEY1_5_LSB _u(0) +#define OTP_DATA_BOOTKEY1_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_6 +// Description : Bits 111:96 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_6_ROW _u(0x00000096) +#define OTP_DATA_BOOTKEY1_6_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_6_RESET "-" +#define OTP_DATA_BOOTKEY1_6_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_6_MSB _u(15) +#define OTP_DATA_BOOTKEY1_6_LSB _u(0) +#define OTP_DATA_BOOTKEY1_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_7 +// Description : Bits 127:112 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_7_ROW _u(0x00000097) +#define OTP_DATA_BOOTKEY1_7_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_7_RESET "-" +#define OTP_DATA_BOOTKEY1_7_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_7_MSB _u(15) +#define OTP_DATA_BOOTKEY1_7_LSB _u(0) +#define OTP_DATA_BOOTKEY1_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_8 +// Description : Bits 143:128 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_8_ROW _u(0x00000098) +#define OTP_DATA_BOOTKEY1_8_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_8_RESET "-" +#define OTP_DATA_BOOTKEY1_8_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_8_MSB _u(15) +#define OTP_DATA_BOOTKEY1_8_LSB _u(0) +#define OTP_DATA_BOOTKEY1_8_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_9 +// Description : Bits 159:144 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_9_ROW _u(0x00000099) +#define OTP_DATA_BOOTKEY1_9_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_9_RESET "-" +#define OTP_DATA_BOOTKEY1_9_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_9_MSB _u(15) +#define OTP_DATA_BOOTKEY1_9_LSB _u(0) +#define OTP_DATA_BOOTKEY1_9_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_10 +// Description : Bits 175:160 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_10_ROW _u(0x0000009a) +#define OTP_DATA_BOOTKEY1_10_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_10_RESET "-" +#define OTP_DATA_BOOTKEY1_10_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_10_MSB _u(15) +#define OTP_DATA_BOOTKEY1_10_LSB _u(0) +#define OTP_DATA_BOOTKEY1_10_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_11 +// Description : Bits 191:176 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_11_ROW _u(0x0000009b) +#define OTP_DATA_BOOTKEY1_11_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_11_RESET "-" +#define OTP_DATA_BOOTKEY1_11_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_11_MSB _u(15) +#define OTP_DATA_BOOTKEY1_11_LSB _u(0) +#define OTP_DATA_BOOTKEY1_11_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_12 +// Description : Bits 207:192 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_12_ROW _u(0x0000009c) +#define OTP_DATA_BOOTKEY1_12_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_12_RESET "-" +#define OTP_DATA_BOOTKEY1_12_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_12_MSB _u(15) +#define OTP_DATA_BOOTKEY1_12_LSB _u(0) +#define OTP_DATA_BOOTKEY1_12_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_13 +// Description : Bits 223:208 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_13_ROW _u(0x0000009d) +#define OTP_DATA_BOOTKEY1_13_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_13_RESET "-" +#define OTP_DATA_BOOTKEY1_13_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_13_MSB _u(15) +#define OTP_DATA_BOOTKEY1_13_LSB _u(0) +#define OTP_DATA_BOOTKEY1_13_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_14 +// Description : Bits 239:224 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_14_ROW _u(0x0000009e) +#define OTP_DATA_BOOTKEY1_14_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_14_RESET "-" +#define OTP_DATA_BOOTKEY1_14_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_14_MSB _u(15) +#define OTP_DATA_BOOTKEY1_14_LSB _u(0) +#define OTP_DATA_BOOTKEY1_14_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY1_15 +// Description : Bits 255:240 of SHA-256 hash of boot key 1 (ECC) +#define OTP_DATA_BOOTKEY1_15_ROW _u(0x0000009f) +#define OTP_DATA_BOOTKEY1_15_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY1_15_RESET "-" +#define OTP_DATA_BOOTKEY1_15_WIDTH _u(16) +#define OTP_DATA_BOOTKEY1_15_MSB _u(15) +#define OTP_DATA_BOOTKEY1_15_LSB _u(0) +#define OTP_DATA_BOOTKEY1_15_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_0 +// Description : Bits 15:0 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_0_ROW _u(0x000000a0) +#define OTP_DATA_BOOTKEY2_0_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_0_RESET "-" +#define OTP_DATA_BOOTKEY2_0_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_0_MSB _u(15) +#define OTP_DATA_BOOTKEY2_0_LSB _u(0) +#define OTP_DATA_BOOTKEY2_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_1 +// Description : Bits 31:16 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_1_ROW _u(0x000000a1) +#define OTP_DATA_BOOTKEY2_1_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_1_RESET "-" +#define OTP_DATA_BOOTKEY2_1_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_1_MSB _u(15) +#define OTP_DATA_BOOTKEY2_1_LSB _u(0) +#define OTP_DATA_BOOTKEY2_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_2 +// Description : Bits 47:32 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_2_ROW _u(0x000000a2) +#define OTP_DATA_BOOTKEY2_2_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_2_RESET "-" +#define OTP_DATA_BOOTKEY2_2_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_2_MSB _u(15) +#define OTP_DATA_BOOTKEY2_2_LSB _u(0) +#define OTP_DATA_BOOTKEY2_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_3 +// Description : Bits 63:48 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_3_ROW _u(0x000000a3) +#define OTP_DATA_BOOTKEY2_3_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_3_RESET "-" +#define OTP_DATA_BOOTKEY2_3_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_3_MSB _u(15) +#define OTP_DATA_BOOTKEY2_3_LSB _u(0) +#define OTP_DATA_BOOTKEY2_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_4 +// Description : Bits 79:64 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_4_ROW _u(0x000000a4) +#define OTP_DATA_BOOTKEY2_4_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_4_RESET "-" +#define OTP_DATA_BOOTKEY2_4_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_4_MSB _u(15) +#define OTP_DATA_BOOTKEY2_4_LSB _u(0) +#define OTP_DATA_BOOTKEY2_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_5 +// Description : Bits 95:80 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_5_ROW _u(0x000000a5) +#define OTP_DATA_BOOTKEY2_5_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_5_RESET "-" +#define OTP_DATA_BOOTKEY2_5_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_5_MSB _u(15) +#define OTP_DATA_BOOTKEY2_5_LSB _u(0) +#define OTP_DATA_BOOTKEY2_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_6 +// Description : Bits 111:96 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_6_ROW _u(0x000000a6) +#define OTP_DATA_BOOTKEY2_6_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_6_RESET "-" +#define OTP_DATA_BOOTKEY2_6_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_6_MSB _u(15) +#define OTP_DATA_BOOTKEY2_6_LSB _u(0) +#define OTP_DATA_BOOTKEY2_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_7 +// Description : Bits 127:112 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_7_ROW _u(0x000000a7) +#define OTP_DATA_BOOTKEY2_7_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_7_RESET "-" +#define OTP_DATA_BOOTKEY2_7_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_7_MSB _u(15) +#define OTP_DATA_BOOTKEY2_7_LSB _u(0) +#define OTP_DATA_BOOTKEY2_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_8 +// Description : Bits 143:128 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_8_ROW _u(0x000000a8) +#define OTP_DATA_BOOTKEY2_8_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_8_RESET "-" +#define OTP_DATA_BOOTKEY2_8_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_8_MSB _u(15) +#define OTP_DATA_BOOTKEY2_8_LSB _u(0) +#define OTP_DATA_BOOTKEY2_8_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_9 +// Description : Bits 159:144 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_9_ROW _u(0x000000a9) +#define OTP_DATA_BOOTKEY2_9_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_9_RESET "-" +#define OTP_DATA_BOOTKEY2_9_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_9_MSB _u(15) +#define OTP_DATA_BOOTKEY2_9_LSB _u(0) +#define OTP_DATA_BOOTKEY2_9_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_10 +// Description : Bits 175:160 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_10_ROW _u(0x000000aa) +#define OTP_DATA_BOOTKEY2_10_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_10_RESET "-" +#define OTP_DATA_BOOTKEY2_10_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_10_MSB _u(15) +#define OTP_DATA_BOOTKEY2_10_LSB _u(0) +#define OTP_DATA_BOOTKEY2_10_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_11 +// Description : Bits 191:176 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_11_ROW _u(0x000000ab) +#define OTP_DATA_BOOTKEY2_11_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_11_RESET "-" +#define OTP_DATA_BOOTKEY2_11_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_11_MSB _u(15) +#define OTP_DATA_BOOTKEY2_11_LSB _u(0) +#define OTP_DATA_BOOTKEY2_11_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_12 +// Description : Bits 207:192 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_12_ROW _u(0x000000ac) +#define OTP_DATA_BOOTKEY2_12_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_12_RESET "-" +#define OTP_DATA_BOOTKEY2_12_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_12_MSB _u(15) +#define OTP_DATA_BOOTKEY2_12_LSB _u(0) +#define OTP_DATA_BOOTKEY2_12_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_13 +// Description : Bits 223:208 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_13_ROW _u(0x000000ad) +#define OTP_DATA_BOOTKEY2_13_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_13_RESET "-" +#define OTP_DATA_BOOTKEY2_13_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_13_MSB _u(15) +#define OTP_DATA_BOOTKEY2_13_LSB _u(0) +#define OTP_DATA_BOOTKEY2_13_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_14 +// Description : Bits 239:224 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_14_ROW _u(0x000000ae) +#define OTP_DATA_BOOTKEY2_14_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_14_RESET "-" +#define OTP_DATA_BOOTKEY2_14_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_14_MSB _u(15) +#define OTP_DATA_BOOTKEY2_14_LSB _u(0) +#define OTP_DATA_BOOTKEY2_14_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY2_15 +// Description : Bits 255:240 of SHA-256 hash of boot key 2 (ECC) +#define OTP_DATA_BOOTKEY2_15_ROW _u(0x000000af) +#define OTP_DATA_BOOTKEY2_15_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY2_15_RESET "-" +#define OTP_DATA_BOOTKEY2_15_WIDTH _u(16) +#define OTP_DATA_BOOTKEY2_15_MSB _u(15) +#define OTP_DATA_BOOTKEY2_15_LSB _u(0) +#define OTP_DATA_BOOTKEY2_15_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_0 +// Description : Bits 15:0 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_0_ROW _u(0x000000b0) +#define OTP_DATA_BOOTKEY3_0_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_0_RESET "-" +#define OTP_DATA_BOOTKEY3_0_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_0_MSB _u(15) +#define OTP_DATA_BOOTKEY3_0_LSB _u(0) +#define OTP_DATA_BOOTKEY3_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_1 +// Description : Bits 31:16 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_1_ROW _u(0x000000b1) +#define OTP_DATA_BOOTKEY3_1_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_1_RESET "-" +#define OTP_DATA_BOOTKEY3_1_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_1_MSB _u(15) +#define OTP_DATA_BOOTKEY3_1_LSB _u(0) +#define OTP_DATA_BOOTKEY3_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_2 +// Description : Bits 47:32 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_2_ROW _u(0x000000b2) +#define OTP_DATA_BOOTKEY3_2_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_2_RESET "-" +#define OTP_DATA_BOOTKEY3_2_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_2_MSB _u(15) +#define OTP_DATA_BOOTKEY3_2_LSB _u(0) +#define OTP_DATA_BOOTKEY3_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_3 +// Description : Bits 63:48 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_3_ROW _u(0x000000b3) +#define OTP_DATA_BOOTKEY3_3_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_3_RESET "-" +#define OTP_DATA_BOOTKEY3_3_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_3_MSB _u(15) +#define OTP_DATA_BOOTKEY3_3_LSB _u(0) +#define OTP_DATA_BOOTKEY3_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_4 +// Description : Bits 79:64 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_4_ROW _u(0x000000b4) +#define OTP_DATA_BOOTKEY3_4_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_4_RESET "-" +#define OTP_DATA_BOOTKEY3_4_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_4_MSB _u(15) +#define OTP_DATA_BOOTKEY3_4_LSB _u(0) +#define OTP_DATA_BOOTKEY3_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_5 +// Description : Bits 95:80 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_5_ROW _u(0x000000b5) +#define OTP_DATA_BOOTKEY3_5_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_5_RESET "-" +#define OTP_DATA_BOOTKEY3_5_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_5_MSB _u(15) +#define OTP_DATA_BOOTKEY3_5_LSB _u(0) +#define OTP_DATA_BOOTKEY3_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_6 +// Description : Bits 111:96 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_6_ROW _u(0x000000b6) +#define OTP_DATA_BOOTKEY3_6_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_6_RESET "-" +#define OTP_DATA_BOOTKEY3_6_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_6_MSB _u(15) +#define OTP_DATA_BOOTKEY3_6_LSB _u(0) +#define OTP_DATA_BOOTKEY3_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_7 +// Description : Bits 127:112 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_7_ROW _u(0x000000b7) +#define OTP_DATA_BOOTKEY3_7_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_7_RESET "-" +#define OTP_DATA_BOOTKEY3_7_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_7_MSB _u(15) +#define OTP_DATA_BOOTKEY3_7_LSB _u(0) +#define OTP_DATA_BOOTKEY3_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_8 +// Description : Bits 143:128 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_8_ROW _u(0x000000b8) +#define OTP_DATA_BOOTKEY3_8_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_8_RESET "-" +#define OTP_DATA_BOOTKEY3_8_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_8_MSB _u(15) +#define OTP_DATA_BOOTKEY3_8_LSB _u(0) +#define OTP_DATA_BOOTKEY3_8_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_9 +// Description : Bits 159:144 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_9_ROW _u(0x000000b9) +#define OTP_DATA_BOOTKEY3_9_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_9_RESET "-" +#define OTP_DATA_BOOTKEY3_9_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_9_MSB _u(15) +#define OTP_DATA_BOOTKEY3_9_LSB _u(0) +#define OTP_DATA_BOOTKEY3_9_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_10 +// Description : Bits 175:160 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_10_ROW _u(0x000000ba) +#define OTP_DATA_BOOTKEY3_10_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_10_RESET "-" +#define OTP_DATA_BOOTKEY3_10_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_10_MSB _u(15) +#define OTP_DATA_BOOTKEY3_10_LSB _u(0) +#define OTP_DATA_BOOTKEY3_10_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_11 +// Description : Bits 191:176 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_11_ROW _u(0x000000bb) +#define OTP_DATA_BOOTKEY3_11_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_11_RESET "-" +#define OTP_DATA_BOOTKEY3_11_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_11_MSB _u(15) +#define OTP_DATA_BOOTKEY3_11_LSB _u(0) +#define OTP_DATA_BOOTKEY3_11_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_12 +// Description : Bits 207:192 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_12_ROW _u(0x000000bc) +#define OTP_DATA_BOOTKEY3_12_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_12_RESET "-" +#define OTP_DATA_BOOTKEY3_12_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_12_MSB _u(15) +#define OTP_DATA_BOOTKEY3_12_LSB _u(0) +#define OTP_DATA_BOOTKEY3_12_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_13 +// Description : Bits 223:208 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_13_ROW _u(0x000000bd) +#define OTP_DATA_BOOTKEY3_13_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_13_RESET "-" +#define OTP_DATA_BOOTKEY3_13_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_13_MSB _u(15) +#define OTP_DATA_BOOTKEY3_13_LSB _u(0) +#define OTP_DATA_BOOTKEY3_13_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_14 +// Description : Bits 239:224 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_14_ROW _u(0x000000be) +#define OTP_DATA_BOOTKEY3_14_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_14_RESET "-" +#define OTP_DATA_BOOTKEY3_14_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_14_MSB _u(15) +#define OTP_DATA_BOOTKEY3_14_LSB _u(0) +#define OTP_DATA_BOOTKEY3_14_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_BOOTKEY3_15 +// Description : Bits 255:240 of SHA-256 hash of boot key 3 (ECC) +#define OTP_DATA_BOOTKEY3_15_ROW _u(0x000000bf) +#define OTP_DATA_BOOTKEY3_15_BITS _u(0x0000ffff) +#define OTP_DATA_BOOTKEY3_15_RESET "-" +#define OTP_DATA_BOOTKEY3_15_WIDTH _u(16) +#define OTP_DATA_BOOTKEY3_15_MSB _u(15) +#define OTP_DATA_BOOTKEY3_15_LSB _u(0) +#define OTP_DATA_BOOTKEY3_15_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_0 +// Description : Bits 15:0 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_0_ROW _u(0x00000f48) +#define OTP_DATA_KEY1_0_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_0_RESET "-" +#define OTP_DATA_KEY1_0_WIDTH _u(16) +#define OTP_DATA_KEY1_0_MSB _u(15) +#define OTP_DATA_KEY1_0_LSB _u(0) +#define OTP_DATA_KEY1_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_1 +// Description : Bits 31:16 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_1_ROW _u(0x00000f49) +#define OTP_DATA_KEY1_1_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_1_RESET "-" +#define OTP_DATA_KEY1_1_WIDTH _u(16) +#define OTP_DATA_KEY1_1_MSB _u(15) +#define OTP_DATA_KEY1_1_LSB _u(0) +#define OTP_DATA_KEY1_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_2 +// Description : Bits 47:32 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_2_ROW _u(0x00000f4a) +#define OTP_DATA_KEY1_2_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_2_RESET "-" +#define OTP_DATA_KEY1_2_WIDTH _u(16) +#define OTP_DATA_KEY1_2_MSB _u(15) +#define OTP_DATA_KEY1_2_LSB _u(0) +#define OTP_DATA_KEY1_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_3 +// Description : Bits 63:48 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_3_ROW _u(0x00000f4b) +#define OTP_DATA_KEY1_3_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_3_RESET "-" +#define OTP_DATA_KEY1_3_WIDTH _u(16) +#define OTP_DATA_KEY1_3_MSB _u(15) +#define OTP_DATA_KEY1_3_LSB _u(0) +#define OTP_DATA_KEY1_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_4 +// Description : Bits 79:64 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_4_ROW _u(0x00000f4c) +#define OTP_DATA_KEY1_4_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_4_RESET "-" +#define OTP_DATA_KEY1_4_WIDTH _u(16) +#define OTP_DATA_KEY1_4_MSB _u(15) +#define OTP_DATA_KEY1_4_LSB _u(0) +#define OTP_DATA_KEY1_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_5 +// Description : Bits 95:80 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_5_ROW _u(0x00000f4d) +#define OTP_DATA_KEY1_5_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_5_RESET "-" +#define OTP_DATA_KEY1_5_WIDTH _u(16) +#define OTP_DATA_KEY1_5_MSB _u(15) +#define OTP_DATA_KEY1_5_LSB _u(0) +#define OTP_DATA_KEY1_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_6 +// Description : Bits 111:96 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_6_ROW _u(0x00000f4e) +#define OTP_DATA_KEY1_6_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_6_RESET "-" +#define OTP_DATA_KEY1_6_WIDTH _u(16) +#define OTP_DATA_KEY1_6_MSB _u(15) +#define OTP_DATA_KEY1_6_LSB _u(0) +#define OTP_DATA_KEY1_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_7 +// Description : Bits 127:112 of OTP access key 1 (ECC) +#define OTP_DATA_KEY1_7_ROW _u(0x00000f4f) +#define OTP_DATA_KEY1_7_BITS _u(0x0000ffff) +#define OTP_DATA_KEY1_7_RESET "-" +#define OTP_DATA_KEY1_7_WIDTH _u(16) +#define OTP_DATA_KEY1_7_MSB _u(15) +#define OTP_DATA_KEY1_7_LSB _u(0) +#define OTP_DATA_KEY1_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_0 +// Description : Bits 15:0 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_0_ROW _u(0x00000f50) +#define OTP_DATA_KEY2_0_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_0_RESET "-" +#define OTP_DATA_KEY2_0_WIDTH _u(16) +#define OTP_DATA_KEY2_0_MSB _u(15) +#define OTP_DATA_KEY2_0_LSB _u(0) +#define OTP_DATA_KEY2_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_1 +// Description : Bits 31:16 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_1_ROW _u(0x00000f51) +#define OTP_DATA_KEY2_1_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_1_RESET "-" +#define OTP_DATA_KEY2_1_WIDTH _u(16) +#define OTP_DATA_KEY2_1_MSB _u(15) +#define OTP_DATA_KEY2_1_LSB _u(0) +#define OTP_DATA_KEY2_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_2 +// Description : Bits 47:32 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_2_ROW _u(0x00000f52) +#define OTP_DATA_KEY2_2_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_2_RESET "-" +#define OTP_DATA_KEY2_2_WIDTH _u(16) +#define OTP_DATA_KEY2_2_MSB _u(15) +#define OTP_DATA_KEY2_2_LSB _u(0) +#define OTP_DATA_KEY2_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_3 +// Description : Bits 63:48 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_3_ROW _u(0x00000f53) +#define OTP_DATA_KEY2_3_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_3_RESET "-" +#define OTP_DATA_KEY2_3_WIDTH _u(16) +#define OTP_DATA_KEY2_3_MSB _u(15) +#define OTP_DATA_KEY2_3_LSB _u(0) +#define OTP_DATA_KEY2_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_4 +// Description : Bits 79:64 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_4_ROW _u(0x00000f54) +#define OTP_DATA_KEY2_4_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_4_RESET "-" +#define OTP_DATA_KEY2_4_WIDTH _u(16) +#define OTP_DATA_KEY2_4_MSB _u(15) +#define OTP_DATA_KEY2_4_LSB _u(0) +#define OTP_DATA_KEY2_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_5 +// Description : Bits 95:80 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_5_ROW _u(0x00000f55) +#define OTP_DATA_KEY2_5_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_5_RESET "-" +#define OTP_DATA_KEY2_5_WIDTH _u(16) +#define OTP_DATA_KEY2_5_MSB _u(15) +#define OTP_DATA_KEY2_5_LSB _u(0) +#define OTP_DATA_KEY2_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_6 +// Description : Bits 111:96 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_6_ROW _u(0x00000f56) +#define OTP_DATA_KEY2_6_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_6_RESET "-" +#define OTP_DATA_KEY2_6_WIDTH _u(16) +#define OTP_DATA_KEY2_6_MSB _u(15) +#define OTP_DATA_KEY2_6_LSB _u(0) +#define OTP_DATA_KEY2_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_7 +// Description : Bits 127:112 of OTP access key 2 (ECC) +#define OTP_DATA_KEY2_7_ROW _u(0x00000f57) +#define OTP_DATA_KEY2_7_BITS _u(0x0000ffff) +#define OTP_DATA_KEY2_7_RESET "-" +#define OTP_DATA_KEY2_7_WIDTH _u(16) +#define OTP_DATA_KEY2_7_MSB _u(15) +#define OTP_DATA_KEY2_7_LSB _u(0) +#define OTP_DATA_KEY2_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_0 +// Description : Bits 15:0 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_0_ROW _u(0x00000f58) +#define OTP_DATA_KEY3_0_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_0_RESET "-" +#define OTP_DATA_KEY3_0_WIDTH _u(16) +#define OTP_DATA_KEY3_0_MSB _u(15) +#define OTP_DATA_KEY3_0_LSB _u(0) +#define OTP_DATA_KEY3_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_1 +// Description : Bits 31:16 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_1_ROW _u(0x00000f59) +#define OTP_DATA_KEY3_1_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_1_RESET "-" +#define OTP_DATA_KEY3_1_WIDTH _u(16) +#define OTP_DATA_KEY3_1_MSB _u(15) +#define OTP_DATA_KEY3_1_LSB _u(0) +#define OTP_DATA_KEY3_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_2 +// Description : Bits 47:32 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_2_ROW _u(0x00000f5a) +#define OTP_DATA_KEY3_2_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_2_RESET "-" +#define OTP_DATA_KEY3_2_WIDTH _u(16) +#define OTP_DATA_KEY3_2_MSB _u(15) +#define OTP_DATA_KEY3_2_LSB _u(0) +#define OTP_DATA_KEY3_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_3 +// Description : Bits 63:48 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_3_ROW _u(0x00000f5b) +#define OTP_DATA_KEY3_3_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_3_RESET "-" +#define OTP_DATA_KEY3_3_WIDTH _u(16) +#define OTP_DATA_KEY3_3_MSB _u(15) +#define OTP_DATA_KEY3_3_LSB _u(0) +#define OTP_DATA_KEY3_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_4 +// Description : Bits 79:64 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_4_ROW _u(0x00000f5c) +#define OTP_DATA_KEY3_4_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_4_RESET "-" +#define OTP_DATA_KEY3_4_WIDTH _u(16) +#define OTP_DATA_KEY3_4_MSB _u(15) +#define OTP_DATA_KEY3_4_LSB _u(0) +#define OTP_DATA_KEY3_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_5 +// Description : Bits 95:80 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_5_ROW _u(0x00000f5d) +#define OTP_DATA_KEY3_5_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_5_RESET "-" +#define OTP_DATA_KEY3_5_WIDTH _u(16) +#define OTP_DATA_KEY3_5_MSB _u(15) +#define OTP_DATA_KEY3_5_LSB _u(0) +#define OTP_DATA_KEY3_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_6 +// Description : Bits 111:96 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_6_ROW _u(0x00000f5e) +#define OTP_DATA_KEY3_6_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_6_RESET "-" +#define OTP_DATA_KEY3_6_WIDTH _u(16) +#define OTP_DATA_KEY3_6_MSB _u(15) +#define OTP_DATA_KEY3_6_LSB _u(0) +#define OTP_DATA_KEY3_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_7 +// Description : Bits 127:112 of OTP access key 3 (ECC) +#define OTP_DATA_KEY3_7_ROW _u(0x00000f5f) +#define OTP_DATA_KEY3_7_BITS _u(0x0000ffff) +#define OTP_DATA_KEY3_7_RESET "-" +#define OTP_DATA_KEY3_7_WIDTH _u(16) +#define OTP_DATA_KEY3_7_MSB _u(15) +#define OTP_DATA_KEY3_7_LSB _u(0) +#define OTP_DATA_KEY3_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_0 +// Description : Bits 15:0 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_0_ROW _u(0x00000f60) +#define OTP_DATA_KEY4_0_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_0_RESET "-" +#define OTP_DATA_KEY4_0_WIDTH _u(16) +#define OTP_DATA_KEY4_0_MSB _u(15) +#define OTP_DATA_KEY4_0_LSB _u(0) +#define OTP_DATA_KEY4_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_1 +// Description : Bits 31:16 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_1_ROW _u(0x00000f61) +#define OTP_DATA_KEY4_1_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_1_RESET "-" +#define OTP_DATA_KEY4_1_WIDTH _u(16) +#define OTP_DATA_KEY4_1_MSB _u(15) +#define OTP_DATA_KEY4_1_LSB _u(0) +#define OTP_DATA_KEY4_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_2 +// Description : Bits 47:32 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_2_ROW _u(0x00000f62) +#define OTP_DATA_KEY4_2_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_2_RESET "-" +#define OTP_DATA_KEY4_2_WIDTH _u(16) +#define OTP_DATA_KEY4_2_MSB _u(15) +#define OTP_DATA_KEY4_2_LSB _u(0) +#define OTP_DATA_KEY4_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_3 +// Description : Bits 63:48 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_3_ROW _u(0x00000f63) +#define OTP_DATA_KEY4_3_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_3_RESET "-" +#define OTP_DATA_KEY4_3_WIDTH _u(16) +#define OTP_DATA_KEY4_3_MSB _u(15) +#define OTP_DATA_KEY4_3_LSB _u(0) +#define OTP_DATA_KEY4_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_4 +// Description : Bits 79:64 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_4_ROW _u(0x00000f64) +#define OTP_DATA_KEY4_4_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_4_RESET "-" +#define OTP_DATA_KEY4_4_WIDTH _u(16) +#define OTP_DATA_KEY4_4_MSB _u(15) +#define OTP_DATA_KEY4_4_LSB _u(0) +#define OTP_DATA_KEY4_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_5 +// Description : Bits 95:80 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_5_ROW _u(0x00000f65) +#define OTP_DATA_KEY4_5_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_5_RESET "-" +#define OTP_DATA_KEY4_5_WIDTH _u(16) +#define OTP_DATA_KEY4_5_MSB _u(15) +#define OTP_DATA_KEY4_5_LSB _u(0) +#define OTP_DATA_KEY4_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_6 +// Description : Bits 111:96 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_6_ROW _u(0x00000f66) +#define OTP_DATA_KEY4_6_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_6_RESET "-" +#define OTP_DATA_KEY4_6_WIDTH _u(16) +#define OTP_DATA_KEY4_6_MSB _u(15) +#define OTP_DATA_KEY4_6_LSB _u(0) +#define OTP_DATA_KEY4_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_7 +// Description : Bits 127:112 of OTP access key 4 (ECC) +#define OTP_DATA_KEY4_7_ROW _u(0x00000f67) +#define OTP_DATA_KEY4_7_BITS _u(0x0000ffff) +#define OTP_DATA_KEY4_7_RESET "-" +#define OTP_DATA_KEY4_7_WIDTH _u(16) +#define OTP_DATA_KEY4_7_MSB _u(15) +#define OTP_DATA_KEY4_7_LSB _u(0) +#define OTP_DATA_KEY4_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_0 +// Description : Bits 15:0 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_0_ROW _u(0x00000f68) +#define OTP_DATA_KEY5_0_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_0_RESET "-" +#define OTP_DATA_KEY5_0_WIDTH _u(16) +#define OTP_DATA_KEY5_0_MSB _u(15) +#define OTP_DATA_KEY5_0_LSB _u(0) +#define OTP_DATA_KEY5_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_1 +// Description : Bits 31:16 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_1_ROW _u(0x00000f69) +#define OTP_DATA_KEY5_1_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_1_RESET "-" +#define OTP_DATA_KEY5_1_WIDTH _u(16) +#define OTP_DATA_KEY5_1_MSB _u(15) +#define OTP_DATA_KEY5_1_LSB _u(0) +#define OTP_DATA_KEY5_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_2 +// Description : Bits 47:32 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_2_ROW _u(0x00000f6a) +#define OTP_DATA_KEY5_2_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_2_RESET "-" +#define OTP_DATA_KEY5_2_WIDTH _u(16) +#define OTP_DATA_KEY5_2_MSB _u(15) +#define OTP_DATA_KEY5_2_LSB _u(0) +#define OTP_DATA_KEY5_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_3 +// Description : Bits 63:48 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_3_ROW _u(0x00000f6b) +#define OTP_DATA_KEY5_3_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_3_RESET "-" +#define OTP_DATA_KEY5_3_WIDTH _u(16) +#define OTP_DATA_KEY5_3_MSB _u(15) +#define OTP_DATA_KEY5_3_LSB _u(0) +#define OTP_DATA_KEY5_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_4 +// Description : Bits 79:64 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_4_ROW _u(0x00000f6c) +#define OTP_DATA_KEY5_4_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_4_RESET "-" +#define OTP_DATA_KEY5_4_WIDTH _u(16) +#define OTP_DATA_KEY5_4_MSB _u(15) +#define OTP_DATA_KEY5_4_LSB _u(0) +#define OTP_DATA_KEY5_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_5 +// Description : Bits 95:80 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_5_ROW _u(0x00000f6d) +#define OTP_DATA_KEY5_5_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_5_RESET "-" +#define OTP_DATA_KEY5_5_WIDTH _u(16) +#define OTP_DATA_KEY5_5_MSB _u(15) +#define OTP_DATA_KEY5_5_LSB _u(0) +#define OTP_DATA_KEY5_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_6 +// Description : Bits 111:96 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_6_ROW _u(0x00000f6e) +#define OTP_DATA_KEY5_6_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_6_RESET "-" +#define OTP_DATA_KEY5_6_WIDTH _u(16) +#define OTP_DATA_KEY5_6_MSB _u(15) +#define OTP_DATA_KEY5_6_LSB _u(0) +#define OTP_DATA_KEY5_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_7 +// Description : Bits 127:112 of OTP access key 5 (ECC) +#define OTP_DATA_KEY5_7_ROW _u(0x00000f6f) +#define OTP_DATA_KEY5_7_BITS _u(0x0000ffff) +#define OTP_DATA_KEY5_7_RESET "-" +#define OTP_DATA_KEY5_7_WIDTH _u(16) +#define OTP_DATA_KEY5_7_MSB _u(15) +#define OTP_DATA_KEY5_7_LSB _u(0) +#define OTP_DATA_KEY5_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_0 +// Description : Bits 15:0 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_0_ROW _u(0x00000f70) +#define OTP_DATA_KEY6_0_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_0_RESET "-" +#define OTP_DATA_KEY6_0_WIDTH _u(16) +#define OTP_DATA_KEY6_0_MSB _u(15) +#define OTP_DATA_KEY6_0_LSB _u(0) +#define OTP_DATA_KEY6_0_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_1 +// Description : Bits 31:16 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_1_ROW _u(0x00000f71) +#define OTP_DATA_KEY6_1_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_1_RESET "-" +#define OTP_DATA_KEY6_1_WIDTH _u(16) +#define OTP_DATA_KEY6_1_MSB _u(15) +#define OTP_DATA_KEY6_1_LSB _u(0) +#define OTP_DATA_KEY6_1_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_2 +// Description : Bits 47:32 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_2_ROW _u(0x00000f72) +#define OTP_DATA_KEY6_2_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_2_RESET "-" +#define OTP_DATA_KEY6_2_WIDTH _u(16) +#define OTP_DATA_KEY6_2_MSB _u(15) +#define OTP_DATA_KEY6_2_LSB _u(0) +#define OTP_DATA_KEY6_2_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_3 +// Description : Bits 63:48 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_3_ROW _u(0x00000f73) +#define OTP_DATA_KEY6_3_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_3_RESET "-" +#define OTP_DATA_KEY6_3_WIDTH _u(16) +#define OTP_DATA_KEY6_3_MSB _u(15) +#define OTP_DATA_KEY6_3_LSB _u(0) +#define OTP_DATA_KEY6_3_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_4 +// Description : Bits 79:64 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_4_ROW _u(0x00000f74) +#define OTP_DATA_KEY6_4_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_4_RESET "-" +#define OTP_DATA_KEY6_4_WIDTH _u(16) +#define OTP_DATA_KEY6_4_MSB _u(15) +#define OTP_DATA_KEY6_4_LSB _u(0) +#define OTP_DATA_KEY6_4_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_5 +// Description : Bits 95:80 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_5_ROW _u(0x00000f75) +#define OTP_DATA_KEY6_5_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_5_RESET "-" +#define OTP_DATA_KEY6_5_WIDTH _u(16) +#define OTP_DATA_KEY6_5_MSB _u(15) +#define OTP_DATA_KEY6_5_LSB _u(0) +#define OTP_DATA_KEY6_5_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_6 +// Description : Bits 111:96 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_6_ROW _u(0x00000f76) +#define OTP_DATA_KEY6_6_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_6_RESET "-" +#define OTP_DATA_KEY6_6_WIDTH _u(16) +#define OTP_DATA_KEY6_6_MSB _u(15) +#define OTP_DATA_KEY6_6_LSB _u(0) +#define OTP_DATA_KEY6_6_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_7 +// Description : Bits 127:112 of OTP access key 6 (ECC) +#define OTP_DATA_KEY6_7_ROW _u(0x00000f77) +#define OTP_DATA_KEY6_7_BITS _u(0x0000ffff) +#define OTP_DATA_KEY6_7_RESET "-" +#define OTP_DATA_KEY6_7_WIDTH _u(16) +#define OTP_DATA_KEY6_7_MSB _u(15) +#define OTP_DATA_KEY6_7_LSB _u(0) +#define OTP_DATA_KEY6_7_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY1_VALID +// Description : Valid flag for key 1. Once the valid flag is set, the key can +// no longer be read or written, and becomes a valid fixed key for +// protecting OTP pages. +#define OTP_DATA_KEY1_VALID_ROW _u(0x00000f79) +#define OTP_DATA_KEY1_VALID_BITS _u(0x00010101) +#define OTP_DATA_KEY1_VALID_RESET _u(0x00000000) +#define OTP_DATA_KEY1_VALID_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY1_VALID_VALID_R2 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY1_VALID_VALID_R2_RESET "-" +#define OTP_DATA_KEY1_VALID_VALID_R2_BITS _u(0x00010000) +#define OTP_DATA_KEY1_VALID_VALID_R2_MSB _u(16) +#define OTP_DATA_KEY1_VALID_VALID_R2_LSB _u(16) +#define OTP_DATA_KEY1_VALID_VALID_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY1_VALID_VALID_R1 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY1_VALID_VALID_R1_RESET "-" +#define OTP_DATA_KEY1_VALID_VALID_R1_BITS _u(0x00000100) +#define OTP_DATA_KEY1_VALID_VALID_R1_MSB _u(8) +#define OTP_DATA_KEY1_VALID_VALID_R1_LSB _u(8) +#define OTP_DATA_KEY1_VALID_VALID_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY1_VALID_VALID +#define OTP_DATA_KEY1_VALID_VALID_RESET "-" +#define OTP_DATA_KEY1_VALID_VALID_BITS _u(0x00000001) +#define OTP_DATA_KEY1_VALID_VALID_MSB _u(0) +#define OTP_DATA_KEY1_VALID_VALID_LSB _u(0) +#define OTP_DATA_KEY1_VALID_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY2_VALID +// Description : Valid flag for key 2. Once the valid flag is set, the key can +// no longer be read or written, and becomes a valid fixed key for +// protecting OTP pages. +#define OTP_DATA_KEY2_VALID_ROW _u(0x00000f7a) +#define OTP_DATA_KEY2_VALID_BITS _u(0x00010101) +#define OTP_DATA_KEY2_VALID_RESET _u(0x00000000) +#define OTP_DATA_KEY2_VALID_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY2_VALID_VALID_R2 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY2_VALID_VALID_R2_RESET "-" +#define OTP_DATA_KEY2_VALID_VALID_R2_BITS _u(0x00010000) +#define OTP_DATA_KEY2_VALID_VALID_R2_MSB _u(16) +#define OTP_DATA_KEY2_VALID_VALID_R2_LSB _u(16) +#define OTP_DATA_KEY2_VALID_VALID_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY2_VALID_VALID_R1 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY2_VALID_VALID_R1_RESET "-" +#define OTP_DATA_KEY2_VALID_VALID_R1_BITS _u(0x00000100) +#define OTP_DATA_KEY2_VALID_VALID_R1_MSB _u(8) +#define OTP_DATA_KEY2_VALID_VALID_R1_LSB _u(8) +#define OTP_DATA_KEY2_VALID_VALID_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY2_VALID_VALID +#define OTP_DATA_KEY2_VALID_VALID_RESET "-" +#define OTP_DATA_KEY2_VALID_VALID_BITS _u(0x00000001) +#define OTP_DATA_KEY2_VALID_VALID_MSB _u(0) +#define OTP_DATA_KEY2_VALID_VALID_LSB _u(0) +#define OTP_DATA_KEY2_VALID_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY3_VALID +// Description : Valid flag for key 3. Once the valid flag is set, the key can +// no longer be read or written, and becomes a valid fixed key for +// protecting OTP pages. +#define OTP_DATA_KEY3_VALID_ROW _u(0x00000f7b) +#define OTP_DATA_KEY3_VALID_BITS _u(0x00010101) +#define OTP_DATA_KEY3_VALID_RESET _u(0x00000000) +#define OTP_DATA_KEY3_VALID_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY3_VALID_VALID_R2 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY3_VALID_VALID_R2_RESET "-" +#define OTP_DATA_KEY3_VALID_VALID_R2_BITS _u(0x00010000) +#define OTP_DATA_KEY3_VALID_VALID_R2_MSB _u(16) +#define OTP_DATA_KEY3_VALID_VALID_R2_LSB _u(16) +#define OTP_DATA_KEY3_VALID_VALID_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY3_VALID_VALID_R1 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY3_VALID_VALID_R1_RESET "-" +#define OTP_DATA_KEY3_VALID_VALID_R1_BITS _u(0x00000100) +#define OTP_DATA_KEY3_VALID_VALID_R1_MSB _u(8) +#define OTP_DATA_KEY3_VALID_VALID_R1_LSB _u(8) +#define OTP_DATA_KEY3_VALID_VALID_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY3_VALID_VALID +#define OTP_DATA_KEY3_VALID_VALID_RESET "-" +#define OTP_DATA_KEY3_VALID_VALID_BITS _u(0x00000001) +#define OTP_DATA_KEY3_VALID_VALID_MSB _u(0) +#define OTP_DATA_KEY3_VALID_VALID_LSB _u(0) +#define OTP_DATA_KEY3_VALID_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY4_VALID +// Description : Valid flag for key 4. Once the valid flag is set, the key can +// no longer be read or written, and becomes a valid fixed key for +// protecting OTP pages. +#define OTP_DATA_KEY4_VALID_ROW _u(0x00000f7c) +#define OTP_DATA_KEY4_VALID_BITS _u(0x00010101) +#define OTP_DATA_KEY4_VALID_RESET _u(0x00000000) +#define OTP_DATA_KEY4_VALID_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY4_VALID_VALID_R2 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY4_VALID_VALID_R2_RESET "-" +#define OTP_DATA_KEY4_VALID_VALID_R2_BITS _u(0x00010000) +#define OTP_DATA_KEY4_VALID_VALID_R2_MSB _u(16) +#define OTP_DATA_KEY4_VALID_VALID_R2_LSB _u(16) +#define OTP_DATA_KEY4_VALID_VALID_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY4_VALID_VALID_R1 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY4_VALID_VALID_R1_RESET "-" +#define OTP_DATA_KEY4_VALID_VALID_R1_BITS _u(0x00000100) +#define OTP_DATA_KEY4_VALID_VALID_R1_MSB _u(8) +#define OTP_DATA_KEY4_VALID_VALID_R1_LSB _u(8) +#define OTP_DATA_KEY4_VALID_VALID_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY4_VALID_VALID +#define OTP_DATA_KEY4_VALID_VALID_RESET "-" +#define OTP_DATA_KEY4_VALID_VALID_BITS _u(0x00000001) +#define OTP_DATA_KEY4_VALID_VALID_MSB _u(0) +#define OTP_DATA_KEY4_VALID_VALID_LSB _u(0) +#define OTP_DATA_KEY4_VALID_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY5_VALID +// Description : Valid flag for key 5. Once the valid flag is set, the key can +// no longer be read or written, and becomes a valid fixed key for +// protecting OTP pages. +#define OTP_DATA_KEY5_VALID_ROW _u(0x00000f7d) +#define OTP_DATA_KEY5_VALID_BITS _u(0x00010101) +#define OTP_DATA_KEY5_VALID_RESET _u(0x00000000) +#define OTP_DATA_KEY5_VALID_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY5_VALID_VALID_R2 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY5_VALID_VALID_R2_RESET "-" +#define OTP_DATA_KEY5_VALID_VALID_R2_BITS _u(0x00010000) +#define OTP_DATA_KEY5_VALID_VALID_R2_MSB _u(16) +#define OTP_DATA_KEY5_VALID_VALID_R2_LSB _u(16) +#define OTP_DATA_KEY5_VALID_VALID_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY5_VALID_VALID_R1 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY5_VALID_VALID_R1_RESET "-" +#define OTP_DATA_KEY5_VALID_VALID_R1_BITS _u(0x00000100) +#define OTP_DATA_KEY5_VALID_VALID_R1_MSB _u(8) +#define OTP_DATA_KEY5_VALID_VALID_R1_LSB _u(8) +#define OTP_DATA_KEY5_VALID_VALID_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY5_VALID_VALID +#define OTP_DATA_KEY5_VALID_VALID_RESET "-" +#define OTP_DATA_KEY5_VALID_VALID_BITS _u(0x00000001) +#define OTP_DATA_KEY5_VALID_VALID_MSB _u(0) +#define OTP_DATA_KEY5_VALID_VALID_LSB _u(0) +#define OTP_DATA_KEY5_VALID_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_KEY6_VALID +// Description : Valid flag for key 6. Once the valid flag is set, the key can +// no longer be read or written, and becomes a valid fixed key for +// protecting OTP pages. +#define OTP_DATA_KEY6_VALID_ROW _u(0x00000f7e) +#define OTP_DATA_KEY6_VALID_BITS _u(0x00010101) +#define OTP_DATA_KEY6_VALID_RESET _u(0x00000000) +#define OTP_DATA_KEY6_VALID_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY6_VALID_VALID_R2 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY6_VALID_VALID_R2_RESET "-" +#define OTP_DATA_KEY6_VALID_VALID_R2_BITS _u(0x00010000) +#define OTP_DATA_KEY6_VALID_VALID_R2_MSB _u(16) +#define OTP_DATA_KEY6_VALID_VALID_R2_LSB _u(16) +#define OTP_DATA_KEY6_VALID_VALID_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY6_VALID_VALID_R1 +// Description : Redundant copy of VALID, with 3-way majority vote +#define OTP_DATA_KEY6_VALID_VALID_R1_RESET "-" +#define OTP_DATA_KEY6_VALID_VALID_R1_BITS _u(0x00000100) +#define OTP_DATA_KEY6_VALID_VALID_R1_MSB _u(8) +#define OTP_DATA_KEY6_VALID_VALID_R1_LSB _u(8) +#define OTP_DATA_KEY6_VALID_VALID_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_KEY6_VALID_VALID +#define OTP_DATA_KEY6_VALID_VALID_RESET "-" +#define OTP_DATA_KEY6_VALID_VALID_BITS _u(0x00000001) +#define OTP_DATA_KEY6_VALID_VALID_MSB _u(0) +#define OTP_DATA_KEY6_VALID_VALID_LSB _u(0) +#define OTP_DATA_KEY6_VALID_VALID_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE0_LOCK0 +// Description : Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE0_LOCK0_ROW _u(0x00000f80) +#define OTP_DATA_PAGE0_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE0_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE0_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE0_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE0_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE0_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE0_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE0_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE0_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE0_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE0_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE0_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE0_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE0_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE0_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE0_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE0_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE0_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE0_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE0_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE0_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE0_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE0_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE0_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE0_LOCK1 +// Description : Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE0_LOCK1_ROW _u(0x00000f81) +#define OTP_DATA_PAGE0_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE0_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE0_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE0_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE0_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE0_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE0_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE0_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE0_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE0_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE0_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE0_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE0_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE0_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE0_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE0_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE0_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE1_LOCK0 +// Description : Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE1_LOCK0_ROW _u(0x00000f82) +#define OTP_DATA_PAGE1_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE1_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE1_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE1_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE1_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE1_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE1_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE1_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE1_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE1_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE1_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE1_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE1_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE1_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE1_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE1_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE1_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE1_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE1_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE1_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE1_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE1_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE1_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE1_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE1_LOCK1 +// Description : Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE1_LOCK1_ROW _u(0x00000f83) +#define OTP_DATA_PAGE1_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE1_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE1_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE1_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE1_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE1_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE1_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE1_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE1_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE1_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE1_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE1_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE1_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE1_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE1_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE1_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE1_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE2_LOCK0 +// Description : Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE2_LOCK0_ROW _u(0x00000f84) +#define OTP_DATA_PAGE2_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE2_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE2_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE2_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE2_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE2_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE2_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE2_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE2_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE2_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE2_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE2_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE2_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE2_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE2_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE2_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE2_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE2_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE2_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE2_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE2_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE2_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE2_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE2_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE2_LOCK1 +// Description : Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE2_LOCK1_ROW _u(0x00000f85) +#define OTP_DATA_PAGE2_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE2_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE2_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE2_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE2_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE2_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE2_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE2_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE2_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE2_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE2_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE2_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE2_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE2_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE2_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE2_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE2_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE3_LOCK0 +// Description : Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE3_LOCK0_ROW _u(0x00000f86) +#define OTP_DATA_PAGE3_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE3_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE3_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE3_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE3_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE3_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE3_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE3_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE3_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE3_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE3_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE3_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE3_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE3_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE3_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE3_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE3_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE3_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE3_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE3_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE3_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE3_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE3_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE3_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE3_LOCK1 +// Description : Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE3_LOCK1_ROW _u(0x00000f87) +#define OTP_DATA_PAGE3_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE3_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE3_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE3_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE3_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE3_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE3_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE3_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE3_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE3_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE3_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE3_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE3_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE3_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE3_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE3_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE3_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE4_LOCK0 +// Description : Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE4_LOCK0_ROW _u(0x00000f88) +#define OTP_DATA_PAGE4_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE4_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE4_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE4_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE4_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE4_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE4_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE4_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE4_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE4_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE4_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE4_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE4_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE4_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE4_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE4_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE4_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE4_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE4_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE4_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE4_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE4_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE4_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE4_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE4_LOCK1 +// Description : Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE4_LOCK1_ROW _u(0x00000f89) +#define OTP_DATA_PAGE4_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE4_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE4_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE4_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE4_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE4_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE4_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE4_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE4_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE4_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE4_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE4_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE4_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE4_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE4_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE4_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE4_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE5_LOCK0 +// Description : Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE5_LOCK0_ROW _u(0x00000f8a) +#define OTP_DATA_PAGE5_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE5_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE5_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE5_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE5_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE5_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE5_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE5_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE5_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE5_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE5_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE5_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE5_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE5_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE5_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE5_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE5_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE5_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE5_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE5_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE5_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE5_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE5_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE5_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE5_LOCK1 +// Description : Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE5_LOCK1_ROW _u(0x00000f8b) +#define OTP_DATA_PAGE5_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE5_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE5_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE5_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE5_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE5_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE5_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE5_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE5_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE5_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE5_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE5_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE5_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE5_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE5_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE5_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE5_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE6_LOCK0 +// Description : Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE6_LOCK0_ROW _u(0x00000f8c) +#define OTP_DATA_PAGE6_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE6_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE6_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE6_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE6_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE6_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE6_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE6_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE6_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE6_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE6_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE6_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE6_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE6_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE6_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE6_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE6_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE6_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE6_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE6_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE6_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE6_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE6_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE6_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE6_LOCK1 +// Description : Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE6_LOCK1_ROW _u(0x00000f8d) +#define OTP_DATA_PAGE6_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE6_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE6_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE6_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE6_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE6_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE6_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE6_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE6_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE6_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE6_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE6_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE6_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE6_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE6_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE6_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE6_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE7_LOCK0 +// Description : Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE7_LOCK0_ROW _u(0x00000f8e) +#define OTP_DATA_PAGE7_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE7_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE7_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE7_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE7_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE7_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE7_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE7_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE7_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE7_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE7_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE7_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE7_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE7_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE7_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE7_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE7_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE7_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE7_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE7_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE7_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE7_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE7_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE7_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE7_LOCK1 +// Description : Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE7_LOCK1_ROW _u(0x00000f8f) +#define OTP_DATA_PAGE7_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE7_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE7_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE7_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE7_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE7_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE7_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE7_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE7_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE7_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE7_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE7_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE7_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE7_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE7_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE7_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE7_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE8_LOCK0 +// Description : Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE8_LOCK0_ROW _u(0x00000f90) +#define OTP_DATA_PAGE8_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE8_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE8_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE8_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE8_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE8_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE8_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE8_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE8_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE8_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE8_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE8_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE8_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE8_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE8_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE8_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE8_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE8_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE8_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE8_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE8_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE8_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE8_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE8_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE8_LOCK1 +// Description : Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE8_LOCK1_ROW _u(0x00000f91) +#define OTP_DATA_PAGE8_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE8_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE8_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE8_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE8_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE8_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE8_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE8_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE8_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE8_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE8_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE8_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE8_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE8_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE8_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE8_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE8_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE9_LOCK0 +// Description : Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE9_LOCK0_ROW _u(0x00000f92) +#define OTP_DATA_PAGE9_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE9_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE9_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE9_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE9_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE9_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE9_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE9_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE9_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE9_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE9_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE9_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE9_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE9_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE9_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE9_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE9_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE9_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE9_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE9_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE9_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE9_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE9_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE9_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE9_LOCK1 +// Description : Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE9_LOCK1_ROW _u(0x00000f93) +#define OTP_DATA_PAGE9_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE9_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE9_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE9_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE9_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE9_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE9_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE9_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE9_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE9_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE9_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE9_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE9_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE9_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE9_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE9_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE9_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE10_LOCK0 +// Description : Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE10_LOCK0_ROW _u(0x00000f94) +#define OTP_DATA_PAGE10_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE10_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE10_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE10_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE10_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE10_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE10_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE10_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE10_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE10_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE10_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE10_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE10_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE10_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE10_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE10_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE10_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE10_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE10_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE10_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE10_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE10_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE10_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE10_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE10_LOCK1 +// Description : Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE10_LOCK1_ROW _u(0x00000f95) +#define OTP_DATA_PAGE10_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE10_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE10_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE10_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE10_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE10_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE10_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE10_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE10_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE10_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE10_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE10_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE10_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE10_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE10_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE10_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE10_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE11_LOCK0 +// Description : Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE11_LOCK0_ROW _u(0x00000f96) +#define OTP_DATA_PAGE11_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE11_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE11_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE11_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE11_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE11_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE11_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE11_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE11_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE11_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE11_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE11_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE11_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE11_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE11_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE11_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE11_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE11_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE11_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE11_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE11_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE11_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE11_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE11_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE11_LOCK1 +// Description : Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE11_LOCK1_ROW _u(0x00000f97) +#define OTP_DATA_PAGE11_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE11_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE11_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE11_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE11_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE11_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE11_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE11_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE11_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE11_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE11_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE11_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE11_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE11_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE11_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE11_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE11_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE12_LOCK0 +// Description : Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE12_LOCK0_ROW _u(0x00000f98) +#define OTP_DATA_PAGE12_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE12_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE12_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE12_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE12_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE12_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE12_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE12_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE12_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE12_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE12_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE12_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE12_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE12_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE12_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE12_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE12_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE12_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE12_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE12_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE12_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE12_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE12_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE12_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE12_LOCK1 +// Description : Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE12_LOCK1_ROW _u(0x00000f99) +#define OTP_DATA_PAGE12_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE12_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE12_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE12_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE12_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE12_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE12_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE12_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE12_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE12_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE12_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE12_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE12_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE12_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE12_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE12_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE12_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE13_LOCK0 +// Description : Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE13_LOCK0_ROW _u(0x00000f9a) +#define OTP_DATA_PAGE13_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE13_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE13_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE13_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE13_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE13_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE13_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE13_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE13_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE13_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE13_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE13_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE13_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE13_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE13_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE13_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE13_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE13_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE13_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE13_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE13_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE13_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE13_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE13_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE13_LOCK1 +// Description : Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE13_LOCK1_ROW _u(0x00000f9b) +#define OTP_DATA_PAGE13_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE13_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE13_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE13_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE13_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE13_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE13_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE13_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE13_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE13_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE13_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE13_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE13_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE13_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE13_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE13_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE13_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE14_LOCK0 +// Description : Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE14_LOCK0_ROW _u(0x00000f9c) +#define OTP_DATA_PAGE14_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE14_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE14_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE14_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE14_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE14_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE14_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE14_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE14_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE14_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE14_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE14_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE14_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE14_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE14_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE14_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE14_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE14_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE14_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE14_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE14_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE14_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE14_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE14_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE14_LOCK1 +// Description : Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE14_LOCK1_ROW _u(0x00000f9d) +#define OTP_DATA_PAGE14_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE14_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE14_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE14_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE14_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE14_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE14_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE14_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE14_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE14_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE14_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE14_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE14_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE14_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE14_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE14_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE14_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE15_LOCK0 +// Description : Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE15_LOCK0_ROW _u(0x00000f9e) +#define OTP_DATA_PAGE15_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE15_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE15_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE15_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE15_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE15_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE15_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE15_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE15_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE15_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE15_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE15_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE15_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE15_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE15_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE15_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE15_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE15_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE15_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE15_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE15_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE15_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE15_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE15_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE15_LOCK1 +// Description : Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE15_LOCK1_ROW _u(0x00000f9f) +#define OTP_DATA_PAGE15_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE15_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE15_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE15_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE15_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE15_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE15_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE15_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE15_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE15_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE15_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE15_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE15_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE15_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE15_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE15_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE15_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE16_LOCK0 +// Description : Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE16_LOCK0_ROW _u(0x00000fa0) +#define OTP_DATA_PAGE16_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE16_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE16_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE16_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE16_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE16_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE16_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE16_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE16_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE16_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE16_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE16_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE16_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE16_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE16_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE16_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE16_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE16_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE16_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE16_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE16_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE16_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE16_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE16_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE16_LOCK1 +// Description : Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE16_LOCK1_ROW _u(0x00000fa1) +#define OTP_DATA_PAGE16_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE16_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE16_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE16_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE16_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE16_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE16_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE16_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE16_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE16_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE16_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE16_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE16_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE16_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE16_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE16_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE16_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE17_LOCK0 +// Description : Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE17_LOCK0_ROW _u(0x00000fa2) +#define OTP_DATA_PAGE17_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE17_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE17_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE17_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE17_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE17_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE17_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE17_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE17_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE17_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE17_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE17_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE17_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE17_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE17_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE17_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE17_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE17_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE17_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE17_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE17_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE17_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE17_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE17_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE17_LOCK1 +// Description : Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE17_LOCK1_ROW _u(0x00000fa3) +#define OTP_DATA_PAGE17_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE17_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE17_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE17_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE17_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE17_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE17_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE17_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE17_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE17_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE17_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE17_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE17_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE17_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE17_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE17_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE17_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE18_LOCK0 +// Description : Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE18_LOCK0_ROW _u(0x00000fa4) +#define OTP_DATA_PAGE18_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE18_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE18_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE18_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE18_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE18_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE18_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE18_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE18_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE18_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE18_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE18_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE18_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE18_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE18_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE18_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE18_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE18_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE18_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE18_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE18_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE18_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE18_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE18_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE18_LOCK1 +// Description : Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE18_LOCK1_ROW _u(0x00000fa5) +#define OTP_DATA_PAGE18_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE18_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE18_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE18_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE18_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE18_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE18_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE18_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE18_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE18_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE18_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE18_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE18_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE18_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE18_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE18_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE18_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE19_LOCK0 +// Description : Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE19_LOCK0_ROW _u(0x00000fa6) +#define OTP_DATA_PAGE19_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE19_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE19_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE19_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE19_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE19_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE19_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE19_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE19_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE19_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE19_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE19_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE19_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE19_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE19_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE19_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE19_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE19_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE19_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE19_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE19_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE19_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE19_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE19_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE19_LOCK1 +// Description : Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE19_LOCK1_ROW _u(0x00000fa7) +#define OTP_DATA_PAGE19_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE19_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE19_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE19_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE19_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE19_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE19_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE19_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE19_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE19_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE19_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE19_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE19_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE19_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE19_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE19_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE19_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE20_LOCK0 +// Description : Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE20_LOCK0_ROW _u(0x00000fa8) +#define OTP_DATA_PAGE20_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE20_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE20_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE20_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE20_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE20_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE20_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE20_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE20_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE20_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE20_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE20_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE20_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE20_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE20_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE20_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE20_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE20_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE20_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE20_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE20_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE20_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE20_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE20_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE20_LOCK1 +// Description : Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE20_LOCK1_ROW _u(0x00000fa9) +#define OTP_DATA_PAGE20_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE20_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE20_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE20_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE20_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE20_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE20_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE20_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE20_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE20_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE20_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE20_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE20_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE20_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE20_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE20_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE20_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE21_LOCK0 +// Description : Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE21_LOCK0_ROW _u(0x00000faa) +#define OTP_DATA_PAGE21_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE21_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE21_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE21_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE21_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE21_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE21_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE21_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE21_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE21_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE21_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE21_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE21_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE21_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE21_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE21_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE21_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE21_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE21_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE21_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE21_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE21_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE21_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE21_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE21_LOCK1 +// Description : Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE21_LOCK1_ROW _u(0x00000fab) +#define OTP_DATA_PAGE21_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE21_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE21_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE21_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE21_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE21_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE21_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE21_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE21_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE21_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE21_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE21_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE21_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE21_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE21_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE21_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE21_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE22_LOCK0 +// Description : Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE22_LOCK0_ROW _u(0x00000fac) +#define OTP_DATA_PAGE22_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE22_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE22_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE22_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE22_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE22_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE22_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE22_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE22_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE22_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE22_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE22_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE22_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE22_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE22_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE22_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE22_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE22_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE22_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE22_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE22_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE22_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE22_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE22_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE22_LOCK1 +// Description : Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE22_LOCK1_ROW _u(0x00000fad) +#define OTP_DATA_PAGE22_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE22_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE22_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE22_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE22_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE22_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE22_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE22_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE22_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE22_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE22_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE22_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE22_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE22_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE22_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE22_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE22_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE23_LOCK0 +// Description : Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE23_LOCK0_ROW _u(0x00000fae) +#define OTP_DATA_PAGE23_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE23_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE23_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE23_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE23_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE23_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE23_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE23_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE23_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE23_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE23_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE23_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE23_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE23_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE23_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE23_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE23_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE23_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE23_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE23_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE23_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE23_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE23_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE23_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE23_LOCK1 +// Description : Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE23_LOCK1_ROW _u(0x00000faf) +#define OTP_DATA_PAGE23_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE23_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE23_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE23_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE23_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE23_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE23_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE23_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE23_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE23_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE23_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE23_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE23_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE23_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE23_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE23_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE23_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE24_LOCK0 +// Description : Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE24_LOCK0_ROW _u(0x00000fb0) +#define OTP_DATA_PAGE24_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE24_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE24_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE24_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE24_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE24_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE24_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE24_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE24_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE24_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE24_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE24_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE24_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE24_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE24_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE24_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE24_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE24_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE24_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE24_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE24_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE24_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE24_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE24_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE24_LOCK1 +// Description : Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE24_LOCK1_ROW _u(0x00000fb1) +#define OTP_DATA_PAGE24_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE24_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE24_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE24_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE24_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE24_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE24_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE24_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE24_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE24_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE24_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE24_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE24_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE24_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE24_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE24_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE24_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE25_LOCK0 +// Description : Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE25_LOCK0_ROW _u(0x00000fb2) +#define OTP_DATA_PAGE25_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE25_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE25_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE25_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE25_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE25_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE25_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE25_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE25_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE25_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE25_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE25_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE25_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE25_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE25_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE25_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE25_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE25_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE25_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE25_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE25_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE25_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE25_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE25_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE25_LOCK1 +// Description : Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE25_LOCK1_ROW _u(0x00000fb3) +#define OTP_DATA_PAGE25_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE25_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE25_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE25_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE25_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE25_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE25_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE25_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE25_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE25_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE25_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE25_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE25_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE25_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE25_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE25_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE25_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE26_LOCK0 +// Description : Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE26_LOCK0_ROW _u(0x00000fb4) +#define OTP_DATA_PAGE26_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE26_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE26_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE26_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE26_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE26_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE26_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE26_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE26_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE26_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE26_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE26_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE26_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE26_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE26_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE26_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE26_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE26_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE26_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE26_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE26_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE26_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE26_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE26_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE26_LOCK1 +// Description : Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE26_LOCK1_ROW _u(0x00000fb5) +#define OTP_DATA_PAGE26_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE26_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE26_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE26_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE26_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE26_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE26_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE26_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE26_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE26_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE26_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE26_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE26_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE26_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE26_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE26_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE26_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE27_LOCK0 +// Description : Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE27_LOCK0_ROW _u(0x00000fb6) +#define OTP_DATA_PAGE27_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE27_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE27_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE27_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE27_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE27_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE27_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE27_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE27_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE27_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE27_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE27_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE27_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE27_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE27_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE27_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE27_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE27_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE27_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE27_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE27_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE27_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE27_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE27_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE27_LOCK1 +// Description : Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE27_LOCK1_ROW _u(0x00000fb7) +#define OTP_DATA_PAGE27_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE27_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE27_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE27_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE27_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE27_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE27_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE27_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE27_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE27_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE27_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE27_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE27_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE27_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE27_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE27_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE27_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE28_LOCK0 +// Description : Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE28_LOCK0_ROW _u(0x00000fb8) +#define OTP_DATA_PAGE28_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE28_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE28_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE28_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE28_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE28_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE28_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE28_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE28_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE28_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE28_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE28_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE28_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE28_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE28_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE28_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE28_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE28_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE28_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE28_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE28_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE28_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE28_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE28_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE28_LOCK1 +// Description : Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE28_LOCK1_ROW _u(0x00000fb9) +#define OTP_DATA_PAGE28_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE28_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE28_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE28_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE28_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE28_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE28_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE28_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE28_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE28_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE28_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE28_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE28_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE28_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE28_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE28_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE28_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE29_LOCK0 +// Description : Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE29_LOCK0_ROW _u(0x00000fba) +#define OTP_DATA_PAGE29_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE29_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE29_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE29_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE29_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE29_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE29_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE29_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE29_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE29_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE29_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE29_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE29_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE29_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE29_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE29_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE29_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE29_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE29_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE29_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE29_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE29_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE29_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE29_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE29_LOCK1 +// Description : Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE29_LOCK1_ROW _u(0x00000fbb) +#define OTP_DATA_PAGE29_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE29_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE29_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE29_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE29_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE29_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE29_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE29_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE29_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE29_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE29_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE29_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE29_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE29_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE29_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE29_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE29_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE30_LOCK0 +// Description : Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE30_LOCK0_ROW _u(0x00000fbc) +#define OTP_DATA_PAGE30_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE30_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE30_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE30_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE30_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE30_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE30_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE30_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE30_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE30_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE30_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE30_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE30_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE30_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE30_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE30_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE30_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE30_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE30_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE30_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE30_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE30_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE30_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE30_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE30_LOCK1 +// Description : Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE30_LOCK1_ROW _u(0x00000fbd) +#define OTP_DATA_PAGE30_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE30_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE30_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE30_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE30_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE30_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE30_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE30_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE30_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE30_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE30_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE30_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE30_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE30_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE30_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE30_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE30_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE31_LOCK0 +// Description : Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE31_LOCK0_ROW _u(0x00000fbe) +#define OTP_DATA_PAGE31_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE31_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE31_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE31_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE31_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE31_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE31_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE31_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE31_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE31_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE31_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE31_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE31_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE31_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE31_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE31_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE31_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE31_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE31_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE31_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE31_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE31_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE31_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE31_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE31_LOCK1 +// Description : Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE31_LOCK1_ROW _u(0x00000fbf) +#define OTP_DATA_PAGE31_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE31_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE31_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE31_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE31_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE31_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE31_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE31_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE31_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE31_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE31_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE31_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE31_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE31_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE31_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE31_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE31_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE32_LOCK0 +// Description : Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE32_LOCK0_ROW _u(0x00000fc0) +#define OTP_DATA_PAGE32_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE32_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE32_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE32_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE32_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE32_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE32_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE32_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE32_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE32_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE32_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE32_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE32_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE32_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE32_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE32_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE32_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE32_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE32_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE32_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE32_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE32_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE32_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE32_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE32_LOCK1 +// Description : Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE32_LOCK1_ROW _u(0x00000fc1) +#define OTP_DATA_PAGE32_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE32_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE32_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE32_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE32_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE32_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE32_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE32_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE32_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE32_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE32_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE32_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE32_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE32_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE32_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE32_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE32_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE33_LOCK0 +// Description : Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE33_LOCK0_ROW _u(0x00000fc2) +#define OTP_DATA_PAGE33_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE33_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE33_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE33_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE33_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE33_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE33_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE33_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE33_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE33_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE33_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE33_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE33_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE33_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE33_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE33_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE33_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE33_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE33_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE33_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE33_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE33_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE33_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE33_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE33_LOCK1 +// Description : Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE33_LOCK1_ROW _u(0x00000fc3) +#define OTP_DATA_PAGE33_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE33_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE33_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE33_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE33_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE33_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE33_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE33_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE33_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE33_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE33_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE33_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE33_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE33_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE33_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE33_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE33_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE34_LOCK0 +// Description : Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE34_LOCK0_ROW _u(0x00000fc4) +#define OTP_DATA_PAGE34_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE34_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE34_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE34_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE34_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE34_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE34_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE34_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE34_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE34_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE34_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE34_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE34_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE34_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE34_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE34_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE34_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE34_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE34_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE34_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE34_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE34_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE34_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE34_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE34_LOCK1 +// Description : Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE34_LOCK1_ROW _u(0x00000fc5) +#define OTP_DATA_PAGE34_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE34_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE34_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE34_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE34_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE34_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE34_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE34_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE34_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE34_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE34_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE34_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE34_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE34_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE34_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE34_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE34_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE35_LOCK0 +// Description : Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE35_LOCK0_ROW _u(0x00000fc6) +#define OTP_DATA_PAGE35_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE35_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE35_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE35_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE35_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE35_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE35_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE35_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE35_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE35_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE35_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE35_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE35_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE35_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE35_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE35_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE35_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE35_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE35_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE35_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE35_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE35_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE35_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE35_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE35_LOCK1 +// Description : Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE35_LOCK1_ROW _u(0x00000fc7) +#define OTP_DATA_PAGE35_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE35_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE35_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE35_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE35_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE35_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE35_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE35_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE35_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE35_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE35_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE35_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE35_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE35_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE35_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE35_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE35_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE36_LOCK0 +// Description : Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE36_LOCK0_ROW _u(0x00000fc8) +#define OTP_DATA_PAGE36_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE36_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE36_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE36_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE36_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE36_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE36_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE36_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE36_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE36_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE36_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE36_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE36_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE36_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE36_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE36_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE36_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE36_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE36_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE36_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE36_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE36_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE36_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE36_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE36_LOCK1 +// Description : Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE36_LOCK1_ROW _u(0x00000fc9) +#define OTP_DATA_PAGE36_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE36_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE36_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE36_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE36_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE36_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE36_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE36_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE36_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE36_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE36_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE36_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE36_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE36_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE36_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE36_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE36_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE37_LOCK0 +// Description : Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE37_LOCK0_ROW _u(0x00000fca) +#define OTP_DATA_PAGE37_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE37_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE37_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE37_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE37_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE37_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE37_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE37_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE37_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE37_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE37_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE37_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE37_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE37_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE37_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE37_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE37_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE37_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE37_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE37_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE37_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE37_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE37_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE37_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE37_LOCK1 +// Description : Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE37_LOCK1_ROW _u(0x00000fcb) +#define OTP_DATA_PAGE37_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE37_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE37_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE37_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE37_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE37_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE37_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE37_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE37_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE37_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE37_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE37_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE37_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE37_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE37_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE37_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE37_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE38_LOCK0 +// Description : Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE38_LOCK0_ROW _u(0x00000fcc) +#define OTP_DATA_PAGE38_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE38_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE38_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE38_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE38_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE38_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE38_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE38_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE38_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE38_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE38_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE38_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE38_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE38_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE38_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE38_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE38_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE38_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE38_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE38_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE38_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE38_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE38_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE38_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE38_LOCK1 +// Description : Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE38_LOCK1_ROW _u(0x00000fcd) +#define OTP_DATA_PAGE38_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE38_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE38_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE38_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE38_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE38_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE38_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE38_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE38_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE38_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE38_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE38_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE38_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE38_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE38_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE38_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE38_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE39_LOCK0 +// Description : Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE39_LOCK0_ROW _u(0x00000fce) +#define OTP_DATA_PAGE39_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE39_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE39_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE39_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE39_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE39_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE39_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE39_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE39_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE39_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE39_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE39_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE39_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE39_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE39_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE39_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE39_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE39_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE39_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE39_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE39_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE39_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE39_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE39_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE39_LOCK1 +// Description : Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE39_LOCK1_ROW _u(0x00000fcf) +#define OTP_DATA_PAGE39_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE39_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE39_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE39_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE39_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE39_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE39_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE39_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE39_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE39_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE39_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE39_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE39_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE39_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE39_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE39_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE39_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE40_LOCK0 +// Description : Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE40_LOCK0_ROW _u(0x00000fd0) +#define OTP_DATA_PAGE40_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE40_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE40_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE40_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE40_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE40_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE40_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE40_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE40_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE40_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE40_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE40_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE40_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE40_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE40_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE40_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE40_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE40_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE40_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE40_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE40_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE40_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE40_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE40_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE40_LOCK1 +// Description : Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE40_LOCK1_ROW _u(0x00000fd1) +#define OTP_DATA_PAGE40_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE40_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE40_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE40_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE40_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE40_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE40_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE40_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE40_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE40_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE40_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE40_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE40_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE40_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE40_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE40_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE40_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE41_LOCK0 +// Description : Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE41_LOCK0_ROW _u(0x00000fd2) +#define OTP_DATA_PAGE41_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE41_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE41_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE41_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE41_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE41_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE41_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE41_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE41_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE41_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE41_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE41_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE41_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE41_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE41_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE41_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE41_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE41_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE41_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE41_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE41_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE41_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE41_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE41_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE41_LOCK1 +// Description : Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE41_LOCK1_ROW _u(0x00000fd3) +#define OTP_DATA_PAGE41_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE41_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE41_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE41_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE41_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE41_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE41_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE41_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE41_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE41_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE41_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE41_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE41_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE41_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE41_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE41_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE41_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE42_LOCK0 +// Description : Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE42_LOCK0_ROW _u(0x00000fd4) +#define OTP_DATA_PAGE42_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE42_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE42_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE42_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE42_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE42_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE42_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE42_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE42_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE42_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE42_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE42_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE42_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE42_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE42_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE42_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE42_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE42_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE42_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE42_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE42_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE42_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE42_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE42_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE42_LOCK1 +// Description : Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE42_LOCK1_ROW _u(0x00000fd5) +#define OTP_DATA_PAGE42_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE42_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE42_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE42_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE42_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE42_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE42_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE42_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE42_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE42_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE42_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE42_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE42_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE42_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE42_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE42_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE42_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE43_LOCK0 +// Description : Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE43_LOCK0_ROW _u(0x00000fd6) +#define OTP_DATA_PAGE43_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE43_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE43_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE43_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE43_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE43_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE43_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE43_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE43_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE43_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE43_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE43_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE43_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE43_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE43_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE43_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE43_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE43_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE43_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE43_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE43_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE43_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE43_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE43_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE43_LOCK1 +// Description : Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE43_LOCK1_ROW _u(0x00000fd7) +#define OTP_DATA_PAGE43_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE43_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE43_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE43_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE43_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE43_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE43_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE43_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE43_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE43_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE43_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE43_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE43_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE43_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE43_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE43_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE43_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE44_LOCK0 +// Description : Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE44_LOCK0_ROW _u(0x00000fd8) +#define OTP_DATA_PAGE44_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE44_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE44_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE44_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE44_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE44_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE44_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE44_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE44_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE44_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE44_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE44_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE44_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE44_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE44_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE44_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE44_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE44_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE44_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE44_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE44_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE44_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE44_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE44_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE44_LOCK1 +// Description : Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE44_LOCK1_ROW _u(0x00000fd9) +#define OTP_DATA_PAGE44_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE44_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE44_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE44_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE44_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE44_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE44_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE44_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE44_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE44_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE44_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE44_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE44_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE44_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE44_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE44_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE44_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE45_LOCK0 +// Description : Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE45_LOCK0_ROW _u(0x00000fda) +#define OTP_DATA_PAGE45_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE45_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE45_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE45_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE45_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE45_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE45_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE45_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE45_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE45_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE45_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE45_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE45_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE45_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE45_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE45_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE45_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE45_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE45_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE45_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE45_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE45_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE45_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE45_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE45_LOCK1 +// Description : Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE45_LOCK1_ROW _u(0x00000fdb) +#define OTP_DATA_PAGE45_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE45_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE45_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE45_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE45_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE45_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE45_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE45_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE45_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE45_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE45_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE45_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE45_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE45_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE45_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE45_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE45_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE46_LOCK0 +// Description : Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE46_LOCK0_ROW _u(0x00000fdc) +#define OTP_DATA_PAGE46_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE46_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE46_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE46_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE46_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE46_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE46_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE46_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE46_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE46_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE46_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE46_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE46_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE46_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE46_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE46_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE46_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE46_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE46_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE46_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE46_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE46_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE46_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE46_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE46_LOCK1 +// Description : Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE46_LOCK1_ROW _u(0x00000fdd) +#define OTP_DATA_PAGE46_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE46_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE46_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE46_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE46_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE46_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE46_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE46_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE46_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE46_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE46_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE46_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE46_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE46_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE46_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE46_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE46_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE47_LOCK0 +// Description : Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE47_LOCK0_ROW _u(0x00000fde) +#define OTP_DATA_PAGE47_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE47_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE47_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE47_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE47_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE47_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE47_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE47_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE47_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE47_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE47_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE47_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE47_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE47_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE47_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE47_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE47_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE47_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE47_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE47_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE47_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE47_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE47_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE47_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE47_LOCK1 +// Description : Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE47_LOCK1_ROW _u(0x00000fdf) +#define OTP_DATA_PAGE47_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE47_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE47_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE47_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE47_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE47_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE47_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE47_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE47_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE47_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE47_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE47_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE47_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE47_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE47_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE47_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE47_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE48_LOCK0 +// Description : Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE48_LOCK0_ROW _u(0x00000fe0) +#define OTP_DATA_PAGE48_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE48_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE48_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE48_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE48_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE48_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE48_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE48_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE48_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE48_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE48_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE48_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE48_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE48_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE48_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE48_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE48_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE48_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE48_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE48_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE48_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE48_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE48_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE48_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE48_LOCK1 +// Description : Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE48_LOCK1_ROW _u(0x00000fe1) +#define OTP_DATA_PAGE48_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE48_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE48_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE48_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE48_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE48_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE48_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE48_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE48_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE48_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE48_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE48_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE48_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE48_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE48_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE48_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE48_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE49_LOCK0 +// Description : Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE49_LOCK0_ROW _u(0x00000fe2) +#define OTP_DATA_PAGE49_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE49_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE49_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE49_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE49_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE49_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE49_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE49_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE49_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE49_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE49_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE49_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE49_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE49_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE49_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE49_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE49_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE49_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE49_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE49_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE49_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE49_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE49_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE49_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE49_LOCK1 +// Description : Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE49_LOCK1_ROW _u(0x00000fe3) +#define OTP_DATA_PAGE49_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE49_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE49_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE49_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE49_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE49_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE49_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE49_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE49_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE49_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE49_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE49_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE49_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE49_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE49_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE49_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE49_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE50_LOCK0 +// Description : Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE50_LOCK0_ROW _u(0x00000fe4) +#define OTP_DATA_PAGE50_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE50_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE50_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE50_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE50_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE50_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE50_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE50_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE50_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE50_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE50_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE50_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE50_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE50_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE50_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE50_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE50_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE50_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE50_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE50_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE50_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE50_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE50_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE50_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE50_LOCK1 +// Description : Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE50_LOCK1_ROW _u(0x00000fe5) +#define OTP_DATA_PAGE50_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE50_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE50_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE50_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE50_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE50_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE50_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE50_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE50_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE50_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE50_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE50_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE50_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE50_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE50_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE50_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE50_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE51_LOCK0 +// Description : Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE51_LOCK0_ROW _u(0x00000fe6) +#define OTP_DATA_PAGE51_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE51_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE51_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE51_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE51_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE51_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE51_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE51_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE51_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE51_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE51_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE51_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE51_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE51_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE51_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE51_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE51_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE51_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE51_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE51_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE51_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE51_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE51_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE51_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE51_LOCK1 +// Description : Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE51_LOCK1_ROW _u(0x00000fe7) +#define OTP_DATA_PAGE51_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE51_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE51_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE51_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE51_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE51_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE51_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE51_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE51_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE51_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE51_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE51_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE51_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE51_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE51_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE51_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE51_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE52_LOCK0 +// Description : Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE52_LOCK0_ROW _u(0x00000fe8) +#define OTP_DATA_PAGE52_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE52_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE52_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE52_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE52_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE52_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE52_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE52_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE52_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE52_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE52_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE52_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE52_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE52_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE52_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE52_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE52_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE52_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE52_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE52_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE52_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE52_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE52_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE52_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE52_LOCK1 +// Description : Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE52_LOCK1_ROW _u(0x00000fe9) +#define OTP_DATA_PAGE52_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE52_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE52_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE52_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE52_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE52_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE52_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE52_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE52_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE52_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE52_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE52_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE52_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE52_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE52_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE52_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE52_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE53_LOCK0 +// Description : Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE53_LOCK0_ROW _u(0x00000fea) +#define OTP_DATA_PAGE53_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE53_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE53_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE53_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE53_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE53_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE53_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE53_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE53_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE53_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE53_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE53_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE53_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE53_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE53_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE53_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE53_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE53_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE53_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE53_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE53_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE53_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE53_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE53_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE53_LOCK1 +// Description : Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE53_LOCK1_ROW _u(0x00000feb) +#define OTP_DATA_PAGE53_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE53_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE53_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE53_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE53_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE53_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE53_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE53_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE53_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE53_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE53_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE53_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE53_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE53_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE53_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE53_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE53_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE54_LOCK0 +// Description : Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE54_LOCK0_ROW _u(0x00000fec) +#define OTP_DATA_PAGE54_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE54_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE54_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE54_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE54_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE54_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE54_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE54_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE54_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE54_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE54_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE54_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE54_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE54_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE54_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE54_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE54_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE54_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE54_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE54_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE54_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE54_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE54_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE54_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE54_LOCK1 +// Description : Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE54_LOCK1_ROW _u(0x00000fed) +#define OTP_DATA_PAGE54_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE54_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE54_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE54_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE54_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE54_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE54_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE54_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE54_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE54_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE54_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE54_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE54_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE54_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE54_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE54_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE54_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE55_LOCK0 +// Description : Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE55_LOCK0_ROW _u(0x00000fee) +#define OTP_DATA_PAGE55_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE55_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE55_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE55_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE55_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE55_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE55_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE55_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE55_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE55_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE55_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE55_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE55_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE55_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE55_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE55_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE55_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE55_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE55_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE55_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE55_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE55_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE55_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE55_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE55_LOCK1 +// Description : Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE55_LOCK1_ROW _u(0x00000fef) +#define OTP_DATA_PAGE55_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE55_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE55_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE55_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE55_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE55_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE55_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE55_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE55_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE55_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE55_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE55_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE55_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE55_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE55_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE55_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE55_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE56_LOCK0 +// Description : Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE56_LOCK0_ROW _u(0x00000ff0) +#define OTP_DATA_PAGE56_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE56_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE56_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE56_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE56_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE56_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE56_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE56_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE56_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE56_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE56_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE56_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE56_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE56_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE56_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE56_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE56_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE56_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE56_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE56_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE56_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE56_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE56_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE56_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE56_LOCK1 +// Description : Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE56_LOCK1_ROW _u(0x00000ff1) +#define OTP_DATA_PAGE56_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE56_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE56_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE56_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE56_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE56_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE56_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE56_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE56_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE56_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE56_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE56_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE56_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE56_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE56_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE56_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE56_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE57_LOCK0 +// Description : Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE57_LOCK0_ROW _u(0x00000ff2) +#define OTP_DATA_PAGE57_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE57_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE57_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE57_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE57_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE57_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE57_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE57_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE57_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE57_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE57_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE57_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE57_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE57_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE57_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE57_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE57_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE57_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE57_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE57_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE57_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE57_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE57_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE57_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE57_LOCK1 +// Description : Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE57_LOCK1_ROW _u(0x00000ff3) +#define OTP_DATA_PAGE57_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE57_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE57_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE57_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE57_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE57_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE57_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE57_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE57_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE57_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE57_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE57_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE57_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE57_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE57_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE57_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE57_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE58_LOCK0 +// Description : Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE58_LOCK0_ROW _u(0x00000ff4) +#define OTP_DATA_PAGE58_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE58_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE58_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE58_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE58_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE58_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE58_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE58_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE58_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE58_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE58_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE58_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE58_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE58_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE58_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE58_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE58_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE58_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE58_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE58_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE58_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE58_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE58_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE58_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE58_LOCK1 +// Description : Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE58_LOCK1_ROW _u(0x00000ff5) +#define OTP_DATA_PAGE58_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE58_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE58_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE58_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE58_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE58_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE58_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE58_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE58_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE58_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE58_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE58_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE58_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE58_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE58_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE58_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE58_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE59_LOCK0 +// Description : Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE59_LOCK0_ROW _u(0x00000ff6) +#define OTP_DATA_PAGE59_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE59_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE59_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE59_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE59_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE59_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE59_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE59_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE59_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE59_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE59_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE59_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE59_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE59_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE59_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE59_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE59_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE59_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE59_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE59_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE59_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE59_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE59_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE59_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE59_LOCK1 +// Description : Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE59_LOCK1_ROW _u(0x00000ff7) +#define OTP_DATA_PAGE59_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE59_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE59_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE59_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE59_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE59_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE59_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE59_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE59_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE59_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE59_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE59_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE59_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE59_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE59_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE59_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE59_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE60_LOCK0 +// Description : Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE60_LOCK0_ROW _u(0x00000ff8) +#define OTP_DATA_PAGE60_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE60_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE60_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE60_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE60_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE60_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE60_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE60_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE60_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE60_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE60_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE60_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE60_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE60_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE60_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE60_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE60_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE60_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE60_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE60_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE60_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE60_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE60_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE60_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE60_LOCK1 +// Description : Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE60_LOCK1_ROW _u(0x00000ff9) +#define OTP_DATA_PAGE60_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE60_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE60_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE60_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE60_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE60_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE60_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE60_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE60_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE60_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE60_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE60_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE60_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE60_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE60_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE60_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE60_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE61_LOCK0 +// Description : Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE61_LOCK0_ROW _u(0x00000ffa) +#define OTP_DATA_PAGE61_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE61_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE61_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE61_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE61_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE61_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE61_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE61_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE61_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE61_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE61_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE61_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE61_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE61_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE61_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE61_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE61_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE61_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE61_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE61_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE61_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE61_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE61_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE61_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE61_LOCK1 +// Description : Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE61_LOCK1_ROW _u(0x00000ffb) +#define OTP_DATA_PAGE61_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE61_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE61_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE61_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE61_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE61_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE61_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE61_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE61_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE61_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE61_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE61_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE61_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE61_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE61_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE61_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE61_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE62_LOCK0 +// Description : Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE62_LOCK0_ROW _u(0x00000ffc) +#define OTP_DATA_PAGE62_LOCK0_BITS _u(0x00ffff7f) +#define OTP_DATA_PAGE62_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE62_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE62_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE62_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE62_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE62_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE62_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE62_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE62_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE62_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE62_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE62_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE62_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE62_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE62_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE62_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE62_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE62_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE62_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE62_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE62_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE62_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE62_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE62_LOCK1 +// Description : Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE62_LOCK1_ROW _u(0x00000ffd) +#define OTP_DATA_PAGE62_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE62_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE62_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE62_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE62_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE62_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE62_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE62_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE62_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE62_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE62_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE62_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE62_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE62_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE62_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE62_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE62_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +// Register : OTP_DATA_PAGE63_LOCK0 +// Description : Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE63_LOCK0_ROW _u(0x00000ffe) +#define OTP_DATA_PAGE63_LOCK0_BITS _u(0x00ffffff) +#define OTP_DATA_PAGE63_LOCK0_RESET _u(0x00000000) +#define OTP_DATA_PAGE63_LOCK0_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK0_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE63_LOCK0_R2_RESET "-" +#define OTP_DATA_PAGE63_LOCK0_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE63_LOCK0_R2_MSB _u(23) +#define OTP_DATA_PAGE63_LOCK0_R2_LSB _u(16) +#define OTP_DATA_PAGE63_LOCK0_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK0_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE63_LOCK0_R1_RESET "-" +#define OTP_DATA_PAGE63_LOCK0_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE63_LOCK0_R1_MSB _u(15) +#define OTP_DATA_PAGE63_LOCK0_R1_LSB _u(8) +#define OTP_DATA_PAGE63_LOCK0_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK0_RMA +// Description : Decommission for RMA of a suspected faulty device. This re- +// enables the factory test JTAG interface, and makes pages 3 +// through 61 of the OTP permanently inaccessible. +#define OTP_DATA_PAGE63_LOCK0_RMA_RESET "-" +#define OTP_DATA_PAGE63_LOCK0_RMA_BITS _u(0x00000080) +#define OTP_DATA_PAGE63_LOCK0_RMA_MSB _u(7) +#define OTP_DATA_PAGE63_LOCK0_RMA_LSB _u(7) +#define OTP_DATA_PAGE63_LOCK0_RMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE +// Description : State when at least one key is registered for this page and no +// matching key has been entered. +// 0x0 -> read_only +// 0x1 -> inaccessible +#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_RESET "-" +#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_BITS _u(0x00000040) +#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_MSB _u(6) +#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_LSB _u(6) +#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_ACCESS "RO" +#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_VALUE_READ_ONLY _u(0x0) +#define OTP_DATA_PAGE63_LOCK0_NO_KEY_STATE_VALUE_INACCESSIBLE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK0_KEY_R +// Description : Index 1-6 of a hardware key which must be entered to grant read +// access, or 0 if no such key is required. +#define OTP_DATA_PAGE63_LOCK0_KEY_R_RESET "-" +#define OTP_DATA_PAGE63_LOCK0_KEY_R_BITS _u(0x00000038) +#define OTP_DATA_PAGE63_LOCK0_KEY_R_MSB _u(5) +#define OTP_DATA_PAGE63_LOCK0_KEY_R_LSB _u(3) +#define OTP_DATA_PAGE63_LOCK0_KEY_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK0_KEY_W +// Description : Index 1-6 of a hardware key which must be entered to grant +// write access, or 0 if no such key is required. +#define OTP_DATA_PAGE63_LOCK0_KEY_W_RESET "-" +#define OTP_DATA_PAGE63_LOCK0_KEY_W_BITS _u(0x00000007) +#define OTP_DATA_PAGE63_LOCK0_KEY_W_MSB _u(2) +#define OTP_DATA_PAGE63_LOCK0_KEY_W_LSB _u(0) +#define OTP_DATA_PAGE63_LOCK0_KEY_W_ACCESS "RO" +// ============================================================================= +// Register : OTP_DATA_PAGE63_LOCK1 +// Description : Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). +// Locks are stored with 3-way majority vote encoding, so that +// bits can be set independently. +// +// This OTP location is always readable, and is write-protected by +// its own permissions. +#define OTP_DATA_PAGE63_LOCK1_ROW _u(0x00000fff) +#define OTP_DATA_PAGE63_LOCK1_BITS _u(0x00ffff3f) +#define OTP_DATA_PAGE63_LOCK1_RESET _u(0x00000000) +#define OTP_DATA_PAGE63_LOCK1_WIDTH _u(24) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK1_R2 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE63_LOCK1_R2_RESET "-" +#define OTP_DATA_PAGE63_LOCK1_R2_BITS _u(0x00ff0000) +#define OTP_DATA_PAGE63_LOCK1_R2_MSB _u(23) +#define OTP_DATA_PAGE63_LOCK1_R2_LSB _u(16) +#define OTP_DATA_PAGE63_LOCK1_R2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK1_R1 +// Description : Redundant copy of bits 7:0 +#define OTP_DATA_PAGE63_LOCK1_R1_RESET "-" +#define OTP_DATA_PAGE63_LOCK1_R1_BITS _u(0x0000ff00) +#define OTP_DATA_PAGE63_LOCK1_R1_MSB _u(15) +#define OTP_DATA_PAGE63_LOCK1_R1_LSB _u(8) +#define OTP_DATA_PAGE63_LOCK1_R1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK1_LOCK_BL +// Description : Dummy lock bits reserved for bootloaders (including the RP2350 +// USB bootloader) to store their own OTP access permissions. No +// hardware effect, and no corresponding SW_LOCKx registers. +// 0x0 -> Bootloader permits user reads and writes to this page +// 0x1 -> Bootloader permits user reads of this page +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE +// 0x3 -> Bootloader does not permit user access to this page +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_RESET "-" +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_BITS _u(0x00000030) +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_MSB _u(5) +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_LSB _u(4) +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_ACCESS "RO" +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE63_LOCK1_LOCK_BL_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK1_LOCK_NS +// Description : Lock state for Non-secure accesses to this page. Thermometer- +// coded, so lock state can be advanced permanently from any state +// to any less-permissive state by programming OTP. Software can +// also advance the lock state temporarily (until next OTP reset) +// using the SW_LOCKx registers. +// +// Note that READ_WRITE and READ_ONLY are equivalent in hardware, +// as the SBPI programming interface is not accessible to Non- +// secure software. However, Secure software may check these bits +// to apply write permissions to a Non-secure OTP programming API. +// 0x0 -> Page can be read by Non-secure software, and Secure software may permit Non-secure writes. +// 0x1 -> Page can be read by Non-secure software +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Non-secure software. +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_RESET "-" +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_BITS _u(0x0000000c) +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_MSB _u(3) +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_LSB _u(2) +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_ACCESS "RO" +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE63_LOCK1_LOCK_NS_VALUE_INACCESSIBLE _u(0x3) +// ----------------------------------------------------------------------------- +// Field : OTP_DATA_PAGE63_LOCK1_LOCK_S +// Description : Lock state for Secure accesses to this page. Thermometer-coded, +// so lock state can be advanced permanently from any state to any +// less-permissive state by programming OTP. Software can also +// advance the lock state temporarily (until next OTP reset) using +// the SW_LOCKx registers. +// 0x0 -> Page is fully accessible by Secure software. +// 0x1 -> Page can be read by Secure software, but can not be written. +// 0x2 -> Do not use. Behaves the same as INACCESSIBLE. +// 0x3 -> Page can not be accessed by Secure software. +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_RESET "-" +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_BITS _u(0x00000003) +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_MSB _u(1) +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_LSB _u(0) +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_ACCESS "RO" +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_VALUE_READ_WRITE _u(0x0) +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_VALUE_READ_ONLY _u(0x1) +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_VALUE_RESERVED _u(0x2) +#define OTP_DATA_PAGE63_LOCK1_LOCK_S_VALUE_INACCESSIBLE _u(0x3) +// ============================================================================= +#endif // _HARDWARE_REGS_OTP_DATA_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/pads_bank0.h b/lib/pico-sdk/rp2350/hardware/regs/pads_bank0.h new file mode 100644 index 000000000000..cf262054f33c --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/pads_bank0.h @@ -0,0 +1,3980 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PADS_BANK0 +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_PADS_BANK0_H +#define _HARDWARE_REGS_PADS_BANK0_H +// ============================================================================= +// Register : PADS_BANK0_VOLTAGE_SELECT +// Description : Voltage select. Per bank control +// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) +// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) +#define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000) +#define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001) +#define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000) +#define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0) +#define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0) +#define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" +#define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) +#define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) +// ============================================================================= +// Register : PADS_BANK0_GPIO0 +#define PADS_BANK0_GPIO0_OFFSET _u(0x00000004) +#define PADS_BANK0_GPIO0_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO0_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO0_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO0_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO0_ISO_MSB _u(8) +#define PADS_BANK0_GPIO0_ISO_LSB _u(8) +#define PADS_BANK0_GPIO0_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO0_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO0_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO0_OD_MSB _u(7) +#define PADS_BANK0_GPIO0_OD_LSB _u(7) +#define PADS_BANK0_GPIO0_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_IE +// Description : Input enable +#define PADS_BANK0_GPIO0_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO0_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO0_IE_MSB _u(6) +#define PADS_BANK0_GPIO0_IE_LSB _u(6) +#define PADS_BANK0_GPIO0_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO0_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO0_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO0_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO0_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO0_PUE_MSB _u(3) +#define PADS_BANK0_GPIO0_PUE_LSB _u(3) +#define PADS_BANK0_GPIO0_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO0_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO0_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO0_PDE_MSB _u(2) +#define PADS_BANK0_GPIO0_PDE_LSB _u(2) +#define PADS_BANK0_GPIO0_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO0_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO0_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO0_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO0_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO0_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO0_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO0_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO0_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO0_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO0_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO0_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO1 +#define PADS_BANK0_GPIO1_OFFSET _u(0x00000008) +#define PADS_BANK0_GPIO1_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO1_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO1_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO1_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO1_ISO_MSB _u(8) +#define PADS_BANK0_GPIO1_ISO_LSB _u(8) +#define PADS_BANK0_GPIO1_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO1_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO1_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO1_OD_MSB _u(7) +#define PADS_BANK0_GPIO1_OD_LSB _u(7) +#define PADS_BANK0_GPIO1_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_IE +// Description : Input enable +#define PADS_BANK0_GPIO1_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO1_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO1_IE_MSB _u(6) +#define PADS_BANK0_GPIO1_IE_LSB _u(6) +#define PADS_BANK0_GPIO1_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO1_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO1_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO1_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO1_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO1_PUE_MSB _u(3) +#define PADS_BANK0_GPIO1_PUE_LSB _u(3) +#define PADS_BANK0_GPIO1_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO1_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO1_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO1_PDE_MSB _u(2) +#define PADS_BANK0_GPIO1_PDE_LSB _u(2) +#define PADS_BANK0_GPIO1_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO1_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO1_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO1_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO1_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO1_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO1_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO1_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO1_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO1_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO1_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO1_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO2 +#define PADS_BANK0_GPIO2_OFFSET _u(0x0000000c) +#define PADS_BANK0_GPIO2_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO2_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO2_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO2_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO2_ISO_MSB _u(8) +#define PADS_BANK0_GPIO2_ISO_LSB _u(8) +#define PADS_BANK0_GPIO2_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO2_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO2_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO2_OD_MSB _u(7) +#define PADS_BANK0_GPIO2_OD_LSB _u(7) +#define PADS_BANK0_GPIO2_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_IE +// Description : Input enable +#define PADS_BANK0_GPIO2_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO2_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO2_IE_MSB _u(6) +#define PADS_BANK0_GPIO2_IE_LSB _u(6) +#define PADS_BANK0_GPIO2_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO2_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO2_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO2_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO2_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO2_PUE_MSB _u(3) +#define PADS_BANK0_GPIO2_PUE_LSB _u(3) +#define PADS_BANK0_GPIO2_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO2_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO2_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO2_PDE_MSB _u(2) +#define PADS_BANK0_GPIO2_PDE_LSB _u(2) +#define PADS_BANK0_GPIO2_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO2_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO2_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO2_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO2_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO2_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO2_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO2_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO2_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO2_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO2_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO2_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO3 +#define PADS_BANK0_GPIO3_OFFSET _u(0x00000010) +#define PADS_BANK0_GPIO3_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO3_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO3_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO3_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO3_ISO_MSB _u(8) +#define PADS_BANK0_GPIO3_ISO_LSB _u(8) +#define PADS_BANK0_GPIO3_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO3_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO3_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO3_OD_MSB _u(7) +#define PADS_BANK0_GPIO3_OD_LSB _u(7) +#define PADS_BANK0_GPIO3_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_IE +// Description : Input enable +#define PADS_BANK0_GPIO3_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO3_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO3_IE_MSB _u(6) +#define PADS_BANK0_GPIO3_IE_LSB _u(6) +#define PADS_BANK0_GPIO3_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO3_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO3_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO3_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO3_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO3_PUE_MSB _u(3) +#define PADS_BANK0_GPIO3_PUE_LSB _u(3) +#define PADS_BANK0_GPIO3_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO3_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO3_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO3_PDE_MSB _u(2) +#define PADS_BANK0_GPIO3_PDE_LSB _u(2) +#define PADS_BANK0_GPIO3_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO3_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO3_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO3_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO3_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO3_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO3_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO3_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO3_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO3_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO3_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO3_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO4 +#define PADS_BANK0_GPIO4_OFFSET _u(0x00000014) +#define PADS_BANK0_GPIO4_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO4_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO4_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO4_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO4_ISO_MSB _u(8) +#define PADS_BANK0_GPIO4_ISO_LSB _u(8) +#define PADS_BANK0_GPIO4_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO4_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO4_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO4_OD_MSB _u(7) +#define PADS_BANK0_GPIO4_OD_LSB _u(7) +#define PADS_BANK0_GPIO4_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_IE +// Description : Input enable +#define PADS_BANK0_GPIO4_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO4_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO4_IE_MSB _u(6) +#define PADS_BANK0_GPIO4_IE_LSB _u(6) +#define PADS_BANK0_GPIO4_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO4_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO4_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO4_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO4_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO4_PUE_MSB _u(3) +#define PADS_BANK0_GPIO4_PUE_LSB _u(3) +#define PADS_BANK0_GPIO4_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO4_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO4_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO4_PDE_MSB _u(2) +#define PADS_BANK0_GPIO4_PDE_LSB _u(2) +#define PADS_BANK0_GPIO4_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO4_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO4_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO4_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO4_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO4_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO4_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO4_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO4_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO4_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO4_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO4_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO5 +#define PADS_BANK0_GPIO5_OFFSET _u(0x00000018) +#define PADS_BANK0_GPIO5_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO5_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO5_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO5_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO5_ISO_MSB _u(8) +#define PADS_BANK0_GPIO5_ISO_LSB _u(8) +#define PADS_BANK0_GPIO5_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO5_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO5_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO5_OD_MSB _u(7) +#define PADS_BANK0_GPIO5_OD_LSB _u(7) +#define PADS_BANK0_GPIO5_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_IE +// Description : Input enable +#define PADS_BANK0_GPIO5_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO5_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO5_IE_MSB _u(6) +#define PADS_BANK0_GPIO5_IE_LSB _u(6) +#define PADS_BANK0_GPIO5_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO5_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO5_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO5_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO5_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO5_PUE_MSB _u(3) +#define PADS_BANK0_GPIO5_PUE_LSB _u(3) +#define PADS_BANK0_GPIO5_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO5_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO5_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO5_PDE_MSB _u(2) +#define PADS_BANK0_GPIO5_PDE_LSB _u(2) +#define PADS_BANK0_GPIO5_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO5_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO5_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO5_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO5_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO5_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO5_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO5_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO5_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO5_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO5_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO5_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO6 +#define PADS_BANK0_GPIO6_OFFSET _u(0x0000001c) +#define PADS_BANK0_GPIO6_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO6_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO6_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO6_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO6_ISO_MSB _u(8) +#define PADS_BANK0_GPIO6_ISO_LSB _u(8) +#define PADS_BANK0_GPIO6_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO6_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO6_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO6_OD_MSB _u(7) +#define PADS_BANK0_GPIO6_OD_LSB _u(7) +#define PADS_BANK0_GPIO6_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_IE +// Description : Input enable +#define PADS_BANK0_GPIO6_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO6_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO6_IE_MSB _u(6) +#define PADS_BANK0_GPIO6_IE_LSB _u(6) +#define PADS_BANK0_GPIO6_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO6_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO6_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO6_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO6_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO6_PUE_MSB _u(3) +#define PADS_BANK0_GPIO6_PUE_LSB _u(3) +#define PADS_BANK0_GPIO6_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO6_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO6_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO6_PDE_MSB _u(2) +#define PADS_BANK0_GPIO6_PDE_LSB _u(2) +#define PADS_BANK0_GPIO6_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO6_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO6_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO6_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO6_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO6_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO6_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO6_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO6_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO6_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO6_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO6_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO7 +#define PADS_BANK0_GPIO7_OFFSET _u(0x00000020) +#define PADS_BANK0_GPIO7_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO7_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO7_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO7_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO7_ISO_MSB _u(8) +#define PADS_BANK0_GPIO7_ISO_LSB _u(8) +#define PADS_BANK0_GPIO7_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO7_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO7_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO7_OD_MSB _u(7) +#define PADS_BANK0_GPIO7_OD_LSB _u(7) +#define PADS_BANK0_GPIO7_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_IE +// Description : Input enable +#define PADS_BANK0_GPIO7_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO7_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO7_IE_MSB _u(6) +#define PADS_BANK0_GPIO7_IE_LSB _u(6) +#define PADS_BANK0_GPIO7_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO7_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO7_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO7_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO7_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO7_PUE_MSB _u(3) +#define PADS_BANK0_GPIO7_PUE_LSB _u(3) +#define PADS_BANK0_GPIO7_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO7_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO7_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO7_PDE_MSB _u(2) +#define PADS_BANK0_GPIO7_PDE_LSB _u(2) +#define PADS_BANK0_GPIO7_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO7_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO7_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO7_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO7_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO7_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO7_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO7_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO7_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO7_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO7_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO7_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO8 +#define PADS_BANK0_GPIO8_OFFSET _u(0x00000024) +#define PADS_BANK0_GPIO8_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO8_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO8_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO8_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO8_ISO_MSB _u(8) +#define PADS_BANK0_GPIO8_ISO_LSB _u(8) +#define PADS_BANK0_GPIO8_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO8_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO8_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO8_OD_MSB _u(7) +#define PADS_BANK0_GPIO8_OD_LSB _u(7) +#define PADS_BANK0_GPIO8_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_IE +// Description : Input enable +#define PADS_BANK0_GPIO8_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO8_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO8_IE_MSB _u(6) +#define PADS_BANK0_GPIO8_IE_LSB _u(6) +#define PADS_BANK0_GPIO8_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO8_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO8_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO8_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO8_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO8_PUE_MSB _u(3) +#define PADS_BANK0_GPIO8_PUE_LSB _u(3) +#define PADS_BANK0_GPIO8_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO8_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO8_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO8_PDE_MSB _u(2) +#define PADS_BANK0_GPIO8_PDE_LSB _u(2) +#define PADS_BANK0_GPIO8_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO8_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO8_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO8_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO8_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO8_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO8_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO8_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO8_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO8_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO8_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO8_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO9 +#define PADS_BANK0_GPIO9_OFFSET _u(0x00000028) +#define PADS_BANK0_GPIO9_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO9_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO9_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO9_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO9_ISO_MSB _u(8) +#define PADS_BANK0_GPIO9_ISO_LSB _u(8) +#define PADS_BANK0_GPIO9_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO9_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO9_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO9_OD_MSB _u(7) +#define PADS_BANK0_GPIO9_OD_LSB _u(7) +#define PADS_BANK0_GPIO9_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_IE +// Description : Input enable +#define PADS_BANK0_GPIO9_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO9_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO9_IE_MSB _u(6) +#define PADS_BANK0_GPIO9_IE_LSB _u(6) +#define PADS_BANK0_GPIO9_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO9_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO9_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO9_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO9_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO9_PUE_MSB _u(3) +#define PADS_BANK0_GPIO9_PUE_LSB _u(3) +#define PADS_BANK0_GPIO9_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO9_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO9_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO9_PDE_MSB _u(2) +#define PADS_BANK0_GPIO9_PDE_LSB _u(2) +#define PADS_BANK0_GPIO9_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO9_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO9_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO9_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO9_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO9_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO9_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO9_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO9_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO9_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO9_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO9_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO10 +#define PADS_BANK0_GPIO10_OFFSET _u(0x0000002c) +#define PADS_BANK0_GPIO10_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO10_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO10_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO10_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO10_ISO_MSB _u(8) +#define PADS_BANK0_GPIO10_ISO_LSB _u(8) +#define PADS_BANK0_GPIO10_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO10_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO10_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO10_OD_MSB _u(7) +#define PADS_BANK0_GPIO10_OD_LSB _u(7) +#define PADS_BANK0_GPIO10_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_IE +// Description : Input enable +#define PADS_BANK0_GPIO10_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO10_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO10_IE_MSB _u(6) +#define PADS_BANK0_GPIO10_IE_LSB _u(6) +#define PADS_BANK0_GPIO10_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO10_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO10_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO10_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO10_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO10_PUE_MSB _u(3) +#define PADS_BANK0_GPIO10_PUE_LSB _u(3) +#define PADS_BANK0_GPIO10_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO10_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO10_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO10_PDE_MSB _u(2) +#define PADS_BANK0_GPIO10_PDE_LSB _u(2) +#define PADS_BANK0_GPIO10_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO10_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO10_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO10_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO10_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO10_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO10_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO10_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO10_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO10_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO10_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO10_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO11 +#define PADS_BANK0_GPIO11_OFFSET _u(0x00000030) +#define PADS_BANK0_GPIO11_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO11_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO11_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO11_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO11_ISO_MSB _u(8) +#define PADS_BANK0_GPIO11_ISO_LSB _u(8) +#define PADS_BANK0_GPIO11_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO11_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO11_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO11_OD_MSB _u(7) +#define PADS_BANK0_GPIO11_OD_LSB _u(7) +#define PADS_BANK0_GPIO11_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_IE +// Description : Input enable +#define PADS_BANK0_GPIO11_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO11_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO11_IE_MSB _u(6) +#define PADS_BANK0_GPIO11_IE_LSB _u(6) +#define PADS_BANK0_GPIO11_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO11_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO11_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO11_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO11_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO11_PUE_MSB _u(3) +#define PADS_BANK0_GPIO11_PUE_LSB _u(3) +#define PADS_BANK0_GPIO11_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO11_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO11_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO11_PDE_MSB _u(2) +#define PADS_BANK0_GPIO11_PDE_LSB _u(2) +#define PADS_BANK0_GPIO11_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO11_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO11_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO11_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO11_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO11_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO11_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO11_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO11_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO11_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO11_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO11_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO12 +#define PADS_BANK0_GPIO12_OFFSET _u(0x00000034) +#define PADS_BANK0_GPIO12_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO12_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO12_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO12_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO12_ISO_MSB _u(8) +#define PADS_BANK0_GPIO12_ISO_LSB _u(8) +#define PADS_BANK0_GPIO12_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO12_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO12_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO12_OD_MSB _u(7) +#define PADS_BANK0_GPIO12_OD_LSB _u(7) +#define PADS_BANK0_GPIO12_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_IE +// Description : Input enable +#define PADS_BANK0_GPIO12_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO12_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO12_IE_MSB _u(6) +#define PADS_BANK0_GPIO12_IE_LSB _u(6) +#define PADS_BANK0_GPIO12_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO12_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO12_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO12_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO12_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO12_PUE_MSB _u(3) +#define PADS_BANK0_GPIO12_PUE_LSB _u(3) +#define PADS_BANK0_GPIO12_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO12_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO12_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO12_PDE_MSB _u(2) +#define PADS_BANK0_GPIO12_PDE_LSB _u(2) +#define PADS_BANK0_GPIO12_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO12_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO12_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO12_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO12_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO12_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO12_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO12_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO12_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO12_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO12_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO12_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO13 +#define PADS_BANK0_GPIO13_OFFSET _u(0x00000038) +#define PADS_BANK0_GPIO13_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO13_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO13_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO13_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO13_ISO_MSB _u(8) +#define PADS_BANK0_GPIO13_ISO_LSB _u(8) +#define PADS_BANK0_GPIO13_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO13_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO13_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO13_OD_MSB _u(7) +#define PADS_BANK0_GPIO13_OD_LSB _u(7) +#define PADS_BANK0_GPIO13_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_IE +// Description : Input enable +#define PADS_BANK0_GPIO13_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO13_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO13_IE_MSB _u(6) +#define PADS_BANK0_GPIO13_IE_LSB _u(6) +#define PADS_BANK0_GPIO13_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO13_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO13_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO13_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO13_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO13_PUE_MSB _u(3) +#define PADS_BANK0_GPIO13_PUE_LSB _u(3) +#define PADS_BANK0_GPIO13_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO13_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO13_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO13_PDE_MSB _u(2) +#define PADS_BANK0_GPIO13_PDE_LSB _u(2) +#define PADS_BANK0_GPIO13_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO13_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO13_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO13_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO13_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO13_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO13_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO13_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO13_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO13_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO13_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO13_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO14 +#define PADS_BANK0_GPIO14_OFFSET _u(0x0000003c) +#define PADS_BANK0_GPIO14_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO14_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO14_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO14_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO14_ISO_MSB _u(8) +#define PADS_BANK0_GPIO14_ISO_LSB _u(8) +#define PADS_BANK0_GPIO14_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO14_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO14_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO14_OD_MSB _u(7) +#define PADS_BANK0_GPIO14_OD_LSB _u(7) +#define PADS_BANK0_GPIO14_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_IE +// Description : Input enable +#define PADS_BANK0_GPIO14_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO14_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO14_IE_MSB _u(6) +#define PADS_BANK0_GPIO14_IE_LSB _u(6) +#define PADS_BANK0_GPIO14_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO14_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO14_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO14_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO14_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO14_PUE_MSB _u(3) +#define PADS_BANK0_GPIO14_PUE_LSB _u(3) +#define PADS_BANK0_GPIO14_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO14_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO14_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO14_PDE_MSB _u(2) +#define PADS_BANK0_GPIO14_PDE_LSB _u(2) +#define PADS_BANK0_GPIO14_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO14_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO14_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO14_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO14_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO14_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO14_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO14_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO14_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO14_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO14_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO14_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO15 +#define PADS_BANK0_GPIO15_OFFSET _u(0x00000040) +#define PADS_BANK0_GPIO15_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO15_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO15_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO15_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO15_ISO_MSB _u(8) +#define PADS_BANK0_GPIO15_ISO_LSB _u(8) +#define PADS_BANK0_GPIO15_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO15_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO15_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO15_OD_MSB _u(7) +#define PADS_BANK0_GPIO15_OD_LSB _u(7) +#define PADS_BANK0_GPIO15_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_IE +// Description : Input enable +#define PADS_BANK0_GPIO15_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO15_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO15_IE_MSB _u(6) +#define PADS_BANK0_GPIO15_IE_LSB _u(6) +#define PADS_BANK0_GPIO15_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO15_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO15_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO15_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO15_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO15_PUE_MSB _u(3) +#define PADS_BANK0_GPIO15_PUE_LSB _u(3) +#define PADS_BANK0_GPIO15_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO15_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO15_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO15_PDE_MSB _u(2) +#define PADS_BANK0_GPIO15_PDE_LSB _u(2) +#define PADS_BANK0_GPIO15_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO15_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO15_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO15_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO15_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO15_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO15_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO15_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO15_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO15_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO15_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO15_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO16 +#define PADS_BANK0_GPIO16_OFFSET _u(0x00000044) +#define PADS_BANK0_GPIO16_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO16_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO16_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO16_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO16_ISO_MSB _u(8) +#define PADS_BANK0_GPIO16_ISO_LSB _u(8) +#define PADS_BANK0_GPIO16_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO16_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO16_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO16_OD_MSB _u(7) +#define PADS_BANK0_GPIO16_OD_LSB _u(7) +#define PADS_BANK0_GPIO16_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_IE +// Description : Input enable +#define PADS_BANK0_GPIO16_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO16_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO16_IE_MSB _u(6) +#define PADS_BANK0_GPIO16_IE_LSB _u(6) +#define PADS_BANK0_GPIO16_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO16_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO16_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO16_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO16_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO16_PUE_MSB _u(3) +#define PADS_BANK0_GPIO16_PUE_LSB _u(3) +#define PADS_BANK0_GPIO16_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO16_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO16_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO16_PDE_MSB _u(2) +#define PADS_BANK0_GPIO16_PDE_LSB _u(2) +#define PADS_BANK0_GPIO16_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO16_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO16_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO16_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO16_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO16_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO16_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO16_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO16_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO16_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO16_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO16_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO17 +#define PADS_BANK0_GPIO17_OFFSET _u(0x00000048) +#define PADS_BANK0_GPIO17_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO17_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO17_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO17_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO17_ISO_MSB _u(8) +#define PADS_BANK0_GPIO17_ISO_LSB _u(8) +#define PADS_BANK0_GPIO17_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO17_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO17_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO17_OD_MSB _u(7) +#define PADS_BANK0_GPIO17_OD_LSB _u(7) +#define PADS_BANK0_GPIO17_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_IE +// Description : Input enable +#define PADS_BANK0_GPIO17_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO17_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO17_IE_MSB _u(6) +#define PADS_BANK0_GPIO17_IE_LSB _u(6) +#define PADS_BANK0_GPIO17_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO17_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO17_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO17_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO17_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO17_PUE_MSB _u(3) +#define PADS_BANK0_GPIO17_PUE_LSB _u(3) +#define PADS_BANK0_GPIO17_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO17_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO17_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO17_PDE_MSB _u(2) +#define PADS_BANK0_GPIO17_PDE_LSB _u(2) +#define PADS_BANK0_GPIO17_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO17_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO17_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO17_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO17_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO17_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO17_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO17_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO17_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO17_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO17_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO17_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO18 +#define PADS_BANK0_GPIO18_OFFSET _u(0x0000004c) +#define PADS_BANK0_GPIO18_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO18_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO18_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO18_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO18_ISO_MSB _u(8) +#define PADS_BANK0_GPIO18_ISO_LSB _u(8) +#define PADS_BANK0_GPIO18_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO18_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO18_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO18_OD_MSB _u(7) +#define PADS_BANK0_GPIO18_OD_LSB _u(7) +#define PADS_BANK0_GPIO18_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_IE +// Description : Input enable +#define PADS_BANK0_GPIO18_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO18_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO18_IE_MSB _u(6) +#define PADS_BANK0_GPIO18_IE_LSB _u(6) +#define PADS_BANK0_GPIO18_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO18_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO18_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO18_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO18_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO18_PUE_MSB _u(3) +#define PADS_BANK0_GPIO18_PUE_LSB _u(3) +#define PADS_BANK0_GPIO18_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO18_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO18_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO18_PDE_MSB _u(2) +#define PADS_BANK0_GPIO18_PDE_LSB _u(2) +#define PADS_BANK0_GPIO18_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO18_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO18_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO18_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO18_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO18_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO18_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO18_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO18_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO18_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO18_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO18_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO19 +#define PADS_BANK0_GPIO19_OFFSET _u(0x00000050) +#define PADS_BANK0_GPIO19_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO19_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO19_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO19_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO19_ISO_MSB _u(8) +#define PADS_BANK0_GPIO19_ISO_LSB _u(8) +#define PADS_BANK0_GPIO19_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO19_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO19_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO19_OD_MSB _u(7) +#define PADS_BANK0_GPIO19_OD_LSB _u(7) +#define PADS_BANK0_GPIO19_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_IE +// Description : Input enable +#define PADS_BANK0_GPIO19_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO19_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO19_IE_MSB _u(6) +#define PADS_BANK0_GPIO19_IE_LSB _u(6) +#define PADS_BANK0_GPIO19_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO19_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO19_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO19_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO19_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO19_PUE_MSB _u(3) +#define PADS_BANK0_GPIO19_PUE_LSB _u(3) +#define PADS_BANK0_GPIO19_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO19_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO19_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO19_PDE_MSB _u(2) +#define PADS_BANK0_GPIO19_PDE_LSB _u(2) +#define PADS_BANK0_GPIO19_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO19_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO19_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO19_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO19_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO19_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO19_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO19_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO19_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO19_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO19_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO19_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO20 +#define PADS_BANK0_GPIO20_OFFSET _u(0x00000054) +#define PADS_BANK0_GPIO20_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO20_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO20_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO20_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO20_ISO_MSB _u(8) +#define PADS_BANK0_GPIO20_ISO_LSB _u(8) +#define PADS_BANK0_GPIO20_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO20_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO20_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO20_OD_MSB _u(7) +#define PADS_BANK0_GPIO20_OD_LSB _u(7) +#define PADS_BANK0_GPIO20_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_IE +// Description : Input enable +#define PADS_BANK0_GPIO20_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO20_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO20_IE_MSB _u(6) +#define PADS_BANK0_GPIO20_IE_LSB _u(6) +#define PADS_BANK0_GPIO20_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO20_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO20_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO20_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO20_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO20_PUE_MSB _u(3) +#define PADS_BANK0_GPIO20_PUE_LSB _u(3) +#define PADS_BANK0_GPIO20_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO20_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO20_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO20_PDE_MSB _u(2) +#define PADS_BANK0_GPIO20_PDE_LSB _u(2) +#define PADS_BANK0_GPIO20_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO20_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO20_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO20_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO20_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO20_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO20_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO20_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO20_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO20_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO20_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO20_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO21 +#define PADS_BANK0_GPIO21_OFFSET _u(0x00000058) +#define PADS_BANK0_GPIO21_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO21_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO21_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO21_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO21_ISO_MSB _u(8) +#define PADS_BANK0_GPIO21_ISO_LSB _u(8) +#define PADS_BANK0_GPIO21_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO21_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO21_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO21_OD_MSB _u(7) +#define PADS_BANK0_GPIO21_OD_LSB _u(7) +#define PADS_BANK0_GPIO21_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_IE +// Description : Input enable +#define PADS_BANK0_GPIO21_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO21_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO21_IE_MSB _u(6) +#define PADS_BANK0_GPIO21_IE_LSB _u(6) +#define PADS_BANK0_GPIO21_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO21_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO21_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO21_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO21_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO21_PUE_MSB _u(3) +#define PADS_BANK0_GPIO21_PUE_LSB _u(3) +#define PADS_BANK0_GPIO21_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO21_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO21_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO21_PDE_MSB _u(2) +#define PADS_BANK0_GPIO21_PDE_LSB _u(2) +#define PADS_BANK0_GPIO21_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO21_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO21_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO21_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO21_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO21_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO21_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO21_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO21_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO21_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO21_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO21_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO22 +#define PADS_BANK0_GPIO22_OFFSET _u(0x0000005c) +#define PADS_BANK0_GPIO22_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO22_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO22_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO22_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO22_ISO_MSB _u(8) +#define PADS_BANK0_GPIO22_ISO_LSB _u(8) +#define PADS_BANK0_GPIO22_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO22_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO22_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO22_OD_MSB _u(7) +#define PADS_BANK0_GPIO22_OD_LSB _u(7) +#define PADS_BANK0_GPIO22_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_IE +// Description : Input enable +#define PADS_BANK0_GPIO22_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO22_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO22_IE_MSB _u(6) +#define PADS_BANK0_GPIO22_IE_LSB _u(6) +#define PADS_BANK0_GPIO22_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO22_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO22_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO22_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO22_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO22_PUE_MSB _u(3) +#define PADS_BANK0_GPIO22_PUE_LSB _u(3) +#define PADS_BANK0_GPIO22_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO22_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO22_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO22_PDE_MSB _u(2) +#define PADS_BANK0_GPIO22_PDE_LSB _u(2) +#define PADS_BANK0_GPIO22_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO22_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO22_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO22_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO22_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO22_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO22_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO22_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO22_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO22_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO22_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO22_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO23 +#define PADS_BANK0_GPIO23_OFFSET _u(0x00000060) +#define PADS_BANK0_GPIO23_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO23_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO23_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO23_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO23_ISO_MSB _u(8) +#define PADS_BANK0_GPIO23_ISO_LSB _u(8) +#define PADS_BANK0_GPIO23_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO23_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO23_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO23_OD_MSB _u(7) +#define PADS_BANK0_GPIO23_OD_LSB _u(7) +#define PADS_BANK0_GPIO23_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_IE +// Description : Input enable +#define PADS_BANK0_GPIO23_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO23_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO23_IE_MSB _u(6) +#define PADS_BANK0_GPIO23_IE_LSB _u(6) +#define PADS_BANK0_GPIO23_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO23_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO23_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO23_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO23_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO23_PUE_MSB _u(3) +#define PADS_BANK0_GPIO23_PUE_LSB _u(3) +#define PADS_BANK0_GPIO23_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO23_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO23_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO23_PDE_MSB _u(2) +#define PADS_BANK0_GPIO23_PDE_LSB _u(2) +#define PADS_BANK0_GPIO23_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO23_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO23_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO23_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO23_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO23_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO23_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO23_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO23_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO23_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO23_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO23_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO24 +#define PADS_BANK0_GPIO24_OFFSET _u(0x00000064) +#define PADS_BANK0_GPIO24_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO24_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO24_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO24_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO24_ISO_MSB _u(8) +#define PADS_BANK0_GPIO24_ISO_LSB _u(8) +#define PADS_BANK0_GPIO24_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO24_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO24_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO24_OD_MSB _u(7) +#define PADS_BANK0_GPIO24_OD_LSB _u(7) +#define PADS_BANK0_GPIO24_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_IE +// Description : Input enable +#define PADS_BANK0_GPIO24_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO24_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO24_IE_MSB _u(6) +#define PADS_BANK0_GPIO24_IE_LSB _u(6) +#define PADS_BANK0_GPIO24_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO24_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO24_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO24_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO24_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO24_PUE_MSB _u(3) +#define PADS_BANK0_GPIO24_PUE_LSB _u(3) +#define PADS_BANK0_GPIO24_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO24_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO24_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO24_PDE_MSB _u(2) +#define PADS_BANK0_GPIO24_PDE_LSB _u(2) +#define PADS_BANK0_GPIO24_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO24_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO24_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO24_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO24_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO24_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO24_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO24_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO24_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO24_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO24_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO24_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO25 +#define PADS_BANK0_GPIO25_OFFSET _u(0x00000068) +#define PADS_BANK0_GPIO25_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO25_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO25_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO25_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO25_ISO_MSB _u(8) +#define PADS_BANK0_GPIO25_ISO_LSB _u(8) +#define PADS_BANK0_GPIO25_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO25_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO25_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO25_OD_MSB _u(7) +#define PADS_BANK0_GPIO25_OD_LSB _u(7) +#define PADS_BANK0_GPIO25_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_IE +// Description : Input enable +#define PADS_BANK0_GPIO25_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO25_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO25_IE_MSB _u(6) +#define PADS_BANK0_GPIO25_IE_LSB _u(6) +#define PADS_BANK0_GPIO25_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO25_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO25_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO25_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO25_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO25_PUE_MSB _u(3) +#define PADS_BANK0_GPIO25_PUE_LSB _u(3) +#define PADS_BANK0_GPIO25_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO25_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO25_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO25_PDE_MSB _u(2) +#define PADS_BANK0_GPIO25_PDE_LSB _u(2) +#define PADS_BANK0_GPIO25_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO25_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO25_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO25_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO25_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO25_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO25_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO25_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO25_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO25_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO25_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO25_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO26 +#define PADS_BANK0_GPIO26_OFFSET _u(0x0000006c) +#define PADS_BANK0_GPIO26_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO26_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO26_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO26_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO26_ISO_MSB _u(8) +#define PADS_BANK0_GPIO26_ISO_LSB _u(8) +#define PADS_BANK0_GPIO26_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO26_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO26_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO26_OD_MSB _u(7) +#define PADS_BANK0_GPIO26_OD_LSB _u(7) +#define PADS_BANK0_GPIO26_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_IE +// Description : Input enable +#define PADS_BANK0_GPIO26_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO26_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO26_IE_MSB _u(6) +#define PADS_BANK0_GPIO26_IE_LSB _u(6) +#define PADS_BANK0_GPIO26_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO26_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO26_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO26_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO26_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO26_PUE_MSB _u(3) +#define PADS_BANK0_GPIO26_PUE_LSB _u(3) +#define PADS_BANK0_GPIO26_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO26_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO26_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO26_PDE_MSB _u(2) +#define PADS_BANK0_GPIO26_PDE_LSB _u(2) +#define PADS_BANK0_GPIO26_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO26_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO26_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO26_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO26_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO26_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO26_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO26_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO26_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO26_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO26_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO26_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO27 +#define PADS_BANK0_GPIO27_OFFSET _u(0x00000070) +#define PADS_BANK0_GPIO27_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO27_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO27_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO27_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO27_ISO_MSB _u(8) +#define PADS_BANK0_GPIO27_ISO_LSB _u(8) +#define PADS_BANK0_GPIO27_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO27_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO27_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO27_OD_MSB _u(7) +#define PADS_BANK0_GPIO27_OD_LSB _u(7) +#define PADS_BANK0_GPIO27_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_IE +// Description : Input enable +#define PADS_BANK0_GPIO27_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO27_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO27_IE_MSB _u(6) +#define PADS_BANK0_GPIO27_IE_LSB _u(6) +#define PADS_BANK0_GPIO27_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO27_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO27_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO27_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO27_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO27_PUE_MSB _u(3) +#define PADS_BANK0_GPIO27_PUE_LSB _u(3) +#define PADS_BANK0_GPIO27_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO27_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO27_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO27_PDE_MSB _u(2) +#define PADS_BANK0_GPIO27_PDE_LSB _u(2) +#define PADS_BANK0_GPIO27_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO27_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO27_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO27_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO27_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO27_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO27_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO27_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO27_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO27_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO27_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO27_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO28 +#define PADS_BANK0_GPIO28_OFFSET _u(0x00000074) +#define PADS_BANK0_GPIO28_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO28_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO28_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO28_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO28_ISO_MSB _u(8) +#define PADS_BANK0_GPIO28_ISO_LSB _u(8) +#define PADS_BANK0_GPIO28_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO28_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO28_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO28_OD_MSB _u(7) +#define PADS_BANK0_GPIO28_OD_LSB _u(7) +#define PADS_BANK0_GPIO28_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_IE +// Description : Input enable +#define PADS_BANK0_GPIO28_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO28_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO28_IE_MSB _u(6) +#define PADS_BANK0_GPIO28_IE_LSB _u(6) +#define PADS_BANK0_GPIO28_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO28_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO28_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO28_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO28_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO28_PUE_MSB _u(3) +#define PADS_BANK0_GPIO28_PUE_LSB _u(3) +#define PADS_BANK0_GPIO28_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO28_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO28_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO28_PDE_MSB _u(2) +#define PADS_BANK0_GPIO28_PDE_LSB _u(2) +#define PADS_BANK0_GPIO28_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO28_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO28_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO28_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO28_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO28_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO28_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO28_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO28_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO28_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO28_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO28_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO29 +#define PADS_BANK0_GPIO29_OFFSET _u(0x00000078) +#define PADS_BANK0_GPIO29_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO29_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO29_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO29_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO29_ISO_MSB _u(8) +#define PADS_BANK0_GPIO29_ISO_LSB _u(8) +#define PADS_BANK0_GPIO29_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO29_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO29_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO29_OD_MSB _u(7) +#define PADS_BANK0_GPIO29_OD_LSB _u(7) +#define PADS_BANK0_GPIO29_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_IE +// Description : Input enable +#define PADS_BANK0_GPIO29_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO29_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO29_IE_MSB _u(6) +#define PADS_BANK0_GPIO29_IE_LSB _u(6) +#define PADS_BANK0_GPIO29_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO29_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO29_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO29_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO29_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO29_PUE_MSB _u(3) +#define PADS_BANK0_GPIO29_PUE_LSB _u(3) +#define PADS_BANK0_GPIO29_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO29_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO29_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO29_PDE_MSB _u(2) +#define PADS_BANK0_GPIO29_PDE_LSB _u(2) +#define PADS_BANK0_GPIO29_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO29_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO29_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO29_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO29_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO29_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO29_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO29_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO29_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO29_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO29_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO29_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO30 +#define PADS_BANK0_GPIO30_OFFSET _u(0x0000007c) +#define PADS_BANK0_GPIO30_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO30_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO30_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO30_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO30_ISO_MSB _u(8) +#define PADS_BANK0_GPIO30_ISO_LSB _u(8) +#define PADS_BANK0_GPIO30_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO30_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO30_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO30_OD_MSB _u(7) +#define PADS_BANK0_GPIO30_OD_LSB _u(7) +#define PADS_BANK0_GPIO30_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_IE +// Description : Input enable +#define PADS_BANK0_GPIO30_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO30_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO30_IE_MSB _u(6) +#define PADS_BANK0_GPIO30_IE_LSB _u(6) +#define PADS_BANK0_GPIO30_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO30_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO30_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO30_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO30_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO30_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO30_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO30_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO30_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO30_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO30_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO30_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO30_PUE_MSB _u(3) +#define PADS_BANK0_GPIO30_PUE_LSB _u(3) +#define PADS_BANK0_GPIO30_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO30_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO30_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO30_PDE_MSB _u(2) +#define PADS_BANK0_GPIO30_PDE_LSB _u(2) +#define PADS_BANK0_GPIO30_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO30_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO30_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO30_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO30_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO30_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO30_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO30_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO30_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO30_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO30_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO30_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO31 +#define PADS_BANK0_GPIO31_OFFSET _u(0x00000080) +#define PADS_BANK0_GPIO31_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO31_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO31_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO31_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO31_ISO_MSB _u(8) +#define PADS_BANK0_GPIO31_ISO_LSB _u(8) +#define PADS_BANK0_GPIO31_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO31_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO31_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO31_OD_MSB _u(7) +#define PADS_BANK0_GPIO31_OD_LSB _u(7) +#define PADS_BANK0_GPIO31_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_IE +// Description : Input enable +#define PADS_BANK0_GPIO31_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO31_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO31_IE_MSB _u(6) +#define PADS_BANK0_GPIO31_IE_LSB _u(6) +#define PADS_BANK0_GPIO31_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO31_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO31_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO31_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO31_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO31_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO31_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO31_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO31_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO31_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO31_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO31_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO31_PUE_MSB _u(3) +#define PADS_BANK0_GPIO31_PUE_LSB _u(3) +#define PADS_BANK0_GPIO31_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO31_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO31_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO31_PDE_MSB _u(2) +#define PADS_BANK0_GPIO31_PDE_LSB _u(2) +#define PADS_BANK0_GPIO31_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO31_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO31_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO31_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO31_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO31_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO31_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO31_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO31_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO31_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO31_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO31_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO32 +#define PADS_BANK0_GPIO32_OFFSET _u(0x00000084) +#define PADS_BANK0_GPIO32_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO32_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO32_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO32_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO32_ISO_MSB _u(8) +#define PADS_BANK0_GPIO32_ISO_LSB _u(8) +#define PADS_BANK0_GPIO32_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO32_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO32_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO32_OD_MSB _u(7) +#define PADS_BANK0_GPIO32_OD_LSB _u(7) +#define PADS_BANK0_GPIO32_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_IE +// Description : Input enable +#define PADS_BANK0_GPIO32_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO32_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO32_IE_MSB _u(6) +#define PADS_BANK0_GPIO32_IE_LSB _u(6) +#define PADS_BANK0_GPIO32_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO32_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO32_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO32_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO32_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO32_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO32_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO32_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO32_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO32_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO32_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO32_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO32_PUE_MSB _u(3) +#define PADS_BANK0_GPIO32_PUE_LSB _u(3) +#define PADS_BANK0_GPIO32_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO32_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO32_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO32_PDE_MSB _u(2) +#define PADS_BANK0_GPIO32_PDE_LSB _u(2) +#define PADS_BANK0_GPIO32_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO32_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO32_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO32_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO32_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO32_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO32_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO32_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO32_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO32_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO32_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO32_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO33 +#define PADS_BANK0_GPIO33_OFFSET _u(0x00000088) +#define PADS_BANK0_GPIO33_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO33_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO33_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO33_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO33_ISO_MSB _u(8) +#define PADS_BANK0_GPIO33_ISO_LSB _u(8) +#define PADS_BANK0_GPIO33_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO33_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO33_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO33_OD_MSB _u(7) +#define PADS_BANK0_GPIO33_OD_LSB _u(7) +#define PADS_BANK0_GPIO33_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_IE +// Description : Input enable +#define PADS_BANK0_GPIO33_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO33_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO33_IE_MSB _u(6) +#define PADS_BANK0_GPIO33_IE_LSB _u(6) +#define PADS_BANK0_GPIO33_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO33_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO33_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO33_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO33_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO33_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO33_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO33_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO33_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO33_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO33_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO33_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO33_PUE_MSB _u(3) +#define PADS_BANK0_GPIO33_PUE_LSB _u(3) +#define PADS_BANK0_GPIO33_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO33_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO33_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO33_PDE_MSB _u(2) +#define PADS_BANK0_GPIO33_PDE_LSB _u(2) +#define PADS_BANK0_GPIO33_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO33_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO33_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO33_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO33_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO33_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO33_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO33_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO33_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO33_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO33_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO33_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO34 +#define PADS_BANK0_GPIO34_OFFSET _u(0x0000008c) +#define PADS_BANK0_GPIO34_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO34_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO34_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO34_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO34_ISO_MSB _u(8) +#define PADS_BANK0_GPIO34_ISO_LSB _u(8) +#define PADS_BANK0_GPIO34_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO34_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO34_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO34_OD_MSB _u(7) +#define PADS_BANK0_GPIO34_OD_LSB _u(7) +#define PADS_BANK0_GPIO34_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_IE +// Description : Input enable +#define PADS_BANK0_GPIO34_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO34_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO34_IE_MSB _u(6) +#define PADS_BANK0_GPIO34_IE_LSB _u(6) +#define PADS_BANK0_GPIO34_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO34_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO34_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO34_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO34_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO34_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO34_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO34_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO34_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO34_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO34_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO34_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO34_PUE_MSB _u(3) +#define PADS_BANK0_GPIO34_PUE_LSB _u(3) +#define PADS_BANK0_GPIO34_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO34_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO34_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO34_PDE_MSB _u(2) +#define PADS_BANK0_GPIO34_PDE_LSB _u(2) +#define PADS_BANK0_GPIO34_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO34_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO34_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO34_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO34_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO34_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO34_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO34_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO34_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO34_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO34_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO34_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO35 +#define PADS_BANK0_GPIO35_OFFSET _u(0x00000090) +#define PADS_BANK0_GPIO35_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO35_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO35_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO35_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO35_ISO_MSB _u(8) +#define PADS_BANK0_GPIO35_ISO_LSB _u(8) +#define PADS_BANK0_GPIO35_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO35_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO35_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO35_OD_MSB _u(7) +#define PADS_BANK0_GPIO35_OD_LSB _u(7) +#define PADS_BANK0_GPIO35_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_IE +// Description : Input enable +#define PADS_BANK0_GPIO35_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO35_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO35_IE_MSB _u(6) +#define PADS_BANK0_GPIO35_IE_LSB _u(6) +#define PADS_BANK0_GPIO35_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO35_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO35_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO35_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO35_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO35_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO35_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO35_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO35_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO35_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO35_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO35_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO35_PUE_MSB _u(3) +#define PADS_BANK0_GPIO35_PUE_LSB _u(3) +#define PADS_BANK0_GPIO35_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO35_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO35_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO35_PDE_MSB _u(2) +#define PADS_BANK0_GPIO35_PDE_LSB _u(2) +#define PADS_BANK0_GPIO35_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO35_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO35_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO35_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO35_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO35_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO35_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO35_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO35_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO35_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO35_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO35_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO36 +#define PADS_BANK0_GPIO36_OFFSET _u(0x00000094) +#define PADS_BANK0_GPIO36_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO36_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO36_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO36_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO36_ISO_MSB _u(8) +#define PADS_BANK0_GPIO36_ISO_LSB _u(8) +#define PADS_BANK0_GPIO36_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO36_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO36_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO36_OD_MSB _u(7) +#define PADS_BANK0_GPIO36_OD_LSB _u(7) +#define PADS_BANK0_GPIO36_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_IE +// Description : Input enable +#define PADS_BANK0_GPIO36_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO36_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO36_IE_MSB _u(6) +#define PADS_BANK0_GPIO36_IE_LSB _u(6) +#define PADS_BANK0_GPIO36_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO36_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO36_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO36_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO36_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO36_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO36_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO36_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO36_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO36_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO36_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO36_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO36_PUE_MSB _u(3) +#define PADS_BANK0_GPIO36_PUE_LSB _u(3) +#define PADS_BANK0_GPIO36_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO36_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO36_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO36_PDE_MSB _u(2) +#define PADS_BANK0_GPIO36_PDE_LSB _u(2) +#define PADS_BANK0_GPIO36_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO36_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO36_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO36_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO36_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO36_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO36_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO36_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO36_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO36_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO36_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO36_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO37 +#define PADS_BANK0_GPIO37_OFFSET _u(0x00000098) +#define PADS_BANK0_GPIO37_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO37_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO37_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO37_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO37_ISO_MSB _u(8) +#define PADS_BANK0_GPIO37_ISO_LSB _u(8) +#define PADS_BANK0_GPIO37_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO37_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO37_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO37_OD_MSB _u(7) +#define PADS_BANK0_GPIO37_OD_LSB _u(7) +#define PADS_BANK0_GPIO37_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_IE +// Description : Input enable +#define PADS_BANK0_GPIO37_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO37_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO37_IE_MSB _u(6) +#define PADS_BANK0_GPIO37_IE_LSB _u(6) +#define PADS_BANK0_GPIO37_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO37_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO37_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO37_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO37_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO37_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO37_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO37_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO37_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO37_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO37_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO37_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO37_PUE_MSB _u(3) +#define PADS_BANK0_GPIO37_PUE_LSB _u(3) +#define PADS_BANK0_GPIO37_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO37_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO37_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO37_PDE_MSB _u(2) +#define PADS_BANK0_GPIO37_PDE_LSB _u(2) +#define PADS_BANK0_GPIO37_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO37_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO37_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO37_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO37_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO37_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO37_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO37_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO37_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO37_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO37_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO37_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO38 +#define PADS_BANK0_GPIO38_OFFSET _u(0x0000009c) +#define PADS_BANK0_GPIO38_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO38_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO38_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO38_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO38_ISO_MSB _u(8) +#define PADS_BANK0_GPIO38_ISO_LSB _u(8) +#define PADS_BANK0_GPIO38_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO38_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO38_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO38_OD_MSB _u(7) +#define PADS_BANK0_GPIO38_OD_LSB _u(7) +#define PADS_BANK0_GPIO38_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_IE +// Description : Input enable +#define PADS_BANK0_GPIO38_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO38_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO38_IE_MSB _u(6) +#define PADS_BANK0_GPIO38_IE_LSB _u(6) +#define PADS_BANK0_GPIO38_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO38_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO38_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO38_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO38_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO38_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO38_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO38_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO38_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO38_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO38_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO38_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO38_PUE_MSB _u(3) +#define PADS_BANK0_GPIO38_PUE_LSB _u(3) +#define PADS_BANK0_GPIO38_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO38_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO38_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO38_PDE_MSB _u(2) +#define PADS_BANK0_GPIO38_PDE_LSB _u(2) +#define PADS_BANK0_GPIO38_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO38_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO38_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO38_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO38_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO38_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO38_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO38_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO38_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO38_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO38_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO38_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO39 +#define PADS_BANK0_GPIO39_OFFSET _u(0x000000a0) +#define PADS_BANK0_GPIO39_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO39_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO39_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO39_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO39_ISO_MSB _u(8) +#define PADS_BANK0_GPIO39_ISO_LSB _u(8) +#define PADS_BANK0_GPIO39_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO39_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO39_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO39_OD_MSB _u(7) +#define PADS_BANK0_GPIO39_OD_LSB _u(7) +#define PADS_BANK0_GPIO39_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_IE +// Description : Input enable +#define PADS_BANK0_GPIO39_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO39_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO39_IE_MSB _u(6) +#define PADS_BANK0_GPIO39_IE_LSB _u(6) +#define PADS_BANK0_GPIO39_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO39_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO39_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO39_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO39_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO39_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO39_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO39_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO39_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO39_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO39_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO39_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO39_PUE_MSB _u(3) +#define PADS_BANK0_GPIO39_PUE_LSB _u(3) +#define PADS_BANK0_GPIO39_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO39_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO39_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO39_PDE_MSB _u(2) +#define PADS_BANK0_GPIO39_PDE_LSB _u(2) +#define PADS_BANK0_GPIO39_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO39_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO39_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO39_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO39_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO39_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO39_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO39_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO39_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO39_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO39_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO39_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO40 +#define PADS_BANK0_GPIO40_OFFSET _u(0x000000a4) +#define PADS_BANK0_GPIO40_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO40_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO40_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO40_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO40_ISO_MSB _u(8) +#define PADS_BANK0_GPIO40_ISO_LSB _u(8) +#define PADS_BANK0_GPIO40_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO40_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO40_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO40_OD_MSB _u(7) +#define PADS_BANK0_GPIO40_OD_LSB _u(7) +#define PADS_BANK0_GPIO40_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_IE +// Description : Input enable +#define PADS_BANK0_GPIO40_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO40_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO40_IE_MSB _u(6) +#define PADS_BANK0_GPIO40_IE_LSB _u(6) +#define PADS_BANK0_GPIO40_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO40_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO40_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO40_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO40_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO40_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO40_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO40_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO40_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO40_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO40_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO40_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO40_PUE_MSB _u(3) +#define PADS_BANK0_GPIO40_PUE_LSB _u(3) +#define PADS_BANK0_GPIO40_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO40_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO40_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO40_PDE_MSB _u(2) +#define PADS_BANK0_GPIO40_PDE_LSB _u(2) +#define PADS_BANK0_GPIO40_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO40_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO40_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO40_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO40_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO40_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO40_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO40_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO40_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO40_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO40_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO40_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO41 +#define PADS_BANK0_GPIO41_OFFSET _u(0x000000a8) +#define PADS_BANK0_GPIO41_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO41_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO41_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO41_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO41_ISO_MSB _u(8) +#define PADS_BANK0_GPIO41_ISO_LSB _u(8) +#define PADS_BANK0_GPIO41_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO41_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO41_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO41_OD_MSB _u(7) +#define PADS_BANK0_GPIO41_OD_LSB _u(7) +#define PADS_BANK0_GPIO41_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_IE +// Description : Input enable +#define PADS_BANK0_GPIO41_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO41_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO41_IE_MSB _u(6) +#define PADS_BANK0_GPIO41_IE_LSB _u(6) +#define PADS_BANK0_GPIO41_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO41_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO41_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO41_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO41_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO41_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO41_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO41_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO41_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO41_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO41_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO41_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO41_PUE_MSB _u(3) +#define PADS_BANK0_GPIO41_PUE_LSB _u(3) +#define PADS_BANK0_GPIO41_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO41_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO41_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO41_PDE_MSB _u(2) +#define PADS_BANK0_GPIO41_PDE_LSB _u(2) +#define PADS_BANK0_GPIO41_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO41_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO41_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO41_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO41_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO41_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO41_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO41_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO41_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO41_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO41_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO41_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO42 +#define PADS_BANK0_GPIO42_OFFSET _u(0x000000ac) +#define PADS_BANK0_GPIO42_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO42_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO42_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO42_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO42_ISO_MSB _u(8) +#define PADS_BANK0_GPIO42_ISO_LSB _u(8) +#define PADS_BANK0_GPIO42_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO42_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO42_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO42_OD_MSB _u(7) +#define PADS_BANK0_GPIO42_OD_LSB _u(7) +#define PADS_BANK0_GPIO42_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_IE +// Description : Input enable +#define PADS_BANK0_GPIO42_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO42_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO42_IE_MSB _u(6) +#define PADS_BANK0_GPIO42_IE_LSB _u(6) +#define PADS_BANK0_GPIO42_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO42_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO42_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO42_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO42_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO42_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO42_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO42_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO42_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO42_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO42_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO42_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO42_PUE_MSB _u(3) +#define PADS_BANK0_GPIO42_PUE_LSB _u(3) +#define PADS_BANK0_GPIO42_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO42_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO42_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO42_PDE_MSB _u(2) +#define PADS_BANK0_GPIO42_PDE_LSB _u(2) +#define PADS_BANK0_GPIO42_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO42_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO42_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO42_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO42_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO42_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO42_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO42_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO42_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO42_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO42_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO42_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO43 +#define PADS_BANK0_GPIO43_OFFSET _u(0x000000b0) +#define PADS_BANK0_GPIO43_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO43_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO43_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO43_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO43_ISO_MSB _u(8) +#define PADS_BANK0_GPIO43_ISO_LSB _u(8) +#define PADS_BANK0_GPIO43_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO43_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO43_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO43_OD_MSB _u(7) +#define PADS_BANK0_GPIO43_OD_LSB _u(7) +#define PADS_BANK0_GPIO43_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_IE +// Description : Input enable +#define PADS_BANK0_GPIO43_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO43_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO43_IE_MSB _u(6) +#define PADS_BANK0_GPIO43_IE_LSB _u(6) +#define PADS_BANK0_GPIO43_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO43_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO43_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO43_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO43_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO43_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO43_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO43_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO43_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO43_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO43_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO43_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO43_PUE_MSB _u(3) +#define PADS_BANK0_GPIO43_PUE_LSB _u(3) +#define PADS_BANK0_GPIO43_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO43_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO43_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO43_PDE_MSB _u(2) +#define PADS_BANK0_GPIO43_PDE_LSB _u(2) +#define PADS_BANK0_GPIO43_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO43_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO43_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO43_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO43_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO43_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO43_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO43_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO43_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO43_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO43_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO43_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO44 +#define PADS_BANK0_GPIO44_OFFSET _u(0x000000b4) +#define PADS_BANK0_GPIO44_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO44_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO44_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO44_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO44_ISO_MSB _u(8) +#define PADS_BANK0_GPIO44_ISO_LSB _u(8) +#define PADS_BANK0_GPIO44_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO44_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO44_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO44_OD_MSB _u(7) +#define PADS_BANK0_GPIO44_OD_LSB _u(7) +#define PADS_BANK0_GPIO44_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_IE +// Description : Input enable +#define PADS_BANK0_GPIO44_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO44_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO44_IE_MSB _u(6) +#define PADS_BANK0_GPIO44_IE_LSB _u(6) +#define PADS_BANK0_GPIO44_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO44_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO44_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO44_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO44_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO44_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO44_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO44_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO44_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO44_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO44_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO44_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO44_PUE_MSB _u(3) +#define PADS_BANK0_GPIO44_PUE_LSB _u(3) +#define PADS_BANK0_GPIO44_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO44_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO44_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO44_PDE_MSB _u(2) +#define PADS_BANK0_GPIO44_PDE_LSB _u(2) +#define PADS_BANK0_GPIO44_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO44_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO44_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO44_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO44_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO44_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO44_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO44_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO44_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO44_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO44_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO44_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO45 +#define PADS_BANK0_GPIO45_OFFSET _u(0x000000b8) +#define PADS_BANK0_GPIO45_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO45_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO45_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO45_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO45_ISO_MSB _u(8) +#define PADS_BANK0_GPIO45_ISO_LSB _u(8) +#define PADS_BANK0_GPIO45_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO45_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO45_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO45_OD_MSB _u(7) +#define PADS_BANK0_GPIO45_OD_LSB _u(7) +#define PADS_BANK0_GPIO45_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_IE +// Description : Input enable +#define PADS_BANK0_GPIO45_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO45_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO45_IE_MSB _u(6) +#define PADS_BANK0_GPIO45_IE_LSB _u(6) +#define PADS_BANK0_GPIO45_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO45_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO45_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO45_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO45_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO45_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO45_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO45_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO45_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO45_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO45_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO45_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO45_PUE_MSB _u(3) +#define PADS_BANK0_GPIO45_PUE_LSB _u(3) +#define PADS_BANK0_GPIO45_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO45_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO45_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO45_PDE_MSB _u(2) +#define PADS_BANK0_GPIO45_PDE_LSB _u(2) +#define PADS_BANK0_GPIO45_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO45_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO45_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO45_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO45_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO45_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO45_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO45_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO45_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO45_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO45_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO45_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO46 +#define PADS_BANK0_GPIO46_OFFSET _u(0x000000bc) +#define PADS_BANK0_GPIO46_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO46_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO46_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO46_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO46_ISO_MSB _u(8) +#define PADS_BANK0_GPIO46_ISO_LSB _u(8) +#define PADS_BANK0_GPIO46_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO46_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO46_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO46_OD_MSB _u(7) +#define PADS_BANK0_GPIO46_OD_LSB _u(7) +#define PADS_BANK0_GPIO46_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_IE +// Description : Input enable +#define PADS_BANK0_GPIO46_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO46_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO46_IE_MSB _u(6) +#define PADS_BANK0_GPIO46_IE_LSB _u(6) +#define PADS_BANK0_GPIO46_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO46_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO46_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO46_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO46_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO46_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO46_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO46_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO46_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO46_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO46_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO46_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO46_PUE_MSB _u(3) +#define PADS_BANK0_GPIO46_PUE_LSB _u(3) +#define PADS_BANK0_GPIO46_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO46_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO46_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO46_PDE_MSB _u(2) +#define PADS_BANK0_GPIO46_PDE_LSB _u(2) +#define PADS_BANK0_GPIO46_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO46_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO46_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO46_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO46_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO46_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO46_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO46_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO46_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO46_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO46_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO46_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_GPIO47 +#define PADS_BANK0_GPIO47_OFFSET _u(0x000000c0) +#define PADS_BANK0_GPIO47_BITS _u(0x000001ff) +#define PADS_BANK0_GPIO47_RESET _u(0x00000116) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_GPIO47_ISO_RESET _u(0x1) +#define PADS_BANK0_GPIO47_ISO_BITS _u(0x00000100) +#define PADS_BANK0_GPIO47_ISO_MSB _u(8) +#define PADS_BANK0_GPIO47_ISO_LSB _u(8) +#define PADS_BANK0_GPIO47_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_GPIO47_OD_RESET _u(0x0) +#define PADS_BANK0_GPIO47_OD_BITS _u(0x00000080) +#define PADS_BANK0_GPIO47_OD_MSB _u(7) +#define PADS_BANK0_GPIO47_OD_LSB _u(7) +#define PADS_BANK0_GPIO47_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_IE +// Description : Input enable +#define PADS_BANK0_GPIO47_IE_RESET _u(0x0) +#define PADS_BANK0_GPIO47_IE_BITS _u(0x00000040) +#define PADS_BANK0_GPIO47_IE_MSB _u(6) +#define PADS_BANK0_GPIO47_IE_LSB _u(6) +#define PADS_BANK0_GPIO47_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_GPIO47_DRIVE_RESET _u(0x1) +#define PADS_BANK0_GPIO47_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_GPIO47_DRIVE_MSB _u(5) +#define PADS_BANK0_GPIO47_DRIVE_LSB _u(4) +#define PADS_BANK0_GPIO47_DRIVE_ACCESS "RW" +#define PADS_BANK0_GPIO47_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_GPIO47_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_GPIO47_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_GPIO47_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_PUE +// Description : Pull up enable +#define PADS_BANK0_GPIO47_PUE_RESET _u(0x0) +#define PADS_BANK0_GPIO47_PUE_BITS _u(0x00000008) +#define PADS_BANK0_GPIO47_PUE_MSB _u(3) +#define PADS_BANK0_GPIO47_PUE_LSB _u(3) +#define PADS_BANK0_GPIO47_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_PDE +// Description : Pull down enable +#define PADS_BANK0_GPIO47_PDE_RESET _u(0x1) +#define PADS_BANK0_GPIO47_PDE_BITS _u(0x00000004) +#define PADS_BANK0_GPIO47_PDE_MSB _u(2) +#define PADS_BANK0_GPIO47_PDE_LSB _u(2) +#define PADS_BANK0_GPIO47_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_GPIO47_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_GPIO47_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_GPIO47_SCHMITT_MSB _u(1) +#define PADS_BANK0_GPIO47_SCHMITT_LSB _u(1) +#define PADS_BANK0_GPIO47_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_GPIO47_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_GPIO47_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_GPIO47_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_GPIO47_SLEWFAST_MSB _u(0) +#define PADS_BANK0_GPIO47_SLEWFAST_LSB _u(0) +#define PADS_BANK0_GPIO47_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_SWCLK +#define PADS_BANK0_SWCLK_OFFSET _u(0x000000c4) +#define PADS_BANK0_SWCLK_BITS _u(0x000001ff) +#define PADS_BANK0_SWCLK_RESET _u(0x0000005a) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_SWCLK_ISO_RESET _u(0x0) +#define PADS_BANK0_SWCLK_ISO_BITS _u(0x00000100) +#define PADS_BANK0_SWCLK_ISO_MSB _u(8) +#define PADS_BANK0_SWCLK_ISO_LSB _u(8) +#define PADS_BANK0_SWCLK_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_SWCLK_OD_RESET _u(0x0) +#define PADS_BANK0_SWCLK_OD_BITS _u(0x00000080) +#define PADS_BANK0_SWCLK_OD_MSB _u(7) +#define PADS_BANK0_SWCLK_OD_LSB _u(7) +#define PADS_BANK0_SWCLK_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_IE +// Description : Input enable +#define PADS_BANK0_SWCLK_IE_RESET _u(0x1) +#define PADS_BANK0_SWCLK_IE_BITS _u(0x00000040) +#define PADS_BANK0_SWCLK_IE_MSB _u(6) +#define PADS_BANK0_SWCLK_IE_LSB _u(6) +#define PADS_BANK0_SWCLK_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1) +#define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_SWCLK_DRIVE_MSB _u(5) +#define PADS_BANK0_SWCLK_DRIVE_LSB _u(4) +#define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" +#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_PUE +// Description : Pull up enable +#define PADS_BANK0_SWCLK_PUE_RESET _u(0x1) +#define PADS_BANK0_SWCLK_PUE_BITS _u(0x00000008) +#define PADS_BANK0_SWCLK_PUE_MSB _u(3) +#define PADS_BANK0_SWCLK_PUE_LSB _u(3) +#define PADS_BANK0_SWCLK_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_PDE +// Description : Pull down enable +#define PADS_BANK0_SWCLK_PDE_RESET _u(0x0) +#define PADS_BANK0_SWCLK_PDE_BITS _u(0x00000004) +#define PADS_BANK0_SWCLK_PDE_MSB _u(2) +#define PADS_BANK0_SWCLK_PDE_LSB _u(2) +#define PADS_BANK0_SWCLK_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_SWCLK_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_SWCLK_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_SWCLK_SCHMITT_MSB _u(1) +#define PADS_BANK0_SWCLK_SCHMITT_LSB _u(1) +#define PADS_BANK0_SWCLK_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWCLK_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_SWCLK_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_SWCLK_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_SWCLK_SLEWFAST_MSB _u(0) +#define PADS_BANK0_SWCLK_SLEWFAST_LSB _u(0) +#define PADS_BANK0_SWCLK_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_BANK0_SWD +#define PADS_BANK0_SWD_OFFSET _u(0x000000c8) +#define PADS_BANK0_SWD_BITS _u(0x000001ff) +#define PADS_BANK0_SWD_RESET _u(0x0000005a) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_BANK0_SWD_ISO_RESET _u(0x0) +#define PADS_BANK0_SWD_ISO_BITS _u(0x00000100) +#define PADS_BANK0_SWD_ISO_MSB _u(8) +#define PADS_BANK0_SWD_ISO_LSB _u(8) +#define PADS_BANK0_SWD_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_BANK0_SWD_OD_RESET _u(0x0) +#define PADS_BANK0_SWD_OD_BITS _u(0x00000080) +#define PADS_BANK0_SWD_OD_MSB _u(7) +#define PADS_BANK0_SWD_OD_LSB _u(7) +#define PADS_BANK0_SWD_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_IE +// Description : Input enable +#define PADS_BANK0_SWD_IE_RESET _u(0x1) +#define PADS_BANK0_SWD_IE_BITS _u(0x00000040) +#define PADS_BANK0_SWD_IE_MSB _u(6) +#define PADS_BANK0_SWD_IE_LSB _u(6) +#define PADS_BANK0_SWD_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_BANK0_SWD_DRIVE_RESET _u(0x1) +#define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030) +#define PADS_BANK0_SWD_DRIVE_MSB _u(5) +#define PADS_BANK0_SWD_DRIVE_LSB _u(4) +#define PADS_BANK0_SWD_DRIVE_ACCESS "RW" +#define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0) +#define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1) +#define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2) +#define PADS_BANK0_SWD_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_PUE +// Description : Pull up enable +#define PADS_BANK0_SWD_PUE_RESET _u(0x1) +#define PADS_BANK0_SWD_PUE_BITS _u(0x00000008) +#define PADS_BANK0_SWD_PUE_MSB _u(3) +#define PADS_BANK0_SWD_PUE_LSB _u(3) +#define PADS_BANK0_SWD_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_PDE +// Description : Pull down enable +#define PADS_BANK0_SWD_PDE_RESET _u(0x0) +#define PADS_BANK0_SWD_PDE_BITS _u(0x00000004) +#define PADS_BANK0_SWD_PDE_MSB _u(2) +#define PADS_BANK0_SWD_PDE_LSB _u(2) +#define PADS_BANK0_SWD_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_SCHMITT +// Description : Enable schmitt trigger +#define PADS_BANK0_SWD_SCHMITT_RESET _u(0x1) +#define PADS_BANK0_SWD_SCHMITT_BITS _u(0x00000002) +#define PADS_BANK0_SWD_SCHMITT_MSB _u(1) +#define PADS_BANK0_SWD_SCHMITT_LSB _u(1) +#define PADS_BANK0_SWD_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_BANK0_SWD_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_BANK0_SWD_SLEWFAST_RESET _u(0x0) +#define PADS_BANK0_SWD_SLEWFAST_BITS _u(0x00000001) +#define PADS_BANK0_SWD_SLEWFAST_MSB _u(0) +#define PADS_BANK0_SWD_SLEWFAST_LSB _u(0) +#define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_PADS_BANK0_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/pads_qspi.h b/lib/pico-sdk/rp2350/hardware/regs/pads_qspi.h new file mode 100644 index 000000000000..5e31fd042185 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/pads_qspi.h @@ -0,0 +1,504 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PADS_QSPI +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_PADS_QSPI_H +#define _HARDWARE_REGS_PADS_QSPI_H +// ============================================================================= +// Register : PADS_QSPI_VOLTAGE_SELECT +// Description : Voltage select. Per bank control +// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) +// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) +#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000) +#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001) +#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000) +#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0) +#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0) +#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW" +#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) +#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SCLK +#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000001ff) +#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000156) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_BITS _u(0x00000100) +#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_MSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_LSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD0 +#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000001ff) +#define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000156) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_QSPI_GPIO_QSPI_SD0_ISO_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_ISO_BITS _u(0x00000100) +#define PADS_QSPI_GPIO_QSPI_SD0_ISO_MSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD0_ISO_LSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD0_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD1 +#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c) +#define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000001ff) +#define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000156) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_QSPI_GPIO_QSPI_SD1_ISO_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_ISO_BITS _u(0x00000100) +#define PADS_QSPI_GPIO_QSPI_SD1_ISO_MSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD1_ISO_LSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD1_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD2 +#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010) +#define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000001ff) +#define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x0000015a) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_QSPI_GPIO_QSPI_SD2_ISO_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_ISO_BITS _u(0x00000100) +#define PADS_QSPI_GPIO_QSPI_SD2_ISO_MSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD2_ISO_LSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD2_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SD3 +#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014) +#define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000001ff) +#define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x0000015a) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_QSPI_GPIO_QSPI_SD3_ISO_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_ISO_BITS _u(0x00000100) +#define PADS_QSPI_GPIO_QSPI_SD3_ISO_MSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD3_ISO_LSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SD3_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW" +// ============================================================================= +// Register : PADS_QSPI_GPIO_QSPI_SS +#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018) +#define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000001ff) +#define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000015a) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_ISO +// Description : Pad isolation control. Remove this once the pad is configured +// by software. +#define PADS_QSPI_GPIO_QSPI_SS_ISO_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_ISO_BITS _u(0x00000100) +#define PADS_QSPI_GPIO_QSPI_SS_ISO_MSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SS_ISO_LSB _u(8) +#define PADS_QSPI_GPIO_QSPI_SS_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_OD +// Description : Output disable. Has priority over output enable from +// peripherals +#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080) +#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7) +#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_IE +// Description : Input enable +#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040) +#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6) +#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE +// Description : Drive strength. +// 0x0 -> 2mA +// 0x1 -> 4mA +// 0x2 -> 8mA +// 0x3 -> 12mA +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW" +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2) +#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_PUE +// Description : Pull up enable +#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008) +#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3) +#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_PDE +// Description : Pull down enable +#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004) +#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2) +#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT +// Description : Enable schmitt trigger +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1) +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002) +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1) +#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST +// Description : Slew rate control. 1 = Fast, 0 = Slow +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0) +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001) +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0) +#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_PADS_QSPI_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/pio.h b/lib/pico-sdk/rp2350/hardware/regs/pio.h new file mode 100644 index 000000000000..4a18b5c6fd73 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/pio.h @@ -0,0 +1,3417 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PIO +// Version : 1 +// Bus type : ahbl +// Description : Programmable IO block +// ============================================================================= +#ifndef _HARDWARE_REGS_PIO_H +#define _HARDWARE_REGS_PIO_H +// ============================================================================= +// Register : PIO_CTRL +// Description : PIO control register +#define PIO_CTRL_OFFSET _u(0x00000000) +#define PIO_CTRL_BITS _u(0x07ff0fff) +#define PIO_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_NEXTPREV_CLKDIV_RESTART +// Description : Write 1 to restart the clock dividers of state machines in +// neighbouring PIO blocks, as specified by NEXT_PIO_MASK and +// PREV_PIO_MASK in the same write. +// +// This is equivalent to writing 1 to the corresponding +// CLKDIV_RESTART bits in those PIOs' CTRL registers. +#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_RESET _u(0x0) +#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_BITS _u(0x04000000) +#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_MSB _u(26) +#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_LSB _u(26) +#define PIO_CTRL_NEXTPREV_CLKDIV_RESTART_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_NEXTPREV_SM_DISABLE +// Description : Write 1 to disable state machines in neighbouring PIO blocks, +// as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same +// write. +// +// This is equivalent to clearing the corresponding SM_ENABLE bits +// in those PIOs' CTRL registers. +#define PIO_CTRL_NEXTPREV_SM_DISABLE_RESET _u(0x0) +#define PIO_CTRL_NEXTPREV_SM_DISABLE_BITS _u(0x02000000) +#define PIO_CTRL_NEXTPREV_SM_DISABLE_MSB _u(25) +#define PIO_CTRL_NEXTPREV_SM_DISABLE_LSB _u(25) +#define PIO_CTRL_NEXTPREV_SM_DISABLE_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_NEXTPREV_SM_ENABLE +// Description : Write 1 to enable state machines in neighbouring PIO blocks, as +// specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. +// +// This is equivalent to setting the corresponding SM_ENABLE bits +// in those PIOs' CTRL registers. +// +// If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the +// disable takes precedence. +#define PIO_CTRL_NEXTPREV_SM_ENABLE_RESET _u(0x0) +#define PIO_CTRL_NEXTPREV_SM_ENABLE_BITS _u(0x01000000) +#define PIO_CTRL_NEXTPREV_SM_ENABLE_MSB _u(24) +#define PIO_CTRL_NEXTPREV_SM_ENABLE_LSB _u(24) +#define PIO_CTRL_NEXTPREV_SM_ENABLE_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_NEXT_PIO_MASK +// Description : A mask of state machines in the neighbouring higher-numbered +// PIO block in the system (or PIO block 0 if this is the highest- +// numbered PIO block) to which to apply the operations specified +// by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and +// NEXTPREV_SM_DISABLE in the same write. +// +// This allows state machines in a neighbouring PIO block to be +// started/stopped/clock-synced exactly simultaneously with a +// write to this PIO block's CTRL register. +// +// Note that in a system with two PIOs, NEXT_PIO_MASK and +// PREV_PIO_MASK actually indicate the same PIO block. In this +// case the effects are applied cumulatively (as though the masks +// were OR'd together). +// +// Neighbouring PIO blocks are disconnected (status signals tied +// to 0 and control signals ignored) if one block is accessible to +// NonSecure code, and one is not. +#define PIO_CTRL_NEXT_PIO_MASK_RESET _u(0x0) +#define PIO_CTRL_NEXT_PIO_MASK_BITS _u(0x00f00000) +#define PIO_CTRL_NEXT_PIO_MASK_MSB _u(23) +#define PIO_CTRL_NEXT_PIO_MASK_LSB _u(20) +#define PIO_CTRL_NEXT_PIO_MASK_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_PREV_PIO_MASK +// Description : A mask of state machines in the neighbouring lower-numbered PIO +// block in the system (or the highest-numbered PIO block if this +// is PIO block 0) to which to apply the operations specified by +// OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. +// +// This allows state machines in a neighbouring PIO block to be +// started/stopped/clock-synced exactly simultaneously with a +// write to this PIO block's CTRL register. +// +// Neighbouring PIO blocks are disconnected (status signals tied +// to 0 and control signals ignored) if one block is accessible to +// NonSecure code, and one is not. +#define PIO_CTRL_PREV_PIO_MASK_RESET _u(0x0) +#define PIO_CTRL_PREV_PIO_MASK_BITS _u(0x000f0000) +#define PIO_CTRL_PREV_PIO_MASK_MSB _u(19) +#define PIO_CTRL_PREV_PIO_MASK_LSB _u(16) +#define PIO_CTRL_PREV_PIO_MASK_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_CLKDIV_RESTART +// Description : Restart a state machine's clock divider from an initial phase +// of 0. Clock dividers are free-running, so once started, their +// output (including fractional jitter) is completely determined +// by the integer/fractional divisor configured in SMx_CLKDIV. +// This means that, if multiple clock dividers with the same +// divisor are restarted simultaneously, by writing multiple 1 +// bits to this field, the execution clocks of those state +// machines will run in precise lockstep. +// +// Note that setting/clearing SM_ENABLE does not stop the clock +// divider from running, so once multiple state machines' clocks +// are synchronised, it is safe to disable/reenable a state +// machine, whilst keeping the clock dividers in sync. +// +// Note also that CLKDIV_RESTART can be written to whilst the +// state machine is running, and this is useful to resynchronise +// clock dividers after the divisors (SMx_CLKDIV) have been +// changed on-the-fly. +#define PIO_CTRL_CLKDIV_RESTART_RESET _u(0x0) +#define PIO_CTRL_CLKDIV_RESTART_BITS _u(0x00000f00) +#define PIO_CTRL_CLKDIV_RESTART_MSB _u(11) +#define PIO_CTRL_CLKDIV_RESTART_LSB _u(8) +#define PIO_CTRL_CLKDIV_RESTART_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_SM_RESTART +// Description : Write 1 to instantly clear internal SM state which may be +// otherwise difficult to access and will affect future execution. +// +// Specifically, the following are cleared: input and output shift +// counters; the contents of the input shift register; the delay +// counter; the waiting-on-IRQ state; any stalled instruction +// written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left +// asserted due to OUT_STICKY. +// +// The contents of the output shift register and the X/Y scratch +// registers are not affected. +#define PIO_CTRL_SM_RESTART_RESET _u(0x0) +#define PIO_CTRL_SM_RESTART_BITS _u(0x000000f0) +#define PIO_CTRL_SM_RESTART_MSB _u(7) +#define PIO_CTRL_SM_RESTART_LSB _u(4) +#define PIO_CTRL_SM_RESTART_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PIO_CTRL_SM_ENABLE +// Description : Enable/disable each of the four state machines by writing 1/0 +// to each of these four bits. When disabled, a state machine will +// cease executing instructions, except those written directly to +// SMx_INSTR by the system. Multiple bits can be set/cleared at +// once to run/halt multiple state machines simultaneously. +#define PIO_CTRL_SM_ENABLE_RESET _u(0x0) +#define PIO_CTRL_SM_ENABLE_BITS _u(0x0000000f) +#define PIO_CTRL_SM_ENABLE_MSB _u(3) +#define PIO_CTRL_SM_ENABLE_LSB _u(0) +#define PIO_CTRL_SM_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : PIO_FSTAT +// Description : FIFO status register +#define PIO_FSTAT_OFFSET _u(0x00000004) +#define PIO_FSTAT_BITS _u(0x0f0f0f0f) +#define PIO_FSTAT_RESET _u(0x0f000f00) +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_TXEMPTY +// Description : State machine TX FIFO is empty +#define PIO_FSTAT_TXEMPTY_RESET _u(0xf) +#define PIO_FSTAT_TXEMPTY_BITS _u(0x0f000000) +#define PIO_FSTAT_TXEMPTY_MSB _u(27) +#define PIO_FSTAT_TXEMPTY_LSB _u(24) +#define PIO_FSTAT_TXEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_TXFULL +// Description : State machine TX FIFO is full +#define PIO_FSTAT_TXFULL_RESET _u(0x0) +#define PIO_FSTAT_TXFULL_BITS _u(0x000f0000) +#define PIO_FSTAT_TXFULL_MSB _u(19) +#define PIO_FSTAT_TXFULL_LSB _u(16) +#define PIO_FSTAT_TXFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_RXEMPTY +// Description : State machine RX FIFO is empty +#define PIO_FSTAT_RXEMPTY_RESET _u(0xf) +#define PIO_FSTAT_RXEMPTY_BITS _u(0x00000f00) +#define PIO_FSTAT_RXEMPTY_MSB _u(11) +#define PIO_FSTAT_RXEMPTY_LSB _u(8) +#define PIO_FSTAT_RXEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FSTAT_RXFULL +// Description : State machine RX FIFO is full +#define PIO_FSTAT_RXFULL_RESET _u(0x0) +#define PIO_FSTAT_RXFULL_BITS _u(0x0000000f) +#define PIO_FSTAT_RXFULL_MSB _u(3) +#define PIO_FSTAT_RXFULL_LSB _u(0) +#define PIO_FSTAT_RXFULL_ACCESS "RO" +// ============================================================================= +// Register : PIO_FDEBUG +// Description : FIFO debug register +#define PIO_FDEBUG_OFFSET _u(0x00000008) +#define PIO_FDEBUG_BITS _u(0x0f0f0f0f) +#define PIO_FDEBUG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_TXSTALL +// Description : State machine has stalled on empty TX FIFO during a blocking +// PULL, or an OUT with autopull enabled. Write 1 to clear. +#define PIO_FDEBUG_TXSTALL_RESET _u(0x0) +#define PIO_FDEBUG_TXSTALL_BITS _u(0x0f000000) +#define PIO_FDEBUG_TXSTALL_MSB _u(27) +#define PIO_FDEBUG_TXSTALL_LSB _u(24) +#define PIO_FDEBUG_TXSTALL_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_TXOVER +// Description : TX FIFO overflow (i.e. write-on-full by the system) has +// occurred. Write 1 to clear. Note that write-on-full does not +// alter the state or contents of the FIFO in any way, but the +// data that the system attempted to write is dropped, so if this +// flag is set, your software has quite likely dropped some data +// on the floor. +#define PIO_FDEBUG_TXOVER_RESET _u(0x0) +#define PIO_FDEBUG_TXOVER_BITS _u(0x000f0000) +#define PIO_FDEBUG_TXOVER_MSB _u(19) +#define PIO_FDEBUG_TXOVER_LSB _u(16) +#define PIO_FDEBUG_TXOVER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_RXUNDER +// Description : RX FIFO underflow (i.e. read-on-empty by the system) has +// occurred. Write 1 to clear. Note that read-on-empty does not +// perturb the state of the FIFO in any way, but the data returned +// by reading from an empty FIFO is undefined, so this flag +// generally only becomes set due to some kind of software error. +#define PIO_FDEBUG_RXUNDER_RESET _u(0x0) +#define PIO_FDEBUG_RXUNDER_BITS _u(0x00000f00) +#define PIO_FDEBUG_RXUNDER_MSB _u(11) +#define PIO_FDEBUG_RXUNDER_LSB _u(8) +#define PIO_FDEBUG_RXUNDER_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PIO_FDEBUG_RXSTALL +// Description : State machine has stalled on full RX FIFO during a blocking +// PUSH, or an IN with autopush enabled. This flag is also set +// when a nonblocking PUSH to a full FIFO took place, in which +// case the state machine has dropped data. Write 1 to clear. +#define PIO_FDEBUG_RXSTALL_RESET _u(0x0) +#define PIO_FDEBUG_RXSTALL_BITS _u(0x0000000f) +#define PIO_FDEBUG_RXSTALL_MSB _u(3) +#define PIO_FDEBUG_RXSTALL_LSB _u(0) +#define PIO_FDEBUG_RXSTALL_ACCESS "WC" +// ============================================================================= +// Register : PIO_FLEVEL +// Description : FIFO levels +#define PIO_FLEVEL_OFFSET _u(0x0000000c) +#define PIO_FLEVEL_BITS _u(0xffffffff) +#define PIO_FLEVEL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX3 +#define PIO_FLEVEL_RX3_RESET _u(0x0) +#define PIO_FLEVEL_RX3_BITS _u(0xf0000000) +#define PIO_FLEVEL_RX3_MSB _u(31) +#define PIO_FLEVEL_RX3_LSB _u(28) +#define PIO_FLEVEL_RX3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX3 +#define PIO_FLEVEL_TX3_RESET _u(0x0) +#define PIO_FLEVEL_TX3_BITS _u(0x0f000000) +#define PIO_FLEVEL_TX3_MSB _u(27) +#define PIO_FLEVEL_TX3_LSB _u(24) +#define PIO_FLEVEL_TX3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX2 +#define PIO_FLEVEL_RX2_RESET _u(0x0) +#define PIO_FLEVEL_RX2_BITS _u(0x00f00000) +#define PIO_FLEVEL_RX2_MSB _u(23) +#define PIO_FLEVEL_RX2_LSB _u(20) +#define PIO_FLEVEL_RX2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX2 +#define PIO_FLEVEL_TX2_RESET _u(0x0) +#define PIO_FLEVEL_TX2_BITS _u(0x000f0000) +#define PIO_FLEVEL_TX2_MSB _u(19) +#define PIO_FLEVEL_TX2_LSB _u(16) +#define PIO_FLEVEL_TX2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX1 +#define PIO_FLEVEL_RX1_RESET _u(0x0) +#define PIO_FLEVEL_RX1_BITS _u(0x0000f000) +#define PIO_FLEVEL_RX1_MSB _u(15) +#define PIO_FLEVEL_RX1_LSB _u(12) +#define PIO_FLEVEL_RX1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX1 +#define PIO_FLEVEL_TX1_RESET _u(0x0) +#define PIO_FLEVEL_TX1_BITS _u(0x00000f00) +#define PIO_FLEVEL_TX1_MSB _u(11) +#define PIO_FLEVEL_TX1_LSB _u(8) +#define PIO_FLEVEL_TX1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_RX0 +#define PIO_FLEVEL_RX0_RESET _u(0x0) +#define PIO_FLEVEL_RX0_BITS _u(0x000000f0) +#define PIO_FLEVEL_RX0_MSB _u(7) +#define PIO_FLEVEL_RX0_LSB _u(4) +#define PIO_FLEVEL_RX0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_FLEVEL_TX0 +#define PIO_FLEVEL_TX0_RESET _u(0x0) +#define PIO_FLEVEL_TX0_BITS _u(0x0000000f) +#define PIO_FLEVEL_TX0_MSB _u(3) +#define PIO_FLEVEL_TX0_LSB _u(0) +#define PIO_FLEVEL_TX0_ACCESS "RO" +// ============================================================================= +// Register : PIO_TXF0 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF0_OFFSET _u(0x00000010) +#define PIO_TXF0_BITS _u(0xffffffff) +#define PIO_TXF0_RESET _u(0x00000000) +#define PIO_TXF0_MSB _u(31) +#define PIO_TXF0_LSB _u(0) +#define PIO_TXF0_ACCESS "WF" +// ============================================================================= +// Register : PIO_TXF1 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF1_OFFSET _u(0x00000014) +#define PIO_TXF1_BITS _u(0xffffffff) +#define PIO_TXF1_RESET _u(0x00000000) +#define PIO_TXF1_MSB _u(31) +#define PIO_TXF1_LSB _u(0) +#define PIO_TXF1_ACCESS "WF" +// ============================================================================= +// Register : PIO_TXF2 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF2_OFFSET _u(0x00000018) +#define PIO_TXF2_BITS _u(0xffffffff) +#define PIO_TXF2_RESET _u(0x00000000) +#define PIO_TXF2_MSB _u(31) +#define PIO_TXF2_LSB _u(0) +#define PIO_TXF2_ACCESS "WF" +// ============================================================================= +// Register : PIO_TXF3 +// Description : Direct write access to the TX FIFO for this state machine. Each +// write pushes one word to the FIFO. Attempting to write to a +// full FIFO has no effect on the FIFO state or contents, and sets +// the sticky FDEBUG_TXOVER error flag for this FIFO. +#define PIO_TXF3_OFFSET _u(0x0000001c) +#define PIO_TXF3_BITS _u(0xffffffff) +#define PIO_TXF3_RESET _u(0x00000000) +#define PIO_TXF3_MSB _u(31) +#define PIO_TXF3_LSB _u(0) +#define PIO_TXF3_ACCESS "WF" +// ============================================================================= +// Register : PIO_RXF0 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF0_OFFSET _u(0x00000020) +#define PIO_RXF0_BITS _u(0xffffffff) +#define PIO_RXF0_RESET "-" +#define PIO_RXF0_MSB _u(31) +#define PIO_RXF0_LSB _u(0) +#define PIO_RXF0_ACCESS "RF" +// ============================================================================= +// Register : PIO_RXF1 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF1_OFFSET _u(0x00000024) +#define PIO_RXF1_BITS _u(0xffffffff) +#define PIO_RXF1_RESET "-" +#define PIO_RXF1_MSB _u(31) +#define PIO_RXF1_LSB _u(0) +#define PIO_RXF1_ACCESS "RF" +// ============================================================================= +// Register : PIO_RXF2 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF2_OFFSET _u(0x00000028) +#define PIO_RXF2_BITS _u(0xffffffff) +#define PIO_RXF2_RESET "-" +#define PIO_RXF2_MSB _u(31) +#define PIO_RXF2_LSB _u(0) +#define PIO_RXF2_ACCESS "RF" +// ============================================================================= +// Register : PIO_RXF3 +// Description : Direct read access to the RX FIFO for this state machine. Each +// read pops one word from the FIFO. Attempting to read from an +// empty FIFO has no effect on the FIFO state, and sets the sticky +// FDEBUG_RXUNDER error flag for this FIFO. The data returned to +// the system on a read from an empty FIFO is undefined. +#define PIO_RXF3_OFFSET _u(0x0000002c) +#define PIO_RXF3_BITS _u(0xffffffff) +#define PIO_RXF3_RESET "-" +#define PIO_RXF3_MSB _u(31) +#define PIO_RXF3_LSB _u(0) +#define PIO_RXF3_ACCESS "RF" +// ============================================================================= +// Register : PIO_IRQ +// Description : State machine IRQ flags register. Write 1 to clear. There are +// eight state machine IRQ flags, which can be set, cleared, and +// waited on by the state machines. There's no fixed association +// between flags and state machines -- any state machine can use +// any flag. +// +// Any of the eight flags can be used for timing synchronisation +// between state machines, using IRQ and WAIT instructions. Any +// combination of the eight flags can also routed out to either of +// the two system-level interrupt requests, alongside FIFO status +// interrupts -- see e.g. IRQ0_INTE. +#define PIO_IRQ_OFFSET _u(0x00000030) +#define PIO_IRQ_BITS _u(0x000000ff) +#define PIO_IRQ_RESET _u(0x00000000) +#define PIO_IRQ_MSB _u(7) +#define PIO_IRQ_LSB _u(0) +#define PIO_IRQ_ACCESS "WC" +// ============================================================================= +// Register : PIO_IRQ_FORCE +// Description : Writing a 1 to each of these bits will forcibly assert the +// corresponding IRQ. Note this is different to the INTF register: +// writing here affects PIO internal state. INTF just asserts the +// processor-facing IRQ signal for testing ISRs, and is not +// visible to the state machines. +#define PIO_IRQ_FORCE_OFFSET _u(0x00000034) +#define PIO_IRQ_FORCE_BITS _u(0x000000ff) +#define PIO_IRQ_FORCE_RESET _u(0x00000000) +#define PIO_IRQ_FORCE_MSB _u(7) +#define PIO_IRQ_FORCE_LSB _u(0) +#define PIO_IRQ_FORCE_ACCESS "WF" +// ============================================================================= +// Register : PIO_INPUT_SYNC_BYPASS +// Description : There is a 2-flipflop synchronizer on each GPIO input, which +// protects PIO logic from metastabilities. This increases input +// delay, and for fast synchronous IO (e.g. SPI) these +// synchronizers may need to be bypassed. Each bit in this +// register corresponds to one GPIO. +// 0 -> input is synchronized (default) +// 1 -> synchronizer is bypassed +// If in doubt, leave this register as all zeroes. +#define PIO_INPUT_SYNC_BYPASS_OFFSET _u(0x00000038) +#define PIO_INPUT_SYNC_BYPASS_BITS _u(0xffffffff) +#define PIO_INPUT_SYNC_BYPASS_RESET _u(0x00000000) +#define PIO_INPUT_SYNC_BYPASS_MSB _u(31) +#define PIO_INPUT_SYNC_BYPASS_LSB _u(0) +#define PIO_INPUT_SYNC_BYPASS_ACCESS "RW" +// ============================================================================= +// Register : PIO_DBG_PADOUT +// Description : Read to sample the pad output values PIO is currently driving +// to the GPIOs. On RP2040 there are 30 GPIOs, so the two most +// significant bits are hardwired to 0. +#define PIO_DBG_PADOUT_OFFSET _u(0x0000003c) +#define PIO_DBG_PADOUT_BITS _u(0xffffffff) +#define PIO_DBG_PADOUT_RESET _u(0x00000000) +#define PIO_DBG_PADOUT_MSB _u(31) +#define PIO_DBG_PADOUT_LSB _u(0) +#define PIO_DBG_PADOUT_ACCESS "RO" +// ============================================================================= +// Register : PIO_DBG_PADOE +// Description : Read to sample the pad output enables (direction) PIO is +// currently driving to the GPIOs. On RP2040 there are 30 GPIOs, +// so the two most significant bits are hardwired to 0. +#define PIO_DBG_PADOE_OFFSET _u(0x00000040) +#define PIO_DBG_PADOE_BITS _u(0xffffffff) +#define PIO_DBG_PADOE_RESET _u(0x00000000) +#define PIO_DBG_PADOE_MSB _u(31) +#define PIO_DBG_PADOE_LSB _u(0) +#define PIO_DBG_PADOE_ACCESS "RO" +// ============================================================================= +// Register : PIO_DBG_CFGINFO +// Description : The PIO hardware has some free parameters that may vary between +// chip products. +// These should be provided in the chip datasheet, but are also +// exposed here. +#define PIO_DBG_CFGINFO_OFFSET _u(0x00000044) +#define PIO_DBG_CFGINFO_BITS _u(0xf03f0f3f) +#define PIO_DBG_CFGINFO_RESET _u(0x10000000) +// ----------------------------------------------------------------------------- +// Field : PIO_DBG_CFGINFO_VERSION +// Description : Version of the core PIO hardware. +// 0x0 -> Version 0 (RP2040) +// 0x1 -> Version 1 (RP2350) +#define PIO_DBG_CFGINFO_VERSION_RESET _u(0x1) +#define PIO_DBG_CFGINFO_VERSION_BITS _u(0xf0000000) +#define PIO_DBG_CFGINFO_VERSION_MSB _u(31) +#define PIO_DBG_CFGINFO_VERSION_LSB _u(28) +#define PIO_DBG_CFGINFO_VERSION_ACCESS "RO" +#define PIO_DBG_CFGINFO_VERSION_VALUE_V0 _u(0x0) +#define PIO_DBG_CFGINFO_VERSION_VALUE_V1 _u(0x1) +// ----------------------------------------------------------------------------- +// Field : PIO_DBG_CFGINFO_IMEM_SIZE +// Description : The size of the instruction memory, measured in units of one +// instruction +#define PIO_DBG_CFGINFO_IMEM_SIZE_RESET "-" +#define PIO_DBG_CFGINFO_IMEM_SIZE_BITS _u(0x003f0000) +#define PIO_DBG_CFGINFO_IMEM_SIZE_MSB _u(21) +#define PIO_DBG_CFGINFO_IMEM_SIZE_LSB _u(16) +#define PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_DBG_CFGINFO_SM_COUNT +// Description : The number of state machines this PIO instance is equipped +// with. +#define PIO_DBG_CFGINFO_SM_COUNT_RESET "-" +#define PIO_DBG_CFGINFO_SM_COUNT_BITS _u(0x00000f00) +#define PIO_DBG_CFGINFO_SM_COUNT_MSB _u(11) +#define PIO_DBG_CFGINFO_SM_COUNT_LSB _u(8) +#define PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_DBG_CFGINFO_FIFO_DEPTH +// Description : The depth of the state machine TX/RX FIFOs, measured in words. +// Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double +// this depth. +#define PIO_DBG_CFGINFO_FIFO_DEPTH_RESET "-" +#define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS _u(0x0000003f) +#define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB _u(5) +#define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB _u(0) +#define PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO" +// ============================================================================= +// Register : PIO_INSTR_MEM0 +// Description : Write-only access to instruction memory location 0 +#define PIO_INSTR_MEM0_OFFSET _u(0x00000048) +#define PIO_INSTR_MEM0_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM0_RESET _u(0x00000000) +#define PIO_INSTR_MEM0_MSB _u(15) +#define PIO_INSTR_MEM0_LSB _u(0) +#define PIO_INSTR_MEM0_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM1 +// Description : Write-only access to instruction memory location 1 +#define PIO_INSTR_MEM1_OFFSET _u(0x0000004c) +#define PIO_INSTR_MEM1_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM1_RESET _u(0x00000000) +#define PIO_INSTR_MEM1_MSB _u(15) +#define PIO_INSTR_MEM1_LSB _u(0) +#define PIO_INSTR_MEM1_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM2 +// Description : Write-only access to instruction memory location 2 +#define PIO_INSTR_MEM2_OFFSET _u(0x00000050) +#define PIO_INSTR_MEM2_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM2_RESET _u(0x00000000) +#define PIO_INSTR_MEM2_MSB _u(15) +#define PIO_INSTR_MEM2_LSB _u(0) +#define PIO_INSTR_MEM2_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM3 +// Description : Write-only access to instruction memory location 3 +#define PIO_INSTR_MEM3_OFFSET _u(0x00000054) +#define PIO_INSTR_MEM3_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM3_RESET _u(0x00000000) +#define PIO_INSTR_MEM3_MSB _u(15) +#define PIO_INSTR_MEM3_LSB _u(0) +#define PIO_INSTR_MEM3_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM4 +// Description : Write-only access to instruction memory location 4 +#define PIO_INSTR_MEM4_OFFSET _u(0x00000058) +#define PIO_INSTR_MEM4_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM4_RESET _u(0x00000000) +#define PIO_INSTR_MEM4_MSB _u(15) +#define PIO_INSTR_MEM4_LSB _u(0) +#define PIO_INSTR_MEM4_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM5 +// Description : Write-only access to instruction memory location 5 +#define PIO_INSTR_MEM5_OFFSET _u(0x0000005c) +#define PIO_INSTR_MEM5_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM5_RESET _u(0x00000000) +#define PIO_INSTR_MEM5_MSB _u(15) +#define PIO_INSTR_MEM5_LSB _u(0) +#define PIO_INSTR_MEM5_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM6 +// Description : Write-only access to instruction memory location 6 +#define PIO_INSTR_MEM6_OFFSET _u(0x00000060) +#define PIO_INSTR_MEM6_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM6_RESET _u(0x00000000) +#define PIO_INSTR_MEM6_MSB _u(15) +#define PIO_INSTR_MEM6_LSB _u(0) +#define PIO_INSTR_MEM6_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM7 +// Description : Write-only access to instruction memory location 7 +#define PIO_INSTR_MEM7_OFFSET _u(0x00000064) +#define PIO_INSTR_MEM7_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM7_RESET _u(0x00000000) +#define PIO_INSTR_MEM7_MSB _u(15) +#define PIO_INSTR_MEM7_LSB _u(0) +#define PIO_INSTR_MEM7_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM8 +// Description : Write-only access to instruction memory location 8 +#define PIO_INSTR_MEM8_OFFSET _u(0x00000068) +#define PIO_INSTR_MEM8_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM8_RESET _u(0x00000000) +#define PIO_INSTR_MEM8_MSB _u(15) +#define PIO_INSTR_MEM8_LSB _u(0) +#define PIO_INSTR_MEM8_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM9 +// Description : Write-only access to instruction memory location 9 +#define PIO_INSTR_MEM9_OFFSET _u(0x0000006c) +#define PIO_INSTR_MEM9_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM9_RESET _u(0x00000000) +#define PIO_INSTR_MEM9_MSB _u(15) +#define PIO_INSTR_MEM9_LSB _u(0) +#define PIO_INSTR_MEM9_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM10 +// Description : Write-only access to instruction memory location 10 +#define PIO_INSTR_MEM10_OFFSET _u(0x00000070) +#define PIO_INSTR_MEM10_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM10_RESET _u(0x00000000) +#define PIO_INSTR_MEM10_MSB _u(15) +#define PIO_INSTR_MEM10_LSB _u(0) +#define PIO_INSTR_MEM10_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM11 +// Description : Write-only access to instruction memory location 11 +#define PIO_INSTR_MEM11_OFFSET _u(0x00000074) +#define PIO_INSTR_MEM11_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM11_RESET _u(0x00000000) +#define PIO_INSTR_MEM11_MSB _u(15) +#define PIO_INSTR_MEM11_LSB _u(0) +#define PIO_INSTR_MEM11_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM12 +// Description : Write-only access to instruction memory location 12 +#define PIO_INSTR_MEM12_OFFSET _u(0x00000078) +#define PIO_INSTR_MEM12_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM12_RESET _u(0x00000000) +#define PIO_INSTR_MEM12_MSB _u(15) +#define PIO_INSTR_MEM12_LSB _u(0) +#define PIO_INSTR_MEM12_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM13 +// Description : Write-only access to instruction memory location 13 +#define PIO_INSTR_MEM13_OFFSET _u(0x0000007c) +#define PIO_INSTR_MEM13_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM13_RESET _u(0x00000000) +#define PIO_INSTR_MEM13_MSB _u(15) +#define PIO_INSTR_MEM13_LSB _u(0) +#define PIO_INSTR_MEM13_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM14 +// Description : Write-only access to instruction memory location 14 +#define PIO_INSTR_MEM14_OFFSET _u(0x00000080) +#define PIO_INSTR_MEM14_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM14_RESET _u(0x00000000) +#define PIO_INSTR_MEM14_MSB _u(15) +#define PIO_INSTR_MEM14_LSB _u(0) +#define PIO_INSTR_MEM14_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM15 +// Description : Write-only access to instruction memory location 15 +#define PIO_INSTR_MEM15_OFFSET _u(0x00000084) +#define PIO_INSTR_MEM15_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM15_RESET _u(0x00000000) +#define PIO_INSTR_MEM15_MSB _u(15) +#define PIO_INSTR_MEM15_LSB _u(0) +#define PIO_INSTR_MEM15_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM16 +// Description : Write-only access to instruction memory location 16 +#define PIO_INSTR_MEM16_OFFSET _u(0x00000088) +#define PIO_INSTR_MEM16_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM16_RESET _u(0x00000000) +#define PIO_INSTR_MEM16_MSB _u(15) +#define PIO_INSTR_MEM16_LSB _u(0) +#define PIO_INSTR_MEM16_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM17 +// Description : Write-only access to instruction memory location 17 +#define PIO_INSTR_MEM17_OFFSET _u(0x0000008c) +#define PIO_INSTR_MEM17_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM17_RESET _u(0x00000000) +#define PIO_INSTR_MEM17_MSB _u(15) +#define PIO_INSTR_MEM17_LSB _u(0) +#define PIO_INSTR_MEM17_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM18 +// Description : Write-only access to instruction memory location 18 +#define PIO_INSTR_MEM18_OFFSET _u(0x00000090) +#define PIO_INSTR_MEM18_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM18_RESET _u(0x00000000) +#define PIO_INSTR_MEM18_MSB _u(15) +#define PIO_INSTR_MEM18_LSB _u(0) +#define PIO_INSTR_MEM18_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM19 +// Description : Write-only access to instruction memory location 19 +#define PIO_INSTR_MEM19_OFFSET _u(0x00000094) +#define PIO_INSTR_MEM19_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM19_RESET _u(0x00000000) +#define PIO_INSTR_MEM19_MSB _u(15) +#define PIO_INSTR_MEM19_LSB _u(0) +#define PIO_INSTR_MEM19_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM20 +// Description : Write-only access to instruction memory location 20 +#define PIO_INSTR_MEM20_OFFSET _u(0x00000098) +#define PIO_INSTR_MEM20_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM20_RESET _u(0x00000000) +#define PIO_INSTR_MEM20_MSB _u(15) +#define PIO_INSTR_MEM20_LSB _u(0) +#define PIO_INSTR_MEM20_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM21 +// Description : Write-only access to instruction memory location 21 +#define PIO_INSTR_MEM21_OFFSET _u(0x0000009c) +#define PIO_INSTR_MEM21_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM21_RESET _u(0x00000000) +#define PIO_INSTR_MEM21_MSB _u(15) +#define PIO_INSTR_MEM21_LSB _u(0) +#define PIO_INSTR_MEM21_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM22 +// Description : Write-only access to instruction memory location 22 +#define PIO_INSTR_MEM22_OFFSET _u(0x000000a0) +#define PIO_INSTR_MEM22_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM22_RESET _u(0x00000000) +#define PIO_INSTR_MEM22_MSB _u(15) +#define PIO_INSTR_MEM22_LSB _u(0) +#define PIO_INSTR_MEM22_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM23 +// Description : Write-only access to instruction memory location 23 +#define PIO_INSTR_MEM23_OFFSET _u(0x000000a4) +#define PIO_INSTR_MEM23_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM23_RESET _u(0x00000000) +#define PIO_INSTR_MEM23_MSB _u(15) +#define PIO_INSTR_MEM23_LSB _u(0) +#define PIO_INSTR_MEM23_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM24 +// Description : Write-only access to instruction memory location 24 +#define PIO_INSTR_MEM24_OFFSET _u(0x000000a8) +#define PIO_INSTR_MEM24_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM24_RESET _u(0x00000000) +#define PIO_INSTR_MEM24_MSB _u(15) +#define PIO_INSTR_MEM24_LSB _u(0) +#define PIO_INSTR_MEM24_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM25 +// Description : Write-only access to instruction memory location 25 +#define PIO_INSTR_MEM25_OFFSET _u(0x000000ac) +#define PIO_INSTR_MEM25_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM25_RESET _u(0x00000000) +#define PIO_INSTR_MEM25_MSB _u(15) +#define PIO_INSTR_MEM25_LSB _u(0) +#define PIO_INSTR_MEM25_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM26 +// Description : Write-only access to instruction memory location 26 +#define PIO_INSTR_MEM26_OFFSET _u(0x000000b0) +#define PIO_INSTR_MEM26_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM26_RESET _u(0x00000000) +#define PIO_INSTR_MEM26_MSB _u(15) +#define PIO_INSTR_MEM26_LSB _u(0) +#define PIO_INSTR_MEM26_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM27 +// Description : Write-only access to instruction memory location 27 +#define PIO_INSTR_MEM27_OFFSET _u(0x000000b4) +#define PIO_INSTR_MEM27_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM27_RESET _u(0x00000000) +#define PIO_INSTR_MEM27_MSB _u(15) +#define PIO_INSTR_MEM27_LSB _u(0) +#define PIO_INSTR_MEM27_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM28 +// Description : Write-only access to instruction memory location 28 +#define PIO_INSTR_MEM28_OFFSET _u(0x000000b8) +#define PIO_INSTR_MEM28_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM28_RESET _u(0x00000000) +#define PIO_INSTR_MEM28_MSB _u(15) +#define PIO_INSTR_MEM28_LSB _u(0) +#define PIO_INSTR_MEM28_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM29 +// Description : Write-only access to instruction memory location 29 +#define PIO_INSTR_MEM29_OFFSET _u(0x000000bc) +#define PIO_INSTR_MEM29_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM29_RESET _u(0x00000000) +#define PIO_INSTR_MEM29_MSB _u(15) +#define PIO_INSTR_MEM29_LSB _u(0) +#define PIO_INSTR_MEM29_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM30 +// Description : Write-only access to instruction memory location 30 +#define PIO_INSTR_MEM30_OFFSET _u(0x000000c0) +#define PIO_INSTR_MEM30_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM30_RESET _u(0x00000000) +#define PIO_INSTR_MEM30_MSB _u(15) +#define PIO_INSTR_MEM30_LSB _u(0) +#define PIO_INSTR_MEM30_ACCESS "WO" +// ============================================================================= +// Register : PIO_INSTR_MEM31 +// Description : Write-only access to instruction memory location 31 +#define PIO_INSTR_MEM31_OFFSET _u(0x000000c4) +#define PIO_INSTR_MEM31_BITS _u(0x0000ffff) +#define PIO_INSTR_MEM31_RESET _u(0x00000000) +#define PIO_INSTR_MEM31_MSB _u(15) +#define PIO_INSTR_MEM31_LSB _u(0) +#define PIO_INSTR_MEM31_ACCESS "WO" +// ============================================================================= +// Register : PIO_SM0_CLKDIV +// Description : Clock divisor register for state machine 0 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM0_CLKDIV_OFFSET _u(0x000000c8) +#define PIO_SM0_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM0_CLKDIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_CLKDIV_INT +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM0_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM0_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM0_CLKDIV_INT_MSB _u(31) +#define PIO_SM0_CLKDIV_INT_LSB _u(16) +#define PIO_SM0_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_CLKDIV_FRAC +// Description : Fractional part of clock divisor +#define PIO_SM0_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM0_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM0_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM0_CLKDIV_FRAC_LSB _u(8) +#define PIO_SM0_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM0_EXECCTRL +// Description : Execution/behavioural settings for state machine 0 +#define PIO_SM0_EXECCTRL_OFFSET _u(0x000000cc) +#define PIO_SM0_EXECCTRL_BITS _u(0xffffffff) +#define PIO_SM0_EXECCTRL_RESET _u(0x0001f000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_EXEC_STALLED +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB _u(31) +#define PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_SIDE_EN +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM0_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM0_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM0_EXECCTRL_SIDE_EN_LSB _u(30) +#define PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_SIDE_PINDIR +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB _u(29) +#define PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM0_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM0_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM0_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM0_EXECCTRL_JMP_PIN_LSB _u(24) +#define PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB _u(19) +#define PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB _u(18) +#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM0_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM0_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM0_EXECCTRL_OUT_STICKY_LSB _u(17) +#define PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM0_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM0_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM0_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM0_EXECCTRL_WRAP_TOP_LSB _u(12) +#define PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB _u(7) +#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes +#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) +#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(6) +#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(5) +#define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) +#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_IRQ _u(0x2) +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_EXECCTRL_STATUS_N +// Description : Comparison level or IRQ index for the MOV x, STATUS +// instruction. +// +// If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N +// greater than the current FIFO depth are reserved, and have +// undefined behaviour. +// 0x00 -> Index 0-7 of an IRQ flag in this PIO block +// 0x08 -> Index 0-7 of an IRQ flag in the next lower-numbered PIO block +// 0x10 -> Index 0-7 of an IRQ flag in the next higher-numbered PIO block +#define PIO_SM0_EXECCTRL_STATUS_N_RESET _u(0x00) +#define PIO_SM0_EXECCTRL_STATUS_N_BITS _u(0x0000001f) +#define PIO_SM0_EXECCTRL_STATUS_N_MSB _u(4) +#define PIO_SM0_EXECCTRL_STATUS_N_LSB _u(0) +#define PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW" +#define PIO_SM0_EXECCTRL_STATUS_N_VALUE_IRQ _u(0x00) +#define PIO_SM0_EXECCTRL_STATUS_N_VALUE_IRQ_PREVPIO _u(0x08) +#define PIO_SM0_EXECCTRL_STATUS_N_VALUE_IRQ_NEXTPIO _u(0x10) +// ============================================================================= +// Register : PIO_SM0_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 0 +#define PIO_SM0_SHIFTCTRL_OFFSET _u(0x000000d0) +#define PIO_SM0_SHIFTCTRL_BITS _u(0xffffc01f) +#define PIO_SM0_SHIFTCTRL_RESET _u(0x000c0000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB _u(31) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB _u(30) +#define PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. +// Write 0 for value of 32. +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB _u(25) +#define PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. +// Write 0 for value of 32. +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB _u(20) +#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) +#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) +#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB _u(17) +#define PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB _u(16) +#define PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random write access by the state machine (using +// the `put` instruction) and, unless FJOIN_RX_GET is also set, +// random read access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_BITS _u(0x00008000) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_MSB _u(15) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_LSB _u(15) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_PUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_FJOIN_RX_GET +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random read access by the state machine (using +// the `get` instruction) and, unless FJOIN_RX_PUT is also set, +// random write access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_RESET _u(0x0) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_BITS _u(0x00004000) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_MSB _u(14) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_LSB _u(14) +#define PIO_SM0_SHIFTCTRL_FJOIN_RX_GET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_SHIFTCTRL_IN_COUNT +// Description : Set the number of pins which are not masked to 0 when read by +// an IN PINS, WAIT PIN or MOV x, PINS instruction. +// +// For example, an IN_COUNT of 5 means that the 5 LSBs of the IN +// pin group are visible (bits 4:0), but the remaining 27 MSBs are +// masked to 0. A count of 32 is encoded with a field value of 0, +// so the default behaviour is to not perform any masking. +// +// Note this masking is applied in addition to the masking usually +// performed by the IN instruction. This is mainly useful for the +// MOV x, PINS instruction, which otherwise has no way of masking +// pins. +#define PIO_SM0_SHIFTCTRL_IN_COUNT_RESET _u(0x00) +#define PIO_SM0_SHIFTCTRL_IN_COUNT_BITS _u(0x0000001f) +#define PIO_SM0_SHIFTCTRL_IN_COUNT_MSB _u(4) +#define PIO_SM0_SHIFTCTRL_IN_COUNT_LSB _u(0) +#define PIO_SM0_SHIFTCTRL_IN_COUNT_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM0_ADDR +// Description : Current instruction address of state machine 0 +#define PIO_SM0_ADDR_OFFSET _u(0x000000d4) +#define PIO_SM0_ADDR_BITS _u(0x0000001f) +#define PIO_SM0_ADDR_RESET _u(0x00000000) +#define PIO_SM0_ADDR_MSB _u(4) +#define PIO_SM0_ADDR_LSB _u(0) +#define PIO_SM0_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM0_INSTR +// Description : Read to see the instruction currently addressed by state +// machine 0's program counter +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM0_INSTR_OFFSET _u(0x000000d8) +#define PIO_SM0_INSTR_BITS _u(0x0000ffff) +#define PIO_SM0_INSTR_RESET "-" +#define PIO_SM0_INSTR_MSB _u(15) +#define PIO_SM0_INSTR_LSB _u(0) +#define PIO_SM0_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM0_PINCTRL +// Description : State machine pin control +#define PIO_SM0_PINCTRL_OFFSET _u(0x000000dc) +#define PIO_SM0_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM0_PINCTRL_RESET _u(0x14000000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SIDESET_COUNT +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB _u(29) +#define PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM0_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM0_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM0_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM0_PINCTRL_SET_COUNT_LSB _u(26) +#define PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM0_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM0_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM0_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM0_PINCTRL_OUT_COUNT_LSB _u(20) +#define PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_IN_BASE +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM0_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM0_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM0_PINCTRL_IN_BASE_LSB _u(15) +#define PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SIDESET_BASE +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. +#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM0_PINCTRL_SIDESET_BASE_LSB _u(10) +#define PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_SET_BASE +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM0_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM0_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM0_PINCTRL_SET_BASE_LSB _u(5) +#define PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM0_PINCTRL_OUT_BASE +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM0_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM0_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM0_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM0_PINCTRL_OUT_BASE_LSB _u(0) +#define PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_CLKDIV +// Description : Clock divisor register for state machine 1 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM1_CLKDIV_OFFSET _u(0x000000e0) +#define PIO_SM1_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM1_CLKDIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_CLKDIV_INT +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM1_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM1_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM1_CLKDIV_INT_MSB _u(31) +#define PIO_SM1_CLKDIV_INT_LSB _u(16) +#define PIO_SM1_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_CLKDIV_FRAC +// Description : Fractional part of clock divisor +#define PIO_SM1_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM1_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM1_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM1_CLKDIV_FRAC_LSB _u(8) +#define PIO_SM1_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_EXECCTRL +// Description : Execution/behavioural settings for state machine 1 +#define PIO_SM1_EXECCTRL_OFFSET _u(0x000000e4) +#define PIO_SM1_EXECCTRL_BITS _u(0xffffffff) +#define PIO_SM1_EXECCTRL_RESET _u(0x0001f000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_EXEC_STALLED +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB _u(31) +#define PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_SIDE_EN +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM1_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM1_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM1_EXECCTRL_SIDE_EN_LSB _u(30) +#define PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_SIDE_PINDIR +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB _u(29) +#define PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM1_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM1_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM1_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM1_EXECCTRL_JMP_PIN_LSB _u(24) +#define PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB _u(19) +#define PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB _u(18) +#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM1_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM1_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM1_EXECCTRL_OUT_STICKY_LSB _u(17) +#define PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM1_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM1_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM1_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM1_EXECCTRL_WRAP_TOP_LSB _u(12) +#define PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB _u(7) +#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes +#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) +#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(6) +#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(5) +#define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) +#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_IRQ _u(0x2) +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_EXECCTRL_STATUS_N +// Description : Comparison level or IRQ index for the MOV x, STATUS +// instruction. +// +// If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N +// greater than the current FIFO depth are reserved, and have +// undefined behaviour. +// 0x00 -> Index 0-7 of an IRQ flag in this PIO block +// 0x08 -> Index 0-7 of an IRQ flag in the next lower-numbered PIO block +// 0x10 -> Index 0-7 of an IRQ flag in the next higher-numbered PIO block +#define PIO_SM1_EXECCTRL_STATUS_N_RESET _u(0x00) +#define PIO_SM1_EXECCTRL_STATUS_N_BITS _u(0x0000001f) +#define PIO_SM1_EXECCTRL_STATUS_N_MSB _u(4) +#define PIO_SM1_EXECCTRL_STATUS_N_LSB _u(0) +#define PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW" +#define PIO_SM1_EXECCTRL_STATUS_N_VALUE_IRQ _u(0x00) +#define PIO_SM1_EXECCTRL_STATUS_N_VALUE_IRQ_PREVPIO _u(0x08) +#define PIO_SM1_EXECCTRL_STATUS_N_VALUE_IRQ_NEXTPIO _u(0x10) +// ============================================================================= +// Register : PIO_SM1_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 1 +#define PIO_SM1_SHIFTCTRL_OFFSET _u(0x000000e8) +#define PIO_SM1_SHIFTCTRL_BITS _u(0xffffc01f) +#define PIO_SM1_SHIFTCTRL_RESET _u(0x000c0000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB _u(31) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB _u(30) +#define PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. +// Write 0 for value of 32. +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB _u(25) +#define PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. +// Write 0 for value of 32. +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB _u(20) +#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) +#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) +#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB _u(17) +#define PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB _u(16) +#define PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random write access by the state machine (using +// the `put` instruction) and, unless FJOIN_RX_GET is also set, +// random read access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_BITS _u(0x00008000) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_MSB _u(15) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_LSB _u(15) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_PUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_FJOIN_RX_GET +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random read access by the state machine (using +// the `get` instruction) and, unless FJOIN_RX_PUT is also set, +// random write access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_RESET _u(0x0) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_BITS _u(0x00004000) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_MSB _u(14) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_LSB _u(14) +#define PIO_SM1_SHIFTCTRL_FJOIN_RX_GET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_SHIFTCTRL_IN_COUNT +// Description : Set the number of pins which are not masked to 0 when read by +// an IN PINS, WAIT PIN or MOV x, PINS instruction. +// +// For example, an IN_COUNT of 5 means that the 5 LSBs of the IN +// pin group are visible (bits 4:0), but the remaining 27 MSBs are +// masked to 0. A count of 32 is encoded with a field value of 0, +// so the default behaviour is to not perform any masking. +// +// Note this masking is applied in addition to the masking usually +// performed by the IN instruction. This is mainly useful for the +// MOV x, PINS instruction, which otherwise has no way of masking +// pins. +#define PIO_SM1_SHIFTCTRL_IN_COUNT_RESET _u(0x00) +#define PIO_SM1_SHIFTCTRL_IN_COUNT_BITS _u(0x0000001f) +#define PIO_SM1_SHIFTCTRL_IN_COUNT_MSB _u(4) +#define PIO_SM1_SHIFTCTRL_IN_COUNT_LSB _u(0) +#define PIO_SM1_SHIFTCTRL_IN_COUNT_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_ADDR +// Description : Current instruction address of state machine 1 +#define PIO_SM1_ADDR_OFFSET _u(0x000000ec) +#define PIO_SM1_ADDR_BITS _u(0x0000001f) +#define PIO_SM1_ADDR_RESET _u(0x00000000) +#define PIO_SM1_ADDR_MSB _u(4) +#define PIO_SM1_ADDR_LSB _u(0) +#define PIO_SM1_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM1_INSTR +// Description : Read to see the instruction currently addressed by state +// machine 1's program counter +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM1_INSTR_OFFSET _u(0x000000f0) +#define PIO_SM1_INSTR_BITS _u(0x0000ffff) +#define PIO_SM1_INSTR_RESET "-" +#define PIO_SM1_INSTR_MSB _u(15) +#define PIO_SM1_INSTR_LSB _u(0) +#define PIO_SM1_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM1_PINCTRL +// Description : State machine pin control +#define PIO_SM1_PINCTRL_OFFSET _u(0x000000f4) +#define PIO_SM1_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM1_PINCTRL_RESET _u(0x14000000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SIDESET_COUNT +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB _u(29) +#define PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM1_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM1_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM1_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM1_PINCTRL_SET_COUNT_LSB _u(26) +#define PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM1_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM1_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM1_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM1_PINCTRL_OUT_COUNT_LSB _u(20) +#define PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_IN_BASE +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM1_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM1_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM1_PINCTRL_IN_BASE_LSB _u(15) +#define PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SIDESET_BASE +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. +#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM1_PINCTRL_SIDESET_BASE_LSB _u(10) +#define PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_SET_BASE +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM1_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM1_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM1_PINCTRL_SET_BASE_LSB _u(5) +#define PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM1_PINCTRL_OUT_BASE +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM1_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM1_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM1_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM1_PINCTRL_OUT_BASE_LSB _u(0) +#define PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_CLKDIV +// Description : Clock divisor register for state machine 2 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM2_CLKDIV_OFFSET _u(0x000000f8) +#define PIO_SM2_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM2_CLKDIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_CLKDIV_INT +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM2_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM2_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM2_CLKDIV_INT_MSB _u(31) +#define PIO_SM2_CLKDIV_INT_LSB _u(16) +#define PIO_SM2_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_CLKDIV_FRAC +// Description : Fractional part of clock divisor +#define PIO_SM2_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM2_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM2_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM2_CLKDIV_FRAC_LSB _u(8) +#define PIO_SM2_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_EXECCTRL +// Description : Execution/behavioural settings for state machine 2 +#define PIO_SM2_EXECCTRL_OFFSET _u(0x000000fc) +#define PIO_SM2_EXECCTRL_BITS _u(0xffffffff) +#define PIO_SM2_EXECCTRL_RESET _u(0x0001f000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_EXEC_STALLED +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB _u(31) +#define PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_SIDE_EN +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM2_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM2_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM2_EXECCTRL_SIDE_EN_LSB _u(30) +#define PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_SIDE_PINDIR +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB _u(29) +#define PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM2_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM2_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM2_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM2_EXECCTRL_JMP_PIN_LSB _u(24) +#define PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB _u(19) +#define PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB _u(18) +#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM2_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM2_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM2_EXECCTRL_OUT_STICKY_LSB _u(17) +#define PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM2_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM2_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM2_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM2_EXECCTRL_WRAP_TOP_LSB _u(12) +#define PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB _u(7) +#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes +#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) +#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(6) +#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(5) +#define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) +#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_IRQ _u(0x2) +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_EXECCTRL_STATUS_N +// Description : Comparison level or IRQ index for the MOV x, STATUS +// instruction. +// +// If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N +// greater than the current FIFO depth are reserved, and have +// undefined behaviour. +// 0x00 -> Index 0-7 of an IRQ flag in this PIO block +// 0x08 -> Index 0-7 of an IRQ flag in the next lower-numbered PIO block +// 0x10 -> Index 0-7 of an IRQ flag in the next higher-numbered PIO block +#define PIO_SM2_EXECCTRL_STATUS_N_RESET _u(0x00) +#define PIO_SM2_EXECCTRL_STATUS_N_BITS _u(0x0000001f) +#define PIO_SM2_EXECCTRL_STATUS_N_MSB _u(4) +#define PIO_SM2_EXECCTRL_STATUS_N_LSB _u(0) +#define PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW" +#define PIO_SM2_EXECCTRL_STATUS_N_VALUE_IRQ _u(0x00) +#define PIO_SM2_EXECCTRL_STATUS_N_VALUE_IRQ_PREVPIO _u(0x08) +#define PIO_SM2_EXECCTRL_STATUS_N_VALUE_IRQ_NEXTPIO _u(0x10) +// ============================================================================= +// Register : PIO_SM2_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 2 +#define PIO_SM2_SHIFTCTRL_OFFSET _u(0x00000100) +#define PIO_SM2_SHIFTCTRL_BITS _u(0xffffc01f) +#define PIO_SM2_SHIFTCTRL_RESET _u(0x000c0000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB _u(31) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB _u(30) +#define PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. +// Write 0 for value of 32. +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB _u(25) +#define PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. +// Write 0 for value of 32. +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB _u(20) +#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) +#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) +#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB _u(17) +#define PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB _u(16) +#define PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random write access by the state machine (using +// the `put` instruction) and, unless FJOIN_RX_GET is also set, +// random read access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_BITS _u(0x00008000) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_MSB _u(15) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_LSB _u(15) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_PUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_FJOIN_RX_GET +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random read access by the state machine (using +// the `get` instruction) and, unless FJOIN_RX_PUT is also set, +// random write access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_RESET _u(0x0) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_BITS _u(0x00004000) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_MSB _u(14) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_LSB _u(14) +#define PIO_SM2_SHIFTCTRL_FJOIN_RX_GET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_SHIFTCTRL_IN_COUNT +// Description : Set the number of pins which are not masked to 0 when read by +// an IN PINS, WAIT PIN or MOV x, PINS instruction. +// +// For example, an IN_COUNT of 5 means that the 5 LSBs of the IN +// pin group are visible (bits 4:0), but the remaining 27 MSBs are +// masked to 0. A count of 32 is encoded with a field value of 0, +// so the default behaviour is to not perform any masking. +// +// Note this masking is applied in addition to the masking usually +// performed by the IN instruction. This is mainly useful for the +// MOV x, PINS instruction, which otherwise has no way of masking +// pins. +#define PIO_SM2_SHIFTCTRL_IN_COUNT_RESET _u(0x00) +#define PIO_SM2_SHIFTCTRL_IN_COUNT_BITS _u(0x0000001f) +#define PIO_SM2_SHIFTCTRL_IN_COUNT_MSB _u(4) +#define PIO_SM2_SHIFTCTRL_IN_COUNT_LSB _u(0) +#define PIO_SM2_SHIFTCTRL_IN_COUNT_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_ADDR +// Description : Current instruction address of state machine 2 +#define PIO_SM2_ADDR_OFFSET _u(0x00000104) +#define PIO_SM2_ADDR_BITS _u(0x0000001f) +#define PIO_SM2_ADDR_RESET _u(0x00000000) +#define PIO_SM2_ADDR_MSB _u(4) +#define PIO_SM2_ADDR_LSB _u(0) +#define PIO_SM2_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM2_INSTR +// Description : Read to see the instruction currently addressed by state +// machine 2's program counter +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM2_INSTR_OFFSET _u(0x00000108) +#define PIO_SM2_INSTR_BITS _u(0x0000ffff) +#define PIO_SM2_INSTR_RESET "-" +#define PIO_SM2_INSTR_MSB _u(15) +#define PIO_SM2_INSTR_LSB _u(0) +#define PIO_SM2_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM2_PINCTRL +// Description : State machine pin control +#define PIO_SM2_PINCTRL_OFFSET _u(0x0000010c) +#define PIO_SM2_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM2_PINCTRL_RESET _u(0x14000000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SIDESET_COUNT +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB _u(29) +#define PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM2_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM2_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM2_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM2_PINCTRL_SET_COUNT_LSB _u(26) +#define PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM2_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM2_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM2_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM2_PINCTRL_OUT_COUNT_LSB _u(20) +#define PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_IN_BASE +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM2_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM2_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM2_PINCTRL_IN_BASE_LSB _u(15) +#define PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SIDESET_BASE +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. +#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM2_PINCTRL_SIDESET_BASE_LSB _u(10) +#define PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_SET_BASE +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM2_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM2_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM2_PINCTRL_SET_BASE_LSB _u(5) +#define PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM2_PINCTRL_OUT_BASE +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM2_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM2_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM2_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM2_PINCTRL_OUT_BASE_LSB _u(0) +#define PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_CLKDIV +// Description : Clock divisor register for state machine 3 +// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) +#define PIO_SM3_CLKDIV_OFFSET _u(0x00000110) +#define PIO_SM3_CLKDIV_BITS _u(0xffffff00) +#define PIO_SM3_CLKDIV_RESET _u(0x00010000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_CLKDIV_INT +// Description : Effective frequency is sysclk/(int + frac/256). +// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also +// be 0. +#define PIO_SM3_CLKDIV_INT_RESET _u(0x0001) +#define PIO_SM3_CLKDIV_INT_BITS _u(0xffff0000) +#define PIO_SM3_CLKDIV_INT_MSB _u(31) +#define PIO_SM3_CLKDIV_INT_LSB _u(16) +#define PIO_SM3_CLKDIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_CLKDIV_FRAC +// Description : Fractional part of clock divisor +#define PIO_SM3_CLKDIV_FRAC_RESET _u(0x00) +#define PIO_SM3_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PIO_SM3_CLKDIV_FRAC_MSB _u(15) +#define PIO_SM3_CLKDIV_FRAC_LSB _u(8) +#define PIO_SM3_CLKDIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_EXECCTRL +// Description : Execution/behavioural settings for state machine 3 +#define PIO_SM3_EXECCTRL_OFFSET _u(0x00000114) +#define PIO_SM3_EXECCTRL_BITS _u(0xffffffff) +#define PIO_SM3_EXECCTRL_RESET _u(0x0001f000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_EXEC_STALLED +// Description : If 1, an instruction written to SMx_INSTR is stalled, and +// latched by the state machine. Will clear to 0 once this +// instruction completes. +#define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB _u(31) +#define PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_SIDE_EN +// Description : If 1, the MSB of the Delay/Side-set instruction field is used +// as side-set enable, rather than a side-set data bit. This +// allows instructions to perform side-set optionally, rather than +// on every instruction, but the maximum possible side-set width +// is reduced from 5 to 4. Note that the value of +// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. +#define PIO_SM3_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PIO_SM3_EXECCTRL_SIDE_EN_MSB _u(30) +#define PIO_SM3_EXECCTRL_SIDE_EN_LSB _u(30) +#define PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_SIDE_PINDIR +// Description : If 1, side-set data is asserted to pin directions, instead of +// pin values +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB _u(29) +#define PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_JMP_PIN +// Description : The GPIO number to use as condition for JMP PIN. Unaffected by +// input mapping. +#define PIO_SM3_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PIO_SM3_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PIO_SM3_EXECCTRL_JMP_PIN_MSB _u(28) +#define PIO_SM3_EXECCTRL_JMP_PIN_LSB _u(24) +#define PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_OUT_EN_SEL +// Description : Which data bit to use for inline OUT enable +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB _u(19) +#define PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_INLINE_OUT_EN +// Description : If 1, use a bit of OUT data as an auxiliary write enable +// When used in conjunction with OUT_STICKY, writes with an enable +// of 0 will +// deassert the latest pin write. This can create useful +// masking/override behaviour +// due to the priority ordering of state machine pin writes (SM0 < +// SM1 < ...) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB _u(18) +#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_OUT_STICKY +// Description : Continuously assert the most recent OUT/SET to the pins +#define PIO_SM3_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PIO_SM3_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PIO_SM3_EXECCTRL_OUT_STICKY_LSB _u(17) +#define PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_WRAP_TOP +// Description : After reaching this address, execution is wrapped to +// wrap_bottom. +// If the instruction is a jump, and the jump condition is true, +// the jump takes priority. +#define PIO_SM3_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PIO_SM3_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PIO_SM3_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PIO_SM3_EXECCTRL_WRAP_TOP_LSB _u(12) +#define PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_WRAP_BOTTOM +// Description : After reaching wrap_top, execution is wrapped to this address. +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB _u(7) +#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_STATUS_SEL +// Description : Comparison used for the MOV x, STATUS instruction. +// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes +// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes +// 0x2 -> All-ones if the indexed IRQ flag is raised, otherwise all-zeroes +#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000060) +#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(6) +#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(5) +#define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) +#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) +#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_IRQ _u(0x2) +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_EXECCTRL_STATUS_N +// Description : Comparison level or IRQ index for the MOV x, STATUS +// instruction. +// +// If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N +// greater than the current FIFO depth are reserved, and have +// undefined behaviour. +// 0x00 -> Index 0-7 of an IRQ flag in this PIO block +// 0x08 -> Index 0-7 of an IRQ flag in the next lower-numbered PIO block +// 0x10 -> Index 0-7 of an IRQ flag in the next higher-numbered PIO block +#define PIO_SM3_EXECCTRL_STATUS_N_RESET _u(0x00) +#define PIO_SM3_EXECCTRL_STATUS_N_BITS _u(0x0000001f) +#define PIO_SM3_EXECCTRL_STATUS_N_MSB _u(4) +#define PIO_SM3_EXECCTRL_STATUS_N_LSB _u(0) +#define PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW" +#define PIO_SM3_EXECCTRL_STATUS_N_VALUE_IRQ _u(0x00) +#define PIO_SM3_EXECCTRL_STATUS_N_VALUE_IRQ_PREVPIO _u(0x08) +#define PIO_SM3_EXECCTRL_STATUS_N_VALUE_IRQ_NEXTPIO _u(0x10) +// ============================================================================= +// Register : PIO_SM3_SHIFTCTRL +// Description : Control behaviour of the input/output shift registers for state +// machine 3 +#define PIO_SM3_SHIFTCTRL_OFFSET _u(0x00000118) +#define PIO_SM3_SHIFTCTRL_BITS _u(0xffffc01f) +#define PIO_SM3_SHIFTCTRL_RESET _u(0x000c0000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_FJOIN_RX +// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice +// as deep. +// TX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB _u(31) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_FJOIN_TX +// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice +// as deep. +// RX FIFO is disabled as a result (always reads as both full and +// empty). +// FIFOs are flushed when this bit is changed. +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB _u(30) +#define PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_PULL_THRESH +// Description : Number of bits shifted out of OSR before autopull, or +// conditional pull (PULL IFEMPTY), will take place. +// Write 0 for value of 32. +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB _u(25) +#define PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_PUSH_THRESH +// Description : Number of bits shifted into ISR before autopush, or conditional +// push (PUSH IFFULL), will take place. +// Write 0 for value of 32. +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB _u(20) +#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR +// Description : 1 = shift out of output shift register to right. 0 = to left. +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) +#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_IN_SHIFTDIR +// Description : 1 = shift input shift register to right (data enters from +// left). 0 = to left. +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) +#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_AUTOPULL +// Description : Pull automatically when the output shift register is emptied, +// i.e. on or following an OUT instruction which causes the output +// shift counter to reach or exceed PULL_THRESH. +#define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB _u(17) +#define PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_AUTOPUSH +// Description : Push automatically when the input shift register is filled, +// i.e. on an IN instruction which causes the input shift counter +// to reach or exceed PUSH_THRESH. +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB _u(16) +#define PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random write access by the state machine (using +// the `put` instruction) and, unless FJOIN_RX_GET is also set, +// random read access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_BITS _u(0x00008000) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_MSB _u(15) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_LSB _u(15) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_PUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_FJOIN_RX_GET +// Description : If 1, disable this state machine's RX FIFO, make its storage +// available for random read access by the state machine (using +// the `get` instruction) and, unless FJOIN_RX_PUT is also set, +// random write access by the processor (through the RXFx_PUTGETy +// registers). +// +// If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX +// FIFO's registers can be randomly read/written by the state +// machine, but are completely inaccessible to the processor. +// +// Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_RESET _u(0x0) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_BITS _u(0x00004000) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_MSB _u(14) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_LSB _u(14) +#define PIO_SM3_SHIFTCTRL_FJOIN_RX_GET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_SHIFTCTRL_IN_COUNT +// Description : Set the number of pins which are not masked to 0 when read by +// an IN PINS, WAIT PIN or MOV x, PINS instruction. +// +// For example, an IN_COUNT of 5 means that the 5 LSBs of the IN +// pin group are visible (bits 4:0), but the remaining 27 MSBs are +// masked to 0. A count of 32 is encoded with a field value of 0, +// so the default behaviour is to not perform any masking. +// +// Note this masking is applied in addition to the masking usually +// performed by the IN instruction. This is mainly useful for the +// MOV x, PINS instruction, which otherwise has no way of masking +// pins. +#define PIO_SM3_SHIFTCTRL_IN_COUNT_RESET _u(0x00) +#define PIO_SM3_SHIFTCTRL_IN_COUNT_BITS _u(0x0000001f) +#define PIO_SM3_SHIFTCTRL_IN_COUNT_MSB _u(4) +#define PIO_SM3_SHIFTCTRL_IN_COUNT_LSB _u(0) +#define PIO_SM3_SHIFTCTRL_IN_COUNT_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_ADDR +// Description : Current instruction address of state machine 3 +#define PIO_SM3_ADDR_OFFSET _u(0x0000011c) +#define PIO_SM3_ADDR_BITS _u(0x0000001f) +#define PIO_SM3_ADDR_RESET _u(0x00000000) +#define PIO_SM3_ADDR_MSB _u(4) +#define PIO_SM3_ADDR_LSB _u(0) +#define PIO_SM3_ADDR_ACCESS "RO" +// ============================================================================= +// Register : PIO_SM3_INSTR +// Description : Read to see the instruction currently addressed by state +// machine 3's program counter +// Write to execute an instruction immediately (including jumps) +// and then resume execution. +#define PIO_SM3_INSTR_OFFSET _u(0x00000120) +#define PIO_SM3_INSTR_BITS _u(0x0000ffff) +#define PIO_SM3_INSTR_RESET "-" +#define PIO_SM3_INSTR_MSB _u(15) +#define PIO_SM3_INSTR_LSB _u(0) +#define PIO_SM3_INSTR_ACCESS "RW" +// ============================================================================= +// Register : PIO_SM3_PINCTRL +// Description : State machine pin control +#define PIO_SM3_PINCTRL_OFFSET _u(0x00000124) +#define PIO_SM3_PINCTRL_BITS _u(0xffffffff) +#define PIO_SM3_PINCTRL_RESET _u(0x14000000) +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SIDESET_COUNT +// Description : The number of MSBs of the Delay/Side-set instruction field +// which are used for side-set. Inclusive of the enable bit, if +// present. Minimum of 0 (all delay bits, no side-set) and maximum +// of 5 (all side-set, no delay). +#define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB _u(29) +#define PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SET_COUNT +// Description : The number of pins asserted by a SET. In the range 0 to 5 +// inclusive. +#define PIO_SM3_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PIO_SM3_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PIO_SM3_PINCTRL_SET_COUNT_MSB _u(28) +#define PIO_SM3_PINCTRL_SET_COUNT_LSB _u(26) +#define PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_OUT_COUNT +// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV +// PINS instruction. In the range 0 to 32 inclusive. +#define PIO_SM3_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PIO_SM3_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PIO_SM3_PINCTRL_OUT_COUNT_MSB _u(25) +#define PIO_SM3_PINCTRL_OUT_COUNT_LSB _u(20) +#define PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_IN_BASE +// Description : The pin which is mapped to the least-significant bit of a state +// machine's IN data bus. Higher-numbered pins are mapped to +// consecutively more-significant data bits, with a modulo of 32 +// applied to pin number. +#define PIO_SM3_PINCTRL_IN_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PIO_SM3_PINCTRL_IN_BASE_MSB _u(19) +#define PIO_SM3_PINCTRL_IN_BASE_LSB _u(15) +#define PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SIDESET_BASE +// Description : The lowest-numbered pin that will be affected by a side-set +// operation. The MSBs of an instruction's side-set/delay field +// (up to 5, determined by SIDESET_COUNT) are used for side-set +// data, with the remaining LSBs used for delay. The least- +// significant bit of the side-set portion is the bit written to +// this pin, with more-significant bits written to higher-numbered +// pins. +#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PIO_SM3_PINCTRL_SIDESET_BASE_LSB _u(10) +#define PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_SET_BASE +// Description : The lowest-numbered pin that will be affected by a SET PINS or +// SET PINDIRS instruction. The data written to this pin is the +// least-significant bit of the SET data. +#define PIO_SM3_PINCTRL_SET_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PIO_SM3_PINCTRL_SET_BASE_MSB _u(9) +#define PIO_SM3_PINCTRL_SET_BASE_LSB _u(5) +#define PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_SM3_PINCTRL_OUT_BASE +// Description : The lowest-numbered pin that will be affected by an OUT PINS, +// OUT PINDIRS or MOV PINS instruction. The data written to this +// pin will always be the least-significant bit of the OUT or MOV +// data. +#define PIO_SM3_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PIO_SM3_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PIO_SM3_PINCTRL_OUT_BASE_MSB _u(4) +#define PIO_SM3_PINCTRL_OUT_BASE_LSB _u(0) +#define PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF0_PUTGET0 +// Description : Direct read/write access to entry 0 of SM0's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF0_PUTGET0_OFFSET _u(0x00000128) +#define PIO_RXF0_PUTGET0_BITS _u(0xffffffff) +#define PIO_RXF0_PUTGET0_RESET _u(0x00000000) +#define PIO_RXF0_PUTGET0_MSB _u(31) +#define PIO_RXF0_PUTGET0_LSB _u(0) +#define PIO_RXF0_PUTGET0_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF0_PUTGET1 +// Description : Direct read/write access to entry 1 of SM0's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF0_PUTGET1_OFFSET _u(0x0000012c) +#define PIO_RXF0_PUTGET1_BITS _u(0xffffffff) +#define PIO_RXF0_PUTGET1_RESET _u(0x00000000) +#define PIO_RXF0_PUTGET1_MSB _u(31) +#define PIO_RXF0_PUTGET1_LSB _u(0) +#define PIO_RXF0_PUTGET1_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF0_PUTGET2 +// Description : Direct read/write access to entry 2 of SM0's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF0_PUTGET2_OFFSET _u(0x00000130) +#define PIO_RXF0_PUTGET2_BITS _u(0xffffffff) +#define PIO_RXF0_PUTGET2_RESET _u(0x00000000) +#define PIO_RXF0_PUTGET2_MSB _u(31) +#define PIO_RXF0_PUTGET2_LSB _u(0) +#define PIO_RXF0_PUTGET2_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF0_PUTGET3 +// Description : Direct read/write access to entry 3 of SM0's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF0_PUTGET3_OFFSET _u(0x00000134) +#define PIO_RXF0_PUTGET3_BITS _u(0xffffffff) +#define PIO_RXF0_PUTGET3_RESET _u(0x00000000) +#define PIO_RXF0_PUTGET3_MSB _u(31) +#define PIO_RXF0_PUTGET3_LSB _u(0) +#define PIO_RXF0_PUTGET3_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF1_PUTGET0 +// Description : Direct read/write access to entry 0 of SM1's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF1_PUTGET0_OFFSET _u(0x00000138) +#define PIO_RXF1_PUTGET0_BITS _u(0xffffffff) +#define PIO_RXF1_PUTGET0_RESET _u(0x00000000) +#define PIO_RXF1_PUTGET0_MSB _u(31) +#define PIO_RXF1_PUTGET0_LSB _u(0) +#define PIO_RXF1_PUTGET0_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF1_PUTGET1 +// Description : Direct read/write access to entry 1 of SM1's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF1_PUTGET1_OFFSET _u(0x0000013c) +#define PIO_RXF1_PUTGET1_BITS _u(0xffffffff) +#define PIO_RXF1_PUTGET1_RESET _u(0x00000000) +#define PIO_RXF1_PUTGET1_MSB _u(31) +#define PIO_RXF1_PUTGET1_LSB _u(0) +#define PIO_RXF1_PUTGET1_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF1_PUTGET2 +// Description : Direct read/write access to entry 2 of SM1's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF1_PUTGET2_OFFSET _u(0x00000140) +#define PIO_RXF1_PUTGET2_BITS _u(0xffffffff) +#define PIO_RXF1_PUTGET2_RESET _u(0x00000000) +#define PIO_RXF1_PUTGET2_MSB _u(31) +#define PIO_RXF1_PUTGET2_LSB _u(0) +#define PIO_RXF1_PUTGET2_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF1_PUTGET3 +// Description : Direct read/write access to entry 3 of SM1's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF1_PUTGET3_OFFSET _u(0x00000144) +#define PIO_RXF1_PUTGET3_BITS _u(0xffffffff) +#define PIO_RXF1_PUTGET3_RESET _u(0x00000000) +#define PIO_RXF1_PUTGET3_MSB _u(31) +#define PIO_RXF1_PUTGET3_LSB _u(0) +#define PIO_RXF1_PUTGET3_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF2_PUTGET0 +// Description : Direct read/write access to entry 0 of SM2's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF2_PUTGET0_OFFSET _u(0x00000148) +#define PIO_RXF2_PUTGET0_BITS _u(0xffffffff) +#define PIO_RXF2_PUTGET0_RESET _u(0x00000000) +#define PIO_RXF2_PUTGET0_MSB _u(31) +#define PIO_RXF2_PUTGET0_LSB _u(0) +#define PIO_RXF2_PUTGET0_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF2_PUTGET1 +// Description : Direct read/write access to entry 1 of SM2's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF2_PUTGET1_OFFSET _u(0x0000014c) +#define PIO_RXF2_PUTGET1_BITS _u(0xffffffff) +#define PIO_RXF2_PUTGET1_RESET _u(0x00000000) +#define PIO_RXF2_PUTGET1_MSB _u(31) +#define PIO_RXF2_PUTGET1_LSB _u(0) +#define PIO_RXF2_PUTGET1_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF2_PUTGET2 +// Description : Direct read/write access to entry 2 of SM2's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF2_PUTGET2_OFFSET _u(0x00000150) +#define PIO_RXF2_PUTGET2_BITS _u(0xffffffff) +#define PIO_RXF2_PUTGET2_RESET _u(0x00000000) +#define PIO_RXF2_PUTGET2_MSB _u(31) +#define PIO_RXF2_PUTGET2_LSB _u(0) +#define PIO_RXF2_PUTGET2_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF2_PUTGET3 +// Description : Direct read/write access to entry 3 of SM2's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF2_PUTGET3_OFFSET _u(0x00000154) +#define PIO_RXF2_PUTGET3_BITS _u(0xffffffff) +#define PIO_RXF2_PUTGET3_RESET _u(0x00000000) +#define PIO_RXF2_PUTGET3_MSB _u(31) +#define PIO_RXF2_PUTGET3_LSB _u(0) +#define PIO_RXF2_PUTGET3_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF3_PUTGET0 +// Description : Direct read/write access to entry 0 of SM3's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF3_PUTGET0_OFFSET _u(0x00000158) +#define PIO_RXF3_PUTGET0_BITS _u(0xffffffff) +#define PIO_RXF3_PUTGET0_RESET _u(0x00000000) +#define PIO_RXF3_PUTGET0_MSB _u(31) +#define PIO_RXF3_PUTGET0_LSB _u(0) +#define PIO_RXF3_PUTGET0_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF3_PUTGET1 +// Description : Direct read/write access to entry 1 of SM3's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF3_PUTGET1_OFFSET _u(0x0000015c) +#define PIO_RXF3_PUTGET1_BITS _u(0xffffffff) +#define PIO_RXF3_PUTGET1_RESET _u(0x00000000) +#define PIO_RXF3_PUTGET1_MSB _u(31) +#define PIO_RXF3_PUTGET1_LSB _u(0) +#define PIO_RXF3_PUTGET1_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF3_PUTGET2 +// Description : Direct read/write access to entry 2 of SM3's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF3_PUTGET2_OFFSET _u(0x00000160) +#define PIO_RXF3_PUTGET2_BITS _u(0xffffffff) +#define PIO_RXF3_PUTGET2_RESET _u(0x00000000) +#define PIO_RXF3_PUTGET2_MSB _u(31) +#define PIO_RXF3_PUTGET2_LSB _u(0) +#define PIO_RXF3_PUTGET2_ACCESS "RW" +// ============================================================================= +// Register : PIO_RXF3_PUTGET3 +// Description : Direct read/write access to entry 3 of SM3's RX FIFO, if +// SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. +#define PIO_RXF3_PUTGET3_OFFSET _u(0x00000164) +#define PIO_RXF3_PUTGET3_BITS _u(0xffffffff) +#define PIO_RXF3_PUTGET3_RESET _u(0x00000000) +#define PIO_RXF3_PUTGET3_MSB _u(31) +#define PIO_RXF3_PUTGET3_LSB _u(0) +#define PIO_RXF3_PUTGET3_ACCESS "RW" +// ============================================================================= +// Register : PIO_GPIOBASE +// Description : Relocate GPIO 0 (from PIO's point of view) in the system GPIO +// numbering, to access more than 32 GPIOs from PIO. +// +// Only the values 0 and 16 are supported (only bit 4 is +// writable). +#define PIO_GPIOBASE_OFFSET _u(0x00000168) +#define PIO_GPIOBASE_BITS _u(0x00000010) +#define PIO_GPIOBASE_RESET _u(0x00000000) +#define PIO_GPIOBASE_MSB _u(4) +#define PIO_GPIOBASE_LSB _u(4) +#define PIO_GPIOBASE_ACCESS "RW" +// ============================================================================= +// Register : PIO_INTR +// Description : Raw Interrupts +#define PIO_INTR_OFFSET _u(0x0000016c) +#define PIO_INTR_BITS _u(0x0000ffff) +#define PIO_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM7 +#define PIO_INTR_SM7_RESET _u(0x0) +#define PIO_INTR_SM7_BITS _u(0x00008000) +#define PIO_INTR_SM7_MSB _u(15) +#define PIO_INTR_SM7_LSB _u(15) +#define PIO_INTR_SM7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM6 +#define PIO_INTR_SM6_RESET _u(0x0) +#define PIO_INTR_SM6_BITS _u(0x00004000) +#define PIO_INTR_SM6_MSB _u(14) +#define PIO_INTR_SM6_LSB _u(14) +#define PIO_INTR_SM6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM5 +#define PIO_INTR_SM5_RESET _u(0x0) +#define PIO_INTR_SM5_BITS _u(0x00002000) +#define PIO_INTR_SM5_MSB _u(13) +#define PIO_INTR_SM5_LSB _u(13) +#define PIO_INTR_SM5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM4 +#define PIO_INTR_SM4_RESET _u(0x0) +#define PIO_INTR_SM4_BITS _u(0x00001000) +#define PIO_INTR_SM4_MSB _u(12) +#define PIO_INTR_SM4_LSB _u(12) +#define PIO_INTR_SM4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM3 +#define PIO_INTR_SM3_RESET _u(0x0) +#define PIO_INTR_SM3_BITS _u(0x00000800) +#define PIO_INTR_SM3_MSB _u(11) +#define PIO_INTR_SM3_LSB _u(11) +#define PIO_INTR_SM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM2 +#define PIO_INTR_SM2_RESET _u(0x0) +#define PIO_INTR_SM2_BITS _u(0x00000400) +#define PIO_INTR_SM2_MSB _u(10) +#define PIO_INTR_SM2_LSB _u(10) +#define PIO_INTR_SM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM1 +#define PIO_INTR_SM1_RESET _u(0x0) +#define PIO_INTR_SM1_BITS _u(0x00000200) +#define PIO_INTR_SM1_MSB _u(9) +#define PIO_INTR_SM1_LSB _u(9) +#define PIO_INTR_SM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM0 +#define PIO_INTR_SM0_RESET _u(0x0) +#define PIO_INTR_SM0_BITS _u(0x00000100) +#define PIO_INTR_SM0_MSB _u(8) +#define PIO_INTR_SM0_LSB _u(8) +#define PIO_INTR_SM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM3_TXNFULL +#define PIO_INTR_SM3_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_INTR_SM3_TXNFULL_MSB _u(7) +#define PIO_INTR_SM3_TXNFULL_LSB _u(7) +#define PIO_INTR_SM3_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM2_TXNFULL +#define PIO_INTR_SM2_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_INTR_SM2_TXNFULL_MSB _u(6) +#define PIO_INTR_SM2_TXNFULL_LSB _u(6) +#define PIO_INTR_SM2_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM1_TXNFULL +#define PIO_INTR_SM1_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_INTR_SM1_TXNFULL_MSB _u(5) +#define PIO_INTR_SM1_TXNFULL_LSB _u(5) +#define PIO_INTR_SM1_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM0_TXNFULL +#define PIO_INTR_SM0_TXNFULL_RESET _u(0x0) +#define PIO_INTR_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_INTR_SM0_TXNFULL_MSB _u(4) +#define PIO_INTR_SM0_TXNFULL_LSB _u(4) +#define PIO_INTR_SM0_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM3_RXNEMPTY +#define PIO_INTR_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_INTR_SM3_RXNEMPTY_MSB _u(3) +#define PIO_INTR_SM3_RXNEMPTY_LSB _u(3) +#define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM2_RXNEMPTY +#define PIO_INTR_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_INTR_SM2_RXNEMPTY_MSB _u(2) +#define PIO_INTR_SM2_RXNEMPTY_LSB _u(2) +#define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM1_RXNEMPTY +#define PIO_INTR_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_INTR_SM1_RXNEMPTY_MSB _u(1) +#define PIO_INTR_SM1_RXNEMPTY_LSB _u(1) +#define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_INTR_SM0_RXNEMPTY +#define PIO_INTR_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_INTR_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_INTR_SM0_RXNEMPTY_MSB _u(0) +#define PIO_INTR_SM0_RXNEMPTY_LSB _u(0) +#define PIO_INTR_SM0_RXNEMPTY_ACCESS "RO" +// ============================================================================= +// Register : PIO_IRQ0_INTE +// Description : Interrupt Enable for irq0 +#define PIO_IRQ0_INTE_OFFSET _u(0x00000170) +#define PIO_IRQ0_INTE_BITS _u(0x0000ffff) +#define PIO_IRQ0_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM7 +#define PIO_IRQ0_INTE_SM7_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM7_BITS _u(0x00008000) +#define PIO_IRQ0_INTE_SM7_MSB _u(15) +#define PIO_IRQ0_INTE_SM7_LSB _u(15) +#define PIO_IRQ0_INTE_SM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM6 +#define PIO_IRQ0_INTE_SM6_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM6_BITS _u(0x00004000) +#define PIO_IRQ0_INTE_SM6_MSB _u(14) +#define PIO_IRQ0_INTE_SM6_LSB _u(14) +#define PIO_IRQ0_INTE_SM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM5 +#define PIO_IRQ0_INTE_SM5_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM5_BITS _u(0x00002000) +#define PIO_IRQ0_INTE_SM5_MSB _u(13) +#define PIO_IRQ0_INTE_SM5_LSB _u(13) +#define PIO_IRQ0_INTE_SM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM4 +#define PIO_IRQ0_INTE_SM4_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM4_BITS _u(0x00001000) +#define PIO_IRQ0_INTE_SM4_MSB _u(12) +#define PIO_IRQ0_INTE_SM4_LSB _u(12) +#define PIO_IRQ0_INTE_SM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM3 +#define PIO_IRQ0_INTE_SM3_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM3_BITS _u(0x00000800) +#define PIO_IRQ0_INTE_SM3_MSB _u(11) +#define PIO_IRQ0_INTE_SM3_LSB _u(11) +#define PIO_IRQ0_INTE_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM2 +#define PIO_IRQ0_INTE_SM2_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM2_BITS _u(0x00000400) +#define PIO_IRQ0_INTE_SM2_MSB _u(10) +#define PIO_IRQ0_INTE_SM2_LSB _u(10) +#define PIO_IRQ0_INTE_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM1 +#define PIO_IRQ0_INTE_SM1_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM1_BITS _u(0x00000200) +#define PIO_IRQ0_INTE_SM1_MSB _u(9) +#define PIO_IRQ0_INTE_SM1_LSB _u(9) +#define PIO_IRQ0_INTE_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM0 +#define PIO_IRQ0_INTE_SM0_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM0_BITS _u(0x00000100) +#define PIO_IRQ0_INTE_SM0_MSB _u(8) +#define PIO_IRQ0_INTE_SM0_LSB _u(8) +#define PIO_IRQ0_INTE_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM3_TXNFULL +#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ0_INTE_SM3_TXNFULL_LSB _u(7) +#define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM2_TXNFULL +#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ0_INTE_SM2_TXNFULL_LSB _u(6) +#define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM1_TXNFULL +#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ0_INTE_SM1_TXNFULL_LSB _u(5) +#define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM0_TXNFULL +#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ0_INTE_SM0_TXNFULL_LSB _u(4) +#define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM3_RXNEMPTY +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB _u(3) +#define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM2_RXNEMPTY +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB _u(2) +#define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM1_RXNEMPTY +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB _u(1) +#define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTE_SM0_RXNEMPTY +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB _u(0) +#define PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ0_INTF +// Description : Interrupt Force for irq0 +#define PIO_IRQ0_INTF_OFFSET _u(0x00000174) +#define PIO_IRQ0_INTF_BITS _u(0x0000ffff) +#define PIO_IRQ0_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM7 +#define PIO_IRQ0_INTF_SM7_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM7_BITS _u(0x00008000) +#define PIO_IRQ0_INTF_SM7_MSB _u(15) +#define PIO_IRQ0_INTF_SM7_LSB _u(15) +#define PIO_IRQ0_INTF_SM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM6 +#define PIO_IRQ0_INTF_SM6_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM6_BITS _u(0x00004000) +#define PIO_IRQ0_INTF_SM6_MSB _u(14) +#define PIO_IRQ0_INTF_SM6_LSB _u(14) +#define PIO_IRQ0_INTF_SM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM5 +#define PIO_IRQ0_INTF_SM5_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM5_BITS _u(0x00002000) +#define PIO_IRQ0_INTF_SM5_MSB _u(13) +#define PIO_IRQ0_INTF_SM5_LSB _u(13) +#define PIO_IRQ0_INTF_SM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM4 +#define PIO_IRQ0_INTF_SM4_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM4_BITS _u(0x00001000) +#define PIO_IRQ0_INTF_SM4_MSB _u(12) +#define PIO_IRQ0_INTF_SM4_LSB _u(12) +#define PIO_IRQ0_INTF_SM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM3 +#define PIO_IRQ0_INTF_SM3_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM3_BITS _u(0x00000800) +#define PIO_IRQ0_INTF_SM3_MSB _u(11) +#define PIO_IRQ0_INTF_SM3_LSB _u(11) +#define PIO_IRQ0_INTF_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM2 +#define PIO_IRQ0_INTF_SM2_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM2_BITS _u(0x00000400) +#define PIO_IRQ0_INTF_SM2_MSB _u(10) +#define PIO_IRQ0_INTF_SM2_LSB _u(10) +#define PIO_IRQ0_INTF_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM1 +#define PIO_IRQ0_INTF_SM1_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM1_BITS _u(0x00000200) +#define PIO_IRQ0_INTF_SM1_MSB _u(9) +#define PIO_IRQ0_INTF_SM1_LSB _u(9) +#define PIO_IRQ0_INTF_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM0 +#define PIO_IRQ0_INTF_SM0_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM0_BITS _u(0x00000100) +#define PIO_IRQ0_INTF_SM0_MSB _u(8) +#define PIO_IRQ0_INTF_SM0_LSB _u(8) +#define PIO_IRQ0_INTF_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM3_TXNFULL +#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ0_INTF_SM3_TXNFULL_LSB _u(7) +#define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM2_TXNFULL +#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ0_INTF_SM2_TXNFULL_LSB _u(6) +#define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM1_TXNFULL +#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ0_INTF_SM1_TXNFULL_LSB _u(5) +#define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM0_TXNFULL +#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ0_INTF_SM0_TXNFULL_LSB _u(4) +#define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM3_RXNEMPTY +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB _u(3) +#define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM2_RXNEMPTY +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB _u(2) +#define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM1_RXNEMPTY +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB _u(1) +#define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTF_SM0_RXNEMPTY +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB _u(0) +#define PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ0_INTS +// Description : Interrupt status after masking & forcing for irq0 +#define PIO_IRQ0_INTS_OFFSET _u(0x00000178) +#define PIO_IRQ0_INTS_BITS _u(0x0000ffff) +#define PIO_IRQ0_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM7 +#define PIO_IRQ0_INTS_SM7_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM7_BITS _u(0x00008000) +#define PIO_IRQ0_INTS_SM7_MSB _u(15) +#define PIO_IRQ0_INTS_SM7_LSB _u(15) +#define PIO_IRQ0_INTS_SM7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM6 +#define PIO_IRQ0_INTS_SM6_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM6_BITS _u(0x00004000) +#define PIO_IRQ0_INTS_SM6_MSB _u(14) +#define PIO_IRQ0_INTS_SM6_LSB _u(14) +#define PIO_IRQ0_INTS_SM6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM5 +#define PIO_IRQ0_INTS_SM5_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM5_BITS _u(0x00002000) +#define PIO_IRQ0_INTS_SM5_MSB _u(13) +#define PIO_IRQ0_INTS_SM5_LSB _u(13) +#define PIO_IRQ0_INTS_SM5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM4 +#define PIO_IRQ0_INTS_SM4_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM4_BITS _u(0x00001000) +#define PIO_IRQ0_INTS_SM4_MSB _u(12) +#define PIO_IRQ0_INTS_SM4_LSB _u(12) +#define PIO_IRQ0_INTS_SM4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM3 +#define PIO_IRQ0_INTS_SM3_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM3_BITS _u(0x00000800) +#define PIO_IRQ0_INTS_SM3_MSB _u(11) +#define PIO_IRQ0_INTS_SM3_LSB _u(11) +#define PIO_IRQ0_INTS_SM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM2 +#define PIO_IRQ0_INTS_SM2_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM2_BITS _u(0x00000400) +#define PIO_IRQ0_INTS_SM2_MSB _u(10) +#define PIO_IRQ0_INTS_SM2_LSB _u(10) +#define PIO_IRQ0_INTS_SM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM1 +#define PIO_IRQ0_INTS_SM1_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM1_BITS _u(0x00000200) +#define PIO_IRQ0_INTS_SM1_MSB _u(9) +#define PIO_IRQ0_INTS_SM1_LSB _u(9) +#define PIO_IRQ0_INTS_SM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM0 +#define PIO_IRQ0_INTS_SM0_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM0_BITS _u(0x00000100) +#define PIO_IRQ0_INTS_SM0_MSB _u(8) +#define PIO_IRQ0_INTS_SM0_LSB _u(8) +#define PIO_IRQ0_INTS_SM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM3_TXNFULL +#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ0_INTS_SM3_TXNFULL_LSB _u(7) +#define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM2_TXNFULL +#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ0_INTS_SM2_TXNFULL_LSB _u(6) +#define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM1_TXNFULL +#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ0_INTS_SM1_TXNFULL_LSB _u(5) +#define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM0_TXNFULL +#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ0_INTS_SM0_TXNFULL_LSB _u(4) +#define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM3_RXNEMPTY +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB _u(3) +#define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM2_RXNEMPTY +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB _u(2) +#define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM1_RXNEMPTY +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB _u(1) +#define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ0_INTS_SM0_RXNEMPTY +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB _u(0) +#define PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO" +// ============================================================================= +// Register : PIO_IRQ1_INTE +// Description : Interrupt Enable for irq1 +#define PIO_IRQ1_INTE_OFFSET _u(0x0000017c) +#define PIO_IRQ1_INTE_BITS _u(0x0000ffff) +#define PIO_IRQ1_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM7 +#define PIO_IRQ1_INTE_SM7_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM7_BITS _u(0x00008000) +#define PIO_IRQ1_INTE_SM7_MSB _u(15) +#define PIO_IRQ1_INTE_SM7_LSB _u(15) +#define PIO_IRQ1_INTE_SM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM6 +#define PIO_IRQ1_INTE_SM6_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM6_BITS _u(0x00004000) +#define PIO_IRQ1_INTE_SM6_MSB _u(14) +#define PIO_IRQ1_INTE_SM6_LSB _u(14) +#define PIO_IRQ1_INTE_SM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM5 +#define PIO_IRQ1_INTE_SM5_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM5_BITS _u(0x00002000) +#define PIO_IRQ1_INTE_SM5_MSB _u(13) +#define PIO_IRQ1_INTE_SM5_LSB _u(13) +#define PIO_IRQ1_INTE_SM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM4 +#define PIO_IRQ1_INTE_SM4_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM4_BITS _u(0x00001000) +#define PIO_IRQ1_INTE_SM4_MSB _u(12) +#define PIO_IRQ1_INTE_SM4_LSB _u(12) +#define PIO_IRQ1_INTE_SM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM3 +#define PIO_IRQ1_INTE_SM3_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM3_BITS _u(0x00000800) +#define PIO_IRQ1_INTE_SM3_MSB _u(11) +#define PIO_IRQ1_INTE_SM3_LSB _u(11) +#define PIO_IRQ1_INTE_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM2 +#define PIO_IRQ1_INTE_SM2_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM2_BITS _u(0x00000400) +#define PIO_IRQ1_INTE_SM2_MSB _u(10) +#define PIO_IRQ1_INTE_SM2_LSB _u(10) +#define PIO_IRQ1_INTE_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM1 +#define PIO_IRQ1_INTE_SM1_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM1_BITS _u(0x00000200) +#define PIO_IRQ1_INTE_SM1_MSB _u(9) +#define PIO_IRQ1_INTE_SM1_LSB _u(9) +#define PIO_IRQ1_INTE_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM0 +#define PIO_IRQ1_INTE_SM0_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM0_BITS _u(0x00000100) +#define PIO_IRQ1_INTE_SM0_MSB _u(8) +#define PIO_IRQ1_INTE_SM0_LSB _u(8) +#define PIO_IRQ1_INTE_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM3_TXNFULL +#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ1_INTE_SM3_TXNFULL_LSB _u(7) +#define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM2_TXNFULL +#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ1_INTE_SM2_TXNFULL_LSB _u(6) +#define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM1_TXNFULL +#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ1_INTE_SM1_TXNFULL_LSB _u(5) +#define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM0_TXNFULL +#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ1_INTE_SM0_TXNFULL_LSB _u(4) +#define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM3_RXNEMPTY +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB _u(3) +#define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM2_RXNEMPTY +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB _u(2) +#define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM1_RXNEMPTY +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB _u(1) +#define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTE_SM0_RXNEMPTY +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB _u(0) +#define PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ1_INTF +// Description : Interrupt Force for irq1 +#define PIO_IRQ1_INTF_OFFSET _u(0x00000180) +#define PIO_IRQ1_INTF_BITS _u(0x0000ffff) +#define PIO_IRQ1_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM7 +#define PIO_IRQ1_INTF_SM7_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM7_BITS _u(0x00008000) +#define PIO_IRQ1_INTF_SM7_MSB _u(15) +#define PIO_IRQ1_INTF_SM7_LSB _u(15) +#define PIO_IRQ1_INTF_SM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM6 +#define PIO_IRQ1_INTF_SM6_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM6_BITS _u(0x00004000) +#define PIO_IRQ1_INTF_SM6_MSB _u(14) +#define PIO_IRQ1_INTF_SM6_LSB _u(14) +#define PIO_IRQ1_INTF_SM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM5 +#define PIO_IRQ1_INTF_SM5_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM5_BITS _u(0x00002000) +#define PIO_IRQ1_INTF_SM5_MSB _u(13) +#define PIO_IRQ1_INTF_SM5_LSB _u(13) +#define PIO_IRQ1_INTF_SM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM4 +#define PIO_IRQ1_INTF_SM4_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM4_BITS _u(0x00001000) +#define PIO_IRQ1_INTF_SM4_MSB _u(12) +#define PIO_IRQ1_INTF_SM4_LSB _u(12) +#define PIO_IRQ1_INTF_SM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM3 +#define PIO_IRQ1_INTF_SM3_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM3_BITS _u(0x00000800) +#define PIO_IRQ1_INTF_SM3_MSB _u(11) +#define PIO_IRQ1_INTF_SM3_LSB _u(11) +#define PIO_IRQ1_INTF_SM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM2 +#define PIO_IRQ1_INTF_SM2_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM2_BITS _u(0x00000400) +#define PIO_IRQ1_INTF_SM2_MSB _u(10) +#define PIO_IRQ1_INTF_SM2_LSB _u(10) +#define PIO_IRQ1_INTF_SM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM1 +#define PIO_IRQ1_INTF_SM1_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM1_BITS _u(0x00000200) +#define PIO_IRQ1_INTF_SM1_MSB _u(9) +#define PIO_IRQ1_INTF_SM1_LSB _u(9) +#define PIO_IRQ1_INTF_SM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM0 +#define PIO_IRQ1_INTF_SM0_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM0_BITS _u(0x00000100) +#define PIO_IRQ1_INTF_SM0_MSB _u(8) +#define PIO_IRQ1_INTF_SM0_LSB _u(8) +#define PIO_IRQ1_INTF_SM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM3_TXNFULL +#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ1_INTF_SM3_TXNFULL_LSB _u(7) +#define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM2_TXNFULL +#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ1_INTF_SM2_TXNFULL_LSB _u(6) +#define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM1_TXNFULL +#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ1_INTF_SM1_TXNFULL_LSB _u(5) +#define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM0_TXNFULL +#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ1_INTF_SM0_TXNFULL_LSB _u(4) +#define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM3_RXNEMPTY +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB _u(3) +#define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM2_RXNEMPTY +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB _u(2) +#define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM1_RXNEMPTY +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB _u(1) +#define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTF_SM0_RXNEMPTY +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB _u(0) +#define PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW" +// ============================================================================= +// Register : PIO_IRQ1_INTS +// Description : Interrupt status after masking & forcing for irq1 +#define PIO_IRQ1_INTS_OFFSET _u(0x00000184) +#define PIO_IRQ1_INTS_BITS _u(0x0000ffff) +#define PIO_IRQ1_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM7 +#define PIO_IRQ1_INTS_SM7_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM7_BITS _u(0x00008000) +#define PIO_IRQ1_INTS_SM7_MSB _u(15) +#define PIO_IRQ1_INTS_SM7_LSB _u(15) +#define PIO_IRQ1_INTS_SM7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM6 +#define PIO_IRQ1_INTS_SM6_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM6_BITS _u(0x00004000) +#define PIO_IRQ1_INTS_SM6_MSB _u(14) +#define PIO_IRQ1_INTS_SM6_LSB _u(14) +#define PIO_IRQ1_INTS_SM6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM5 +#define PIO_IRQ1_INTS_SM5_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM5_BITS _u(0x00002000) +#define PIO_IRQ1_INTS_SM5_MSB _u(13) +#define PIO_IRQ1_INTS_SM5_LSB _u(13) +#define PIO_IRQ1_INTS_SM5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM4 +#define PIO_IRQ1_INTS_SM4_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM4_BITS _u(0x00001000) +#define PIO_IRQ1_INTS_SM4_MSB _u(12) +#define PIO_IRQ1_INTS_SM4_LSB _u(12) +#define PIO_IRQ1_INTS_SM4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM3 +#define PIO_IRQ1_INTS_SM3_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM3_BITS _u(0x00000800) +#define PIO_IRQ1_INTS_SM3_MSB _u(11) +#define PIO_IRQ1_INTS_SM3_LSB _u(11) +#define PIO_IRQ1_INTS_SM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM2 +#define PIO_IRQ1_INTS_SM2_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM2_BITS _u(0x00000400) +#define PIO_IRQ1_INTS_SM2_MSB _u(10) +#define PIO_IRQ1_INTS_SM2_LSB _u(10) +#define PIO_IRQ1_INTS_SM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM1 +#define PIO_IRQ1_INTS_SM1_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM1_BITS _u(0x00000200) +#define PIO_IRQ1_INTS_SM1_MSB _u(9) +#define PIO_IRQ1_INTS_SM1_LSB _u(9) +#define PIO_IRQ1_INTS_SM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM0 +#define PIO_IRQ1_INTS_SM0_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM0_BITS _u(0x00000100) +#define PIO_IRQ1_INTS_SM0_MSB _u(8) +#define PIO_IRQ1_INTS_SM0_LSB _u(8) +#define PIO_IRQ1_INTS_SM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM3_TXNFULL +#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS _u(0x00000080) +#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB _u(7) +#define PIO_IRQ1_INTS_SM3_TXNFULL_LSB _u(7) +#define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM2_TXNFULL +#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS _u(0x00000040) +#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB _u(6) +#define PIO_IRQ1_INTS_SM2_TXNFULL_LSB _u(6) +#define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM1_TXNFULL +#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS _u(0x00000020) +#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB _u(5) +#define PIO_IRQ1_INTS_SM1_TXNFULL_LSB _u(5) +#define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM0_TXNFULL +#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS _u(0x00000010) +#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB _u(4) +#define PIO_IRQ1_INTS_SM0_TXNFULL_LSB _u(4) +#define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM3_RXNEMPTY +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _u(3) +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB _u(3) +#define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM2_RXNEMPTY +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _u(2) +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB _u(2) +#define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM1_RXNEMPTY +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _u(1) +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB _u(1) +#define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PIO_IRQ1_INTS_SM0_RXNEMPTY +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _u(0x0) +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _u(0) +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _u(0) +#define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_PIO_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/pll.h b/lib/pico-sdk/rp2350/hardware/regs/pll.h new file mode 100644 index 000000000000..fdf254d15f14 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/pll.h @@ -0,0 +1,199 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PLL +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_PLL_H +#define _HARDWARE_REGS_PLL_H +// ============================================================================= +// Register : PLL_CS +// Description : Control and Status +// GENERAL CONSTRAINTS: +// Reference clock frequency min=5MHz, max=800MHz +// Feedback divider min=16, max=320 +// VCO frequency min=750MHz, max=1600MHz +#define PLL_CS_OFFSET _u(0x00000000) +#define PLL_CS_BITS _u(0xc000013f) +#define PLL_CS_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : PLL_CS_LOCK +// Description : PLL is locked +#define PLL_CS_LOCK_RESET _u(0x0) +#define PLL_CS_LOCK_BITS _u(0x80000000) +#define PLL_CS_LOCK_MSB _u(31) +#define PLL_CS_LOCK_LSB _u(31) +#define PLL_CS_LOCK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PLL_CS_LOCK_N +// Description : PLL is not locked +// Ideally this is cleared when PLL lock is seen and this should +// never normally be set +#define PLL_CS_LOCK_N_RESET _u(0x0) +#define PLL_CS_LOCK_N_BITS _u(0x40000000) +#define PLL_CS_LOCK_N_MSB _u(30) +#define PLL_CS_LOCK_N_LSB _u(30) +#define PLL_CS_LOCK_N_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PLL_CS_BYPASS +// Description : Passes the reference clock to the output instead of the divided +// VCO. The VCO continues to run so the user can switch between +// the reference clock and the divided VCO but the output will +// glitch when doing so. +#define PLL_CS_BYPASS_RESET _u(0x0) +#define PLL_CS_BYPASS_BITS _u(0x00000100) +#define PLL_CS_BYPASS_MSB _u(8) +#define PLL_CS_BYPASS_LSB _u(8) +#define PLL_CS_BYPASS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_CS_REFDIV +// Description : Divides the PLL input reference clock. +// Behaviour is undefined for div=0. +// PLL output will be unpredictable during refdiv changes, wait +// for lock=1 before using it. +#define PLL_CS_REFDIV_RESET _u(0x01) +#define PLL_CS_REFDIV_BITS _u(0x0000003f) +#define PLL_CS_REFDIV_MSB _u(5) +#define PLL_CS_REFDIV_LSB _u(0) +#define PLL_CS_REFDIV_ACCESS "RW" +// ============================================================================= +// Register : PLL_PWR +// Description : Controls the PLL power modes. +#define PLL_PWR_OFFSET _u(0x00000004) +#define PLL_PWR_BITS _u(0x0000002d) +#define PLL_PWR_RESET _u(0x0000002d) +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_VCOPD +// Description : PLL VCO powerdown +// To save power set high when PLL output not required or +// bypass=1. +#define PLL_PWR_VCOPD_RESET _u(0x1) +#define PLL_PWR_VCOPD_BITS _u(0x00000020) +#define PLL_PWR_VCOPD_MSB _u(5) +#define PLL_PWR_VCOPD_LSB _u(5) +#define PLL_PWR_VCOPD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_POSTDIVPD +// Description : PLL post divider powerdown +// To save power set high when PLL output not required or +// bypass=1. +#define PLL_PWR_POSTDIVPD_RESET _u(0x1) +#define PLL_PWR_POSTDIVPD_BITS _u(0x00000008) +#define PLL_PWR_POSTDIVPD_MSB _u(3) +#define PLL_PWR_POSTDIVPD_LSB _u(3) +#define PLL_PWR_POSTDIVPD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_DSMPD +// Description : PLL DSM powerdown +// Nothing is achieved by setting this low. +#define PLL_PWR_DSMPD_RESET _u(0x1) +#define PLL_PWR_DSMPD_BITS _u(0x00000004) +#define PLL_PWR_DSMPD_MSB _u(2) +#define PLL_PWR_DSMPD_LSB _u(2) +#define PLL_PWR_DSMPD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PWR_PD +// Description : PLL powerdown +// To save power set high when PLL output not required. +#define PLL_PWR_PD_RESET _u(0x1) +#define PLL_PWR_PD_BITS _u(0x00000001) +#define PLL_PWR_PD_MSB _u(0) +#define PLL_PWR_PD_LSB _u(0) +#define PLL_PWR_PD_ACCESS "RW" +// ============================================================================= +// Register : PLL_FBDIV_INT +// Description : Feedback divisor +// (note: this PLL does not support fractional division) +// see ctrl reg description for constraints +#define PLL_FBDIV_INT_OFFSET _u(0x00000008) +#define PLL_FBDIV_INT_BITS _u(0x00000fff) +#define PLL_FBDIV_INT_RESET _u(0x00000000) +#define PLL_FBDIV_INT_MSB _u(11) +#define PLL_FBDIV_INT_LSB _u(0) +#define PLL_FBDIV_INT_ACCESS "RW" +// ============================================================================= +// Register : PLL_PRIM +// Description : Controls the PLL post dividers for the primary output +// (note: this PLL does not have a secondary output) +// the primary output is driven from VCO divided by +// postdiv1*postdiv2 +#define PLL_PRIM_OFFSET _u(0x0000000c) +#define PLL_PRIM_BITS _u(0x00077000) +#define PLL_PRIM_RESET _u(0x00077000) +// ----------------------------------------------------------------------------- +// Field : PLL_PRIM_POSTDIV1 +// Description : divide by 1-7 +#define PLL_PRIM_POSTDIV1_RESET _u(0x7) +#define PLL_PRIM_POSTDIV1_BITS _u(0x00070000) +#define PLL_PRIM_POSTDIV1_MSB _u(18) +#define PLL_PRIM_POSTDIV1_LSB _u(16) +#define PLL_PRIM_POSTDIV1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PLL_PRIM_POSTDIV2 +// Description : divide by 1-7 +#define PLL_PRIM_POSTDIV2_RESET _u(0x7) +#define PLL_PRIM_POSTDIV2_BITS _u(0x00007000) +#define PLL_PRIM_POSTDIV2_MSB _u(14) +#define PLL_PRIM_POSTDIV2_LSB _u(12) +#define PLL_PRIM_POSTDIV2_ACCESS "RW" +// ============================================================================= +// Register : PLL_INTR +// Description : Raw Interrupts +#define PLL_INTR_OFFSET _u(0x00000010) +#define PLL_INTR_BITS _u(0x00000001) +#define PLL_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PLL_INTR_LOCK_N_STICKY +#define PLL_INTR_LOCK_N_STICKY_RESET _u(0x0) +#define PLL_INTR_LOCK_N_STICKY_BITS _u(0x00000001) +#define PLL_INTR_LOCK_N_STICKY_MSB _u(0) +#define PLL_INTR_LOCK_N_STICKY_LSB _u(0) +#define PLL_INTR_LOCK_N_STICKY_ACCESS "WC" +// ============================================================================= +// Register : PLL_INTE +// Description : Interrupt Enable +#define PLL_INTE_OFFSET _u(0x00000014) +#define PLL_INTE_BITS _u(0x00000001) +#define PLL_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PLL_INTE_LOCK_N_STICKY +#define PLL_INTE_LOCK_N_STICKY_RESET _u(0x0) +#define PLL_INTE_LOCK_N_STICKY_BITS _u(0x00000001) +#define PLL_INTE_LOCK_N_STICKY_MSB _u(0) +#define PLL_INTE_LOCK_N_STICKY_LSB _u(0) +#define PLL_INTE_LOCK_N_STICKY_ACCESS "RW" +// ============================================================================= +// Register : PLL_INTF +// Description : Interrupt Force +#define PLL_INTF_OFFSET _u(0x00000018) +#define PLL_INTF_BITS _u(0x00000001) +#define PLL_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PLL_INTF_LOCK_N_STICKY +#define PLL_INTF_LOCK_N_STICKY_RESET _u(0x0) +#define PLL_INTF_LOCK_N_STICKY_BITS _u(0x00000001) +#define PLL_INTF_LOCK_N_STICKY_MSB _u(0) +#define PLL_INTF_LOCK_N_STICKY_LSB _u(0) +#define PLL_INTF_LOCK_N_STICKY_ACCESS "RW" +// ============================================================================= +// Register : PLL_INTS +// Description : Interrupt status after masking & forcing +#define PLL_INTS_OFFSET _u(0x0000001c) +#define PLL_INTS_BITS _u(0x00000001) +#define PLL_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PLL_INTS_LOCK_N_STICKY +#define PLL_INTS_LOCK_N_STICKY_RESET _u(0x0) +#define PLL_INTS_LOCK_N_STICKY_BITS _u(0x00000001) +#define PLL_INTS_LOCK_N_STICKY_MSB _u(0) +#define PLL_INTS_LOCK_N_STICKY_LSB _u(0) +#define PLL_INTS_LOCK_N_STICKY_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_PLL_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/powman.h b/lib/pico-sdk/rp2350/hardware/regs/powman.h new file mode 100644 index 000000000000..edfbabbcc1af --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/powman.h @@ -0,0 +1,2194 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : POWMAN +// Version : 1 +// Bus type : apb +// Description : Controls vreg, bor, lposc, chip resets & xosc startup, +// powman and provides scratch register for general use and for +// bootcode use +// ============================================================================= +#ifndef _HARDWARE_REGS_POWMAN_H +#define _HARDWARE_REGS_POWMAN_H +// ============================================================================= +// Register : POWMAN_BADPASSWD +// Description : Indicates a bad password has been used +#define POWMAN_BADPASSWD_OFFSET _u(0x00000000) +#define POWMAN_BADPASSWD_BITS _u(0x00000001) +#define POWMAN_BADPASSWD_RESET _u(0x00000000) +#define POWMAN_BADPASSWD_MSB _u(0) +#define POWMAN_BADPASSWD_LSB _u(0) +#define POWMAN_BADPASSWD_ACCESS "WC" +// ============================================================================= +// Register : POWMAN_VREG_CTRL +// Description : Voltage Regulator Control +#define POWMAN_VREG_CTRL_OFFSET _u(0x00000004) +#define POWMAN_VREG_CTRL_BITS _u(0x0000b170) +#define POWMAN_VREG_CTRL_RESET _u(0x00008050) +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_CTRL_RST_N +// Description : returns the regulator to its startup settings +// 0 - reset +// 1 - not reset (default) +#define POWMAN_VREG_CTRL_RST_N_RESET _u(0x1) +#define POWMAN_VREG_CTRL_RST_N_BITS _u(0x00008000) +#define POWMAN_VREG_CTRL_RST_N_MSB _u(15) +#define POWMAN_VREG_CTRL_RST_N_LSB _u(15) +#define POWMAN_VREG_CTRL_RST_N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_CTRL_UNLOCK +// Description : unlocks the VREG control interface after power up +// 0 - Locked (default) +// 1 - Unlocked +// It cannot be relocked when it is unlocked. +#define POWMAN_VREG_CTRL_UNLOCK_RESET _u(0x0) +#define POWMAN_VREG_CTRL_UNLOCK_BITS _u(0x00002000) +#define POWMAN_VREG_CTRL_UNLOCK_MSB _u(13) +#define POWMAN_VREG_CTRL_UNLOCK_LSB _u(13) +#define POWMAN_VREG_CTRL_UNLOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_CTRL_ISOLATE +// Description : isolates the VREG control interface +// 0 - not isolated (default) +// 1 - isolated +#define POWMAN_VREG_CTRL_ISOLATE_RESET _u(0x0) +#define POWMAN_VREG_CTRL_ISOLATE_BITS _u(0x00001000) +#define POWMAN_VREG_CTRL_ISOLATE_MSB _u(12) +#define POWMAN_VREG_CTRL_ISOLATE_LSB _u(12) +#define POWMAN_VREG_CTRL_ISOLATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT +// Description : 0=not disabled, 1=enabled +#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_RESET _u(0x0) +#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_BITS _u(0x00000100) +#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_MSB _u(8) +#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_LSB _u(8) +#define POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_CTRL_HT_TH +// Description : high temperature protection threshold +// regulator power transistors are disabled when junction +// temperature exceeds threshold +// 000 - 100C +// 001 - 105C +// 010 - 110C +// 011 - 115C +// 100 - 120C +// 101 - 125C +// 110 - 135C +// 111 - 150C +#define POWMAN_VREG_CTRL_HT_TH_RESET _u(0x5) +#define POWMAN_VREG_CTRL_HT_TH_BITS _u(0x00000070) +#define POWMAN_VREG_CTRL_HT_TH_MSB _u(6) +#define POWMAN_VREG_CTRL_HT_TH_LSB _u(4) +#define POWMAN_VREG_CTRL_HT_TH_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_VREG_STS +// Description : Voltage Regulator Status +#define POWMAN_VREG_STS_OFFSET _u(0x00000008) +#define POWMAN_VREG_STS_BITS _u(0x00000011) +#define POWMAN_VREG_STS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_STS_VOUT_OK +// Description : output regulation status +// 0=not in regulation, 1=in regulation +#define POWMAN_VREG_STS_VOUT_OK_RESET _u(0x0) +#define POWMAN_VREG_STS_VOUT_OK_BITS _u(0x00000010) +#define POWMAN_VREG_STS_VOUT_OK_MSB _u(4) +#define POWMAN_VREG_STS_VOUT_OK_LSB _u(4) +#define POWMAN_VREG_STS_VOUT_OK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_STS_STARTUP +// Description : startup status +// 0=startup complete, 1=starting up +#define POWMAN_VREG_STS_STARTUP_RESET _u(0x0) +#define POWMAN_VREG_STS_STARTUP_BITS _u(0x00000001) +#define POWMAN_VREG_STS_STARTUP_MSB _u(0) +#define POWMAN_VREG_STS_STARTUP_LSB _u(0) +#define POWMAN_VREG_STS_STARTUP_ACCESS "RO" +// ============================================================================= +// Register : POWMAN_VREG +// Description : Voltage Regulator Settings +#define POWMAN_VREG_OFFSET _u(0x0000000c) +#define POWMAN_VREG_BITS _u(0x000081f2) +#define POWMAN_VREG_RESET _u(0x000000b0) +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_UPDATE_IN_PROGRESS +// Description : regulator state is being updated +// writes to the vreg register will be ignored when this field is +// set +#define POWMAN_VREG_UPDATE_IN_PROGRESS_RESET _u(0x0) +#define POWMAN_VREG_UPDATE_IN_PROGRESS_BITS _u(0x00008000) +#define POWMAN_VREG_UPDATE_IN_PROGRESS_MSB _u(15) +#define POWMAN_VREG_UPDATE_IN_PROGRESS_LSB _u(15) +#define POWMAN_VREG_UPDATE_IN_PROGRESS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_VSEL +// Description : output voltage select +// the regulator output voltage is limited to 1.3V unless the +// voltage limit +// is disabled using the disable_voltage_limit field in the +// vreg_ctrl register +// 00000 - 0.55V +// 00001 - 0.60V +// 00010 - 0.65V +// 00011 - 0.70V +// 00100 - 0.75V +// 00101 - 0.80V +// 00110 - 0.85V +// 00111 - 0.90V +// 01000 - 0.95V +// 01001 - 1.00V +// 01010 - 1.05V +// 01011 - 1.10V (default) +// 01100 - 1.15V +// 01101 - 1.20V +// 01110 - 1.25V +// 01111 - 1.30V +// 10000 - 1.35V +// 10001 - 1.40V +// 10010 - 1.50V +// 10011 - 1.60V +// 10100 - 1.65V +// 10101 - 1.70V +// 10110 - 1.80V +// 10111 - 1.90V +// 11000 - 2.00V +// 11001 - 2.35V +// 11010 - 2.50V +// 11011 - 2.65V +// 11100 - 2.80V +// 11101 - 3.00V +// 11110 - 3.15V +// 11111 - 3.30V +#define POWMAN_VREG_VSEL_RESET _u(0x0b) +#define POWMAN_VREG_VSEL_BITS _u(0x000001f0) +#define POWMAN_VREG_VSEL_MSB _u(8) +#define POWMAN_VREG_VSEL_LSB _u(4) +#define POWMAN_VREG_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_HIZ +// Description : high impedance mode select +// 0=not in high impedance mode, 1=in high impedance mode +#define POWMAN_VREG_HIZ_RESET _u(0x0) +#define POWMAN_VREG_HIZ_BITS _u(0x00000002) +#define POWMAN_VREG_HIZ_MSB _u(1) +#define POWMAN_VREG_HIZ_LSB _u(1) +#define POWMAN_VREG_HIZ_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_VREG_LP_ENTRY +// Description : Voltage Regulator Low Power Entry Settings +#define POWMAN_VREG_LP_ENTRY_OFFSET _u(0x00000010) +#define POWMAN_VREG_LP_ENTRY_BITS _u(0x000001f6) +#define POWMAN_VREG_LP_ENTRY_RESET _u(0x000000b4) +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_LP_ENTRY_VSEL +// Description : output voltage select +// the regulator output voltage is limited to 1.3V unless the +// voltage limit +// is disabled using the disable_voltage_limit field in the +// vreg_ctrl register +// 00000 - 0.55V +// 00001 - 0.60V +// 00010 - 0.65V +// 00011 - 0.70V +// 00100 - 0.75V +// 00101 - 0.80V +// 00110 - 0.85V +// 00111 - 0.90V +// 01000 - 0.95V +// 01001 - 1.00V +// 01010 - 1.05V +// 01011 - 1.10V (default) +// 01100 - 1.15V +// 01101 - 1.20V +// 01110 - 1.25V +// 01111 - 1.30V +// 10000 - 1.35V +// 10001 - 1.40V +// 10010 - 1.50V +// 10011 - 1.60V +// 10100 - 1.65V +// 10101 - 1.70V +// 10110 - 1.80V +// 10111 - 1.90V +// 11000 - 2.00V +// 11001 - 2.35V +// 11010 - 2.50V +// 11011 - 2.65V +// 11100 - 2.80V +// 11101 - 3.00V +// 11110 - 3.15V +// 11111 - 3.30V +#define POWMAN_VREG_LP_ENTRY_VSEL_RESET _u(0x0b) +#define POWMAN_VREG_LP_ENTRY_VSEL_BITS _u(0x000001f0) +#define POWMAN_VREG_LP_ENTRY_VSEL_MSB _u(8) +#define POWMAN_VREG_LP_ENTRY_VSEL_LSB _u(4) +#define POWMAN_VREG_LP_ENTRY_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_LP_ENTRY_MODE +// Description : selects either normal (switching) mode or low power (linear) +// mode +// low power mode can only be selected for output voltages up to +// 1.3V +// 0 = normal mode (switching) +// 1 = low power mode (linear) +#define POWMAN_VREG_LP_ENTRY_MODE_RESET _u(0x1) +#define POWMAN_VREG_LP_ENTRY_MODE_BITS _u(0x00000004) +#define POWMAN_VREG_LP_ENTRY_MODE_MSB _u(2) +#define POWMAN_VREG_LP_ENTRY_MODE_LSB _u(2) +#define POWMAN_VREG_LP_ENTRY_MODE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_LP_ENTRY_HIZ +// Description : high impedance mode select +// 0=not in high impedance mode, 1=in high impedance mode +#define POWMAN_VREG_LP_ENTRY_HIZ_RESET _u(0x0) +#define POWMAN_VREG_LP_ENTRY_HIZ_BITS _u(0x00000002) +#define POWMAN_VREG_LP_ENTRY_HIZ_MSB _u(1) +#define POWMAN_VREG_LP_ENTRY_HIZ_LSB _u(1) +#define POWMAN_VREG_LP_ENTRY_HIZ_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_VREG_LP_EXIT +// Description : Voltage Regulator Low Power Exit Settings +#define POWMAN_VREG_LP_EXIT_OFFSET _u(0x00000014) +#define POWMAN_VREG_LP_EXIT_BITS _u(0x000001f6) +#define POWMAN_VREG_LP_EXIT_RESET _u(0x000000b0) +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_LP_EXIT_VSEL +// Description : output voltage select +// the regulator output voltage is limited to 1.3V unless the +// voltage limit +// is disabled using the disable_voltage_limit field in the +// vreg_ctrl register +// 00000 - 0.55V +// 00001 - 0.60V +// 00010 - 0.65V +// 00011 - 0.70V +// 00100 - 0.75V +// 00101 - 0.80V +// 00110 - 0.85V +// 00111 - 0.90V +// 01000 - 0.95V +// 01001 - 1.00V +// 01010 - 1.05V +// 01011 - 1.10V (default) +// 01100 - 1.15V +// 01101 - 1.20V +// 01110 - 1.25V +// 01111 - 1.30V +// 10000 - 1.35V +// 10001 - 1.40V +// 10010 - 1.50V +// 10011 - 1.60V +// 10100 - 1.65V +// 10101 - 1.70V +// 10110 - 1.80V +// 10111 - 1.90V +// 11000 - 2.00V +// 11001 - 2.35V +// 11010 - 2.50V +// 11011 - 2.65V +// 11100 - 2.80V +// 11101 - 3.00V +// 11110 - 3.15V +// 11111 - 3.30V +#define POWMAN_VREG_LP_EXIT_VSEL_RESET _u(0x0b) +#define POWMAN_VREG_LP_EXIT_VSEL_BITS _u(0x000001f0) +#define POWMAN_VREG_LP_EXIT_VSEL_MSB _u(8) +#define POWMAN_VREG_LP_EXIT_VSEL_LSB _u(4) +#define POWMAN_VREG_LP_EXIT_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_LP_EXIT_MODE +// Description : selects either normal (switching) mode or low power (linear) +// mode +// low power mode can only be selected for output voltages up to +// 1.3V +// 0 = normal mode (switching) +// 1 = low power mode (linear) +#define POWMAN_VREG_LP_EXIT_MODE_RESET _u(0x0) +#define POWMAN_VREG_LP_EXIT_MODE_BITS _u(0x00000004) +#define POWMAN_VREG_LP_EXIT_MODE_MSB _u(2) +#define POWMAN_VREG_LP_EXIT_MODE_LSB _u(2) +#define POWMAN_VREG_LP_EXIT_MODE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_VREG_LP_EXIT_HIZ +// Description : high impedance mode select +// 0=not in high impedance mode, 1=in high impedance mode +#define POWMAN_VREG_LP_EXIT_HIZ_RESET _u(0x0) +#define POWMAN_VREG_LP_EXIT_HIZ_BITS _u(0x00000002) +#define POWMAN_VREG_LP_EXIT_HIZ_MSB _u(1) +#define POWMAN_VREG_LP_EXIT_HIZ_LSB _u(1) +#define POWMAN_VREG_LP_EXIT_HIZ_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOD_CTRL +// Description : Brown-out Detection Control +#define POWMAN_BOD_CTRL_OFFSET _u(0x00000018) +#define POWMAN_BOD_CTRL_BITS _u(0x00001000) +#define POWMAN_BOD_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOD_CTRL_ISOLATE +// Description : isolates the brown-out detection control interface +// 0 - not isolated (default) +// 1 - isolated +#define POWMAN_BOD_CTRL_ISOLATE_RESET _u(0x0) +#define POWMAN_BOD_CTRL_ISOLATE_BITS _u(0x00001000) +#define POWMAN_BOD_CTRL_ISOLATE_MSB _u(12) +#define POWMAN_BOD_CTRL_ISOLATE_LSB _u(12) +#define POWMAN_BOD_CTRL_ISOLATE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOD +// Description : Brown-out Detection Settings +#define POWMAN_BOD_OFFSET _u(0x0000001c) +#define POWMAN_BOD_BITS _u(0x000001f1) +#define POWMAN_BOD_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOD_VSEL +// Description : threshold select +// 00000 - 0.473V +// 00001 - 0.516V +// 00010 - 0.559V +// 00011 - 0.602V +// 00100 - 0.645VS +// 00101 - 0.688V +// 00110 - 0.731V +// 00111 - 0.774V +// 01000 - 0.817V +// 01001 - 0.860V (default) +// 01010 - 0.903V +// 01011 - 0.946V +// 01100 - 0.989V +// 01101 - 1.032V +// 01110 - 1.075V +// 01111 - 1.118V +// 10000 - 1.161 +// 10001 - 1.204V +#define POWMAN_BOD_VSEL_RESET _u(0x0b) +#define POWMAN_BOD_VSEL_BITS _u(0x000001f0) +#define POWMAN_BOD_VSEL_MSB _u(8) +#define POWMAN_BOD_VSEL_LSB _u(4) +#define POWMAN_BOD_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOD_EN +// Description : enable brown-out detection +// 0=not enabled, 1=enabled +#define POWMAN_BOD_EN_RESET _u(0x1) +#define POWMAN_BOD_EN_BITS _u(0x00000001) +#define POWMAN_BOD_EN_MSB _u(0) +#define POWMAN_BOD_EN_LSB _u(0) +#define POWMAN_BOD_EN_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOD_LP_ENTRY +// Description : Brown-out Detection Low Power Entry Settings +#define POWMAN_BOD_LP_ENTRY_OFFSET _u(0x00000020) +#define POWMAN_BOD_LP_ENTRY_BITS _u(0x000001f1) +#define POWMAN_BOD_LP_ENTRY_RESET _u(0x000000b0) +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOD_LP_ENTRY_VSEL +// Description : threshold select +// 00000 - 0.473V +// 00001 - 0.516V +// 00010 - 0.559V +// 00011 - 0.602V +// 00100 - 0.645VS +// 00101 - 0.688V +// 00110 - 0.731V +// 00111 - 0.774V +// 01000 - 0.817V +// 01001 - 0.860V (default) +// 01010 - 0.903V +// 01011 - 0.946V +// 01100 - 0.989V +// 01101 - 1.032V +// 01110 - 1.075V +// 01111 - 1.118V +// 10000 - 1.161 +// 10001 - 1.204V +#define POWMAN_BOD_LP_ENTRY_VSEL_RESET _u(0x0b) +#define POWMAN_BOD_LP_ENTRY_VSEL_BITS _u(0x000001f0) +#define POWMAN_BOD_LP_ENTRY_VSEL_MSB _u(8) +#define POWMAN_BOD_LP_ENTRY_VSEL_LSB _u(4) +#define POWMAN_BOD_LP_ENTRY_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOD_LP_ENTRY_EN +// Description : enable brown-out detection +// 0=not enabled, 1=enabled +#define POWMAN_BOD_LP_ENTRY_EN_RESET _u(0x0) +#define POWMAN_BOD_LP_ENTRY_EN_BITS _u(0x00000001) +#define POWMAN_BOD_LP_ENTRY_EN_MSB _u(0) +#define POWMAN_BOD_LP_ENTRY_EN_LSB _u(0) +#define POWMAN_BOD_LP_ENTRY_EN_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOD_LP_EXIT +// Description : Brown-out Detection Low Power Exit Settings +#define POWMAN_BOD_LP_EXIT_OFFSET _u(0x00000024) +#define POWMAN_BOD_LP_EXIT_BITS _u(0x000001f1) +#define POWMAN_BOD_LP_EXIT_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOD_LP_EXIT_VSEL +// Description : threshold select +// 00000 - 0.473V +// 00001 - 0.516V +// 00010 - 0.559V +// 00011 - 0.602V +// 00100 - 0.645VS +// 00101 - 0.688V +// 00110 - 0.731V +// 00111 - 0.774V +// 01000 - 0.817V +// 01001 - 0.860V (default) +// 01010 - 0.903V +// 01011 - 0.946V +// 01100 - 0.989V +// 01101 - 1.032V +// 01110 - 1.075V +// 01111 - 1.118V +// 10000 - 1.161 +// 10001 - 1.204V +#define POWMAN_BOD_LP_EXIT_VSEL_RESET _u(0x0b) +#define POWMAN_BOD_LP_EXIT_VSEL_BITS _u(0x000001f0) +#define POWMAN_BOD_LP_EXIT_VSEL_MSB _u(8) +#define POWMAN_BOD_LP_EXIT_VSEL_LSB _u(4) +#define POWMAN_BOD_LP_EXIT_VSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOD_LP_EXIT_EN +// Description : enable brown-out detection +// 0=not enabled, 1=enabled +#define POWMAN_BOD_LP_EXIT_EN_RESET _u(0x1) +#define POWMAN_BOD_LP_EXIT_EN_BITS _u(0x00000001) +#define POWMAN_BOD_LP_EXIT_EN_MSB _u(0) +#define POWMAN_BOD_LP_EXIT_EN_LSB _u(0) +#define POWMAN_BOD_LP_EXIT_EN_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_LPOSC +// Description : Low power oscillator control register. +#define POWMAN_LPOSC_OFFSET _u(0x00000028) +#define POWMAN_LPOSC_BITS _u(0x000003f3) +#define POWMAN_LPOSC_RESET _u(0x00000203) +// ----------------------------------------------------------------------------- +// Field : POWMAN_LPOSC_TRIM +// Description : Frequency trim - the trim step is typically 1% of the reset +// frequency, but can be up to 3% +#define POWMAN_LPOSC_TRIM_RESET _u(0x20) +#define POWMAN_LPOSC_TRIM_BITS _u(0x000003f0) +#define POWMAN_LPOSC_TRIM_MSB _u(9) +#define POWMAN_LPOSC_TRIM_LSB _u(4) +#define POWMAN_LPOSC_TRIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_LPOSC_MODE +// Description : This feature has been removed +#define POWMAN_LPOSC_MODE_RESET _u(0x3) +#define POWMAN_LPOSC_MODE_BITS _u(0x00000003) +#define POWMAN_LPOSC_MODE_MSB _u(1) +#define POWMAN_LPOSC_MODE_LSB _u(0) +#define POWMAN_LPOSC_MODE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_CHIP_RESET +// Description : Chip reset control and status +#define POWMAN_CHIP_RESET_OFFSET _u(0x0000002c) +#define POWMAN_CHIP_RESET_BITS _u(0x1fef0011) +#define POWMAN_CHIP_RESET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM +// Description : Last reset was a watchdog timeout which was configured to reset +// the power-on state machine +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no +// timer no +// powman no +// swcore no +// psm yes +// and does not change the power state +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_BITS _u(0x10000000) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_MSB _u(28) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_LSB _u(28) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ +// Description : Last reset was a system reset from the hazard debugger +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no +// timer no +// powman no +// swcore no +// psm yes +// and does not change the power state +#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_BITS _u(0x08000000) +#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_MSB _u(27) +#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_LSB _u(27) +#define POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_GLITCH_DETECT +// Description : Last reset was due to a power supply glitch +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no +// timer no +// powman no +// swcore no +// psm yes +// and does not change the power state +#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_BITS _u(0x04000000) +#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_MSB _u(26) +#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_LSB _u(26) +#define POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_SWCORE_PD +// Description : Last reset was a switched core powerdown +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no +// timer no +// powman no +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_BITS _u(0x02000000) +#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_MSB _u(25) +#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_LSB _u(25) +#define POWMAN_CHIP_RESET_HAD_SWCORE_PD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE +// Description : Last reset was a watchdog timeout which was configured to reset +// the switched-core +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no +// timer no +// powman no +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_BITS _u(0x01000000) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_MSB _u(24) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_LSB _u(24) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN +// Description : Last reset was a watchdog timeout which was configured to reset +// the power manager +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no +// timer yes +// powman yes +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_BITS _u(0x00800000) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_MSB _u(23) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_LSB _u(23) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC +// Description : Last reset was a watchdog timeout which was configured to reset +// the power manager asynchronously +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no +// timer yes +// powman yes +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_BITS _u(0x00400000) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_MSB _u(22) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_LSB _u(22) +#define POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_RESCUE +// Description : Last reset was a rescue reset from the debugger +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag no, it sets this flag +// timer yes +// powman yes +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_RESCUE_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_RESCUE_BITS _u(0x00200000) +#define POWMAN_CHIP_RESET_HAD_RESCUE_MSB _u(21) +#define POWMAN_CHIP_RESET_HAD_RESCUE_LSB _u(21) +#define POWMAN_CHIP_RESET_HAD_RESCUE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_DP_RESET_REQ +// Description : Last reset was an reset request from the arm debugger +// This resets: +// double_tap flag no +// DP no +// RPAP no +// rescue_flag yes +// timer yes +// powman yes +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_BITS _u(0x00080000) +#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_MSB _u(19) +#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_LSB _u(19) +#define POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_RUN_LOW +// Description : Last reset was from the RUN pin +// This resets: +// double_tap flag no +// DP yes +// RPAP yes +// rescue_flag yes +// timer yes +// powman yes +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_RUN_LOW_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_RUN_LOW_BITS _u(0x00040000) +#define POWMAN_CHIP_RESET_HAD_RUN_LOW_MSB _u(18) +#define POWMAN_CHIP_RESET_HAD_RUN_LOW_LSB _u(18) +#define POWMAN_CHIP_RESET_HAD_RUN_LOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_BOR +// Description : Last reset was from the brown-out detection block +// This resets: +// double_tap flag yes +// DP yes +// RPAP yes +// rescue_flag yes +// timer yes +// powman yes +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_BOR_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_BOR_BITS _u(0x00020000) +#define POWMAN_CHIP_RESET_HAD_BOR_MSB _u(17) +#define POWMAN_CHIP_RESET_HAD_BOR_LSB _u(17) +#define POWMAN_CHIP_RESET_HAD_BOR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_HAD_POR +// Description : Last reset was from the power-on reset +// This resets: +// double_tap flag yes +// DP yes +// RPAP yes +// rescue_flag yes +// timer yes +// powman yes +// swcore yes +// psm yes +// then starts the power sequencer +#define POWMAN_CHIP_RESET_HAD_POR_RESET _u(0x0) +#define POWMAN_CHIP_RESET_HAD_POR_BITS _u(0x00010000) +#define POWMAN_CHIP_RESET_HAD_POR_MSB _u(16) +#define POWMAN_CHIP_RESET_HAD_POR_LSB _u(16) +#define POWMAN_CHIP_RESET_HAD_POR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_RESCUE_FLAG +// Description : This is set by a rescue reset from the RP-AP. +// Its purpose is to halt before the bootrom before booting from +// flash in order to recover from a boot lock-up. +// The debugger can then attach once the bootrom has been halted +// and flash some working code that does not lock up. +#define POWMAN_CHIP_RESET_RESCUE_FLAG_RESET _u(0x0) +#define POWMAN_CHIP_RESET_RESCUE_FLAG_BITS _u(0x00000010) +#define POWMAN_CHIP_RESET_RESCUE_FLAG_MSB _u(4) +#define POWMAN_CHIP_RESET_RESCUE_FLAG_LSB _u(4) +#define POWMAN_CHIP_RESET_RESCUE_FLAG_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_CHIP_RESET_DOUBLE_TAP +// Description : This flag is set by double-tapping RUN. It tells bootcode to go +// into the bootloader. +#define POWMAN_CHIP_RESET_DOUBLE_TAP_RESET _u(0x0) +#define POWMAN_CHIP_RESET_DOUBLE_TAP_BITS _u(0x00000001) +#define POWMAN_CHIP_RESET_DOUBLE_TAP_MSB _u(0) +#define POWMAN_CHIP_RESET_DOUBLE_TAP_LSB _u(0) +#define POWMAN_CHIP_RESET_DOUBLE_TAP_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_WDSEL +// Description : Allows a watchdog reset to reset the internal state of powman +// in addition to the power-on state machine (PSM). +// Note that powman ignores watchdog resets that do not select at +// least the CLOCKS stage or earlier stages in the PSM. If using +// these bits, it's recommended to set PSM_WDSEL to all-ones in +// addition to the desired bits in this register. Failing to +// select CLOCKS or earlier will result in the POWMAN_WDSEL +// register having no effect. +#define POWMAN_WDSEL_OFFSET _u(0x00000030) +#define POWMAN_WDSEL_BITS _u(0x00001111) +#define POWMAN_WDSEL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_WDSEL_RESET_RSM +// Description : If set to 1, a watchdog reset will run the full power-on state +// machine (PSM) sequence +// From a user perspective it is the same as setting +// RSM_WDSEL_PROC_COLD +// From a hardware debug perspective it has the same effect as a +// reset from a glitch detector +#define POWMAN_WDSEL_RESET_RSM_RESET _u(0x0) +#define POWMAN_WDSEL_RESET_RSM_BITS _u(0x00001000) +#define POWMAN_WDSEL_RESET_RSM_MSB _u(12) +#define POWMAN_WDSEL_RESET_RSM_LSB _u(12) +#define POWMAN_WDSEL_RESET_RSM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_WDSEL_RESET_SWCORE +// Description : If set to 1, a watchdog reset will reset the switched core +// power domain and run the full power-on state machine (PSM) +// sequence +// From a user perspective it is the same as setting +// RSM_WDSEL_PROC_COLD +// From a hardware debug perspective it has the same effect as a +// power-on reset for the switched core power domain +#define POWMAN_WDSEL_RESET_SWCORE_RESET _u(0x0) +#define POWMAN_WDSEL_RESET_SWCORE_BITS _u(0x00000100) +#define POWMAN_WDSEL_RESET_SWCORE_MSB _u(8) +#define POWMAN_WDSEL_RESET_SWCORE_LSB _u(8) +#define POWMAN_WDSEL_RESET_SWCORE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_WDSEL_RESET_POWMAN +// Description : If set to 1, a watchdog reset will restore powman defaults, +// reset the timer, reset the switched core power domain +// and run the full power-on state machine (PSM) sequence +// This relies on clk_ref running. Use reset_powman_async if that +// may not be true +#define POWMAN_WDSEL_RESET_POWMAN_RESET _u(0x0) +#define POWMAN_WDSEL_RESET_POWMAN_BITS _u(0x00000010) +#define POWMAN_WDSEL_RESET_POWMAN_MSB _u(4) +#define POWMAN_WDSEL_RESET_POWMAN_LSB _u(4) +#define POWMAN_WDSEL_RESET_POWMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_WDSEL_RESET_POWMAN_ASYNC +// Description : If set to 1, a watchdog reset will restore powman defaults, +// reset the timer, +// reset the switched core domain and run the full power-on state +// machine (PSM) sequence +// This does not rely on clk_ref running +#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_RESET _u(0x0) +#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_BITS _u(0x00000001) +#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_MSB _u(0) +#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_LSB _u(0) +#define POWMAN_WDSEL_RESET_POWMAN_ASYNC_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SEQ_CFG +// Description : For configuration of the power sequencer +// Writes are ignored while POWMAN_STATE_CHANGING=1 +#define POWMAN_SEQ_CFG_OFFSET _u(0x00000034) +#define POWMAN_SEQ_CFG_BITS _u(0x001311f3) +#define POWMAN_SEQ_CFG_RESET _u(0x001011f0) +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USING_FAST_POWCK +// Description : 0 indicates the POWMAN clock is running from the low power +// oscillator (32kHz) +// 1 indicates the POWMAN clock is running from the reference +// clock (2-50MHz) +#define POWMAN_SEQ_CFG_USING_FAST_POWCK_RESET _u(0x1) +#define POWMAN_SEQ_CFG_USING_FAST_POWCK_BITS _u(0x00100000) +#define POWMAN_SEQ_CFG_USING_FAST_POWCK_MSB _u(20) +#define POWMAN_SEQ_CFG_USING_FAST_POWCK_LSB _u(20) +#define POWMAN_SEQ_CFG_USING_FAST_POWCK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USING_BOD_LP +// Description : Indicates the brown-out detector (BOD) mode +// 0 = BOD high power mode which is the default +// 1 = BOD low power mode +#define POWMAN_SEQ_CFG_USING_BOD_LP_RESET _u(0x0) +#define POWMAN_SEQ_CFG_USING_BOD_LP_BITS _u(0x00020000) +#define POWMAN_SEQ_CFG_USING_BOD_LP_MSB _u(17) +#define POWMAN_SEQ_CFG_USING_BOD_LP_LSB _u(17) +#define POWMAN_SEQ_CFG_USING_BOD_LP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USING_VREG_LP +// Description : Indicates the voltage regulator (VREG) mode +// 0 = VREG high power mode which is the default +// 1 = VREG low power mode +#define POWMAN_SEQ_CFG_USING_VREG_LP_RESET _u(0x0) +#define POWMAN_SEQ_CFG_USING_VREG_LP_BITS _u(0x00010000) +#define POWMAN_SEQ_CFG_USING_VREG_LP_MSB _u(16) +#define POWMAN_SEQ_CFG_USING_VREG_LP_LSB _u(16) +#define POWMAN_SEQ_CFG_USING_VREG_LP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USE_FAST_POWCK +// Description : selects the reference clock (clk_ref) as the source of the +// POWMAN clock when switched-core is powered. The POWMAN clock +// always switches to the slow clock (lposc) when switched-core is +// powered down because the fast clock stops running. +// 0 always run the POWMAN clock from the slow clock (lposc) +// 1 run the POWMAN clock from the fast clock when available +// This setting takes effect when a power up sequence is next run +#define POWMAN_SEQ_CFG_USE_FAST_POWCK_RESET _u(0x1) +#define POWMAN_SEQ_CFG_USE_FAST_POWCK_BITS _u(0x00001000) +#define POWMAN_SEQ_CFG_USE_FAST_POWCK_MSB _u(12) +#define POWMAN_SEQ_CFG_USE_FAST_POWCK_LSB _u(12) +#define POWMAN_SEQ_CFG_USE_FAST_POWCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP +// Description : Set to 0 to stop the low power osc when the switched-core is +// powered down, which is unwise if using it to clock the timer +// This setting takes effect when the swcore is next powered down +#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_RESET _u(0x1) +#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_BITS _u(0x00000100) +#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_MSB _u(8) +#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_LSB _u(8) +#define POWMAN_SEQ_CFG_RUN_LPOSC_IN_LP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USE_BOD_HP +// Description : Set to 0 to prevent automatic switching to bod high power mode +// when switched-core is powered up +// This setting takes effect when the swcore is next powered up +#define POWMAN_SEQ_CFG_USE_BOD_HP_RESET _u(0x1) +#define POWMAN_SEQ_CFG_USE_BOD_HP_BITS _u(0x00000080) +#define POWMAN_SEQ_CFG_USE_BOD_HP_MSB _u(7) +#define POWMAN_SEQ_CFG_USE_BOD_HP_LSB _u(7) +#define POWMAN_SEQ_CFG_USE_BOD_HP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USE_BOD_LP +// Description : Set to 0 to prevent automatic switching to bod low power mode +// when switched-core is powered down +// This setting takes effect when the swcore is next powered down +#define POWMAN_SEQ_CFG_USE_BOD_LP_RESET _u(0x1) +#define POWMAN_SEQ_CFG_USE_BOD_LP_BITS _u(0x00000040) +#define POWMAN_SEQ_CFG_USE_BOD_LP_MSB _u(6) +#define POWMAN_SEQ_CFG_USE_BOD_LP_LSB _u(6) +#define POWMAN_SEQ_CFG_USE_BOD_LP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USE_VREG_HP +// Description : Set to 0 to prevent automatic switching to vreg high power mode +// when switched-core is powered up +// This setting takes effect when the swcore is next powered up +#define POWMAN_SEQ_CFG_USE_VREG_HP_RESET _u(0x1) +#define POWMAN_SEQ_CFG_USE_VREG_HP_BITS _u(0x00000020) +#define POWMAN_SEQ_CFG_USE_VREG_HP_MSB _u(5) +#define POWMAN_SEQ_CFG_USE_VREG_HP_LSB _u(5) +#define POWMAN_SEQ_CFG_USE_VREG_HP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_USE_VREG_LP +// Description : Set to 0 to prevent automatic switching to vreg low power mode +// when switched-core is powered down +// This setting takes effect when the swcore is next powered down +#define POWMAN_SEQ_CFG_USE_VREG_LP_RESET _u(0x1) +#define POWMAN_SEQ_CFG_USE_VREG_LP_BITS _u(0x00000010) +#define POWMAN_SEQ_CFG_USE_VREG_LP_MSB _u(4) +#define POWMAN_SEQ_CFG_USE_VREG_LP_LSB _u(4) +#define POWMAN_SEQ_CFG_USE_VREG_LP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_HW_PWRUP_SRAM0 +// Description : Specifies the power state of SRAM0 when powering up swcore from +// a low power state (P1.xxx) to a high power state (P0.0xx). +// 0=power-up +// 1=no change +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_RESET _u(0x0) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_BITS _u(0x00000002) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_MSB _u(1) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_LSB _u(1) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_SEQ_CFG_HW_PWRUP_SRAM1 +// Description : Specifies the power state of SRAM1 when powering up swcore from +// a low power state (P1.xxx) to a high power state (P0.0xx). +// 0=power-up +// 1=no change +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_RESET _u(0x0) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_BITS _u(0x00000001) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_MSB _u(0) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_LSB _u(0) +#define POWMAN_SEQ_CFG_HW_PWRUP_SRAM1_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_STATE +// Description : This register controls the power state of the 4 power domains. +// The current power state is indicated in POWMAN_STATE_CURRENT +// which is read-only. +// To change the state, write to POWMAN_STATE_REQ. +// The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ +// corresponds to the power states +// defined in the datasheet: +// bit 3 = SWCORE +// bit 2 = XIP cache +// bit 1 = SRAM0 +// bit 0 = SRAM1 +// 0 = powered up +// 1 = powered down +// When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag +// is set while the Power Manager determines what is required. If +// an invalid transition is requested the Power Manager will still +// register the request in POWMAN_STATE_REQ but will also set the +// POWMAN_BAD_REQ flag. It will then implement the power-up +// requests and ignore the power down requests. To do nothing +// would risk entering an unrecoverable lock-up state. Invalid +// requests are: any combination of power up and power down +// requests any request that results in swcore boing powered and +// xip unpowered If the request is to power down the switched-core +// domain then POWMAN_STATE_WAITING stays active until the +// processors halt. During this time the POWMAN_STATE_REQ field +// can be re-written to change or cancel the request. When the +// power state transition begins the POWMAN_STATE_WAITING_flag is +// cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN +// register writes are ignored until the transition completes. +#define POWMAN_STATE_OFFSET _u(0x00000038) +#define POWMAN_STATE_BITS _u(0x00003fff) +#define POWMAN_STATE_RESET _u(0x0000000f) +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_CHANGING +#define POWMAN_STATE_CHANGING_RESET _u(0x0) +#define POWMAN_STATE_CHANGING_BITS _u(0x00002000) +#define POWMAN_STATE_CHANGING_MSB _u(13) +#define POWMAN_STATE_CHANGING_LSB _u(13) +#define POWMAN_STATE_CHANGING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_WAITING +#define POWMAN_STATE_WAITING_RESET _u(0x0) +#define POWMAN_STATE_WAITING_BITS _u(0x00001000) +#define POWMAN_STATE_WAITING_MSB _u(12) +#define POWMAN_STATE_WAITING_LSB _u(12) +#define POWMAN_STATE_WAITING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_BAD_HW_REQ +// Description : Bad hardware initiated state request. Went back to state 0 +// (i.e. everything powered up) +#define POWMAN_STATE_BAD_HW_REQ_RESET _u(0x0) +#define POWMAN_STATE_BAD_HW_REQ_BITS _u(0x00000800) +#define POWMAN_STATE_BAD_HW_REQ_MSB _u(11) +#define POWMAN_STATE_BAD_HW_REQ_LSB _u(11) +#define POWMAN_STATE_BAD_HW_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_BAD_SW_REQ +// Description : Bad software initiated state request. No action taken. +#define POWMAN_STATE_BAD_SW_REQ_RESET _u(0x0) +#define POWMAN_STATE_BAD_SW_REQ_BITS _u(0x00000400) +#define POWMAN_STATE_BAD_SW_REQ_MSB _u(10) +#define POWMAN_STATE_BAD_SW_REQ_LSB _u(10) +#define POWMAN_STATE_BAD_SW_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_PWRUP_WHILE_WAITING +// Description : Request ignored because of a pending pwrup request. See +// current_pwrup_req. Note this blocks powering up AND powering +// down. +#define POWMAN_STATE_PWRUP_WHILE_WAITING_RESET _u(0x0) +#define POWMAN_STATE_PWRUP_WHILE_WAITING_BITS _u(0x00000200) +#define POWMAN_STATE_PWRUP_WHILE_WAITING_MSB _u(9) +#define POWMAN_STATE_PWRUP_WHILE_WAITING_LSB _u(9) +#define POWMAN_STATE_PWRUP_WHILE_WAITING_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_REQ_IGNORED +#define POWMAN_STATE_REQ_IGNORED_RESET _u(0x0) +#define POWMAN_STATE_REQ_IGNORED_BITS _u(0x00000100) +#define POWMAN_STATE_REQ_IGNORED_MSB _u(8) +#define POWMAN_STATE_REQ_IGNORED_LSB _u(8) +#define POWMAN_STATE_REQ_IGNORED_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_REQ +#define POWMAN_STATE_REQ_RESET _u(0x0) +#define POWMAN_STATE_REQ_BITS _u(0x000000f0) +#define POWMAN_STATE_REQ_MSB _u(7) +#define POWMAN_STATE_REQ_LSB _u(4) +#define POWMAN_STATE_REQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_STATE_CURRENT +#define POWMAN_STATE_CURRENT_RESET _u(0xf) +#define POWMAN_STATE_CURRENT_BITS _u(0x0000000f) +#define POWMAN_STATE_CURRENT_MSB _u(3) +#define POWMAN_STATE_CURRENT_LSB _u(0) +#define POWMAN_STATE_CURRENT_ACCESS "RO" +// ============================================================================= +// Register : POWMAN_POW_FASTDIV +// Description : None +// divides the POWMAN clock to provide a tick for the delay module +// and state machines +// when clk_pow is running from the slow clock it is not divided +// when clk_pow is running from the fast clock it is divided by +// tick_div +#define POWMAN_POW_FASTDIV_OFFSET _u(0x0000003c) +#define POWMAN_POW_FASTDIV_BITS _u(0x000007ff) +#define POWMAN_POW_FASTDIV_RESET _u(0x00000040) +#define POWMAN_POW_FASTDIV_MSB _u(10) +#define POWMAN_POW_FASTDIV_LSB _u(0) +#define POWMAN_POW_FASTDIV_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_POW_DELAY +// Description : power state machine delays +#define POWMAN_POW_DELAY_OFFSET _u(0x00000040) +#define POWMAN_POW_DELAY_BITS _u(0x0000ffff) +#define POWMAN_POW_DELAY_RESET _u(0x00002011) +// ----------------------------------------------------------------------------- +// Field : POWMAN_POW_DELAY_SRAM_STEP +// Description : timing between the sram0 and sram1 power state machine steps +// measured in units of the powman tick period (>=1us), 0 gives a +// delay of 1 unit +#define POWMAN_POW_DELAY_SRAM_STEP_RESET _u(0x20) +#define POWMAN_POW_DELAY_SRAM_STEP_BITS _u(0x0000ff00) +#define POWMAN_POW_DELAY_SRAM_STEP_MSB _u(15) +#define POWMAN_POW_DELAY_SRAM_STEP_LSB _u(8) +#define POWMAN_POW_DELAY_SRAM_STEP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_POW_DELAY_XIP_STEP +// Description : timing between the xip power state machine steps +// measured in units of the lposc period, 0 gives a delay of 1 +// unit +#define POWMAN_POW_DELAY_XIP_STEP_RESET _u(0x1) +#define POWMAN_POW_DELAY_XIP_STEP_BITS _u(0x000000f0) +#define POWMAN_POW_DELAY_XIP_STEP_MSB _u(7) +#define POWMAN_POW_DELAY_XIP_STEP_LSB _u(4) +#define POWMAN_POW_DELAY_XIP_STEP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_POW_DELAY_SWCORE_STEP +// Description : timing between the swcore power state machine steps +// measured in units of the lposc period, 0 gives a delay of 1 +// unit +#define POWMAN_POW_DELAY_SWCORE_STEP_RESET _u(0x1) +#define POWMAN_POW_DELAY_SWCORE_STEP_BITS _u(0x0000000f) +#define POWMAN_POW_DELAY_SWCORE_STEP_MSB _u(3) +#define POWMAN_POW_DELAY_SWCORE_STEP_LSB _u(0) +#define POWMAN_POW_DELAY_SWCORE_STEP_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_EXT_CTRL0 +// Description : Configures a gpio as a power mode aware control output +#define POWMAN_EXT_CTRL0_OFFSET _u(0x00000044) +#define POWMAN_EXT_CTRL0_BITS _u(0x0000713f) +#define POWMAN_EXT_CTRL0_RESET _u(0x0000003f) +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL0_LP_EXIT_STATE +// Description : output level when exiting the low power state +#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_RESET _u(0x0) +#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_BITS _u(0x00004000) +#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_MSB _u(14) +#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_LSB _u(14) +#define POWMAN_EXT_CTRL0_LP_EXIT_STATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL0_LP_ENTRY_STATE +// Description : output level when entering the low power state +#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_RESET _u(0x0) +#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_BITS _u(0x00002000) +#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_MSB _u(13) +#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_LSB _u(13) +#define POWMAN_EXT_CTRL0_LP_ENTRY_STATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL0_INIT_STATE +#define POWMAN_EXT_CTRL0_INIT_STATE_RESET _u(0x0) +#define POWMAN_EXT_CTRL0_INIT_STATE_BITS _u(0x00001000) +#define POWMAN_EXT_CTRL0_INIT_STATE_MSB _u(12) +#define POWMAN_EXT_CTRL0_INIT_STATE_LSB _u(12) +#define POWMAN_EXT_CTRL0_INIT_STATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL0_INIT +#define POWMAN_EXT_CTRL0_INIT_RESET _u(0x0) +#define POWMAN_EXT_CTRL0_INIT_BITS _u(0x00000100) +#define POWMAN_EXT_CTRL0_INIT_MSB _u(8) +#define POWMAN_EXT_CTRL0_INIT_LSB _u(8) +#define POWMAN_EXT_CTRL0_INIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL0_GPIO_SELECT +// Description : selects from gpio 0->30 +// set to 31 to disable this feature +#define POWMAN_EXT_CTRL0_GPIO_SELECT_RESET _u(0x3f) +#define POWMAN_EXT_CTRL0_GPIO_SELECT_BITS _u(0x0000003f) +#define POWMAN_EXT_CTRL0_GPIO_SELECT_MSB _u(5) +#define POWMAN_EXT_CTRL0_GPIO_SELECT_LSB _u(0) +#define POWMAN_EXT_CTRL0_GPIO_SELECT_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_EXT_CTRL1 +// Description : Configures a gpio as a power mode aware control output +#define POWMAN_EXT_CTRL1_OFFSET _u(0x00000048) +#define POWMAN_EXT_CTRL1_BITS _u(0x0000713f) +#define POWMAN_EXT_CTRL1_RESET _u(0x0000003f) +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL1_LP_EXIT_STATE +// Description : output level when exiting the low power state +#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_RESET _u(0x0) +#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_BITS _u(0x00004000) +#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_MSB _u(14) +#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_LSB _u(14) +#define POWMAN_EXT_CTRL1_LP_EXIT_STATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL1_LP_ENTRY_STATE +// Description : output level when entering the low power state +#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_RESET _u(0x0) +#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_BITS _u(0x00002000) +#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_MSB _u(13) +#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_LSB _u(13) +#define POWMAN_EXT_CTRL1_LP_ENTRY_STATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL1_INIT_STATE +#define POWMAN_EXT_CTRL1_INIT_STATE_RESET _u(0x0) +#define POWMAN_EXT_CTRL1_INIT_STATE_BITS _u(0x00001000) +#define POWMAN_EXT_CTRL1_INIT_STATE_MSB _u(12) +#define POWMAN_EXT_CTRL1_INIT_STATE_LSB _u(12) +#define POWMAN_EXT_CTRL1_INIT_STATE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL1_INIT +#define POWMAN_EXT_CTRL1_INIT_RESET _u(0x0) +#define POWMAN_EXT_CTRL1_INIT_BITS _u(0x00000100) +#define POWMAN_EXT_CTRL1_INIT_MSB _u(8) +#define POWMAN_EXT_CTRL1_INIT_LSB _u(8) +#define POWMAN_EXT_CTRL1_INIT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_CTRL1_GPIO_SELECT +// Description : selects from gpio 0->30 +// set to 31 to disable this feature +#define POWMAN_EXT_CTRL1_GPIO_SELECT_RESET _u(0x3f) +#define POWMAN_EXT_CTRL1_GPIO_SELECT_BITS _u(0x0000003f) +#define POWMAN_EXT_CTRL1_GPIO_SELECT_MSB _u(5) +#define POWMAN_EXT_CTRL1_GPIO_SELECT_LSB _u(0) +#define POWMAN_EXT_CTRL1_GPIO_SELECT_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_EXT_TIME_REF +// Description : Select a GPIO to use as a time reference, the source can be +// used to drive the low power clock at 32kHz, or to provide a 1ms +// tick to the timer, or provide a 1Hz tick to the timer. The tick +// selection is controlled by the POWMAN_TIMER register. +#define POWMAN_EXT_TIME_REF_OFFSET _u(0x0000004c) +#define POWMAN_EXT_TIME_REF_BITS _u(0x00000013) +#define POWMAN_EXT_TIME_REF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_TIME_REF_DRIVE_LPCK +// Description : Use the selected GPIO to drive the 32kHz low power clock, in +// place of LPOSC. This field must only be written when +// POWMAN_TIMER_RUN=0 +#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_RESET _u(0x0) +#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_BITS _u(0x00000010) +#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_MSB _u(4) +#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_LSB _u(4) +#define POWMAN_EXT_TIME_REF_DRIVE_LPCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_EXT_TIME_REF_SOURCE_SEL +// Description : 0 -> gpio12 +// 1 -> gpio20 +// 2 -> gpio14 +// 3 -> gpio22 +#define POWMAN_EXT_TIME_REF_SOURCE_SEL_RESET _u(0x0) +#define POWMAN_EXT_TIME_REF_SOURCE_SEL_BITS _u(0x00000003) +#define POWMAN_EXT_TIME_REF_SOURCE_SEL_MSB _u(1) +#define POWMAN_EXT_TIME_REF_SOURCE_SEL_LSB _u(0) +#define POWMAN_EXT_TIME_REF_SOURCE_SEL_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_LPOSC_FREQ_KHZ_INT +// Description : Informs the AON Timer of the integer component of the clock +// frequency when running off the LPOSC. +// Integer component of the LPOSC or GPIO clock source frequency +// in kHz. Default = 32 This field must only be written when +// POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 +#define POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET _u(0x00000050) +#define POWMAN_LPOSC_FREQ_KHZ_INT_BITS _u(0x0000003f) +#define POWMAN_LPOSC_FREQ_KHZ_INT_RESET _u(0x00000020) +#define POWMAN_LPOSC_FREQ_KHZ_INT_MSB _u(5) +#define POWMAN_LPOSC_FREQ_KHZ_INT_LSB _u(0) +#define POWMAN_LPOSC_FREQ_KHZ_INT_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_LPOSC_FREQ_KHZ_FRAC +// Description : Informs the AON Timer of the fractional component of the clock +// frequency when running off the LPOSC. +// Fractional component of the LPOSC or GPIO clock source +// frequency in kHz. Default = 0.768 This field must only be +// written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 +#define POWMAN_LPOSC_FREQ_KHZ_FRAC_OFFSET _u(0x00000054) +#define POWMAN_LPOSC_FREQ_KHZ_FRAC_BITS _u(0x0000ffff) +#define POWMAN_LPOSC_FREQ_KHZ_FRAC_RESET _u(0x0000c49c) +#define POWMAN_LPOSC_FREQ_KHZ_FRAC_MSB _u(15) +#define POWMAN_LPOSC_FREQ_KHZ_FRAC_LSB _u(0) +#define POWMAN_LPOSC_FREQ_KHZ_FRAC_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_XOSC_FREQ_KHZ_INT +// Description : Informs the AON Timer of the integer component of the clock +// frequency when running off the XOSC. +// Integer component of the XOSC frequency in kHz. Default = 12000 +// Must be >1 This field must only be written when +// POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 +#define POWMAN_XOSC_FREQ_KHZ_INT_OFFSET _u(0x00000058) +#define POWMAN_XOSC_FREQ_KHZ_INT_BITS _u(0x0000ffff) +#define POWMAN_XOSC_FREQ_KHZ_INT_RESET _u(0x00002ee0) +#define POWMAN_XOSC_FREQ_KHZ_INT_MSB _u(15) +#define POWMAN_XOSC_FREQ_KHZ_INT_LSB _u(0) +#define POWMAN_XOSC_FREQ_KHZ_INT_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_XOSC_FREQ_KHZ_FRAC +// Description : Informs the AON Timer of the fractional component of the clock +// frequency when running off the XOSC. +// Fractional component of the XOSC frequency in kHz. This field +// must only be written when POWMAN_TIMER_RUN=0 or +// POWMAN_TIMER_USING_XOSC=0 +#define POWMAN_XOSC_FREQ_KHZ_FRAC_OFFSET _u(0x0000005c) +#define POWMAN_XOSC_FREQ_KHZ_FRAC_BITS _u(0x0000ffff) +#define POWMAN_XOSC_FREQ_KHZ_FRAC_RESET _u(0x00000000) +#define POWMAN_XOSC_FREQ_KHZ_FRAC_MSB _u(15) +#define POWMAN_XOSC_FREQ_KHZ_FRAC_LSB _u(0) +#define POWMAN_XOSC_FREQ_KHZ_FRAC_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SET_TIME_63TO48 +// Description : None +// For setting the time, do not use for reading the time, use +// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field +// must only be written when POWMAN_TIMER_RUN=0 +#define POWMAN_SET_TIME_63TO48_OFFSET _u(0x00000060) +#define POWMAN_SET_TIME_63TO48_BITS _u(0x0000ffff) +#define POWMAN_SET_TIME_63TO48_RESET _u(0x00000000) +#define POWMAN_SET_TIME_63TO48_MSB _u(15) +#define POWMAN_SET_TIME_63TO48_LSB _u(0) +#define POWMAN_SET_TIME_63TO48_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SET_TIME_47TO32 +// Description : None +// For setting the time, do not use for reading the time, use +// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field +// must only be written when POWMAN_TIMER_RUN=0 +#define POWMAN_SET_TIME_47TO32_OFFSET _u(0x00000064) +#define POWMAN_SET_TIME_47TO32_BITS _u(0x0000ffff) +#define POWMAN_SET_TIME_47TO32_RESET _u(0x00000000) +#define POWMAN_SET_TIME_47TO32_MSB _u(15) +#define POWMAN_SET_TIME_47TO32_LSB _u(0) +#define POWMAN_SET_TIME_47TO32_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SET_TIME_31TO16 +// Description : None +// For setting the time, do not use for reading the time, use +// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field +// must only be written when POWMAN_TIMER_RUN=0 +#define POWMAN_SET_TIME_31TO16_OFFSET _u(0x00000068) +#define POWMAN_SET_TIME_31TO16_BITS _u(0x0000ffff) +#define POWMAN_SET_TIME_31TO16_RESET _u(0x00000000) +#define POWMAN_SET_TIME_31TO16_MSB _u(15) +#define POWMAN_SET_TIME_31TO16_LSB _u(0) +#define POWMAN_SET_TIME_31TO16_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SET_TIME_15TO0 +// Description : None +// For setting the time, do not use for reading the time, use +// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field +// must only be written when POWMAN_TIMER_RUN=0 +#define POWMAN_SET_TIME_15TO0_OFFSET _u(0x0000006c) +#define POWMAN_SET_TIME_15TO0_BITS _u(0x0000ffff) +#define POWMAN_SET_TIME_15TO0_RESET _u(0x00000000) +#define POWMAN_SET_TIME_15TO0_MSB _u(15) +#define POWMAN_SET_TIME_15TO0_LSB _u(0) +#define POWMAN_SET_TIME_15TO0_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_READ_TIME_UPPER +// Description : None +// For reading bits 63:32 of the timer. When reading all 64 bits +// it is possible for the LOWER count to rollover during the read. +// It is recommended to read UPPER, then LOWER, then re-read UPPER +// and, if it has changed, re-read LOWER. +#define POWMAN_READ_TIME_UPPER_OFFSET _u(0x00000070) +#define POWMAN_READ_TIME_UPPER_BITS _u(0xffffffff) +#define POWMAN_READ_TIME_UPPER_RESET _u(0x00000000) +#define POWMAN_READ_TIME_UPPER_MSB _u(31) +#define POWMAN_READ_TIME_UPPER_LSB _u(0) +#define POWMAN_READ_TIME_UPPER_ACCESS "RO" +// ============================================================================= +// Register : POWMAN_READ_TIME_LOWER +// Description : None +// For reading bits 31:0 of the timer. +#define POWMAN_READ_TIME_LOWER_OFFSET _u(0x00000074) +#define POWMAN_READ_TIME_LOWER_BITS _u(0xffffffff) +#define POWMAN_READ_TIME_LOWER_RESET _u(0x00000000) +#define POWMAN_READ_TIME_LOWER_MSB _u(31) +#define POWMAN_READ_TIME_LOWER_LSB _u(0) +#define POWMAN_READ_TIME_LOWER_ACCESS "RO" +// ============================================================================= +// Register : POWMAN_ALARM_TIME_63TO48 +// Description : None +// This field must only be written when POWMAN_ALARM_ENAB=0 +#define POWMAN_ALARM_TIME_63TO48_OFFSET _u(0x00000078) +#define POWMAN_ALARM_TIME_63TO48_BITS _u(0x0000ffff) +#define POWMAN_ALARM_TIME_63TO48_RESET _u(0x00000000) +#define POWMAN_ALARM_TIME_63TO48_MSB _u(15) +#define POWMAN_ALARM_TIME_63TO48_LSB _u(0) +#define POWMAN_ALARM_TIME_63TO48_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_ALARM_TIME_47TO32 +// Description : None +// This field must only be written when POWMAN_ALARM_ENAB=0 +#define POWMAN_ALARM_TIME_47TO32_OFFSET _u(0x0000007c) +#define POWMAN_ALARM_TIME_47TO32_BITS _u(0x0000ffff) +#define POWMAN_ALARM_TIME_47TO32_RESET _u(0x00000000) +#define POWMAN_ALARM_TIME_47TO32_MSB _u(15) +#define POWMAN_ALARM_TIME_47TO32_LSB _u(0) +#define POWMAN_ALARM_TIME_47TO32_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_ALARM_TIME_31TO16 +// Description : None +// This field must only be written when POWMAN_ALARM_ENAB=0 +#define POWMAN_ALARM_TIME_31TO16_OFFSET _u(0x00000080) +#define POWMAN_ALARM_TIME_31TO16_BITS _u(0x0000ffff) +#define POWMAN_ALARM_TIME_31TO16_RESET _u(0x00000000) +#define POWMAN_ALARM_TIME_31TO16_MSB _u(15) +#define POWMAN_ALARM_TIME_31TO16_LSB _u(0) +#define POWMAN_ALARM_TIME_31TO16_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_ALARM_TIME_15TO0 +// Description : None +// This field must only be written when POWMAN_ALARM_ENAB=0 +#define POWMAN_ALARM_TIME_15TO0_OFFSET _u(0x00000084) +#define POWMAN_ALARM_TIME_15TO0_BITS _u(0x0000ffff) +#define POWMAN_ALARM_TIME_15TO0_RESET _u(0x00000000) +#define POWMAN_ALARM_TIME_15TO0_MSB _u(15) +#define POWMAN_ALARM_TIME_15TO0_LSB _u(0) +#define POWMAN_ALARM_TIME_15TO0_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_TIMER +#define POWMAN_TIMER_OFFSET _u(0x00000088) +#define POWMAN_TIMER_BITS _u(0x000f2777) +#define POWMAN_TIMER_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USING_GPIO_1HZ +// Description : Timer is synchronised to a 1hz gpio source +#define POWMAN_TIMER_USING_GPIO_1HZ_RESET _u(0x0) +#define POWMAN_TIMER_USING_GPIO_1HZ_BITS _u(0x00080000) +#define POWMAN_TIMER_USING_GPIO_1HZ_MSB _u(19) +#define POWMAN_TIMER_USING_GPIO_1HZ_LSB _u(19) +#define POWMAN_TIMER_USING_GPIO_1HZ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USING_GPIO_1KHZ +// Description : Timer is running from a 1khz gpio source +#define POWMAN_TIMER_USING_GPIO_1KHZ_RESET _u(0x0) +#define POWMAN_TIMER_USING_GPIO_1KHZ_BITS _u(0x00040000) +#define POWMAN_TIMER_USING_GPIO_1KHZ_MSB _u(18) +#define POWMAN_TIMER_USING_GPIO_1KHZ_LSB _u(18) +#define POWMAN_TIMER_USING_GPIO_1KHZ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USING_LPOSC +// Description : Timer is running from lposc +#define POWMAN_TIMER_USING_LPOSC_RESET _u(0x0) +#define POWMAN_TIMER_USING_LPOSC_BITS _u(0x00020000) +#define POWMAN_TIMER_USING_LPOSC_MSB _u(17) +#define POWMAN_TIMER_USING_LPOSC_LSB _u(17) +#define POWMAN_TIMER_USING_LPOSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USING_XOSC +// Description : Timer is running from xosc +#define POWMAN_TIMER_USING_XOSC_RESET _u(0x0) +#define POWMAN_TIMER_USING_XOSC_BITS _u(0x00010000) +#define POWMAN_TIMER_USING_XOSC_MSB _u(16) +#define POWMAN_TIMER_USING_XOSC_LSB _u(16) +#define POWMAN_TIMER_USING_XOSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USE_GPIO_1HZ +// Description : Selects the gpio source as the reference for the sec counter. +// The msec counter will continue to use the lposc or xosc +// reference. +#define POWMAN_TIMER_USE_GPIO_1HZ_RESET _u(0x0) +#define POWMAN_TIMER_USE_GPIO_1HZ_BITS _u(0x00002000) +#define POWMAN_TIMER_USE_GPIO_1HZ_MSB _u(13) +#define POWMAN_TIMER_USE_GPIO_1HZ_LSB _u(13) +#define POWMAN_TIMER_USE_GPIO_1HZ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USE_GPIO_1KHZ +// Description : switch to gpio as the source of the 1kHz timer tick +#define POWMAN_TIMER_USE_GPIO_1KHZ_RESET _u(0x0) +#define POWMAN_TIMER_USE_GPIO_1KHZ_BITS _u(0x00000400) +#define POWMAN_TIMER_USE_GPIO_1KHZ_MSB _u(10) +#define POWMAN_TIMER_USE_GPIO_1KHZ_LSB _u(10) +#define POWMAN_TIMER_USE_GPIO_1KHZ_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USE_XOSC +// Description : switch to xosc as the source of the 1kHz timer tick +#define POWMAN_TIMER_USE_XOSC_RESET _u(0x0) +#define POWMAN_TIMER_USE_XOSC_BITS _u(0x00000200) +#define POWMAN_TIMER_USE_XOSC_MSB _u(9) +#define POWMAN_TIMER_USE_XOSC_LSB _u(9) +#define POWMAN_TIMER_USE_XOSC_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_USE_LPOSC +// Description : Switch to lposc as the source of the 1kHz timer tick +#define POWMAN_TIMER_USE_LPOSC_RESET _u(0x0) +#define POWMAN_TIMER_USE_LPOSC_BITS _u(0x00000100) +#define POWMAN_TIMER_USE_LPOSC_MSB _u(8) +#define POWMAN_TIMER_USE_LPOSC_LSB _u(8) +#define POWMAN_TIMER_USE_LPOSC_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_ALARM +// Description : Alarm has fired. Write to 1 to clear the alarm. +#define POWMAN_TIMER_ALARM_RESET _u(0x0) +#define POWMAN_TIMER_ALARM_BITS _u(0x00000040) +#define POWMAN_TIMER_ALARM_MSB _u(6) +#define POWMAN_TIMER_ALARM_LSB _u(6) +#define POWMAN_TIMER_ALARM_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_PWRUP_ON_ALARM +// Description : Alarm wakes the chip from low power mode +#define POWMAN_TIMER_PWRUP_ON_ALARM_RESET _u(0x0) +#define POWMAN_TIMER_PWRUP_ON_ALARM_BITS _u(0x00000020) +#define POWMAN_TIMER_PWRUP_ON_ALARM_MSB _u(5) +#define POWMAN_TIMER_PWRUP_ON_ALARM_LSB _u(5) +#define POWMAN_TIMER_PWRUP_ON_ALARM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_ALARM_ENAB +// Description : Enables the alarm. The alarm must be disabled while writing the +// alarm time. +#define POWMAN_TIMER_ALARM_ENAB_RESET _u(0x0) +#define POWMAN_TIMER_ALARM_ENAB_BITS _u(0x00000010) +#define POWMAN_TIMER_ALARM_ENAB_MSB _u(4) +#define POWMAN_TIMER_ALARM_ENAB_LSB _u(4) +#define POWMAN_TIMER_ALARM_ENAB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_CLEAR +// Description : Clears the timer, does not disable the timer and does not +// affect the alarm. This control can be written at any time. +#define POWMAN_TIMER_CLEAR_RESET _u(0x0) +#define POWMAN_TIMER_CLEAR_BITS _u(0x00000004) +#define POWMAN_TIMER_CLEAR_MSB _u(2) +#define POWMAN_TIMER_CLEAR_LSB _u(2) +#define POWMAN_TIMER_CLEAR_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_RUN +// Description : Timer enable. Setting this bit causes the timer to begin +// counting up from its current value. Clearing this bit stops the +// timer from counting. +// +// Before enabling the timer, set the POWMAN_LPOSC_FREQ* and +// POWMAN_XOSC_FREQ* registers to configure the count rate, and +// initialise the current time by writing to SET_TIME_63TO48 +// through SET_TIME_15TO0. You must not write to the SET_TIME_x +// registers when the timer is running. +// +// Once configured, start the timer by setting POWMAN_TIMER_RUN=1. +// This will start the timer running from the LPOSC. When the XOSC +// is available switch the reference clock to XOSC then select it +// as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 +#define POWMAN_TIMER_RUN_RESET _u(0x0) +#define POWMAN_TIMER_RUN_BITS _u(0x00000002) +#define POWMAN_TIMER_RUN_MSB _u(1) +#define POWMAN_TIMER_RUN_LSB _u(1) +#define POWMAN_TIMER_RUN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_TIMER_NONSEC_WRITE +// Description : Control whether Non-secure software can write to the timer +// registers. All other registers are hardwired to be inaccessible +// to Non-secure. +#define POWMAN_TIMER_NONSEC_WRITE_RESET _u(0x0) +#define POWMAN_TIMER_NONSEC_WRITE_BITS _u(0x00000001) +#define POWMAN_TIMER_NONSEC_WRITE_MSB _u(0) +#define POWMAN_TIMER_NONSEC_WRITE_LSB _u(0) +#define POWMAN_TIMER_NONSEC_WRITE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_PWRUP0 +// Description : 4 GPIO powerup events can be configured to wake the chip up +// from a low power state. +// The pwrups are level/edge sensitive and can be set to trigger +// on a high/rising or low/falling event +// The number of gpios available depends on the package option. An +// invalid selection will be ignored +// source = 0 selects gpio0 +// . +// . +// source = 47 selects gpio47 +// source = 48 selects qspi_ss +// source = 49 selects qspi_sd0 +// source = 50 selects qspi_sd1 +// source = 51 selects qspi_sd2 +// source = 52 selects qspi_sd3 +// source = 53 selects qspi_sclk +// level = 0 triggers the pwrup when the source is low +// level = 1 triggers the pwrup when the source is high +#define POWMAN_PWRUP0_OFFSET _u(0x0000008c) +#define POWMAN_PWRUP0_BITS _u(0x000007ff) +#define POWMAN_PWRUP0_RESET _u(0x0000003f) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP0_RAW_STATUS +// Description : Value of selected gpio pin (only if enable == 1) +#define POWMAN_PWRUP0_RAW_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP0_RAW_STATUS_BITS _u(0x00000400) +#define POWMAN_PWRUP0_RAW_STATUS_MSB _u(10) +#define POWMAN_PWRUP0_RAW_STATUS_LSB _u(10) +#define POWMAN_PWRUP0_RAW_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP0_STATUS +// Description : Status of gpio wakeup. Write to 1 to clear a latched edge +// detect. +#define POWMAN_PWRUP0_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP0_STATUS_BITS _u(0x00000200) +#define POWMAN_PWRUP0_STATUS_MSB _u(9) +#define POWMAN_PWRUP0_STATUS_LSB _u(9) +#define POWMAN_PWRUP0_STATUS_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP0_MODE +// Description : Edge or level detect. Edge will detect a 0 to 1 transition (or +// 1 to 0 transition). Level will detect a 1 or 0. Both types of +// event get latched into the current_pwrup_req register. +// 0x0 -> level +// 0x1 -> edge +#define POWMAN_PWRUP0_MODE_RESET _u(0x0) +#define POWMAN_PWRUP0_MODE_BITS _u(0x00000100) +#define POWMAN_PWRUP0_MODE_MSB _u(8) +#define POWMAN_PWRUP0_MODE_LSB _u(8) +#define POWMAN_PWRUP0_MODE_ACCESS "RW" +#define POWMAN_PWRUP0_MODE_VALUE_LEVEL _u(0x0) +#define POWMAN_PWRUP0_MODE_VALUE_EDGE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP0_DIRECTION +// 0x0 -> low_falling +// 0x1 -> high_rising +#define POWMAN_PWRUP0_DIRECTION_RESET _u(0x0) +#define POWMAN_PWRUP0_DIRECTION_BITS _u(0x00000080) +#define POWMAN_PWRUP0_DIRECTION_MSB _u(7) +#define POWMAN_PWRUP0_DIRECTION_LSB _u(7) +#define POWMAN_PWRUP0_DIRECTION_ACCESS "RW" +#define POWMAN_PWRUP0_DIRECTION_VALUE_LOW_FALLING _u(0x0) +#define POWMAN_PWRUP0_DIRECTION_VALUE_HIGH_RISING _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP0_ENABLE +// Description : Set to 1 to enable the wakeup source. Set to 0 to disable the +// wakeup source and clear a pending wakeup event. +// If using edge detect a latched edge needs to be cleared by +// writing 1 to the status register also. +#define POWMAN_PWRUP0_ENABLE_RESET _u(0x0) +#define POWMAN_PWRUP0_ENABLE_BITS _u(0x00000040) +#define POWMAN_PWRUP0_ENABLE_MSB _u(6) +#define POWMAN_PWRUP0_ENABLE_LSB _u(6) +#define POWMAN_PWRUP0_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP0_SOURCE +#define POWMAN_PWRUP0_SOURCE_RESET _u(0x3f) +#define POWMAN_PWRUP0_SOURCE_BITS _u(0x0000003f) +#define POWMAN_PWRUP0_SOURCE_MSB _u(5) +#define POWMAN_PWRUP0_SOURCE_LSB _u(0) +#define POWMAN_PWRUP0_SOURCE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_PWRUP1 +// Description : 4 GPIO powerup events can be configured to wake the chip up +// from a low power state. +// The pwrups are level/edge sensitive and can be set to trigger +// on a high/rising or low/falling event +// The number of gpios available depends on the package option. An +// invalid selection will be ignored +// source = 0 selects gpio0 +// . +// . +// source = 47 selects gpio47 +// source = 48 selects qspi_ss +// source = 49 selects qspi_sd0 +// source = 50 selects qspi_sd1 +// source = 51 selects qspi_sd2 +// source = 52 selects qspi_sd3 +// source = 53 selects qspi_sclk +// level = 0 triggers the pwrup when the source is low +// level = 1 triggers the pwrup when the source is high +#define POWMAN_PWRUP1_OFFSET _u(0x00000090) +#define POWMAN_PWRUP1_BITS _u(0x000007ff) +#define POWMAN_PWRUP1_RESET _u(0x0000003f) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP1_RAW_STATUS +// Description : Value of selected gpio pin (only if enable == 1) +#define POWMAN_PWRUP1_RAW_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP1_RAW_STATUS_BITS _u(0x00000400) +#define POWMAN_PWRUP1_RAW_STATUS_MSB _u(10) +#define POWMAN_PWRUP1_RAW_STATUS_LSB _u(10) +#define POWMAN_PWRUP1_RAW_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP1_STATUS +// Description : Status of gpio wakeup. Write to 1 to clear a latched edge +// detect. +#define POWMAN_PWRUP1_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP1_STATUS_BITS _u(0x00000200) +#define POWMAN_PWRUP1_STATUS_MSB _u(9) +#define POWMAN_PWRUP1_STATUS_LSB _u(9) +#define POWMAN_PWRUP1_STATUS_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP1_MODE +// Description : Edge or level detect. Edge will detect a 0 to 1 transition (or +// 1 to 0 transition). Level will detect a 1 or 0. Both types of +// event get latched into the current_pwrup_req register. +// 0x0 -> level +// 0x1 -> edge +#define POWMAN_PWRUP1_MODE_RESET _u(0x0) +#define POWMAN_PWRUP1_MODE_BITS _u(0x00000100) +#define POWMAN_PWRUP1_MODE_MSB _u(8) +#define POWMAN_PWRUP1_MODE_LSB _u(8) +#define POWMAN_PWRUP1_MODE_ACCESS "RW" +#define POWMAN_PWRUP1_MODE_VALUE_LEVEL _u(0x0) +#define POWMAN_PWRUP1_MODE_VALUE_EDGE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP1_DIRECTION +// 0x0 -> low_falling +// 0x1 -> high_rising +#define POWMAN_PWRUP1_DIRECTION_RESET _u(0x0) +#define POWMAN_PWRUP1_DIRECTION_BITS _u(0x00000080) +#define POWMAN_PWRUP1_DIRECTION_MSB _u(7) +#define POWMAN_PWRUP1_DIRECTION_LSB _u(7) +#define POWMAN_PWRUP1_DIRECTION_ACCESS "RW" +#define POWMAN_PWRUP1_DIRECTION_VALUE_LOW_FALLING _u(0x0) +#define POWMAN_PWRUP1_DIRECTION_VALUE_HIGH_RISING _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP1_ENABLE +// Description : Set to 1 to enable the wakeup source. Set to 0 to disable the +// wakeup source and clear a pending wakeup event. +// If using edge detect a latched edge needs to be cleared by +// writing 1 to the status register also. +#define POWMAN_PWRUP1_ENABLE_RESET _u(0x0) +#define POWMAN_PWRUP1_ENABLE_BITS _u(0x00000040) +#define POWMAN_PWRUP1_ENABLE_MSB _u(6) +#define POWMAN_PWRUP1_ENABLE_LSB _u(6) +#define POWMAN_PWRUP1_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP1_SOURCE +#define POWMAN_PWRUP1_SOURCE_RESET _u(0x3f) +#define POWMAN_PWRUP1_SOURCE_BITS _u(0x0000003f) +#define POWMAN_PWRUP1_SOURCE_MSB _u(5) +#define POWMAN_PWRUP1_SOURCE_LSB _u(0) +#define POWMAN_PWRUP1_SOURCE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_PWRUP2 +// Description : 4 GPIO powerup events can be configured to wake the chip up +// from a low power state. +// The pwrups are level/edge sensitive and can be set to trigger +// on a high/rising or low/falling event +// The number of gpios available depends on the package option. An +// invalid selection will be ignored +// source = 0 selects gpio0 +// . +// . +// source = 47 selects gpio47 +// source = 48 selects qspi_ss +// source = 49 selects qspi_sd0 +// source = 50 selects qspi_sd1 +// source = 51 selects qspi_sd2 +// source = 52 selects qspi_sd3 +// source = 53 selects qspi_sclk +// level = 0 triggers the pwrup when the source is low +// level = 1 triggers the pwrup when the source is high +#define POWMAN_PWRUP2_OFFSET _u(0x00000094) +#define POWMAN_PWRUP2_BITS _u(0x000007ff) +#define POWMAN_PWRUP2_RESET _u(0x0000003f) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP2_RAW_STATUS +// Description : Value of selected gpio pin (only if enable == 1) +#define POWMAN_PWRUP2_RAW_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP2_RAW_STATUS_BITS _u(0x00000400) +#define POWMAN_PWRUP2_RAW_STATUS_MSB _u(10) +#define POWMAN_PWRUP2_RAW_STATUS_LSB _u(10) +#define POWMAN_PWRUP2_RAW_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP2_STATUS +// Description : Status of gpio wakeup. Write to 1 to clear a latched edge +// detect. +#define POWMAN_PWRUP2_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP2_STATUS_BITS _u(0x00000200) +#define POWMAN_PWRUP2_STATUS_MSB _u(9) +#define POWMAN_PWRUP2_STATUS_LSB _u(9) +#define POWMAN_PWRUP2_STATUS_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP2_MODE +// Description : Edge or level detect. Edge will detect a 0 to 1 transition (or +// 1 to 0 transition). Level will detect a 1 or 0. Both types of +// event get latched into the current_pwrup_req register. +// 0x0 -> level +// 0x1 -> edge +#define POWMAN_PWRUP2_MODE_RESET _u(0x0) +#define POWMAN_PWRUP2_MODE_BITS _u(0x00000100) +#define POWMAN_PWRUP2_MODE_MSB _u(8) +#define POWMAN_PWRUP2_MODE_LSB _u(8) +#define POWMAN_PWRUP2_MODE_ACCESS "RW" +#define POWMAN_PWRUP2_MODE_VALUE_LEVEL _u(0x0) +#define POWMAN_PWRUP2_MODE_VALUE_EDGE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP2_DIRECTION +// 0x0 -> low_falling +// 0x1 -> high_rising +#define POWMAN_PWRUP2_DIRECTION_RESET _u(0x0) +#define POWMAN_PWRUP2_DIRECTION_BITS _u(0x00000080) +#define POWMAN_PWRUP2_DIRECTION_MSB _u(7) +#define POWMAN_PWRUP2_DIRECTION_LSB _u(7) +#define POWMAN_PWRUP2_DIRECTION_ACCESS "RW" +#define POWMAN_PWRUP2_DIRECTION_VALUE_LOW_FALLING _u(0x0) +#define POWMAN_PWRUP2_DIRECTION_VALUE_HIGH_RISING _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP2_ENABLE +// Description : Set to 1 to enable the wakeup source. Set to 0 to disable the +// wakeup source and clear a pending wakeup event. +// If using edge detect a latched edge needs to be cleared by +// writing 1 to the status register also. +#define POWMAN_PWRUP2_ENABLE_RESET _u(0x0) +#define POWMAN_PWRUP2_ENABLE_BITS _u(0x00000040) +#define POWMAN_PWRUP2_ENABLE_MSB _u(6) +#define POWMAN_PWRUP2_ENABLE_LSB _u(6) +#define POWMAN_PWRUP2_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP2_SOURCE +#define POWMAN_PWRUP2_SOURCE_RESET _u(0x3f) +#define POWMAN_PWRUP2_SOURCE_BITS _u(0x0000003f) +#define POWMAN_PWRUP2_SOURCE_MSB _u(5) +#define POWMAN_PWRUP2_SOURCE_LSB _u(0) +#define POWMAN_PWRUP2_SOURCE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_PWRUP3 +// Description : 4 GPIO powerup events can be configured to wake the chip up +// from a low power state. +// The pwrups are level/edge sensitive and can be set to trigger +// on a high/rising or low/falling event +// The number of gpios available depends on the package option. An +// invalid selection will be ignored +// source = 0 selects gpio0 +// . +// . +// source = 47 selects gpio47 +// source = 48 selects qspi_ss +// source = 49 selects qspi_sd0 +// source = 50 selects qspi_sd1 +// source = 51 selects qspi_sd2 +// source = 52 selects qspi_sd3 +// source = 53 selects qspi_sclk +// level = 0 triggers the pwrup when the source is low +// level = 1 triggers the pwrup when the source is high +#define POWMAN_PWRUP3_OFFSET _u(0x00000098) +#define POWMAN_PWRUP3_BITS _u(0x000007ff) +#define POWMAN_PWRUP3_RESET _u(0x0000003f) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP3_RAW_STATUS +// Description : Value of selected gpio pin (only if enable == 1) +#define POWMAN_PWRUP3_RAW_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP3_RAW_STATUS_BITS _u(0x00000400) +#define POWMAN_PWRUP3_RAW_STATUS_MSB _u(10) +#define POWMAN_PWRUP3_RAW_STATUS_LSB _u(10) +#define POWMAN_PWRUP3_RAW_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP3_STATUS +// Description : Status of gpio wakeup. Write to 1 to clear a latched edge +// detect. +#define POWMAN_PWRUP3_STATUS_RESET _u(0x0) +#define POWMAN_PWRUP3_STATUS_BITS _u(0x00000200) +#define POWMAN_PWRUP3_STATUS_MSB _u(9) +#define POWMAN_PWRUP3_STATUS_LSB _u(9) +#define POWMAN_PWRUP3_STATUS_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP3_MODE +// Description : Edge or level detect. Edge will detect a 0 to 1 transition (or +// 1 to 0 transition). Level will detect a 1 or 0. Both types of +// event get latched into the current_pwrup_req register. +// 0x0 -> level +// 0x1 -> edge +#define POWMAN_PWRUP3_MODE_RESET _u(0x0) +#define POWMAN_PWRUP3_MODE_BITS _u(0x00000100) +#define POWMAN_PWRUP3_MODE_MSB _u(8) +#define POWMAN_PWRUP3_MODE_LSB _u(8) +#define POWMAN_PWRUP3_MODE_ACCESS "RW" +#define POWMAN_PWRUP3_MODE_VALUE_LEVEL _u(0x0) +#define POWMAN_PWRUP3_MODE_VALUE_EDGE _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP3_DIRECTION +// 0x0 -> low_falling +// 0x1 -> high_rising +#define POWMAN_PWRUP3_DIRECTION_RESET _u(0x0) +#define POWMAN_PWRUP3_DIRECTION_BITS _u(0x00000080) +#define POWMAN_PWRUP3_DIRECTION_MSB _u(7) +#define POWMAN_PWRUP3_DIRECTION_LSB _u(7) +#define POWMAN_PWRUP3_DIRECTION_ACCESS "RW" +#define POWMAN_PWRUP3_DIRECTION_VALUE_LOW_FALLING _u(0x0) +#define POWMAN_PWRUP3_DIRECTION_VALUE_HIGH_RISING _u(0x1) +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP3_ENABLE +// Description : Set to 1 to enable the wakeup source. Set to 0 to disable the +// wakeup source and clear a pending wakeup event. +// If using edge detect a latched edge needs to be cleared by +// writing 1 to the status register also. +#define POWMAN_PWRUP3_ENABLE_RESET _u(0x0) +#define POWMAN_PWRUP3_ENABLE_BITS _u(0x00000040) +#define POWMAN_PWRUP3_ENABLE_MSB _u(6) +#define POWMAN_PWRUP3_ENABLE_LSB _u(6) +#define POWMAN_PWRUP3_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_PWRUP3_SOURCE +#define POWMAN_PWRUP3_SOURCE_RESET _u(0x3f) +#define POWMAN_PWRUP3_SOURCE_BITS _u(0x0000003f) +#define POWMAN_PWRUP3_SOURCE_MSB _u(5) +#define POWMAN_PWRUP3_SOURCE_LSB _u(0) +#define POWMAN_PWRUP3_SOURCE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_CURRENT_PWRUP_REQ +// Description : Indicates current powerup request state +// pwrup events can be cleared by removing the enable from the +// pwrup register. The alarm pwrup req can be cleared by clearing +// timer.alarm_enab +// 0 = chip reset, for the source of the last reset see +// POWMAN_CHIP_RESET +// 1 = pwrup0 +// 2 = pwrup1 +// 3 = pwrup2 +// 4 = pwrup3 +// 5 = coresight_pwrup +// 6 = alarm_pwrup +#define POWMAN_CURRENT_PWRUP_REQ_OFFSET _u(0x0000009c) +#define POWMAN_CURRENT_PWRUP_REQ_BITS _u(0x0000007f) +#define POWMAN_CURRENT_PWRUP_REQ_RESET _u(0x00000000) +#define POWMAN_CURRENT_PWRUP_REQ_MSB _u(6) +#define POWMAN_CURRENT_PWRUP_REQ_LSB _u(0) +#define POWMAN_CURRENT_PWRUP_REQ_ACCESS "RO" +// ============================================================================= +// Register : POWMAN_LAST_SWCORE_PWRUP +// Description : Indicates which pwrup source triggered the last switched-core +// power up +// 0 = chip reset, for the source of the last reset see +// POWMAN_CHIP_RESET +// 1 = pwrup0 +// 2 = pwrup1 +// 3 = pwrup2 +// 4 = pwrup3 +// 5 = coresight_pwrup +// 6 = alarm_pwrup +#define POWMAN_LAST_SWCORE_PWRUP_OFFSET _u(0x000000a0) +#define POWMAN_LAST_SWCORE_PWRUP_BITS _u(0x0000007f) +#define POWMAN_LAST_SWCORE_PWRUP_RESET _u(0x00000000) +#define POWMAN_LAST_SWCORE_PWRUP_MSB _u(6) +#define POWMAN_LAST_SWCORE_PWRUP_LSB _u(0) +#define POWMAN_LAST_SWCORE_PWRUP_ACCESS "RO" +// ============================================================================= +// Register : POWMAN_DBG_PWRCFG +#define POWMAN_DBG_PWRCFG_OFFSET _u(0x000000a4) +#define POWMAN_DBG_PWRCFG_BITS _u(0x00000001) +#define POWMAN_DBG_PWRCFG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_DBG_PWRCFG_IGNORE +// Description : Ignore pwrup req from debugger. If pwrup req is asserted then +// this will prevent power down and set powerdown blocked. Set +// ignore to stop paying attention to pwrup_req +#define POWMAN_DBG_PWRCFG_IGNORE_RESET _u(0x0) +#define POWMAN_DBG_PWRCFG_IGNORE_BITS _u(0x00000001) +#define POWMAN_DBG_PWRCFG_IGNORE_MSB _u(0) +#define POWMAN_DBG_PWRCFG_IGNORE_LSB _u(0) +#define POWMAN_DBG_PWRCFG_IGNORE_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOOTDIS +// Description : Tell the bootrom to ignore the BOOT0..3 registers following the +// next RSM reset (e.g. the next core power down/up). +// +// If an early boot stage has soft-locked some OTP pages in order +// to protect their contents from later stages, there is a risk +// that Secure code running at a later stage can unlock the pages +// by powering the core up and down. +// +// This register can be used to ensure that the bootloader runs as +// normal on the next power up, preventing Secure code at a later +// stage from accessing OTP in its unlocked state. +// +// Should be used in conjunction with the OTP BOOTDIS register. +#define POWMAN_BOOTDIS_OFFSET _u(0x000000a8) +#define POWMAN_BOOTDIS_BITS _u(0x00000003) +#define POWMAN_BOOTDIS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOOTDIS_NEXT +// Description : This flag always ORs writes into its current contents. It can +// be set but not cleared by software. +// +// The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the +// core is powered down. Simultaneously, the BOOTDIS_NEXT bit is +// cleared. Setting this bit means that the BOOT0..3 registers +// will be ignored following the next reset of the RSM by powman. +// +// This flag should be set by an early boot stage that has soft- +// locked OTP pages, to prevent later stages from unlocking it by +// power cycling. +#define POWMAN_BOOTDIS_NEXT_RESET _u(0x0) +#define POWMAN_BOOTDIS_NEXT_BITS _u(0x00000002) +#define POWMAN_BOOTDIS_NEXT_MSB _u(1) +#define POWMAN_BOOTDIS_NEXT_LSB _u(1) +#define POWMAN_BOOTDIS_NEXT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_BOOTDIS_NOW +// Description : When powman resets the RSM, the current value of BOOTDIS_NEXT +// is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. +// +// The bootrom checks this flag before reading the BOOT0..3 +// registers. If it is set, the bootrom clears it, and ignores the +// BOOT registers. This prevents Secure software from diverting +// the boot path before a bootloader has had the chance to soft +// lock OTP pages containing sensitive data. +#define POWMAN_BOOTDIS_NOW_RESET _u(0x0) +#define POWMAN_BOOTDIS_NOW_BITS _u(0x00000001) +#define POWMAN_BOOTDIS_NOW_MSB _u(0) +#define POWMAN_BOOTDIS_NOW_LSB _u(0) +#define POWMAN_BOOTDIS_NOW_ACCESS "WC" +// ============================================================================= +// Register : POWMAN_DBGCONFIG +#define POWMAN_DBGCONFIG_OFFSET _u(0x000000ac) +#define POWMAN_DBGCONFIG_BITS _u(0x0000000f) +#define POWMAN_DBGCONFIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_DBGCONFIG_DP_INSTID +// Description : Configure DP instance ID for SWD multidrop selection. +// Recommend that this is NOT changed until you require debug +// access in multi-chip environment +#define POWMAN_DBGCONFIG_DP_INSTID_RESET _u(0x0) +#define POWMAN_DBGCONFIG_DP_INSTID_BITS _u(0x0000000f) +#define POWMAN_DBGCONFIG_DP_INSTID_MSB _u(3) +#define POWMAN_DBGCONFIG_DP_INSTID_LSB _u(0) +#define POWMAN_DBGCONFIG_DP_INSTID_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH0 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH0_OFFSET _u(0x000000b0) +#define POWMAN_SCRATCH0_BITS _u(0xffffffff) +#define POWMAN_SCRATCH0_RESET _u(0x00000000) +#define POWMAN_SCRATCH0_MSB _u(31) +#define POWMAN_SCRATCH0_LSB _u(0) +#define POWMAN_SCRATCH0_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH1 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH1_OFFSET _u(0x000000b4) +#define POWMAN_SCRATCH1_BITS _u(0xffffffff) +#define POWMAN_SCRATCH1_RESET _u(0x00000000) +#define POWMAN_SCRATCH1_MSB _u(31) +#define POWMAN_SCRATCH1_LSB _u(0) +#define POWMAN_SCRATCH1_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH2 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH2_OFFSET _u(0x000000b8) +#define POWMAN_SCRATCH2_BITS _u(0xffffffff) +#define POWMAN_SCRATCH2_RESET _u(0x00000000) +#define POWMAN_SCRATCH2_MSB _u(31) +#define POWMAN_SCRATCH2_LSB _u(0) +#define POWMAN_SCRATCH2_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH3 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH3_OFFSET _u(0x000000bc) +#define POWMAN_SCRATCH3_BITS _u(0xffffffff) +#define POWMAN_SCRATCH3_RESET _u(0x00000000) +#define POWMAN_SCRATCH3_MSB _u(31) +#define POWMAN_SCRATCH3_LSB _u(0) +#define POWMAN_SCRATCH3_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH4 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH4_OFFSET _u(0x000000c0) +#define POWMAN_SCRATCH4_BITS _u(0xffffffff) +#define POWMAN_SCRATCH4_RESET _u(0x00000000) +#define POWMAN_SCRATCH4_MSB _u(31) +#define POWMAN_SCRATCH4_LSB _u(0) +#define POWMAN_SCRATCH4_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH5 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH5_OFFSET _u(0x000000c4) +#define POWMAN_SCRATCH5_BITS _u(0xffffffff) +#define POWMAN_SCRATCH5_RESET _u(0x00000000) +#define POWMAN_SCRATCH5_MSB _u(31) +#define POWMAN_SCRATCH5_LSB _u(0) +#define POWMAN_SCRATCH5_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH6 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH6_OFFSET _u(0x000000c8) +#define POWMAN_SCRATCH6_BITS _u(0xffffffff) +#define POWMAN_SCRATCH6_RESET _u(0x00000000) +#define POWMAN_SCRATCH6_MSB _u(31) +#define POWMAN_SCRATCH6_LSB _u(0) +#define POWMAN_SCRATCH6_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_SCRATCH7 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_SCRATCH7_OFFSET _u(0x000000cc) +#define POWMAN_SCRATCH7_BITS _u(0xffffffff) +#define POWMAN_SCRATCH7_RESET _u(0x00000000) +#define POWMAN_SCRATCH7_MSB _u(31) +#define POWMAN_SCRATCH7_LSB _u(0) +#define POWMAN_SCRATCH7_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOOT0 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_BOOT0_OFFSET _u(0x000000d0) +#define POWMAN_BOOT0_BITS _u(0xffffffff) +#define POWMAN_BOOT0_RESET _u(0x00000000) +#define POWMAN_BOOT0_MSB _u(31) +#define POWMAN_BOOT0_LSB _u(0) +#define POWMAN_BOOT0_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOOT1 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_BOOT1_OFFSET _u(0x000000d4) +#define POWMAN_BOOT1_BITS _u(0xffffffff) +#define POWMAN_BOOT1_RESET _u(0x00000000) +#define POWMAN_BOOT1_MSB _u(31) +#define POWMAN_BOOT1_LSB _u(0) +#define POWMAN_BOOT1_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOOT2 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_BOOT2_OFFSET _u(0x000000d8) +#define POWMAN_BOOT2_BITS _u(0xffffffff) +#define POWMAN_BOOT2_RESET _u(0x00000000) +#define POWMAN_BOOT2_MSB _u(31) +#define POWMAN_BOOT2_LSB _u(0) +#define POWMAN_BOOT2_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_BOOT3 +// Description : Scratch register. Information persists in low power mode +#define POWMAN_BOOT3_OFFSET _u(0x000000dc) +#define POWMAN_BOOT3_BITS _u(0xffffffff) +#define POWMAN_BOOT3_RESET _u(0x00000000) +#define POWMAN_BOOT3_MSB _u(31) +#define POWMAN_BOOT3_LSB _u(0) +#define POWMAN_BOOT3_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_INTR +// Description : Raw Interrupts +#define POWMAN_INTR_OFFSET _u(0x000000e0) +#define POWMAN_INTR_BITS _u(0x0000000f) +#define POWMAN_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTR_PWRUP_WHILE_WAITING +// Description : Source is state.pwrup_while_waiting +#define POWMAN_INTR_PWRUP_WHILE_WAITING_RESET _u(0x0) +#define POWMAN_INTR_PWRUP_WHILE_WAITING_BITS _u(0x00000008) +#define POWMAN_INTR_PWRUP_WHILE_WAITING_MSB _u(3) +#define POWMAN_INTR_PWRUP_WHILE_WAITING_LSB _u(3) +#define POWMAN_INTR_PWRUP_WHILE_WAITING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTR_STATE_REQ_IGNORED +// Description : Source is state.req_ignored +#define POWMAN_INTR_STATE_REQ_IGNORED_RESET _u(0x0) +#define POWMAN_INTR_STATE_REQ_IGNORED_BITS _u(0x00000004) +#define POWMAN_INTR_STATE_REQ_IGNORED_MSB _u(2) +#define POWMAN_INTR_STATE_REQ_IGNORED_LSB _u(2) +#define POWMAN_INTR_STATE_REQ_IGNORED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTR_TIMER +#define POWMAN_INTR_TIMER_RESET _u(0x0) +#define POWMAN_INTR_TIMER_BITS _u(0x00000002) +#define POWMAN_INTR_TIMER_MSB _u(1) +#define POWMAN_INTR_TIMER_LSB _u(1) +#define POWMAN_INTR_TIMER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTR_VREG_OUTPUT_LOW +#define POWMAN_INTR_VREG_OUTPUT_LOW_RESET _u(0x0) +#define POWMAN_INTR_VREG_OUTPUT_LOW_BITS _u(0x00000001) +#define POWMAN_INTR_VREG_OUTPUT_LOW_MSB _u(0) +#define POWMAN_INTR_VREG_OUTPUT_LOW_LSB _u(0) +#define POWMAN_INTR_VREG_OUTPUT_LOW_ACCESS "WC" +// ============================================================================= +// Register : POWMAN_INTE +// Description : Interrupt Enable +#define POWMAN_INTE_OFFSET _u(0x000000e4) +#define POWMAN_INTE_BITS _u(0x0000000f) +#define POWMAN_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTE_PWRUP_WHILE_WAITING +// Description : Source is state.pwrup_while_waiting +#define POWMAN_INTE_PWRUP_WHILE_WAITING_RESET _u(0x0) +#define POWMAN_INTE_PWRUP_WHILE_WAITING_BITS _u(0x00000008) +#define POWMAN_INTE_PWRUP_WHILE_WAITING_MSB _u(3) +#define POWMAN_INTE_PWRUP_WHILE_WAITING_LSB _u(3) +#define POWMAN_INTE_PWRUP_WHILE_WAITING_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTE_STATE_REQ_IGNORED +// Description : Source is state.req_ignored +#define POWMAN_INTE_STATE_REQ_IGNORED_RESET _u(0x0) +#define POWMAN_INTE_STATE_REQ_IGNORED_BITS _u(0x00000004) +#define POWMAN_INTE_STATE_REQ_IGNORED_MSB _u(2) +#define POWMAN_INTE_STATE_REQ_IGNORED_LSB _u(2) +#define POWMAN_INTE_STATE_REQ_IGNORED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTE_TIMER +#define POWMAN_INTE_TIMER_RESET _u(0x0) +#define POWMAN_INTE_TIMER_BITS _u(0x00000002) +#define POWMAN_INTE_TIMER_MSB _u(1) +#define POWMAN_INTE_TIMER_LSB _u(1) +#define POWMAN_INTE_TIMER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTE_VREG_OUTPUT_LOW +#define POWMAN_INTE_VREG_OUTPUT_LOW_RESET _u(0x0) +#define POWMAN_INTE_VREG_OUTPUT_LOW_BITS _u(0x00000001) +#define POWMAN_INTE_VREG_OUTPUT_LOW_MSB _u(0) +#define POWMAN_INTE_VREG_OUTPUT_LOW_LSB _u(0) +#define POWMAN_INTE_VREG_OUTPUT_LOW_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_INTF +// Description : Interrupt Force +#define POWMAN_INTF_OFFSET _u(0x000000e8) +#define POWMAN_INTF_BITS _u(0x0000000f) +#define POWMAN_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTF_PWRUP_WHILE_WAITING +// Description : Source is state.pwrup_while_waiting +#define POWMAN_INTF_PWRUP_WHILE_WAITING_RESET _u(0x0) +#define POWMAN_INTF_PWRUP_WHILE_WAITING_BITS _u(0x00000008) +#define POWMAN_INTF_PWRUP_WHILE_WAITING_MSB _u(3) +#define POWMAN_INTF_PWRUP_WHILE_WAITING_LSB _u(3) +#define POWMAN_INTF_PWRUP_WHILE_WAITING_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTF_STATE_REQ_IGNORED +// Description : Source is state.req_ignored +#define POWMAN_INTF_STATE_REQ_IGNORED_RESET _u(0x0) +#define POWMAN_INTF_STATE_REQ_IGNORED_BITS _u(0x00000004) +#define POWMAN_INTF_STATE_REQ_IGNORED_MSB _u(2) +#define POWMAN_INTF_STATE_REQ_IGNORED_LSB _u(2) +#define POWMAN_INTF_STATE_REQ_IGNORED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTF_TIMER +#define POWMAN_INTF_TIMER_RESET _u(0x0) +#define POWMAN_INTF_TIMER_BITS _u(0x00000002) +#define POWMAN_INTF_TIMER_MSB _u(1) +#define POWMAN_INTF_TIMER_LSB _u(1) +#define POWMAN_INTF_TIMER_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTF_VREG_OUTPUT_LOW +#define POWMAN_INTF_VREG_OUTPUT_LOW_RESET _u(0x0) +#define POWMAN_INTF_VREG_OUTPUT_LOW_BITS _u(0x00000001) +#define POWMAN_INTF_VREG_OUTPUT_LOW_MSB _u(0) +#define POWMAN_INTF_VREG_OUTPUT_LOW_LSB _u(0) +#define POWMAN_INTF_VREG_OUTPUT_LOW_ACCESS "RW" +// ============================================================================= +// Register : POWMAN_INTS +// Description : Interrupt status after masking & forcing +#define POWMAN_INTS_OFFSET _u(0x000000ec) +#define POWMAN_INTS_BITS _u(0x0000000f) +#define POWMAN_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTS_PWRUP_WHILE_WAITING +// Description : Source is state.pwrup_while_waiting +#define POWMAN_INTS_PWRUP_WHILE_WAITING_RESET _u(0x0) +#define POWMAN_INTS_PWRUP_WHILE_WAITING_BITS _u(0x00000008) +#define POWMAN_INTS_PWRUP_WHILE_WAITING_MSB _u(3) +#define POWMAN_INTS_PWRUP_WHILE_WAITING_LSB _u(3) +#define POWMAN_INTS_PWRUP_WHILE_WAITING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTS_STATE_REQ_IGNORED +// Description : Source is state.req_ignored +#define POWMAN_INTS_STATE_REQ_IGNORED_RESET _u(0x0) +#define POWMAN_INTS_STATE_REQ_IGNORED_BITS _u(0x00000004) +#define POWMAN_INTS_STATE_REQ_IGNORED_MSB _u(2) +#define POWMAN_INTS_STATE_REQ_IGNORED_LSB _u(2) +#define POWMAN_INTS_STATE_REQ_IGNORED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTS_TIMER +#define POWMAN_INTS_TIMER_RESET _u(0x0) +#define POWMAN_INTS_TIMER_BITS _u(0x00000002) +#define POWMAN_INTS_TIMER_MSB _u(1) +#define POWMAN_INTS_TIMER_LSB _u(1) +#define POWMAN_INTS_TIMER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : POWMAN_INTS_VREG_OUTPUT_LOW +#define POWMAN_INTS_VREG_OUTPUT_LOW_RESET _u(0x0) +#define POWMAN_INTS_VREG_OUTPUT_LOW_BITS _u(0x00000001) +#define POWMAN_INTS_VREG_OUTPUT_LOW_MSB _u(0) +#define POWMAN_INTS_VREG_OUTPUT_LOW_LSB _u(0) +#define POWMAN_INTS_VREG_OUTPUT_LOW_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_POWMAN_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/psm.h b/lib/pico-sdk/rp2350/hardware/regs/psm.h new file mode 100644 index 000000000000..cad268a36e1d --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/psm.h @@ -0,0 +1,741 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PSM +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_PSM_H +#define _HARDWARE_REGS_PSM_H +// ============================================================================= +// Register : PSM_FRCE_ON +// Description : Force block out of reset (i.e. power it on) +#define PSM_FRCE_ON_OFFSET _u(0x00000000) +#define PSM_FRCE_ON_BITS _u(0x01ffffff) +#define PSM_FRCE_ON_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_PROC1 +#define PSM_FRCE_ON_PROC1_RESET _u(0x0) +#define PSM_FRCE_ON_PROC1_BITS _u(0x01000000) +#define PSM_FRCE_ON_PROC1_MSB _u(24) +#define PSM_FRCE_ON_PROC1_LSB _u(24) +#define PSM_FRCE_ON_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_PROC0 +#define PSM_FRCE_ON_PROC0_RESET _u(0x0) +#define PSM_FRCE_ON_PROC0_BITS _u(0x00800000) +#define PSM_FRCE_ON_PROC0_MSB _u(23) +#define PSM_FRCE_ON_PROC0_LSB _u(23) +#define PSM_FRCE_ON_PROC0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_ACCESSCTRL +#define PSM_FRCE_ON_ACCESSCTRL_RESET _u(0x0) +#define PSM_FRCE_ON_ACCESSCTRL_BITS _u(0x00400000) +#define PSM_FRCE_ON_ACCESSCTRL_MSB _u(22) +#define PSM_FRCE_ON_ACCESSCTRL_LSB _u(22) +#define PSM_FRCE_ON_ACCESSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SIO +#define PSM_FRCE_ON_SIO_RESET _u(0x0) +#define PSM_FRCE_ON_SIO_BITS _u(0x00200000) +#define PSM_FRCE_ON_SIO_MSB _u(21) +#define PSM_FRCE_ON_SIO_LSB _u(21) +#define PSM_FRCE_ON_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_XIP +#define PSM_FRCE_ON_XIP_RESET _u(0x0) +#define PSM_FRCE_ON_XIP_BITS _u(0x00100000) +#define PSM_FRCE_ON_XIP_MSB _u(20) +#define PSM_FRCE_ON_XIP_LSB _u(20) +#define PSM_FRCE_ON_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM9 +#define PSM_FRCE_ON_SRAM9_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM9_BITS _u(0x00080000) +#define PSM_FRCE_ON_SRAM9_MSB _u(19) +#define PSM_FRCE_ON_SRAM9_LSB _u(19) +#define PSM_FRCE_ON_SRAM9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM8 +#define PSM_FRCE_ON_SRAM8_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM8_BITS _u(0x00040000) +#define PSM_FRCE_ON_SRAM8_MSB _u(18) +#define PSM_FRCE_ON_SRAM8_LSB _u(18) +#define PSM_FRCE_ON_SRAM8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM7 +#define PSM_FRCE_ON_SRAM7_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM7_BITS _u(0x00020000) +#define PSM_FRCE_ON_SRAM7_MSB _u(17) +#define PSM_FRCE_ON_SRAM7_LSB _u(17) +#define PSM_FRCE_ON_SRAM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM6 +#define PSM_FRCE_ON_SRAM6_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM6_BITS _u(0x00010000) +#define PSM_FRCE_ON_SRAM6_MSB _u(16) +#define PSM_FRCE_ON_SRAM6_LSB _u(16) +#define PSM_FRCE_ON_SRAM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM5 +#define PSM_FRCE_ON_SRAM5_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM5_BITS _u(0x00008000) +#define PSM_FRCE_ON_SRAM5_MSB _u(15) +#define PSM_FRCE_ON_SRAM5_LSB _u(15) +#define PSM_FRCE_ON_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM4 +#define PSM_FRCE_ON_SRAM4_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM4_BITS _u(0x00004000) +#define PSM_FRCE_ON_SRAM4_MSB _u(14) +#define PSM_FRCE_ON_SRAM4_LSB _u(14) +#define PSM_FRCE_ON_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM3 +#define PSM_FRCE_ON_SRAM3_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM3_BITS _u(0x00002000) +#define PSM_FRCE_ON_SRAM3_MSB _u(13) +#define PSM_FRCE_ON_SRAM3_LSB _u(13) +#define PSM_FRCE_ON_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM2 +#define PSM_FRCE_ON_SRAM2_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM2_BITS _u(0x00001000) +#define PSM_FRCE_ON_SRAM2_MSB _u(12) +#define PSM_FRCE_ON_SRAM2_LSB _u(12) +#define PSM_FRCE_ON_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM1 +#define PSM_FRCE_ON_SRAM1_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000800) +#define PSM_FRCE_ON_SRAM1_MSB _u(11) +#define PSM_FRCE_ON_SRAM1_LSB _u(11) +#define PSM_FRCE_ON_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_SRAM0 +#define PSM_FRCE_ON_SRAM0_RESET _u(0x0) +#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000400) +#define PSM_FRCE_ON_SRAM0_MSB _u(10) +#define PSM_FRCE_ON_SRAM0_LSB _u(10) +#define PSM_FRCE_ON_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_BOOTRAM +#define PSM_FRCE_ON_BOOTRAM_RESET _u(0x0) +#define PSM_FRCE_ON_BOOTRAM_BITS _u(0x00000200) +#define PSM_FRCE_ON_BOOTRAM_MSB _u(9) +#define PSM_FRCE_ON_BOOTRAM_LSB _u(9) +#define PSM_FRCE_ON_BOOTRAM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_ROM +#define PSM_FRCE_ON_ROM_RESET _u(0x0) +#define PSM_FRCE_ON_ROM_BITS _u(0x00000100) +#define PSM_FRCE_ON_ROM_MSB _u(8) +#define PSM_FRCE_ON_ROM_LSB _u(8) +#define PSM_FRCE_ON_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_BUSFABRIC +#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0) +#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000080) +#define PSM_FRCE_ON_BUSFABRIC_MSB _u(7) +#define PSM_FRCE_ON_BUSFABRIC_LSB _u(7) +#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_PSM_READY +#define PSM_FRCE_ON_PSM_READY_RESET _u(0x0) +#define PSM_FRCE_ON_PSM_READY_BITS _u(0x00000040) +#define PSM_FRCE_ON_PSM_READY_MSB _u(6) +#define PSM_FRCE_ON_PSM_READY_LSB _u(6) +#define PSM_FRCE_ON_PSM_READY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_CLOCKS +#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0) +#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000020) +#define PSM_FRCE_ON_CLOCKS_MSB _u(5) +#define PSM_FRCE_ON_CLOCKS_LSB _u(5) +#define PSM_FRCE_ON_CLOCKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_RESETS +#define PSM_FRCE_ON_RESETS_RESET _u(0x0) +#define PSM_FRCE_ON_RESETS_BITS _u(0x00000010) +#define PSM_FRCE_ON_RESETS_MSB _u(4) +#define PSM_FRCE_ON_RESETS_LSB _u(4) +#define PSM_FRCE_ON_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_XOSC +#define PSM_FRCE_ON_XOSC_RESET _u(0x0) +#define PSM_FRCE_ON_XOSC_BITS _u(0x00000008) +#define PSM_FRCE_ON_XOSC_MSB _u(3) +#define PSM_FRCE_ON_XOSC_LSB _u(3) +#define PSM_FRCE_ON_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_ROSC +#define PSM_FRCE_ON_ROSC_RESET _u(0x0) +#define PSM_FRCE_ON_ROSC_BITS _u(0x00000004) +#define PSM_FRCE_ON_ROSC_MSB _u(2) +#define PSM_FRCE_ON_ROSC_LSB _u(2) +#define PSM_FRCE_ON_ROSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_OTP +#define PSM_FRCE_ON_OTP_RESET _u(0x0) +#define PSM_FRCE_ON_OTP_BITS _u(0x00000002) +#define PSM_FRCE_ON_OTP_MSB _u(1) +#define PSM_FRCE_ON_OTP_LSB _u(1) +#define PSM_FRCE_ON_OTP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_ON_PROC_COLD +#define PSM_FRCE_ON_PROC_COLD_RESET _u(0x0) +#define PSM_FRCE_ON_PROC_COLD_BITS _u(0x00000001) +#define PSM_FRCE_ON_PROC_COLD_MSB _u(0) +#define PSM_FRCE_ON_PROC_COLD_LSB _u(0) +#define PSM_FRCE_ON_PROC_COLD_ACCESS "RW" +// ============================================================================= +// Register : PSM_FRCE_OFF +// Description : Force into reset (i.e. power it off) +#define PSM_FRCE_OFF_OFFSET _u(0x00000004) +#define PSM_FRCE_OFF_BITS _u(0x01ffffff) +#define PSM_FRCE_OFF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_PROC1 +#define PSM_FRCE_OFF_PROC1_RESET _u(0x0) +#define PSM_FRCE_OFF_PROC1_BITS _u(0x01000000) +#define PSM_FRCE_OFF_PROC1_MSB _u(24) +#define PSM_FRCE_OFF_PROC1_LSB _u(24) +#define PSM_FRCE_OFF_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_PROC0 +#define PSM_FRCE_OFF_PROC0_RESET _u(0x0) +#define PSM_FRCE_OFF_PROC0_BITS _u(0x00800000) +#define PSM_FRCE_OFF_PROC0_MSB _u(23) +#define PSM_FRCE_OFF_PROC0_LSB _u(23) +#define PSM_FRCE_OFF_PROC0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_ACCESSCTRL +#define PSM_FRCE_OFF_ACCESSCTRL_RESET _u(0x0) +#define PSM_FRCE_OFF_ACCESSCTRL_BITS _u(0x00400000) +#define PSM_FRCE_OFF_ACCESSCTRL_MSB _u(22) +#define PSM_FRCE_OFF_ACCESSCTRL_LSB _u(22) +#define PSM_FRCE_OFF_ACCESSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SIO +#define PSM_FRCE_OFF_SIO_RESET _u(0x0) +#define PSM_FRCE_OFF_SIO_BITS _u(0x00200000) +#define PSM_FRCE_OFF_SIO_MSB _u(21) +#define PSM_FRCE_OFF_SIO_LSB _u(21) +#define PSM_FRCE_OFF_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_XIP +#define PSM_FRCE_OFF_XIP_RESET _u(0x0) +#define PSM_FRCE_OFF_XIP_BITS _u(0x00100000) +#define PSM_FRCE_OFF_XIP_MSB _u(20) +#define PSM_FRCE_OFF_XIP_LSB _u(20) +#define PSM_FRCE_OFF_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM9 +#define PSM_FRCE_OFF_SRAM9_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM9_BITS _u(0x00080000) +#define PSM_FRCE_OFF_SRAM9_MSB _u(19) +#define PSM_FRCE_OFF_SRAM9_LSB _u(19) +#define PSM_FRCE_OFF_SRAM9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM8 +#define PSM_FRCE_OFF_SRAM8_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM8_BITS _u(0x00040000) +#define PSM_FRCE_OFF_SRAM8_MSB _u(18) +#define PSM_FRCE_OFF_SRAM8_LSB _u(18) +#define PSM_FRCE_OFF_SRAM8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM7 +#define PSM_FRCE_OFF_SRAM7_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM7_BITS _u(0x00020000) +#define PSM_FRCE_OFF_SRAM7_MSB _u(17) +#define PSM_FRCE_OFF_SRAM7_LSB _u(17) +#define PSM_FRCE_OFF_SRAM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM6 +#define PSM_FRCE_OFF_SRAM6_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM6_BITS _u(0x00010000) +#define PSM_FRCE_OFF_SRAM6_MSB _u(16) +#define PSM_FRCE_OFF_SRAM6_LSB _u(16) +#define PSM_FRCE_OFF_SRAM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM5 +#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00008000) +#define PSM_FRCE_OFF_SRAM5_MSB _u(15) +#define PSM_FRCE_OFF_SRAM5_LSB _u(15) +#define PSM_FRCE_OFF_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM4 +#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00004000) +#define PSM_FRCE_OFF_SRAM4_MSB _u(14) +#define PSM_FRCE_OFF_SRAM4_LSB _u(14) +#define PSM_FRCE_OFF_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM3 +#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00002000) +#define PSM_FRCE_OFF_SRAM3_MSB _u(13) +#define PSM_FRCE_OFF_SRAM3_LSB _u(13) +#define PSM_FRCE_OFF_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM2 +#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00001000) +#define PSM_FRCE_OFF_SRAM2_MSB _u(12) +#define PSM_FRCE_OFF_SRAM2_LSB _u(12) +#define PSM_FRCE_OFF_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM1 +#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000800) +#define PSM_FRCE_OFF_SRAM1_MSB _u(11) +#define PSM_FRCE_OFF_SRAM1_LSB _u(11) +#define PSM_FRCE_OFF_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_SRAM0 +#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0) +#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000400) +#define PSM_FRCE_OFF_SRAM0_MSB _u(10) +#define PSM_FRCE_OFF_SRAM0_LSB _u(10) +#define PSM_FRCE_OFF_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_BOOTRAM +#define PSM_FRCE_OFF_BOOTRAM_RESET _u(0x0) +#define PSM_FRCE_OFF_BOOTRAM_BITS _u(0x00000200) +#define PSM_FRCE_OFF_BOOTRAM_MSB _u(9) +#define PSM_FRCE_OFF_BOOTRAM_LSB _u(9) +#define PSM_FRCE_OFF_BOOTRAM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_ROM +#define PSM_FRCE_OFF_ROM_RESET _u(0x0) +#define PSM_FRCE_OFF_ROM_BITS _u(0x00000100) +#define PSM_FRCE_OFF_ROM_MSB _u(8) +#define PSM_FRCE_OFF_ROM_LSB _u(8) +#define PSM_FRCE_OFF_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_BUSFABRIC +#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0) +#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000080) +#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(7) +#define PSM_FRCE_OFF_BUSFABRIC_LSB _u(7) +#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_PSM_READY +#define PSM_FRCE_OFF_PSM_READY_RESET _u(0x0) +#define PSM_FRCE_OFF_PSM_READY_BITS _u(0x00000040) +#define PSM_FRCE_OFF_PSM_READY_MSB _u(6) +#define PSM_FRCE_OFF_PSM_READY_LSB _u(6) +#define PSM_FRCE_OFF_PSM_READY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_CLOCKS +#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0) +#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000020) +#define PSM_FRCE_OFF_CLOCKS_MSB _u(5) +#define PSM_FRCE_OFF_CLOCKS_LSB _u(5) +#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_RESETS +#define PSM_FRCE_OFF_RESETS_RESET _u(0x0) +#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000010) +#define PSM_FRCE_OFF_RESETS_MSB _u(4) +#define PSM_FRCE_OFF_RESETS_LSB _u(4) +#define PSM_FRCE_OFF_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_XOSC +#define PSM_FRCE_OFF_XOSC_RESET _u(0x0) +#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000008) +#define PSM_FRCE_OFF_XOSC_MSB _u(3) +#define PSM_FRCE_OFF_XOSC_LSB _u(3) +#define PSM_FRCE_OFF_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_ROSC +#define PSM_FRCE_OFF_ROSC_RESET _u(0x0) +#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000004) +#define PSM_FRCE_OFF_ROSC_MSB _u(2) +#define PSM_FRCE_OFF_ROSC_LSB _u(2) +#define PSM_FRCE_OFF_ROSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_OTP +#define PSM_FRCE_OFF_OTP_RESET _u(0x0) +#define PSM_FRCE_OFF_OTP_BITS _u(0x00000002) +#define PSM_FRCE_OFF_OTP_MSB _u(1) +#define PSM_FRCE_OFF_OTP_LSB _u(1) +#define PSM_FRCE_OFF_OTP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_FRCE_OFF_PROC_COLD +#define PSM_FRCE_OFF_PROC_COLD_RESET _u(0x0) +#define PSM_FRCE_OFF_PROC_COLD_BITS _u(0x00000001) +#define PSM_FRCE_OFF_PROC_COLD_MSB _u(0) +#define PSM_FRCE_OFF_PROC_COLD_LSB _u(0) +#define PSM_FRCE_OFF_PROC_COLD_ACCESS "RW" +// ============================================================================= +// Register : PSM_WDSEL +// Description : Set to 1 if the watchdog should reset this +#define PSM_WDSEL_OFFSET _u(0x00000008) +#define PSM_WDSEL_BITS _u(0x01ffffff) +#define PSM_WDSEL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_PROC1 +#define PSM_WDSEL_PROC1_RESET _u(0x0) +#define PSM_WDSEL_PROC1_BITS _u(0x01000000) +#define PSM_WDSEL_PROC1_MSB _u(24) +#define PSM_WDSEL_PROC1_LSB _u(24) +#define PSM_WDSEL_PROC1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_PROC0 +#define PSM_WDSEL_PROC0_RESET _u(0x0) +#define PSM_WDSEL_PROC0_BITS _u(0x00800000) +#define PSM_WDSEL_PROC0_MSB _u(23) +#define PSM_WDSEL_PROC0_LSB _u(23) +#define PSM_WDSEL_PROC0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_ACCESSCTRL +#define PSM_WDSEL_ACCESSCTRL_RESET _u(0x0) +#define PSM_WDSEL_ACCESSCTRL_BITS _u(0x00400000) +#define PSM_WDSEL_ACCESSCTRL_MSB _u(22) +#define PSM_WDSEL_ACCESSCTRL_LSB _u(22) +#define PSM_WDSEL_ACCESSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SIO +#define PSM_WDSEL_SIO_RESET _u(0x0) +#define PSM_WDSEL_SIO_BITS _u(0x00200000) +#define PSM_WDSEL_SIO_MSB _u(21) +#define PSM_WDSEL_SIO_LSB _u(21) +#define PSM_WDSEL_SIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_XIP +#define PSM_WDSEL_XIP_RESET _u(0x0) +#define PSM_WDSEL_XIP_BITS _u(0x00100000) +#define PSM_WDSEL_XIP_MSB _u(20) +#define PSM_WDSEL_XIP_LSB _u(20) +#define PSM_WDSEL_XIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM9 +#define PSM_WDSEL_SRAM9_RESET _u(0x0) +#define PSM_WDSEL_SRAM9_BITS _u(0x00080000) +#define PSM_WDSEL_SRAM9_MSB _u(19) +#define PSM_WDSEL_SRAM9_LSB _u(19) +#define PSM_WDSEL_SRAM9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM8 +#define PSM_WDSEL_SRAM8_RESET _u(0x0) +#define PSM_WDSEL_SRAM8_BITS _u(0x00040000) +#define PSM_WDSEL_SRAM8_MSB _u(18) +#define PSM_WDSEL_SRAM8_LSB _u(18) +#define PSM_WDSEL_SRAM8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM7 +#define PSM_WDSEL_SRAM7_RESET _u(0x0) +#define PSM_WDSEL_SRAM7_BITS _u(0x00020000) +#define PSM_WDSEL_SRAM7_MSB _u(17) +#define PSM_WDSEL_SRAM7_LSB _u(17) +#define PSM_WDSEL_SRAM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM6 +#define PSM_WDSEL_SRAM6_RESET _u(0x0) +#define PSM_WDSEL_SRAM6_BITS _u(0x00010000) +#define PSM_WDSEL_SRAM6_MSB _u(16) +#define PSM_WDSEL_SRAM6_LSB _u(16) +#define PSM_WDSEL_SRAM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM5 +#define PSM_WDSEL_SRAM5_RESET _u(0x0) +#define PSM_WDSEL_SRAM5_BITS _u(0x00008000) +#define PSM_WDSEL_SRAM5_MSB _u(15) +#define PSM_WDSEL_SRAM5_LSB _u(15) +#define PSM_WDSEL_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM4 +#define PSM_WDSEL_SRAM4_RESET _u(0x0) +#define PSM_WDSEL_SRAM4_BITS _u(0x00004000) +#define PSM_WDSEL_SRAM4_MSB _u(14) +#define PSM_WDSEL_SRAM4_LSB _u(14) +#define PSM_WDSEL_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM3 +#define PSM_WDSEL_SRAM3_RESET _u(0x0) +#define PSM_WDSEL_SRAM3_BITS _u(0x00002000) +#define PSM_WDSEL_SRAM3_MSB _u(13) +#define PSM_WDSEL_SRAM3_LSB _u(13) +#define PSM_WDSEL_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM2 +#define PSM_WDSEL_SRAM2_RESET _u(0x0) +#define PSM_WDSEL_SRAM2_BITS _u(0x00001000) +#define PSM_WDSEL_SRAM2_MSB _u(12) +#define PSM_WDSEL_SRAM2_LSB _u(12) +#define PSM_WDSEL_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM1 +#define PSM_WDSEL_SRAM1_RESET _u(0x0) +#define PSM_WDSEL_SRAM1_BITS _u(0x00000800) +#define PSM_WDSEL_SRAM1_MSB _u(11) +#define PSM_WDSEL_SRAM1_LSB _u(11) +#define PSM_WDSEL_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_SRAM0 +#define PSM_WDSEL_SRAM0_RESET _u(0x0) +#define PSM_WDSEL_SRAM0_BITS _u(0x00000400) +#define PSM_WDSEL_SRAM0_MSB _u(10) +#define PSM_WDSEL_SRAM0_LSB _u(10) +#define PSM_WDSEL_SRAM0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_BOOTRAM +#define PSM_WDSEL_BOOTRAM_RESET _u(0x0) +#define PSM_WDSEL_BOOTRAM_BITS _u(0x00000200) +#define PSM_WDSEL_BOOTRAM_MSB _u(9) +#define PSM_WDSEL_BOOTRAM_LSB _u(9) +#define PSM_WDSEL_BOOTRAM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_ROM +#define PSM_WDSEL_ROM_RESET _u(0x0) +#define PSM_WDSEL_ROM_BITS _u(0x00000100) +#define PSM_WDSEL_ROM_MSB _u(8) +#define PSM_WDSEL_ROM_LSB _u(8) +#define PSM_WDSEL_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_BUSFABRIC +#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0) +#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000080) +#define PSM_WDSEL_BUSFABRIC_MSB _u(7) +#define PSM_WDSEL_BUSFABRIC_LSB _u(7) +#define PSM_WDSEL_BUSFABRIC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_PSM_READY +#define PSM_WDSEL_PSM_READY_RESET _u(0x0) +#define PSM_WDSEL_PSM_READY_BITS _u(0x00000040) +#define PSM_WDSEL_PSM_READY_MSB _u(6) +#define PSM_WDSEL_PSM_READY_LSB _u(6) +#define PSM_WDSEL_PSM_READY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_CLOCKS +#define PSM_WDSEL_CLOCKS_RESET _u(0x0) +#define PSM_WDSEL_CLOCKS_BITS _u(0x00000020) +#define PSM_WDSEL_CLOCKS_MSB _u(5) +#define PSM_WDSEL_CLOCKS_LSB _u(5) +#define PSM_WDSEL_CLOCKS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_RESETS +#define PSM_WDSEL_RESETS_RESET _u(0x0) +#define PSM_WDSEL_RESETS_BITS _u(0x00000010) +#define PSM_WDSEL_RESETS_MSB _u(4) +#define PSM_WDSEL_RESETS_LSB _u(4) +#define PSM_WDSEL_RESETS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_XOSC +#define PSM_WDSEL_XOSC_RESET _u(0x0) +#define PSM_WDSEL_XOSC_BITS _u(0x00000008) +#define PSM_WDSEL_XOSC_MSB _u(3) +#define PSM_WDSEL_XOSC_LSB _u(3) +#define PSM_WDSEL_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_ROSC +#define PSM_WDSEL_ROSC_RESET _u(0x0) +#define PSM_WDSEL_ROSC_BITS _u(0x00000004) +#define PSM_WDSEL_ROSC_MSB _u(2) +#define PSM_WDSEL_ROSC_LSB _u(2) +#define PSM_WDSEL_ROSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_OTP +#define PSM_WDSEL_OTP_RESET _u(0x0) +#define PSM_WDSEL_OTP_BITS _u(0x00000002) +#define PSM_WDSEL_OTP_MSB _u(1) +#define PSM_WDSEL_OTP_LSB _u(1) +#define PSM_WDSEL_OTP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PSM_WDSEL_PROC_COLD +#define PSM_WDSEL_PROC_COLD_RESET _u(0x0) +#define PSM_WDSEL_PROC_COLD_BITS _u(0x00000001) +#define PSM_WDSEL_PROC_COLD_MSB _u(0) +#define PSM_WDSEL_PROC_COLD_LSB _u(0) +#define PSM_WDSEL_PROC_COLD_ACCESS "RW" +// ============================================================================= +// Register : PSM_DONE +// Description : Is the subsystem ready? +#define PSM_DONE_OFFSET _u(0x0000000c) +#define PSM_DONE_BITS _u(0x01ffffff) +#define PSM_DONE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_PROC1 +#define PSM_DONE_PROC1_RESET _u(0x0) +#define PSM_DONE_PROC1_BITS _u(0x01000000) +#define PSM_DONE_PROC1_MSB _u(24) +#define PSM_DONE_PROC1_LSB _u(24) +#define PSM_DONE_PROC1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_PROC0 +#define PSM_DONE_PROC0_RESET _u(0x0) +#define PSM_DONE_PROC0_BITS _u(0x00800000) +#define PSM_DONE_PROC0_MSB _u(23) +#define PSM_DONE_PROC0_LSB _u(23) +#define PSM_DONE_PROC0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_ACCESSCTRL +#define PSM_DONE_ACCESSCTRL_RESET _u(0x0) +#define PSM_DONE_ACCESSCTRL_BITS _u(0x00400000) +#define PSM_DONE_ACCESSCTRL_MSB _u(22) +#define PSM_DONE_ACCESSCTRL_LSB _u(22) +#define PSM_DONE_ACCESSCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SIO +#define PSM_DONE_SIO_RESET _u(0x0) +#define PSM_DONE_SIO_BITS _u(0x00200000) +#define PSM_DONE_SIO_MSB _u(21) +#define PSM_DONE_SIO_LSB _u(21) +#define PSM_DONE_SIO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_XIP +#define PSM_DONE_XIP_RESET _u(0x0) +#define PSM_DONE_XIP_BITS _u(0x00100000) +#define PSM_DONE_XIP_MSB _u(20) +#define PSM_DONE_XIP_LSB _u(20) +#define PSM_DONE_XIP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM9 +#define PSM_DONE_SRAM9_RESET _u(0x0) +#define PSM_DONE_SRAM9_BITS _u(0x00080000) +#define PSM_DONE_SRAM9_MSB _u(19) +#define PSM_DONE_SRAM9_LSB _u(19) +#define PSM_DONE_SRAM9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM8 +#define PSM_DONE_SRAM8_RESET _u(0x0) +#define PSM_DONE_SRAM8_BITS _u(0x00040000) +#define PSM_DONE_SRAM8_MSB _u(18) +#define PSM_DONE_SRAM8_LSB _u(18) +#define PSM_DONE_SRAM8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM7 +#define PSM_DONE_SRAM7_RESET _u(0x0) +#define PSM_DONE_SRAM7_BITS _u(0x00020000) +#define PSM_DONE_SRAM7_MSB _u(17) +#define PSM_DONE_SRAM7_LSB _u(17) +#define PSM_DONE_SRAM7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM6 +#define PSM_DONE_SRAM6_RESET _u(0x0) +#define PSM_DONE_SRAM6_BITS _u(0x00010000) +#define PSM_DONE_SRAM6_MSB _u(16) +#define PSM_DONE_SRAM6_LSB _u(16) +#define PSM_DONE_SRAM6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM5 +#define PSM_DONE_SRAM5_RESET _u(0x0) +#define PSM_DONE_SRAM5_BITS _u(0x00008000) +#define PSM_DONE_SRAM5_MSB _u(15) +#define PSM_DONE_SRAM5_LSB _u(15) +#define PSM_DONE_SRAM5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM4 +#define PSM_DONE_SRAM4_RESET _u(0x0) +#define PSM_DONE_SRAM4_BITS _u(0x00004000) +#define PSM_DONE_SRAM4_MSB _u(14) +#define PSM_DONE_SRAM4_LSB _u(14) +#define PSM_DONE_SRAM4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM3 +#define PSM_DONE_SRAM3_RESET _u(0x0) +#define PSM_DONE_SRAM3_BITS _u(0x00002000) +#define PSM_DONE_SRAM3_MSB _u(13) +#define PSM_DONE_SRAM3_LSB _u(13) +#define PSM_DONE_SRAM3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM2 +#define PSM_DONE_SRAM2_RESET _u(0x0) +#define PSM_DONE_SRAM2_BITS _u(0x00001000) +#define PSM_DONE_SRAM2_MSB _u(12) +#define PSM_DONE_SRAM2_LSB _u(12) +#define PSM_DONE_SRAM2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM1 +#define PSM_DONE_SRAM1_RESET _u(0x0) +#define PSM_DONE_SRAM1_BITS _u(0x00000800) +#define PSM_DONE_SRAM1_MSB _u(11) +#define PSM_DONE_SRAM1_LSB _u(11) +#define PSM_DONE_SRAM1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_SRAM0 +#define PSM_DONE_SRAM0_RESET _u(0x0) +#define PSM_DONE_SRAM0_BITS _u(0x00000400) +#define PSM_DONE_SRAM0_MSB _u(10) +#define PSM_DONE_SRAM0_LSB _u(10) +#define PSM_DONE_SRAM0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_BOOTRAM +#define PSM_DONE_BOOTRAM_RESET _u(0x0) +#define PSM_DONE_BOOTRAM_BITS _u(0x00000200) +#define PSM_DONE_BOOTRAM_MSB _u(9) +#define PSM_DONE_BOOTRAM_LSB _u(9) +#define PSM_DONE_BOOTRAM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_ROM +#define PSM_DONE_ROM_RESET _u(0x0) +#define PSM_DONE_ROM_BITS _u(0x00000100) +#define PSM_DONE_ROM_MSB _u(8) +#define PSM_DONE_ROM_LSB _u(8) +#define PSM_DONE_ROM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_BUSFABRIC +#define PSM_DONE_BUSFABRIC_RESET _u(0x0) +#define PSM_DONE_BUSFABRIC_BITS _u(0x00000080) +#define PSM_DONE_BUSFABRIC_MSB _u(7) +#define PSM_DONE_BUSFABRIC_LSB _u(7) +#define PSM_DONE_BUSFABRIC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_PSM_READY +#define PSM_DONE_PSM_READY_RESET _u(0x0) +#define PSM_DONE_PSM_READY_BITS _u(0x00000040) +#define PSM_DONE_PSM_READY_MSB _u(6) +#define PSM_DONE_PSM_READY_LSB _u(6) +#define PSM_DONE_PSM_READY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_CLOCKS +#define PSM_DONE_CLOCKS_RESET _u(0x0) +#define PSM_DONE_CLOCKS_BITS _u(0x00000020) +#define PSM_DONE_CLOCKS_MSB _u(5) +#define PSM_DONE_CLOCKS_LSB _u(5) +#define PSM_DONE_CLOCKS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_RESETS +#define PSM_DONE_RESETS_RESET _u(0x0) +#define PSM_DONE_RESETS_BITS _u(0x00000010) +#define PSM_DONE_RESETS_MSB _u(4) +#define PSM_DONE_RESETS_LSB _u(4) +#define PSM_DONE_RESETS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_XOSC +#define PSM_DONE_XOSC_RESET _u(0x0) +#define PSM_DONE_XOSC_BITS _u(0x00000008) +#define PSM_DONE_XOSC_MSB _u(3) +#define PSM_DONE_XOSC_LSB _u(3) +#define PSM_DONE_XOSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_ROSC +#define PSM_DONE_ROSC_RESET _u(0x0) +#define PSM_DONE_ROSC_BITS _u(0x00000004) +#define PSM_DONE_ROSC_MSB _u(2) +#define PSM_DONE_ROSC_LSB _u(2) +#define PSM_DONE_ROSC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_OTP +#define PSM_DONE_OTP_RESET _u(0x0) +#define PSM_DONE_OTP_BITS _u(0x00000002) +#define PSM_DONE_OTP_MSB _u(1) +#define PSM_DONE_OTP_LSB _u(1) +#define PSM_DONE_OTP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PSM_DONE_PROC_COLD +#define PSM_DONE_PROC_COLD_RESET _u(0x0) +#define PSM_DONE_PROC_COLD_BITS _u(0x00000001) +#define PSM_DONE_PROC_COLD_MSB _u(0) +#define PSM_DONE_PROC_COLD_LSB _u(0) +#define PSM_DONE_PROC_COLD_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_PSM_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/pwm.h b/lib/pico-sdk/rp2350/hardware/regs/pwm.h new file mode 100644 index 000000000000..629ee8a655db --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/pwm.h @@ -0,0 +1,2374 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : PWM +// Version : 1 +// Bus type : apb +// Description : Simple PWM +// ============================================================================= +#ifndef _HARDWARE_REGS_PWM_H +#define _HARDWARE_REGS_PWM_H +// ============================================================================= +// Register : PWM_CH0_CSR +// Description : Control and status register +#define PWM_CH0_CSR_OFFSET _u(0x00000000) +#define PWM_CH0_CSR_BITS _u(0x000000ff) +#define PWM_CH0_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH0_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH0_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH0_CSR_PH_ADV_MSB _u(7) +#define PWM_CH0_CSR_PH_ADV_LSB _u(7) +#define PWM_CH0_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH0_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH0_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH0_CSR_PH_RET_MSB _u(6) +#define PWM_CH0_CSR_PH_RET_LSB _u(6) +#define PWM_CH0_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH0_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH0_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH0_CSR_DIVMODE_MSB _u(5) +#define PWM_CH0_CSR_DIVMODE_LSB _u(4) +#define PWM_CH0_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH0_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH0_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH0_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_B_INV +// Description : Invert output B +#define PWM_CH0_CSR_B_INV_RESET _u(0x0) +#define PWM_CH0_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH0_CSR_B_INV_MSB _u(3) +#define PWM_CH0_CSR_B_INV_LSB _u(3) +#define PWM_CH0_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_A_INV +// Description : Invert output A +#define PWM_CH0_CSR_A_INV_RESET _u(0x0) +#define PWM_CH0_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH0_CSR_A_INV_MSB _u(2) +#define PWM_CH0_CSR_A_INV_LSB _u(2) +#define PWM_CH0_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH0_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH0_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH0_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH0_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH0_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH0_CSR_EN_RESET _u(0x0) +#define PWM_CH0_CSR_EN_BITS _u(0x00000001) +#define PWM_CH0_CSR_EN_MSB _u(0) +#define PWM_CH0_CSR_EN_LSB _u(0) +#define PWM_CH0_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH0_DIV_OFFSET _u(0x00000004) +#define PWM_CH0_DIV_BITS _u(0x00000fff) +#define PWM_CH0_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_DIV_INT +#define PWM_CH0_DIV_INT_RESET _u(0x01) +#define PWM_CH0_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH0_DIV_INT_MSB _u(11) +#define PWM_CH0_DIV_INT_LSB _u(4) +#define PWM_CH0_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_DIV_FRAC +#define PWM_CH0_DIV_FRAC_RESET _u(0x0) +#define PWM_CH0_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH0_DIV_FRAC_MSB _u(3) +#define PWM_CH0_DIV_FRAC_LSB _u(0) +#define PWM_CH0_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_CTR +// Description : Direct access to the PWM counter +#define PWM_CH0_CTR_OFFSET _u(0x00000008) +#define PWM_CH0_CTR_BITS _u(0x0000ffff) +#define PWM_CH0_CTR_RESET _u(0x00000000) +#define PWM_CH0_CTR_MSB _u(15) +#define PWM_CH0_CTR_LSB _u(0) +#define PWM_CH0_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_CC +// Description : Counter compare values +#define PWM_CH0_CC_OFFSET _u(0x0000000c) +#define PWM_CH0_CC_BITS _u(0xffffffff) +#define PWM_CH0_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CC_B +#define PWM_CH0_CC_B_RESET _u(0x0000) +#define PWM_CH0_CC_B_BITS _u(0xffff0000) +#define PWM_CH0_CC_B_MSB _u(31) +#define PWM_CH0_CC_B_LSB _u(16) +#define PWM_CH0_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH0_CC_A +#define PWM_CH0_CC_A_RESET _u(0x0000) +#define PWM_CH0_CC_A_BITS _u(0x0000ffff) +#define PWM_CH0_CC_A_MSB _u(15) +#define PWM_CH0_CC_A_LSB _u(0) +#define PWM_CH0_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH0_TOP +// Description : Counter wrap value +#define PWM_CH0_TOP_OFFSET _u(0x00000010) +#define PWM_CH0_TOP_BITS _u(0x0000ffff) +#define PWM_CH0_TOP_RESET _u(0x0000ffff) +#define PWM_CH0_TOP_MSB _u(15) +#define PWM_CH0_TOP_LSB _u(0) +#define PWM_CH0_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_CSR +// Description : Control and status register +#define PWM_CH1_CSR_OFFSET _u(0x00000014) +#define PWM_CH1_CSR_BITS _u(0x000000ff) +#define PWM_CH1_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH1_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH1_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH1_CSR_PH_ADV_MSB _u(7) +#define PWM_CH1_CSR_PH_ADV_LSB _u(7) +#define PWM_CH1_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH1_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH1_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH1_CSR_PH_RET_MSB _u(6) +#define PWM_CH1_CSR_PH_RET_LSB _u(6) +#define PWM_CH1_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH1_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH1_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH1_CSR_DIVMODE_MSB _u(5) +#define PWM_CH1_CSR_DIVMODE_LSB _u(4) +#define PWM_CH1_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH1_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH1_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH1_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_B_INV +// Description : Invert output B +#define PWM_CH1_CSR_B_INV_RESET _u(0x0) +#define PWM_CH1_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH1_CSR_B_INV_MSB _u(3) +#define PWM_CH1_CSR_B_INV_LSB _u(3) +#define PWM_CH1_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_A_INV +// Description : Invert output A +#define PWM_CH1_CSR_A_INV_RESET _u(0x0) +#define PWM_CH1_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH1_CSR_A_INV_MSB _u(2) +#define PWM_CH1_CSR_A_INV_LSB _u(2) +#define PWM_CH1_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH1_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH1_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH1_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH1_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH1_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH1_CSR_EN_RESET _u(0x0) +#define PWM_CH1_CSR_EN_BITS _u(0x00000001) +#define PWM_CH1_CSR_EN_MSB _u(0) +#define PWM_CH1_CSR_EN_LSB _u(0) +#define PWM_CH1_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH1_DIV_OFFSET _u(0x00000018) +#define PWM_CH1_DIV_BITS _u(0x00000fff) +#define PWM_CH1_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_DIV_INT +#define PWM_CH1_DIV_INT_RESET _u(0x01) +#define PWM_CH1_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH1_DIV_INT_MSB _u(11) +#define PWM_CH1_DIV_INT_LSB _u(4) +#define PWM_CH1_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_DIV_FRAC +#define PWM_CH1_DIV_FRAC_RESET _u(0x0) +#define PWM_CH1_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH1_DIV_FRAC_MSB _u(3) +#define PWM_CH1_DIV_FRAC_LSB _u(0) +#define PWM_CH1_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_CTR +// Description : Direct access to the PWM counter +#define PWM_CH1_CTR_OFFSET _u(0x0000001c) +#define PWM_CH1_CTR_BITS _u(0x0000ffff) +#define PWM_CH1_CTR_RESET _u(0x00000000) +#define PWM_CH1_CTR_MSB _u(15) +#define PWM_CH1_CTR_LSB _u(0) +#define PWM_CH1_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_CC +// Description : Counter compare values +#define PWM_CH1_CC_OFFSET _u(0x00000020) +#define PWM_CH1_CC_BITS _u(0xffffffff) +#define PWM_CH1_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CC_B +#define PWM_CH1_CC_B_RESET _u(0x0000) +#define PWM_CH1_CC_B_BITS _u(0xffff0000) +#define PWM_CH1_CC_B_MSB _u(31) +#define PWM_CH1_CC_B_LSB _u(16) +#define PWM_CH1_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH1_CC_A +#define PWM_CH1_CC_A_RESET _u(0x0000) +#define PWM_CH1_CC_A_BITS _u(0x0000ffff) +#define PWM_CH1_CC_A_MSB _u(15) +#define PWM_CH1_CC_A_LSB _u(0) +#define PWM_CH1_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH1_TOP +// Description : Counter wrap value +#define PWM_CH1_TOP_OFFSET _u(0x00000024) +#define PWM_CH1_TOP_BITS _u(0x0000ffff) +#define PWM_CH1_TOP_RESET _u(0x0000ffff) +#define PWM_CH1_TOP_MSB _u(15) +#define PWM_CH1_TOP_LSB _u(0) +#define PWM_CH1_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_CSR +// Description : Control and status register +#define PWM_CH2_CSR_OFFSET _u(0x00000028) +#define PWM_CH2_CSR_BITS _u(0x000000ff) +#define PWM_CH2_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH2_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH2_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH2_CSR_PH_ADV_MSB _u(7) +#define PWM_CH2_CSR_PH_ADV_LSB _u(7) +#define PWM_CH2_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH2_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH2_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH2_CSR_PH_RET_MSB _u(6) +#define PWM_CH2_CSR_PH_RET_LSB _u(6) +#define PWM_CH2_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH2_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH2_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH2_CSR_DIVMODE_MSB _u(5) +#define PWM_CH2_CSR_DIVMODE_LSB _u(4) +#define PWM_CH2_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH2_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH2_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH2_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_B_INV +// Description : Invert output B +#define PWM_CH2_CSR_B_INV_RESET _u(0x0) +#define PWM_CH2_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH2_CSR_B_INV_MSB _u(3) +#define PWM_CH2_CSR_B_INV_LSB _u(3) +#define PWM_CH2_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_A_INV +// Description : Invert output A +#define PWM_CH2_CSR_A_INV_RESET _u(0x0) +#define PWM_CH2_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH2_CSR_A_INV_MSB _u(2) +#define PWM_CH2_CSR_A_INV_LSB _u(2) +#define PWM_CH2_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH2_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH2_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH2_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH2_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH2_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH2_CSR_EN_RESET _u(0x0) +#define PWM_CH2_CSR_EN_BITS _u(0x00000001) +#define PWM_CH2_CSR_EN_MSB _u(0) +#define PWM_CH2_CSR_EN_LSB _u(0) +#define PWM_CH2_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH2_DIV_OFFSET _u(0x0000002c) +#define PWM_CH2_DIV_BITS _u(0x00000fff) +#define PWM_CH2_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_DIV_INT +#define PWM_CH2_DIV_INT_RESET _u(0x01) +#define PWM_CH2_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH2_DIV_INT_MSB _u(11) +#define PWM_CH2_DIV_INT_LSB _u(4) +#define PWM_CH2_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_DIV_FRAC +#define PWM_CH2_DIV_FRAC_RESET _u(0x0) +#define PWM_CH2_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH2_DIV_FRAC_MSB _u(3) +#define PWM_CH2_DIV_FRAC_LSB _u(0) +#define PWM_CH2_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_CTR +// Description : Direct access to the PWM counter +#define PWM_CH2_CTR_OFFSET _u(0x00000030) +#define PWM_CH2_CTR_BITS _u(0x0000ffff) +#define PWM_CH2_CTR_RESET _u(0x00000000) +#define PWM_CH2_CTR_MSB _u(15) +#define PWM_CH2_CTR_LSB _u(0) +#define PWM_CH2_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_CC +// Description : Counter compare values +#define PWM_CH2_CC_OFFSET _u(0x00000034) +#define PWM_CH2_CC_BITS _u(0xffffffff) +#define PWM_CH2_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CC_B +#define PWM_CH2_CC_B_RESET _u(0x0000) +#define PWM_CH2_CC_B_BITS _u(0xffff0000) +#define PWM_CH2_CC_B_MSB _u(31) +#define PWM_CH2_CC_B_LSB _u(16) +#define PWM_CH2_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH2_CC_A +#define PWM_CH2_CC_A_RESET _u(0x0000) +#define PWM_CH2_CC_A_BITS _u(0x0000ffff) +#define PWM_CH2_CC_A_MSB _u(15) +#define PWM_CH2_CC_A_LSB _u(0) +#define PWM_CH2_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH2_TOP +// Description : Counter wrap value +#define PWM_CH2_TOP_OFFSET _u(0x00000038) +#define PWM_CH2_TOP_BITS _u(0x0000ffff) +#define PWM_CH2_TOP_RESET _u(0x0000ffff) +#define PWM_CH2_TOP_MSB _u(15) +#define PWM_CH2_TOP_LSB _u(0) +#define PWM_CH2_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_CSR +// Description : Control and status register +#define PWM_CH3_CSR_OFFSET _u(0x0000003c) +#define PWM_CH3_CSR_BITS _u(0x000000ff) +#define PWM_CH3_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH3_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH3_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH3_CSR_PH_ADV_MSB _u(7) +#define PWM_CH3_CSR_PH_ADV_LSB _u(7) +#define PWM_CH3_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH3_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH3_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH3_CSR_PH_RET_MSB _u(6) +#define PWM_CH3_CSR_PH_RET_LSB _u(6) +#define PWM_CH3_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH3_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH3_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH3_CSR_DIVMODE_MSB _u(5) +#define PWM_CH3_CSR_DIVMODE_LSB _u(4) +#define PWM_CH3_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH3_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH3_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH3_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_B_INV +// Description : Invert output B +#define PWM_CH3_CSR_B_INV_RESET _u(0x0) +#define PWM_CH3_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH3_CSR_B_INV_MSB _u(3) +#define PWM_CH3_CSR_B_INV_LSB _u(3) +#define PWM_CH3_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_A_INV +// Description : Invert output A +#define PWM_CH3_CSR_A_INV_RESET _u(0x0) +#define PWM_CH3_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH3_CSR_A_INV_MSB _u(2) +#define PWM_CH3_CSR_A_INV_LSB _u(2) +#define PWM_CH3_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH3_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH3_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH3_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH3_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH3_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH3_CSR_EN_RESET _u(0x0) +#define PWM_CH3_CSR_EN_BITS _u(0x00000001) +#define PWM_CH3_CSR_EN_MSB _u(0) +#define PWM_CH3_CSR_EN_LSB _u(0) +#define PWM_CH3_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH3_DIV_OFFSET _u(0x00000040) +#define PWM_CH3_DIV_BITS _u(0x00000fff) +#define PWM_CH3_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_DIV_INT +#define PWM_CH3_DIV_INT_RESET _u(0x01) +#define PWM_CH3_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH3_DIV_INT_MSB _u(11) +#define PWM_CH3_DIV_INT_LSB _u(4) +#define PWM_CH3_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_DIV_FRAC +#define PWM_CH3_DIV_FRAC_RESET _u(0x0) +#define PWM_CH3_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH3_DIV_FRAC_MSB _u(3) +#define PWM_CH3_DIV_FRAC_LSB _u(0) +#define PWM_CH3_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_CTR +// Description : Direct access to the PWM counter +#define PWM_CH3_CTR_OFFSET _u(0x00000044) +#define PWM_CH3_CTR_BITS _u(0x0000ffff) +#define PWM_CH3_CTR_RESET _u(0x00000000) +#define PWM_CH3_CTR_MSB _u(15) +#define PWM_CH3_CTR_LSB _u(0) +#define PWM_CH3_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_CC +// Description : Counter compare values +#define PWM_CH3_CC_OFFSET _u(0x00000048) +#define PWM_CH3_CC_BITS _u(0xffffffff) +#define PWM_CH3_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CC_B +#define PWM_CH3_CC_B_RESET _u(0x0000) +#define PWM_CH3_CC_B_BITS _u(0xffff0000) +#define PWM_CH3_CC_B_MSB _u(31) +#define PWM_CH3_CC_B_LSB _u(16) +#define PWM_CH3_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH3_CC_A +#define PWM_CH3_CC_A_RESET _u(0x0000) +#define PWM_CH3_CC_A_BITS _u(0x0000ffff) +#define PWM_CH3_CC_A_MSB _u(15) +#define PWM_CH3_CC_A_LSB _u(0) +#define PWM_CH3_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH3_TOP +// Description : Counter wrap value +#define PWM_CH3_TOP_OFFSET _u(0x0000004c) +#define PWM_CH3_TOP_BITS _u(0x0000ffff) +#define PWM_CH3_TOP_RESET _u(0x0000ffff) +#define PWM_CH3_TOP_MSB _u(15) +#define PWM_CH3_TOP_LSB _u(0) +#define PWM_CH3_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_CSR +// Description : Control and status register +#define PWM_CH4_CSR_OFFSET _u(0x00000050) +#define PWM_CH4_CSR_BITS _u(0x000000ff) +#define PWM_CH4_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH4_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH4_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH4_CSR_PH_ADV_MSB _u(7) +#define PWM_CH4_CSR_PH_ADV_LSB _u(7) +#define PWM_CH4_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH4_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH4_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH4_CSR_PH_RET_MSB _u(6) +#define PWM_CH4_CSR_PH_RET_LSB _u(6) +#define PWM_CH4_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH4_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH4_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH4_CSR_DIVMODE_MSB _u(5) +#define PWM_CH4_CSR_DIVMODE_LSB _u(4) +#define PWM_CH4_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH4_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH4_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH4_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_B_INV +// Description : Invert output B +#define PWM_CH4_CSR_B_INV_RESET _u(0x0) +#define PWM_CH4_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH4_CSR_B_INV_MSB _u(3) +#define PWM_CH4_CSR_B_INV_LSB _u(3) +#define PWM_CH4_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_A_INV +// Description : Invert output A +#define PWM_CH4_CSR_A_INV_RESET _u(0x0) +#define PWM_CH4_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH4_CSR_A_INV_MSB _u(2) +#define PWM_CH4_CSR_A_INV_LSB _u(2) +#define PWM_CH4_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH4_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH4_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH4_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH4_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH4_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH4_CSR_EN_RESET _u(0x0) +#define PWM_CH4_CSR_EN_BITS _u(0x00000001) +#define PWM_CH4_CSR_EN_MSB _u(0) +#define PWM_CH4_CSR_EN_LSB _u(0) +#define PWM_CH4_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH4_DIV_OFFSET _u(0x00000054) +#define PWM_CH4_DIV_BITS _u(0x00000fff) +#define PWM_CH4_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_DIV_INT +#define PWM_CH4_DIV_INT_RESET _u(0x01) +#define PWM_CH4_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH4_DIV_INT_MSB _u(11) +#define PWM_CH4_DIV_INT_LSB _u(4) +#define PWM_CH4_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_DIV_FRAC +#define PWM_CH4_DIV_FRAC_RESET _u(0x0) +#define PWM_CH4_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH4_DIV_FRAC_MSB _u(3) +#define PWM_CH4_DIV_FRAC_LSB _u(0) +#define PWM_CH4_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_CTR +// Description : Direct access to the PWM counter +#define PWM_CH4_CTR_OFFSET _u(0x00000058) +#define PWM_CH4_CTR_BITS _u(0x0000ffff) +#define PWM_CH4_CTR_RESET _u(0x00000000) +#define PWM_CH4_CTR_MSB _u(15) +#define PWM_CH4_CTR_LSB _u(0) +#define PWM_CH4_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_CC +// Description : Counter compare values +#define PWM_CH4_CC_OFFSET _u(0x0000005c) +#define PWM_CH4_CC_BITS _u(0xffffffff) +#define PWM_CH4_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CC_B +#define PWM_CH4_CC_B_RESET _u(0x0000) +#define PWM_CH4_CC_B_BITS _u(0xffff0000) +#define PWM_CH4_CC_B_MSB _u(31) +#define PWM_CH4_CC_B_LSB _u(16) +#define PWM_CH4_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH4_CC_A +#define PWM_CH4_CC_A_RESET _u(0x0000) +#define PWM_CH4_CC_A_BITS _u(0x0000ffff) +#define PWM_CH4_CC_A_MSB _u(15) +#define PWM_CH4_CC_A_LSB _u(0) +#define PWM_CH4_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH4_TOP +// Description : Counter wrap value +#define PWM_CH4_TOP_OFFSET _u(0x00000060) +#define PWM_CH4_TOP_BITS _u(0x0000ffff) +#define PWM_CH4_TOP_RESET _u(0x0000ffff) +#define PWM_CH4_TOP_MSB _u(15) +#define PWM_CH4_TOP_LSB _u(0) +#define PWM_CH4_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_CSR +// Description : Control and status register +#define PWM_CH5_CSR_OFFSET _u(0x00000064) +#define PWM_CH5_CSR_BITS _u(0x000000ff) +#define PWM_CH5_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH5_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH5_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH5_CSR_PH_ADV_MSB _u(7) +#define PWM_CH5_CSR_PH_ADV_LSB _u(7) +#define PWM_CH5_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH5_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH5_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH5_CSR_PH_RET_MSB _u(6) +#define PWM_CH5_CSR_PH_RET_LSB _u(6) +#define PWM_CH5_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH5_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH5_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH5_CSR_DIVMODE_MSB _u(5) +#define PWM_CH5_CSR_DIVMODE_LSB _u(4) +#define PWM_CH5_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH5_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH5_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH5_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_B_INV +// Description : Invert output B +#define PWM_CH5_CSR_B_INV_RESET _u(0x0) +#define PWM_CH5_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH5_CSR_B_INV_MSB _u(3) +#define PWM_CH5_CSR_B_INV_LSB _u(3) +#define PWM_CH5_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_A_INV +// Description : Invert output A +#define PWM_CH5_CSR_A_INV_RESET _u(0x0) +#define PWM_CH5_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH5_CSR_A_INV_MSB _u(2) +#define PWM_CH5_CSR_A_INV_LSB _u(2) +#define PWM_CH5_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH5_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH5_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH5_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH5_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH5_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH5_CSR_EN_RESET _u(0x0) +#define PWM_CH5_CSR_EN_BITS _u(0x00000001) +#define PWM_CH5_CSR_EN_MSB _u(0) +#define PWM_CH5_CSR_EN_LSB _u(0) +#define PWM_CH5_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH5_DIV_OFFSET _u(0x00000068) +#define PWM_CH5_DIV_BITS _u(0x00000fff) +#define PWM_CH5_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_DIV_INT +#define PWM_CH5_DIV_INT_RESET _u(0x01) +#define PWM_CH5_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH5_DIV_INT_MSB _u(11) +#define PWM_CH5_DIV_INT_LSB _u(4) +#define PWM_CH5_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_DIV_FRAC +#define PWM_CH5_DIV_FRAC_RESET _u(0x0) +#define PWM_CH5_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH5_DIV_FRAC_MSB _u(3) +#define PWM_CH5_DIV_FRAC_LSB _u(0) +#define PWM_CH5_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_CTR +// Description : Direct access to the PWM counter +#define PWM_CH5_CTR_OFFSET _u(0x0000006c) +#define PWM_CH5_CTR_BITS _u(0x0000ffff) +#define PWM_CH5_CTR_RESET _u(0x00000000) +#define PWM_CH5_CTR_MSB _u(15) +#define PWM_CH5_CTR_LSB _u(0) +#define PWM_CH5_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_CC +// Description : Counter compare values +#define PWM_CH5_CC_OFFSET _u(0x00000070) +#define PWM_CH5_CC_BITS _u(0xffffffff) +#define PWM_CH5_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CC_B +#define PWM_CH5_CC_B_RESET _u(0x0000) +#define PWM_CH5_CC_B_BITS _u(0xffff0000) +#define PWM_CH5_CC_B_MSB _u(31) +#define PWM_CH5_CC_B_LSB _u(16) +#define PWM_CH5_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH5_CC_A +#define PWM_CH5_CC_A_RESET _u(0x0000) +#define PWM_CH5_CC_A_BITS _u(0x0000ffff) +#define PWM_CH5_CC_A_MSB _u(15) +#define PWM_CH5_CC_A_LSB _u(0) +#define PWM_CH5_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH5_TOP +// Description : Counter wrap value +#define PWM_CH5_TOP_OFFSET _u(0x00000074) +#define PWM_CH5_TOP_BITS _u(0x0000ffff) +#define PWM_CH5_TOP_RESET _u(0x0000ffff) +#define PWM_CH5_TOP_MSB _u(15) +#define PWM_CH5_TOP_LSB _u(0) +#define PWM_CH5_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_CSR +// Description : Control and status register +#define PWM_CH6_CSR_OFFSET _u(0x00000078) +#define PWM_CH6_CSR_BITS _u(0x000000ff) +#define PWM_CH6_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH6_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH6_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH6_CSR_PH_ADV_MSB _u(7) +#define PWM_CH6_CSR_PH_ADV_LSB _u(7) +#define PWM_CH6_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH6_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH6_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH6_CSR_PH_RET_MSB _u(6) +#define PWM_CH6_CSR_PH_RET_LSB _u(6) +#define PWM_CH6_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH6_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH6_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH6_CSR_DIVMODE_MSB _u(5) +#define PWM_CH6_CSR_DIVMODE_LSB _u(4) +#define PWM_CH6_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH6_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH6_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH6_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_B_INV +// Description : Invert output B +#define PWM_CH6_CSR_B_INV_RESET _u(0x0) +#define PWM_CH6_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH6_CSR_B_INV_MSB _u(3) +#define PWM_CH6_CSR_B_INV_LSB _u(3) +#define PWM_CH6_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_A_INV +// Description : Invert output A +#define PWM_CH6_CSR_A_INV_RESET _u(0x0) +#define PWM_CH6_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH6_CSR_A_INV_MSB _u(2) +#define PWM_CH6_CSR_A_INV_LSB _u(2) +#define PWM_CH6_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH6_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH6_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH6_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH6_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH6_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH6_CSR_EN_RESET _u(0x0) +#define PWM_CH6_CSR_EN_BITS _u(0x00000001) +#define PWM_CH6_CSR_EN_MSB _u(0) +#define PWM_CH6_CSR_EN_LSB _u(0) +#define PWM_CH6_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH6_DIV_OFFSET _u(0x0000007c) +#define PWM_CH6_DIV_BITS _u(0x00000fff) +#define PWM_CH6_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_DIV_INT +#define PWM_CH6_DIV_INT_RESET _u(0x01) +#define PWM_CH6_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH6_DIV_INT_MSB _u(11) +#define PWM_CH6_DIV_INT_LSB _u(4) +#define PWM_CH6_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_DIV_FRAC +#define PWM_CH6_DIV_FRAC_RESET _u(0x0) +#define PWM_CH6_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH6_DIV_FRAC_MSB _u(3) +#define PWM_CH6_DIV_FRAC_LSB _u(0) +#define PWM_CH6_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_CTR +// Description : Direct access to the PWM counter +#define PWM_CH6_CTR_OFFSET _u(0x00000080) +#define PWM_CH6_CTR_BITS _u(0x0000ffff) +#define PWM_CH6_CTR_RESET _u(0x00000000) +#define PWM_CH6_CTR_MSB _u(15) +#define PWM_CH6_CTR_LSB _u(0) +#define PWM_CH6_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_CC +// Description : Counter compare values +#define PWM_CH6_CC_OFFSET _u(0x00000084) +#define PWM_CH6_CC_BITS _u(0xffffffff) +#define PWM_CH6_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CC_B +#define PWM_CH6_CC_B_RESET _u(0x0000) +#define PWM_CH6_CC_B_BITS _u(0xffff0000) +#define PWM_CH6_CC_B_MSB _u(31) +#define PWM_CH6_CC_B_LSB _u(16) +#define PWM_CH6_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH6_CC_A +#define PWM_CH6_CC_A_RESET _u(0x0000) +#define PWM_CH6_CC_A_BITS _u(0x0000ffff) +#define PWM_CH6_CC_A_MSB _u(15) +#define PWM_CH6_CC_A_LSB _u(0) +#define PWM_CH6_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH6_TOP +// Description : Counter wrap value +#define PWM_CH6_TOP_OFFSET _u(0x00000088) +#define PWM_CH6_TOP_BITS _u(0x0000ffff) +#define PWM_CH6_TOP_RESET _u(0x0000ffff) +#define PWM_CH6_TOP_MSB _u(15) +#define PWM_CH6_TOP_LSB _u(0) +#define PWM_CH6_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_CSR +// Description : Control and status register +#define PWM_CH7_CSR_OFFSET _u(0x0000008c) +#define PWM_CH7_CSR_BITS _u(0x000000ff) +#define PWM_CH7_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH7_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH7_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH7_CSR_PH_ADV_MSB _u(7) +#define PWM_CH7_CSR_PH_ADV_LSB _u(7) +#define PWM_CH7_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH7_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH7_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH7_CSR_PH_RET_MSB _u(6) +#define PWM_CH7_CSR_PH_RET_LSB _u(6) +#define PWM_CH7_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH7_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH7_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH7_CSR_DIVMODE_MSB _u(5) +#define PWM_CH7_CSR_DIVMODE_LSB _u(4) +#define PWM_CH7_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH7_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH7_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH7_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_B_INV +// Description : Invert output B +#define PWM_CH7_CSR_B_INV_RESET _u(0x0) +#define PWM_CH7_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH7_CSR_B_INV_MSB _u(3) +#define PWM_CH7_CSR_B_INV_LSB _u(3) +#define PWM_CH7_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_A_INV +// Description : Invert output A +#define PWM_CH7_CSR_A_INV_RESET _u(0x0) +#define PWM_CH7_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH7_CSR_A_INV_MSB _u(2) +#define PWM_CH7_CSR_A_INV_LSB _u(2) +#define PWM_CH7_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH7_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH7_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH7_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH7_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH7_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH7_CSR_EN_RESET _u(0x0) +#define PWM_CH7_CSR_EN_BITS _u(0x00000001) +#define PWM_CH7_CSR_EN_MSB _u(0) +#define PWM_CH7_CSR_EN_LSB _u(0) +#define PWM_CH7_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH7_DIV_OFFSET _u(0x00000090) +#define PWM_CH7_DIV_BITS _u(0x00000fff) +#define PWM_CH7_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_DIV_INT +#define PWM_CH7_DIV_INT_RESET _u(0x01) +#define PWM_CH7_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH7_DIV_INT_MSB _u(11) +#define PWM_CH7_DIV_INT_LSB _u(4) +#define PWM_CH7_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_DIV_FRAC +#define PWM_CH7_DIV_FRAC_RESET _u(0x0) +#define PWM_CH7_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH7_DIV_FRAC_MSB _u(3) +#define PWM_CH7_DIV_FRAC_LSB _u(0) +#define PWM_CH7_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_CTR +// Description : Direct access to the PWM counter +#define PWM_CH7_CTR_OFFSET _u(0x00000094) +#define PWM_CH7_CTR_BITS _u(0x0000ffff) +#define PWM_CH7_CTR_RESET _u(0x00000000) +#define PWM_CH7_CTR_MSB _u(15) +#define PWM_CH7_CTR_LSB _u(0) +#define PWM_CH7_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_CC +// Description : Counter compare values +#define PWM_CH7_CC_OFFSET _u(0x00000098) +#define PWM_CH7_CC_BITS _u(0xffffffff) +#define PWM_CH7_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CC_B +#define PWM_CH7_CC_B_RESET _u(0x0000) +#define PWM_CH7_CC_B_BITS _u(0xffff0000) +#define PWM_CH7_CC_B_MSB _u(31) +#define PWM_CH7_CC_B_LSB _u(16) +#define PWM_CH7_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH7_CC_A +#define PWM_CH7_CC_A_RESET _u(0x0000) +#define PWM_CH7_CC_A_BITS _u(0x0000ffff) +#define PWM_CH7_CC_A_MSB _u(15) +#define PWM_CH7_CC_A_LSB _u(0) +#define PWM_CH7_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH7_TOP +// Description : Counter wrap value +#define PWM_CH7_TOP_OFFSET _u(0x0000009c) +#define PWM_CH7_TOP_BITS _u(0x0000ffff) +#define PWM_CH7_TOP_RESET _u(0x0000ffff) +#define PWM_CH7_TOP_MSB _u(15) +#define PWM_CH7_TOP_LSB _u(0) +#define PWM_CH7_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH8_CSR +// Description : Control and status register +#define PWM_CH8_CSR_OFFSET _u(0x000000a0) +#define PWM_CH8_CSR_BITS _u(0x000000ff) +#define PWM_CH8_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH8_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH8_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH8_CSR_PH_ADV_MSB _u(7) +#define PWM_CH8_CSR_PH_ADV_LSB _u(7) +#define PWM_CH8_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH8_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH8_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH8_CSR_PH_RET_MSB _u(6) +#define PWM_CH8_CSR_PH_RET_LSB _u(6) +#define PWM_CH8_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH8_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH8_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH8_CSR_DIVMODE_MSB _u(5) +#define PWM_CH8_CSR_DIVMODE_LSB _u(4) +#define PWM_CH8_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH8_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH8_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH8_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH8_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CSR_B_INV +// Description : Invert output B +#define PWM_CH8_CSR_B_INV_RESET _u(0x0) +#define PWM_CH8_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH8_CSR_B_INV_MSB _u(3) +#define PWM_CH8_CSR_B_INV_LSB _u(3) +#define PWM_CH8_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CSR_A_INV +// Description : Invert output A +#define PWM_CH8_CSR_A_INV_RESET _u(0x0) +#define PWM_CH8_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH8_CSR_A_INV_MSB _u(2) +#define PWM_CH8_CSR_A_INV_LSB _u(2) +#define PWM_CH8_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH8_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH8_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH8_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH8_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH8_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH8_CSR_EN_RESET _u(0x0) +#define PWM_CH8_CSR_EN_BITS _u(0x00000001) +#define PWM_CH8_CSR_EN_MSB _u(0) +#define PWM_CH8_CSR_EN_LSB _u(0) +#define PWM_CH8_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH8_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH8_DIV_OFFSET _u(0x000000a4) +#define PWM_CH8_DIV_BITS _u(0x00000fff) +#define PWM_CH8_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_DIV_INT +#define PWM_CH8_DIV_INT_RESET _u(0x01) +#define PWM_CH8_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH8_DIV_INT_MSB _u(11) +#define PWM_CH8_DIV_INT_LSB _u(4) +#define PWM_CH8_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_DIV_FRAC +#define PWM_CH8_DIV_FRAC_RESET _u(0x0) +#define PWM_CH8_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH8_DIV_FRAC_MSB _u(3) +#define PWM_CH8_DIV_FRAC_LSB _u(0) +#define PWM_CH8_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH8_CTR +// Description : Direct access to the PWM counter +#define PWM_CH8_CTR_OFFSET _u(0x000000a8) +#define PWM_CH8_CTR_BITS _u(0x0000ffff) +#define PWM_CH8_CTR_RESET _u(0x00000000) +#define PWM_CH8_CTR_MSB _u(15) +#define PWM_CH8_CTR_LSB _u(0) +#define PWM_CH8_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH8_CC +// Description : Counter compare values +#define PWM_CH8_CC_OFFSET _u(0x000000ac) +#define PWM_CH8_CC_BITS _u(0xffffffff) +#define PWM_CH8_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CC_B +#define PWM_CH8_CC_B_RESET _u(0x0000) +#define PWM_CH8_CC_B_BITS _u(0xffff0000) +#define PWM_CH8_CC_B_MSB _u(31) +#define PWM_CH8_CC_B_LSB _u(16) +#define PWM_CH8_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH8_CC_A +#define PWM_CH8_CC_A_RESET _u(0x0000) +#define PWM_CH8_CC_A_BITS _u(0x0000ffff) +#define PWM_CH8_CC_A_MSB _u(15) +#define PWM_CH8_CC_A_LSB _u(0) +#define PWM_CH8_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH8_TOP +// Description : Counter wrap value +#define PWM_CH8_TOP_OFFSET _u(0x000000b0) +#define PWM_CH8_TOP_BITS _u(0x0000ffff) +#define PWM_CH8_TOP_RESET _u(0x0000ffff) +#define PWM_CH8_TOP_MSB _u(15) +#define PWM_CH8_TOP_LSB _u(0) +#define PWM_CH8_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH9_CSR +// Description : Control and status register +#define PWM_CH9_CSR_OFFSET _u(0x000000b4) +#define PWM_CH9_CSR_BITS _u(0x000000ff) +#define PWM_CH9_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH9_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH9_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH9_CSR_PH_ADV_MSB _u(7) +#define PWM_CH9_CSR_PH_ADV_LSB _u(7) +#define PWM_CH9_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH9_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH9_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH9_CSR_PH_RET_MSB _u(6) +#define PWM_CH9_CSR_PH_RET_LSB _u(6) +#define PWM_CH9_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH9_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH9_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH9_CSR_DIVMODE_MSB _u(5) +#define PWM_CH9_CSR_DIVMODE_LSB _u(4) +#define PWM_CH9_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH9_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH9_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH9_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH9_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CSR_B_INV +// Description : Invert output B +#define PWM_CH9_CSR_B_INV_RESET _u(0x0) +#define PWM_CH9_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH9_CSR_B_INV_MSB _u(3) +#define PWM_CH9_CSR_B_INV_LSB _u(3) +#define PWM_CH9_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CSR_A_INV +// Description : Invert output A +#define PWM_CH9_CSR_A_INV_RESET _u(0x0) +#define PWM_CH9_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH9_CSR_A_INV_MSB _u(2) +#define PWM_CH9_CSR_A_INV_LSB _u(2) +#define PWM_CH9_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH9_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH9_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH9_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH9_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH9_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH9_CSR_EN_RESET _u(0x0) +#define PWM_CH9_CSR_EN_BITS _u(0x00000001) +#define PWM_CH9_CSR_EN_MSB _u(0) +#define PWM_CH9_CSR_EN_LSB _u(0) +#define PWM_CH9_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH9_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH9_DIV_OFFSET _u(0x000000b8) +#define PWM_CH9_DIV_BITS _u(0x00000fff) +#define PWM_CH9_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_DIV_INT +#define PWM_CH9_DIV_INT_RESET _u(0x01) +#define PWM_CH9_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH9_DIV_INT_MSB _u(11) +#define PWM_CH9_DIV_INT_LSB _u(4) +#define PWM_CH9_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_DIV_FRAC +#define PWM_CH9_DIV_FRAC_RESET _u(0x0) +#define PWM_CH9_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH9_DIV_FRAC_MSB _u(3) +#define PWM_CH9_DIV_FRAC_LSB _u(0) +#define PWM_CH9_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH9_CTR +// Description : Direct access to the PWM counter +#define PWM_CH9_CTR_OFFSET _u(0x000000bc) +#define PWM_CH9_CTR_BITS _u(0x0000ffff) +#define PWM_CH9_CTR_RESET _u(0x00000000) +#define PWM_CH9_CTR_MSB _u(15) +#define PWM_CH9_CTR_LSB _u(0) +#define PWM_CH9_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH9_CC +// Description : Counter compare values +#define PWM_CH9_CC_OFFSET _u(0x000000c0) +#define PWM_CH9_CC_BITS _u(0xffffffff) +#define PWM_CH9_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CC_B +#define PWM_CH9_CC_B_RESET _u(0x0000) +#define PWM_CH9_CC_B_BITS _u(0xffff0000) +#define PWM_CH9_CC_B_MSB _u(31) +#define PWM_CH9_CC_B_LSB _u(16) +#define PWM_CH9_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH9_CC_A +#define PWM_CH9_CC_A_RESET _u(0x0000) +#define PWM_CH9_CC_A_BITS _u(0x0000ffff) +#define PWM_CH9_CC_A_MSB _u(15) +#define PWM_CH9_CC_A_LSB _u(0) +#define PWM_CH9_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH9_TOP +// Description : Counter wrap value +#define PWM_CH9_TOP_OFFSET _u(0x000000c4) +#define PWM_CH9_TOP_BITS _u(0x0000ffff) +#define PWM_CH9_TOP_RESET _u(0x0000ffff) +#define PWM_CH9_TOP_MSB _u(15) +#define PWM_CH9_TOP_LSB _u(0) +#define PWM_CH9_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH10_CSR +// Description : Control and status register +#define PWM_CH10_CSR_OFFSET _u(0x000000c8) +#define PWM_CH10_CSR_BITS _u(0x000000ff) +#define PWM_CH10_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH10_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH10_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH10_CSR_PH_ADV_MSB _u(7) +#define PWM_CH10_CSR_PH_ADV_LSB _u(7) +#define PWM_CH10_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH10_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH10_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH10_CSR_PH_RET_MSB _u(6) +#define PWM_CH10_CSR_PH_RET_LSB _u(6) +#define PWM_CH10_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH10_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH10_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH10_CSR_DIVMODE_MSB _u(5) +#define PWM_CH10_CSR_DIVMODE_LSB _u(4) +#define PWM_CH10_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH10_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH10_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH10_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH10_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CSR_B_INV +// Description : Invert output B +#define PWM_CH10_CSR_B_INV_RESET _u(0x0) +#define PWM_CH10_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH10_CSR_B_INV_MSB _u(3) +#define PWM_CH10_CSR_B_INV_LSB _u(3) +#define PWM_CH10_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CSR_A_INV +// Description : Invert output A +#define PWM_CH10_CSR_A_INV_RESET _u(0x0) +#define PWM_CH10_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH10_CSR_A_INV_MSB _u(2) +#define PWM_CH10_CSR_A_INV_LSB _u(2) +#define PWM_CH10_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH10_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH10_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH10_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH10_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH10_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH10_CSR_EN_RESET _u(0x0) +#define PWM_CH10_CSR_EN_BITS _u(0x00000001) +#define PWM_CH10_CSR_EN_MSB _u(0) +#define PWM_CH10_CSR_EN_LSB _u(0) +#define PWM_CH10_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH10_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH10_DIV_OFFSET _u(0x000000cc) +#define PWM_CH10_DIV_BITS _u(0x00000fff) +#define PWM_CH10_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_DIV_INT +#define PWM_CH10_DIV_INT_RESET _u(0x01) +#define PWM_CH10_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH10_DIV_INT_MSB _u(11) +#define PWM_CH10_DIV_INT_LSB _u(4) +#define PWM_CH10_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_DIV_FRAC +#define PWM_CH10_DIV_FRAC_RESET _u(0x0) +#define PWM_CH10_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH10_DIV_FRAC_MSB _u(3) +#define PWM_CH10_DIV_FRAC_LSB _u(0) +#define PWM_CH10_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH10_CTR +// Description : Direct access to the PWM counter +#define PWM_CH10_CTR_OFFSET _u(0x000000d0) +#define PWM_CH10_CTR_BITS _u(0x0000ffff) +#define PWM_CH10_CTR_RESET _u(0x00000000) +#define PWM_CH10_CTR_MSB _u(15) +#define PWM_CH10_CTR_LSB _u(0) +#define PWM_CH10_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH10_CC +// Description : Counter compare values +#define PWM_CH10_CC_OFFSET _u(0x000000d4) +#define PWM_CH10_CC_BITS _u(0xffffffff) +#define PWM_CH10_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CC_B +#define PWM_CH10_CC_B_RESET _u(0x0000) +#define PWM_CH10_CC_B_BITS _u(0xffff0000) +#define PWM_CH10_CC_B_MSB _u(31) +#define PWM_CH10_CC_B_LSB _u(16) +#define PWM_CH10_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH10_CC_A +#define PWM_CH10_CC_A_RESET _u(0x0000) +#define PWM_CH10_CC_A_BITS _u(0x0000ffff) +#define PWM_CH10_CC_A_MSB _u(15) +#define PWM_CH10_CC_A_LSB _u(0) +#define PWM_CH10_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH10_TOP +// Description : Counter wrap value +#define PWM_CH10_TOP_OFFSET _u(0x000000d8) +#define PWM_CH10_TOP_BITS _u(0x0000ffff) +#define PWM_CH10_TOP_RESET _u(0x0000ffff) +#define PWM_CH10_TOP_MSB _u(15) +#define PWM_CH10_TOP_LSB _u(0) +#define PWM_CH10_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH11_CSR +// Description : Control and status register +#define PWM_CH11_CSR_OFFSET _u(0x000000dc) +#define PWM_CH11_CSR_BITS _u(0x000000ff) +#define PWM_CH11_CSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CSR_PH_ADV +// Description : Advance the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running +// at less than full speed (div_int + div_frac / 16 > 1) +#define PWM_CH11_CSR_PH_ADV_RESET _u(0x0) +#define PWM_CH11_CSR_PH_ADV_BITS _u(0x00000080) +#define PWM_CH11_CSR_PH_ADV_MSB _u(7) +#define PWM_CH11_CSR_PH_ADV_LSB _u(7) +#define PWM_CH11_CSR_PH_ADV_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CSR_PH_RET +// Description : Retard the phase of the counter by 1 count, while it is +// running. +// Self-clearing. Write a 1, and poll until low. Counter must be +// running. +#define PWM_CH11_CSR_PH_RET_RESET _u(0x0) +#define PWM_CH11_CSR_PH_RET_BITS _u(0x00000040) +#define PWM_CH11_CSR_PH_RET_MSB _u(6) +#define PWM_CH11_CSR_PH_RET_LSB _u(6) +#define PWM_CH11_CSR_PH_RET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CSR_DIVMODE +// 0x0 -> Free-running counting at rate dictated by fractional divider +// 0x1 -> Fractional divider operation is gated by the PWM B pin. +// 0x2 -> Counter advances with each rising edge of the PWM B pin. +// 0x3 -> Counter advances with each falling edge of the PWM B pin. +#define PWM_CH11_CSR_DIVMODE_RESET _u(0x0) +#define PWM_CH11_CSR_DIVMODE_BITS _u(0x00000030) +#define PWM_CH11_CSR_DIVMODE_MSB _u(5) +#define PWM_CH11_CSR_DIVMODE_LSB _u(4) +#define PWM_CH11_CSR_DIVMODE_ACCESS "RW" +#define PWM_CH11_CSR_DIVMODE_VALUE_DIV _u(0x0) +#define PWM_CH11_CSR_DIVMODE_VALUE_LEVEL _u(0x1) +#define PWM_CH11_CSR_DIVMODE_VALUE_RISE _u(0x2) +#define PWM_CH11_CSR_DIVMODE_VALUE_FALL _u(0x3) +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CSR_B_INV +// Description : Invert output B +#define PWM_CH11_CSR_B_INV_RESET _u(0x0) +#define PWM_CH11_CSR_B_INV_BITS _u(0x00000008) +#define PWM_CH11_CSR_B_INV_MSB _u(3) +#define PWM_CH11_CSR_B_INV_LSB _u(3) +#define PWM_CH11_CSR_B_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CSR_A_INV +// Description : Invert output A +#define PWM_CH11_CSR_A_INV_RESET _u(0x0) +#define PWM_CH11_CSR_A_INV_BITS _u(0x00000004) +#define PWM_CH11_CSR_A_INV_MSB _u(2) +#define PWM_CH11_CSR_A_INV_LSB _u(2) +#define PWM_CH11_CSR_A_INV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CSR_PH_CORRECT +// Description : 1: Enable phase-correct modulation. 0: Trailing-edge +#define PWM_CH11_CSR_PH_CORRECT_RESET _u(0x0) +#define PWM_CH11_CSR_PH_CORRECT_BITS _u(0x00000002) +#define PWM_CH11_CSR_PH_CORRECT_MSB _u(1) +#define PWM_CH11_CSR_PH_CORRECT_LSB _u(1) +#define PWM_CH11_CSR_PH_CORRECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CSR_EN +// Description : Enable the PWM channel. +#define PWM_CH11_CSR_EN_RESET _u(0x0) +#define PWM_CH11_CSR_EN_BITS _u(0x00000001) +#define PWM_CH11_CSR_EN_MSB _u(0) +#define PWM_CH11_CSR_EN_LSB _u(0) +#define PWM_CH11_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH11_DIV +// Description : INT and FRAC form a fixed-point fractional number. +// Counting rate is system clock frequency divided by this number. +// Fractional division uses simple 1st-order sigma-delta. +#define PWM_CH11_DIV_OFFSET _u(0x000000e0) +#define PWM_CH11_DIV_BITS _u(0x00000fff) +#define PWM_CH11_DIV_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_DIV_INT +#define PWM_CH11_DIV_INT_RESET _u(0x01) +#define PWM_CH11_DIV_INT_BITS _u(0x00000ff0) +#define PWM_CH11_DIV_INT_MSB _u(11) +#define PWM_CH11_DIV_INT_LSB _u(4) +#define PWM_CH11_DIV_INT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_DIV_FRAC +#define PWM_CH11_DIV_FRAC_RESET _u(0x0) +#define PWM_CH11_DIV_FRAC_BITS _u(0x0000000f) +#define PWM_CH11_DIV_FRAC_MSB _u(3) +#define PWM_CH11_DIV_FRAC_LSB _u(0) +#define PWM_CH11_DIV_FRAC_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH11_CTR +// Description : Direct access to the PWM counter +#define PWM_CH11_CTR_OFFSET _u(0x000000e4) +#define PWM_CH11_CTR_BITS _u(0x0000ffff) +#define PWM_CH11_CTR_RESET _u(0x00000000) +#define PWM_CH11_CTR_MSB _u(15) +#define PWM_CH11_CTR_LSB _u(0) +#define PWM_CH11_CTR_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH11_CC +// Description : Counter compare values +#define PWM_CH11_CC_OFFSET _u(0x000000e8) +#define PWM_CH11_CC_BITS _u(0xffffffff) +#define PWM_CH11_CC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CC_B +#define PWM_CH11_CC_B_RESET _u(0x0000) +#define PWM_CH11_CC_B_BITS _u(0xffff0000) +#define PWM_CH11_CC_B_MSB _u(31) +#define PWM_CH11_CC_B_LSB _u(16) +#define PWM_CH11_CC_B_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_CH11_CC_A +#define PWM_CH11_CC_A_RESET _u(0x0000) +#define PWM_CH11_CC_A_BITS _u(0x0000ffff) +#define PWM_CH11_CC_A_MSB _u(15) +#define PWM_CH11_CC_A_LSB _u(0) +#define PWM_CH11_CC_A_ACCESS "RW" +// ============================================================================= +// Register : PWM_CH11_TOP +// Description : Counter wrap value +#define PWM_CH11_TOP_OFFSET _u(0x000000ec) +#define PWM_CH11_TOP_BITS _u(0x0000ffff) +#define PWM_CH11_TOP_RESET _u(0x0000ffff) +#define PWM_CH11_TOP_MSB _u(15) +#define PWM_CH11_TOP_LSB _u(0) +#define PWM_CH11_TOP_ACCESS "RW" +// ============================================================================= +// Register : PWM_EN +// Description : This register aliases the CSR_EN bits for all channels. +// Writing to this register allows multiple channels to be enabled +// or disabled simultaneously, so they can run in perfect sync. +// For each channel, there is only one physical EN register bit, +// which can be accessed through here or CHx_CSR. +#define PWM_EN_OFFSET _u(0x000000f0) +#define PWM_EN_BITS _u(0x00000fff) +#define PWM_EN_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH11 +#define PWM_EN_CH11_RESET _u(0x0) +#define PWM_EN_CH11_BITS _u(0x00000800) +#define PWM_EN_CH11_MSB _u(11) +#define PWM_EN_CH11_LSB _u(11) +#define PWM_EN_CH11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH10 +#define PWM_EN_CH10_RESET _u(0x0) +#define PWM_EN_CH10_BITS _u(0x00000400) +#define PWM_EN_CH10_MSB _u(10) +#define PWM_EN_CH10_LSB _u(10) +#define PWM_EN_CH10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH9 +#define PWM_EN_CH9_RESET _u(0x0) +#define PWM_EN_CH9_BITS _u(0x00000200) +#define PWM_EN_CH9_MSB _u(9) +#define PWM_EN_CH9_LSB _u(9) +#define PWM_EN_CH9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH8 +#define PWM_EN_CH8_RESET _u(0x0) +#define PWM_EN_CH8_BITS _u(0x00000100) +#define PWM_EN_CH8_MSB _u(8) +#define PWM_EN_CH8_LSB _u(8) +#define PWM_EN_CH8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH7 +#define PWM_EN_CH7_RESET _u(0x0) +#define PWM_EN_CH7_BITS _u(0x00000080) +#define PWM_EN_CH7_MSB _u(7) +#define PWM_EN_CH7_LSB _u(7) +#define PWM_EN_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH6 +#define PWM_EN_CH6_RESET _u(0x0) +#define PWM_EN_CH6_BITS _u(0x00000040) +#define PWM_EN_CH6_MSB _u(6) +#define PWM_EN_CH6_LSB _u(6) +#define PWM_EN_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH5 +#define PWM_EN_CH5_RESET _u(0x0) +#define PWM_EN_CH5_BITS _u(0x00000020) +#define PWM_EN_CH5_MSB _u(5) +#define PWM_EN_CH5_LSB _u(5) +#define PWM_EN_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH4 +#define PWM_EN_CH4_RESET _u(0x0) +#define PWM_EN_CH4_BITS _u(0x00000010) +#define PWM_EN_CH4_MSB _u(4) +#define PWM_EN_CH4_LSB _u(4) +#define PWM_EN_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH3 +#define PWM_EN_CH3_RESET _u(0x0) +#define PWM_EN_CH3_BITS _u(0x00000008) +#define PWM_EN_CH3_MSB _u(3) +#define PWM_EN_CH3_LSB _u(3) +#define PWM_EN_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH2 +#define PWM_EN_CH2_RESET _u(0x0) +#define PWM_EN_CH2_BITS _u(0x00000004) +#define PWM_EN_CH2_MSB _u(2) +#define PWM_EN_CH2_LSB _u(2) +#define PWM_EN_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH1 +#define PWM_EN_CH1_RESET _u(0x0) +#define PWM_EN_CH1_BITS _u(0x00000002) +#define PWM_EN_CH1_MSB _u(1) +#define PWM_EN_CH1_LSB _u(1) +#define PWM_EN_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_EN_CH0 +#define PWM_EN_CH0_RESET _u(0x0) +#define PWM_EN_CH0_BITS _u(0x00000001) +#define PWM_EN_CH0_MSB _u(0) +#define PWM_EN_CH0_LSB _u(0) +#define PWM_EN_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_INTR +// Description : Raw Interrupts +#define PWM_INTR_OFFSET _u(0x000000f4) +#define PWM_INTR_BITS _u(0x00000fff) +#define PWM_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH11 +#define PWM_INTR_CH11_RESET _u(0x0) +#define PWM_INTR_CH11_BITS _u(0x00000800) +#define PWM_INTR_CH11_MSB _u(11) +#define PWM_INTR_CH11_LSB _u(11) +#define PWM_INTR_CH11_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH10 +#define PWM_INTR_CH10_RESET _u(0x0) +#define PWM_INTR_CH10_BITS _u(0x00000400) +#define PWM_INTR_CH10_MSB _u(10) +#define PWM_INTR_CH10_LSB _u(10) +#define PWM_INTR_CH10_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH9 +#define PWM_INTR_CH9_RESET _u(0x0) +#define PWM_INTR_CH9_BITS _u(0x00000200) +#define PWM_INTR_CH9_MSB _u(9) +#define PWM_INTR_CH9_LSB _u(9) +#define PWM_INTR_CH9_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH8 +#define PWM_INTR_CH8_RESET _u(0x0) +#define PWM_INTR_CH8_BITS _u(0x00000100) +#define PWM_INTR_CH8_MSB _u(8) +#define PWM_INTR_CH8_LSB _u(8) +#define PWM_INTR_CH8_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH7 +#define PWM_INTR_CH7_RESET _u(0x0) +#define PWM_INTR_CH7_BITS _u(0x00000080) +#define PWM_INTR_CH7_MSB _u(7) +#define PWM_INTR_CH7_LSB _u(7) +#define PWM_INTR_CH7_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH6 +#define PWM_INTR_CH6_RESET _u(0x0) +#define PWM_INTR_CH6_BITS _u(0x00000040) +#define PWM_INTR_CH6_MSB _u(6) +#define PWM_INTR_CH6_LSB _u(6) +#define PWM_INTR_CH6_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH5 +#define PWM_INTR_CH5_RESET _u(0x0) +#define PWM_INTR_CH5_BITS _u(0x00000020) +#define PWM_INTR_CH5_MSB _u(5) +#define PWM_INTR_CH5_LSB _u(5) +#define PWM_INTR_CH5_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH4 +#define PWM_INTR_CH4_RESET _u(0x0) +#define PWM_INTR_CH4_BITS _u(0x00000010) +#define PWM_INTR_CH4_MSB _u(4) +#define PWM_INTR_CH4_LSB _u(4) +#define PWM_INTR_CH4_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH3 +#define PWM_INTR_CH3_RESET _u(0x0) +#define PWM_INTR_CH3_BITS _u(0x00000008) +#define PWM_INTR_CH3_MSB _u(3) +#define PWM_INTR_CH3_LSB _u(3) +#define PWM_INTR_CH3_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH2 +#define PWM_INTR_CH2_RESET _u(0x0) +#define PWM_INTR_CH2_BITS _u(0x00000004) +#define PWM_INTR_CH2_MSB _u(2) +#define PWM_INTR_CH2_LSB _u(2) +#define PWM_INTR_CH2_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH1 +#define PWM_INTR_CH1_RESET _u(0x0) +#define PWM_INTR_CH1_BITS _u(0x00000002) +#define PWM_INTR_CH1_MSB _u(1) +#define PWM_INTR_CH1_LSB _u(1) +#define PWM_INTR_CH1_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : PWM_INTR_CH0 +#define PWM_INTR_CH0_RESET _u(0x0) +#define PWM_INTR_CH0_BITS _u(0x00000001) +#define PWM_INTR_CH0_MSB _u(0) +#define PWM_INTR_CH0_LSB _u(0) +#define PWM_INTR_CH0_ACCESS "WC" +// ============================================================================= +// Register : PWM_IRQ0_INTE +// Description : Interrupt Enable for irq0 +#define PWM_IRQ0_INTE_OFFSET _u(0x000000f8) +#define PWM_IRQ0_INTE_BITS _u(0x00000fff) +#define PWM_IRQ0_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH11 +#define PWM_IRQ0_INTE_CH11_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH11_BITS _u(0x00000800) +#define PWM_IRQ0_INTE_CH11_MSB _u(11) +#define PWM_IRQ0_INTE_CH11_LSB _u(11) +#define PWM_IRQ0_INTE_CH11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH10 +#define PWM_IRQ0_INTE_CH10_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH10_BITS _u(0x00000400) +#define PWM_IRQ0_INTE_CH10_MSB _u(10) +#define PWM_IRQ0_INTE_CH10_LSB _u(10) +#define PWM_IRQ0_INTE_CH10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH9 +#define PWM_IRQ0_INTE_CH9_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH9_BITS _u(0x00000200) +#define PWM_IRQ0_INTE_CH9_MSB _u(9) +#define PWM_IRQ0_INTE_CH9_LSB _u(9) +#define PWM_IRQ0_INTE_CH9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH8 +#define PWM_IRQ0_INTE_CH8_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH8_BITS _u(0x00000100) +#define PWM_IRQ0_INTE_CH8_MSB _u(8) +#define PWM_IRQ0_INTE_CH8_LSB _u(8) +#define PWM_IRQ0_INTE_CH8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH7 +#define PWM_IRQ0_INTE_CH7_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH7_BITS _u(0x00000080) +#define PWM_IRQ0_INTE_CH7_MSB _u(7) +#define PWM_IRQ0_INTE_CH7_LSB _u(7) +#define PWM_IRQ0_INTE_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH6 +#define PWM_IRQ0_INTE_CH6_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH6_BITS _u(0x00000040) +#define PWM_IRQ0_INTE_CH6_MSB _u(6) +#define PWM_IRQ0_INTE_CH6_LSB _u(6) +#define PWM_IRQ0_INTE_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH5 +#define PWM_IRQ0_INTE_CH5_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH5_BITS _u(0x00000020) +#define PWM_IRQ0_INTE_CH5_MSB _u(5) +#define PWM_IRQ0_INTE_CH5_LSB _u(5) +#define PWM_IRQ0_INTE_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH4 +#define PWM_IRQ0_INTE_CH4_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH4_BITS _u(0x00000010) +#define PWM_IRQ0_INTE_CH4_MSB _u(4) +#define PWM_IRQ0_INTE_CH4_LSB _u(4) +#define PWM_IRQ0_INTE_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH3 +#define PWM_IRQ0_INTE_CH3_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH3_BITS _u(0x00000008) +#define PWM_IRQ0_INTE_CH3_MSB _u(3) +#define PWM_IRQ0_INTE_CH3_LSB _u(3) +#define PWM_IRQ0_INTE_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH2 +#define PWM_IRQ0_INTE_CH2_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH2_BITS _u(0x00000004) +#define PWM_IRQ0_INTE_CH2_MSB _u(2) +#define PWM_IRQ0_INTE_CH2_LSB _u(2) +#define PWM_IRQ0_INTE_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH1 +#define PWM_IRQ0_INTE_CH1_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH1_BITS _u(0x00000002) +#define PWM_IRQ0_INTE_CH1_MSB _u(1) +#define PWM_IRQ0_INTE_CH1_LSB _u(1) +#define PWM_IRQ0_INTE_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTE_CH0 +#define PWM_IRQ0_INTE_CH0_RESET _u(0x0) +#define PWM_IRQ0_INTE_CH0_BITS _u(0x00000001) +#define PWM_IRQ0_INTE_CH0_MSB _u(0) +#define PWM_IRQ0_INTE_CH0_LSB _u(0) +#define PWM_IRQ0_INTE_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_IRQ0_INTF +// Description : Interrupt Force for irq0 +#define PWM_IRQ0_INTF_OFFSET _u(0x000000fc) +#define PWM_IRQ0_INTF_BITS _u(0x00000fff) +#define PWM_IRQ0_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH11 +#define PWM_IRQ0_INTF_CH11_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH11_BITS _u(0x00000800) +#define PWM_IRQ0_INTF_CH11_MSB _u(11) +#define PWM_IRQ0_INTF_CH11_LSB _u(11) +#define PWM_IRQ0_INTF_CH11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH10 +#define PWM_IRQ0_INTF_CH10_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH10_BITS _u(0x00000400) +#define PWM_IRQ0_INTF_CH10_MSB _u(10) +#define PWM_IRQ0_INTF_CH10_LSB _u(10) +#define PWM_IRQ0_INTF_CH10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH9 +#define PWM_IRQ0_INTF_CH9_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH9_BITS _u(0x00000200) +#define PWM_IRQ0_INTF_CH9_MSB _u(9) +#define PWM_IRQ0_INTF_CH9_LSB _u(9) +#define PWM_IRQ0_INTF_CH9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH8 +#define PWM_IRQ0_INTF_CH8_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH8_BITS _u(0x00000100) +#define PWM_IRQ0_INTF_CH8_MSB _u(8) +#define PWM_IRQ0_INTF_CH8_LSB _u(8) +#define PWM_IRQ0_INTF_CH8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH7 +#define PWM_IRQ0_INTF_CH7_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH7_BITS _u(0x00000080) +#define PWM_IRQ0_INTF_CH7_MSB _u(7) +#define PWM_IRQ0_INTF_CH7_LSB _u(7) +#define PWM_IRQ0_INTF_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH6 +#define PWM_IRQ0_INTF_CH6_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH6_BITS _u(0x00000040) +#define PWM_IRQ0_INTF_CH6_MSB _u(6) +#define PWM_IRQ0_INTF_CH6_LSB _u(6) +#define PWM_IRQ0_INTF_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH5 +#define PWM_IRQ0_INTF_CH5_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH5_BITS _u(0x00000020) +#define PWM_IRQ0_INTF_CH5_MSB _u(5) +#define PWM_IRQ0_INTF_CH5_LSB _u(5) +#define PWM_IRQ0_INTF_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH4 +#define PWM_IRQ0_INTF_CH4_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH4_BITS _u(0x00000010) +#define PWM_IRQ0_INTF_CH4_MSB _u(4) +#define PWM_IRQ0_INTF_CH4_LSB _u(4) +#define PWM_IRQ0_INTF_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH3 +#define PWM_IRQ0_INTF_CH3_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH3_BITS _u(0x00000008) +#define PWM_IRQ0_INTF_CH3_MSB _u(3) +#define PWM_IRQ0_INTF_CH3_LSB _u(3) +#define PWM_IRQ0_INTF_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH2 +#define PWM_IRQ0_INTF_CH2_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH2_BITS _u(0x00000004) +#define PWM_IRQ0_INTF_CH2_MSB _u(2) +#define PWM_IRQ0_INTF_CH2_LSB _u(2) +#define PWM_IRQ0_INTF_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH1 +#define PWM_IRQ0_INTF_CH1_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH1_BITS _u(0x00000002) +#define PWM_IRQ0_INTF_CH1_MSB _u(1) +#define PWM_IRQ0_INTF_CH1_LSB _u(1) +#define PWM_IRQ0_INTF_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTF_CH0 +#define PWM_IRQ0_INTF_CH0_RESET _u(0x0) +#define PWM_IRQ0_INTF_CH0_BITS _u(0x00000001) +#define PWM_IRQ0_INTF_CH0_MSB _u(0) +#define PWM_IRQ0_INTF_CH0_LSB _u(0) +#define PWM_IRQ0_INTF_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_IRQ0_INTS +// Description : Interrupt status after masking & forcing for irq0 +#define PWM_IRQ0_INTS_OFFSET _u(0x00000100) +#define PWM_IRQ0_INTS_BITS _u(0x00000fff) +#define PWM_IRQ0_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH11 +#define PWM_IRQ0_INTS_CH11_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH11_BITS _u(0x00000800) +#define PWM_IRQ0_INTS_CH11_MSB _u(11) +#define PWM_IRQ0_INTS_CH11_LSB _u(11) +#define PWM_IRQ0_INTS_CH11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH10 +#define PWM_IRQ0_INTS_CH10_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH10_BITS _u(0x00000400) +#define PWM_IRQ0_INTS_CH10_MSB _u(10) +#define PWM_IRQ0_INTS_CH10_LSB _u(10) +#define PWM_IRQ0_INTS_CH10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH9 +#define PWM_IRQ0_INTS_CH9_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH9_BITS _u(0x00000200) +#define PWM_IRQ0_INTS_CH9_MSB _u(9) +#define PWM_IRQ0_INTS_CH9_LSB _u(9) +#define PWM_IRQ0_INTS_CH9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH8 +#define PWM_IRQ0_INTS_CH8_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH8_BITS _u(0x00000100) +#define PWM_IRQ0_INTS_CH8_MSB _u(8) +#define PWM_IRQ0_INTS_CH8_LSB _u(8) +#define PWM_IRQ0_INTS_CH8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH7 +#define PWM_IRQ0_INTS_CH7_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH7_BITS _u(0x00000080) +#define PWM_IRQ0_INTS_CH7_MSB _u(7) +#define PWM_IRQ0_INTS_CH7_LSB _u(7) +#define PWM_IRQ0_INTS_CH7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH6 +#define PWM_IRQ0_INTS_CH6_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH6_BITS _u(0x00000040) +#define PWM_IRQ0_INTS_CH6_MSB _u(6) +#define PWM_IRQ0_INTS_CH6_LSB _u(6) +#define PWM_IRQ0_INTS_CH6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH5 +#define PWM_IRQ0_INTS_CH5_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH5_BITS _u(0x00000020) +#define PWM_IRQ0_INTS_CH5_MSB _u(5) +#define PWM_IRQ0_INTS_CH5_LSB _u(5) +#define PWM_IRQ0_INTS_CH5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH4 +#define PWM_IRQ0_INTS_CH4_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH4_BITS _u(0x00000010) +#define PWM_IRQ0_INTS_CH4_MSB _u(4) +#define PWM_IRQ0_INTS_CH4_LSB _u(4) +#define PWM_IRQ0_INTS_CH4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH3 +#define PWM_IRQ0_INTS_CH3_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH3_BITS _u(0x00000008) +#define PWM_IRQ0_INTS_CH3_MSB _u(3) +#define PWM_IRQ0_INTS_CH3_LSB _u(3) +#define PWM_IRQ0_INTS_CH3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH2 +#define PWM_IRQ0_INTS_CH2_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH2_BITS _u(0x00000004) +#define PWM_IRQ0_INTS_CH2_MSB _u(2) +#define PWM_IRQ0_INTS_CH2_LSB _u(2) +#define PWM_IRQ0_INTS_CH2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH1 +#define PWM_IRQ0_INTS_CH1_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH1_BITS _u(0x00000002) +#define PWM_IRQ0_INTS_CH1_MSB _u(1) +#define PWM_IRQ0_INTS_CH1_LSB _u(1) +#define PWM_IRQ0_INTS_CH1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ0_INTS_CH0 +#define PWM_IRQ0_INTS_CH0_RESET _u(0x0) +#define PWM_IRQ0_INTS_CH0_BITS _u(0x00000001) +#define PWM_IRQ0_INTS_CH0_MSB _u(0) +#define PWM_IRQ0_INTS_CH0_LSB _u(0) +#define PWM_IRQ0_INTS_CH0_ACCESS "RO" +// ============================================================================= +// Register : PWM_IRQ1_INTE +// Description : Interrupt Enable for irq1 +#define PWM_IRQ1_INTE_OFFSET _u(0x00000104) +#define PWM_IRQ1_INTE_BITS _u(0x00000fff) +#define PWM_IRQ1_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH11 +#define PWM_IRQ1_INTE_CH11_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH11_BITS _u(0x00000800) +#define PWM_IRQ1_INTE_CH11_MSB _u(11) +#define PWM_IRQ1_INTE_CH11_LSB _u(11) +#define PWM_IRQ1_INTE_CH11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH10 +#define PWM_IRQ1_INTE_CH10_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH10_BITS _u(0x00000400) +#define PWM_IRQ1_INTE_CH10_MSB _u(10) +#define PWM_IRQ1_INTE_CH10_LSB _u(10) +#define PWM_IRQ1_INTE_CH10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH9 +#define PWM_IRQ1_INTE_CH9_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH9_BITS _u(0x00000200) +#define PWM_IRQ1_INTE_CH9_MSB _u(9) +#define PWM_IRQ1_INTE_CH9_LSB _u(9) +#define PWM_IRQ1_INTE_CH9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH8 +#define PWM_IRQ1_INTE_CH8_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH8_BITS _u(0x00000100) +#define PWM_IRQ1_INTE_CH8_MSB _u(8) +#define PWM_IRQ1_INTE_CH8_LSB _u(8) +#define PWM_IRQ1_INTE_CH8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH7 +#define PWM_IRQ1_INTE_CH7_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH7_BITS _u(0x00000080) +#define PWM_IRQ1_INTE_CH7_MSB _u(7) +#define PWM_IRQ1_INTE_CH7_LSB _u(7) +#define PWM_IRQ1_INTE_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH6 +#define PWM_IRQ1_INTE_CH6_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH6_BITS _u(0x00000040) +#define PWM_IRQ1_INTE_CH6_MSB _u(6) +#define PWM_IRQ1_INTE_CH6_LSB _u(6) +#define PWM_IRQ1_INTE_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH5 +#define PWM_IRQ1_INTE_CH5_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH5_BITS _u(0x00000020) +#define PWM_IRQ1_INTE_CH5_MSB _u(5) +#define PWM_IRQ1_INTE_CH5_LSB _u(5) +#define PWM_IRQ1_INTE_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH4 +#define PWM_IRQ1_INTE_CH4_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH4_BITS _u(0x00000010) +#define PWM_IRQ1_INTE_CH4_MSB _u(4) +#define PWM_IRQ1_INTE_CH4_LSB _u(4) +#define PWM_IRQ1_INTE_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH3 +#define PWM_IRQ1_INTE_CH3_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH3_BITS _u(0x00000008) +#define PWM_IRQ1_INTE_CH3_MSB _u(3) +#define PWM_IRQ1_INTE_CH3_LSB _u(3) +#define PWM_IRQ1_INTE_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH2 +#define PWM_IRQ1_INTE_CH2_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH2_BITS _u(0x00000004) +#define PWM_IRQ1_INTE_CH2_MSB _u(2) +#define PWM_IRQ1_INTE_CH2_LSB _u(2) +#define PWM_IRQ1_INTE_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH1 +#define PWM_IRQ1_INTE_CH1_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH1_BITS _u(0x00000002) +#define PWM_IRQ1_INTE_CH1_MSB _u(1) +#define PWM_IRQ1_INTE_CH1_LSB _u(1) +#define PWM_IRQ1_INTE_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTE_CH0 +#define PWM_IRQ1_INTE_CH0_RESET _u(0x0) +#define PWM_IRQ1_INTE_CH0_BITS _u(0x00000001) +#define PWM_IRQ1_INTE_CH0_MSB _u(0) +#define PWM_IRQ1_INTE_CH0_LSB _u(0) +#define PWM_IRQ1_INTE_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_IRQ1_INTF +// Description : Interrupt Force for irq1 +#define PWM_IRQ1_INTF_OFFSET _u(0x00000108) +#define PWM_IRQ1_INTF_BITS _u(0x00000fff) +#define PWM_IRQ1_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH11 +#define PWM_IRQ1_INTF_CH11_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH11_BITS _u(0x00000800) +#define PWM_IRQ1_INTF_CH11_MSB _u(11) +#define PWM_IRQ1_INTF_CH11_LSB _u(11) +#define PWM_IRQ1_INTF_CH11_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH10 +#define PWM_IRQ1_INTF_CH10_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH10_BITS _u(0x00000400) +#define PWM_IRQ1_INTF_CH10_MSB _u(10) +#define PWM_IRQ1_INTF_CH10_LSB _u(10) +#define PWM_IRQ1_INTF_CH10_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH9 +#define PWM_IRQ1_INTF_CH9_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH9_BITS _u(0x00000200) +#define PWM_IRQ1_INTF_CH9_MSB _u(9) +#define PWM_IRQ1_INTF_CH9_LSB _u(9) +#define PWM_IRQ1_INTF_CH9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH8 +#define PWM_IRQ1_INTF_CH8_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH8_BITS _u(0x00000100) +#define PWM_IRQ1_INTF_CH8_MSB _u(8) +#define PWM_IRQ1_INTF_CH8_LSB _u(8) +#define PWM_IRQ1_INTF_CH8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH7 +#define PWM_IRQ1_INTF_CH7_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH7_BITS _u(0x00000080) +#define PWM_IRQ1_INTF_CH7_MSB _u(7) +#define PWM_IRQ1_INTF_CH7_LSB _u(7) +#define PWM_IRQ1_INTF_CH7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH6 +#define PWM_IRQ1_INTF_CH6_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH6_BITS _u(0x00000040) +#define PWM_IRQ1_INTF_CH6_MSB _u(6) +#define PWM_IRQ1_INTF_CH6_LSB _u(6) +#define PWM_IRQ1_INTF_CH6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH5 +#define PWM_IRQ1_INTF_CH5_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH5_BITS _u(0x00000020) +#define PWM_IRQ1_INTF_CH5_MSB _u(5) +#define PWM_IRQ1_INTF_CH5_LSB _u(5) +#define PWM_IRQ1_INTF_CH5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH4 +#define PWM_IRQ1_INTF_CH4_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH4_BITS _u(0x00000010) +#define PWM_IRQ1_INTF_CH4_MSB _u(4) +#define PWM_IRQ1_INTF_CH4_LSB _u(4) +#define PWM_IRQ1_INTF_CH4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH3 +#define PWM_IRQ1_INTF_CH3_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH3_BITS _u(0x00000008) +#define PWM_IRQ1_INTF_CH3_MSB _u(3) +#define PWM_IRQ1_INTF_CH3_LSB _u(3) +#define PWM_IRQ1_INTF_CH3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH2 +#define PWM_IRQ1_INTF_CH2_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH2_BITS _u(0x00000004) +#define PWM_IRQ1_INTF_CH2_MSB _u(2) +#define PWM_IRQ1_INTF_CH2_LSB _u(2) +#define PWM_IRQ1_INTF_CH2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH1 +#define PWM_IRQ1_INTF_CH1_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH1_BITS _u(0x00000002) +#define PWM_IRQ1_INTF_CH1_MSB _u(1) +#define PWM_IRQ1_INTF_CH1_LSB _u(1) +#define PWM_IRQ1_INTF_CH1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTF_CH0 +#define PWM_IRQ1_INTF_CH0_RESET _u(0x0) +#define PWM_IRQ1_INTF_CH0_BITS _u(0x00000001) +#define PWM_IRQ1_INTF_CH0_MSB _u(0) +#define PWM_IRQ1_INTF_CH0_LSB _u(0) +#define PWM_IRQ1_INTF_CH0_ACCESS "RW" +// ============================================================================= +// Register : PWM_IRQ1_INTS +// Description : Interrupt status after masking & forcing for irq1 +#define PWM_IRQ1_INTS_OFFSET _u(0x0000010c) +#define PWM_IRQ1_INTS_BITS _u(0x00000fff) +#define PWM_IRQ1_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH11 +#define PWM_IRQ1_INTS_CH11_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH11_BITS _u(0x00000800) +#define PWM_IRQ1_INTS_CH11_MSB _u(11) +#define PWM_IRQ1_INTS_CH11_LSB _u(11) +#define PWM_IRQ1_INTS_CH11_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH10 +#define PWM_IRQ1_INTS_CH10_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH10_BITS _u(0x00000400) +#define PWM_IRQ1_INTS_CH10_MSB _u(10) +#define PWM_IRQ1_INTS_CH10_LSB _u(10) +#define PWM_IRQ1_INTS_CH10_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH9 +#define PWM_IRQ1_INTS_CH9_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH9_BITS _u(0x00000200) +#define PWM_IRQ1_INTS_CH9_MSB _u(9) +#define PWM_IRQ1_INTS_CH9_LSB _u(9) +#define PWM_IRQ1_INTS_CH9_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH8 +#define PWM_IRQ1_INTS_CH8_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH8_BITS _u(0x00000100) +#define PWM_IRQ1_INTS_CH8_MSB _u(8) +#define PWM_IRQ1_INTS_CH8_LSB _u(8) +#define PWM_IRQ1_INTS_CH8_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH7 +#define PWM_IRQ1_INTS_CH7_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH7_BITS _u(0x00000080) +#define PWM_IRQ1_INTS_CH7_MSB _u(7) +#define PWM_IRQ1_INTS_CH7_LSB _u(7) +#define PWM_IRQ1_INTS_CH7_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH6 +#define PWM_IRQ1_INTS_CH6_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH6_BITS _u(0x00000040) +#define PWM_IRQ1_INTS_CH6_MSB _u(6) +#define PWM_IRQ1_INTS_CH6_LSB _u(6) +#define PWM_IRQ1_INTS_CH6_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH5 +#define PWM_IRQ1_INTS_CH5_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH5_BITS _u(0x00000020) +#define PWM_IRQ1_INTS_CH5_MSB _u(5) +#define PWM_IRQ1_INTS_CH5_LSB _u(5) +#define PWM_IRQ1_INTS_CH5_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH4 +#define PWM_IRQ1_INTS_CH4_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH4_BITS _u(0x00000010) +#define PWM_IRQ1_INTS_CH4_MSB _u(4) +#define PWM_IRQ1_INTS_CH4_LSB _u(4) +#define PWM_IRQ1_INTS_CH4_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH3 +#define PWM_IRQ1_INTS_CH3_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH3_BITS _u(0x00000008) +#define PWM_IRQ1_INTS_CH3_MSB _u(3) +#define PWM_IRQ1_INTS_CH3_LSB _u(3) +#define PWM_IRQ1_INTS_CH3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH2 +#define PWM_IRQ1_INTS_CH2_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH2_BITS _u(0x00000004) +#define PWM_IRQ1_INTS_CH2_MSB _u(2) +#define PWM_IRQ1_INTS_CH2_LSB _u(2) +#define PWM_IRQ1_INTS_CH2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH1 +#define PWM_IRQ1_INTS_CH1_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH1_BITS _u(0x00000002) +#define PWM_IRQ1_INTS_CH1_MSB _u(1) +#define PWM_IRQ1_INTS_CH1_LSB _u(1) +#define PWM_IRQ1_INTS_CH1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : PWM_IRQ1_INTS_CH0 +#define PWM_IRQ1_INTS_CH0_RESET _u(0x0) +#define PWM_IRQ1_INTS_CH0_BITS _u(0x00000001) +#define PWM_IRQ1_INTS_CH0_MSB _u(0) +#define PWM_IRQ1_INTS_CH0_LSB _u(0) +#define PWM_IRQ1_INTS_CH0_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_PWM_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/qmi.h b/lib/pico-sdk/rp2350/hardware/regs/qmi.h new file mode 100644 index 000000000000..3efebc13f3ab --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/qmi.h @@ -0,0 +1,1781 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : QMI +// Version : 1 +// Bus type : apb +// Description : QSPI Memory Interface. +// +// Provides a memory-mapped interface to up to two +// SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial +// interface for programming and configuration of the external +// device. +// ============================================================================= +#ifndef _HARDWARE_REGS_QMI_H +#define _HARDWARE_REGS_QMI_H +// ============================================================================= +// Register : QMI_DIRECT_CSR +// Description : Control and status for direct serial mode +// +// Direct serial mode allows the processor to send and receive raw +// serial frames, for programming, configuration and control of +// the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is +// supported. +#define QMI_DIRECT_CSR_OFFSET _u(0x00000000) +#define QMI_DIRECT_CSR_BITS _u(0xffdf7ccf) +#define QMI_DIRECT_CSR_RESET _u(0x01800000) +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_RXDELAY +// Description : Delay the read data sample timing, in units of one half of a +// system clock cycle. (Not necessarily half of an SCK cycle.) +#define QMI_DIRECT_CSR_RXDELAY_RESET _u(0x0) +#define QMI_DIRECT_CSR_RXDELAY_BITS _u(0xc0000000) +#define QMI_DIRECT_CSR_RXDELAY_MSB _u(31) +#define QMI_DIRECT_CSR_RXDELAY_LSB _u(30) +#define QMI_DIRECT_CSR_RXDELAY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_CLKDIV +// Description : Clock divisor for direct serial mode. Divisors of 1..255 are +// encoded directly, and the maximum divisor of 256 is encoded by +// a value of CLKDIV=0. +// +// The clock divisor can be changed on-the-fly by software, +// without halting or otherwise coordinating with the serial +// interface. The serial interface will sample the latest clock +// divisor each time it begins the transmission of a new byte. +#define QMI_DIRECT_CSR_CLKDIV_RESET _u(0x06) +#define QMI_DIRECT_CSR_CLKDIV_BITS _u(0x3fc00000) +#define QMI_DIRECT_CSR_CLKDIV_MSB _u(29) +#define QMI_DIRECT_CSR_CLKDIV_LSB _u(22) +#define QMI_DIRECT_CSR_CLKDIV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_RXLEVEL +// Description : Current level of DIRECT_RX FIFO +#define QMI_DIRECT_CSR_RXLEVEL_RESET _u(0x0) +#define QMI_DIRECT_CSR_RXLEVEL_BITS _u(0x001c0000) +#define QMI_DIRECT_CSR_RXLEVEL_MSB _u(20) +#define QMI_DIRECT_CSR_RXLEVEL_LSB _u(18) +#define QMI_DIRECT_CSR_RXLEVEL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_RXFULL +// Description : When 1, the DIRECT_RX FIFO is currently full. The serial +// interface will be stalled until data is popped; the interface +// will not begin a new serial frame when the DIRECT_TX FIFO is +// empty or the DIRECT_RX FIFO is full. +#define QMI_DIRECT_CSR_RXFULL_RESET _u(0x0) +#define QMI_DIRECT_CSR_RXFULL_BITS _u(0x00020000) +#define QMI_DIRECT_CSR_RXFULL_MSB _u(17) +#define QMI_DIRECT_CSR_RXFULL_LSB _u(17) +#define QMI_DIRECT_CSR_RXFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_RXEMPTY +// Description : When 1, the DIRECT_RX FIFO is currently empty. If the processor +// attempts to read more data, the FIFO state is not affected, but +// the value returned to the processor is undefined. +#define QMI_DIRECT_CSR_RXEMPTY_RESET _u(0x0) +#define QMI_DIRECT_CSR_RXEMPTY_BITS _u(0x00010000) +#define QMI_DIRECT_CSR_RXEMPTY_MSB _u(16) +#define QMI_DIRECT_CSR_RXEMPTY_LSB _u(16) +#define QMI_DIRECT_CSR_RXEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_TXLEVEL +// Description : Current level of DIRECT_TX FIFO +#define QMI_DIRECT_CSR_TXLEVEL_RESET _u(0x0) +#define QMI_DIRECT_CSR_TXLEVEL_BITS _u(0x00007000) +#define QMI_DIRECT_CSR_TXLEVEL_MSB _u(14) +#define QMI_DIRECT_CSR_TXLEVEL_LSB _u(12) +#define QMI_DIRECT_CSR_TXLEVEL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_TXEMPTY +// Description : When 1, the DIRECT_TX FIFO is currently empty. Unless the +// processor pushes more data, transmission will stop and BUSY +// will go low once the current 8-bit serial frame completes. +#define QMI_DIRECT_CSR_TXEMPTY_RESET _u(0x0) +#define QMI_DIRECT_CSR_TXEMPTY_BITS _u(0x00000800) +#define QMI_DIRECT_CSR_TXEMPTY_MSB _u(11) +#define QMI_DIRECT_CSR_TXEMPTY_LSB _u(11) +#define QMI_DIRECT_CSR_TXEMPTY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_TXFULL +// Description : When 1, the DIRECT_TX FIFO is currently full. If the processor +// tries to write more data, that data will be ignored. +#define QMI_DIRECT_CSR_TXFULL_RESET _u(0x0) +#define QMI_DIRECT_CSR_TXFULL_BITS _u(0x00000400) +#define QMI_DIRECT_CSR_TXFULL_MSB _u(10) +#define QMI_DIRECT_CSR_TXFULL_LSB _u(10) +#define QMI_DIRECT_CSR_TXFULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_AUTO_CS1N +// Description : When 1, automatically assert the CS1n chip select line whenever +// the BUSY flag is set. +#define QMI_DIRECT_CSR_AUTO_CS1N_RESET _u(0x0) +#define QMI_DIRECT_CSR_AUTO_CS1N_BITS _u(0x00000080) +#define QMI_DIRECT_CSR_AUTO_CS1N_MSB _u(7) +#define QMI_DIRECT_CSR_AUTO_CS1N_LSB _u(7) +#define QMI_DIRECT_CSR_AUTO_CS1N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_AUTO_CS0N +// Description : When 1, automatically assert the CS0n chip select line whenever +// the BUSY flag is set. +#define QMI_DIRECT_CSR_AUTO_CS0N_RESET _u(0x0) +#define QMI_DIRECT_CSR_AUTO_CS0N_BITS _u(0x00000040) +#define QMI_DIRECT_CSR_AUTO_CS0N_MSB _u(6) +#define QMI_DIRECT_CSR_AUTO_CS0N_LSB _u(6) +#define QMI_DIRECT_CSR_AUTO_CS0N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_ASSERT_CS1N +// Description : When 1, assert (i.e. drive low) the CS1n chip select line. +// +// Note that this applies even when DIRECT_CSR_EN is 0. +#define QMI_DIRECT_CSR_ASSERT_CS1N_RESET _u(0x0) +#define QMI_DIRECT_CSR_ASSERT_CS1N_BITS _u(0x00000008) +#define QMI_DIRECT_CSR_ASSERT_CS1N_MSB _u(3) +#define QMI_DIRECT_CSR_ASSERT_CS1N_LSB _u(3) +#define QMI_DIRECT_CSR_ASSERT_CS1N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_ASSERT_CS0N +// Description : When 1, assert (i.e. drive low) the CS0n chip select line. +// +// Note that this applies even when DIRECT_CSR_EN is 0. +#define QMI_DIRECT_CSR_ASSERT_CS0N_RESET _u(0x0) +#define QMI_DIRECT_CSR_ASSERT_CS0N_BITS _u(0x00000004) +#define QMI_DIRECT_CSR_ASSERT_CS0N_MSB _u(2) +#define QMI_DIRECT_CSR_ASSERT_CS0N_LSB _u(2) +#define QMI_DIRECT_CSR_ASSERT_CS0N_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_BUSY +// Description : Direct mode busy flag. If 1, data is currently being shifted +// in/out (or would be if the interface were not stalled on the RX +// FIFO), and the chip select must not yet be deasserted. +// +// The busy flag will also be set to 1 if a memory-mapped transfer +// is still in progress when direct mode is enabled. Direct mode +// blocks new memory-mapped transfers, but can't halt a transfer +// that is already in progress. If there is a chance that memory- +// mapped transfers may be in progress, the busy flag should be +// polled for 0 before asserting the chip select. +// +// (In practice you will usually discover this timing condition +// through other means, because any subsequent memory-mapped +// transfers when direct mode is enabled will return bus errors, +// which are difficult to ignore.) +#define QMI_DIRECT_CSR_BUSY_RESET _u(0x0) +#define QMI_DIRECT_CSR_BUSY_BITS _u(0x00000002) +#define QMI_DIRECT_CSR_BUSY_MSB _u(1) +#define QMI_DIRECT_CSR_BUSY_LSB _u(1) +#define QMI_DIRECT_CSR_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_CSR_EN +// Description : Enable direct mode. +// +// In direct mode, software controls the chip select lines, and +// can perform direct SPI transfers by pushing data to the +// DIRECT_TX FIFO, and popping the same amount of data from the +// DIRECT_RX FIFO. +// +// Memory-mapped accesses will generate bus errors when direct +// serial mode is enabled. +#define QMI_DIRECT_CSR_EN_RESET _u(0x0) +#define QMI_DIRECT_CSR_EN_BITS _u(0x00000001) +#define QMI_DIRECT_CSR_EN_MSB _u(0) +#define QMI_DIRECT_CSR_EN_LSB _u(0) +#define QMI_DIRECT_CSR_EN_ACCESS "RW" +// ============================================================================= +// Register : QMI_DIRECT_TX +// Description : Transmit FIFO for direct mode +#define QMI_DIRECT_TX_OFFSET _u(0x00000004) +#define QMI_DIRECT_TX_BITS _u(0x001fffff) +#define QMI_DIRECT_TX_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_TX_NOPUSH +// Description : Inhibit the RX FIFO push that would correspond to this TX FIFO +// entry. +// +// Useful to avoid garbage appearing in the RX FIFO when pushing +// the command at the beginning of a SPI transfer. +#define QMI_DIRECT_TX_NOPUSH_RESET _u(0x0) +#define QMI_DIRECT_TX_NOPUSH_BITS _u(0x00100000) +#define QMI_DIRECT_TX_NOPUSH_MSB _u(20) +#define QMI_DIRECT_TX_NOPUSH_LSB _u(20) +#define QMI_DIRECT_TX_NOPUSH_ACCESS "WF" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_TX_OE +// Description : Output enable (active-high). For single width (SPI), this field +// is ignored, and SD0 is always set to output, with SD1 always +// set to input. +// +// For dual and quad width (DSPI/QSPI), this sets whether the +// relevant SDx pads are set to output whilst transferring this +// FIFO record. In this case the command/address should have OE +// set, and the data transfer should have OE set or clear +// depending on the direction of the transfer. +#define QMI_DIRECT_TX_OE_RESET _u(0x0) +#define QMI_DIRECT_TX_OE_BITS _u(0x00080000) +#define QMI_DIRECT_TX_OE_MSB _u(19) +#define QMI_DIRECT_TX_OE_LSB _u(19) +#define QMI_DIRECT_TX_OE_ACCESS "WF" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_TX_DWIDTH +// Description : Data width. If 0, hardware will transmit the 8 LSBs of the +// DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs +// of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and +// 16-bit transfers can be mixed freely. +#define QMI_DIRECT_TX_DWIDTH_RESET _u(0x0) +#define QMI_DIRECT_TX_DWIDTH_BITS _u(0x00040000) +#define QMI_DIRECT_TX_DWIDTH_MSB _u(18) +#define QMI_DIRECT_TX_DWIDTH_LSB _u(18) +#define QMI_DIRECT_TX_DWIDTH_ACCESS "WF" +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_TX_IWIDTH +// Description : Configure whether this FIFO record is transferred with +// single/dual/quad interface width (0/1/2). Different widths can +// be mixed freely. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_DIRECT_TX_IWIDTH_RESET _u(0x0) +#define QMI_DIRECT_TX_IWIDTH_BITS _u(0x00030000) +#define QMI_DIRECT_TX_IWIDTH_MSB _u(17) +#define QMI_DIRECT_TX_IWIDTH_LSB _u(16) +#define QMI_DIRECT_TX_IWIDTH_ACCESS "WF" +#define QMI_DIRECT_TX_IWIDTH_VALUE_S _u(0x0) +#define QMI_DIRECT_TX_IWIDTH_VALUE_D _u(0x1) +#define QMI_DIRECT_TX_IWIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_DIRECT_TX_DATA +// Description : Data pushed here will be clocked out falling edges of SCK (or +// before the very first rising edge of SCK, if this is the first +// pulse). For each byte clocked out, the interface will +// simultaneously sample one byte, on rising edges of SCK, and +// push this to the DIRECT_RX FIFO. +// +// For 16-bit data, the least-significant byte is transmitted +// first. +#define QMI_DIRECT_TX_DATA_RESET _u(0x0000) +#define QMI_DIRECT_TX_DATA_BITS _u(0x0000ffff) +#define QMI_DIRECT_TX_DATA_MSB _u(15) +#define QMI_DIRECT_TX_DATA_LSB _u(0) +#define QMI_DIRECT_TX_DATA_ACCESS "WF" +// ============================================================================= +// Register : QMI_DIRECT_RX +// Description : Receive FIFO for direct mode +// With each byte clocked out on the serial interface, one byte +// will simultaneously be clocked in, and will appear in this +// FIFO. The serial interface will stall when this FIFO is full, +// to avoid dropping data. +// +// When 16-bit data is pushed into the TX FIFO, the corresponding +// RX FIFO push will also contain 16 bits of data. The least- +// significant byte is the first one received. +#define QMI_DIRECT_RX_OFFSET _u(0x00000008) +#define QMI_DIRECT_RX_BITS _u(0x0000ffff) +#define QMI_DIRECT_RX_RESET _u(0x00000000) +#define QMI_DIRECT_RX_MSB _u(15) +#define QMI_DIRECT_RX_LSB _u(0) +#define QMI_DIRECT_RX_ACCESS "RF" +// ============================================================================= +// Register : QMI_M0_TIMING +// Description : Timing configuration register for memory address window 0. +#define QMI_M0_TIMING_OFFSET _u(0x0000000c) +#define QMI_M0_TIMING_BITS _u(0xf3fff7ff) +#define QMI_M0_TIMING_RESET _u(0x40000004) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_COOLDOWN +// Description : Chip select cooldown period. When a memory transfer finishes, +// the chip select remains asserted for 64 x COOLDOWN system clock +// cycles, plus half an SCK clock period (rounded up for odd SCK +// divisors). After this cooldown expires, the chip select is +// always deasserted to save power. +// +// If the next memory access arrives within the cooldown period, +// the QMI may be able to append more SCK cycles to the currently +// ongoing SPI transfer, rather than starting a new transfer. This +// reduces access latency and increases bus throughput. +// +// Specifically, the next access must be in the same direction +// (read/write), access the same memory window (chip select 0/1), +// and follow sequentially the address of the last transfer. If +// any of these are false, the new access will first deassert the +// chip select, then begin a new transfer. +// +// If COOLDOWN is 0, the address alignment configured by PAGEBREAK +// has been reached, or the total chip select assertion limit +// MAX_SELECT has been reached, the cooldown period is skipped, +// and the chip select will always be deasserted one half SCK +// period after the transfer finishes. +#define QMI_M0_TIMING_COOLDOWN_RESET _u(0x1) +#define QMI_M0_TIMING_COOLDOWN_BITS _u(0xc0000000) +#define QMI_M0_TIMING_COOLDOWN_MSB _u(31) +#define QMI_M0_TIMING_COOLDOWN_LSB _u(30) +#define QMI_M0_TIMING_COOLDOWN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_PAGEBREAK +// Description : When page break is enabled, chip select will automatically +// deassert when crossing certain power-of-2-aligned address +// boundaries. The next access will always begin a new read/write +// SPI burst, even if the address of the next access follows in +// sequence with the last access before the page boundary. +// +// Some flash and PSRAM devices forbid crossing page boundaries +// with a single read/write transfer, or restrict the operating +// frequency for transfers that do cross page a boundary. This +// option allows the QMI to safely support those devices. +// +// This field has no effect when COOLDOWN is disabled. +// 0x0 -> No page boundary is enforced +// 0x1 -> Break bursts crossing a 256-byte page boundary +// 0x2 -> Break bursts crossing a 1024-byte quad-page boundary +// 0x3 -> Break bursts crossing a 4096-byte sector boundary +#define QMI_M0_TIMING_PAGEBREAK_RESET _u(0x0) +#define QMI_M0_TIMING_PAGEBREAK_BITS _u(0x30000000) +#define QMI_M0_TIMING_PAGEBREAK_MSB _u(29) +#define QMI_M0_TIMING_PAGEBREAK_LSB _u(28) +#define QMI_M0_TIMING_PAGEBREAK_ACCESS "RW" +#define QMI_M0_TIMING_PAGEBREAK_VALUE_NONE _u(0x0) +#define QMI_M0_TIMING_PAGEBREAK_VALUE_256 _u(0x1) +#define QMI_M0_TIMING_PAGEBREAK_VALUE_1024 _u(0x2) +#define QMI_M0_TIMING_PAGEBREAK_VALUE_4096 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_SELECT_SETUP +// Description : Add up to one additional system clock cycle of setup between +// chip select assertion and the first rising edge of SCK. +// +// The default setup time is one half SCK period, which is usually +// sufficient except for very high SCK frequencies with some flash +// devices. +#define QMI_M0_TIMING_SELECT_SETUP_RESET _u(0x0) +#define QMI_M0_TIMING_SELECT_SETUP_BITS _u(0x02000000) +#define QMI_M0_TIMING_SELECT_SETUP_MSB _u(25) +#define QMI_M0_TIMING_SELECT_SETUP_LSB _u(25) +#define QMI_M0_TIMING_SELECT_SETUP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_SELECT_HOLD +// Description : Add up to three additional system clock cycles of active hold +// between the last falling edge of SCK and the deassertion of +// this window's chip select. +// +// The default hold time is one system clock cycle. Note that +// flash datasheets usually give chip select active hold time from +// the last *rising* edge of SCK, and so even zero hold from the +// last falling edge would be safe. +// +// Note that this is a minimum hold time guaranteed by the QMI: +// the actual chip select active hold may be slightly longer for +// read transfers with low clock divisors and/or high sample +// delays. Specifically, if the point two cycles after the last RX +// data sample is later than the last SCK falling edge, then the +// hold time is measured from *this* point. +// +// Note also that, in case the final SCK pulse is masked to save +// energy (true for non-DTR reads when COOLDOWN is disabled or +// PAGE_BREAK is reached), all of QMI's timing logic behaves as +// though the clock pulse were still present. The SELECT_HOLD time +// is applied from the point where the last SCK falling edge would +// be if the clock pulse were not masked. +#define QMI_M0_TIMING_SELECT_HOLD_RESET _u(0x0) +#define QMI_M0_TIMING_SELECT_HOLD_BITS _u(0x01800000) +#define QMI_M0_TIMING_SELECT_HOLD_MSB _u(24) +#define QMI_M0_TIMING_SELECT_HOLD_LSB _u(23) +#define QMI_M0_TIMING_SELECT_HOLD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_MAX_SELECT +// Description : Enforce a maximum assertion duration for this window's chip +// select, in units of 64 system clock cycles. If 0, the QMI is +// permitted to keep the chip select asserted indefinitely when +// servicing sequential memory accesses (see COOLDOWN). +// +// This feature is required to meet timing constraints of PSRAM +// devices, which specify a maximum chip select assertion so they +// can perform DRAM refresh cycles. See also MIN_DESELECT, which +// can enforce a minimum deselect time. +// +// If a memory access is in progress at the time MAX_SELECT is +// reached, the QMI will wait for the access to complete before +// deasserting the chip select. This additional time must be +// accounted for to calculate a safe MAX_SELECT value. In the +// worst case, this may be a fully-formed serial transfer, +// including command prefix and address, with a data payload as +// large as one cache line. +#define QMI_M0_TIMING_MAX_SELECT_RESET _u(0x00) +#define QMI_M0_TIMING_MAX_SELECT_BITS _u(0x007e0000) +#define QMI_M0_TIMING_MAX_SELECT_MSB _u(22) +#define QMI_M0_TIMING_MAX_SELECT_LSB _u(17) +#define QMI_M0_TIMING_MAX_SELECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_MIN_DESELECT +// Description : After this window's chip select is deasserted, it remains +// deasserted for half an SCK cycle (rounded up to an integer +// number of system clock cycles), plus MIN_DESELECT additional +// system clock cycles, before the QMI reasserts either chip +// select pin. +// +// Nonzero values may be required for PSRAM devices which enforce +// a longer minimum CS deselect time, so that they can perform +// internal DRAM refresh cycles whilst deselected. +#define QMI_M0_TIMING_MIN_DESELECT_RESET _u(0x00) +#define QMI_M0_TIMING_MIN_DESELECT_BITS _u(0x0001f000) +#define QMI_M0_TIMING_MIN_DESELECT_MSB _u(16) +#define QMI_M0_TIMING_MIN_DESELECT_LSB _u(12) +#define QMI_M0_TIMING_MIN_DESELECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_RXDELAY +// Description : Delay the read data sample timing, in units of one half of a +// system clock cycle. (Not necessarily half of an SCK cycle.) An +// RXDELAY of 0 means the sample is captured at the SDI input +// registers simultaneously with the rising edge of SCK launched +// from the SCK output register. +// +// At higher SCK frequencies, RXDELAY may need to be increased to +// account for the round trip delay of the pads, and the clock- +// to-Q delay of the QSPI memory device. +#define QMI_M0_TIMING_RXDELAY_RESET _u(0x0) +#define QMI_M0_TIMING_RXDELAY_BITS _u(0x00000700) +#define QMI_M0_TIMING_RXDELAY_MSB _u(10) +#define QMI_M0_TIMING_RXDELAY_LSB _u(8) +#define QMI_M0_TIMING_RXDELAY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_TIMING_CLKDIV +// Description : Clock divisor. Odd and even divisors are supported. Defines the +// SCK clock period in units of 1 system clock cycle. Divisors +// 1..255 are encoded directly, and a divisor of 256 is encoded +// with a value of CLKDIV=0. +// +// The clock divisor can be changed on-the-fly, even when the QMI +// is currently accessing memory in this address window. All other +// parameters must only be changed when the QMI is idle. +// +// If software is increasing CLKDIV in anticipation of an increase +// in the system clock frequency, a dummy access to either memory +// window (and appropriate processor barriers/fences) must be +// inserted after the Mx_TIMING write to ensure the SCK divisor +// change is in effect _before_ the system clock is changed. +#define QMI_M0_TIMING_CLKDIV_RESET _u(0x04) +#define QMI_M0_TIMING_CLKDIV_BITS _u(0x000000ff) +#define QMI_M0_TIMING_CLKDIV_MSB _u(7) +#define QMI_M0_TIMING_CLKDIV_LSB _u(0) +#define QMI_M0_TIMING_CLKDIV_ACCESS "RW" +// ============================================================================= +// Register : QMI_M0_RFMT +// Description : Read transfer format configuration for memory address window 0. +// +// Configure the bus width of each transfer phase individually, +// and configure the length or presence of the command prefix, +// command suffix and dummy/turnaround transfer phases. Only +// 24-bit addresses are supported. +// +// The reset value of the M0_RFMT register is configured to +// support a basic 03h serial read transfer with no additional +// configuration. +#define QMI_M0_RFMT_OFFSET _u(0x00000010) +#define QMI_M0_RFMT_BITS _u(0x1007d3ff) +#define QMI_M0_RFMT_RESET _u(0x00001000) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_DTR +// Description : Enable double transfer rate (DTR) for read commands: address, +// suffix and read data phases are active on both edges of SCK. +// SDO data is launched centre-aligned on each SCK edge, and SDI +// data is captured on the SCK edge that follows its launch. +// +// DTR is implemented by halving the clock rate; SCK has a period +// of 2 x CLK_DIV throughout the transfer. The prefix and dummy +// phases are still single transfer rate. +// +// If the suffix is quad-width, it must be 0 or 8 bits in length, +// to ensure an even number of SCK edges. +#define QMI_M0_RFMT_DTR_RESET _u(0x0) +#define QMI_M0_RFMT_DTR_BITS _u(0x10000000) +#define QMI_M0_RFMT_DTR_MSB _u(28) +#define QMI_M0_RFMT_DTR_LSB _u(28) +#define QMI_M0_RFMT_DTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_DUMMY_LEN +// Description : Length of dummy phase between command suffix and data phase, in +// units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 +// for single) +// 0x0 -> No dummy phase +// 0x1 -> 4 dummy bits +// 0x2 -> 8 dummy bits +// 0x3 -> 12 dummy bits +// 0x4 -> 16 dummy bits +// 0x5 -> 20 dummy bits +// 0x6 -> 24 dummy bits +// 0x7 -> 28 dummy bits +#define QMI_M0_RFMT_DUMMY_LEN_RESET _u(0x0) +#define QMI_M0_RFMT_DUMMY_LEN_BITS _u(0x00070000) +#define QMI_M0_RFMT_DUMMY_LEN_MSB _u(18) +#define QMI_M0_RFMT_DUMMY_LEN_LSB _u(16) +#define QMI_M0_RFMT_DUMMY_LEN_ACCESS "RW" +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_NONE _u(0x0) +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_4 _u(0x1) +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_8 _u(0x2) +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_12 _u(0x3) +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_16 _u(0x4) +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_20 _u(0x5) +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_24 _u(0x6) +#define QMI_M0_RFMT_DUMMY_LEN_VALUE_28 _u(0x7) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_SUFFIX_LEN +// Description : Length of post-address command suffix, in units of 4 bits. +// (i.e. 1 cycle for quad width, 2 for dual, 4 for single) +// +// Only values of 0 and 8 bits are supported. +// 0x0 -> No suffix +// 0x2 -> 8-bit suffix +#define QMI_M0_RFMT_SUFFIX_LEN_RESET _u(0x0) +#define QMI_M0_RFMT_SUFFIX_LEN_BITS _u(0x0000c000) +#define QMI_M0_RFMT_SUFFIX_LEN_MSB _u(15) +#define QMI_M0_RFMT_SUFFIX_LEN_LSB _u(14) +#define QMI_M0_RFMT_SUFFIX_LEN_ACCESS "RW" +#define QMI_M0_RFMT_SUFFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M0_RFMT_SUFFIX_LEN_VALUE_8 _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_PREFIX_LEN +// Description : Length of command prefix, in units of 8 bits. (i.e. 2 cycles +// for quad width, 4 for dual, 8 for single) +// 0x0 -> No prefix +// 0x1 -> 8-bit prefix +#define QMI_M0_RFMT_PREFIX_LEN_RESET _u(0x1) +#define QMI_M0_RFMT_PREFIX_LEN_BITS _u(0x00001000) +#define QMI_M0_RFMT_PREFIX_LEN_MSB _u(12) +#define QMI_M0_RFMT_PREFIX_LEN_LSB _u(12) +#define QMI_M0_RFMT_PREFIX_LEN_ACCESS "RW" +#define QMI_M0_RFMT_PREFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M0_RFMT_PREFIX_LEN_VALUE_8 _u(0x1) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_DATA_WIDTH +// Description : The width used for the data transfer +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_RFMT_DATA_WIDTH_RESET _u(0x0) +#define QMI_M0_RFMT_DATA_WIDTH_BITS _u(0x00000300) +#define QMI_M0_RFMT_DATA_WIDTH_MSB _u(9) +#define QMI_M0_RFMT_DATA_WIDTH_LSB _u(8) +#define QMI_M0_RFMT_DATA_WIDTH_ACCESS "RW" +#define QMI_M0_RFMT_DATA_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_RFMT_DATA_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_RFMT_DATA_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_DUMMY_WIDTH +// Description : The width used for the dummy phase, if any. +// +// If width is single, SD0/MOSI is held asserted low during the +// dummy phase, and SD1...SD3 are tristated. If width is +// dual/quad, all IOs are tristated during the dummy phase. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_RFMT_DUMMY_WIDTH_RESET _u(0x0) +#define QMI_M0_RFMT_DUMMY_WIDTH_BITS _u(0x000000c0) +#define QMI_M0_RFMT_DUMMY_WIDTH_MSB _u(7) +#define QMI_M0_RFMT_DUMMY_WIDTH_LSB _u(6) +#define QMI_M0_RFMT_DUMMY_WIDTH_ACCESS "RW" +#define QMI_M0_RFMT_DUMMY_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_RFMT_DUMMY_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_RFMT_DUMMY_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_SUFFIX_WIDTH +// Description : The width used for the post-address command suffix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_RFMT_SUFFIX_WIDTH_RESET _u(0x0) +#define QMI_M0_RFMT_SUFFIX_WIDTH_BITS _u(0x00000030) +#define QMI_M0_RFMT_SUFFIX_WIDTH_MSB _u(5) +#define QMI_M0_RFMT_SUFFIX_WIDTH_LSB _u(4) +#define QMI_M0_RFMT_SUFFIX_WIDTH_ACCESS "RW" +#define QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_RFMT_SUFFIX_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_ADDR_WIDTH +// Description : The transfer width used for the address. The address phase +// always transfers 24 bits in total. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_RFMT_ADDR_WIDTH_RESET _u(0x0) +#define QMI_M0_RFMT_ADDR_WIDTH_BITS _u(0x0000000c) +#define QMI_M0_RFMT_ADDR_WIDTH_MSB _u(3) +#define QMI_M0_RFMT_ADDR_WIDTH_LSB _u(2) +#define QMI_M0_RFMT_ADDR_WIDTH_ACCESS "RW" +#define QMI_M0_RFMT_ADDR_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_RFMT_ADDR_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_RFMT_ADDR_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RFMT_PREFIX_WIDTH +// Description : The transfer width used for the command prefix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_RFMT_PREFIX_WIDTH_RESET _u(0x0) +#define QMI_M0_RFMT_PREFIX_WIDTH_BITS _u(0x00000003) +#define QMI_M0_RFMT_PREFIX_WIDTH_MSB _u(1) +#define QMI_M0_RFMT_PREFIX_WIDTH_LSB _u(0) +#define QMI_M0_RFMT_PREFIX_WIDTH_ACCESS "RW" +#define QMI_M0_RFMT_PREFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_RFMT_PREFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_RFMT_PREFIX_WIDTH_VALUE_Q _u(0x2) +// ============================================================================= +// Register : QMI_M0_RCMD +// Description : Command constants used for reads from memory address window 0. +// +// The reset value of the M0_RCMD register is configured to +// support a basic 03h serial read transfer with no additional +// configuration. +#define QMI_M0_RCMD_OFFSET _u(0x00000014) +#define QMI_M0_RCMD_BITS _u(0x0000ffff) +#define QMI_M0_RCMD_RESET _u(0x0000a003) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RCMD_SUFFIX +// Description : The command suffix bits following the address, if +// Mx_RFMT_SUFFIX_LEN is nonzero. +#define QMI_M0_RCMD_SUFFIX_RESET _u(0xa0) +#define QMI_M0_RCMD_SUFFIX_BITS _u(0x0000ff00) +#define QMI_M0_RCMD_SUFFIX_MSB _u(15) +#define QMI_M0_RCMD_SUFFIX_LSB _u(8) +#define QMI_M0_RCMD_SUFFIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_RCMD_PREFIX +// Description : The command prefix bits to prepend on each new transfer, if +// Mx_RFMT_PREFIX_LEN is nonzero. +#define QMI_M0_RCMD_PREFIX_RESET _u(0x03) +#define QMI_M0_RCMD_PREFIX_BITS _u(0x000000ff) +#define QMI_M0_RCMD_PREFIX_MSB _u(7) +#define QMI_M0_RCMD_PREFIX_LSB _u(0) +#define QMI_M0_RCMD_PREFIX_ACCESS "RW" +// ============================================================================= +// Register : QMI_M0_WFMT +// Description : Write transfer format configuration for memory address window +// 0. +// +// Configure the bus width of each transfer phase individually, +// and configure the length or presence of the command prefix, +// command suffix and dummy/turnaround transfer phases. Only +// 24-bit addresses are supported. +// +// The reset value of the M0_WFMT register is configured to +// support a basic 02h serial write transfer. However, writes to +// this window must first be enabled via the XIP_CTRL_WRITABLE_M0 +// bit, as XIP memory is read-only by default. +#define QMI_M0_WFMT_OFFSET _u(0x00000018) +#define QMI_M0_WFMT_BITS _u(0x1007d3ff) +#define QMI_M0_WFMT_RESET _u(0x00001000) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_DTR +// Description : Enable double transfer rate (DTR) for write commands: address, +// suffix and write data phases are active on both edges of SCK. +// SDO data is launched centre-aligned on each SCK edge, and SDI +// data is captured on the SCK edge that follows its launch. +// +// DTR is implemented by halving the clock rate; SCK has a period +// of 2 x CLK_DIV throughout the transfer. The prefix and dummy +// phases are still single transfer rate. +// +// If the suffix is quad-width, it must be 0 or 8 bits in length, +// to ensure an even number of SCK edges. +#define QMI_M0_WFMT_DTR_RESET _u(0x0) +#define QMI_M0_WFMT_DTR_BITS _u(0x10000000) +#define QMI_M0_WFMT_DTR_MSB _u(28) +#define QMI_M0_WFMT_DTR_LSB _u(28) +#define QMI_M0_WFMT_DTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_DUMMY_LEN +// Description : Length of dummy phase between command suffix and data phase, in +// units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 +// for single) +// 0x0 -> No dummy phase +// 0x1 -> 4 dummy bits +// 0x2 -> 8 dummy bits +// 0x3 -> 12 dummy bits +// 0x4 -> 16 dummy bits +// 0x5 -> 20 dummy bits +// 0x6 -> 24 dummy bits +// 0x7 -> 28 dummy bits +#define QMI_M0_WFMT_DUMMY_LEN_RESET _u(0x0) +#define QMI_M0_WFMT_DUMMY_LEN_BITS _u(0x00070000) +#define QMI_M0_WFMT_DUMMY_LEN_MSB _u(18) +#define QMI_M0_WFMT_DUMMY_LEN_LSB _u(16) +#define QMI_M0_WFMT_DUMMY_LEN_ACCESS "RW" +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_NONE _u(0x0) +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_4 _u(0x1) +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_8 _u(0x2) +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_12 _u(0x3) +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_16 _u(0x4) +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_20 _u(0x5) +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_24 _u(0x6) +#define QMI_M0_WFMT_DUMMY_LEN_VALUE_28 _u(0x7) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_SUFFIX_LEN +// Description : Length of post-address command suffix, in units of 4 bits. +// (i.e. 1 cycle for quad width, 2 for dual, 4 for single) +// +// Only values of 0 and 8 bits are supported. +// 0x0 -> No suffix +// 0x2 -> 8-bit suffix +#define QMI_M0_WFMT_SUFFIX_LEN_RESET _u(0x0) +#define QMI_M0_WFMT_SUFFIX_LEN_BITS _u(0x0000c000) +#define QMI_M0_WFMT_SUFFIX_LEN_MSB _u(15) +#define QMI_M0_WFMT_SUFFIX_LEN_LSB _u(14) +#define QMI_M0_WFMT_SUFFIX_LEN_ACCESS "RW" +#define QMI_M0_WFMT_SUFFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M0_WFMT_SUFFIX_LEN_VALUE_8 _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_PREFIX_LEN +// Description : Length of command prefix, in units of 8 bits. (i.e. 2 cycles +// for quad width, 4 for dual, 8 for single) +// 0x0 -> No prefix +// 0x1 -> 8-bit prefix +#define QMI_M0_WFMT_PREFIX_LEN_RESET _u(0x1) +#define QMI_M0_WFMT_PREFIX_LEN_BITS _u(0x00001000) +#define QMI_M0_WFMT_PREFIX_LEN_MSB _u(12) +#define QMI_M0_WFMT_PREFIX_LEN_LSB _u(12) +#define QMI_M0_WFMT_PREFIX_LEN_ACCESS "RW" +#define QMI_M0_WFMT_PREFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M0_WFMT_PREFIX_LEN_VALUE_8 _u(0x1) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_DATA_WIDTH +// Description : The width used for the data transfer +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_WFMT_DATA_WIDTH_RESET _u(0x0) +#define QMI_M0_WFMT_DATA_WIDTH_BITS _u(0x00000300) +#define QMI_M0_WFMT_DATA_WIDTH_MSB _u(9) +#define QMI_M0_WFMT_DATA_WIDTH_LSB _u(8) +#define QMI_M0_WFMT_DATA_WIDTH_ACCESS "RW" +#define QMI_M0_WFMT_DATA_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_WFMT_DATA_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_WFMT_DATA_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_DUMMY_WIDTH +// Description : The width used for the dummy phase, if any. +// +// If width is single, SD0/MOSI is held asserted low during the +// dummy phase, and SD1...SD3 are tristated. If width is +// dual/quad, all IOs are tristated during the dummy phase. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_WFMT_DUMMY_WIDTH_RESET _u(0x0) +#define QMI_M0_WFMT_DUMMY_WIDTH_BITS _u(0x000000c0) +#define QMI_M0_WFMT_DUMMY_WIDTH_MSB _u(7) +#define QMI_M0_WFMT_DUMMY_WIDTH_LSB _u(6) +#define QMI_M0_WFMT_DUMMY_WIDTH_ACCESS "RW" +#define QMI_M0_WFMT_DUMMY_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_WFMT_DUMMY_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_WFMT_DUMMY_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_SUFFIX_WIDTH +// Description : The width used for the post-address command suffix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_WFMT_SUFFIX_WIDTH_RESET _u(0x0) +#define QMI_M0_WFMT_SUFFIX_WIDTH_BITS _u(0x00000030) +#define QMI_M0_WFMT_SUFFIX_WIDTH_MSB _u(5) +#define QMI_M0_WFMT_SUFFIX_WIDTH_LSB _u(4) +#define QMI_M0_WFMT_SUFFIX_WIDTH_ACCESS "RW" +#define QMI_M0_WFMT_SUFFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_WFMT_SUFFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_WFMT_SUFFIX_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_ADDR_WIDTH +// Description : The transfer width used for the address. The address phase +// always transfers 24 bits in total. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_WFMT_ADDR_WIDTH_RESET _u(0x0) +#define QMI_M0_WFMT_ADDR_WIDTH_BITS _u(0x0000000c) +#define QMI_M0_WFMT_ADDR_WIDTH_MSB _u(3) +#define QMI_M0_WFMT_ADDR_WIDTH_LSB _u(2) +#define QMI_M0_WFMT_ADDR_WIDTH_ACCESS "RW" +#define QMI_M0_WFMT_ADDR_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_WFMT_ADDR_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_WFMT_ADDR_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WFMT_PREFIX_WIDTH +// Description : The transfer width used for the command prefix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M0_WFMT_PREFIX_WIDTH_RESET _u(0x0) +#define QMI_M0_WFMT_PREFIX_WIDTH_BITS _u(0x00000003) +#define QMI_M0_WFMT_PREFIX_WIDTH_MSB _u(1) +#define QMI_M0_WFMT_PREFIX_WIDTH_LSB _u(0) +#define QMI_M0_WFMT_PREFIX_WIDTH_ACCESS "RW" +#define QMI_M0_WFMT_PREFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M0_WFMT_PREFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M0_WFMT_PREFIX_WIDTH_VALUE_Q _u(0x2) +// ============================================================================= +// Register : QMI_M0_WCMD +// Description : Command constants used for writes to memory address window 0. +// +// The reset value of the M0_WCMD register is configured to +// support a basic 02h serial write transfer with no additional +// configuration. +#define QMI_M0_WCMD_OFFSET _u(0x0000001c) +#define QMI_M0_WCMD_BITS _u(0x0000ffff) +#define QMI_M0_WCMD_RESET _u(0x0000a002) +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WCMD_SUFFIX +// Description : The command suffix bits following the address, if +// Mx_WFMT_SUFFIX_LEN is nonzero. +#define QMI_M0_WCMD_SUFFIX_RESET _u(0xa0) +#define QMI_M0_WCMD_SUFFIX_BITS _u(0x0000ff00) +#define QMI_M0_WCMD_SUFFIX_MSB _u(15) +#define QMI_M0_WCMD_SUFFIX_LSB _u(8) +#define QMI_M0_WCMD_SUFFIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M0_WCMD_PREFIX +// Description : The command prefix bits to prepend on each new transfer, if +// Mx_WFMT_PREFIX_LEN is nonzero. +#define QMI_M0_WCMD_PREFIX_RESET _u(0x02) +#define QMI_M0_WCMD_PREFIX_BITS _u(0x000000ff) +#define QMI_M0_WCMD_PREFIX_MSB _u(7) +#define QMI_M0_WCMD_PREFIX_LSB _u(0) +#define QMI_M0_WCMD_PREFIX_ACCESS "RW" +// ============================================================================= +// Register : QMI_M1_TIMING +// Description : Timing configuration register for memory address window 1. +#define QMI_M1_TIMING_OFFSET _u(0x00000020) +#define QMI_M1_TIMING_BITS _u(0xf3fff7ff) +#define QMI_M1_TIMING_RESET _u(0x40000004) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_COOLDOWN +// Description : Chip select cooldown period. When a memory transfer finishes, +// the chip select remains asserted for 64 x COOLDOWN system clock +// cycles, plus half an SCK clock period (rounded up for odd SCK +// divisors). After this cooldown expires, the chip select is +// always deasserted to save power. +// +// If the next memory access arrives within the cooldown period, +// the QMI may be able to append more SCK cycles to the currently +// ongoing SPI transfer, rather than starting a new transfer. This +// reduces access latency and increases bus throughput. +// +// Specifically, the next access must be in the same direction +// (read/write), access the same memory window (chip select 0/1), +// and follow sequentially the address of the last transfer. If +// any of these are false, the new access will first deassert the +// chip select, then begin a new transfer. +// +// If COOLDOWN is 0, the address alignment configured by PAGEBREAK +// has been reached, or the total chip select assertion limit +// MAX_SELECT has been reached, the cooldown period is skipped, +// and the chip select will always be deasserted one half SCK +// period after the transfer finishes. +#define QMI_M1_TIMING_COOLDOWN_RESET _u(0x1) +#define QMI_M1_TIMING_COOLDOWN_BITS _u(0xc0000000) +#define QMI_M1_TIMING_COOLDOWN_MSB _u(31) +#define QMI_M1_TIMING_COOLDOWN_LSB _u(30) +#define QMI_M1_TIMING_COOLDOWN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_PAGEBREAK +// Description : When page break is enabled, chip select will automatically +// deassert when crossing certain power-of-2-aligned address +// boundaries. The next access will always begin a new read/write +// SPI burst, even if the address of the next access follows in +// sequence with the last access before the page boundary. +// +// Some flash and PSRAM devices forbid crossing page boundaries +// with a single read/write transfer, or restrict the operating +// frequency for transfers that do cross page a boundary. This +// option allows the QMI to safely support those devices. +// +// This field has no effect when COOLDOWN is disabled. +// 0x0 -> No page boundary is enforced +// 0x1 -> Break bursts crossing a 256-byte page boundary +// 0x2 -> Break bursts crossing a 1024-byte quad-page boundary +// 0x3 -> Break bursts crossing a 4096-byte sector boundary +#define QMI_M1_TIMING_PAGEBREAK_RESET _u(0x0) +#define QMI_M1_TIMING_PAGEBREAK_BITS _u(0x30000000) +#define QMI_M1_TIMING_PAGEBREAK_MSB _u(29) +#define QMI_M1_TIMING_PAGEBREAK_LSB _u(28) +#define QMI_M1_TIMING_PAGEBREAK_ACCESS "RW" +#define QMI_M1_TIMING_PAGEBREAK_VALUE_NONE _u(0x0) +#define QMI_M1_TIMING_PAGEBREAK_VALUE_256 _u(0x1) +#define QMI_M1_TIMING_PAGEBREAK_VALUE_1024 _u(0x2) +#define QMI_M1_TIMING_PAGEBREAK_VALUE_4096 _u(0x3) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_SELECT_SETUP +// Description : Add up to one additional system clock cycle of setup between +// chip select assertion and the first rising edge of SCK. +// +// The default setup time is one half SCK period, which is usually +// sufficient except for very high SCK frequencies with some flash +// devices. +#define QMI_M1_TIMING_SELECT_SETUP_RESET _u(0x0) +#define QMI_M1_TIMING_SELECT_SETUP_BITS _u(0x02000000) +#define QMI_M1_TIMING_SELECT_SETUP_MSB _u(25) +#define QMI_M1_TIMING_SELECT_SETUP_LSB _u(25) +#define QMI_M1_TIMING_SELECT_SETUP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_SELECT_HOLD +// Description : Add up to three additional system clock cycles of active hold +// between the last falling edge of SCK and the deassertion of +// this window's chip select. +// +// The default hold time is one system clock cycle. Note that +// flash datasheets usually give chip select active hold time from +// the last *rising* edge of SCK, and so even zero hold from the +// last falling edge would be safe. +// +// Note that this is a minimum hold time guaranteed by the QMI: +// the actual chip select active hold may be slightly longer for +// read transfers with low clock divisors and/or high sample +// delays. Specifically, if the point two cycles after the last RX +// data sample is later than the last SCK falling edge, then the +// hold time is measured from *this* point. +// +// Note also that, in case the final SCK pulse is masked to save +// energy (true for non-DTR reads when COOLDOWN is disabled or +// PAGE_BREAK is reached), all of QMI's timing logic behaves as +// though the clock pulse were still present. The SELECT_HOLD time +// is applied from the point where the last SCK falling edge would +// be if the clock pulse were not masked. +#define QMI_M1_TIMING_SELECT_HOLD_RESET _u(0x0) +#define QMI_M1_TIMING_SELECT_HOLD_BITS _u(0x01800000) +#define QMI_M1_TIMING_SELECT_HOLD_MSB _u(24) +#define QMI_M1_TIMING_SELECT_HOLD_LSB _u(23) +#define QMI_M1_TIMING_SELECT_HOLD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_MAX_SELECT +// Description : Enforce a maximum assertion duration for this window's chip +// select, in units of 64 system clock cycles. If 0, the QMI is +// permitted to keep the chip select asserted indefinitely when +// servicing sequential memory accesses (see COOLDOWN). +// +// This feature is required to meet timing constraints of PSRAM +// devices, which specify a maximum chip select assertion so they +// can perform DRAM refresh cycles. See also MIN_DESELECT, which +// can enforce a minimum deselect time. +// +// If a memory access is in progress at the time MAX_SELECT is +// reached, the QMI will wait for the access to complete before +// deasserting the chip select. This additional time must be +// accounted for to calculate a safe MAX_SELECT value. In the +// worst case, this may be a fully-formed serial transfer, +// including command prefix and address, with a data payload as +// large as one cache line. +#define QMI_M1_TIMING_MAX_SELECT_RESET _u(0x00) +#define QMI_M1_TIMING_MAX_SELECT_BITS _u(0x007e0000) +#define QMI_M1_TIMING_MAX_SELECT_MSB _u(22) +#define QMI_M1_TIMING_MAX_SELECT_LSB _u(17) +#define QMI_M1_TIMING_MAX_SELECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_MIN_DESELECT +// Description : After this window's chip select is deasserted, it remains +// deasserted for half an SCK cycle (rounded up to an integer +// number of system clock cycles), plus MIN_DESELECT additional +// system clock cycles, before the QMI reasserts either chip +// select pin. +// +// Nonzero values may be required for PSRAM devices which enforce +// a longer minimum CS deselect time, so that they can perform +// internal DRAM refresh cycles whilst deselected. +#define QMI_M1_TIMING_MIN_DESELECT_RESET _u(0x00) +#define QMI_M1_TIMING_MIN_DESELECT_BITS _u(0x0001f000) +#define QMI_M1_TIMING_MIN_DESELECT_MSB _u(16) +#define QMI_M1_TIMING_MIN_DESELECT_LSB _u(12) +#define QMI_M1_TIMING_MIN_DESELECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_RXDELAY +// Description : Delay the read data sample timing, in units of one half of a +// system clock cycle. (Not necessarily half of an SCK cycle.) An +// RXDELAY of 0 means the sample is captured at the SDI input +// registers simultaneously with the rising edge of SCK launched +// from the SCK output register. +// +// At higher SCK frequencies, RXDELAY may need to be increased to +// account for the round trip delay of the pads, and the clock- +// to-Q delay of the QSPI memory device. +#define QMI_M1_TIMING_RXDELAY_RESET _u(0x0) +#define QMI_M1_TIMING_RXDELAY_BITS _u(0x00000700) +#define QMI_M1_TIMING_RXDELAY_MSB _u(10) +#define QMI_M1_TIMING_RXDELAY_LSB _u(8) +#define QMI_M1_TIMING_RXDELAY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_TIMING_CLKDIV +// Description : Clock divisor. Odd and even divisors are supported. Defines the +// SCK clock period in units of 1 system clock cycle. Divisors +// 1..255 are encoded directly, and a divisor of 256 is encoded +// with a value of CLKDIV=0. +// +// The clock divisor can be changed on-the-fly, even when the QMI +// is currently accessing memory in this address window. All other +// parameters must only be changed when the QMI is idle. +// +// If software is increasing CLKDIV in anticipation of an increase +// in the system clock frequency, a dummy access to either memory +// window (and appropriate processor barriers/fences) must be +// inserted after the Mx_TIMING write to ensure the SCK divisor +// change is in effect _before_ the system clock is changed. +#define QMI_M1_TIMING_CLKDIV_RESET _u(0x04) +#define QMI_M1_TIMING_CLKDIV_BITS _u(0x000000ff) +#define QMI_M1_TIMING_CLKDIV_MSB _u(7) +#define QMI_M1_TIMING_CLKDIV_LSB _u(0) +#define QMI_M1_TIMING_CLKDIV_ACCESS "RW" +// ============================================================================= +// Register : QMI_M1_RFMT +// Description : Read transfer format configuration for memory address window 1. +// +// Configure the bus width of each transfer phase individually, +// and configure the length or presence of the command prefix, +// command suffix and dummy/turnaround transfer phases. Only +// 24-bit addresses are supported. +// +// The reset value of the M1_RFMT register is configured to +// support a basic 03h serial read transfer with no additional +// configuration. +#define QMI_M1_RFMT_OFFSET _u(0x00000024) +#define QMI_M1_RFMT_BITS _u(0x1007d3ff) +#define QMI_M1_RFMT_RESET _u(0x00001000) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_DTR +// Description : Enable double transfer rate (DTR) for read commands: address, +// suffix and read data phases are active on both edges of SCK. +// SDO data is launched centre-aligned on each SCK edge, and SDI +// data is captured on the SCK edge that follows its launch. +// +// DTR is implemented by halving the clock rate; SCK has a period +// of 2 x CLK_DIV throughout the transfer. The prefix and dummy +// phases are still single transfer rate. +// +// If the suffix is quad-width, it must be 0 or 8 bits in length, +// to ensure an even number of SCK edges. +#define QMI_M1_RFMT_DTR_RESET _u(0x0) +#define QMI_M1_RFMT_DTR_BITS _u(0x10000000) +#define QMI_M1_RFMT_DTR_MSB _u(28) +#define QMI_M1_RFMT_DTR_LSB _u(28) +#define QMI_M1_RFMT_DTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_DUMMY_LEN +// Description : Length of dummy phase between command suffix and data phase, in +// units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 +// for single) +// 0x0 -> No dummy phase +// 0x1 -> 4 dummy bits +// 0x2 -> 8 dummy bits +// 0x3 -> 12 dummy bits +// 0x4 -> 16 dummy bits +// 0x5 -> 20 dummy bits +// 0x6 -> 24 dummy bits +// 0x7 -> 28 dummy bits +#define QMI_M1_RFMT_DUMMY_LEN_RESET _u(0x0) +#define QMI_M1_RFMT_DUMMY_LEN_BITS _u(0x00070000) +#define QMI_M1_RFMT_DUMMY_LEN_MSB _u(18) +#define QMI_M1_RFMT_DUMMY_LEN_LSB _u(16) +#define QMI_M1_RFMT_DUMMY_LEN_ACCESS "RW" +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_NONE _u(0x0) +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_4 _u(0x1) +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_8 _u(0x2) +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_12 _u(0x3) +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_16 _u(0x4) +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_20 _u(0x5) +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_24 _u(0x6) +#define QMI_M1_RFMT_DUMMY_LEN_VALUE_28 _u(0x7) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_SUFFIX_LEN +// Description : Length of post-address command suffix, in units of 4 bits. +// (i.e. 1 cycle for quad width, 2 for dual, 4 for single) +// +// Only values of 0 and 8 bits are supported. +// 0x0 -> No suffix +// 0x2 -> 8-bit suffix +#define QMI_M1_RFMT_SUFFIX_LEN_RESET _u(0x0) +#define QMI_M1_RFMT_SUFFIX_LEN_BITS _u(0x0000c000) +#define QMI_M1_RFMT_SUFFIX_LEN_MSB _u(15) +#define QMI_M1_RFMT_SUFFIX_LEN_LSB _u(14) +#define QMI_M1_RFMT_SUFFIX_LEN_ACCESS "RW" +#define QMI_M1_RFMT_SUFFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M1_RFMT_SUFFIX_LEN_VALUE_8 _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_PREFIX_LEN +// Description : Length of command prefix, in units of 8 bits. (i.e. 2 cycles +// for quad width, 4 for dual, 8 for single) +// 0x0 -> No prefix +// 0x1 -> 8-bit prefix +#define QMI_M1_RFMT_PREFIX_LEN_RESET _u(0x1) +#define QMI_M1_RFMT_PREFIX_LEN_BITS _u(0x00001000) +#define QMI_M1_RFMT_PREFIX_LEN_MSB _u(12) +#define QMI_M1_RFMT_PREFIX_LEN_LSB _u(12) +#define QMI_M1_RFMT_PREFIX_LEN_ACCESS "RW" +#define QMI_M1_RFMT_PREFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M1_RFMT_PREFIX_LEN_VALUE_8 _u(0x1) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_DATA_WIDTH +// Description : The width used for the data transfer +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_RFMT_DATA_WIDTH_RESET _u(0x0) +#define QMI_M1_RFMT_DATA_WIDTH_BITS _u(0x00000300) +#define QMI_M1_RFMT_DATA_WIDTH_MSB _u(9) +#define QMI_M1_RFMT_DATA_WIDTH_LSB _u(8) +#define QMI_M1_RFMT_DATA_WIDTH_ACCESS "RW" +#define QMI_M1_RFMT_DATA_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_RFMT_DATA_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_RFMT_DATA_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_DUMMY_WIDTH +// Description : The width used for the dummy phase, if any. +// +// If width is single, SD0/MOSI is held asserted low during the +// dummy phase, and SD1...SD3 are tristated. If width is +// dual/quad, all IOs are tristated during the dummy phase. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_RFMT_DUMMY_WIDTH_RESET _u(0x0) +#define QMI_M1_RFMT_DUMMY_WIDTH_BITS _u(0x000000c0) +#define QMI_M1_RFMT_DUMMY_WIDTH_MSB _u(7) +#define QMI_M1_RFMT_DUMMY_WIDTH_LSB _u(6) +#define QMI_M1_RFMT_DUMMY_WIDTH_ACCESS "RW" +#define QMI_M1_RFMT_DUMMY_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_RFMT_DUMMY_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_RFMT_DUMMY_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_SUFFIX_WIDTH +// Description : The width used for the post-address command suffix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_RFMT_SUFFIX_WIDTH_RESET _u(0x0) +#define QMI_M1_RFMT_SUFFIX_WIDTH_BITS _u(0x00000030) +#define QMI_M1_RFMT_SUFFIX_WIDTH_MSB _u(5) +#define QMI_M1_RFMT_SUFFIX_WIDTH_LSB _u(4) +#define QMI_M1_RFMT_SUFFIX_WIDTH_ACCESS "RW" +#define QMI_M1_RFMT_SUFFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_RFMT_SUFFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_RFMT_SUFFIX_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_ADDR_WIDTH +// Description : The transfer width used for the address. The address phase +// always transfers 24 bits in total. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_RFMT_ADDR_WIDTH_RESET _u(0x0) +#define QMI_M1_RFMT_ADDR_WIDTH_BITS _u(0x0000000c) +#define QMI_M1_RFMT_ADDR_WIDTH_MSB _u(3) +#define QMI_M1_RFMT_ADDR_WIDTH_LSB _u(2) +#define QMI_M1_RFMT_ADDR_WIDTH_ACCESS "RW" +#define QMI_M1_RFMT_ADDR_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_RFMT_ADDR_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_RFMT_ADDR_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RFMT_PREFIX_WIDTH +// Description : The transfer width used for the command prefix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_RFMT_PREFIX_WIDTH_RESET _u(0x0) +#define QMI_M1_RFMT_PREFIX_WIDTH_BITS _u(0x00000003) +#define QMI_M1_RFMT_PREFIX_WIDTH_MSB _u(1) +#define QMI_M1_RFMT_PREFIX_WIDTH_LSB _u(0) +#define QMI_M1_RFMT_PREFIX_WIDTH_ACCESS "RW" +#define QMI_M1_RFMT_PREFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_RFMT_PREFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_RFMT_PREFIX_WIDTH_VALUE_Q _u(0x2) +// ============================================================================= +// Register : QMI_M1_RCMD +// Description : Command constants used for reads from memory address window 1. +// +// The reset value of the M1_RCMD register is configured to +// support a basic 03h serial read transfer with no additional +// configuration. +#define QMI_M1_RCMD_OFFSET _u(0x00000028) +#define QMI_M1_RCMD_BITS _u(0x0000ffff) +#define QMI_M1_RCMD_RESET _u(0x0000a003) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RCMD_SUFFIX +// Description : The command suffix bits following the address, if +// Mx_RFMT_SUFFIX_LEN is nonzero. +#define QMI_M1_RCMD_SUFFIX_RESET _u(0xa0) +#define QMI_M1_RCMD_SUFFIX_BITS _u(0x0000ff00) +#define QMI_M1_RCMD_SUFFIX_MSB _u(15) +#define QMI_M1_RCMD_SUFFIX_LSB _u(8) +#define QMI_M1_RCMD_SUFFIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_RCMD_PREFIX +// Description : The command prefix bits to prepend on each new transfer, if +// Mx_RFMT_PREFIX_LEN is nonzero. +#define QMI_M1_RCMD_PREFIX_RESET _u(0x03) +#define QMI_M1_RCMD_PREFIX_BITS _u(0x000000ff) +#define QMI_M1_RCMD_PREFIX_MSB _u(7) +#define QMI_M1_RCMD_PREFIX_LSB _u(0) +#define QMI_M1_RCMD_PREFIX_ACCESS "RW" +// ============================================================================= +// Register : QMI_M1_WFMT +// Description : Write transfer format configuration for memory address window +// 1. +// +// Configure the bus width of each transfer phase individually, +// and configure the length or presence of the command prefix, +// command suffix and dummy/turnaround transfer phases. Only +// 24-bit addresses are supported. +// +// The reset value of the M1_WFMT register is configured to +// support a basic 02h serial write transfer. However, writes to +// this window must first be enabled via the XIP_CTRL_WRITABLE_M1 +// bit, as XIP memory is read-only by default. +#define QMI_M1_WFMT_OFFSET _u(0x0000002c) +#define QMI_M1_WFMT_BITS _u(0x1007d3ff) +#define QMI_M1_WFMT_RESET _u(0x00001000) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_DTR +// Description : Enable double transfer rate (DTR) for write commands: address, +// suffix and write data phases are active on both edges of SCK. +// SDO data is launched centre-aligned on each SCK edge, and SDI +// data is captured on the SCK edge that follows its launch. +// +// DTR is implemented by halving the clock rate; SCK has a period +// of 2 x CLK_DIV throughout the transfer. The prefix and dummy +// phases are still single transfer rate. +// +// If the suffix is quad-width, it must be 0 or 8 bits in length, +// to ensure an even number of SCK edges. +#define QMI_M1_WFMT_DTR_RESET _u(0x0) +#define QMI_M1_WFMT_DTR_BITS _u(0x10000000) +#define QMI_M1_WFMT_DTR_MSB _u(28) +#define QMI_M1_WFMT_DTR_LSB _u(28) +#define QMI_M1_WFMT_DTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_DUMMY_LEN +// Description : Length of dummy phase between command suffix and data phase, in +// units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 +// for single) +// 0x0 -> No dummy phase +// 0x1 -> 4 dummy bits +// 0x2 -> 8 dummy bits +// 0x3 -> 12 dummy bits +// 0x4 -> 16 dummy bits +// 0x5 -> 20 dummy bits +// 0x6 -> 24 dummy bits +// 0x7 -> 28 dummy bits +#define QMI_M1_WFMT_DUMMY_LEN_RESET _u(0x0) +#define QMI_M1_WFMT_DUMMY_LEN_BITS _u(0x00070000) +#define QMI_M1_WFMT_DUMMY_LEN_MSB _u(18) +#define QMI_M1_WFMT_DUMMY_LEN_LSB _u(16) +#define QMI_M1_WFMT_DUMMY_LEN_ACCESS "RW" +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_NONE _u(0x0) +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_4 _u(0x1) +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_8 _u(0x2) +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_12 _u(0x3) +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_16 _u(0x4) +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_20 _u(0x5) +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_24 _u(0x6) +#define QMI_M1_WFMT_DUMMY_LEN_VALUE_28 _u(0x7) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_SUFFIX_LEN +// Description : Length of post-address command suffix, in units of 4 bits. +// (i.e. 1 cycle for quad width, 2 for dual, 4 for single) +// +// Only values of 0 and 8 bits are supported. +// 0x0 -> No suffix +// 0x2 -> 8-bit suffix +#define QMI_M1_WFMT_SUFFIX_LEN_RESET _u(0x0) +#define QMI_M1_WFMT_SUFFIX_LEN_BITS _u(0x0000c000) +#define QMI_M1_WFMT_SUFFIX_LEN_MSB _u(15) +#define QMI_M1_WFMT_SUFFIX_LEN_LSB _u(14) +#define QMI_M1_WFMT_SUFFIX_LEN_ACCESS "RW" +#define QMI_M1_WFMT_SUFFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M1_WFMT_SUFFIX_LEN_VALUE_8 _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_PREFIX_LEN +// Description : Length of command prefix, in units of 8 bits. (i.e. 2 cycles +// for quad width, 4 for dual, 8 for single) +// 0x0 -> No prefix +// 0x1 -> 8-bit prefix +#define QMI_M1_WFMT_PREFIX_LEN_RESET _u(0x1) +#define QMI_M1_WFMT_PREFIX_LEN_BITS _u(0x00001000) +#define QMI_M1_WFMT_PREFIX_LEN_MSB _u(12) +#define QMI_M1_WFMT_PREFIX_LEN_LSB _u(12) +#define QMI_M1_WFMT_PREFIX_LEN_ACCESS "RW" +#define QMI_M1_WFMT_PREFIX_LEN_VALUE_NONE _u(0x0) +#define QMI_M1_WFMT_PREFIX_LEN_VALUE_8 _u(0x1) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_DATA_WIDTH +// Description : The width used for the data transfer +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_WFMT_DATA_WIDTH_RESET _u(0x0) +#define QMI_M1_WFMT_DATA_WIDTH_BITS _u(0x00000300) +#define QMI_M1_WFMT_DATA_WIDTH_MSB _u(9) +#define QMI_M1_WFMT_DATA_WIDTH_LSB _u(8) +#define QMI_M1_WFMT_DATA_WIDTH_ACCESS "RW" +#define QMI_M1_WFMT_DATA_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_WFMT_DATA_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_WFMT_DATA_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_DUMMY_WIDTH +// Description : The width used for the dummy phase, if any. +// +// If width is single, SD0/MOSI is held asserted low during the +// dummy phase, and SD1...SD3 are tristated. If width is +// dual/quad, all IOs are tristated during the dummy phase. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_WFMT_DUMMY_WIDTH_RESET _u(0x0) +#define QMI_M1_WFMT_DUMMY_WIDTH_BITS _u(0x000000c0) +#define QMI_M1_WFMT_DUMMY_WIDTH_MSB _u(7) +#define QMI_M1_WFMT_DUMMY_WIDTH_LSB _u(6) +#define QMI_M1_WFMT_DUMMY_WIDTH_ACCESS "RW" +#define QMI_M1_WFMT_DUMMY_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_WFMT_DUMMY_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_WFMT_DUMMY_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_SUFFIX_WIDTH +// Description : The width used for the post-address command suffix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_WFMT_SUFFIX_WIDTH_RESET _u(0x0) +#define QMI_M1_WFMT_SUFFIX_WIDTH_BITS _u(0x00000030) +#define QMI_M1_WFMT_SUFFIX_WIDTH_MSB _u(5) +#define QMI_M1_WFMT_SUFFIX_WIDTH_LSB _u(4) +#define QMI_M1_WFMT_SUFFIX_WIDTH_ACCESS "RW" +#define QMI_M1_WFMT_SUFFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_WFMT_SUFFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_WFMT_SUFFIX_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_ADDR_WIDTH +// Description : The transfer width used for the address. The address phase +// always transfers 24 bits in total. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_WFMT_ADDR_WIDTH_RESET _u(0x0) +#define QMI_M1_WFMT_ADDR_WIDTH_BITS _u(0x0000000c) +#define QMI_M1_WFMT_ADDR_WIDTH_MSB _u(3) +#define QMI_M1_WFMT_ADDR_WIDTH_LSB _u(2) +#define QMI_M1_WFMT_ADDR_WIDTH_ACCESS "RW" +#define QMI_M1_WFMT_ADDR_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_WFMT_ADDR_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_WFMT_ADDR_WIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WFMT_PREFIX_WIDTH +// Description : The transfer width used for the command prefix, if any +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define QMI_M1_WFMT_PREFIX_WIDTH_RESET _u(0x0) +#define QMI_M1_WFMT_PREFIX_WIDTH_BITS _u(0x00000003) +#define QMI_M1_WFMT_PREFIX_WIDTH_MSB _u(1) +#define QMI_M1_WFMT_PREFIX_WIDTH_LSB _u(0) +#define QMI_M1_WFMT_PREFIX_WIDTH_ACCESS "RW" +#define QMI_M1_WFMT_PREFIX_WIDTH_VALUE_S _u(0x0) +#define QMI_M1_WFMT_PREFIX_WIDTH_VALUE_D _u(0x1) +#define QMI_M1_WFMT_PREFIX_WIDTH_VALUE_Q _u(0x2) +// ============================================================================= +// Register : QMI_M1_WCMD +// Description : Command constants used for writes to memory address window 1. +// +// The reset value of the M1_WCMD register is configured to +// support a basic 02h serial write transfer with no additional +// configuration. +#define QMI_M1_WCMD_OFFSET _u(0x00000030) +#define QMI_M1_WCMD_BITS _u(0x0000ffff) +#define QMI_M1_WCMD_RESET _u(0x0000a002) +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WCMD_SUFFIX +// Description : The command suffix bits following the address, if +// Mx_WFMT_SUFFIX_LEN is nonzero. +#define QMI_M1_WCMD_SUFFIX_RESET _u(0xa0) +#define QMI_M1_WCMD_SUFFIX_BITS _u(0x0000ff00) +#define QMI_M1_WCMD_SUFFIX_MSB _u(15) +#define QMI_M1_WCMD_SUFFIX_LSB _u(8) +#define QMI_M1_WCMD_SUFFIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_M1_WCMD_PREFIX +// Description : The command prefix bits to prepend on each new transfer, if +// Mx_WFMT_PREFIX_LEN is nonzero. +#define QMI_M1_WCMD_PREFIX_RESET _u(0x02) +#define QMI_M1_WCMD_PREFIX_BITS _u(0x000000ff) +#define QMI_M1_WCMD_PREFIX_MSB _u(7) +#define QMI_M1_WCMD_PREFIX_LSB _u(0) +#define QMI_M1_WCMD_PREFIX_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS0 +// Description : Configure address translation for XIP virtual addresses +// 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS0_OFFSET _u(0x00000034) +#define QMI_ATRANS0_BITS _u(0x07ff0fff) +#define QMI_ATRANS0_RESET _u(0x04000000) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS0_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS0_SIZE_RESET _u(0x400) +#define QMI_ATRANS0_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS0_SIZE_MSB _u(26) +#define QMI_ATRANS0_SIZE_LSB _u(16) +#define QMI_ATRANS0_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS0_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS0_BASE_RESET _u(0x000) +#define QMI_ATRANS0_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS0_BASE_MSB _u(11) +#define QMI_ATRANS0_BASE_LSB _u(0) +#define QMI_ATRANS0_BASE_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS1 +// Description : Configure address translation for XIP virtual addresses +// 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS1_OFFSET _u(0x00000038) +#define QMI_ATRANS1_BITS _u(0x07ff0fff) +#define QMI_ATRANS1_RESET _u(0x04000400) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS1_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS1_SIZE_RESET _u(0x400) +#define QMI_ATRANS1_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS1_SIZE_MSB _u(26) +#define QMI_ATRANS1_SIZE_LSB _u(16) +#define QMI_ATRANS1_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS1_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS1_BASE_RESET _u(0x400) +#define QMI_ATRANS1_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS1_BASE_MSB _u(11) +#define QMI_ATRANS1_BASE_LSB _u(0) +#define QMI_ATRANS1_BASE_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS2 +// Description : Configure address translation for XIP virtual addresses +// 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS2_OFFSET _u(0x0000003c) +#define QMI_ATRANS2_BITS _u(0x07ff0fff) +#define QMI_ATRANS2_RESET _u(0x04000800) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS2_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS2_SIZE_RESET _u(0x400) +#define QMI_ATRANS2_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS2_SIZE_MSB _u(26) +#define QMI_ATRANS2_SIZE_LSB _u(16) +#define QMI_ATRANS2_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS2_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS2_BASE_RESET _u(0x800) +#define QMI_ATRANS2_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS2_BASE_MSB _u(11) +#define QMI_ATRANS2_BASE_LSB _u(0) +#define QMI_ATRANS2_BASE_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS3 +// Description : Configure address translation for XIP virtual addresses +// 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS3_OFFSET _u(0x00000040) +#define QMI_ATRANS3_BITS _u(0x07ff0fff) +#define QMI_ATRANS3_RESET _u(0x04000c00) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS3_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS3_SIZE_RESET _u(0x400) +#define QMI_ATRANS3_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS3_SIZE_MSB _u(26) +#define QMI_ATRANS3_SIZE_LSB _u(16) +#define QMI_ATRANS3_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS3_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS3_BASE_RESET _u(0xc00) +#define QMI_ATRANS3_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS3_BASE_MSB _u(11) +#define QMI_ATRANS3_BASE_LSB _u(0) +#define QMI_ATRANS3_BASE_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS4 +// Description : Configure address translation for XIP virtual addresses +// 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 +// MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS4_OFFSET _u(0x00000044) +#define QMI_ATRANS4_BITS _u(0x07ff0fff) +#define QMI_ATRANS4_RESET _u(0x04000000) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS4_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS4_SIZE_RESET _u(0x400) +#define QMI_ATRANS4_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS4_SIZE_MSB _u(26) +#define QMI_ATRANS4_SIZE_LSB _u(16) +#define QMI_ATRANS4_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS4_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS4_BASE_RESET _u(0x000) +#define QMI_ATRANS4_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS4_BASE_MSB _u(11) +#define QMI_ATRANS4_BASE_LSB _u(0) +#define QMI_ATRANS4_BASE_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS5 +// Description : Configure address translation for XIP virtual addresses +// 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 +// MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS5_OFFSET _u(0x00000048) +#define QMI_ATRANS5_BITS _u(0x07ff0fff) +#define QMI_ATRANS5_RESET _u(0x04000400) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS5_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS5_SIZE_RESET _u(0x400) +#define QMI_ATRANS5_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS5_SIZE_MSB _u(26) +#define QMI_ATRANS5_SIZE_LSB _u(16) +#define QMI_ATRANS5_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS5_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS5_BASE_RESET _u(0x400) +#define QMI_ATRANS5_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS5_BASE_MSB _u(11) +#define QMI_ATRANS5_BASE_LSB _u(0) +#define QMI_ATRANS5_BASE_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS6 +// Description : Configure address translation for XIP virtual addresses +// 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 +// MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS6_OFFSET _u(0x0000004c) +#define QMI_ATRANS6_BITS _u(0x07ff0fff) +#define QMI_ATRANS6_RESET _u(0x04000800) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS6_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS6_SIZE_RESET _u(0x400) +#define QMI_ATRANS6_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS6_SIZE_MSB _u(26) +#define QMI_ATRANS6_SIZE_LSB _u(16) +#define QMI_ATRANS6_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS6_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS6_BASE_RESET _u(0x800) +#define QMI_ATRANS6_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS6_BASE_MSB _u(11) +#define QMI_ATRANS6_BASE_LSB _u(0) +#define QMI_ATRANS6_BASE_ACCESS "RW" +// ============================================================================= +// Register : QMI_ATRANS7 +// Description : Configure address translation for XIP virtual addresses +// 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 +// MiB). +// +// Address translation allows a program image to be executed in +// place at multiple physical flash addresses (for example, a +// double-buffered flash image for over-the-air updates), without +// the overhead of position-independent code. +// +// At reset, the address translation registers are initialised to +// an identity mapping, so that they can be ignored if address +// translation is not required. +// +// Note that the XIP cache is fully virtually addressed, so a +// cache flush is required after changing the address translation. +#define QMI_ATRANS7_OFFSET _u(0x00000050) +#define QMI_ATRANS7_BITS _u(0x07ff0fff) +#define QMI_ATRANS7_RESET _u(0x04000c00) +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS7_SIZE +// Description : Translation aperture size for this virtual address range, in +// units of 4 kiB (one flash sector). +// +// Bits 21:12 of the virtual address are compared to SIZE. Offsets +// greater than SIZE return a bus error, and do not cause a QSPI +// access. +#define QMI_ATRANS7_SIZE_RESET _u(0x400) +#define QMI_ATRANS7_SIZE_BITS _u(0x07ff0000) +#define QMI_ATRANS7_SIZE_MSB _u(26) +#define QMI_ATRANS7_SIZE_LSB _u(16) +#define QMI_ATRANS7_SIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : QMI_ATRANS7_BASE +// Description : Physical address base for this virtual address range, in units +// of 4 kiB (one flash sector). +// +// Taking a 24-bit virtual address, firstly bits 23:22 (the two +// MSBs) are masked to zero, and then BASE is added to bits 23:12 +// (the upper 12 bits) to form the physical address. Translation +// wraps on a 16 MiB boundary. +#define QMI_ATRANS7_BASE_RESET _u(0xc00) +#define QMI_ATRANS7_BASE_BITS _u(0x00000fff) +#define QMI_ATRANS7_BASE_MSB _u(11) +#define QMI_ATRANS7_BASE_LSB _u(0) +#define QMI_ATRANS7_BASE_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_QMI_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/resets.h b/lib/pico-sdk/rp2350/hardware/regs/resets.h new file mode 100644 index 000000000000..459f24e9eae2 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/resets.h @@ -0,0 +1,641 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : RESETS +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_RESETS_H +#define _HARDWARE_REGS_RESETS_H +// ============================================================================= +// Register : RESETS_RESET +#define RESETS_RESET_OFFSET _u(0x00000000) +#define RESETS_RESET_BITS _u(0x1fffffff) +#define RESETS_RESET_RESET _u(0x1fffffff) +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_USBCTRL +#define RESETS_RESET_USBCTRL_RESET _u(0x1) +#define RESETS_RESET_USBCTRL_BITS _u(0x10000000) +#define RESETS_RESET_USBCTRL_MSB _u(28) +#define RESETS_RESET_USBCTRL_LSB _u(28) +#define RESETS_RESET_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_UART1 +#define RESETS_RESET_UART1_RESET _u(0x1) +#define RESETS_RESET_UART1_BITS _u(0x08000000) +#define RESETS_RESET_UART1_MSB _u(27) +#define RESETS_RESET_UART1_LSB _u(27) +#define RESETS_RESET_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_UART0 +#define RESETS_RESET_UART0_RESET _u(0x1) +#define RESETS_RESET_UART0_BITS _u(0x04000000) +#define RESETS_RESET_UART0_MSB _u(26) +#define RESETS_RESET_UART0_LSB _u(26) +#define RESETS_RESET_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_TRNG +#define RESETS_RESET_TRNG_RESET _u(0x1) +#define RESETS_RESET_TRNG_BITS _u(0x02000000) +#define RESETS_RESET_TRNG_MSB _u(25) +#define RESETS_RESET_TRNG_LSB _u(25) +#define RESETS_RESET_TRNG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_TIMER1 +#define RESETS_RESET_TIMER1_RESET _u(0x1) +#define RESETS_RESET_TIMER1_BITS _u(0x01000000) +#define RESETS_RESET_TIMER1_MSB _u(24) +#define RESETS_RESET_TIMER1_LSB _u(24) +#define RESETS_RESET_TIMER1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_TIMER0 +#define RESETS_RESET_TIMER0_RESET _u(0x1) +#define RESETS_RESET_TIMER0_BITS _u(0x00800000) +#define RESETS_RESET_TIMER0_MSB _u(23) +#define RESETS_RESET_TIMER0_LSB _u(23) +#define RESETS_RESET_TIMER0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_TBMAN +#define RESETS_RESET_TBMAN_RESET _u(0x1) +#define RESETS_RESET_TBMAN_BITS _u(0x00400000) +#define RESETS_RESET_TBMAN_MSB _u(22) +#define RESETS_RESET_TBMAN_LSB _u(22) +#define RESETS_RESET_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SYSINFO +#define RESETS_RESET_SYSINFO_RESET _u(0x1) +#define RESETS_RESET_SYSINFO_BITS _u(0x00200000) +#define RESETS_RESET_SYSINFO_MSB _u(21) +#define RESETS_RESET_SYSINFO_LSB _u(21) +#define RESETS_RESET_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SYSCFG +#define RESETS_RESET_SYSCFG_RESET _u(0x1) +#define RESETS_RESET_SYSCFG_BITS _u(0x00100000) +#define RESETS_RESET_SYSCFG_MSB _u(20) +#define RESETS_RESET_SYSCFG_LSB _u(20) +#define RESETS_RESET_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SPI1 +#define RESETS_RESET_SPI1_RESET _u(0x1) +#define RESETS_RESET_SPI1_BITS _u(0x00080000) +#define RESETS_RESET_SPI1_MSB _u(19) +#define RESETS_RESET_SPI1_LSB _u(19) +#define RESETS_RESET_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SPI0 +#define RESETS_RESET_SPI0_RESET _u(0x1) +#define RESETS_RESET_SPI0_BITS _u(0x00040000) +#define RESETS_RESET_SPI0_MSB _u(18) +#define RESETS_RESET_SPI0_LSB _u(18) +#define RESETS_RESET_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_SHA256 +#define RESETS_RESET_SHA256_RESET _u(0x1) +#define RESETS_RESET_SHA256_BITS _u(0x00020000) +#define RESETS_RESET_SHA256_MSB _u(17) +#define RESETS_RESET_SHA256_LSB _u(17) +#define RESETS_RESET_SHA256_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PWM +#define RESETS_RESET_PWM_RESET _u(0x1) +#define RESETS_RESET_PWM_BITS _u(0x00010000) +#define RESETS_RESET_PWM_MSB _u(16) +#define RESETS_RESET_PWM_LSB _u(16) +#define RESETS_RESET_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PLL_USB +#define RESETS_RESET_PLL_USB_RESET _u(0x1) +#define RESETS_RESET_PLL_USB_BITS _u(0x00008000) +#define RESETS_RESET_PLL_USB_MSB _u(15) +#define RESETS_RESET_PLL_USB_LSB _u(15) +#define RESETS_RESET_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PLL_SYS +#define RESETS_RESET_PLL_SYS_RESET _u(0x1) +#define RESETS_RESET_PLL_SYS_BITS _u(0x00004000) +#define RESETS_RESET_PLL_SYS_MSB _u(14) +#define RESETS_RESET_PLL_SYS_LSB _u(14) +#define RESETS_RESET_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PIO2 +#define RESETS_RESET_PIO2_RESET _u(0x1) +#define RESETS_RESET_PIO2_BITS _u(0x00002000) +#define RESETS_RESET_PIO2_MSB _u(13) +#define RESETS_RESET_PIO2_LSB _u(13) +#define RESETS_RESET_PIO2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PIO1 +#define RESETS_RESET_PIO1_RESET _u(0x1) +#define RESETS_RESET_PIO1_BITS _u(0x00001000) +#define RESETS_RESET_PIO1_MSB _u(12) +#define RESETS_RESET_PIO1_LSB _u(12) +#define RESETS_RESET_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PIO0 +#define RESETS_RESET_PIO0_RESET _u(0x1) +#define RESETS_RESET_PIO0_BITS _u(0x00000800) +#define RESETS_RESET_PIO0_MSB _u(11) +#define RESETS_RESET_PIO0_LSB _u(11) +#define RESETS_RESET_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PADS_QSPI +#define RESETS_RESET_PADS_QSPI_RESET _u(0x1) +#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000400) +#define RESETS_RESET_PADS_QSPI_MSB _u(10) +#define RESETS_RESET_PADS_QSPI_LSB _u(10) +#define RESETS_RESET_PADS_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_PADS_BANK0 +#define RESETS_RESET_PADS_BANK0_RESET _u(0x1) +#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000200) +#define RESETS_RESET_PADS_BANK0_MSB _u(9) +#define RESETS_RESET_PADS_BANK0_LSB _u(9) +#define RESETS_RESET_PADS_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_JTAG +#define RESETS_RESET_JTAG_RESET _u(0x1) +#define RESETS_RESET_JTAG_BITS _u(0x00000100) +#define RESETS_RESET_JTAG_MSB _u(8) +#define RESETS_RESET_JTAG_LSB _u(8) +#define RESETS_RESET_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_IO_QSPI +#define RESETS_RESET_IO_QSPI_RESET _u(0x1) +#define RESETS_RESET_IO_QSPI_BITS _u(0x00000080) +#define RESETS_RESET_IO_QSPI_MSB _u(7) +#define RESETS_RESET_IO_QSPI_LSB _u(7) +#define RESETS_RESET_IO_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_IO_BANK0 +#define RESETS_RESET_IO_BANK0_RESET _u(0x1) +#define RESETS_RESET_IO_BANK0_BITS _u(0x00000040) +#define RESETS_RESET_IO_BANK0_MSB _u(6) +#define RESETS_RESET_IO_BANK0_LSB _u(6) +#define RESETS_RESET_IO_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_I2C1 +#define RESETS_RESET_I2C1_RESET _u(0x1) +#define RESETS_RESET_I2C1_BITS _u(0x00000020) +#define RESETS_RESET_I2C1_MSB _u(5) +#define RESETS_RESET_I2C1_LSB _u(5) +#define RESETS_RESET_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_I2C0 +#define RESETS_RESET_I2C0_RESET _u(0x1) +#define RESETS_RESET_I2C0_BITS _u(0x00000010) +#define RESETS_RESET_I2C0_MSB _u(4) +#define RESETS_RESET_I2C0_LSB _u(4) +#define RESETS_RESET_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_HSTX +#define RESETS_RESET_HSTX_RESET _u(0x1) +#define RESETS_RESET_HSTX_BITS _u(0x00000008) +#define RESETS_RESET_HSTX_MSB _u(3) +#define RESETS_RESET_HSTX_LSB _u(3) +#define RESETS_RESET_HSTX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DMA +#define RESETS_RESET_DMA_RESET _u(0x1) +#define RESETS_RESET_DMA_BITS _u(0x00000004) +#define RESETS_RESET_DMA_MSB _u(2) +#define RESETS_RESET_DMA_LSB _u(2) +#define RESETS_RESET_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_BUSCTRL +#define RESETS_RESET_BUSCTRL_RESET _u(0x1) +#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002) +#define RESETS_RESET_BUSCTRL_MSB _u(1) +#define RESETS_RESET_BUSCTRL_LSB _u(1) +#define RESETS_RESET_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_ADC +#define RESETS_RESET_ADC_RESET _u(0x1) +#define RESETS_RESET_ADC_BITS _u(0x00000001) +#define RESETS_RESET_ADC_MSB _u(0) +#define RESETS_RESET_ADC_LSB _u(0) +#define RESETS_RESET_ADC_ACCESS "RW" +// ============================================================================= +// Register : RESETS_WDSEL +#define RESETS_WDSEL_OFFSET _u(0x00000004) +#define RESETS_WDSEL_BITS _u(0x1fffffff) +#define RESETS_WDSEL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_USBCTRL +#define RESETS_WDSEL_USBCTRL_RESET _u(0x0) +#define RESETS_WDSEL_USBCTRL_BITS _u(0x10000000) +#define RESETS_WDSEL_USBCTRL_MSB _u(28) +#define RESETS_WDSEL_USBCTRL_LSB _u(28) +#define RESETS_WDSEL_USBCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_UART1 +#define RESETS_WDSEL_UART1_RESET _u(0x0) +#define RESETS_WDSEL_UART1_BITS _u(0x08000000) +#define RESETS_WDSEL_UART1_MSB _u(27) +#define RESETS_WDSEL_UART1_LSB _u(27) +#define RESETS_WDSEL_UART1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_UART0 +#define RESETS_WDSEL_UART0_RESET _u(0x0) +#define RESETS_WDSEL_UART0_BITS _u(0x04000000) +#define RESETS_WDSEL_UART0_MSB _u(26) +#define RESETS_WDSEL_UART0_LSB _u(26) +#define RESETS_WDSEL_UART0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_TRNG +#define RESETS_WDSEL_TRNG_RESET _u(0x0) +#define RESETS_WDSEL_TRNG_BITS _u(0x02000000) +#define RESETS_WDSEL_TRNG_MSB _u(25) +#define RESETS_WDSEL_TRNG_LSB _u(25) +#define RESETS_WDSEL_TRNG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_TIMER1 +#define RESETS_WDSEL_TIMER1_RESET _u(0x0) +#define RESETS_WDSEL_TIMER1_BITS _u(0x01000000) +#define RESETS_WDSEL_TIMER1_MSB _u(24) +#define RESETS_WDSEL_TIMER1_LSB _u(24) +#define RESETS_WDSEL_TIMER1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_TIMER0 +#define RESETS_WDSEL_TIMER0_RESET _u(0x0) +#define RESETS_WDSEL_TIMER0_BITS _u(0x00800000) +#define RESETS_WDSEL_TIMER0_MSB _u(23) +#define RESETS_WDSEL_TIMER0_LSB _u(23) +#define RESETS_WDSEL_TIMER0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_TBMAN +#define RESETS_WDSEL_TBMAN_RESET _u(0x0) +#define RESETS_WDSEL_TBMAN_BITS _u(0x00400000) +#define RESETS_WDSEL_TBMAN_MSB _u(22) +#define RESETS_WDSEL_TBMAN_LSB _u(22) +#define RESETS_WDSEL_TBMAN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SYSINFO +#define RESETS_WDSEL_SYSINFO_RESET _u(0x0) +#define RESETS_WDSEL_SYSINFO_BITS _u(0x00200000) +#define RESETS_WDSEL_SYSINFO_MSB _u(21) +#define RESETS_WDSEL_SYSINFO_LSB _u(21) +#define RESETS_WDSEL_SYSINFO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SYSCFG +#define RESETS_WDSEL_SYSCFG_RESET _u(0x0) +#define RESETS_WDSEL_SYSCFG_BITS _u(0x00100000) +#define RESETS_WDSEL_SYSCFG_MSB _u(20) +#define RESETS_WDSEL_SYSCFG_LSB _u(20) +#define RESETS_WDSEL_SYSCFG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SPI1 +#define RESETS_WDSEL_SPI1_RESET _u(0x0) +#define RESETS_WDSEL_SPI1_BITS _u(0x00080000) +#define RESETS_WDSEL_SPI1_MSB _u(19) +#define RESETS_WDSEL_SPI1_LSB _u(19) +#define RESETS_WDSEL_SPI1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SPI0 +#define RESETS_WDSEL_SPI0_RESET _u(0x0) +#define RESETS_WDSEL_SPI0_BITS _u(0x00040000) +#define RESETS_WDSEL_SPI0_MSB _u(18) +#define RESETS_WDSEL_SPI0_LSB _u(18) +#define RESETS_WDSEL_SPI0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_SHA256 +#define RESETS_WDSEL_SHA256_RESET _u(0x0) +#define RESETS_WDSEL_SHA256_BITS _u(0x00020000) +#define RESETS_WDSEL_SHA256_MSB _u(17) +#define RESETS_WDSEL_SHA256_LSB _u(17) +#define RESETS_WDSEL_SHA256_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PWM +#define RESETS_WDSEL_PWM_RESET _u(0x0) +#define RESETS_WDSEL_PWM_BITS _u(0x00010000) +#define RESETS_WDSEL_PWM_MSB _u(16) +#define RESETS_WDSEL_PWM_LSB _u(16) +#define RESETS_WDSEL_PWM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PLL_USB +#define RESETS_WDSEL_PLL_USB_RESET _u(0x0) +#define RESETS_WDSEL_PLL_USB_BITS _u(0x00008000) +#define RESETS_WDSEL_PLL_USB_MSB _u(15) +#define RESETS_WDSEL_PLL_USB_LSB _u(15) +#define RESETS_WDSEL_PLL_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PLL_SYS +#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0) +#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00004000) +#define RESETS_WDSEL_PLL_SYS_MSB _u(14) +#define RESETS_WDSEL_PLL_SYS_LSB _u(14) +#define RESETS_WDSEL_PLL_SYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PIO2 +#define RESETS_WDSEL_PIO2_RESET _u(0x0) +#define RESETS_WDSEL_PIO2_BITS _u(0x00002000) +#define RESETS_WDSEL_PIO2_MSB _u(13) +#define RESETS_WDSEL_PIO2_LSB _u(13) +#define RESETS_WDSEL_PIO2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PIO1 +#define RESETS_WDSEL_PIO1_RESET _u(0x0) +#define RESETS_WDSEL_PIO1_BITS _u(0x00001000) +#define RESETS_WDSEL_PIO1_MSB _u(12) +#define RESETS_WDSEL_PIO1_LSB _u(12) +#define RESETS_WDSEL_PIO1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PIO0 +#define RESETS_WDSEL_PIO0_RESET _u(0x0) +#define RESETS_WDSEL_PIO0_BITS _u(0x00000800) +#define RESETS_WDSEL_PIO0_MSB _u(11) +#define RESETS_WDSEL_PIO0_LSB _u(11) +#define RESETS_WDSEL_PIO0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PADS_QSPI +#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0) +#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000400) +#define RESETS_WDSEL_PADS_QSPI_MSB _u(10) +#define RESETS_WDSEL_PADS_QSPI_LSB _u(10) +#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_PADS_BANK0 +#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0) +#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000200) +#define RESETS_WDSEL_PADS_BANK0_MSB _u(9) +#define RESETS_WDSEL_PADS_BANK0_LSB _u(9) +#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_JTAG +#define RESETS_WDSEL_JTAG_RESET _u(0x0) +#define RESETS_WDSEL_JTAG_BITS _u(0x00000100) +#define RESETS_WDSEL_JTAG_MSB _u(8) +#define RESETS_WDSEL_JTAG_LSB _u(8) +#define RESETS_WDSEL_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_IO_QSPI +#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0) +#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000080) +#define RESETS_WDSEL_IO_QSPI_MSB _u(7) +#define RESETS_WDSEL_IO_QSPI_LSB _u(7) +#define RESETS_WDSEL_IO_QSPI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_IO_BANK0 +#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0) +#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000040) +#define RESETS_WDSEL_IO_BANK0_MSB _u(6) +#define RESETS_WDSEL_IO_BANK0_LSB _u(6) +#define RESETS_WDSEL_IO_BANK0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_I2C1 +#define RESETS_WDSEL_I2C1_RESET _u(0x0) +#define RESETS_WDSEL_I2C1_BITS _u(0x00000020) +#define RESETS_WDSEL_I2C1_MSB _u(5) +#define RESETS_WDSEL_I2C1_LSB _u(5) +#define RESETS_WDSEL_I2C1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_I2C0 +#define RESETS_WDSEL_I2C0_RESET _u(0x0) +#define RESETS_WDSEL_I2C0_BITS _u(0x00000010) +#define RESETS_WDSEL_I2C0_MSB _u(4) +#define RESETS_WDSEL_I2C0_LSB _u(4) +#define RESETS_WDSEL_I2C0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_HSTX +#define RESETS_WDSEL_HSTX_RESET _u(0x0) +#define RESETS_WDSEL_HSTX_BITS _u(0x00000008) +#define RESETS_WDSEL_HSTX_MSB _u(3) +#define RESETS_WDSEL_HSTX_LSB _u(3) +#define RESETS_WDSEL_HSTX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_DMA +#define RESETS_WDSEL_DMA_RESET _u(0x0) +#define RESETS_WDSEL_DMA_BITS _u(0x00000004) +#define RESETS_WDSEL_DMA_MSB _u(2) +#define RESETS_WDSEL_DMA_LSB _u(2) +#define RESETS_WDSEL_DMA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_BUSCTRL +#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0) +#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002) +#define RESETS_WDSEL_BUSCTRL_MSB _u(1) +#define RESETS_WDSEL_BUSCTRL_LSB _u(1) +#define RESETS_WDSEL_BUSCTRL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RESETS_WDSEL_ADC +#define RESETS_WDSEL_ADC_RESET _u(0x0) +#define RESETS_WDSEL_ADC_BITS _u(0x00000001) +#define RESETS_WDSEL_ADC_MSB _u(0) +#define RESETS_WDSEL_ADC_LSB _u(0) +#define RESETS_WDSEL_ADC_ACCESS "RW" +// ============================================================================= +// Register : RESETS_RESET_DONE +#define RESETS_RESET_DONE_OFFSET _u(0x00000008) +#define RESETS_RESET_DONE_BITS _u(0x1fffffff) +#define RESETS_RESET_DONE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_USBCTRL +#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0) +#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x10000000) +#define RESETS_RESET_DONE_USBCTRL_MSB _u(28) +#define RESETS_RESET_DONE_USBCTRL_LSB _u(28) +#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_UART1 +#define RESETS_RESET_DONE_UART1_RESET _u(0x0) +#define RESETS_RESET_DONE_UART1_BITS _u(0x08000000) +#define RESETS_RESET_DONE_UART1_MSB _u(27) +#define RESETS_RESET_DONE_UART1_LSB _u(27) +#define RESETS_RESET_DONE_UART1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_UART0 +#define RESETS_RESET_DONE_UART0_RESET _u(0x0) +#define RESETS_RESET_DONE_UART0_BITS _u(0x04000000) +#define RESETS_RESET_DONE_UART0_MSB _u(26) +#define RESETS_RESET_DONE_UART0_LSB _u(26) +#define RESETS_RESET_DONE_UART0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_TRNG +#define RESETS_RESET_DONE_TRNG_RESET _u(0x0) +#define RESETS_RESET_DONE_TRNG_BITS _u(0x02000000) +#define RESETS_RESET_DONE_TRNG_MSB _u(25) +#define RESETS_RESET_DONE_TRNG_LSB _u(25) +#define RESETS_RESET_DONE_TRNG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_TIMER1 +#define RESETS_RESET_DONE_TIMER1_RESET _u(0x0) +#define RESETS_RESET_DONE_TIMER1_BITS _u(0x01000000) +#define RESETS_RESET_DONE_TIMER1_MSB _u(24) +#define RESETS_RESET_DONE_TIMER1_LSB _u(24) +#define RESETS_RESET_DONE_TIMER1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_TIMER0 +#define RESETS_RESET_DONE_TIMER0_RESET _u(0x0) +#define RESETS_RESET_DONE_TIMER0_BITS _u(0x00800000) +#define RESETS_RESET_DONE_TIMER0_MSB _u(23) +#define RESETS_RESET_DONE_TIMER0_LSB _u(23) +#define RESETS_RESET_DONE_TIMER0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_TBMAN +#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0) +#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00400000) +#define RESETS_RESET_DONE_TBMAN_MSB _u(22) +#define RESETS_RESET_DONE_TBMAN_LSB _u(22) +#define RESETS_RESET_DONE_TBMAN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SYSINFO +#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0) +#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00200000) +#define RESETS_RESET_DONE_SYSINFO_MSB _u(21) +#define RESETS_RESET_DONE_SYSINFO_LSB _u(21) +#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SYSCFG +#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0) +#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00100000) +#define RESETS_RESET_DONE_SYSCFG_MSB _u(20) +#define RESETS_RESET_DONE_SYSCFG_LSB _u(20) +#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SPI1 +#define RESETS_RESET_DONE_SPI1_RESET _u(0x0) +#define RESETS_RESET_DONE_SPI1_BITS _u(0x00080000) +#define RESETS_RESET_DONE_SPI1_MSB _u(19) +#define RESETS_RESET_DONE_SPI1_LSB _u(19) +#define RESETS_RESET_DONE_SPI1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SPI0 +#define RESETS_RESET_DONE_SPI0_RESET _u(0x0) +#define RESETS_RESET_DONE_SPI0_BITS _u(0x00040000) +#define RESETS_RESET_DONE_SPI0_MSB _u(18) +#define RESETS_RESET_DONE_SPI0_LSB _u(18) +#define RESETS_RESET_DONE_SPI0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_SHA256 +#define RESETS_RESET_DONE_SHA256_RESET _u(0x0) +#define RESETS_RESET_DONE_SHA256_BITS _u(0x00020000) +#define RESETS_RESET_DONE_SHA256_MSB _u(17) +#define RESETS_RESET_DONE_SHA256_LSB _u(17) +#define RESETS_RESET_DONE_SHA256_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PWM +#define RESETS_RESET_DONE_PWM_RESET _u(0x0) +#define RESETS_RESET_DONE_PWM_BITS _u(0x00010000) +#define RESETS_RESET_DONE_PWM_MSB _u(16) +#define RESETS_RESET_DONE_PWM_LSB _u(16) +#define RESETS_RESET_DONE_PWM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PLL_USB +#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0) +#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00008000) +#define RESETS_RESET_DONE_PLL_USB_MSB _u(15) +#define RESETS_RESET_DONE_PLL_USB_LSB _u(15) +#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PLL_SYS +#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0) +#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00004000) +#define RESETS_RESET_DONE_PLL_SYS_MSB _u(14) +#define RESETS_RESET_DONE_PLL_SYS_LSB _u(14) +#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PIO2 +#define RESETS_RESET_DONE_PIO2_RESET _u(0x0) +#define RESETS_RESET_DONE_PIO2_BITS _u(0x00002000) +#define RESETS_RESET_DONE_PIO2_MSB _u(13) +#define RESETS_RESET_DONE_PIO2_LSB _u(13) +#define RESETS_RESET_DONE_PIO2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PIO1 +#define RESETS_RESET_DONE_PIO1_RESET _u(0x0) +#define RESETS_RESET_DONE_PIO1_BITS _u(0x00001000) +#define RESETS_RESET_DONE_PIO1_MSB _u(12) +#define RESETS_RESET_DONE_PIO1_LSB _u(12) +#define RESETS_RESET_DONE_PIO1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PIO0 +#define RESETS_RESET_DONE_PIO0_RESET _u(0x0) +#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000800) +#define RESETS_RESET_DONE_PIO0_MSB _u(11) +#define RESETS_RESET_DONE_PIO0_LSB _u(11) +#define RESETS_RESET_DONE_PIO0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PADS_QSPI +#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0) +#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000400) +#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(10) +#define RESETS_RESET_DONE_PADS_QSPI_LSB _u(10) +#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_PADS_BANK0 +#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0) +#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000200) +#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(9) +#define RESETS_RESET_DONE_PADS_BANK0_LSB _u(9) +#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_JTAG +#define RESETS_RESET_DONE_JTAG_RESET _u(0x0) +#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000100) +#define RESETS_RESET_DONE_JTAG_MSB _u(8) +#define RESETS_RESET_DONE_JTAG_LSB _u(8) +#define RESETS_RESET_DONE_JTAG_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_IO_QSPI +#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0) +#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000080) +#define RESETS_RESET_DONE_IO_QSPI_MSB _u(7) +#define RESETS_RESET_DONE_IO_QSPI_LSB _u(7) +#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_IO_BANK0 +#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0) +#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000040) +#define RESETS_RESET_DONE_IO_BANK0_MSB _u(6) +#define RESETS_RESET_DONE_IO_BANK0_LSB _u(6) +#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_I2C1 +#define RESETS_RESET_DONE_I2C1_RESET _u(0x0) +#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000020) +#define RESETS_RESET_DONE_I2C1_MSB _u(5) +#define RESETS_RESET_DONE_I2C1_LSB _u(5) +#define RESETS_RESET_DONE_I2C1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_I2C0 +#define RESETS_RESET_DONE_I2C0_RESET _u(0x0) +#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000010) +#define RESETS_RESET_DONE_I2C0_MSB _u(4) +#define RESETS_RESET_DONE_I2C0_LSB _u(4) +#define RESETS_RESET_DONE_I2C0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_HSTX +#define RESETS_RESET_DONE_HSTX_RESET _u(0x0) +#define RESETS_RESET_DONE_HSTX_BITS _u(0x00000008) +#define RESETS_RESET_DONE_HSTX_MSB _u(3) +#define RESETS_RESET_DONE_HSTX_LSB _u(3) +#define RESETS_RESET_DONE_HSTX_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_DMA +#define RESETS_RESET_DONE_DMA_RESET _u(0x0) +#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004) +#define RESETS_RESET_DONE_DMA_MSB _u(2) +#define RESETS_RESET_DONE_DMA_LSB _u(2) +#define RESETS_RESET_DONE_DMA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_BUSCTRL +#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0) +#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002) +#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1) +#define RESETS_RESET_DONE_BUSCTRL_LSB _u(1) +#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RESETS_RESET_DONE_ADC +#define RESETS_RESET_DONE_ADC_RESET _u(0x0) +#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001) +#define RESETS_RESET_DONE_ADC_MSB _u(0) +#define RESETS_RESET_DONE_ADC_LSB _u(0) +#define RESETS_RESET_DONE_ADC_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_RESETS_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/riscv_dm.h b/lib/pico-sdk/rp2350/hardware/regs/riscv_dm.h new file mode 100644 index 000000000000..bbf64a2963ca --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/riscv_dm.h @@ -0,0 +1,1025 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : RISCV_DM +// Version : 1 +// Bus type : apb +// Description : RISC-V Debug module registers (Hazard3 subset only). Read- +// only information fields (such as dmstatus.version) are +// listed here with the values they have on the RP2350 +// instantiation of Hazard3. +// ============================================================================= +#ifndef _HARDWARE_REGS_RISCV_DM_H +#define _HARDWARE_REGS_RISCV_DM_H +// ============================================================================= +// Register : RISCV_DM_DATA0 +// Description : data0 through data11 are basic read/write registers that may be +// read or changed by abstract commands. abstractcs.datacount +// indicates how many of them are implemented, starting at data0, +// counting up. +// +// Accessing these registers while an abstract command is +// executing causes abstractcs.cmderr to be set to 1 (busy) if it +// is 0. +// +// Attempts to write them while abstractcs.busy is set does not +// change their value. +// +// The values in these registers may not be preserved after an +// abstract command is executed. The only guarantees on their +// contents are the ones offered by the command in question. If +// the command fails, no assumptions can be made about the +// contents of these registers. +// +// (Note: Hazard3 implements data0 only.) +#define RISCV_DM_DATA0_OFFSET _u(0x00000010) +#define RISCV_DM_DATA0_BITS _u(0xffffffff) +#define RISCV_DM_DATA0_RESET _u(0x00000000) +#define RISCV_DM_DATA0_MSB _u(31) +#define RISCV_DM_DATA0_LSB _u(0) +#define RISCV_DM_DATA0_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_DMCONTROL +// Description : This register controls the overall Debug Module as well as the +// currently selected harts, as defined in hasel. +#define RISCV_DM_DMCONTROL_OFFSET _u(0x00000040) +#define RISCV_DM_DMCONTROL_BITS _u(0xf7ffffcf) +#define RISCV_DM_DMCONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_HALTREQ +// Description : Writing 0 clears the halt request bit for all currently +// selected harts. This may cancel outstanding halt requests for +// those harts. +// +// Writing 1 sets the halt request bit for all currently selected +// harts. Running harts will halt whenever their halt request bit +// is set. +// +// Writes apply to the new value of hartsel and hasel. +#define RISCV_DM_DMCONTROL_HALTREQ_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_HALTREQ_BITS _u(0x80000000) +#define RISCV_DM_DMCONTROL_HALTREQ_MSB _u(31) +#define RISCV_DM_DMCONTROL_HALTREQ_LSB _u(31) +#define RISCV_DM_DMCONTROL_HALTREQ_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_RESUMEREQ +// Description : Writing 1 causes the currently selected harts to resume once, +// if they are halted when the write occurs. It also clears the +// resume ack bit for those harts. +// +// resumereq is ignored if haltreq is set. +// +// Writes apply to the new value of hartsel and hasel. +#define RISCV_DM_DMCONTROL_RESUMEREQ_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_RESUMEREQ_BITS _u(0x40000000) +#define RISCV_DM_DMCONTROL_RESUMEREQ_MSB _u(30) +#define RISCV_DM_DMCONTROL_RESUMEREQ_LSB _u(30) +#define RISCV_DM_DMCONTROL_RESUMEREQ_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_HARTRESET +// Description : This optional field writes the reset bit for all the currently +// selected harts. To perform a reset the debugger writes 1, and +// then writes 0 to deassert the reset signal. +// +// While this bit is 1, the debugger must not change which harts +// are selected. +// +// Writes apply to the new value of hartsel and hasel. +// +// (The exact behaviour of this field is implementation-defined: +// on RP2350 it (triggers a local reset of the selected core(s) +// only.) +#define RISCV_DM_DMCONTROL_HARTRESET_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_HARTRESET_BITS _u(0x20000000) +#define RISCV_DM_DMCONTROL_HARTRESET_MSB _u(29) +#define RISCV_DM_DMCONTROL_HARTRESET_LSB _u(29) +#define RISCV_DM_DMCONTROL_HARTRESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_ACKHAVERESET +// Description : 0: No effect. +// +// 1: Clears havereset for any selected harts. +// +// Writes apply to the new value of hartsel and hasel. +#define RISCV_DM_DMCONTROL_ACKHAVERESET_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_ACKHAVERESET_BITS _u(0x10000000) +#define RISCV_DM_DMCONTROL_ACKHAVERESET_MSB _u(28) +#define RISCV_DM_DMCONTROL_ACKHAVERESET_LSB _u(28) +#define RISCV_DM_DMCONTROL_ACKHAVERESET_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_HASEL +// Description : Selects the definition of currently selected harts. +// +// 0: There is a single currently selected hart, that is selected +// by hartsel. +// +// 1: There may be multiple currently selected harts – the hart +// selected by hartsel, plus those selected by the hart array mask +// register. +// +// Hazard3 does support the hart array mask. +#define RISCV_DM_DMCONTROL_HASEL_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_HASEL_BITS _u(0x04000000) +#define RISCV_DM_DMCONTROL_HASEL_MSB _u(26) +#define RISCV_DM_DMCONTROL_HASEL_LSB _u(26) +#define RISCV_DM_DMCONTROL_HASEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_HARTSELLO +// Description : The low 10 bits of hartsel: the DM-specific index of the hart +// to select. This hart is always part of the currently selected +// harts. +// +// On RP2350, since there are only two cores (with one hart each), +// only the least-significant bit is writable. The others are tied +// to 0. +#define RISCV_DM_DMCONTROL_HARTSELLO_RESET _u(0x000) +#define RISCV_DM_DMCONTROL_HARTSELLO_BITS _u(0x03ff0000) +#define RISCV_DM_DMCONTROL_HARTSELLO_MSB _u(25) +#define RISCV_DM_DMCONTROL_HARTSELLO_LSB _u(16) +#define RISCV_DM_DMCONTROL_HARTSELLO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_HARTSELHI +// Description : The high 10 bits of hartsel: the DM-specific index of the hart +// to select. This hart is always part of the currently selected +// harts. +// +// On Hazard3 this field is always tied to all-zeroes. +#define RISCV_DM_DMCONTROL_HARTSELHI_RESET _u(0x000) +#define RISCV_DM_DMCONTROL_HARTSELHI_BITS _u(0x0000ffc0) +#define RISCV_DM_DMCONTROL_HARTSELHI_MSB _u(15) +#define RISCV_DM_DMCONTROL_HARTSELHI_LSB _u(6) +#define RISCV_DM_DMCONTROL_HARTSELHI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_SETRESETHALTREQ +// Description : This optional field writes the halt-on-reset request bit for +// all currently selected harts, unless clrresethaltreq is +// simultaneously set to 1. +// +// When set to 1, each selected hart will halt upon the next +// deassertion of its reset. The halt-on-reset request bit is not +// automatically cleared. The debugger must write to +// clrresethaltreq to clear it. +// +// Writes apply to the new value of hartsel and hasel. +#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_BITS _u(0x00000008) +#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_MSB _u(3) +#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_LSB _u(3) +#define RISCV_DM_DMCONTROL_SETRESETHALTREQ_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_CLRRESETHALTREQ +// Description : This optional field clears the halt-on-reset request bit for +// all currently selected harts. +// +// Writes apply to the new value of hartsel and hasel. +#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_BITS _u(0x00000004) +#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_MSB _u(2) +#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_LSB _u(2) +#define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_NDMRESET +// Description : This bit controls the reset signal from the DM to the rest of +// the system. The signal should reset every part of the system, +// including every hart, except for the DM and any logic required +// to access the DM. To perform a system reset the debugger writes +// 1, and then writes 0 to deassert the reset. +// +// On RP2350 this performs a cold reset, the equivalent of a +// watchdog reset with all WDSEL bits set. This includes both +// cores and all peripherals. +#define RISCV_DM_DMCONTROL_NDMRESET_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_NDMRESET_BITS _u(0x00000002) +#define RISCV_DM_DMCONTROL_NDMRESET_MSB _u(1) +#define RISCV_DM_DMCONTROL_NDMRESET_LSB _u(1) +#define RISCV_DM_DMCONTROL_NDMRESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMCONTROL_DMACTIVE +// Description : This bit serves as a reset signal for the Debug Module itself. +// +// 0: The module’s state, including authentication mechanism, +// takes its reset values (the dmactive bit is the only bit which +// can be written to something other than its reset value). +// +// 1: The module functions normally. +// +// No other mechanism should exist that may result in resetting +// the Debug Module after power up, with the possible (but not +// recommended) exception of a global reset signal that resets the +// entire platform. +// +// (On RP2350, the Debug Module is reset by a power-on reset, a +// brownout reset, the RUN pin, and a rescue reset.) +// +// A debugger may pulse this bit low to get the Debug Module into +// a known state. +#define RISCV_DM_DMCONTROL_DMACTIVE_RESET _u(0x0) +#define RISCV_DM_DMCONTROL_DMACTIVE_BITS _u(0x00000001) +#define RISCV_DM_DMCONTROL_DMACTIVE_MSB _u(0) +#define RISCV_DM_DMCONTROL_DMACTIVE_LSB _u(0) +#define RISCV_DM_DMCONTROL_DMACTIVE_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_DMSTATUS +// Description : This register reports status for the overall Debug Module as +// well as the currently selected harts, as defined in hasel. Its +// address will not change in the future, because it contains +// version. +// +// This entire register is read-only. +#define RISCV_DM_DMSTATUS_OFFSET _u(0x00000044) +#define RISCV_DM_DMSTATUS_BITS _u(0x004fffff) +#define RISCV_DM_DMSTATUS_RESET _u(0x004000a2) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_IMPEBREAK +// Description : If 1, then there is an implicit ebreak instruction at the non- +// existent word immediately after the Program Buffer. This saves +// the debugger from having to write the ebreak itself, and allows +// the Program Buffer to be one word smaller. +#define RISCV_DM_DMSTATUS_IMPEBREAK_RESET _u(0x1) +#define RISCV_DM_DMSTATUS_IMPEBREAK_BITS _u(0x00400000) +#define RISCV_DM_DMSTATUS_IMPEBREAK_MSB _u(22) +#define RISCV_DM_DMSTATUS_IMPEBREAK_LSB _u(22) +#define RISCV_DM_DMSTATUS_IMPEBREAK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ALLHAVERESET +// Description : This field is 1 when all currently selected harts have been +// reset and reset has not been acknowledged for any of them. +#define RISCV_DM_DMSTATUS_ALLHAVERESET_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ALLHAVERESET_BITS _u(0x00080000) +#define RISCV_DM_DMSTATUS_ALLHAVERESET_MSB _u(19) +#define RISCV_DM_DMSTATUS_ALLHAVERESET_LSB _u(19) +#define RISCV_DM_DMSTATUS_ALLHAVERESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ANYHAVERESET +// Description : This field is 1 when at least one currently selected hart has +// been reset and reset has not been acknowledged for that hart. +#define RISCV_DM_DMSTATUS_ANYHAVERESET_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ANYHAVERESET_BITS _u(0x00040000) +#define RISCV_DM_DMSTATUS_ANYHAVERESET_MSB _u(18) +#define RISCV_DM_DMSTATUS_ANYHAVERESET_LSB _u(18) +#define RISCV_DM_DMSTATUS_ANYHAVERESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ALLRESUMEACK +// Description : This field is 1 when all currently selected harts have +// acknowledged their last resume request. +#define RISCV_DM_DMSTATUS_ALLRESUMEACK_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ALLRESUMEACK_BITS _u(0x00020000) +#define RISCV_DM_DMSTATUS_ALLRESUMEACK_MSB _u(17) +#define RISCV_DM_DMSTATUS_ALLRESUMEACK_LSB _u(17) +#define RISCV_DM_DMSTATUS_ALLRESUMEACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ANYRESUMEACK +// Description : This field is 1 when any currently selected hart has +// acknowledged its last resume request. +#define RISCV_DM_DMSTATUS_ANYRESUMEACK_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ANYRESUMEACK_BITS _u(0x00010000) +#define RISCV_DM_DMSTATUS_ANYRESUMEACK_MSB _u(16) +#define RISCV_DM_DMSTATUS_ANYRESUMEACK_LSB _u(16) +#define RISCV_DM_DMSTATUS_ANYRESUMEACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ALLNONEXISTENT +// Description : This field is 1 when all currently selected harts do not exist +// on this platform. +#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_RESET "-" +#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_BITS _u(0x00008000) +#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_MSB _u(15) +#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_LSB _u(15) +#define RISCV_DM_DMSTATUS_ALLNONEXISTENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ANYNONEXISTENT +// Description : This field is 1 when any currently selected hart does not exist +// in this platform. +#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_RESET "-" +#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_BITS _u(0x00004000) +#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_MSB _u(14) +#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_LSB _u(14) +#define RISCV_DM_DMSTATUS_ANYNONEXISTENT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ALLUNAVAIL +// Description : This field is 1 when all currently selected harts are +// unavailable. +#define RISCV_DM_DMSTATUS_ALLUNAVAIL_RESET "-" +#define RISCV_DM_DMSTATUS_ALLUNAVAIL_BITS _u(0x00002000) +#define RISCV_DM_DMSTATUS_ALLUNAVAIL_MSB _u(13) +#define RISCV_DM_DMSTATUS_ALLUNAVAIL_LSB _u(13) +#define RISCV_DM_DMSTATUS_ALLUNAVAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ANYUNAVAIL +// Description : This field is 1 when any currently selected hart is +// unavailable. +#define RISCV_DM_DMSTATUS_ANYUNAVAIL_RESET "-" +#define RISCV_DM_DMSTATUS_ANYUNAVAIL_BITS _u(0x00001000) +#define RISCV_DM_DMSTATUS_ANYUNAVAIL_MSB _u(12) +#define RISCV_DM_DMSTATUS_ANYUNAVAIL_LSB _u(12) +#define RISCV_DM_DMSTATUS_ANYUNAVAIL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ALLRUNNING +// Description : This field is 1 when all currently selected harts are running. +#define RISCV_DM_DMSTATUS_ALLRUNNING_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ALLRUNNING_BITS _u(0x00000800) +#define RISCV_DM_DMSTATUS_ALLRUNNING_MSB _u(11) +#define RISCV_DM_DMSTATUS_ALLRUNNING_LSB _u(11) +#define RISCV_DM_DMSTATUS_ALLRUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ANYRUNNING +// Description : This field is 1 when any currently selected hart is running. +#define RISCV_DM_DMSTATUS_ANYRUNNING_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ANYRUNNING_BITS _u(0x00000400) +#define RISCV_DM_DMSTATUS_ANYRUNNING_MSB _u(10) +#define RISCV_DM_DMSTATUS_ANYRUNNING_LSB _u(10) +#define RISCV_DM_DMSTATUS_ANYRUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ALLHALTED +// Description : This field is 1 when all currently selected harts are halted. +#define RISCV_DM_DMSTATUS_ALLHALTED_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ALLHALTED_BITS _u(0x00000200) +#define RISCV_DM_DMSTATUS_ALLHALTED_MSB _u(9) +#define RISCV_DM_DMSTATUS_ALLHALTED_LSB _u(9) +#define RISCV_DM_DMSTATUS_ALLHALTED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_ANYHALTED +// Description : This field is 1 when any currently selected hart is halted. +#define RISCV_DM_DMSTATUS_ANYHALTED_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_ANYHALTED_BITS _u(0x00000100) +#define RISCV_DM_DMSTATUS_ANYHALTED_MSB _u(8) +#define RISCV_DM_DMSTATUS_ANYHALTED_LSB _u(8) +#define RISCV_DM_DMSTATUS_ANYHALTED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_AUTHENTICATED +// Description : 0: Authentication is required before using the DM. +// +// 1: The authentication check has passed. +// +// On components that don’t implement authentication, this bit +// must be preset as 1. (Note: the version of Hazard3 on RP2350 +// does not implement authentication.) +#define RISCV_DM_DMSTATUS_AUTHENTICATED_RESET _u(0x1) +#define RISCV_DM_DMSTATUS_AUTHENTICATED_BITS _u(0x00000080) +#define RISCV_DM_DMSTATUS_AUTHENTICATED_MSB _u(7) +#define RISCV_DM_DMSTATUS_AUTHENTICATED_LSB _u(7) +#define RISCV_DM_DMSTATUS_AUTHENTICATED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_AUTHBUSY +// Description : 0: The authentication module is ready to process the next +// read/write to authdata. +// +// 1: The authentication module is busy. Accessing authdata +// results in unspecified behavior. authbusy only becomes set in +// immediate response to an access to authdata. +#define RISCV_DM_DMSTATUS_AUTHBUSY_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_AUTHBUSY_BITS _u(0x00000040) +#define RISCV_DM_DMSTATUS_AUTHBUSY_MSB _u(6) +#define RISCV_DM_DMSTATUS_AUTHBUSY_LSB _u(6) +#define RISCV_DM_DMSTATUS_AUTHBUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_HASRESETHALTREQ +// Description : 1 if this Debug Module supports halt-on-reset functionality +// controllable by the setresethaltreq and clrresethaltreq bits. 0 +// otherwise. +#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_RESET _u(0x1) +#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_BITS _u(0x00000020) +#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_MSB _u(5) +#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_LSB _u(5) +#define RISCV_DM_DMSTATUS_HASRESETHALTREQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_CONFSTPTRVALID +// Description : 0: confstrptr0–confstrptr3 hold information which is not +// relevant to the configuration string. +// +// 1: confstrptr0–confstrptr3 hold the address of the +// configuration string. +#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_RESET _u(0x0) +#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_BITS _u(0x00000010) +#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_MSB _u(4) +#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_LSB _u(4) +#define RISCV_DM_DMSTATUS_CONFSTPTRVALID_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_DMSTATUS_VERSION +// Description : 0: There is no Debug Module present. 1: There is a Debug Module +// and it conforms to version 0.11 of the RISC-V debug +// specification. +// +// 2: There is a Debug Module and it conforms to version 0.13 of +// the RISC-V debug specification. +// +// 15: There is a Debug Module but it does not con- form to any +// available version of the RISC-V debug spec. +#define RISCV_DM_DMSTATUS_VERSION_RESET _u(0x2) +#define RISCV_DM_DMSTATUS_VERSION_BITS _u(0x0000000f) +#define RISCV_DM_DMSTATUS_VERSION_MSB _u(3) +#define RISCV_DM_DMSTATUS_VERSION_LSB _u(0) +#define RISCV_DM_DMSTATUS_VERSION_ACCESS "RO" +// ============================================================================= +// Register : RISCV_DM_HARTINFO +// Description : This register gives information about the hart currently +// selected by hartsel. +// +// This entire register is read-only. +#define RISCV_DM_HARTINFO_OFFSET _u(0x00000048) +#define RISCV_DM_HARTINFO_BITS _u(0x00f1ffff) +#define RISCV_DM_HARTINFO_RESET _u(0x00001bff) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_HARTINFO_NSCRATCH +// Description : Number of dscratch registers available for the debugger to use +// during program buffer execution, starting from dscratch0. The +// debugger can make no assumptions about the contents of these +// registers between commands. +#define RISCV_DM_HARTINFO_NSCRATCH_RESET _u(0x0) +#define RISCV_DM_HARTINFO_NSCRATCH_BITS _u(0x00f00000) +#define RISCV_DM_HARTINFO_NSCRATCH_MSB _u(23) +#define RISCV_DM_HARTINFO_NSCRATCH_LSB _u(20) +#define RISCV_DM_HARTINFO_NSCRATCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_HARTINFO_DATAACCESS +// Description : 0: The data registers are shadowed in the hart by CSRs. Each +// CSR is DXLEN bits in size, and corresponds to a single +// argument. +// +// 1: The data registers are shadowed in the hart’s memory map. +// Each register takes up 4 bytes in the memory map. +#define RISCV_DM_HARTINFO_DATAACCESS_RESET _u(0x0) +#define RISCV_DM_HARTINFO_DATAACCESS_BITS _u(0x00010000) +#define RISCV_DM_HARTINFO_DATAACCESS_MSB _u(16) +#define RISCV_DM_HARTINFO_DATAACCESS_LSB _u(16) +#define RISCV_DM_HARTINFO_DATAACCESS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_HARTINFO_DATASIZE +// Description : If dataaccess is 0: Number of CSRs dedicated to shadowing the +// data registers. +// +// If dataaccess is 1: Number of 32-bit words in the memory map +// dedicated to shadowing the data registers. +#define RISCV_DM_HARTINFO_DATASIZE_RESET _u(0x1) +#define RISCV_DM_HARTINFO_DATASIZE_BITS _u(0x0000f000) +#define RISCV_DM_HARTINFO_DATASIZE_MSB _u(15) +#define RISCV_DM_HARTINFO_DATASIZE_LSB _u(12) +#define RISCV_DM_HARTINFO_DATASIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_HARTINFO_DATAADDR +// Description : If dataaccess is 0: The number of the first CSR dedicated to +// shadowing the data registers. +// +// If dataaccess is 1: Signed address of RAM where the data +// registers are shadowed, to be used to access relative to zero +// +// On Hazard3 this indicates the single data register mapped as +// dmdata0. There is actually only a single shared register, +// internal to the Debug Module, and mirrored in each core's CSR +// space. +#define RISCV_DM_HARTINFO_DATAADDR_RESET _u(0xbff) +#define RISCV_DM_HARTINFO_DATAADDR_BITS _u(0x00000fff) +#define RISCV_DM_HARTINFO_DATAADDR_MSB _u(11) +#define RISCV_DM_HARTINFO_DATAADDR_LSB _u(0) +#define RISCV_DM_HARTINFO_DATAADDR_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_HALTSUM1 +// Description : Each bit in this read-only register indicates whether any of a +// group of harts is halted or not. Unavailable/nonexistent harts +// are not considered to be halted. +// +// Each bit in haltsum1 is an OR reduction of 32 bits' worth of +// haltsum0. On RP2350, only the LSB is implemented. +#define RISCV_DM_HALTSUM1_OFFSET _u(0x0000004c) +#define RISCV_DM_HALTSUM1_BITS _u(0x00000001) +#define RISCV_DM_HALTSUM1_RESET _u(0x00000000) +#define RISCV_DM_HALTSUM1_MSB _u(0) +#define RISCV_DM_HALTSUM1_LSB _u(0) +#define RISCV_DM_HALTSUM1_ACCESS "RO" +// ============================================================================= +// Register : RISCV_DM_HAWINDOWSEL +// Description : This register selects which of the 32-bit portion of the hart +// array mask register is accessible in hawindow. +#define RISCV_DM_HAWINDOWSEL_OFFSET _u(0x00000050) +#define RISCV_DM_HAWINDOWSEL_BITS _u(0x00007fff) +#define RISCV_DM_HAWINDOWSEL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_HAWINDOWSEL_HAWINDOWSEL +// Description : On Hazard3 this register is entirely hardwired to 0. +#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_RESET _u(0x0000) +#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_BITS _u(0x00007fff) +#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_MSB _u(14) +#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_LSB _u(0) +#define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_HAWINDOW +// Description : This register provides R/W access to a 32-bit portion of the +// hart array mask register. The position of the window is +// determined by hawindowsel. I.e. bit 0 refers to hart +// hawindowsel ∗ 32, while bit 31 refers to hart hawindowsel ∗ 32 +// + 31. +// +// On RP2350 only the two least-significant bits of this register +// are implemented, since there are only two cores. This is still +// useful to run/halt/reset both cores exactly simultaneously. +#define RISCV_DM_HAWINDOW_OFFSET _u(0x00000054) +#define RISCV_DM_HAWINDOW_BITS _u(0x00000003) +#define RISCV_DM_HAWINDOW_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_HAWINDOW_MASKDATA +#define RISCV_DM_HAWINDOW_MASKDATA_RESET _u(0x0) +#define RISCV_DM_HAWINDOW_MASKDATA_BITS _u(0x00000003) +#define RISCV_DM_HAWINDOW_MASKDATA_MSB _u(1) +#define RISCV_DM_HAWINDOW_MASKDATA_LSB _u(0) +#define RISCV_DM_HAWINDOW_MASKDATA_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_ABSTRACTS +// Description : Abstract Control and Status. Writing this register while an +// abstract command is executing causes cmderr to be set to 1 +// (busy) if it is 0. +#define RISCV_DM_ABSTRACTS_OFFSET _u(0x00000058) +#define RISCV_DM_ABSTRACTS_BITS _u(0x1f00170f) +#define RISCV_DM_ABSTRACTS_RESET _u(0x02000001) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_ABSTRACTS_PROGBUFSIZE +// Description : Size of the Program Buffer, in 32-bit words. +#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_RESET _u(0x02) +#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_BITS _u(0x1f000000) +#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_MSB _u(28) +#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_LSB _u(24) +#define RISCV_DM_ABSTRACTS_PROGBUFSIZE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_ABSTRACTS_BUSY +// Description : 1: An abstract command is currently being executed. +// +// This bit is set as soon as command is written, and is not +// cleared until that command has completed. +#define RISCV_DM_ABSTRACTS_BUSY_RESET _u(0x0) +#define RISCV_DM_ABSTRACTS_BUSY_BITS _u(0x00001000) +#define RISCV_DM_ABSTRACTS_BUSY_MSB _u(12) +#define RISCV_DM_ABSTRACTS_BUSY_LSB _u(12) +#define RISCV_DM_ABSTRACTS_BUSY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_ABSTRACTS_CMDERR +// Description : Gets set if an abstract command fails. The bits in this field +// remain set until they are cleared by writing 1 to them. No +// abstract command is started until the value is reset to 0. +// +// This field only contains a valid value if busy is 0. +// +// 0 (none): No error. +// +// 1 (busy): An abstract command was executing while command, +// abstractcs, or abstractauto was written, or when one of the +// data or progbuf registers was read or written. This status is +// only written if cmderr contains 0. +// +// 2 (not supported): The requested command is not supported, +// regardless of whether the hart is running or not. +// +// 3 (exception): An exception occurred while executing the +// command (e.g. while executing the Program Buffer). +// +// 4 (halt/resume): The abstract command couldn’t execute because +// the hart wasn’t in the required state (running/halted), or +// unavailable. +// +// 5 (bus): The abstract command failed due to a bus error (e.g. +// alignment, access size, or timeout). +// +// 7 (other): The command failed for another reason. +// +// Note: Hazard3 does not set values 5 or 7. Load/store +// instructions in the program buffer raise an exception when they +// encounter a bus fault, setting cmderr=3. +#define RISCV_DM_ABSTRACTS_CMDERR_RESET _u(0x0) +#define RISCV_DM_ABSTRACTS_CMDERR_BITS _u(0x00000700) +#define RISCV_DM_ABSTRACTS_CMDERR_MSB _u(10) +#define RISCV_DM_ABSTRACTS_CMDERR_LSB _u(8) +#define RISCV_DM_ABSTRACTS_CMDERR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_ABSTRACTS_DATACOUNT +// Description : Number of data registers that are implemented as part of the +// abstract command interface. +#define RISCV_DM_ABSTRACTS_DATACOUNT_RESET _u(0x1) +#define RISCV_DM_ABSTRACTS_DATACOUNT_BITS _u(0x0000000f) +#define RISCV_DM_ABSTRACTS_DATACOUNT_MSB _u(3) +#define RISCV_DM_ABSTRACTS_DATACOUNT_LSB _u(0) +#define RISCV_DM_ABSTRACTS_DATACOUNT_ACCESS "RO" +// ============================================================================= +// Register : RISCV_DM_COMMAND +// Description : Writes to this register cause the corresponding abstract +// command to be executed. +// +// Writing this register while an abstract command is executing +// causes cmderr to be set to 1 (busy) if it is 0. +// +// If cmderr is non-zero, writes to this register are ignored. +#define RISCV_DM_COMMAND_OFFSET _u(0x0000005c) +#define RISCV_DM_COMMAND_BITS _u(0xff7fffff) +#define RISCV_DM_COMMAND_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_COMMAND_CMDTYPE +// Description : On Hazard3 this field must be 0 (Access Register) +#define RISCV_DM_COMMAND_CMDTYPE_RESET _u(0x00) +#define RISCV_DM_COMMAND_CMDTYPE_BITS _u(0xff000000) +#define RISCV_DM_COMMAND_CMDTYPE_MSB _u(31) +#define RISCV_DM_COMMAND_CMDTYPE_LSB _u(24) +#define RISCV_DM_COMMAND_CMDTYPE_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_COMMAND_AARSIZE +// Description : On Hazard3 this field must be 2 (32-bit register access) +#define RISCV_DM_COMMAND_AARSIZE_RESET _u(0x0) +#define RISCV_DM_COMMAND_AARSIZE_BITS _u(0x00700000) +#define RISCV_DM_COMMAND_AARSIZE_MSB _u(22) +#define RISCV_DM_COMMAND_AARSIZE_LSB _u(20) +#define RISCV_DM_COMMAND_AARSIZE_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_COMMAND_AARPOSTINCREMENT +// Description : On Hazard3 this field must be 0 (no post-increment of regno) +#define RISCV_DM_COMMAND_AARPOSTINCREMENT_RESET _u(0x0) +#define RISCV_DM_COMMAND_AARPOSTINCREMENT_BITS _u(0x00080000) +#define RISCV_DM_COMMAND_AARPOSTINCREMENT_MSB _u(19) +#define RISCV_DM_COMMAND_AARPOSTINCREMENT_LSB _u(19) +#define RISCV_DM_COMMAND_AARPOSTINCREMENT_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_COMMAND_POSTEXEC +// Description : 0: No effect. +// +// 1: Execute the program in the Program Buffer exactly once after +// performing the transfer, if any. +#define RISCV_DM_COMMAND_POSTEXEC_RESET _u(0x0) +#define RISCV_DM_COMMAND_POSTEXEC_BITS _u(0x00040000) +#define RISCV_DM_COMMAND_POSTEXEC_MSB _u(18) +#define RISCV_DM_COMMAND_POSTEXEC_LSB _u(18) +#define RISCV_DM_COMMAND_POSTEXEC_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_COMMAND_TRANSFER +// Description : 0: Don’t do the operation specified by write. +// +// 1: Do the operation specified by write. +// +// This bit can be used to just execute the Program Buffer without +// having to worry about placing valid values into aarsize or +// regno. +#define RISCV_DM_COMMAND_TRANSFER_RESET _u(0x0) +#define RISCV_DM_COMMAND_TRANSFER_BITS _u(0x00020000) +#define RISCV_DM_COMMAND_TRANSFER_MSB _u(17) +#define RISCV_DM_COMMAND_TRANSFER_LSB _u(17) +#define RISCV_DM_COMMAND_TRANSFER_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_COMMAND_WRITE +// Description : When transfer is set: +// +// 0: Copy data from the specified register into data0. +// +// 1: Copy data from data0 into the specified register. +#define RISCV_DM_COMMAND_WRITE_RESET _u(0x0) +#define RISCV_DM_COMMAND_WRITE_BITS _u(0x00010000) +#define RISCV_DM_COMMAND_WRITE_MSB _u(16) +#define RISCV_DM_COMMAND_WRITE_LSB _u(16) +#define RISCV_DM_COMMAND_WRITE_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_COMMAND_REGNO +// Description : Number of the register to access. +// +// On Hazard3 this must be in the range 0x1000 through 0x101f +// inclusive, referring to GPRs x0 through x31. +#define RISCV_DM_COMMAND_REGNO_RESET _u(0x0000) +#define RISCV_DM_COMMAND_REGNO_BITS _u(0x0000ffff) +#define RISCV_DM_COMMAND_REGNO_MSB _u(15) +#define RISCV_DM_COMMAND_REGNO_LSB _u(0) +#define RISCV_DM_COMMAND_REGNO_ACCESS "WO" +// ============================================================================= +// Register : RISCV_DM_ABSTRACTAUTO +// Description : Abstract Command Autoexec. Writing this register while an +// abstract command is executing causes cmderr to be set to 1 +// (busy) if it is 0. +#define RISCV_DM_ABSTRACTAUTO_OFFSET _u(0x00000060) +#define RISCV_DM_ABSTRACTAUTO_BITS _u(0xffff8fff) +#define RISCV_DM_ABSTRACTAUTO_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF +// Description : When a bit in this field is 1, read or write accesses to the +// corresponding progbuf word cause the command in command to be +// executed again. +// +// Hazard3 implements only the two least-significant bits of this +// field (for the two-entry progbuf) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_RESET _u(0x00000) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_BITS _u(0xffff8000) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_MSB _u(31) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_LSB _u(15) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA +// Description : When a bit in this field is 1, read or write accesses to the +// corresponding data word cause the command in command to be +// executed again. +// +// Hazard3 implements only the least-significant bit of this +// field. +#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_RESET _u(0x000) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_BITS _u(0x00000fff) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_MSB _u(11) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_LSB _u(0) +#define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_NEXTDM +// Description : If there is more than one DM accessible on this DMI, this +// register contains the base address of thenext one in the chain, +// or 0 if this is the last one in the chain. +#define RISCV_DM_NEXTDM_OFFSET _u(0x00000074) +#define RISCV_DM_NEXTDM_BITS _u(0xffffffff) +#define RISCV_DM_NEXTDM_RESET _u(0x00000000) +#define RISCV_DM_NEXTDM_MSB _u(31) +#define RISCV_DM_NEXTDM_LSB _u(0) +#define RISCV_DM_NEXTDM_ACCESS "RO" +// ============================================================================= +// Register : RISCV_DM_PROGBUF0 +// Description : progbuf0 through progbuf15 provide read/write access to the +// program buffer. abstractcs.progbufsize indicates how many of +// them are implemented starting at progbuf0, counting up. +// +// (Hazard3 implements a 2-word program buffer.) +#define RISCV_DM_PROGBUF0_OFFSET _u(0x00000080) +#define RISCV_DM_PROGBUF0_BITS _u(0xffffffff) +#define RISCV_DM_PROGBUF0_RESET _u(0x00000000) +#define RISCV_DM_PROGBUF0_MSB _u(31) +#define RISCV_DM_PROGBUF0_LSB _u(0) +#define RISCV_DM_PROGBUF0_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_PROGBUF1 +// Description : progbuf0 through progbuf15 provide read/write access to the +// program buffer. abstractcs.progbufsize indicates how many of +// them are implemented starting at progbuf0, counting up. +// +// (Hazard3 implements a 2-word program buffer.) +#define RISCV_DM_PROGBUF1_OFFSET _u(0x00000084) +#define RISCV_DM_PROGBUF1_BITS _u(0xffffffff) +#define RISCV_DM_PROGBUF1_RESET _u(0x00000000) +#define RISCV_DM_PROGBUF1_MSB _u(31) +#define RISCV_DM_PROGBUF1_LSB _u(0) +#define RISCV_DM_PROGBUF1_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_SBCS +// Description : System Bus Access Control and Status +#define RISCV_DM_SBCS_OFFSET _u(0x000000e0) +#define RISCV_DM_SBCS_BITS _u(0xe07fffff) +#define RISCV_DM_SBCS_RESET _u(0x20000407) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBVERSION +// Description : 1: The System Bus interface conforms to version 0.13.2 of the +// RISC-V debug spec. +#define RISCV_DM_SBCS_SBVERSION_RESET _u(0x1) +#define RISCV_DM_SBCS_SBVERSION_BITS _u(0xe0000000) +#define RISCV_DM_SBCS_SBVERSION_MSB _u(31) +#define RISCV_DM_SBCS_SBVERSION_LSB _u(29) +#define RISCV_DM_SBCS_SBVERSION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBBUSYERROR +// Description : Set when the debugger attempts to read data while a read is in +// progress, or when the debugger initiates a new access while one +// is already in progress (while sbbusy is set). It remains set +// until it’s explicitly cleared by the debugger. +// +// While this field is set, no more system bus accesses can be +// initiated by the Debug Module. +#define RISCV_DM_SBCS_SBBUSYERROR_RESET _u(0x0) +#define RISCV_DM_SBCS_SBBUSYERROR_BITS _u(0x00400000) +#define RISCV_DM_SBCS_SBBUSYERROR_MSB _u(22) +#define RISCV_DM_SBCS_SBBUSYERROR_LSB _u(22) +#define RISCV_DM_SBCS_SBBUSYERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBBUSY +// Description : When 1, indicates the system bus master is busy. (Whether the +// system bus itself is busy is related, but not the same thing.) +// This bit goes high immediately when a read or write is +// requested for any reason, and does not go low until the access +// is fully completed. +// +// Writes to sbcs while sbbusy is high result in undefined +// behavior. A debugger must not write to sbcs until it reads +// sbbusy as 0. +#define RISCV_DM_SBCS_SBBUSY_RESET _u(0x0) +#define RISCV_DM_SBCS_SBBUSY_BITS _u(0x00200000) +#define RISCV_DM_SBCS_SBBUSY_MSB _u(21) +#define RISCV_DM_SBCS_SBBUSY_LSB _u(21) +#define RISCV_DM_SBCS_SBBUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBREADONADDR +// Description : When 1, every write to sbaddress0 automatically triggers a +// system bus read at the new address. +#define RISCV_DM_SBCS_SBREADONADDR_RESET _u(0x0) +#define RISCV_DM_SBCS_SBREADONADDR_BITS _u(0x00100000) +#define RISCV_DM_SBCS_SBREADONADDR_MSB _u(20) +#define RISCV_DM_SBCS_SBREADONADDR_LSB _u(20) +#define RISCV_DM_SBCS_SBREADONADDR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBACCESS +// Description : Select the access size to use for system bus accesses. +// +// 0: 8-bit +// +// 1: 16-bit +// +// 2: 32-bit +// +// 3: 64-bit +// +// 4: 128-bit +// +// If sbaccess has an unsupported value when the DM starts a bus +// access, the access is not per formed and sberror is set to 4. +// (On Hazard3 the supported values are 8-bit, 16-bit and 32-bit.) +#define RISCV_DM_SBCS_SBACCESS_RESET _u(0x0) +#define RISCV_DM_SBCS_SBACCESS_BITS _u(0x000e0000) +#define RISCV_DM_SBCS_SBACCESS_MSB _u(19) +#define RISCV_DM_SBCS_SBACCESS_LSB _u(17) +#define RISCV_DM_SBCS_SBACCESS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBAUTOINCREMENT +// Description : When 1, sbaddress is incremented by the access size (in bytes) +// selected in sbaccess after every system bus access. +#define RISCV_DM_SBCS_SBAUTOINCREMENT_RESET _u(0x0) +#define RISCV_DM_SBCS_SBAUTOINCREMENT_BITS _u(0x00010000) +#define RISCV_DM_SBCS_SBAUTOINCREMENT_MSB _u(16) +#define RISCV_DM_SBCS_SBAUTOINCREMENT_LSB _u(16) +#define RISCV_DM_SBCS_SBAUTOINCREMENT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBREADONDATA +// Description : When 1, every read from sbdata0 automatically triggers a system +// bus read at the (possibly auto- incremented) address. +#define RISCV_DM_SBCS_SBREADONDATA_RESET _u(0x0) +#define RISCV_DM_SBCS_SBREADONDATA_BITS _u(0x00008000) +#define RISCV_DM_SBCS_SBREADONDATA_MSB _u(15) +#define RISCV_DM_SBCS_SBREADONDATA_LSB _u(15) +#define RISCV_DM_SBCS_SBREADONDATA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBERROR +// Description : When the Debug Module’s system bus master encounters an error, +// this field gets set. The bits in this field remain set until +// they are cleared by writing 1 to them. While this field is non- +// zero, no more system bus accesses can be initiated by the Debug +// Module. +// +// An implementation may report “Other” (7) for any error +// condition. (Hazard3 does not use this value for any errors.) +// +// 0: There was no bus error. +// +// 1: There was a timeout. +// +// 2: A bad address was accessed. +// +// 3: There was an alignment error. +// +// 4: An access of unsupported size was requested. +// +// 7: Other. +// +// Hazard3 raises an alignment error for any non-naturally-aligned +// bus transfer which would otherwise be a valid transfer. +#define RISCV_DM_SBCS_SBERROR_RESET _u(0x0) +#define RISCV_DM_SBCS_SBERROR_BITS _u(0x00007000) +#define RISCV_DM_SBCS_SBERROR_MSB _u(14) +#define RISCV_DM_SBCS_SBERROR_LSB _u(12) +#define RISCV_DM_SBCS_SBERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBASIZE +// Description : Width of system bus addresses in bits. (0 indicates there is no +// bus access support.) +#define RISCV_DM_SBCS_SBASIZE_RESET _u(0x20) +#define RISCV_DM_SBCS_SBASIZE_BITS _u(0x00000fe0) +#define RISCV_DM_SBCS_SBASIZE_MSB _u(11) +#define RISCV_DM_SBCS_SBASIZE_LSB _u(5) +#define RISCV_DM_SBCS_SBASIZE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBACCESS128 +// Description : 1 when 128-bit system bus accesses are supported. +#define RISCV_DM_SBCS_SBACCESS128_RESET _u(0x0) +#define RISCV_DM_SBCS_SBACCESS128_BITS _u(0x00000010) +#define RISCV_DM_SBCS_SBACCESS128_MSB _u(4) +#define RISCV_DM_SBCS_SBACCESS128_LSB _u(4) +#define RISCV_DM_SBCS_SBACCESS128_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBACCESS64 +// Description : 1 when 64-bit system bus accesses are supported. +#define RISCV_DM_SBCS_SBACCESS64_RESET _u(0x0) +#define RISCV_DM_SBCS_SBACCESS64_BITS _u(0x00000008) +#define RISCV_DM_SBCS_SBACCESS64_MSB _u(3) +#define RISCV_DM_SBCS_SBACCESS64_LSB _u(3) +#define RISCV_DM_SBCS_SBACCESS64_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBACCESS32 +// Description : 1 when 32-bit system bus accesses are supported. +#define RISCV_DM_SBCS_SBACCESS32_RESET _u(0x1) +#define RISCV_DM_SBCS_SBACCESS32_BITS _u(0x00000004) +#define RISCV_DM_SBCS_SBACCESS32_MSB _u(2) +#define RISCV_DM_SBCS_SBACCESS32_LSB _u(2) +#define RISCV_DM_SBCS_SBACCESS32_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBACCESS16 +// Description : 1 when 16-bit system bus accesses are supported. +#define RISCV_DM_SBCS_SBACCESS16_RESET _u(0x1) +#define RISCV_DM_SBCS_SBACCESS16_BITS _u(0x00000002) +#define RISCV_DM_SBCS_SBACCESS16_MSB _u(1) +#define RISCV_DM_SBCS_SBACCESS16_LSB _u(1) +#define RISCV_DM_SBCS_SBACCESS16_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBCS_SBACCESS8 +// Description : 1 when 8-bit system bus accesses are supported. +#define RISCV_DM_SBCS_SBACCESS8_RESET _u(0x1) +#define RISCV_DM_SBCS_SBACCESS8_BITS _u(0x00000001) +#define RISCV_DM_SBCS_SBACCESS8_MSB _u(0) +#define RISCV_DM_SBCS_SBACCESS8_LSB _u(0) +#define RISCV_DM_SBCS_SBACCESS8_ACCESS "RO" +// ============================================================================= +// Register : RISCV_DM_SBADDRESS0 +// Description : System Bus Address 31:0 +// +// When the system bus master is busy, writes to this register +// will set sbbusyerror and don’t do anything else. +// +// If sberror is 0, sbbusyerror is 0, and sbreadonaddr is set then +// writes to this register start the following: +// +// 1. Set sbbusy. +// +// 2. Perform a bus read from the new value of sbaddress. +// +// 3. If the read succeeded and sbautoincrement is set, increment +// sbaddress. +// +// 4. Clear sbbusy. +#define RISCV_DM_SBADDRESS0_OFFSET _u(0x000000e4) +#define RISCV_DM_SBADDRESS0_BITS _u(0xffffffff) +#define RISCV_DM_SBADDRESS0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBADDRESS0_ADDRESS +// Description : Accesses bits 31:0 of the physical address in sbaddress. +#define RISCV_DM_SBADDRESS0_ADDRESS_RESET _u(0x00000000) +#define RISCV_DM_SBADDRESS0_ADDRESS_BITS _u(0xffffffff) +#define RISCV_DM_SBADDRESS0_ADDRESS_MSB _u(31) +#define RISCV_DM_SBADDRESS0_ADDRESS_LSB _u(0) +#define RISCV_DM_SBADDRESS0_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_SBDATA0 +// Description : System Bus Data 31:0 +// +// Any successful system bus read updates sbdata. If the width of +// the read access is less than the width of sbdata, the contents +// of the remaining high bits may take on any value. +// +// If sberror or sbbusyerror both aren’t 0 then accesses do +// nothing. +// +// If the bus master is busy then accesses set sbbusyerror, and +// don’t do anything else. Writes to this register start the +// following: +// +// 1. Set sbbusy. +// +// 2. Perform a bus write of the new value of sbdata to sbaddress. +// +// 3. If the write succeeded and sbautoincrement is set, increment +// sbaddress. +// +// 4. Clear sbbusy. +// +// Reads from this register start the following: +// +// 1. “Return” the data. +// +// 2. Set sbbusy. +// +// 3. If sbreadondata is set, perform a system bus read from the +// address contained in sbaddress, placing the result in sbdata. +// +// 4. If the read was successful, and sbautoincrement is set, +// increment sbaddress. +// +// 5. Clear sbbusy. +#define RISCV_DM_SBDATA0_OFFSET _u(0x000000f0) +#define RISCV_DM_SBDATA0_BITS _u(0xffffffff) +#define RISCV_DM_SBDATA0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RISCV_DM_SBDATA0_DATA +#define RISCV_DM_SBDATA0_DATA_RESET _u(0x00000000) +#define RISCV_DM_SBDATA0_DATA_BITS _u(0xffffffff) +#define RISCV_DM_SBDATA0_DATA_MSB _u(31) +#define RISCV_DM_SBDATA0_DATA_LSB _u(0) +#define RISCV_DM_SBDATA0_DATA_ACCESS "RW" +// ============================================================================= +// Register : RISCV_DM_HALTSUM0 +// Description : Each bit in this read-only register indicates whether one +// specific hart is halted or not. Unavailable/nonexistent harts +// are not considered to be halted. +// +// On RP2350, only the two LSBs of this register are implemented, +// one for each core/hart. +// +// This entire register is read-only. +#define RISCV_DM_HALTSUM0_OFFSET _u(0x00000100) +#define RISCV_DM_HALTSUM0_BITS _u(0xffffffff) +#define RISCV_DM_HALTSUM0_RESET _u(0x00000000) +#define RISCV_DM_HALTSUM0_MSB _u(31) +#define RISCV_DM_HALTSUM0_LSB _u(0) +#define RISCV_DM_HALTSUM0_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_RISCV_DM_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/rosc.h b/lib/pico-sdk/rp2350/hardware/regs/rosc.h new file mode 100644 index 000000000000..4865c2ee3190 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/rosc.h @@ -0,0 +1,345 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : ROSC +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_ROSC_H +#define _HARDWARE_REGS_ROSC_H +// ============================================================================= +// Register : ROSC_CTRL +// Description : Ring Oscillator control +#define ROSC_CTRL_OFFSET _u(0x00000000) +#define ROSC_CTRL_BITS _u(0x00ffffff) +#define ROSC_CTRL_RESET _u(0x00000aa0) +// ----------------------------------------------------------------------------- +// Field : ROSC_CTRL_ENABLE +// Description : On power-up this field is initialised to ENABLE +// The system clock must be switched to another source before +// setting this field to DISABLE otherwise the chip will lock up +// The 12-bit code is intended to give some protection against +// accidental writes. An invalid setting will enable the +// oscillator. +// 0xd1e -> DISABLE +// 0xfab -> ENABLE +#define ROSC_CTRL_ENABLE_RESET "-" +#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000) +#define ROSC_CTRL_ENABLE_MSB _u(23) +#define ROSC_CTRL_ENABLE_LSB _u(12) +#define ROSC_CTRL_ENABLE_ACCESS "RW" +#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) +#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) +// ----------------------------------------------------------------------------- +// Field : ROSC_CTRL_FREQ_RANGE +// Description : Controls the number of delay stages in the ROSC ring +// LOW uses stages 0 to 7 +// MEDIUM uses stages 2 to 7 +// HIGH uses stages 4 to 7 +// TOOHIGH uses stages 6 to 7 and should not be used because its +// frequency exceeds design specifications +// The clock output will not glitch when changing the range up one +// step at a time +// The clock output will glitch when changing the range down +// Note: the values here are gray coded which is why HIGH comes +// before TOOHIGH +// 0xfa4 -> LOW +// 0xfa5 -> MEDIUM +// 0xfa7 -> HIGH +// 0xfa6 -> TOOHIGH +#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0) +#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) +#define ROSC_CTRL_FREQ_RANGE_MSB _u(11) +#define ROSC_CTRL_FREQ_RANGE_LSB _u(0) +#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW" +#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4) +#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5) +#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7) +#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6) +// ============================================================================= +// Register : ROSC_FREQA +// Description : The FREQA & FREQB registers control the frequency by +// controlling the drive strength of each stage +// The drive strength has 4 levels determined by the number of +// bits set +// Increasing the number of bits set increases the drive strength +// and increases the oscillation frequency +// 0 bits set is the default drive strength +// 1 bit set doubles the drive strength +// 2 bits set triples drive strength +// 3 bits set quadruples drive strength +// For frequency randomisation set both DS0_RANDOM=1 & +// DS1_RANDOM=1 +#define ROSC_FREQA_OFFSET _u(0x00000004) +#define ROSC_FREQA_BITS _u(0xffff77ff) +#define ROSC_FREQA_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_PASSWD +// Description : Set to 0x9696 to apply the settings +// Any other value in this field will set all drive strengths to 0 +// 0x9696 -> PASS +#define ROSC_FREQA_PASSWD_RESET _u(0x0000) +#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000) +#define ROSC_FREQA_PASSWD_MSB _u(31) +#define ROSC_FREQA_PASSWD_LSB _u(16) +#define ROSC_FREQA_PASSWD_ACCESS "RW" +#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696) +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS3 +// Description : Stage 3 drive strength +#define ROSC_FREQA_DS3_RESET _u(0x0) +#define ROSC_FREQA_DS3_BITS _u(0x00007000) +#define ROSC_FREQA_DS3_MSB _u(14) +#define ROSC_FREQA_DS3_LSB _u(12) +#define ROSC_FREQA_DS3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS2 +// Description : Stage 2 drive strength +#define ROSC_FREQA_DS2_RESET _u(0x0) +#define ROSC_FREQA_DS2_BITS _u(0x00000700) +#define ROSC_FREQA_DS2_MSB _u(10) +#define ROSC_FREQA_DS2_LSB _u(8) +#define ROSC_FREQA_DS2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS1_RANDOM +// Description : Randomises the stage 1 drive strength +#define ROSC_FREQA_DS1_RANDOM_RESET _u(0x0) +#define ROSC_FREQA_DS1_RANDOM_BITS _u(0x00000080) +#define ROSC_FREQA_DS1_RANDOM_MSB _u(7) +#define ROSC_FREQA_DS1_RANDOM_LSB _u(7) +#define ROSC_FREQA_DS1_RANDOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS1 +// Description : Stage 1 drive strength +#define ROSC_FREQA_DS1_RESET _u(0x0) +#define ROSC_FREQA_DS1_BITS _u(0x00000070) +#define ROSC_FREQA_DS1_MSB _u(6) +#define ROSC_FREQA_DS1_LSB _u(4) +#define ROSC_FREQA_DS1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS0_RANDOM +// Description : Randomises the stage 0 drive strength +#define ROSC_FREQA_DS0_RANDOM_RESET _u(0x0) +#define ROSC_FREQA_DS0_RANDOM_BITS _u(0x00000008) +#define ROSC_FREQA_DS0_RANDOM_MSB _u(3) +#define ROSC_FREQA_DS0_RANDOM_LSB _u(3) +#define ROSC_FREQA_DS0_RANDOM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQA_DS0 +// Description : Stage 0 drive strength +#define ROSC_FREQA_DS0_RESET _u(0x0) +#define ROSC_FREQA_DS0_BITS _u(0x00000007) +#define ROSC_FREQA_DS0_MSB _u(2) +#define ROSC_FREQA_DS0_LSB _u(0) +#define ROSC_FREQA_DS0_ACCESS "RW" +// ============================================================================= +// Register : ROSC_FREQB +// Description : For a detailed description see freqa register +#define ROSC_FREQB_OFFSET _u(0x00000008) +#define ROSC_FREQB_BITS _u(0xffff7777) +#define ROSC_FREQB_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_PASSWD +// Description : Set to 0x9696 to apply the settings +// Any other value in this field will set all drive strengths to 0 +// 0x9696 -> PASS +#define ROSC_FREQB_PASSWD_RESET _u(0x0000) +#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000) +#define ROSC_FREQB_PASSWD_MSB _u(31) +#define ROSC_FREQB_PASSWD_LSB _u(16) +#define ROSC_FREQB_PASSWD_ACCESS "RW" +#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696) +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS7 +// Description : Stage 7 drive strength +#define ROSC_FREQB_DS7_RESET _u(0x0) +#define ROSC_FREQB_DS7_BITS _u(0x00007000) +#define ROSC_FREQB_DS7_MSB _u(14) +#define ROSC_FREQB_DS7_LSB _u(12) +#define ROSC_FREQB_DS7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS6 +// Description : Stage 6 drive strength +#define ROSC_FREQB_DS6_RESET _u(0x0) +#define ROSC_FREQB_DS6_BITS _u(0x00000700) +#define ROSC_FREQB_DS6_MSB _u(10) +#define ROSC_FREQB_DS6_LSB _u(8) +#define ROSC_FREQB_DS6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS5 +// Description : Stage 5 drive strength +#define ROSC_FREQB_DS5_RESET _u(0x0) +#define ROSC_FREQB_DS5_BITS _u(0x00000070) +#define ROSC_FREQB_DS5_MSB _u(6) +#define ROSC_FREQB_DS5_LSB _u(4) +#define ROSC_FREQB_DS5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_FREQB_DS4 +// Description : Stage 4 drive strength +#define ROSC_FREQB_DS4_RESET _u(0x0) +#define ROSC_FREQB_DS4_BITS _u(0x00000007) +#define ROSC_FREQB_DS4_MSB _u(2) +#define ROSC_FREQB_DS4_LSB _u(0) +#define ROSC_FREQB_DS4_ACCESS "RW" +// ============================================================================= +// Register : ROSC_RANDOM +// Description : Loads a value to the LFSR randomiser +#define ROSC_RANDOM_OFFSET _u(0x0000000c) +#define ROSC_RANDOM_BITS _u(0xffffffff) +#define ROSC_RANDOM_RESET _u(0x3f04b16d) +// ----------------------------------------------------------------------------- +// Field : ROSC_RANDOM_SEED +#define ROSC_RANDOM_SEED_RESET _u(0x3f04b16d) +#define ROSC_RANDOM_SEED_BITS _u(0xffffffff) +#define ROSC_RANDOM_SEED_MSB _u(31) +#define ROSC_RANDOM_SEED_LSB _u(0) +#define ROSC_RANDOM_SEED_ACCESS "RW" +// ============================================================================= +// Register : ROSC_DORMANT +// Description : Ring Oscillator pause control +// This is used to save power by pausing the ROSC +// On power-up this field is initialised to WAKE +// An invalid write will also select WAKE +// Warning: setup the irq before selecting dormant mode +// 0x636f6d61 -> dormant +// 0x77616b65 -> WAKE +#define ROSC_DORMANT_OFFSET _u(0x00000010) +#define ROSC_DORMANT_BITS _u(0xffffffff) +#define ROSC_DORMANT_RESET "-" +#define ROSC_DORMANT_MSB _u(31) +#define ROSC_DORMANT_LSB _u(0) +#define ROSC_DORMANT_ACCESS "RW" +#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) +#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65) +// ============================================================================= +// Register : ROSC_DIV +// Description : Controls the output divider +// set to 0xaa00 + div where +// div = 0 divides by 128 +// div = 1-127 divides by div +// any other value sets div=128 +// this register resets to div=32 +// 0xaa00 -> PASS +#define ROSC_DIV_OFFSET _u(0x00000014) +#define ROSC_DIV_BITS _u(0x0000ffff) +#define ROSC_DIV_RESET "-" +#define ROSC_DIV_MSB _u(15) +#define ROSC_DIV_LSB _u(0) +#define ROSC_DIV_ACCESS "RW" +#define ROSC_DIV_VALUE_PASS _u(0xaa00) +// ============================================================================= +// Register : ROSC_PHASE +// Description : Controls the phase shifted output +#define ROSC_PHASE_OFFSET _u(0x00000018) +#define ROSC_PHASE_BITS _u(0x00000fff) +#define ROSC_PHASE_RESET _u(0x00000008) +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_PASSWD +// Description : set to 0xaa +// any other value enables the output with shift=0 +#define ROSC_PHASE_PASSWD_RESET _u(0x00) +#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0) +#define ROSC_PHASE_PASSWD_MSB _u(11) +#define ROSC_PHASE_PASSWD_LSB _u(4) +#define ROSC_PHASE_PASSWD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_ENABLE +// Description : enable the phase-shifted output +// this can be changed on-the-fly +#define ROSC_PHASE_ENABLE_RESET _u(0x1) +#define ROSC_PHASE_ENABLE_BITS _u(0x00000008) +#define ROSC_PHASE_ENABLE_MSB _u(3) +#define ROSC_PHASE_ENABLE_LSB _u(3) +#define ROSC_PHASE_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_FLIP +// Description : invert the phase-shifted output +// this is ignored when div=1 +#define ROSC_PHASE_FLIP_RESET _u(0x0) +#define ROSC_PHASE_FLIP_BITS _u(0x00000004) +#define ROSC_PHASE_FLIP_MSB _u(2) +#define ROSC_PHASE_FLIP_LSB _u(2) +#define ROSC_PHASE_FLIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : ROSC_PHASE_SHIFT +// Description : phase shift the phase-shifted output by SHIFT input clocks +// this can be changed on-the-fly +// must be set to 0 before setting div=1 +#define ROSC_PHASE_SHIFT_RESET _u(0x0) +#define ROSC_PHASE_SHIFT_BITS _u(0x00000003) +#define ROSC_PHASE_SHIFT_MSB _u(1) +#define ROSC_PHASE_SHIFT_LSB _u(0) +#define ROSC_PHASE_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : ROSC_STATUS +// Description : Ring Oscillator Status +#define ROSC_STATUS_OFFSET _u(0x0000001c) +#define ROSC_STATUS_BITS _u(0x81011000) +#define ROSC_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_STABLE +// Description : Oscillator is running and stable +#define ROSC_STATUS_STABLE_RESET _u(0x0) +#define ROSC_STATUS_STABLE_BITS _u(0x80000000) +#define ROSC_STATUS_STABLE_MSB _u(31) +#define ROSC_STATUS_STABLE_LSB _u(31) +#define ROSC_STATUS_STABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_BADWRITE +// Description : An invalid value has been written to CTRL_ENABLE or +// CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT +#define ROSC_STATUS_BADWRITE_RESET _u(0x0) +#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000) +#define ROSC_STATUS_BADWRITE_MSB _u(24) +#define ROSC_STATUS_BADWRITE_LSB _u(24) +#define ROSC_STATUS_BADWRITE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_DIV_RUNNING +// Description : post-divider is running +// this resets to 0 but transitions to 1 during chip startup +#define ROSC_STATUS_DIV_RUNNING_RESET "-" +#define ROSC_STATUS_DIV_RUNNING_BITS _u(0x00010000) +#define ROSC_STATUS_DIV_RUNNING_MSB _u(16) +#define ROSC_STATUS_DIV_RUNNING_LSB _u(16) +#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : ROSC_STATUS_ENABLED +// Description : Oscillator is enabled but not necessarily running and stable +// this resets to 0 but transitions to 1 during chip startup +#define ROSC_STATUS_ENABLED_RESET "-" +#define ROSC_STATUS_ENABLED_BITS _u(0x00001000) +#define ROSC_STATUS_ENABLED_MSB _u(12) +#define ROSC_STATUS_ENABLED_LSB _u(12) +#define ROSC_STATUS_ENABLED_ACCESS "RO" +// ============================================================================= +// Register : ROSC_RANDOMBIT +// Description : This just reads the state of the oscillator output so +// randomness is compromised if the ring oscillator is stopped or +// run at a harmonic of the bus frequency +#define ROSC_RANDOMBIT_OFFSET _u(0x00000020) +#define ROSC_RANDOMBIT_BITS _u(0x00000001) +#define ROSC_RANDOMBIT_RESET _u(0x00000001) +#define ROSC_RANDOMBIT_MSB _u(0) +#define ROSC_RANDOMBIT_LSB _u(0) +#define ROSC_RANDOMBIT_ACCESS "RO" +// ============================================================================= +// Register : ROSC_COUNT +// Description : A down counter running at the ROSC frequency which counts to +// zero and stops. +// To start the counter write a non-zero value. +// Can be used for short software pauses when setting up time +// sensitive hardware. +#define ROSC_COUNT_OFFSET _u(0x00000024) +#define ROSC_COUNT_BITS _u(0x0000ffff) +#define ROSC_COUNT_RESET _u(0x00000000) +#define ROSC_COUNT_MSB _u(15) +#define ROSC_COUNT_LSB _u(0) +#define ROSC_COUNT_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_ROSC_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/rp_ap.h b/lib/pico-sdk/rp2350/hardware/regs/rp_ap.h new file mode 100644 index 000000000000..ff45438c1f40 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/rp_ap.h @@ -0,0 +1,729 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : RP_AP +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_RP_AP_H +#define _HARDWARE_REGS_RP_AP_H +// ============================================================================= +// Register : RP_AP_CTRL +// Description : This register is primarily used for DFT but can also be used to +// overcome some power up problems. However, it should not be used +// to force power up of domains. Use DBG_POW_OVRD for that. +#define RP_AP_CTRL_OFFSET _u(0x00000000) +#define RP_AP_CTRL_BITS _u(0xc000007f) +#define RP_AP_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_RESCUE_RESTART +// Description : Allows debug of boot problems by restarting the chip with +// minimal boot code execution. Write to 1 to put the chip in +// reset then write to 0 to restart the chip with the rescue flag +// set. The rescue flag is in the POWMAN_CHIP_RESET register and +// is read by boot code. The rescue flag is cleared by writing 0 +// to POWMAN_CHIP_RESET_RESCUE_FLAG or by resetting the chip by +// any means other than RESCUE_RESTART. +#define RP_AP_CTRL_RESCUE_RESTART_RESET _u(0x0) +#define RP_AP_CTRL_RESCUE_RESTART_BITS _u(0x80000000) +#define RP_AP_CTRL_RESCUE_RESTART_MSB _u(31) +#define RP_AP_CTRL_RESCUE_RESTART_LSB _u(31) +#define RP_AP_CTRL_RESCUE_RESTART_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_SPARE +// Description : Unused +#define RP_AP_CTRL_SPARE_RESET _u(0x0) +#define RP_AP_CTRL_SPARE_BITS _u(0x40000000) +#define RP_AP_CTRL_SPARE_MSB _u(30) +#define RP_AP_CTRL_SPARE_LSB _u(30) +#define RP_AP_CTRL_SPARE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_DBG_FRCE_GPIO_LPCK +// Description : Allows chip start-up when the Low Power Oscillator (LPOSC) is +// inoperative or malfunctioning and also allows the initial power +// sequencing rate to be adjusted. Write to 1 to force the LPOSC +// output to be driven from a GPIO (gpio20 on 80-pin package, +// gpio34 on the 60-pin package). If the LPOSC is inoperative or +// malfunctioning it may also be necessary to set the +// LPOSC_STABLE_FRCE bit in this register. The user must provide a +// clock on the GPIO. For normal operation use a clock running at +// around 32kHz. Adjusting the frequency will speed up or slow +// down the initial power-up sequence. +#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_RESET _u(0x0) +#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_BITS _u(0x00000040) +#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_MSB _u(6) +#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_LSB _u(6) +#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_LPOSC_STABLE_FRCE +// Description : Allows the chip to start-up even though the Low Power +// Oscillator (LPOSC) is failing to set its stable flag. Initial +// power sequencing is clocked by LPOSC at around 32kHz but does +// not start until the LPOSC declares itself to be stable. If the +// LPOSC is otherwise working correctly the chip will boot when +// this bit is set. If the LPOSC is not working then +// DBG_FRCE_GPIO_LPCK must be set and an external clock provided. +#define RP_AP_CTRL_LPOSC_STABLE_FRCE_RESET _u(0x0) +#define RP_AP_CTRL_LPOSC_STABLE_FRCE_BITS _u(0x00000020) +#define RP_AP_CTRL_LPOSC_STABLE_FRCE_MSB _u(5) +#define RP_AP_CTRL_LPOSC_STABLE_FRCE_LSB _u(5) +#define RP_AP_CTRL_LPOSC_STABLE_FRCE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_POWMAN_DFT_ISO_OFF +// Description : Holds the isolation gates between power domains in the open +// state. This is intended to hold the gates open for DFT and +// power manager debug. It is not intended to force the isolation +// gates open. Use the overrides in DBG_POW_OVRD to force the +// isolation gates open or closed. +#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_RESET _u(0x0) +#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_BITS _u(0x00000010) +#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_MSB _u(4) +#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_LSB _u(4) +#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_POWMAN_DFT_PWRON +// Description : Holds the power switches on for all domains. This is intended +// to keep the power on for DFT and debug, rather than for +// switching the power on. The power switches are not sequenced +// and the sudden demand for current could cause the always-on +// power domain to brown out. This register is in the always-on +// domain therefore chaos could ensue. It is recommended to use +// the DBG_POW_OVRD controls instead. +#define RP_AP_CTRL_POWMAN_DFT_PWRON_RESET _u(0x0) +#define RP_AP_CTRL_POWMAN_DFT_PWRON_BITS _u(0x00000008) +#define RP_AP_CTRL_POWMAN_DFT_PWRON_MSB _u(3) +#define RP_AP_CTRL_POWMAN_DFT_PWRON_LSB _u(3) +#define RP_AP_CTRL_POWMAN_DFT_PWRON_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_POWMAN_DBGMODE +// Description : This prevents the power manager from powering down and +// resetting the switched-core power domain. It is intended for +// DFT and for debugging the power manager after the chip has +// booted. It cannot be used to force initial power on because it +// simultaneously deasserts the reset. +#define RP_AP_CTRL_POWMAN_DBGMODE_RESET _u(0x0) +#define RP_AP_CTRL_POWMAN_DBGMODE_BITS _u(0x00000004) +#define RP_AP_CTRL_POWMAN_DBGMODE_MSB _u(2) +#define RP_AP_CTRL_POWMAN_DBGMODE_LSB _u(2) +#define RP_AP_CTRL_POWMAN_DBGMODE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_JTAG_FUNCSEL +// Description : Multiplexes the JTAG ports onto GPIO0-3 +#define RP_AP_CTRL_JTAG_FUNCSEL_RESET _u(0x0) +#define RP_AP_CTRL_JTAG_FUNCSEL_BITS _u(0x00000002) +#define RP_AP_CTRL_JTAG_FUNCSEL_MSB _u(1) +#define RP_AP_CTRL_JTAG_FUNCSEL_LSB _u(1) +#define RP_AP_CTRL_JTAG_FUNCSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_CTRL_JTAG_TRSTN +// Description : Resets the JTAG module. Active low. +#define RP_AP_CTRL_JTAG_TRSTN_RESET _u(0x0) +#define RP_AP_CTRL_JTAG_TRSTN_BITS _u(0x00000001) +#define RP_AP_CTRL_JTAG_TRSTN_MSB _u(0) +#define RP_AP_CTRL_JTAG_TRSTN_LSB _u(0) +#define RP_AP_CTRL_JTAG_TRSTN_ACCESS "RW" +// ============================================================================= +// Register : RP_AP_DBGKEY +// Description : Serial key load interface (write-only) +#define RP_AP_DBGKEY_OFFSET _u(0x00000004) +#define RP_AP_DBGKEY_BITS _u(0x00000007) +#define RP_AP_DBGKEY_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBGKEY_RESET +// Description : Reset (before sending a new key) +#define RP_AP_DBGKEY_RESET_RESET _u(0x0) +#define RP_AP_DBGKEY_RESET_BITS _u(0x00000004) +#define RP_AP_DBGKEY_RESET_MSB _u(2) +#define RP_AP_DBGKEY_RESET_LSB _u(2) +#define RP_AP_DBGKEY_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBGKEY_PUSH +#define RP_AP_DBGKEY_PUSH_RESET _u(0x0) +#define RP_AP_DBGKEY_PUSH_BITS _u(0x00000002) +#define RP_AP_DBGKEY_PUSH_MSB _u(1) +#define RP_AP_DBGKEY_PUSH_LSB _u(1) +#define RP_AP_DBGKEY_PUSH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBGKEY_DATA +#define RP_AP_DBGKEY_DATA_RESET _u(0x0) +#define RP_AP_DBGKEY_DATA_BITS _u(0x00000001) +#define RP_AP_DBGKEY_DATA_MSB _u(0) +#define RP_AP_DBGKEY_DATA_LSB _u(0) +#define RP_AP_DBGKEY_DATA_ACCESS "RW" +// ============================================================================= +// Register : RP_AP_DBG_POW_STATE_SWCORE +// Description : This register indicates the state of the power sequencer for +// the switched-core domain. +// The sequencer timing is managed by the POWMAN_SEQ_* registers. +// See the header file for those registers for more information on +// the timing. +// Power up of the domain commences by clearing bit 0 (IS_PD) then +// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the +// sequence is complete. +// Power down of the domain commences by clearing bit 8 (IS_PU) +// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then +// set to indicate the sequence is complete. +// Bits 9-11 describe the states of the power manager clocks which +// change as clock generators in the switched-core become +// available following switched-core power up. +// This bus can be sent to GPIO for debug. See +// DBG_POW_OUTPUT_TO_GPIO in the DBG_POW_OVRD register. +#define RP_AP_DBG_POW_STATE_SWCORE_OFFSET _u(0x00000008) +#define RP_AP_DBG_POW_STATE_SWCORE_BITS _u(0x00000fff) +#define RP_AP_DBG_POW_STATE_SWCORE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK +// Description : Indicates the source of the power manager clock. On switched- +// core power up the clock switches from the LPOSC to clk_ref and +// this flag will be set. clk_ref will be running from the ROSC +// initially but will switch to XOSC when it comes available. On +// switched-core power down the clock switches to LPOSC and this +// flag will be cleared. +#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_BITS _u(0x00000800) +#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_MSB _u(11) +#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_LSB _u(11) +#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK +// Description : Indicates the switched-core power sequencer is waiting for the +// power manager clock to update. On switched-core power up the +// clock switches from the LPOSC to clk_ref. clk_ref will be +// running from the ROSC initially but will switch to XOSC when it +// comes available. On switched-core power down the clock switches +// to LPOSC. +// If the switched-core power up sequence stalls with this flag +// active then it means clk_ref is not running which indicates a +// problem with the ROSC. If that happens then set +// DBG_POW_RESTART_FROM_XOSC in the DBG_POW_OVRD register to avoid +// using the ROSC. +// If the switched-core power down sequence stalls with this flag +// active then it means LPOSC is not running. The solution is to +// not stop LPOSC when the switched-core power domain is powered. +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_BITS _u(0x00000400) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_MSB _u(10) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_LSB _u(10) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK +// Description : Indicates that the switched-core power sequencer is waiting for +// the AON-Timer to update. On switched-core power-up there is +// nothing to be done. The AON-Timer continues to run from the +// LPOSC so this flag will not be set. Software decides whether to +// switch the AON-Timer clock to XOSC (via clk_ref). On switched- +// core power-down the sequencer will switch the AON-Timer back to +// LPOSC if software switched it to XOSC. During the switchover +// the WAITING_TIMCK flag will be set. If the switched-core power +// down sequence stalls with this flag active then the only +// recourse is to reset the chip and change software to not select +// XOSC as the AON-Timer source. +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_BITS _u(0x00000200) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_MSB _u(9) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_LSB _u(9) +#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_IS_PU +// Description : Indicates the power somain is fully powered up. +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_BITS _u(0x00000100) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_MSB _u(8) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_LSB _u(8) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ +// Description : Indicates the state of the reset to the power domain. +#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_BITS _u(0x00000080) +#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_MSB _u(7) +#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_LSB _u(7) +#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK +// Description : Indicates the state of the enable to the power domain. +#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_BITS _u(0x00000040) +#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_MSB _u(6) +#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_LSB _u(6) +#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ +// Description : Indicates the state of the isolation control to the power +// domain. +#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_BITS _u(0x00000020) +#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_MSB _u(5) +#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_LSB _u(5) +#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK +// Description : Indicates the state of the large power switches for the power +// domain. +#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_BITS _u(0x00000010) +#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_MSB _u(4) +#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_LSB _u(4) +#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2 +// Description : The small switches are split into 3 chains. In the power up +// sequence they are switched on separately to allow management of +// the VDD rise time. In the power down sequence they switch off +// simultaneously with the large power switches. +// This bit indicates the state of the last element in small power +// switch chain 2. +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_BITS _u(0x00000008) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_MSB _u(3) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_LSB _u(3) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1 +// Description : This bit indicates the state of the last element in small power +// switch chain 1. +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_BITS _u(0x00000004) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_MSB _u(2) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_LSB _u(2) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0 +// Description : This bit indicates the state of the last element in small power +// switch chain 0. +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_BITS _u(0x00000002) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_MSB _u(1) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_LSB _u(1) +#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SWCORE_IS_PD +// Description : Indicates the power somain is fully powered down. +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_BITS _u(0x00000001) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_MSB _u(0) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_LSB _u(0) +#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_ACCESS "RO" +// ============================================================================= +// Register : RP_AP_DBG_POW_STATE_XIP +// Description : This register indicates the state of the power sequencer for +// the XIP domain. +// The sequencer timing is managed by the POWMAN_SEQ_* registers. +// See the header file for those registers for more information on +// the timing. +// Power up of the domain commences by clearing bit 0 (IS_PD) then +// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the +// sequence is complete. +// Power down of the domain commences by clearing bit 8 (IS_PU) +// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then +// set to indicate the sequence is complete. +#define RP_AP_DBG_POW_STATE_XIP_OFFSET _u(0x0000000c) +#define RP_AP_DBG_POW_STATE_XIP_BITS _u(0x000001ff) +#define RP_AP_DBG_POW_STATE_XIP_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_IS_PU +// Description : Indicates the power somain is fully powered up. +#define RP_AP_DBG_POW_STATE_XIP_IS_PU_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_IS_PU_BITS _u(0x00000100) +#define RP_AP_DBG_POW_STATE_XIP_IS_PU_MSB _u(8) +#define RP_AP_DBG_POW_STATE_XIP_IS_PU_LSB _u(8) +#define RP_AP_DBG_POW_STATE_XIP_IS_PU_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ +// Description : Indicates the state of the reset to the power domain. +#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_BITS _u(0x00000080) +#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_MSB _u(7) +#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_LSB _u(7) +#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_ENAB_ACK +// Description : Indicates the state of the enable to the power domain. +#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_BITS _u(0x00000040) +#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_MSB _u(6) +#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_LSB _u(6) +#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ +// Description : Indicates the state of the isolation control to the power +// domain. +#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_BITS _u(0x00000020) +#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_MSB _u(5) +#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_LSB _u(5) +#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_LARGE_ACK +// Description : Indicates the state of the large power switches for the power +// domain. +#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_BITS _u(0x00000010) +#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_MSB _u(4) +#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_LSB _u(4) +#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2 +// Description : The small switches are split into 3 chains. In the power up +// sequence they are switched on separately to allow management of +// the VDD rise time. In the power down sequence they switch off +// simultaneously with the large power switches. +// This bit indicates the state of the last element in small power +// switch chain 2. +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_BITS _u(0x00000008) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_MSB _u(3) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_LSB _u(3) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1 +// Description : This bit indicates the state of the last element in small power +// switch chain 1. +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_BITS _u(0x00000004) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_MSB _u(2) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_LSB _u(2) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0 +// Description : This bit indicates the state of the last element in small power +// switch chain 0. +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_BITS _u(0x00000002) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_MSB _u(1) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_LSB _u(1) +#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_XIP_IS_PD +// Description : Indicates the power somain is fully powered down. +#define RP_AP_DBG_POW_STATE_XIP_IS_PD_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_XIP_IS_PD_BITS _u(0x00000001) +#define RP_AP_DBG_POW_STATE_XIP_IS_PD_MSB _u(0) +#define RP_AP_DBG_POW_STATE_XIP_IS_PD_LSB _u(0) +#define RP_AP_DBG_POW_STATE_XIP_IS_PD_ACCESS "RO" +// ============================================================================= +// Register : RP_AP_DBG_POW_STATE_SRAM0 +// Description : This register indicates the state of the power sequencer for +// the SRAM0 domain. +// The sequencer timing is managed by the POWMAN_SEQ_* registers. +// See the header file for those registers for more information on +// the timing. +// Power up of the domain commences by clearing bit 0 (IS_PD) then +// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the +// sequence is complete. +// Power down of the domain commences by clearing bit 8 (IS_PU) +// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then +// set to indicate the sequence is complete. +#define RP_AP_DBG_POW_STATE_SRAM0_OFFSET _u(0x00000010) +#define RP_AP_DBG_POW_STATE_SRAM0_BITS _u(0x000001ff) +#define RP_AP_DBG_POW_STATE_SRAM0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_IS_PU +// Description : Indicates the power somain is fully powered up. +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_BITS _u(0x00000100) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_MSB _u(8) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_LSB _u(8) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ +// Description : Indicates the state of the reset to the power domain. +#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_BITS _u(0x00000080) +#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_MSB _u(7) +#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_LSB _u(7) +#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK +// Description : Indicates the state of the enable to the power domain. +#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_BITS _u(0x00000040) +#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_MSB _u(6) +#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_LSB _u(6) +#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ +// Description : Indicates the state of the isolation control to the power +// domain. +#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_BITS _u(0x00000020) +#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_MSB _u(5) +#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_LSB _u(5) +#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK +// Description : Indicates the state of the large power switches for the power +// domain. +#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_BITS _u(0x00000010) +#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_MSB _u(4) +#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_LSB _u(4) +#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2 +// Description : The small switches are split into 3 chains. In the power up +// sequence they are switched on separately to allow management of +// the VDD rise time. In the power down sequence they switch off +// simultaneously with the large power switches. +// This bit indicates the state of the last element in small power +// switch chain 2. +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_BITS _u(0x00000008) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_MSB _u(3) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_LSB _u(3) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1 +// Description : This bit indicates the state of the last element in small power +// switch chain 1. +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_BITS _u(0x00000004) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_MSB _u(2) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_LSB _u(2) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0 +// Description : This bit indicates the state of the last element in small power +// switch chain 0. +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_BITS _u(0x00000002) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_MSB _u(1) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_LSB _u(1) +#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM0_IS_PD +// Description : Indicates the power somain is fully powered down. +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_BITS _u(0x00000001) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_MSB _u(0) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_LSB _u(0) +#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_ACCESS "RO" +// ============================================================================= +// Register : RP_AP_DBG_POW_STATE_SRAM1 +// Description : This register indicates the state of the power sequencer for +// the SRAM1 domain. +// The sequencer timing is managed by the POWMAN_SEQ_* registers. +// See the header file for those registers for more information on +// the timing. +// Power up of the domain commences by clearing bit 0 (IS_PD) then +// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the +// sequence is complete. +// Power down of the domain commences by clearing bit 8 (IS_PU) +// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then +// set to indicate the sequence is complete. +#define RP_AP_DBG_POW_STATE_SRAM1_OFFSET _u(0x00000014) +#define RP_AP_DBG_POW_STATE_SRAM1_BITS _u(0x000001ff) +#define RP_AP_DBG_POW_STATE_SRAM1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_IS_PU +// Description : Indicates the power somain is fully powered up. +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_BITS _u(0x00000100) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_MSB _u(8) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_LSB _u(8) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ +// Description : Indicates the state of the reset to the power domain. +#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_BITS _u(0x00000080) +#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_MSB _u(7) +#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_LSB _u(7) +#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK +// Description : Indicates the state of the enable to the power domain. +#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_BITS _u(0x00000040) +#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_MSB _u(6) +#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_LSB _u(6) +#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ +// Description : Indicates the state of the isolation control to the power +// domain. +#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_BITS _u(0x00000020) +#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_MSB _u(5) +#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_LSB _u(5) +#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK +// Description : Indicates the state of the large power switches for the power +// domain. +#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_BITS _u(0x00000010) +#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_MSB _u(4) +#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_LSB _u(4) +#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2 +// Description : The small switches are split into 3 chains. In the power up +// sequence they are switched on separately to allow management of +// the VDD rise time. In the power down sequence they switch off +// simultaneously with the large power switches. +// This bit indicates the state of the last element in small power +// switch chain 2. +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_BITS _u(0x00000008) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_MSB _u(3) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_LSB _u(3) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1 +// Description : This bit indicates the state of the last element in small power +// switch chain 1. +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_BITS _u(0x00000004) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_MSB _u(2) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_LSB _u(2) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0 +// Description : This bit indicates the state of the last element in small power +// switch chain 0. +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_BITS _u(0x00000002) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_MSB _u(1) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_LSB _u(1) +#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_STATE_SRAM1_IS_PD +// Description : Indicates the power somain is fully powered down. +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_RESET _u(0x0) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_BITS _u(0x00000001) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_MSB _u(0) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_LSB _u(0) +#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_ACCESS "RO" +// ============================================================================= +// Register : RP_AP_DBG_POW_OVRD +// Description : This register allows external control of the power sequencer +// outputs for all the switched power domains. If any of the power +// sequencers stall at any stage then force power up operation of +// all domains by running this sequence: +// - set DBG_POW_OVRD = 0x3b to force small power switches on, +// large power switches off, resets on and isolation on +// - allow time for the domain power supplies to reach full rail +// - set DBG_POW_OVRD = 0x3b to force large power switches on +// - set DBG_POW_OVRD = 0x37 to remove isolation +// - set DBG_POW_OVRD = 0x17 to remove resets +#define RP_AP_DBG_POW_OVRD_OFFSET _u(0x00000018) +#define RP_AP_DBG_POW_OVRD_BITS _u(0x0000007f) +#define RP_AP_DBG_POW_OVRD_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC +// Description : By default the system begins boot as soon as a clock is +// available from the ROSC, then it switches to the XOSC when it +// is available. This is done because the XOSC takes several ms to +// start up. If there is a problem with the ROSC then the default +// behaviour can be changed to not use the ROSC and wait for XOSC. +// However, this requires a mask change to modify the reset value +// of the Power Manager START_FROM_XOSC register. To allow +// experimentation the default can be temporarily changed by +// setting this register bit to 1. After setting this bit the core +// must be reset by a Coresight dprst or a rescue reset (see +// RESCUE_RESTART in the RP_AP_CTRL register above). A power-on +// reset, brown-out reset or RUN pin reset will reset this control +// and revert to the default behaviour. +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_RESET _u(0x0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_BITS _u(0x00000040) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_MSB _u(6) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_LSB _u(6) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OVRD_DBG_POW_RESET +// Description : When DBG_POW_OVRD_RESET=1 this register bit controls the resets +// for all domains. 1 = reset. 0 = not reset. +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_RESET _u(0x0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_BITS _u(0x00000020) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_MSB _u(5) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_LSB _u(5) +#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET +// Description : Enables DBG_POW_RESET to control the resets for the power +// manager and the switched-core. Essentially that is everythjing +// except the Coresight 2-wire interface and the RP_AP registers. +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_RESET _u(0x0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_BITS _u(0x00000010) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_MSB _u(4) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_LSB _u(4) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OVRD_DBG_POW_ISO +// Description : When DBG_POW_OVRD_ISO=1 this register bit controls the +// isolation gates for all domains. 1 = isolated. 0 = not +// isolated. +#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_RESET _u(0x0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_BITS _u(0x00000008) +#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_MSB _u(3) +#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_LSB _u(3) +#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO +// Description : Enables DBG_POW_ISO to control the isolation gates between +// domains. +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_RESET _u(0x0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_BITS _u(0x00000004) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_MSB _u(2) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_LSB _u(2) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ +// Description : Turn on the large power switches for all domains. This should +// not be done until sufficient time has been allowed for the +// small switches to bring the supplies up. Switching the large +// switches on too soon risks browning out the always-on domain +// and corrupting these very registers. +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_RESET _u(0x0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_BITS _u(0x00000002) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_MSB _u(1) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_LSB _u(1) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ +// Description : Turn on the small power switches for all domains. This switches +// on chain 0 for each domain and switches off chains 2 & 3 and +// the large power switch chain. This will bring the power up for +// all domains without browning out the always-on power domain. +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_RESET _u(0x0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_BITS _u(0x00000001) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_MSB _u(0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_LSB _u(0) +#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_ACCESS "RW" +// ============================================================================= +// Register : RP_AP_DBG_POW_OUTPUT_TO_GPIO +// Description : Send some, or all, bits of DBG_POW_STATE_SWCORE to gpios. +// Bit 0 sends bit 0 of DBG_POW_STATE_SWCORE to GPIO 34 +// Bit 1 sends bit 1 of DBG_POW_STATE_SWCORE to GPIO 35 +// Bit 2 sends bit 2 of DBG_POW_STATE_SWCORE to GPIO 36 +// . +// . +// Bit 11 sends bit 11 of DBG_POW_STATE_SWCORE to GPIO 45 +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_OFFSET _u(0x0000001c) +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_BITS _u(0x00000fff) +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_RESET _u(0x000) +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_BITS _u(0x00000fff) +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_MSB _u(11) +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_LSB _u(0) +#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : RP_AP_IDR +// Description : Standard Coresight ID Register +#define RP_AP_IDR_OFFSET _u(0x00000dfc) +#define RP_AP_IDR_BITS _u(0xffffffff) +#define RP_AP_IDR_RESET "-" +#define RP_AP_IDR_MSB _u(31) +#define RP_AP_IDR_LSB _u(0) +#define RP_AP_IDR_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_RP_AP_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/rvcsr.h b/lib/pico-sdk/rp2350/hardware/regs/rvcsr.h new file mode 100644 index 000000000000..f5ff378ab725 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/rvcsr.h @@ -0,0 +1,3154 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : RVCSR +// Version : 1 +// Bus type : apb +// Description : CSR listing for Hazard3 +// ============================================================================= +#ifndef _HARDWARE_REGS_RVCSR_H +#define _HARDWARE_REGS_RVCSR_H +// ============================================================================= +// Register : RVCSR_MSTATUS +// Description : Machine status register +#define RVCSR_MSTATUS_OFFSET _u(0x00000300) +#define RVCSR_MSTATUS_BITS _u(0x00221888) +#define RVCSR_MSTATUS_RESET _u(0x00001800) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSTATUS_TW +// Description : Timeout wait. When 1, attempting to execute a WFI instruction +// in U-mode will instantly cause an illegal instruction +// exception. +#define RVCSR_MSTATUS_TW_RESET _u(0x0) +#define RVCSR_MSTATUS_TW_BITS _u(0x00200000) +#define RVCSR_MSTATUS_TW_MSB _u(21) +#define RVCSR_MSTATUS_TW_LSB _u(21) +#define RVCSR_MSTATUS_TW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSTATUS_MPRV +// Description : Modify privilege. If 1, loads and stores behave as though the +// current privilege level were `mpp`. This includes physical +// memory protection checks, and the privilege level asserted on +// the system bus alongside the load/store address. +#define RVCSR_MSTATUS_MPRV_RESET _u(0x0) +#define RVCSR_MSTATUS_MPRV_BITS _u(0x00020000) +#define RVCSR_MSTATUS_MPRV_MSB _u(17) +#define RVCSR_MSTATUS_MPRV_LSB _u(17) +#define RVCSR_MSTATUS_MPRV_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSTATUS_MPP +// Description : Previous privilege level. Can store the values 3 (M-mode) or 0 +// (U-mode). If another value is written, hardware rounds to the +// nearest supported mode. +#define RVCSR_MSTATUS_MPP_RESET _u(0x3) +#define RVCSR_MSTATUS_MPP_BITS _u(0x00001800) +#define RVCSR_MSTATUS_MPP_MSB _u(12) +#define RVCSR_MSTATUS_MPP_LSB _u(11) +#define RVCSR_MSTATUS_MPP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSTATUS_MPIE +// Description : Previous interrupt enable. Readable and writable. Is set to the +// current value of `mstatus.mie` on trap entry. Is set to 1 on +// trap return. +#define RVCSR_MSTATUS_MPIE_RESET _u(0x0) +#define RVCSR_MSTATUS_MPIE_BITS _u(0x00000080) +#define RVCSR_MSTATUS_MPIE_MSB _u(7) +#define RVCSR_MSTATUS_MPIE_LSB _u(7) +#define RVCSR_MSTATUS_MPIE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSTATUS_MIE +// Description : Interrupt enable. Readable and writable. Is set to 0 on trap +// entry. Is set to the current value of `mstatus.mpie` on trap +// return. +#define RVCSR_MSTATUS_MIE_RESET _u(0x0) +#define RVCSR_MSTATUS_MIE_BITS _u(0x00000008) +#define RVCSR_MSTATUS_MIE_MSB _u(3) +#define RVCSR_MSTATUS_MIE_LSB _u(3) +#define RVCSR_MSTATUS_MIE_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MISA +// Description : Summary of ISA extension support +// +// On RP2350, Hazard3's full `-march` string is: +// `rv32ima_zicsr_zifencei_zba_zbb_zbs_zbkb_zca_zcb_zcmp` +// +// Note Zca is equivalent to the C extension in this case; all +// instructions from the RISC-V C extension relevant to a 32-bit +// non-floating-point processor are supported. On older toolchains +// which do not support the Zc extensions, the appropriate +// `-march` string is: `rv32imac_zicsr_zifencei_zba_zbb_zbs_zbkb` +// +// In addition the following custom extensions are configured: +// Xh3bm, Xh3power, Xh3irq, Xh3pmpm +#define RVCSR_MISA_OFFSET _u(0x00000301) +#define RVCSR_MISA_BITS _u(0xc0901107) +#define RVCSR_MISA_RESET _u(0x40901105) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_MXL +// Description : Value of 0x1 indicates this is a 32-bit processor. +#define RVCSR_MISA_MXL_RESET _u(0x1) +#define RVCSR_MISA_MXL_BITS _u(0xc0000000) +#define RVCSR_MISA_MXL_MSB _u(31) +#define RVCSR_MISA_MXL_LSB _u(30) +#define RVCSR_MISA_MXL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_X +// Description : Value of 1 indicates nonstandard extensions are present. (Xh3b +// bit manipulation, and custom sleep and interrupt control CSRs) +#define RVCSR_MISA_X_RESET _u(0x1) +#define RVCSR_MISA_X_BITS _u(0x00800000) +#define RVCSR_MISA_X_MSB _u(23) +#define RVCSR_MISA_X_LSB _u(23) +#define RVCSR_MISA_X_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_U +// Description : Value of 1 indicates U-mode is implemented. +#define RVCSR_MISA_U_RESET _u(0x1) +#define RVCSR_MISA_U_BITS _u(0x00100000) +#define RVCSR_MISA_U_MSB _u(20) +#define RVCSR_MISA_U_LSB _u(20) +#define RVCSR_MISA_U_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_M +// Description : Value of 1 indicates the M extension (integer multiply/divide) +// is implemented. +#define RVCSR_MISA_M_RESET _u(0x1) +#define RVCSR_MISA_M_BITS _u(0x00001000) +#define RVCSR_MISA_M_MSB _u(12) +#define RVCSR_MISA_M_LSB _u(12) +#define RVCSR_MISA_M_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_I +// Description : Value of 1 indicates the RVI base ISA is implemented (as +// opposed to RVE) +#define RVCSR_MISA_I_RESET _u(0x1) +#define RVCSR_MISA_I_BITS _u(0x00000100) +#define RVCSR_MISA_I_MSB _u(8) +#define RVCSR_MISA_I_LSB _u(8) +#define RVCSR_MISA_I_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_C +// Description : Value of 1 indicates the C extension (compressed instructions) +// is implemented. +#define RVCSR_MISA_C_RESET _u(0x1) +#define RVCSR_MISA_C_BITS _u(0x00000004) +#define RVCSR_MISA_C_MSB _u(2) +#define RVCSR_MISA_C_LSB _u(2) +#define RVCSR_MISA_C_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_B +// Description : Value of 1 indicates the B extension (bit manipulation) is +// implemented. B is the combination of Zba, Zbb and Zbs. +// +// Hazard3 implements all of these extensions, but the definition +// of B as ZbaZbbZbs did not exist at the point this version of +// Hazard3 was taped out. This bit was reserved-0 at that point. +// Therefore this bit reads as 0. +#define RVCSR_MISA_B_RESET _u(0x0) +#define RVCSR_MISA_B_BITS _u(0x00000002) +#define RVCSR_MISA_B_MSB _u(1) +#define RVCSR_MISA_B_LSB _u(1) +#define RVCSR_MISA_B_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MISA_A +// Description : Value of 1 indicates the A extension (atomics) is implemented. +#define RVCSR_MISA_A_RESET _u(0x1) +#define RVCSR_MISA_A_BITS _u(0x00000001) +#define RVCSR_MISA_A_MSB _u(0) +#define RVCSR_MISA_A_LSB _u(0) +#define RVCSR_MISA_A_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MEDELEG +// Description : Machine exception delegation register. Not implemented, as no +// S-mode support. +#define RVCSR_MEDELEG_OFFSET _u(0x00000302) +#define RVCSR_MEDELEG_BITS _u(0xffffffff) +#define RVCSR_MEDELEG_RESET "-" +#define RVCSR_MEDELEG_MSB _u(31) +#define RVCSR_MEDELEG_LSB _u(0) +#define RVCSR_MEDELEG_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MIDELEG +// Description : Machine interrupt delegation register. Not implemented, as no +// S-mode support. +#define RVCSR_MIDELEG_OFFSET _u(0x00000303) +#define RVCSR_MIDELEG_BITS _u(0xffffffff) +#define RVCSR_MIDELEG_RESET "-" +#define RVCSR_MIDELEG_MSB _u(31) +#define RVCSR_MIDELEG_LSB _u(0) +#define RVCSR_MIDELEG_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MIE +// Description : Machine interrupt enable register +#define RVCSR_MIE_OFFSET _u(0x00000304) +#define RVCSR_MIE_BITS _u(0x00000888) +#define RVCSR_MIE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MIE_MEIE +// Description : External interrupt enable. The processor transfers to the +// external interrupt vector when `mie.meie`, `mip.meip` and +// `mstatus.mie` are all 1. +// +// Hazard3 has internal registers to individually filter external +// interrupts (see `meiea`), but this standard control can be used +// to mask all external interrupts at once. +#define RVCSR_MIE_MEIE_RESET _u(0x0) +#define RVCSR_MIE_MEIE_BITS _u(0x00000800) +#define RVCSR_MIE_MEIE_MSB _u(11) +#define RVCSR_MIE_MEIE_LSB _u(11) +#define RVCSR_MIE_MEIE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MIE_MTIE +// Description : Timer interrupt enable. The processor transfers to the timer +// interrupt vector when `mie.mtie`, `mip.mtip` and `mstatus.mie` +// are all 1, unless a software or external interrupt request is +// also valid at this time. +#define RVCSR_MIE_MTIE_RESET _u(0x0) +#define RVCSR_MIE_MTIE_BITS _u(0x00000080) +#define RVCSR_MIE_MTIE_MSB _u(7) +#define RVCSR_MIE_MTIE_LSB _u(7) +#define RVCSR_MIE_MTIE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MIE_MSIE +// Description : Software interrupt enable. The processor transfers to the +// software interrupt vector `mie.msie`, `mip.msip` and +// `mstatus.mie` are all 1, unless an external interrupt request +// is also valid at this time. +#define RVCSR_MIE_MSIE_RESET _u(0x0) +#define RVCSR_MIE_MSIE_BITS _u(0x00000008) +#define RVCSR_MIE_MSIE_MSB _u(3) +#define RVCSR_MIE_MSIE_LSB _u(3) +#define RVCSR_MIE_MSIE_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MTVEC +// Description : Machine trap handler base address. +#define RVCSR_MTVEC_OFFSET _u(0x00000305) +#define RVCSR_MTVEC_BITS _u(0xffffffff) +#define RVCSR_MTVEC_RESET _u(0x00007ffc) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MTVEC_BASE +// Description : The upper 30 bits of the trap vector address (2 LSBs are +// implicitly 0). Must be 64-byte-aligned if vectoring is enabled. +// Otherwise, must be 4-byte-aligned. +#define RVCSR_MTVEC_BASE_RESET _u(0x00001fff) +#define RVCSR_MTVEC_BASE_BITS _u(0xfffffffc) +#define RVCSR_MTVEC_BASE_MSB _u(31) +#define RVCSR_MTVEC_BASE_LSB _u(2) +#define RVCSR_MTVEC_BASE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MTVEC_MODE +// Description : If 0 (direct mode), all traps set pc to the trap vector base. +// If 1 (vectored), exceptions set pc to the trap vector base, and +// interrupts set pc to 4 times the interrupt cause (3=soft IRQ, +// 7=timer IRQ, 11=external IRQ). +// +// The upper bit is hardwired to zero, so attempting to set mode +// to 2 or 3 will result in a value of 0 or 1 respectively. +// 0x0 -> Direct entry to mtvec +// 0x1 -> Vectored entry to a 16-entry jump table starting at mtvec +#define RVCSR_MTVEC_MODE_RESET _u(0x0) +#define RVCSR_MTVEC_MODE_BITS _u(0x00000003) +#define RVCSR_MTVEC_MODE_MSB _u(1) +#define RVCSR_MTVEC_MODE_LSB _u(0) +#define RVCSR_MTVEC_MODE_ACCESS "RW" +#define RVCSR_MTVEC_MODE_VALUE_DIRECT _u(0x0) +#define RVCSR_MTVEC_MODE_VALUE_VECTORED _u(0x1) +// ============================================================================= +// Register : RVCSR_MCOUNTEREN +// Description : Counter enable. Control access to counters from U-mode. Not to +// be confused with mcountinhibit. +#define RVCSR_MCOUNTEREN_OFFSET _u(0x00000306) +#define RVCSR_MCOUNTEREN_BITS _u(0x00000007) +#define RVCSR_MCOUNTEREN_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MCOUNTEREN_IR +// Description : If 1, U-mode is permitted to access the `instret`/`instreth` +// instruction retire counter CSRs. Otherwise, U-mode accesses to +// these CSRs will trap. +#define RVCSR_MCOUNTEREN_IR_RESET _u(0x0) +#define RVCSR_MCOUNTEREN_IR_BITS _u(0x00000004) +#define RVCSR_MCOUNTEREN_IR_MSB _u(2) +#define RVCSR_MCOUNTEREN_IR_LSB _u(2) +#define RVCSR_MCOUNTEREN_IR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MCOUNTEREN_TM +// Description : No hardware effect, as the `time`/`timeh` CSRs are not +// implemented. However, this field still exists, as M-mode +// software can use it to track whether it should emulate U-mode +// attempts to access those CSRs. +#define RVCSR_MCOUNTEREN_TM_RESET _u(0x0) +#define RVCSR_MCOUNTEREN_TM_BITS _u(0x00000002) +#define RVCSR_MCOUNTEREN_TM_MSB _u(1) +#define RVCSR_MCOUNTEREN_TM_LSB _u(1) +#define RVCSR_MCOUNTEREN_TM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MCOUNTEREN_CY +// Description : If 1, U-mode is permitted to access the `cycle`/`cycleh` cycle +// counter CSRs. Otherwise, U-mode accesses to these CSRs will +// trap. +#define RVCSR_MCOUNTEREN_CY_RESET _u(0x0) +#define RVCSR_MCOUNTEREN_CY_BITS _u(0x00000001) +#define RVCSR_MCOUNTEREN_CY_MSB _u(0) +#define RVCSR_MCOUNTEREN_CY_LSB _u(0) +#define RVCSR_MCOUNTEREN_CY_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MENVCFG +// Description : Machine environment configuration register, low half +#define RVCSR_MENVCFG_OFFSET _u(0x0000030a) +#define RVCSR_MENVCFG_BITS _u(0x00000001) +#define RVCSR_MENVCFG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MENVCFG_FIOM +// Description : When set, fence instructions in modes less privileged than +// M-mode which specify that IO memory accesses are ordered will +// also cause ordering of main memory accesses. +// +// FIOM is hardwired to zero on Hazard3, because S-mode is not +// supported, and because fence instructions execute as NOPs (with +// the exception of `fence.i`) +#define RVCSR_MENVCFG_FIOM_RESET _u(0x0) +#define RVCSR_MENVCFG_FIOM_BITS _u(0x00000001) +#define RVCSR_MENVCFG_FIOM_MSB _u(0) +#define RVCSR_MENVCFG_FIOM_LSB _u(0) +#define RVCSR_MENVCFG_FIOM_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MSTATUSH +// Description : High half of mstatus, hardwired to 0. +#define RVCSR_MSTATUSH_OFFSET _u(0x00000310) +#define RVCSR_MSTATUSH_BITS _u(0xffffffff) +#define RVCSR_MSTATUSH_RESET _u(0x00000000) +#define RVCSR_MSTATUSH_MSB _u(31) +#define RVCSR_MSTATUSH_LSB _u(0) +#define RVCSR_MSTATUSH_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MENVCFGH +// Description : Machine environment configuration register, high half +// +// This register is fully reserved, as Hazard3 does not implement +// the relevant extensions. It is implemented as hardwired-0. +#define RVCSR_MENVCFGH_OFFSET _u(0x0000031a) +#define RVCSR_MENVCFGH_BITS _u(0x00000000) +#define RVCSR_MENVCFGH_RESET _u(0x00000000) +#define RVCSR_MENVCFGH_MSB _u(31) +#define RVCSR_MENVCFGH_LSB _u(0) +#define RVCSR_MENVCFGH_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MCOUNTINHIBIT +// Description : Count inhibit register for `mcycle`/`minstret` +#define RVCSR_MCOUNTINHIBIT_OFFSET _u(0x00000320) +#define RVCSR_MCOUNTINHIBIT_BITS _u(0x00000005) +#define RVCSR_MCOUNTINHIBIT_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MCOUNTINHIBIT_IR +// Description : Inhibit counting of the `minstret` and `minstreth` registers. +// Set by default to save power. +#define RVCSR_MCOUNTINHIBIT_IR_RESET _u(0x1) +#define RVCSR_MCOUNTINHIBIT_IR_BITS _u(0x00000004) +#define RVCSR_MCOUNTINHIBIT_IR_MSB _u(2) +#define RVCSR_MCOUNTINHIBIT_IR_LSB _u(2) +#define RVCSR_MCOUNTINHIBIT_IR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MCOUNTINHIBIT_CY +// Description : Inhibit counting of the `mcycle` and `mcycleh` registers. Set +// by default to save power. +#define RVCSR_MCOUNTINHIBIT_CY_RESET _u(0x1) +#define RVCSR_MCOUNTINHIBIT_CY_BITS _u(0x00000001) +#define RVCSR_MCOUNTINHIBIT_CY_MSB _u(0) +#define RVCSR_MCOUNTINHIBIT_CY_LSB _u(0) +#define RVCSR_MCOUNTINHIBIT_CY_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MHPMEVENT3 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT3_OFFSET _u(0x00000323) +#define RVCSR_MHPMEVENT3_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT3_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT3_MSB _u(31) +#define RVCSR_MHPMEVENT3_LSB _u(0) +#define RVCSR_MHPMEVENT3_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT4 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT4_OFFSET _u(0x00000324) +#define RVCSR_MHPMEVENT4_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT4_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT4_MSB _u(31) +#define RVCSR_MHPMEVENT4_LSB _u(0) +#define RVCSR_MHPMEVENT4_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT5 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT5_OFFSET _u(0x00000325) +#define RVCSR_MHPMEVENT5_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT5_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT5_MSB _u(31) +#define RVCSR_MHPMEVENT5_LSB _u(0) +#define RVCSR_MHPMEVENT5_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT6 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT6_OFFSET _u(0x00000326) +#define RVCSR_MHPMEVENT6_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT6_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT6_MSB _u(31) +#define RVCSR_MHPMEVENT6_LSB _u(0) +#define RVCSR_MHPMEVENT6_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT7 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT7_OFFSET _u(0x00000327) +#define RVCSR_MHPMEVENT7_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT7_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT7_MSB _u(31) +#define RVCSR_MHPMEVENT7_LSB _u(0) +#define RVCSR_MHPMEVENT7_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT8 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT8_OFFSET _u(0x00000328) +#define RVCSR_MHPMEVENT8_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT8_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT8_MSB _u(31) +#define RVCSR_MHPMEVENT8_LSB _u(0) +#define RVCSR_MHPMEVENT8_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT9 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT9_OFFSET _u(0x00000329) +#define RVCSR_MHPMEVENT9_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT9_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT9_MSB _u(31) +#define RVCSR_MHPMEVENT9_LSB _u(0) +#define RVCSR_MHPMEVENT9_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT10 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT10_OFFSET _u(0x0000032a) +#define RVCSR_MHPMEVENT10_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT10_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT10_MSB _u(31) +#define RVCSR_MHPMEVENT10_LSB _u(0) +#define RVCSR_MHPMEVENT10_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT11 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT11_OFFSET _u(0x0000032b) +#define RVCSR_MHPMEVENT11_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT11_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT11_MSB _u(31) +#define RVCSR_MHPMEVENT11_LSB _u(0) +#define RVCSR_MHPMEVENT11_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT12 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT12_OFFSET _u(0x0000032c) +#define RVCSR_MHPMEVENT12_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT12_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT12_MSB _u(31) +#define RVCSR_MHPMEVENT12_LSB _u(0) +#define RVCSR_MHPMEVENT12_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT13 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT13_OFFSET _u(0x0000032d) +#define RVCSR_MHPMEVENT13_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT13_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT13_MSB _u(31) +#define RVCSR_MHPMEVENT13_LSB _u(0) +#define RVCSR_MHPMEVENT13_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT14 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT14_OFFSET _u(0x0000032e) +#define RVCSR_MHPMEVENT14_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT14_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT14_MSB _u(31) +#define RVCSR_MHPMEVENT14_LSB _u(0) +#define RVCSR_MHPMEVENT14_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT15 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT15_OFFSET _u(0x0000032f) +#define RVCSR_MHPMEVENT15_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT15_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT15_MSB _u(31) +#define RVCSR_MHPMEVENT15_LSB _u(0) +#define RVCSR_MHPMEVENT15_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT16 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT16_OFFSET _u(0x00000330) +#define RVCSR_MHPMEVENT16_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT16_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT16_MSB _u(31) +#define RVCSR_MHPMEVENT16_LSB _u(0) +#define RVCSR_MHPMEVENT16_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT17 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT17_OFFSET _u(0x00000331) +#define RVCSR_MHPMEVENT17_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT17_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT17_MSB _u(31) +#define RVCSR_MHPMEVENT17_LSB _u(0) +#define RVCSR_MHPMEVENT17_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT18 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT18_OFFSET _u(0x00000332) +#define RVCSR_MHPMEVENT18_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT18_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT18_MSB _u(31) +#define RVCSR_MHPMEVENT18_LSB _u(0) +#define RVCSR_MHPMEVENT18_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT19 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT19_OFFSET _u(0x00000333) +#define RVCSR_MHPMEVENT19_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT19_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT19_MSB _u(31) +#define RVCSR_MHPMEVENT19_LSB _u(0) +#define RVCSR_MHPMEVENT19_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT20 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT20_OFFSET _u(0x00000334) +#define RVCSR_MHPMEVENT20_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT20_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT20_MSB _u(31) +#define RVCSR_MHPMEVENT20_LSB _u(0) +#define RVCSR_MHPMEVENT20_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT21 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT21_OFFSET _u(0x00000335) +#define RVCSR_MHPMEVENT21_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT21_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT21_MSB _u(31) +#define RVCSR_MHPMEVENT21_LSB _u(0) +#define RVCSR_MHPMEVENT21_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT22 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT22_OFFSET _u(0x00000336) +#define RVCSR_MHPMEVENT22_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT22_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT22_MSB _u(31) +#define RVCSR_MHPMEVENT22_LSB _u(0) +#define RVCSR_MHPMEVENT22_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT23 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT23_OFFSET _u(0x00000337) +#define RVCSR_MHPMEVENT23_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT23_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT23_MSB _u(31) +#define RVCSR_MHPMEVENT23_LSB _u(0) +#define RVCSR_MHPMEVENT23_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT24 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT24_OFFSET _u(0x00000338) +#define RVCSR_MHPMEVENT24_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT24_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT24_MSB _u(31) +#define RVCSR_MHPMEVENT24_LSB _u(0) +#define RVCSR_MHPMEVENT24_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT25 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT25_OFFSET _u(0x00000339) +#define RVCSR_MHPMEVENT25_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT25_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT25_MSB _u(31) +#define RVCSR_MHPMEVENT25_LSB _u(0) +#define RVCSR_MHPMEVENT25_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT26 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT26_OFFSET _u(0x0000033a) +#define RVCSR_MHPMEVENT26_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT26_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT26_MSB _u(31) +#define RVCSR_MHPMEVENT26_LSB _u(0) +#define RVCSR_MHPMEVENT26_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT27 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT27_OFFSET _u(0x0000033b) +#define RVCSR_MHPMEVENT27_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT27_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT27_MSB _u(31) +#define RVCSR_MHPMEVENT27_LSB _u(0) +#define RVCSR_MHPMEVENT27_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT28 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT28_OFFSET _u(0x0000033c) +#define RVCSR_MHPMEVENT28_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT28_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT28_MSB _u(31) +#define RVCSR_MHPMEVENT28_LSB _u(0) +#define RVCSR_MHPMEVENT28_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT29 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT29_OFFSET _u(0x0000033d) +#define RVCSR_MHPMEVENT29_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT29_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT29_MSB _u(31) +#define RVCSR_MHPMEVENT29_LSB _u(0) +#define RVCSR_MHPMEVENT29_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT30 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT30_OFFSET _u(0x0000033e) +#define RVCSR_MHPMEVENT30_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT30_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT30_MSB _u(31) +#define RVCSR_MHPMEVENT30_LSB _u(0) +#define RVCSR_MHPMEVENT30_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMEVENT31 +// Description : Extended performance event selector, hardwired to 0. +#define RVCSR_MHPMEVENT31_OFFSET _u(0x0000033f) +#define RVCSR_MHPMEVENT31_BITS _u(0xffffffff) +#define RVCSR_MHPMEVENT31_RESET _u(0x00000000) +#define RVCSR_MHPMEVENT31_MSB _u(31) +#define RVCSR_MHPMEVENT31_LSB _u(0) +#define RVCSR_MHPMEVENT31_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MSCRATCH +// Description : Scratch register for machine trap handlers. +// +// 32-bit read/write register with no specific hardware function. +// Software may use this to do a fast save/restore of a core +// register in a trap handler. +#define RVCSR_MSCRATCH_OFFSET _u(0x00000340) +#define RVCSR_MSCRATCH_BITS _u(0xffffffff) +#define RVCSR_MSCRATCH_RESET _u(0x00000000) +#define RVCSR_MSCRATCH_MSB _u(31) +#define RVCSR_MSCRATCH_LSB _u(0) +#define RVCSR_MSCRATCH_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MEPC +// Description : Machine exception program counter. +// +// When entering a trap, the current value of the program counter +// is recorded here. When executing an `mret`, the processor jumps +// to `mepc`. Can also be read and written by software. +#define RVCSR_MEPC_OFFSET _u(0x00000341) +#define RVCSR_MEPC_BITS _u(0xfffffffc) +#define RVCSR_MEPC_RESET _u(0x00000000) +#define RVCSR_MEPC_MSB _u(31) +#define RVCSR_MEPC_LSB _u(2) +#define RVCSR_MEPC_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MCAUSE +// Description : Machine trap cause. Set when entering a trap to indicate the +// reason for the trap. Readable and writable by software. +#define RVCSR_MCAUSE_OFFSET _u(0x00000342) +#define RVCSR_MCAUSE_BITS _u(0x8000000f) +#define RVCSR_MCAUSE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MCAUSE_INTERRUPT +// Description : If 1, the trap was caused by an interrupt. If 0, it was caused +// by an exception. +#define RVCSR_MCAUSE_INTERRUPT_RESET _u(0x0) +#define RVCSR_MCAUSE_INTERRUPT_BITS _u(0x80000000) +#define RVCSR_MCAUSE_INTERRUPT_MSB _u(31) +#define RVCSR_MCAUSE_INTERRUPT_LSB _u(31) +#define RVCSR_MCAUSE_INTERRUPT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MCAUSE_CODE +// Description : If `interrupt` is set, `code` indicates the index of the bit in +// mip that caused the trap (3=soft IRQ, 7=timer IRQ, 11=external +// IRQ). Otherwise, `code` is set according to the cause of the +// exception. +// 0x0 -> Instruction fetch was misaligned. Will never fire on RP2350, since the C extension is enabled. +// 0x1 -> Instruction access fault. Instruction fetch failed a PMP check, or encountered a downstream bus fault, and then passed the point of no speculation. +// 0x2 -> Illegal instruction was executed (including illegal CSR accesses) +// 0x3 -> Breakpoint. An ebreak instruction was executed when the relevant dcsr.ebreak bit was clear. +// 0x4 -> Load address misaligned. Hazard3 requires natural alignment of all accesses. +// 0x5 -> Load access fault. A load failed a PMP check, or encountered a downstream bus error. +// 0x6 -> Store/AMO address misaligned. Hazard3 requires natural alignment of all accesses. +// 0x7 -> Store/AMO access fault. A store/AMO failed a PMP check, or encountered a downstream bus error. Also set if an AMO is attempted on a region that does not support atomics (on RP2350, anything but SRAM). +// 0x8 -> Environment call from U-mode. +// 0xb -> Environment call from M-mode. +#define RVCSR_MCAUSE_CODE_RESET _u(0x0) +#define RVCSR_MCAUSE_CODE_BITS _u(0x0000000f) +#define RVCSR_MCAUSE_CODE_MSB _u(3) +#define RVCSR_MCAUSE_CODE_LSB _u(0) +#define RVCSR_MCAUSE_CODE_ACCESS "RW" +#define RVCSR_MCAUSE_CODE_VALUE_INSTR_ALIGN _u(0x0) +#define RVCSR_MCAUSE_CODE_VALUE_INSTR_FAULT _u(0x1) +#define RVCSR_MCAUSE_CODE_VALUE_ILLEGAL_INSTR _u(0x2) +#define RVCSR_MCAUSE_CODE_VALUE_BREAKPOINT _u(0x3) +#define RVCSR_MCAUSE_CODE_VALUE_LOAD_ALIGN _u(0x4) +#define RVCSR_MCAUSE_CODE_VALUE_LOAD_FAULT _u(0x5) +#define RVCSR_MCAUSE_CODE_VALUE_STORE_ALIGN _u(0x6) +#define RVCSR_MCAUSE_CODE_VALUE_STORE_FAULT _u(0x7) +#define RVCSR_MCAUSE_CODE_VALUE_U_ECALL _u(0x8) +#define RVCSR_MCAUSE_CODE_VALUE_M_ECALL _u(0xb) +// ============================================================================= +// Register : RVCSR_MTVAL +// Description : Machine bad address or instruction. Hardwired to zero. +#define RVCSR_MTVAL_OFFSET _u(0x00000343) +#define RVCSR_MTVAL_BITS _u(0xffffffff) +#define RVCSR_MTVAL_RESET _u(0x00000000) +#define RVCSR_MTVAL_MSB _u(31) +#define RVCSR_MTVAL_LSB _u(0) +#define RVCSR_MTVAL_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MIP +// Description : Machine interrupt pending +#define RVCSR_MIP_OFFSET _u(0x00000344) +#define RVCSR_MIP_BITS _u(0x00000888) +#define RVCSR_MIP_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MIP_MEIP +// Description : External interrupt pending. The processor transfers to the +// external interrupt vector when `mie.meie`, `mip.meip` and +// `mstatus.mie` are all 1. +// +// Hazard3 has internal registers to individually filter which +// external IRQs appear in `meip`. When `meip` is 1, this +// indicates there is at least one external interrupt which is +// asserted (hence pending in `mieipa`), enabled in `meiea`, and +// of priority greater than or equal to the current preemption +// level in `meicontext.preempt`. +#define RVCSR_MIP_MEIP_RESET _u(0x0) +#define RVCSR_MIP_MEIP_BITS _u(0x00000800) +#define RVCSR_MIP_MEIP_MSB _u(11) +#define RVCSR_MIP_MEIP_LSB _u(11) +#define RVCSR_MIP_MEIP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MIP_MTIP +// Description : Timer interrupt pending. The processor transfers to the timer +// interrupt vector when `mie.mtie`, `mip.mtip` and `mstatus.mie` +// are all 1, unless a software or external interrupt request is +// also valid at this time. +#define RVCSR_MIP_MTIP_RESET _u(0x0) +#define RVCSR_MIP_MTIP_BITS _u(0x00000080) +#define RVCSR_MIP_MTIP_MSB _u(7) +#define RVCSR_MIP_MTIP_LSB _u(7) +#define RVCSR_MIP_MTIP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MIP_MSIP +// Description : Software interrupt pending. The processor transfers to the +// software interrupt vector `mie.msie`, `mip.msip` and +// `mstatus.mie` are all 1, unless an external interrupt request +// is also valid at this time. +#define RVCSR_MIP_MSIP_RESET _u(0x0) +#define RVCSR_MIP_MSIP_BITS _u(0x00000008) +#define RVCSR_MIP_MSIP_MSB _u(3) +#define RVCSR_MIP_MSIP_LSB _u(3) +#define RVCSR_MIP_MSIP_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPCFG0 +// Description : Physical memory protection configuration for regions 0 through +// 3 +#define RVCSR_PMPCFG0_OFFSET _u(0x000003a0) +#define RVCSR_PMPCFG0_BITS _u(0x9f9f9f9f) +#define RVCSR_PMPCFG0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R3_L +// Description : Lock region 3, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG0_R3_L_RESET _u(0x0) +#define RVCSR_PMPCFG0_R3_L_BITS _u(0x80000000) +#define RVCSR_PMPCFG0_R3_L_MSB _u(31) +#define RVCSR_PMPCFG0_R3_L_LSB _u(31) +#define RVCSR_PMPCFG0_R3_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R3_A +// Description : Address matching type for region 3. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG0_R3_A_RESET _u(0x0) +#define RVCSR_PMPCFG0_R3_A_BITS _u(0x18000000) +#define RVCSR_PMPCFG0_R3_A_MSB _u(28) +#define RVCSR_PMPCFG0_R3_A_LSB _u(27) +#define RVCSR_PMPCFG0_R3_A_ACCESS "RW" +#define RVCSR_PMPCFG0_R3_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG0_R3_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG0_R3_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R3_R +// Description : Read permission for region 3. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R3_R_RESET _u(0x0) +#define RVCSR_PMPCFG0_R3_R_BITS _u(0x04000000) +#define RVCSR_PMPCFG0_R3_R_MSB _u(26) +#define RVCSR_PMPCFG0_R3_R_LSB _u(26) +#define RVCSR_PMPCFG0_R3_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R3_W +// Description : Write permission for region 3 +#define RVCSR_PMPCFG0_R3_W_RESET _u(0x0) +#define RVCSR_PMPCFG0_R3_W_BITS _u(0x02000000) +#define RVCSR_PMPCFG0_R3_W_MSB _u(25) +#define RVCSR_PMPCFG0_R3_W_LSB _u(25) +#define RVCSR_PMPCFG0_R3_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R3_X +// Description : Execute permission for region 3. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R3_X_RESET _u(0x0) +#define RVCSR_PMPCFG0_R3_X_BITS _u(0x01000000) +#define RVCSR_PMPCFG0_R3_X_MSB _u(24) +#define RVCSR_PMPCFG0_R3_X_LSB _u(24) +#define RVCSR_PMPCFG0_R3_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R2_L +// Description : Lock region 2, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG0_R2_L_RESET _u(0x0) +#define RVCSR_PMPCFG0_R2_L_BITS _u(0x00800000) +#define RVCSR_PMPCFG0_R2_L_MSB _u(23) +#define RVCSR_PMPCFG0_R2_L_LSB _u(23) +#define RVCSR_PMPCFG0_R2_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R2_A +// Description : Address matching type for region 2. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG0_R2_A_RESET _u(0x0) +#define RVCSR_PMPCFG0_R2_A_BITS _u(0x00180000) +#define RVCSR_PMPCFG0_R2_A_MSB _u(20) +#define RVCSR_PMPCFG0_R2_A_LSB _u(19) +#define RVCSR_PMPCFG0_R2_A_ACCESS "RW" +#define RVCSR_PMPCFG0_R2_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG0_R2_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG0_R2_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R2_R +// Description : Read permission for region 2. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R2_R_RESET _u(0x0) +#define RVCSR_PMPCFG0_R2_R_BITS _u(0x00040000) +#define RVCSR_PMPCFG0_R2_R_MSB _u(18) +#define RVCSR_PMPCFG0_R2_R_LSB _u(18) +#define RVCSR_PMPCFG0_R2_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R2_W +// Description : Write permission for region 2 +#define RVCSR_PMPCFG0_R2_W_RESET _u(0x0) +#define RVCSR_PMPCFG0_R2_W_BITS _u(0x00020000) +#define RVCSR_PMPCFG0_R2_W_MSB _u(17) +#define RVCSR_PMPCFG0_R2_W_LSB _u(17) +#define RVCSR_PMPCFG0_R2_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R2_X +// Description : Execute permission for region 2. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R2_X_RESET _u(0x0) +#define RVCSR_PMPCFG0_R2_X_BITS _u(0x00010000) +#define RVCSR_PMPCFG0_R2_X_MSB _u(16) +#define RVCSR_PMPCFG0_R2_X_LSB _u(16) +#define RVCSR_PMPCFG0_R2_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R1_L +// Description : Lock region 1, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG0_R1_L_RESET _u(0x0) +#define RVCSR_PMPCFG0_R1_L_BITS _u(0x00008000) +#define RVCSR_PMPCFG0_R1_L_MSB _u(15) +#define RVCSR_PMPCFG0_R1_L_LSB _u(15) +#define RVCSR_PMPCFG0_R1_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R1_A +// Description : Address matching type for region 1. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG0_R1_A_RESET _u(0x0) +#define RVCSR_PMPCFG0_R1_A_BITS _u(0x00001800) +#define RVCSR_PMPCFG0_R1_A_MSB _u(12) +#define RVCSR_PMPCFG0_R1_A_LSB _u(11) +#define RVCSR_PMPCFG0_R1_A_ACCESS "RW" +#define RVCSR_PMPCFG0_R1_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG0_R1_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG0_R1_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R1_R +// Description : Read permission for region 1. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R1_R_RESET _u(0x0) +#define RVCSR_PMPCFG0_R1_R_BITS _u(0x00000400) +#define RVCSR_PMPCFG0_R1_R_MSB _u(10) +#define RVCSR_PMPCFG0_R1_R_LSB _u(10) +#define RVCSR_PMPCFG0_R1_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R1_W +// Description : Write permission for region 1 +#define RVCSR_PMPCFG0_R1_W_RESET _u(0x0) +#define RVCSR_PMPCFG0_R1_W_BITS _u(0x00000200) +#define RVCSR_PMPCFG0_R1_W_MSB _u(9) +#define RVCSR_PMPCFG0_R1_W_LSB _u(9) +#define RVCSR_PMPCFG0_R1_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R1_X +// Description : Execute permission for region 1. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R1_X_RESET _u(0x0) +#define RVCSR_PMPCFG0_R1_X_BITS _u(0x00000100) +#define RVCSR_PMPCFG0_R1_X_MSB _u(8) +#define RVCSR_PMPCFG0_R1_X_LSB _u(8) +#define RVCSR_PMPCFG0_R1_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R0_L +// Description : Lock region 0, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG0_R0_L_RESET _u(0x0) +#define RVCSR_PMPCFG0_R0_L_BITS _u(0x00000080) +#define RVCSR_PMPCFG0_R0_L_MSB _u(7) +#define RVCSR_PMPCFG0_R0_L_LSB _u(7) +#define RVCSR_PMPCFG0_R0_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R0_A +// Description : Address matching type for region 0. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG0_R0_A_RESET _u(0x0) +#define RVCSR_PMPCFG0_R0_A_BITS _u(0x00000018) +#define RVCSR_PMPCFG0_R0_A_MSB _u(4) +#define RVCSR_PMPCFG0_R0_A_LSB _u(3) +#define RVCSR_PMPCFG0_R0_A_ACCESS "RW" +#define RVCSR_PMPCFG0_R0_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG0_R0_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG0_R0_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R0_R +// Description : Read permission for region 0. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R0_R_RESET _u(0x0) +#define RVCSR_PMPCFG0_R0_R_BITS _u(0x00000004) +#define RVCSR_PMPCFG0_R0_R_MSB _u(2) +#define RVCSR_PMPCFG0_R0_R_LSB _u(2) +#define RVCSR_PMPCFG0_R0_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R0_W +// Description : Write permission for region 0 +#define RVCSR_PMPCFG0_R0_W_RESET _u(0x0) +#define RVCSR_PMPCFG0_R0_W_BITS _u(0x00000002) +#define RVCSR_PMPCFG0_R0_W_MSB _u(1) +#define RVCSR_PMPCFG0_R0_W_LSB _u(1) +#define RVCSR_PMPCFG0_R0_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG0_R0_X +// Description : Execute permission for region 0. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG0_R0_X_RESET _u(0x0) +#define RVCSR_PMPCFG0_R0_X_BITS _u(0x00000001) +#define RVCSR_PMPCFG0_R0_X_MSB _u(0) +#define RVCSR_PMPCFG0_R0_X_LSB _u(0) +#define RVCSR_PMPCFG0_R0_X_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPCFG1 +// Description : Physical memory protection configuration for regions 4 through +// 7 +#define RVCSR_PMPCFG1_OFFSET _u(0x000003a1) +#define RVCSR_PMPCFG1_BITS _u(0x9f9f9f9f) +#define RVCSR_PMPCFG1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R7_L +// Description : Lock region 7, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG1_R7_L_RESET _u(0x0) +#define RVCSR_PMPCFG1_R7_L_BITS _u(0x80000000) +#define RVCSR_PMPCFG1_R7_L_MSB _u(31) +#define RVCSR_PMPCFG1_R7_L_LSB _u(31) +#define RVCSR_PMPCFG1_R7_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R7_A +// Description : Address matching type for region 7. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG1_R7_A_RESET _u(0x0) +#define RVCSR_PMPCFG1_R7_A_BITS _u(0x18000000) +#define RVCSR_PMPCFG1_R7_A_MSB _u(28) +#define RVCSR_PMPCFG1_R7_A_LSB _u(27) +#define RVCSR_PMPCFG1_R7_A_ACCESS "RW" +#define RVCSR_PMPCFG1_R7_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG1_R7_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG1_R7_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R7_R +// Description : Read permission for region 7. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R7_R_RESET _u(0x0) +#define RVCSR_PMPCFG1_R7_R_BITS _u(0x04000000) +#define RVCSR_PMPCFG1_R7_R_MSB _u(26) +#define RVCSR_PMPCFG1_R7_R_LSB _u(26) +#define RVCSR_PMPCFG1_R7_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R7_W +// Description : Write permission for region 7 +#define RVCSR_PMPCFG1_R7_W_RESET _u(0x0) +#define RVCSR_PMPCFG1_R7_W_BITS _u(0x02000000) +#define RVCSR_PMPCFG1_R7_W_MSB _u(25) +#define RVCSR_PMPCFG1_R7_W_LSB _u(25) +#define RVCSR_PMPCFG1_R7_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R7_X +// Description : Execute permission for region 7. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R7_X_RESET _u(0x0) +#define RVCSR_PMPCFG1_R7_X_BITS _u(0x01000000) +#define RVCSR_PMPCFG1_R7_X_MSB _u(24) +#define RVCSR_PMPCFG1_R7_X_LSB _u(24) +#define RVCSR_PMPCFG1_R7_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R6_L +// Description : Lock region 6, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG1_R6_L_RESET _u(0x0) +#define RVCSR_PMPCFG1_R6_L_BITS _u(0x00800000) +#define RVCSR_PMPCFG1_R6_L_MSB _u(23) +#define RVCSR_PMPCFG1_R6_L_LSB _u(23) +#define RVCSR_PMPCFG1_R6_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R6_A +// Description : Address matching type for region 6. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG1_R6_A_RESET _u(0x0) +#define RVCSR_PMPCFG1_R6_A_BITS _u(0x00180000) +#define RVCSR_PMPCFG1_R6_A_MSB _u(20) +#define RVCSR_PMPCFG1_R6_A_LSB _u(19) +#define RVCSR_PMPCFG1_R6_A_ACCESS "RW" +#define RVCSR_PMPCFG1_R6_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG1_R6_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG1_R6_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R6_R +// Description : Read permission for region 6. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R6_R_RESET _u(0x0) +#define RVCSR_PMPCFG1_R6_R_BITS _u(0x00040000) +#define RVCSR_PMPCFG1_R6_R_MSB _u(18) +#define RVCSR_PMPCFG1_R6_R_LSB _u(18) +#define RVCSR_PMPCFG1_R6_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R6_W +// Description : Write permission for region 6 +#define RVCSR_PMPCFG1_R6_W_RESET _u(0x0) +#define RVCSR_PMPCFG1_R6_W_BITS _u(0x00020000) +#define RVCSR_PMPCFG1_R6_W_MSB _u(17) +#define RVCSR_PMPCFG1_R6_W_LSB _u(17) +#define RVCSR_PMPCFG1_R6_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R6_X +// Description : Execute permission for region 6. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R6_X_RESET _u(0x0) +#define RVCSR_PMPCFG1_R6_X_BITS _u(0x00010000) +#define RVCSR_PMPCFG1_R6_X_MSB _u(16) +#define RVCSR_PMPCFG1_R6_X_LSB _u(16) +#define RVCSR_PMPCFG1_R6_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R5_L +// Description : Lock region 5, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG1_R5_L_RESET _u(0x0) +#define RVCSR_PMPCFG1_R5_L_BITS _u(0x00008000) +#define RVCSR_PMPCFG1_R5_L_MSB _u(15) +#define RVCSR_PMPCFG1_R5_L_LSB _u(15) +#define RVCSR_PMPCFG1_R5_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R5_A +// Description : Address matching type for region 5. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG1_R5_A_RESET _u(0x0) +#define RVCSR_PMPCFG1_R5_A_BITS _u(0x00001800) +#define RVCSR_PMPCFG1_R5_A_MSB _u(12) +#define RVCSR_PMPCFG1_R5_A_LSB _u(11) +#define RVCSR_PMPCFG1_R5_A_ACCESS "RW" +#define RVCSR_PMPCFG1_R5_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG1_R5_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG1_R5_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R5_R +// Description : Read permission for region 5. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R5_R_RESET _u(0x0) +#define RVCSR_PMPCFG1_R5_R_BITS _u(0x00000400) +#define RVCSR_PMPCFG1_R5_R_MSB _u(10) +#define RVCSR_PMPCFG1_R5_R_LSB _u(10) +#define RVCSR_PMPCFG1_R5_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R5_W +// Description : Write permission for region 5 +#define RVCSR_PMPCFG1_R5_W_RESET _u(0x0) +#define RVCSR_PMPCFG1_R5_W_BITS _u(0x00000200) +#define RVCSR_PMPCFG1_R5_W_MSB _u(9) +#define RVCSR_PMPCFG1_R5_W_LSB _u(9) +#define RVCSR_PMPCFG1_R5_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R5_X +// Description : Execute permission for region 5. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R5_X_RESET _u(0x0) +#define RVCSR_PMPCFG1_R5_X_BITS _u(0x00000100) +#define RVCSR_PMPCFG1_R5_X_MSB _u(8) +#define RVCSR_PMPCFG1_R5_X_LSB _u(8) +#define RVCSR_PMPCFG1_R5_X_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R4_L +// Description : Lock region 4, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG1_R4_L_RESET _u(0x0) +#define RVCSR_PMPCFG1_R4_L_BITS _u(0x00000080) +#define RVCSR_PMPCFG1_R4_L_MSB _u(7) +#define RVCSR_PMPCFG1_R4_L_LSB _u(7) +#define RVCSR_PMPCFG1_R4_L_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R4_A +// Description : Address matching type for region 4. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG1_R4_A_RESET _u(0x0) +#define RVCSR_PMPCFG1_R4_A_BITS _u(0x00000018) +#define RVCSR_PMPCFG1_R4_A_MSB _u(4) +#define RVCSR_PMPCFG1_R4_A_LSB _u(3) +#define RVCSR_PMPCFG1_R4_A_ACCESS "RW" +#define RVCSR_PMPCFG1_R4_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG1_R4_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG1_R4_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R4_R +// Description : Read permission for region 4. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R4_R_RESET _u(0x0) +#define RVCSR_PMPCFG1_R4_R_BITS _u(0x00000004) +#define RVCSR_PMPCFG1_R4_R_MSB _u(2) +#define RVCSR_PMPCFG1_R4_R_LSB _u(2) +#define RVCSR_PMPCFG1_R4_R_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R4_W +// Description : Write permission for region 4 +#define RVCSR_PMPCFG1_R4_W_RESET _u(0x0) +#define RVCSR_PMPCFG1_R4_W_BITS _u(0x00000002) +#define RVCSR_PMPCFG1_R4_W_MSB _u(1) +#define RVCSR_PMPCFG1_R4_W_LSB _u(1) +#define RVCSR_PMPCFG1_R4_W_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG1_R4_X +// Description : Execute permission for region 4. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG1_R4_X_RESET _u(0x0) +#define RVCSR_PMPCFG1_R4_X_BITS _u(0x00000001) +#define RVCSR_PMPCFG1_R4_X_MSB _u(0) +#define RVCSR_PMPCFG1_R4_X_LSB _u(0) +#define RVCSR_PMPCFG1_R4_X_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPCFG2 +// Description : Physical memory protection configuration for regions 8 through +// 11 +#define RVCSR_PMPCFG2_OFFSET _u(0x000003a2) +#define RVCSR_PMPCFG2_BITS _u(0x9f9f9f9f) +#define RVCSR_PMPCFG2_RESET _u(0x001f1f1f) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R11_L +// Description : Lock region 11, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG2_R11_L_RESET _u(0x0) +#define RVCSR_PMPCFG2_R11_L_BITS _u(0x80000000) +#define RVCSR_PMPCFG2_R11_L_MSB _u(31) +#define RVCSR_PMPCFG2_R11_L_LSB _u(31) +#define RVCSR_PMPCFG2_R11_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R11_A +// Description : Address matching type for region 11. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG2_R11_A_RESET _u(0x0) +#define RVCSR_PMPCFG2_R11_A_BITS _u(0x18000000) +#define RVCSR_PMPCFG2_R11_A_MSB _u(28) +#define RVCSR_PMPCFG2_R11_A_LSB _u(27) +#define RVCSR_PMPCFG2_R11_A_ACCESS "RO" +#define RVCSR_PMPCFG2_R11_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG2_R11_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG2_R11_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R11_R +// Description : Read permission for region 11. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R11_R_RESET _u(0x0) +#define RVCSR_PMPCFG2_R11_R_BITS _u(0x04000000) +#define RVCSR_PMPCFG2_R11_R_MSB _u(26) +#define RVCSR_PMPCFG2_R11_R_LSB _u(26) +#define RVCSR_PMPCFG2_R11_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R11_W +// Description : Write permission for region 11 +#define RVCSR_PMPCFG2_R11_W_RESET _u(0x0) +#define RVCSR_PMPCFG2_R11_W_BITS _u(0x02000000) +#define RVCSR_PMPCFG2_R11_W_MSB _u(25) +#define RVCSR_PMPCFG2_R11_W_LSB _u(25) +#define RVCSR_PMPCFG2_R11_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R11_X +// Description : Execute permission for region 11. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R11_X_RESET _u(0x0) +#define RVCSR_PMPCFG2_R11_X_BITS _u(0x01000000) +#define RVCSR_PMPCFG2_R11_X_MSB _u(24) +#define RVCSR_PMPCFG2_R11_X_LSB _u(24) +#define RVCSR_PMPCFG2_R11_X_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R10_L +// Description : Lock region 10, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG2_R10_L_RESET _u(0x0) +#define RVCSR_PMPCFG2_R10_L_BITS _u(0x00800000) +#define RVCSR_PMPCFG2_R10_L_MSB _u(23) +#define RVCSR_PMPCFG2_R10_L_LSB _u(23) +#define RVCSR_PMPCFG2_R10_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R10_A +// Description : Address matching type for region 10. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG2_R10_A_RESET _u(0x3) +#define RVCSR_PMPCFG2_R10_A_BITS _u(0x00180000) +#define RVCSR_PMPCFG2_R10_A_MSB _u(20) +#define RVCSR_PMPCFG2_R10_A_LSB _u(19) +#define RVCSR_PMPCFG2_R10_A_ACCESS "RO" +#define RVCSR_PMPCFG2_R10_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG2_R10_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG2_R10_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R10_R +// Description : Read permission for region 10. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R10_R_RESET _u(0x1) +#define RVCSR_PMPCFG2_R10_R_BITS _u(0x00040000) +#define RVCSR_PMPCFG2_R10_R_MSB _u(18) +#define RVCSR_PMPCFG2_R10_R_LSB _u(18) +#define RVCSR_PMPCFG2_R10_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R10_W +// Description : Write permission for region 10 +#define RVCSR_PMPCFG2_R10_W_RESET _u(0x1) +#define RVCSR_PMPCFG2_R10_W_BITS _u(0x00020000) +#define RVCSR_PMPCFG2_R10_W_MSB _u(17) +#define RVCSR_PMPCFG2_R10_W_LSB _u(17) +#define RVCSR_PMPCFG2_R10_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R10_X +// Description : Execute permission for region 10. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R10_X_RESET _u(0x1) +#define RVCSR_PMPCFG2_R10_X_BITS _u(0x00010000) +#define RVCSR_PMPCFG2_R10_X_MSB _u(16) +#define RVCSR_PMPCFG2_R10_X_LSB _u(16) +#define RVCSR_PMPCFG2_R10_X_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R9_L +// Description : Lock region 9, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG2_R9_L_RESET _u(0x0) +#define RVCSR_PMPCFG2_R9_L_BITS _u(0x00008000) +#define RVCSR_PMPCFG2_R9_L_MSB _u(15) +#define RVCSR_PMPCFG2_R9_L_LSB _u(15) +#define RVCSR_PMPCFG2_R9_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R9_A +// Description : Address matching type for region 9. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG2_R9_A_RESET _u(0x3) +#define RVCSR_PMPCFG2_R9_A_BITS _u(0x00001800) +#define RVCSR_PMPCFG2_R9_A_MSB _u(12) +#define RVCSR_PMPCFG2_R9_A_LSB _u(11) +#define RVCSR_PMPCFG2_R9_A_ACCESS "RO" +#define RVCSR_PMPCFG2_R9_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG2_R9_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG2_R9_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R9_R +// Description : Read permission for region 9. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R9_R_RESET _u(0x1) +#define RVCSR_PMPCFG2_R9_R_BITS _u(0x00000400) +#define RVCSR_PMPCFG2_R9_R_MSB _u(10) +#define RVCSR_PMPCFG2_R9_R_LSB _u(10) +#define RVCSR_PMPCFG2_R9_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R9_W +// Description : Write permission for region 9 +#define RVCSR_PMPCFG2_R9_W_RESET _u(0x1) +#define RVCSR_PMPCFG2_R9_W_BITS _u(0x00000200) +#define RVCSR_PMPCFG2_R9_W_MSB _u(9) +#define RVCSR_PMPCFG2_R9_W_LSB _u(9) +#define RVCSR_PMPCFG2_R9_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R9_X +// Description : Execute permission for region 9. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R9_X_RESET _u(0x1) +#define RVCSR_PMPCFG2_R9_X_BITS _u(0x00000100) +#define RVCSR_PMPCFG2_R9_X_MSB _u(8) +#define RVCSR_PMPCFG2_R9_X_LSB _u(8) +#define RVCSR_PMPCFG2_R9_X_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R8_L +// Description : Lock region 8, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG2_R8_L_RESET _u(0x0) +#define RVCSR_PMPCFG2_R8_L_BITS _u(0x00000080) +#define RVCSR_PMPCFG2_R8_L_MSB _u(7) +#define RVCSR_PMPCFG2_R8_L_LSB _u(7) +#define RVCSR_PMPCFG2_R8_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R8_A +// Description : Address matching type for region 8. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG2_R8_A_RESET _u(0x3) +#define RVCSR_PMPCFG2_R8_A_BITS _u(0x00000018) +#define RVCSR_PMPCFG2_R8_A_MSB _u(4) +#define RVCSR_PMPCFG2_R8_A_LSB _u(3) +#define RVCSR_PMPCFG2_R8_A_ACCESS "RO" +#define RVCSR_PMPCFG2_R8_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG2_R8_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG2_R8_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R8_R +// Description : Read permission for region 8. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R8_R_RESET _u(0x1) +#define RVCSR_PMPCFG2_R8_R_BITS _u(0x00000004) +#define RVCSR_PMPCFG2_R8_R_MSB _u(2) +#define RVCSR_PMPCFG2_R8_R_LSB _u(2) +#define RVCSR_PMPCFG2_R8_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R8_W +// Description : Write permission for region 8 +#define RVCSR_PMPCFG2_R8_W_RESET _u(0x1) +#define RVCSR_PMPCFG2_R8_W_BITS _u(0x00000002) +#define RVCSR_PMPCFG2_R8_W_MSB _u(1) +#define RVCSR_PMPCFG2_R8_W_LSB _u(1) +#define RVCSR_PMPCFG2_R8_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG2_R8_X +// Description : Execute permission for region 8. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG2_R8_X_RESET _u(0x1) +#define RVCSR_PMPCFG2_R8_X_BITS _u(0x00000001) +#define RVCSR_PMPCFG2_R8_X_MSB _u(0) +#define RVCSR_PMPCFG2_R8_X_LSB _u(0) +#define RVCSR_PMPCFG2_R8_X_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPCFG3 +// Description : Physical memory protection configuration for regions 12 through +// 15 +#define RVCSR_PMPCFG3_OFFSET _u(0x000003a3) +#define RVCSR_PMPCFG3_BITS _u(0x9f9f9f9f) +#define RVCSR_PMPCFG3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R15_L +// Description : Lock region 15, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG3_R15_L_RESET _u(0x0) +#define RVCSR_PMPCFG3_R15_L_BITS _u(0x80000000) +#define RVCSR_PMPCFG3_R15_L_MSB _u(31) +#define RVCSR_PMPCFG3_R15_L_LSB _u(31) +#define RVCSR_PMPCFG3_R15_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R15_A +// Description : Address matching type for region 15. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG3_R15_A_RESET _u(0x0) +#define RVCSR_PMPCFG3_R15_A_BITS _u(0x18000000) +#define RVCSR_PMPCFG3_R15_A_MSB _u(28) +#define RVCSR_PMPCFG3_R15_A_LSB _u(27) +#define RVCSR_PMPCFG3_R15_A_ACCESS "RO" +#define RVCSR_PMPCFG3_R15_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG3_R15_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG3_R15_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R15_R +// Description : Read permission for region 15. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R15_R_RESET _u(0x0) +#define RVCSR_PMPCFG3_R15_R_BITS _u(0x04000000) +#define RVCSR_PMPCFG3_R15_R_MSB _u(26) +#define RVCSR_PMPCFG3_R15_R_LSB _u(26) +#define RVCSR_PMPCFG3_R15_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R15_W +// Description : Write permission for region 15 +#define RVCSR_PMPCFG3_R15_W_RESET _u(0x0) +#define RVCSR_PMPCFG3_R15_W_BITS _u(0x02000000) +#define RVCSR_PMPCFG3_R15_W_MSB _u(25) +#define RVCSR_PMPCFG3_R15_W_LSB _u(25) +#define RVCSR_PMPCFG3_R15_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R15_X +// Description : Execute permission for region 15. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R15_X_RESET _u(0x0) +#define RVCSR_PMPCFG3_R15_X_BITS _u(0x01000000) +#define RVCSR_PMPCFG3_R15_X_MSB _u(24) +#define RVCSR_PMPCFG3_R15_X_LSB _u(24) +#define RVCSR_PMPCFG3_R15_X_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R14_L +// Description : Lock region 14, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG3_R14_L_RESET _u(0x0) +#define RVCSR_PMPCFG3_R14_L_BITS _u(0x00800000) +#define RVCSR_PMPCFG3_R14_L_MSB _u(23) +#define RVCSR_PMPCFG3_R14_L_LSB _u(23) +#define RVCSR_PMPCFG3_R14_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R14_A +// Description : Address matching type for region 14. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG3_R14_A_RESET _u(0x0) +#define RVCSR_PMPCFG3_R14_A_BITS _u(0x00180000) +#define RVCSR_PMPCFG3_R14_A_MSB _u(20) +#define RVCSR_PMPCFG3_R14_A_LSB _u(19) +#define RVCSR_PMPCFG3_R14_A_ACCESS "RO" +#define RVCSR_PMPCFG3_R14_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG3_R14_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG3_R14_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R14_R +// Description : Read permission for region 14. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R14_R_RESET _u(0x0) +#define RVCSR_PMPCFG3_R14_R_BITS _u(0x00040000) +#define RVCSR_PMPCFG3_R14_R_MSB _u(18) +#define RVCSR_PMPCFG3_R14_R_LSB _u(18) +#define RVCSR_PMPCFG3_R14_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R14_W +// Description : Write permission for region 14 +#define RVCSR_PMPCFG3_R14_W_RESET _u(0x0) +#define RVCSR_PMPCFG3_R14_W_BITS _u(0x00020000) +#define RVCSR_PMPCFG3_R14_W_MSB _u(17) +#define RVCSR_PMPCFG3_R14_W_LSB _u(17) +#define RVCSR_PMPCFG3_R14_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R14_X +// Description : Execute permission for region 14. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R14_X_RESET _u(0x0) +#define RVCSR_PMPCFG3_R14_X_BITS _u(0x00010000) +#define RVCSR_PMPCFG3_R14_X_MSB _u(16) +#define RVCSR_PMPCFG3_R14_X_LSB _u(16) +#define RVCSR_PMPCFG3_R14_X_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R13_L +// Description : Lock region 13, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG3_R13_L_RESET _u(0x0) +#define RVCSR_PMPCFG3_R13_L_BITS _u(0x00008000) +#define RVCSR_PMPCFG3_R13_L_MSB _u(15) +#define RVCSR_PMPCFG3_R13_L_LSB _u(15) +#define RVCSR_PMPCFG3_R13_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R13_A +// Description : Address matching type for region 13. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG3_R13_A_RESET _u(0x0) +#define RVCSR_PMPCFG3_R13_A_BITS _u(0x00001800) +#define RVCSR_PMPCFG3_R13_A_MSB _u(12) +#define RVCSR_PMPCFG3_R13_A_LSB _u(11) +#define RVCSR_PMPCFG3_R13_A_ACCESS "RO" +#define RVCSR_PMPCFG3_R13_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG3_R13_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG3_R13_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R13_R +// Description : Read permission for region 13. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R13_R_RESET _u(0x0) +#define RVCSR_PMPCFG3_R13_R_BITS _u(0x00000400) +#define RVCSR_PMPCFG3_R13_R_MSB _u(10) +#define RVCSR_PMPCFG3_R13_R_LSB _u(10) +#define RVCSR_PMPCFG3_R13_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R13_W +// Description : Write permission for region 13 +#define RVCSR_PMPCFG3_R13_W_RESET _u(0x0) +#define RVCSR_PMPCFG3_R13_W_BITS _u(0x00000200) +#define RVCSR_PMPCFG3_R13_W_MSB _u(9) +#define RVCSR_PMPCFG3_R13_W_LSB _u(9) +#define RVCSR_PMPCFG3_R13_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R13_X +// Description : Execute permission for region 13. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R13_X_RESET _u(0x0) +#define RVCSR_PMPCFG3_R13_X_BITS _u(0x00000100) +#define RVCSR_PMPCFG3_R13_X_MSB _u(8) +#define RVCSR_PMPCFG3_R13_X_LSB _u(8) +#define RVCSR_PMPCFG3_R13_X_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R12_L +// Description : Lock region 12, and apply it to M-mode as well as U-mode. +#define RVCSR_PMPCFG3_R12_L_RESET _u(0x0) +#define RVCSR_PMPCFG3_R12_L_BITS _u(0x00000080) +#define RVCSR_PMPCFG3_R12_L_MSB _u(7) +#define RVCSR_PMPCFG3_R12_L_LSB _u(7) +#define RVCSR_PMPCFG3_R12_L_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R12_A +// Description : Address matching type for region 12. Writing an unsupported +// value (TOR) will set the region to OFF. +// 0x0 -> Disable region +// 0x2 -> Naturally aligned 4-byte +// 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) +#define RVCSR_PMPCFG3_R12_A_RESET _u(0x0) +#define RVCSR_PMPCFG3_R12_A_BITS _u(0x00000018) +#define RVCSR_PMPCFG3_R12_A_MSB _u(4) +#define RVCSR_PMPCFG3_R12_A_LSB _u(3) +#define RVCSR_PMPCFG3_R12_A_ACCESS "RO" +#define RVCSR_PMPCFG3_R12_A_VALUE_OFF _u(0x0) +#define RVCSR_PMPCFG3_R12_A_VALUE_NA4 _u(0x2) +#define RVCSR_PMPCFG3_R12_A_VALUE_NAPOT _u(0x3) +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R12_R +// Description : Read permission for region 12. Note R and X are transposed from +// the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R12_R_RESET _u(0x0) +#define RVCSR_PMPCFG3_R12_R_BITS _u(0x00000004) +#define RVCSR_PMPCFG3_R12_R_MSB _u(2) +#define RVCSR_PMPCFG3_R12_R_LSB _u(2) +#define RVCSR_PMPCFG3_R12_R_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R12_W +// Description : Write permission for region 12 +#define RVCSR_PMPCFG3_R12_W_RESET _u(0x0) +#define RVCSR_PMPCFG3_R12_W_BITS _u(0x00000002) +#define RVCSR_PMPCFG3_R12_W_MSB _u(1) +#define RVCSR_PMPCFG3_R12_W_LSB _u(1) +#define RVCSR_PMPCFG3_R12_W_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_PMPCFG3_R12_X +// Description : Execute permission for region 12. Note R and X are transposed +// from the standard bit order due to erratum RP2350-E6. +#define RVCSR_PMPCFG3_R12_X_RESET _u(0x0) +#define RVCSR_PMPCFG3_R12_X_BITS _u(0x00000001) +#define RVCSR_PMPCFG3_R12_X_MSB _u(0) +#define RVCSR_PMPCFG3_R12_X_LSB _u(0) +#define RVCSR_PMPCFG3_R12_X_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR0 +// Description : Physical memory protection address for region 0. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR0_OFFSET _u(0x000003b0) +#define RVCSR_PMPADDR0_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR0_RESET _u(0x00000000) +#define RVCSR_PMPADDR0_MSB _u(29) +#define RVCSR_PMPADDR0_LSB _u(0) +#define RVCSR_PMPADDR0_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR1 +// Description : Physical memory protection address for region 1. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR1_OFFSET _u(0x000003b1) +#define RVCSR_PMPADDR1_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR1_RESET _u(0x00000000) +#define RVCSR_PMPADDR1_MSB _u(29) +#define RVCSR_PMPADDR1_LSB _u(0) +#define RVCSR_PMPADDR1_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR2 +// Description : Physical memory protection address for region 2. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR2_OFFSET _u(0x000003b2) +#define RVCSR_PMPADDR2_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR2_RESET _u(0x00000000) +#define RVCSR_PMPADDR2_MSB _u(29) +#define RVCSR_PMPADDR2_LSB _u(0) +#define RVCSR_PMPADDR2_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR3 +// Description : Physical memory protection address for region 3. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR3_OFFSET _u(0x000003b3) +#define RVCSR_PMPADDR3_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR3_RESET _u(0x00000000) +#define RVCSR_PMPADDR3_MSB _u(29) +#define RVCSR_PMPADDR3_LSB _u(0) +#define RVCSR_PMPADDR3_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR4 +// Description : Physical memory protection address for region 4. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR4_OFFSET _u(0x000003b4) +#define RVCSR_PMPADDR4_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR4_RESET _u(0x00000000) +#define RVCSR_PMPADDR4_MSB _u(29) +#define RVCSR_PMPADDR4_LSB _u(0) +#define RVCSR_PMPADDR4_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR5 +// Description : Physical memory protection address for region 5. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR5_OFFSET _u(0x000003b5) +#define RVCSR_PMPADDR5_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR5_RESET _u(0x00000000) +#define RVCSR_PMPADDR5_MSB _u(29) +#define RVCSR_PMPADDR5_LSB _u(0) +#define RVCSR_PMPADDR5_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR6 +// Description : Physical memory protection address for region 6. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR6_OFFSET _u(0x000003b6) +#define RVCSR_PMPADDR6_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR6_RESET _u(0x00000000) +#define RVCSR_PMPADDR6_MSB _u(29) +#define RVCSR_PMPADDR6_LSB _u(0) +#define RVCSR_PMPADDR6_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR7 +// Description : Physical memory protection address for region 7. Note all PMP +// addresses are in units of four bytes. +#define RVCSR_PMPADDR7_OFFSET _u(0x000003b7) +#define RVCSR_PMPADDR7_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR7_RESET _u(0x00000000) +#define RVCSR_PMPADDR7_MSB _u(29) +#define RVCSR_PMPADDR7_LSB _u(0) +#define RVCSR_PMPADDR7_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_PMPADDR8 +// Description : Physical memory protection address for region 8. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to the address range `0x00000000` through +// `0x0fffffff`, which contains the boot ROM. This range is made +// accessible to User mode by default. User mode access to this +// range can be disabled using one of the dynamically configurable +// PMP regions, or using the permission registers in ACCESSCTRL. +#define RVCSR_PMPADDR8_OFFSET _u(0x000003b8) +#define RVCSR_PMPADDR8_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR8_RESET _u(0x01ffffff) +#define RVCSR_PMPADDR8_MSB _u(29) +#define RVCSR_PMPADDR8_LSB _u(0) +#define RVCSR_PMPADDR8_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR9 +// Description : Physical memory protection address for region 9. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to the address range `0x40000000` through +// `0x5fffffff`, which contains the system peripherals. This range +// is made accessible to User mode by default. User mode access to +// this range can be disabled using one of the dynamically +// configurable PMP regions, or using the permission registers in +// ACCESSCTRL. +#define RVCSR_PMPADDR9_OFFSET _u(0x000003b9) +#define RVCSR_PMPADDR9_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR9_RESET _u(0x13ffffff) +#define RVCSR_PMPADDR9_MSB _u(29) +#define RVCSR_PMPADDR9_LSB _u(0) +#define RVCSR_PMPADDR9_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR10 +// Description : Physical memory protection address for region 10. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to the address range `0xd0000000` through +// `0xdfffffff`, which contains the core-local peripherals (SIO). +// This range is made accessible to User mode by default. User +// mode access to this range can be disabled using one of the +// dynamically configurable PMP regions, or using the permission +// registers in ACCESSCTRL. +#define RVCSR_PMPADDR10_OFFSET _u(0x000003ba) +#define RVCSR_PMPADDR10_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR10_RESET _u(0x35ffffff) +#define RVCSR_PMPADDR10_MSB _u(29) +#define RVCSR_PMPADDR10_LSB _u(0) +#define RVCSR_PMPADDR10_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR11 +// Description : Physical memory protection address for region 11. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to all-zeroes. This region is not implemented. +#define RVCSR_PMPADDR11_OFFSET _u(0x000003bb) +#define RVCSR_PMPADDR11_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR11_RESET _u(0x00000000) +#define RVCSR_PMPADDR11_MSB _u(29) +#define RVCSR_PMPADDR11_LSB _u(0) +#define RVCSR_PMPADDR11_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR12 +// Description : Physical memory protection address for region 12. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to all-zeroes. This region is not implemented. +#define RVCSR_PMPADDR12_OFFSET _u(0x000003bc) +#define RVCSR_PMPADDR12_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR12_RESET _u(0x00000000) +#define RVCSR_PMPADDR12_MSB _u(29) +#define RVCSR_PMPADDR12_LSB _u(0) +#define RVCSR_PMPADDR12_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR13 +// Description : Physical memory protection address for region 13. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to all-zeroes. This region is not implemented. +#define RVCSR_PMPADDR13_OFFSET _u(0x000003bd) +#define RVCSR_PMPADDR13_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR13_RESET _u(0x00000000) +#define RVCSR_PMPADDR13_MSB _u(29) +#define RVCSR_PMPADDR13_LSB _u(0) +#define RVCSR_PMPADDR13_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR14 +// Description : Physical memory protection address for region 14. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to all-zeroes. This region is not implemented. +#define RVCSR_PMPADDR14_OFFSET _u(0x000003be) +#define RVCSR_PMPADDR14_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR14_RESET _u(0x00000000) +#define RVCSR_PMPADDR14_MSB _u(29) +#define RVCSR_PMPADDR14_LSB _u(0) +#define RVCSR_PMPADDR14_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPADDR15 +// Description : Physical memory protection address for region 15. Note all PMP +// addresses are in units of four bytes. +// +// Hardwired to all-zeroes. This region is not implemented. +#define RVCSR_PMPADDR15_OFFSET _u(0x000003bf) +#define RVCSR_PMPADDR15_BITS _u(0x3fffffff) +#define RVCSR_PMPADDR15_RESET _u(0x00000000) +#define RVCSR_PMPADDR15_MSB _u(29) +#define RVCSR_PMPADDR15_LSB _u(0) +#define RVCSR_PMPADDR15_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_TSELECT +// Description : Select trigger to be configured via `tdata1`/`tdata2` +// +// On RP2350, four instruction address triggers are implemented, +// so only the two LSBs of this register are writable. +#define RVCSR_TSELECT_OFFSET _u(0x000007a0) +#define RVCSR_TSELECT_BITS _u(0x00000003) +#define RVCSR_TSELECT_RESET _u(0x00000000) +#define RVCSR_TSELECT_MSB _u(1) +#define RVCSR_TSELECT_LSB _u(0) +#define RVCSR_TSELECT_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_TDATA1 +// Description : Trigger configuration data 1 +// +// Hazard 3 only supports address/data match triggers (type=2) so +// this register description includes the `mcontrol` fields for +// this type. +// +// More precisely, Hazard3 only supports exact instruction address +// match triggers (hardware breakpoints) so many of this +// register's fields are hardwired. +#define RVCSR_TDATA1_OFFSET _u(0x000007a1) +#define RVCSR_TDATA1_BITS _u(0xffffffcf) +#define RVCSR_TDATA1_RESET _u(0x20000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_TYPE +// Description : Trigger type. Hardwired to type=2, meaning an address/data +// match trigger +#define RVCSR_TDATA1_TYPE_RESET _u(0x2) +#define RVCSR_TDATA1_TYPE_BITS _u(0xf0000000) +#define RVCSR_TDATA1_TYPE_MSB _u(31) +#define RVCSR_TDATA1_TYPE_LSB _u(28) +#define RVCSR_TDATA1_TYPE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_DMODE +// Description : If 0, both Debug and M-mode can write the `tdata` registers at +// the selected `tselect`. +// +// If 1, only Debug Mode can write the `tdata` registers at the +// selected `tselect`. Writes from other modes are ignored. +// +// This bit is only writable from Debug Mode +#define RVCSR_TDATA1_DMODE_RESET _u(0x0) +#define RVCSR_TDATA1_DMODE_BITS _u(0x08000000) +#define RVCSR_TDATA1_DMODE_MSB _u(27) +#define RVCSR_TDATA1_DMODE_LSB _u(27) +#define RVCSR_TDATA1_DMODE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_MASKMAX +// Description : Value of 0 indicates only exact address matches are supported +#define RVCSR_TDATA1_MASKMAX_RESET _u(0x00) +#define RVCSR_TDATA1_MASKMAX_BITS _u(0x07e00000) +#define RVCSR_TDATA1_MASKMAX_MSB _u(26) +#define RVCSR_TDATA1_MASKMAX_LSB _u(21) +#define RVCSR_TDATA1_MASKMAX_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_HIT +// Description : Trigger hit flag. Not implemented, hardwired to 0. +#define RVCSR_TDATA1_HIT_RESET _u(0x0) +#define RVCSR_TDATA1_HIT_BITS _u(0x00100000) +#define RVCSR_TDATA1_HIT_MSB _u(20) +#define RVCSR_TDATA1_HIT_LSB _u(20) +#define RVCSR_TDATA1_HIT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_SELECT +// Description : Hardwired value of 0 indicates that only address matches are +// supported, not data matches +#define RVCSR_TDATA1_SELECT_RESET _u(0x0) +#define RVCSR_TDATA1_SELECT_BITS _u(0x00080000) +#define RVCSR_TDATA1_SELECT_MSB _u(19) +#define RVCSR_TDATA1_SELECT_LSB _u(19) +#define RVCSR_TDATA1_SELECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_TIMING +// Description : Hardwired value of 0 indicates that trigger fires before the +// triggering instruction executes, not afterward +#define RVCSR_TDATA1_TIMING_RESET _u(0x0) +#define RVCSR_TDATA1_TIMING_BITS _u(0x00040000) +#define RVCSR_TDATA1_TIMING_MSB _u(18) +#define RVCSR_TDATA1_TIMING_LSB _u(18) +#define RVCSR_TDATA1_TIMING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_SIZELO +// Description : Hardwired value of 0 indicates that access size matching is not +// supported +#define RVCSR_TDATA1_SIZELO_RESET _u(0x0) +#define RVCSR_TDATA1_SIZELO_BITS _u(0x00030000) +#define RVCSR_TDATA1_SIZELO_MSB _u(17) +#define RVCSR_TDATA1_SIZELO_LSB _u(16) +#define RVCSR_TDATA1_SIZELO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_ACTION +// Description : Select action to be taken when the trigger fires. +// 0x0 -> Raise a breakpoint exception, which can be handled by the M-mode exception handler +// 0x1 -> Enter debug mode. This action is only selectable when `tdata1.dmode` is 1. +#define RVCSR_TDATA1_ACTION_RESET _u(0x0) +#define RVCSR_TDATA1_ACTION_BITS _u(0x0000f000) +#define RVCSR_TDATA1_ACTION_MSB _u(15) +#define RVCSR_TDATA1_ACTION_LSB _u(12) +#define RVCSR_TDATA1_ACTION_ACCESS "RW" +#define RVCSR_TDATA1_ACTION_VALUE_EBREAK _u(0x0) +#define RVCSR_TDATA1_ACTION_VALUE_DEBUG _u(0x1) +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_CHAIN +// Description : Hardwired to 0 to indicate trigger chaining is not supported. +#define RVCSR_TDATA1_CHAIN_RESET _u(0x0) +#define RVCSR_TDATA1_CHAIN_BITS _u(0x00000800) +#define RVCSR_TDATA1_CHAIN_MSB _u(11) +#define RVCSR_TDATA1_CHAIN_LSB _u(11) +#define RVCSR_TDATA1_CHAIN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_MATCH +// Description : Hardwired to 0 to indicate match is always on the full address +// specified by `tdata2` +#define RVCSR_TDATA1_MATCH_RESET _u(0x0) +#define RVCSR_TDATA1_MATCH_BITS _u(0x00000780) +#define RVCSR_TDATA1_MATCH_MSB _u(10) +#define RVCSR_TDATA1_MATCH_LSB _u(7) +#define RVCSR_TDATA1_MATCH_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_M +// Description : When set, enable this trigger in M-mode +#define RVCSR_TDATA1_M_RESET _u(0x0) +#define RVCSR_TDATA1_M_BITS _u(0x00000040) +#define RVCSR_TDATA1_M_MSB _u(6) +#define RVCSR_TDATA1_M_LSB _u(6) +#define RVCSR_TDATA1_M_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_U +// Description : When set, enable this trigger in U-mode +#define RVCSR_TDATA1_U_RESET _u(0x0) +#define RVCSR_TDATA1_U_BITS _u(0x00000008) +#define RVCSR_TDATA1_U_MSB _u(3) +#define RVCSR_TDATA1_U_LSB _u(3) +#define RVCSR_TDATA1_U_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_EXECUTE +// Description : When set, the trigger fires on the address of an instruction +// that is executed. +#define RVCSR_TDATA1_EXECUTE_RESET _u(0x0) +#define RVCSR_TDATA1_EXECUTE_BITS _u(0x00000004) +#define RVCSR_TDATA1_EXECUTE_MSB _u(2) +#define RVCSR_TDATA1_EXECUTE_LSB _u(2) +#define RVCSR_TDATA1_EXECUTE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_STORE +// Description : Hardwired to 0 to indicate store address/data triggers are not +// supported +#define RVCSR_TDATA1_STORE_RESET _u(0x0) +#define RVCSR_TDATA1_STORE_BITS _u(0x00000002) +#define RVCSR_TDATA1_STORE_MSB _u(1) +#define RVCSR_TDATA1_STORE_LSB _u(1) +#define RVCSR_TDATA1_STORE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_TDATA1_LOAD +// Description : Hardwired to 0 to indicate load address/data triggers are not +// supported +#define RVCSR_TDATA1_LOAD_RESET _u(0x0) +#define RVCSR_TDATA1_LOAD_BITS _u(0x00000001) +#define RVCSR_TDATA1_LOAD_MSB _u(0) +#define RVCSR_TDATA1_LOAD_LSB _u(0) +#define RVCSR_TDATA1_LOAD_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_TDATA2 +// Description : Trigger configuration data 2 +// +// Contains the address for instruction address triggers (hardware +// breakpoints) +#define RVCSR_TDATA2_OFFSET _u(0x000007a2) +#define RVCSR_TDATA2_BITS _u(0xffffffff) +#define RVCSR_TDATA2_RESET _u(0x00000000) +#define RVCSR_TDATA2_MSB _u(31) +#define RVCSR_TDATA2_LSB _u(0) +#define RVCSR_TDATA2_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_DCSR +// Description : Debug control and status register. Access outside of Debug Mode +// will cause an illegal instruction exception. +#define RVCSR_DCSR_OFFSET _u(0x000007b0) +#define RVCSR_DCSR_BITS _u(0xf0009fc7) +#define RVCSR_DCSR_RESET _u(0x40000603) +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_XDEBUGVER +// Description : Hardwired to 4: external debug support as per RISC-V 0.13.2 +// debug specification. +#define RVCSR_DCSR_XDEBUGVER_RESET _u(0x4) +#define RVCSR_DCSR_XDEBUGVER_BITS _u(0xf0000000) +#define RVCSR_DCSR_XDEBUGVER_MSB _u(31) +#define RVCSR_DCSR_XDEBUGVER_LSB _u(28) +#define RVCSR_DCSR_XDEBUGVER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_EBREAKM +// Description : When 1, `ebreak` instructions executed in M-mode will break to +// Debug Mode instead of trapping +#define RVCSR_DCSR_EBREAKM_RESET _u(0x0) +#define RVCSR_DCSR_EBREAKM_BITS _u(0x00008000) +#define RVCSR_DCSR_EBREAKM_MSB _u(15) +#define RVCSR_DCSR_EBREAKM_LSB _u(15) +#define RVCSR_DCSR_EBREAKM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_EBREAKU +// Description : When 1, `ebreak` instructions executed in U-mode will break to +// Debug Mode instead of trapping. +#define RVCSR_DCSR_EBREAKU_RESET _u(0x0) +#define RVCSR_DCSR_EBREAKU_BITS _u(0x00001000) +#define RVCSR_DCSR_EBREAKU_MSB _u(12) +#define RVCSR_DCSR_EBREAKU_LSB _u(12) +#define RVCSR_DCSR_EBREAKU_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_STEPIE +// Description : Hardwired to 0: no interrupts are taken during hardware single- +// stepping. +#define RVCSR_DCSR_STEPIE_RESET _u(0x0) +#define RVCSR_DCSR_STEPIE_BITS _u(0x00000800) +#define RVCSR_DCSR_STEPIE_MSB _u(11) +#define RVCSR_DCSR_STEPIE_LSB _u(11) +#define RVCSR_DCSR_STEPIE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_STOPCOUNT +// Description : Hardwired to 1: `mcycle`/`mcycleh` and `minstret`/`minstreth` +// do not increment in Debug Mode. +#define RVCSR_DCSR_STOPCOUNT_RESET _u(0x1) +#define RVCSR_DCSR_STOPCOUNT_BITS _u(0x00000400) +#define RVCSR_DCSR_STOPCOUNT_MSB _u(10) +#define RVCSR_DCSR_STOPCOUNT_LSB _u(10) +#define RVCSR_DCSR_STOPCOUNT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_STOPTIME +// Description : Hardwired to 1: core-local timers don't increment in debug +// mode. External timers (e.g. hart-shared) may be configured to +// ignore this. +#define RVCSR_DCSR_STOPTIME_RESET _u(0x1) +#define RVCSR_DCSR_STOPTIME_BITS _u(0x00000200) +#define RVCSR_DCSR_STOPTIME_MSB _u(9) +#define RVCSR_DCSR_STOPTIME_LSB _u(9) +#define RVCSR_DCSR_STOPTIME_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_CAUSE +// Description : Set by hardware when entering debug mode. +// 0x1 -> An ebreak instruction was executed when the relevant `dcsr.ebreakx` bit was set. +// 0x2 -> The trigger module caused a breakpoint exception. +// 0x3 -> Processor entered Debug Mode due to a halt request, or a reset-halt request present when the core reset was released. +// 0x4 -> Processor entered Debug Mode after executing one instruction with single-stepping enabled. +#define RVCSR_DCSR_CAUSE_RESET _u(0x0) +#define RVCSR_DCSR_CAUSE_BITS _u(0x000001c0) +#define RVCSR_DCSR_CAUSE_MSB _u(8) +#define RVCSR_DCSR_CAUSE_LSB _u(6) +#define RVCSR_DCSR_CAUSE_ACCESS "RO" +#define RVCSR_DCSR_CAUSE_VALUE_EBREAK _u(0x1) +#define RVCSR_DCSR_CAUSE_VALUE_TRIGGER _u(0x2) +#define RVCSR_DCSR_CAUSE_VALUE_HALTREQ _u(0x3) +#define RVCSR_DCSR_CAUSE_VALUE_STEP _u(0x4) +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_STEP +// Description : When 1, re-enter Debug Mode after each instruction executed in +// M-mode or U-mode. +#define RVCSR_DCSR_STEP_RESET _u(0x0) +#define RVCSR_DCSR_STEP_BITS _u(0x00000004) +#define RVCSR_DCSR_STEP_MSB _u(2) +#define RVCSR_DCSR_STEP_LSB _u(2) +#define RVCSR_DCSR_STEP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_DCSR_PRV +// Description : Read the privilege mode the core was in when entering Debug +// Mode, and set the privilege mode the core will execute in when +// returning from Debug Mode. +#define RVCSR_DCSR_PRV_RESET _u(0x3) +#define RVCSR_DCSR_PRV_BITS _u(0x00000003) +#define RVCSR_DCSR_PRV_MSB _u(1) +#define RVCSR_DCSR_PRV_LSB _u(0) +#define RVCSR_DCSR_PRV_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_DPC +// Description : Debug program counter. When entering Debug Mode, `dpc` samples +// the current program counter, e.g. the address of an `ebreak` +// which caused Debug Mode entry. When leaving debug mode, the +// processor jumps to `dpc`. The host may read/write this register +// whilst in Debug Mode. +#define RVCSR_DPC_OFFSET _u(0x000007b1) +#define RVCSR_DPC_BITS _u(0xfffffffe) +#define RVCSR_DPC_RESET _u(0x00000000) +#define RVCSR_DPC_MSB _u(31) +#define RVCSR_DPC_LSB _u(1) +#define RVCSR_DPC_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MCYCLE +// Description : Machine-mode cycle counter, low half +// Counts up once per cycle, when `mcountinhibit.cy` is 0. +// Disabled by default to save power. +#define RVCSR_MCYCLE_OFFSET _u(0x00000b00) +#define RVCSR_MCYCLE_BITS _u(0xffffffff) +#define RVCSR_MCYCLE_RESET _u(0x00000000) +#define RVCSR_MCYCLE_MSB _u(31) +#define RVCSR_MCYCLE_LSB _u(0) +#define RVCSR_MCYCLE_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MINSTRET +// Description : Machine-mode instruction retire counter, low half +// Counts up once per instruction, when `mcountinhibit.ir` is 0. +// Disabled by default to save power. +#define RVCSR_MINSTRET_OFFSET _u(0x00000b02) +#define RVCSR_MINSTRET_BITS _u(0xffffffff) +#define RVCSR_MINSTRET_RESET _u(0x00000000) +#define RVCSR_MINSTRET_MSB _u(31) +#define RVCSR_MINSTRET_LSB _u(0) +#define RVCSR_MINSTRET_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER3 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER3_OFFSET _u(0x00000b03) +#define RVCSR_MHPMCOUNTER3_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER3_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER3_MSB _u(31) +#define RVCSR_MHPMCOUNTER3_LSB _u(0) +#define RVCSR_MHPMCOUNTER3_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER4 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER4_OFFSET _u(0x00000b04) +#define RVCSR_MHPMCOUNTER4_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER4_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER4_MSB _u(31) +#define RVCSR_MHPMCOUNTER4_LSB _u(0) +#define RVCSR_MHPMCOUNTER4_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER5 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER5_OFFSET _u(0x00000b05) +#define RVCSR_MHPMCOUNTER5_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER5_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER5_MSB _u(31) +#define RVCSR_MHPMCOUNTER5_LSB _u(0) +#define RVCSR_MHPMCOUNTER5_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER6 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER6_OFFSET _u(0x00000b06) +#define RVCSR_MHPMCOUNTER6_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER6_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER6_MSB _u(31) +#define RVCSR_MHPMCOUNTER6_LSB _u(0) +#define RVCSR_MHPMCOUNTER6_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER7 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER7_OFFSET _u(0x00000b07) +#define RVCSR_MHPMCOUNTER7_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER7_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER7_MSB _u(31) +#define RVCSR_MHPMCOUNTER7_LSB _u(0) +#define RVCSR_MHPMCOUNTER7_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER8 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER8_OFFSET _u(0x00000b08) +#define RVCSR_MHPMCOUNTER8_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER8_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER8_MSB _u(31) +#define RVCSR_MHPMCOUNTER8_LSB _u(0) +#define RVCSR_MHPMCOUNTER8_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER9 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER9_OFFSET _u(0x00000b09) +#define RVCSR_MHPMCOUNTER9_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER9_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER9_MSB _u(31) +#define RVCSR_MHPMCOUNTER9_LSB _u(0) +#define RVCSR_MHPMCOUNTER9_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER10 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER10_OFFSET _u(0x00000b0a) +#define RVCSR_MHPMCOUNTER10_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER10_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER10_MSB _u(31) +#define RVCSR_MHPMCOUNTER10_LSB _u(0) +#define RVCSR_MHPMCOUNTER10_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER11 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER11_OFFSET _u(0x00000b0b) +#define RVCSR_MHPMCOUNTER11_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER11_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER11_MSB _u(31) +#define RVCSR_MHPMCOUNTER11_LSB _u(0) +#define RVCSR_MHPMCOUNTER11_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER12 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER12_OFFSET _u(0x00000b0c) +#define RVCSR_MHPMCOUNTER12_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER12_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER12_MSB _u(31) +#define RVCSR_MHPMCOUNTER12_LSB _u(0) +#define RVCSR_MHPMCOUNTER12_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER13 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER13_OFFSET _u(0x00000b0d) +#define RVCSR_MHPMCOUNTER13_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER13_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER13_MSB _u(31) +#define RVCSR_MHPMCOUNTER13_LSB _u(0) +#define RVCSR_MHPMCOUNTER13_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER14 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER14_OFFSET _u(0x00000b0e) +#define RVCSR_MHPMCOUNTER14_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER14_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER14_MSB _u(31) +#define RVCSR_MHPMCOUNTER14_LSB _u(0) +#define RVCSR_MHPMCOUNTER14_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER15 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER15_OFFSET _u(0x00000b0f) +#define RVCSR_MHPMCOUNTER15_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER15_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER15_MSB _u(31) +#define RVCSR_MHPMCOUNTER15_LSB _u(0) +#define RVCSR_MHPMCOUNTER15_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER16 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER16_OFFSET _u(0x00000b10) +#define RVCSR_MHPMCOUNTER16_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER16_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER16_MSB _u(31) +#define RVCSR_MHPMCOUNTER16_LSB _u(0) +#define RVCSR_MHPMCOUNTER16_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER17 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER17_OFFSET _u(0x00000b11) +#define RVCSR_MHPMCOUNTER17_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER17_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER17_MSB _u(31) +#define RVCSR_MHPMCOUNTER17_LSB _u(0) +#define RVCSR_MHPMCOUNTER17_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER18 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER18_OFFSET _u(0x00000b12) +#define RVCSR_MHPMCOUNTER18_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER18_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER18_MSB _u(31) +#define RVCSR_MHPMCOUNTER18_LSB _u(0) +#define RVCSR_MHPMCOUNTER18_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER19 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER19_OFFSET _u(0x00000b13) +#define RVCSR_MHPMCOUNTER19_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER19_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER19_MSB _u(31) +#define RVCSR_MHPMCOUNTER19_LSB _u(0) +#define RVCSR_MHPMCOUNTER19_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER20 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER20_OFFSET _u(0x00000b14) +#define RVCSR_MHPMCOUNTER20_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER20_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER20_MSB _u(31) +#define RVCSR_MHPMCOUNTER20_LSB _u(0) +#define RVCSR_MHPMCOUNTER20_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER21 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER21_OFFSET _u(0x00000b15) +#define RVCSR_MHPMCOUNTER21_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER21_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER21_MSB _u(31) +#define RVCSR_MHPMCOUNTER21_LSB _u(0) +#define RVCSR_MHPMCOUNTER21_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER22 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER22_OFFSET _u(0x00000b16) +#define RVCSR_MHPMCOUNTER22_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER22_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER22_MSB _u(31) +#define RVCSR_MHPMCOUNTER22_LSB _u(0) +#define RVCSR_MHPMCOUNTER22_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER23 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER23_OFFSET _u(0x00000b17) +#define RVCSR_MHPMCOUNTER23_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER23_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER23_MSB _u(31) +#define RVCSR_MHPMCOUNTER23_LSB _u(0) +#define RVCSR_MHPMCOUNTER23_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER24 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER24_OFFSET _u(0x00000b18) +#define RVCSR_MHPMCOUNTER24_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER24_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER24_MSB _u(31) +#define RVCSR_MHPMCOUNTER24_LSB _u(0) +#define RVCSR_MHPMCOUNTER24_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER25 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER25_OFFSET _u(0x00000b19) +#define RVCSR_MHPMCOUNTER25_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER25_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER25_MSB _u(31) +#define RVCSR_MHPMCOUNTER25_LSB _u(0) +#define RVCSR_MHPMCOUNTER25_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER26 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER26_OFFSET _u(0x00000b1a) +#define RVCSR_MHPMCOUNTER26_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER26_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER26_MSB _u(31) +#define RVCSR_MHPMCOUNTER26_LSB _u(0) +#define RVCSR_MHPMCOUNTER26_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER27 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER27_OFFSET _u(0x00000b1b) +#define RVCSR_MHPMCOUNTER27_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER27_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER27_MSB _u(31) +#define RVCSR_MHPMCOUNTER27_LSB _u(0) +#define RVCSR_MHPMCOUNTER27_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER28 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER28_OFFSET _u(0x00000b1c) +#define RVCSR_MHPMCOUNTER28_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER28_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER28_MSB _u(31) +#define RVCSR_MHPMCOUNTER28_LSB _u(0) +#define RVCSR_MHPMCOUNTER28_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER29 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER29_OFFSET _u(0x00000b1d) +#define RVCSR_MHPMCOUNTER29_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER29_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER29_MSB _u(31) +#define RVCSR_MHPMCOUNTER29_LSB _u(0) +#define RVCSR_MHPMCOUNTER29_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER30 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER30_OFFSET _u(0x00000b1e) +#define RVCSR_MHPMCOUNTER30_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER30_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER30_MSB _u(31) +#define RVCSR_MHPMCOUNTER30_LSB _u(0) +#define RVCSR_MHPMCOUNTER30_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER31 +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER31_OFFSET _u(0x00000b1f) +#define RVCSR_MHPMCOUNTER31_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER31_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER31_MSB _u(31) +#define RVCSR_MHPMCOUNTER31_LSB _u(0) +#define RVCSR_MHPMCOUNTER31_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MCYCLEH +// Description : Machine-mode cycle counter, high half +// Counts up once per 1 << 32 cycles, when `mcountinhibit.cy` is +// 0. Disabled by default to save power. +#define RVCSR_MCYCLEH_OFFSET _u(0x00000b80) +#define RVCSR_MCYCLEH_BITS _u(0xffffffff) +#define RVCSR_MCYCLEH_RESET _u(0x00000000) +#define RVCSR_MCYCLEH_MSB _u(31) +#define RVCSR_MCYCLEH_LSB _u(0) +#define RVCSR_MCYCLEH_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MINSTRETH +// Description : Machine-mode instruction retire counter, low half +// Counts up once per 1 << 32 instructions, when +// `mcountinhibit.ir` is 0. Disabled by default to save power. +#define RVCSR_MINSTRETH_OFFSET _u(0x00000b82) +#define RVCSR_MINSTRETH_BITS _u(0xffffffff) +#define RVCSR_MINSTRETH_RESET _u(0x00000000) +#define RVCSR_MINSTRETH_MSB _u(31) +#define RVCSR_MINSTRETH_LSB _u(0) +#define RVCSR_MINSTRETH_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER3H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER3H_OFFSET _u(0x00000b83) +#define RVCSR_MHPMCOUNTER3H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER3H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER3H_MSB _u(31) +#define RVCSR_MHPMCOUNTER3H_LSB _u(0) +#define RVCSR_MHPMCOUNTER3H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER4H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER4H_OFFSET _u(0x00000b84) +#define RVCSR_MHPMCOUNTER4H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER4H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER4H_MSB _u(31) +#define RVCSR_MHPMCOUNTER4H_LSB _u(0) +#define RVCSR_MHPMCOUNTER4H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER5H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER5H_OFFSET _u(0x00000b85) +#define RVCSR_MHPMCOUNTER5H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER5H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER5H_MSB _u(31) +#define RVCSR_MHPMCOUNTER5H_LSB _u(0) +#define RVCSR_MHPMCOUNTER5H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER6H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER6H_OFFSET _u(0x00000b86) +#define RVCSR_MHPMCOUNTER6H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER6H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER6H_MSB _u(31) +#define RVCSR_MHPMCOUNTER6H_LSB _u(0) +#define RVCSR_MHPMCOUNTER6H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER7H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER7H_OFFSET _u(0x00000b87) +#define RVCSR_MHPMCOUNTER7H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER7H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER7H_MSB _u(31) +#define RVCSR_MHPMCOUNTER7H_LSB _u(0) +#define RVCSR_MHPMCOUNTER7H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER8H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER8H_OFFSET _u(0x00000b88) +#define RVCSR_MHPMCOUNTER8H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER8H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER8H_MSB _u(31) +#define RVCSR_MHPMCOUNTER8H_LSB _u(0) +#define RVCSR_MHPMCOUNTER8H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER9H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER9H_OFFSET _u(0x00000b89) +#define RVCSR_MHPMCOUNTER9H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER9H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER9H_MSB _u(31) +#define RVCSR_MHPMCOUNTER9H_LSB _u(0) +#define RVCSR_MHPMCOUNTER9H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER10H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER10H_OFFSET _u(0x00000b8a) +#define RVCSR_MHPMCOUNTER10H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER10H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER10H_MSB _u(31) +#define RVCSR_MHPMCOUNTER10H_LSB _u(0) +#define RVCSR_MHPMCOUNTER10H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER11H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER11H_OFFSET _u(0x00000b8b) +#define RVCSR_MHPMCOUNTER11H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER11H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER11H_MSB _u(31) +#define RVCSR_MHPMCOUNTER11H_LSB _u(0) +#define RVCSR_MHPMCOUNTER11H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER12H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER12H_OFFSET _u(0x00000b8c) +#define RVCSR_MHPMCOUNTER12H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER12H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER12H_MSB _u(31) +#define RVCSR_MHPMCOUNTER12H_LSB _u(0) +#define RVCSR_MHPMCOUNTER12H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER13H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER13H_OFFSET _u(0x00000b8d) +#define RVCSR_MHPMCOUNTER13H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER13H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER13H_MSB _u(31) +#define RVCSR_MHPMCOUNTER13H_LSB _u(0) +#define RVCSR_MHPMCOUNTER13H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER14H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER14H_OFFSET _u(0x00000b8e) +#define RVCSR_MHPMCOUNTER14H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER14H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER14H_MSB _u(31) +#define RVCSR_MHPMCOUNTER14H_LSB _u(0) +#define RVCSR_MHPMCOUNTER14H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER15H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER15H_OFFSET _u(0x00000b8f) +#define RVCSR_MHPMCOUNTER15H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER15H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER15H_MSB _u(31) +#define RVCSR_MHPMCOUNTER15H_LSB _u(0) +#define RVCSR_MHPMCOUNTER15H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER16H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER16H_OFFSET _u(0x00000b90) +#define RVCSR_MHPMCOUNTER16H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER16H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER16H_MSB _u(31) +#define RVCSR_MHPMCOUNTER16H_LSB _u(0) +#define RVCSR_MHPMCOUNTER16H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER17H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER17H_OFFSET _u(0x00000b91) +#define RVCSR_MHPMCOUNTER17H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER17H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER17H_MSB _u(31) +#define RVCSR_MHPMCOUNTER17H_LSB _u(0) +#define RVCSR_MHPMCOUNTER17H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER18H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER18H_OFFSET _u(0x00000b92) +#define RVCSR_MHPMCOUNTER18H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER18H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER18H_MSB _u(31) +#define RVCSR_MHPMCOUNTER18H_LSB _u(0) +#define RVCSR_MHPMCOUNTER18H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER19H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER19H_OFFSET _u(0x00000b93) +#define RVCSR_MHPMCOUNTER19H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER19H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER19H_MSB _u(31) +#define RVCSR_MHPMCOUNTER19H_LSB _u(0) +#define RVCSR_MHPMCOUNTER19H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER20H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER20H_OFFSET _u(0x00000b94) +#define RVCSR_MHPMCOUNTER20H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER20H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER20H_MSB _u(31) +#define RVCSR_MHPMCOUNTER20H_LSB _u(0) +#define RVCSR_MHPMCOUNTER20H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER21H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER21H_OFFSET _u(0x00000b95) +#define RVCSR_MHPMCOUNTER21H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER21H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER21H_MSB _u(31) +#define RVCSR_MHPMCOUNTER21H_LSB _u(0) +#define RVCSR_MHPMCOUNTER21H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER22H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER22H_OFFSET _u(0x00000b96) +#define RVCSR_MHPMCOUNTER22H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER22H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER22H_MSB _u(31) +#define RVCSR_MHPMCOUNTER22H_LSB _u(0) +#define RVCSR_MHPMCOUNTER22H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER23H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER23H_OFFSET _u(0x00000b97) +#define RVCSR_MHPMCOUNTER23H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER23H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER23H_MSB _u(31) +#define RVCSR_MHPMCOUNTER23H_LSB _u(0) +#define RVCSR_MHPMCOUNTER23H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER24H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER24H_OFFSET _u(0x00000b98) +#define RVCSR_MHPMCOUNTER24H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER24H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER24H_MSB _u(31) +#define RVCSR_MHPMCOUNTER24H_LSB _u(0) +#define RVCSR_MHPMCOUNTER24H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER25H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER25H_OFFSET _u(0x00000b99) +#define RVCSR_MHPMCOUNTER25H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER25H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER25H_MSB _u(31) +#define RVCSR_MHPMCOUNTER25H_LSB _u(0) +#define RVCSR_MHPMCOUNTER25H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER26H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER26H_OFFSET _u(0x00000b9a) +#define RVCSR_MHPMCOUNTER26H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER26H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER26H_MSB _u(31) +#define RVCSR_MHPMCOUNTER26H_LSB _u(0) +#define RVCSR_MHPMCOUNTER26H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER27H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER27H_OFFSET _u(0x00000b9b) +#define RVCSR_MHPMCOUNTER27H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER27H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER27H_MSB _u(31) +#define RVCSR_MHPMCOUNTER27H_LSB _u(0) +#define RVCSR_MHPMCOUNTER27H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER28H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER28H_OFFSET _u(0x00000b9c) +#define RVCSR_MHPMCOUNTER28H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER28H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER28H_MSB _u(31) +#define RVCSR_MHPMCOUNTER28H_LSB _u(0) +#define RVCSR_MHPMCOUNTER28H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER29H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER29H_OFFSET _u(0x00000b9d) +#define RVCSR_MHPMCOUNTER29H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER29H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER29H_MSB _u(31) +#define RVCSR_MHPMCOUNTER29H_LSB _u(0) +#define RVCSR_MHPMCOUNTER29H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER30H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER30H_OFFSET _u(0x00000b9e) +#define RVCSR_MHPMCOUNTER30H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER30H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER30H_MSB _u(31) +#define RVCSR_MHPMCOUNTER30H_LSB _u(0) +#define RVCSR_MHPMCOUNTER30H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHPMCOUNTER31H +// Description : Extended performance counter, hardwired to 0. +#define RVCSR_MHPMCOUNTER31H_OFFSET _u(0x00000b9f) +#define RVCSR_MHPMCOUNTER31H_BITS _u(0xffffffff) +#define RVCSR_MHPMCOUNTER31H_RESET _u(0x00000000) +#define RVCSR_MHPMCOUNTER31H_MSB _u(31) +#define RVCSR_MHPMCOUNTER31H_LSB _u(0) +#define RVCSR_MHPMCOUNTER31H_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_PMPCFGM0 +// Description : PMP M-mode configuration. One bit per PMP region. Setting a bit +// makes the corresponding region apply to M-mode (like the +// `pmpcfg.L` bit) but does not lock the region. +// +// PMP is useful for non-security-related purposes, such as stack +// guarding and peripheral emulation. This extension allows M-mode +// to freely use any currently unlocked regions for its own +// purposes, without the inconvenience of having to lock them. +// +// Note that this does not grant any new capabilities to M-mode, +// since in the base standard it is already possible to apply +// unlocked regions to M-mode by locking them. In general, PMP +// regions should be locked in ascending region number order so +// they can't be subsequently overridden by currently unlocked +// regions. +// +// Note also that this is not the same as the rule locking bypass +// bit in the ePMP extension, which does not permit locked and +// unlocked M-mode regions to coexist. +// +// This is a Hazard3 custom CSR. +#define RVCSR_PMPCFGM0_OFFSET _u(0x00000bd0) +#define RVCSR_PMPCFGM0_BITS _u(0x0000ffff) +#define RVCSR_PMPCFGM0_RESET _u(0x00000000) +#define RVCSR_PMPCFGM0_MSB _u(15) +#define RVCSR_PMPCFGM0_LSB _u(0) +#define RVCSR_PMPCFGM0_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MEIEA +// Description : External interrupt enable array. +// +// The array contains a read-write bit for each external interrupt +// request: a `1` bit indicates that interrupt is currently +// enabled. At reset, all external interrupts are disabled. +// +// If enabled, an external interrupt can cause assertion of the +// standard RISC-V machine external interrupt pending flag +// (`mip.meip`), and therefore cause the processor to enter the +// external interrupt vector. See `meipa`. +// +// There are up to 512 external interrupts. The upper half of this +// register contains a 16-bit window into the full 512-bit vector. +// The window is indexed by the 5 LSBs of the write data. +#define RVCSR_MEIEA_OFFSET _u(0x00000be0) +#define RVCSR_MEIEA_BITS _u(0xffff001f) +#define RVCSR_MEIEA_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIEA_WINDOW +// Description : 16-bit read/write window into the external interrupt enable +// array +#define RVCSR_MEIEA_WINDOW_RESET _u(0x0000) +#define RVCSR_MEIEA_WINDOW_BITS _u(0xffff0000) +#define RVCSR_MEIEA_WINDOW_MSB _u(31) +#define RVCSR_MEIEA_WINDOW_LSB _u(16) +#define RVCSR_MEIEA_WINDOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIEA_INDEX +// Description : Write-only self-clearing field (no value is stored) used to +// control which window of the array appears in `window`. +#define RVCSR_MEIEA_INDEX_RESET _u(0x00) +#define RVCSR_MEIEA_INDEX_BITS _u(0x0000001f) +#define RVCSR_MEIEA_INDEX_MSB _u(4) +#define RVCSR_MEIEA_INDEX_LSB _u(0) +#define RVCSR_MEIEA_INDEX_ACCESS "WO" +// ============================================================================= +// Register : RVCSR_MEIPA +// Description : External interrupt pending array +// +// Contains a read-only bit for each external interrupt request. +// Similarly to `meiea`, this register is a window into an array +// of up to 512 external interrupt flags. The status appears in +// the upper 16 bits of the value read from `meipa`, and the lower +// 5 bits of the value _written_ by the same CSR instruction (or 0 +// if no write takes place) select a 16-bit window of the full +// interrupt pending array. +// +// A `1` bit indicates that interrupt is currently asserted. IRQs +// are assumed to be level-sensitive, and the relevant `meipa` bit +// is cleared by servicing the requestor so that it deasserts its +// interrupt request. +// +// When any interrupt of sufficient priority is both set in +// `meipa` and enabled in `meiea`, the standard RISC-V external +// interrupt pending bit `mip.meip` is asserted. In other words, +// `meipa` is filtered by `meiea` to generate the standard +// `mip.meip` flag. +#define RVCSR_MEIPA_OFFSET _u(0x00000be1) +#define RVCSR_MEIPA_BITS _u(0xffff001f) +#define RVCSR_MEIPA_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIPA_WINDOW +// Description : 16-bit read-only window into the external interrupt pending +// array +#define RVCSR_MEIPA_WINDOW_RESET "-" +#define RVCSR_MEIPA_WINDOW_BITS _u(0xffff0000) +#define RVCSR_MEIPA_WINDOW_MSB _u(31) +#define RVCSR_MEIPA_WINDOW_LSB _u(16) +#define RVCSR_MEIPA_WINDOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIPA_INDEX +// Description : Write-only, self-clearing field (no value is stored) used to +// control which window of the array appears in `window`. +#define RVCSR_MEIPA_INDEX_RESET _u(0x00) +#define RVCSR_MEIPA_INDEX_BITS _u(0x0000001f) +#define RVCSR_MEIPA_INDEX_MSB _u(4) +#define RVCSR_MEIPA_INDEX_LSB _u(0) +#define RVCSR_MEIPA_INDEX_ACCESS "WO" +// ============================================================================= +// Register : RVCSR_MEIFA +// Description : External interrupt force array +// +// Contains a read-write bit for every interrupt request. Writing +// a 1 to a bit in the interrupt force array causes the +// corresponding bit to become pending in `meipa`. Software can +// use this feature to manually trigger a particular interrupt. +// +// There are no restrictions on using `meifa` inside of an +// interrupt. The more useful case here is to schedule some lower- +// priority handler from within a high-priority interrupt, so that +// it will execute before the core returns to the foreground code. +// Implementers may wish to reserve some external IRQs with their +// external inputs tied to 0 for this purpose. +// +// Bits can be cleared by software, and are cleared automatically +// by hardware upon a read of `meinext` which returns the +// corresponding IRQ number in `meinext.irq` with `mienext.noirq` +// clear (no matter whether `meinext.update` is written). +// +// `meifa` implements the same array window indexing scheme as +// `meiea` and `meipa`. +#define RVCSR_MEIFA_OFFSET _u(0x00000be2) +#define RVCSR_MEIFA_BITS _u(0xffff001f) +#define RVCSR_MEIFA_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIFA_WINDOW +// Description : 16-bit read/write window into the external interrupt force +// array +#define RVCSR_MEIFA_WINDOW_RESET _u(0x0000) +#define RVCSR_MEIFA_WINDOW_BITS _u(0xffff0000) +#define RVCSR_MEIFA_WINDOW_MSB _u(31) +#define RVCSR_MEIFA_WINDOW_LSB _u(16) +#define RVCSR_MEIFA_WINDOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIFA_INDEX +// Description : Write-only, self-clearing field (no value is stored) used to +// control which window of the array appears in `window`. +#define RVCSR_MEIFA_INDEX_RESET _u(0x00) +#define RVCSR_MEIFA_INDEX_BITS _u(0x0000001f) +#define RVCSR_MEIFA_INDEX_MSB _u(4) +#define RVCSR_MEIFA_INDEX_LSB _u(0) +#define RVCSR_MEIFA_INDEX_ACCESS "WO" +// ============================================================================= +// Register : RVCSR_MEIPRA +// Description : External interrupt priority array +// +// Each interrupt has an (up to) 4-bit priority value associated +// with it, and each access to this register reads and/or writes a +// 16-bit window containing four such priority values. When less +// than 16 priority levels are available, the LSBs of the priority +// fields are hardwired to 0. +// +// When an interrupt's priority is lower than the current +// preemption priority `meicontext.preempt`, it is treated as not +// being pending for the purposes of `mip.meip`. The pending bit +// in `meipa` will still assert, but the machine external +// interrupt pending bit `mip.meip` will not, so the processor +// will ignore this interrupt. See `meicontext`. +#define RVCSR_MEIPRA_OFFSET _u(0x00000be3) +#define RVCSR_MEIPRA_BITS _u(0xffff001f) +#define RVCSR_MEIPRA_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIPRA_WINDOW +// Description : 16-bit read/write window into the external interrupt priority +// array, containing four 4-bit priority values. +#define RVCSR_MEIPRA_WINDOW_RESET _u(0x0000) +#define RVCSR_MEIPRA_WINDOW_BITS _u(0xffff0000) +#define RVCSR_MEIPRA_WINDOW_MSB _u(31) +#define RVCSR_MEIPRA_WINDOW_LSB _u(16) +#define RVCSR_MEIPRA_WINDOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEIPRA_INDEX +// Description : Write-only, self-clearing field (no value is stored) used to +// control which window of the array appears in `window`. +#define RVCSR_MEIPRA_INDEX_RESET _u(0x00) +#define RVCSR_MEIPRA_INDEX_BITS _u(0x0000001f) +#define RVCSR_MEIPRA_INDEX_MSB _u(4) +#define RVCSR_MEIPRA_INDEX_LSB _u(0) +#define RVCSR_MEIPRA_INDEX_ACCESS "WO" +// ============================================================================= +// Register : RVCSR_MEINEXT +// Description : Get next external interrupt +// +// Contains the index of the highest-priority external interrupt +// which is both asserted in `meipa` and enabled in `meiea`, left- +// shifted by 2 so that it can be used to index an array of 32-bit +// function pointers. If there is no such interrupt, the MSB is +// set. +// +// When multiple interrupts of the same priority are both pending +// and enabled, the lowest-numbered wins. Interrupts with priority +// less than `meicontext.ppreempt` -- the _previous_ preemption +// priority -- are treated as though they are not pending. This is +// to ensure that a preempting interrupt frame does not service +// interrupts which may be in progress in the frame that was +// preempted. +#define RVCSR_MEINEXT_OFFSET _u(0x00000be4) +#define RVCSR_MEINEXT_BITS _u(0x800007fd) +#define RVCSR_MEINEXT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEINEXT_NOIRQ +// Description : Set when there is no external interrupt which is enabled, +// pending, and has priority greater than or equal to +// `meicontext.ppreempt`. Can be efficiently tested with a `bltz` +// or `bgez` instruction. +#define RVCSR_MEINEXT_NOIRQ_RESET _u(0x0) +#define RVCSR_MEINEXT_NOIRQ_BITS _u(0x80000000) +#define RVCSR_MEINEXT_NOIRQ_MSB _u(31) +#define RVCSR_MEINEXT_NOIRQ_LSB _u(31) +#define RVCSR_MEINEXT_NOIRQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEINEXT_IRQ +// Description : Index of the highest-priority active external interrupt. Zero +// when no external interrupts with sufficient priority are both +// pending and enabled. +#define RVCSR_MEINEXT_IRQ_RESET _u(0x000) +#define RVCSR_MEINEXT_IRQ_BITS _u(0x000007fc) +#define RVCSR_MEINEXT_IRQ_MSB _u(10) +#define RVCSR_MEINEXT_IRQ_LSB _u(2) +#define RVCSR_MEINEXT_IRQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEINEXT_UPDATE +// Description : Writing 1 (self-clearing) causes hardware to update +// `meicontext` according to the IRQ number and preemption +// priority of the interrupt indicated in `noirq`/`irq`. This +// should be done in a single atomic operation, i.e. `csrrsi a0, +// meinext, 0x1`. +#define RVCSR_MEINEXT_UPDATE_RESET _u(0x0) +#define RVCSR_MEINEXT_UPDATE_BITS _u(0x00000001) +#define RVCSR_MEINEXT_UPDATE_MSB _u(0) +#define RVCSR_MEINEXT_UPDATE_LSB _u(0) +#define RVCSR_MEINEXT_UPDATE_ACCESS "SC" +// ============================================================================= +// Register : RVCSR_MEICONTEXT +// Description : External interrupt context register +// +// Configures the priority level for interrupt preemption, and +// helps software track which interrupt it is currently in. The +// latter is useful when a common interrupt service routine +// handles interrupt requests from multiple instances of the same +// peripheral. +// +// A three-level stack of preemption priorities is maintained in +// the `preempt`, `ppreempt` and `pppreempt` fields. The priority +// stack is saved when hardware enters the external interrupt +// vector, and restored by an `mret` instruction if +// `meicontext.mreteirq` is set. +// +// The top entry of the priority stack, `preempt`, is used by +// hardware to ensure that only higher-priority interrupts can +// preempt the current interrupt. The next entry, `ppreempt`, is +// used to avoid servicing interrupts which may already be in +// progress in a frame that was preempted. The third entry, +// `pppreempt`, has no hardware effect, but ensures that `preempt` +// and `ppreempt` can be correctly saved/restored across arbitrary +// levels of preemption. +#define RVCSR_MEICONTEXT_OFFSET _u(0x00000be5) +#define RVCSR_MEICONTEXT_BITS _u(0xff1f9fff) +#define RVCSR_MEICONTEXT_RESET _u(0x00008000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_PPPREEMPT +// Description : Previous `ppreempt`. Set to `ppreempt` on priority save, set to +// zero on priority restore. Has no hardware effect, but ensures +// that when `meicontext` is saved/restored correctly, `preempt` +// and `ppreempt` stack correctly through arbitrarily many +// preemption frames. +#define RVCSR_MEICONTEXT_PPPREEMPT_RESET _u(0x0) +#define RVCSR_MEICONTEXT_PPPREEMPT_BITS _u(0xf0000000) +#define RVCSR_MEICONTEXT_PPPREEMPT_MSB _u(31) +#define RVCSR_MEICONTEXT_PPPREEMPT_LSB _u(28) +#define RVCSR_MEICONTEXT_PPPREEMPT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_PPREEMPT +// Description : Previous `preempt`. Set to `preempt` on priority save, restored +// to to `pppreempt` on priority restore. +// +// IRQs of lower priority than `ppreempt` are not visible in +// `meinext`, so that a preemptee is not re-taken in the +// preempting frame. +#define RVCSR_MEICONTEXT_PPREEMPT_RESET _u(0x0) +#define RVCSR_MEICONTEXT_PPREEMPT_BITS _u(0x0f000000) +#define RVCSR_MEICONTEXT_PPREEMPT_MSB _u(27) +#define RVCSR_MEICONTEXT_PPREEMPT_LSB _u(24) +#define RVCSR_MEICONTEXT_PPREEMPT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_PREEMPT +// Description : Minimum interrupt priority to preempt the current interrupt. +// Interrupts with lower priority than `preempt` do not cause the +// core to transfer to an interrupt handler. Updated by hardware +// when when `meinext.update` is written, or when hardware enters +// the external interrupt vector. +// +// If an interrupt is present in `meinext` when this field is +// updated, then `preempt` is set to one level greater than that +// interrupt's priority. Otherwise, `ppreempt` is set to one level +// greater than the maximum interrupt priority, disabling +// preemption. +#define RVCSR_MEICONTEXT_PREEMPT_RESET _u(0x00) +#define RVCSR_MEICONTEXT_PREEMPT_BITS _u(0x001f0000) +#define RVCSR_MEICONTEXT_PREEMPT_MSB _u(20) +#define RVCSR_MEICONTEXT_PREEMPT_LSB _u(16) +#define RVCSR_MEICONTEXT_PREEMPT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_NOIRQ +// Description : Not in interrupt (read/write). Set to 1 at reset. Set to +// `meinext.noirq` when `meinext.update` is written. No hardware +// effect. +#define RVCSR_MEICONTEXT_NOIRQ_RESET _u(0x1) +#define RVCSR_MEICONTEXT_NOIRQ_BITS _u(0x00008000) +#define RVCSR_MEICONTEXT_NOIRQ_MSB _u(15) +#define RVCSR_MEICONTEXT_NOIRQ_LSB _u(15) +#define RVCSR_MEICONTEXT_NOIRQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_IRQ +// Description : Current IRQ number (read/write). Set to `meinext.irq` when +// `meinext.update` is written. No hardware effect. +#define RVCSR_MEICONTEXT_IRQ_RESET _u(0x000) +#define RVCSR_MEICONTEXT_IRQ_BITS _u(0x00001ff0) +#define RVCSR_MEICONTEXT_IRQ_MSB _u(12) +#define RVCSR_MEICONTEXT_IRQ_LSB _u(4) +#define RVCSR_MEICONTEXT_IRQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_MTIESAVE +// Description : Reads as the current value of `mie.mtie`, if `clearts` is set +// by the same CSR access instruction. Otherwise reads as 0. +// Writes are ORed into `mie.mtie`. +#define RVCSR_MEICONTEXT_MTIESAVE_RESET _u(0x0) +#define RVCSR_MEICONTEXT_MTIESAVE_BITS _u(0x00000008) +#define RVCSR_MEICONTEXT_MTIESAVE_MSB _u(3) +#define RVCSR_MEICONTEXT_MTIESAVE_LSB _u(3) +#define RVCSR_MEICONTEXT_MTIESAVE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_MSIESAVE +// Description : Reads as the current value of `mie.msie`, if `clearts` is set +// by the same CSR access instruction. Otherwise reads as 0. +// Writes are ORed into `mie.msie`. +#define RVCSR_MEICONTEXT_MSIESAVE_RESET _u(0x0) +#define RVCSR_MEICONTEXT_MSIESAVE_BITS _u(0x00000004) +#define RVCSR_MEICONTEXT_MSIESAVE_MSB _u(2) +#define RVCSR_MEICONTEXT_MSIESAVE_LSB _u(2) +#define RVCSR_MEICONTEXT_MSIESAVE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_CLEARTS +// Description : Write-1 self-clearing field. Writing 1 will clear `mie.mtie` +// and `mie.msie`, and present their prior values in the +// `mtiesave` and `msiesave` of this register. This makes it safe +// to re-enable IRQs (via `mstatus.mie`) without the possibility +// of being preempted by the standard timer and soft interrupt +// handlers, which may not be aware of Hazard3's interrupt +// hardware. +// +// The clear due to `clearts` takes precedence over the set due to +// `mtiesave`/`msiesave`, although it would be unusual for +// software to write both on the same cycle. +#define RVCSR_MEICONTEXT_CLEARTS_RESET _u(0x0) +#define RVCSR_MEICONTEXT_CLEARTS_BITS _u(0x00000002) +#define RVCSR_MEICONTEXT_CLEARTS_MSB _u(1) +#define RVCSR_MEICONTEXT_CLEARTS_LSB _u(1) +#define RVCSR_MEICONTEXT_CLEARTS_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MEICONTEXT_MRETEIRQ +// Description : If 1, enable restore of the preemption priority stack on +// `mret`. This bit is set on entering the external interrupt +// vector, cleared by `mret`, and cleared upon taking any trap +// other than an external interrupt. +// +// Provided `meicontext` is saved on entry to the external +// interrupt vector (before enabling preemption), is restored +// before exiting, and the standard software/timer IRQs are +// prevented from preempting (e.g. by using `clearts`), this flag +// allows the hardware to safely manage the preemption priority +// stack even when an external interrupt handler may take +// exceptions. +#define RVCSR_MEICONTEXT_MRETEIRQ_RESET _u(0x0) +#define RVCSR_MEICONTEXT_MRETEIRQ_BITS _u(0x00000001) +#define RVCSR_MEICONTEXT_MRETEIRQ_MSB _u(0) +#define RVCSR_MEICONTEXT_MRETEIRQ_LSB _u(0) +#define RVCSR_MEICONTEXT_MRETEIRQ_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_MSLEEP +// Description : M-mode sleep control register +#define RVCSR_MSLEEP_OFFSET _u(0x00000bf0) +#define RVCSR_MSLEEP_BITS _u(0x00000007) +#define RVCSR_MSLEEP_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSLEEP_SLEEPONBLOCK +// Description : Enter the deep sleep state configured by +// msleep.deepsleep/msleep.powerdown on a `h3.block` instruction, +// as well as a standard `wfi`. If this bit is clear, a `h3.block` +// is always implemented as a simple pipeline stall. +#define RVCSR_MSLEEP_SLEEPONBLOCK_RESET _u(0x0) +#define RVCSR_MSLEEP_SLEEPONBLOCK_BITS _u(0x00000004) +#define RVCSR_MSLEEP_SLEEPONBLOCK_MSB _u(2) +#define RVCSR_MSLEEP_SLEEPONBLOCK_LSB _u(2) +#define RVCSR_MSLEEP_SLEEPONBLOCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSLEEP_POWERDOWN +// Description : Release the external power request when going to sleep. The +// function of this is platform-defined -- it may do nothing, it +// may do something simple like clock-gating the fabric, or it may +// be tied to some complex system-level power controller. +// +// When waking, the processor reasserts its external power-up +// request, and will not fetch any instructions until the request +// is acknowledged. This may add considerable latency to the +// wakeup. +#define RVCSR_MSLEEP_POWERDOWN_RESET _u(0x0) +#define RVCSR_MSLEEP_POWERDOWN_BITS _u(0x00000002) +#define RVCSR_MSLEEP_POWERDOWN_MSB _u(1) +#define RVCSR_MSLEEP_POWERDOWN_LSB _u(1) +#define RVCSR_MSLEEP_POWERDOWN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MSLEEP_DEEPSLEEP +// Description : Deassert the processor clock enable when entering the sleep +// state. If a clock gate is instantiated, this allows most of the +// processor (everything except the power state machine and the +// interrupt and halt input registers) to be clock gated whilst +// asleep, which may reduce the sleep current. This adds one cycle +// to the wakeup latency. +#define RVCSR_MSLEEP_DEEPSLEEP_RESET _u(0x0) +#define RVCSR_MSLEEP_DEEPSLEEP_BITS _u(0x00000001) +#define RVCSR_MSLEEP_DEEPSLEEP_MSB _u(0) +#define RVCSR_MSLEEP_DEEPSLEEP_LSB _u(0) +#define RVCSR_MSLEEP_DEEPSLEEP_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_DMDATA0 +// Description : The Debug Module's DATA0 register is mapped into Hazard3's CSR +// space so that the Debug Module can exchange data with the core +// by executing CSR access instructions (this is used to implement +// the Abstract Access Register command). Only accessible in Debug +// Mode. +#define RVCSR_DMDATA0_OFFSET _u(0x00000bff) +#define RVCSR_DMDATA0_BITS _u(0xffffffff) +#define RVCSR_DMDATA0_RESET _u(0x00000000) +#define RVCSR_DMDATA0_MSB _u(31) +#define RVCSR_DMDATA0_LSB _u(0) +#define RVCSR_DMDATA0_ACCESS "RW" +// ============================================================================= +// Register : RVCSR_CYCLE +// Description : Read-only U-mode alias of mcycle, accessible when +// `mcounteren.cy` is set +#define RVCSR_CYCLE_OFFSET _u(0x00000c00) +#define RVCSR_CYCLE_BITS _u(0xffffffff) +#define RVCSR_CYCLE_RESET _u(0x00000000) +#define RVCSR_CYCLE_MSB _u(31) +#define RVCSR_CYCLE_LSB _u(0) +#define RVCSR_CYCLE_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_INSTRET +// Description : Read-only U-mode alias of minstret, accessible when +// `mcounteren.ir` is set +#define RVCSR_INSTRET_OFFSET _u(0x00000c02) +#define RVCSR_INSTRET_BITS _u(0xffffffff) +#define RVCSR_INSTRET_RESET _u(0x00000000) +#define RVCSR_INSTRET_MSB _u(31) +#define RVCSR_INSTRET_LSB _u(0) +#define RVCSR_INSTRET_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_CYCLEH +// Description : Read-only U-mode alias of mcycleh, accessible when +// `mcounteren.cy` is set +#define RVCSR_CYCLEH_OFFSET _u(0x00000c80) +#define RVCSR_CYCLEH_BITS _u(0xffffffff) +#define RVCSR_CYCLEH_RESET _u(0x00000000) +#define RVCSR_CYCLEH_MSB _u(31) +#define RVCSR_CYCLEH_LSB _u(0) +#define RVCSR_CYCLEH_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_INSTRETH +// Description : Read-only U-mode alias of minstreth, accessible when +// `mcounteren.ir` is set +#define RVCSR_INSTRETH_OFFSET _u(0x00000c82) +#define RVCSR_INSTRETH_BITS _u(0xffffffff) +#define RVCSR_INSTRETH_RESET _u(0x00000000) +#define RVCSR_INSTRETH_MSB _u(31) +#define RVCSR_INSTRETH_LSB _u(0) +#define RVCSR_INSTRETH_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MVENDORID +// Description : Vendor ID +#define RVCSR_MVENDORID_OFFSET _u(0x00000f11) +#define RVCSR_MVENDORID_BITS _u(0xffffffff) +#define RVCSR_MVENDORID_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : RVCSR_MVENDORID_BANK +#define RVCSR_MVENDORID_BANK_RESET "-" +#define RVCSR_MVENDORID_BANK_BITS _u(0xffffff80) +#define RVCSR_MVENDORID_BANK_MSB _u(31) +#define RVCSR_MVENDORID_BANK_LSB _u(7) +#define RVCSR_MVENDORID_BANK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : RVCSR_MVENDORID_OFFSET +#define RVCSR_MVENDORID_OFFSET_RESET "-" +#define RVCSR_MVENDORID_OFFSET_BITS _u(0x0000007f) +#define RVCSR_MVENDORID_OFFSET_MSB _u(6) +#define RVCSR_MVENDORID_OFFSET_LSB _u(0) +#define RVCSR_MVENDORID_OFFSET_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MARCHID +// Description : Architecture ID (Hazard3) +#define RVCSR_MARCHID_OFFSET _u(0x00000f12) +#define RVCSR_MARCHID_BITS _u(0xffffffff) +#define RVCSR_MARCHID_RESET _u(0x0000001b) +#define RVCSR_MARCHID_MSB _u(31) +#define RVCSR_MARCHID_LSB _u(0) +#define RVCSR_MARCHID_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MIMPID +// Description : Implementation ID +#define RVCSR_MIMPID_OFFSET _u(0x00000f13) +#define RVCSR_MIMPID_BITS _u(0xffffffff) +#define RVCSR_MIMPID_RESET "-" +#define RVCSR_MIMPID_MSB _u(31) +#define RVCSR_MIMPID_LSB _u(0) +#define RVCSR_MIMPID_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MHARTID +// Description : Hardware thread ID +// On RP2350, core 0 has a hart ID of 0, and core 1 has a hart ID +// of 1. +#define RVCSR_MHARTID_OFFSET _u(0x00000f14) +#define RVCSR_MHARTID_BITS _u(0xffffffff) +#define RVCSR_MHARTID_RESET "-" +#define RVCSR_MHARTID_MSB _u(31) +#define RVCSR_MHARTID_LSB _u(0) +#define RVCSR_MHARTID_ACCESS "RO" +// ============================================================================= +// Register : RVCSR_MCONFIGPTR +// Description : Pointer to configuration data structure (hardwired to 0) +#define RVCSR_MCONFIGPTR_OFFSET _u(0x00000f15) +#define RVCSR_MCONFIGPTR_BITS _u(0xffffffff) +#define RVCSR_MCONFIGPTR_RESET _u(0x00000000) +#define RVCSR_MCONFIGPTR_MSB _u(31) +#define RVCSR_MCONFIGPTR_LSB _u(0) +#define RVCSR_MCONFIGPTR_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_RVCSR_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/sha256.h b/lib/pico-sdk/rp2350/hardware/regs/sha256.h new file mode 100644 index 000000000000..112963c08e07 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/sha256.h @@ -0,0 +1,228 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SHA256 +// Version : 1 +// Bus type : apb +// Description : SHA-256 hash function implementation +// ============================================================================= +#ifndef _HARDWARE_REGS_SHA256_H +#define _HARDWARE_REGS_SHA256_H +// ============================================================================= +// Register : SHA256_CSR +// Description : Control and status register +#define SHA256_CSR_OFFSET _u(0x00000000) +#define SHA256_CSR_BITS _u(0x00001317) +#define SHA256_CSR_RESET _u(0x00001206) +// ----------------------------------------------------------------------------- +// Field : SHA256_CSR_BSWAP +// Description : Enable byte swapping of 32-bit values at the point they are +// committed to the SHA message scheduler. +// +// This block's bus interface assembles byte/halfword data into +// message words in little-endian order, so that DMAing the same +// buffer with different transfer sizes always gives the same +// result on a little-endian system like RP2350. +// +// However, when marshalling bytes into blocks, SHA expects that +// the first byte is the *most significant* in each message word. +// To resolve this, once the bus interface has accumulated 32 bits +// of data (either a word write, two halfword writes in little- +// endian order, or four byte writes in little-endian order) the +// final value can be byte-swapped before passing to the actual +// SHA core. +// +// This feature is enabled by default because using the SHA core +// to checksum byte buffers is expected to be more common than +// having preformatted SHA message words lying around. +#define SHA256_CSR_BSWAP_RESET _u(0x1) +#define SHA256_CSR_BSWAP_BITS _u(0x00001000) +#define SHA256_CSR_BSWAP_MSB _u(12) +#define SHA256_CSR_BSWAP_LSB _u(12) +#define SHA256_CSR_BSWAP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SHA256_CSR_DMA_SIZE +// Description : Configure DREQ logic for the correct DMA data size. Must be +// configured before the DMA channel is triggered. +// +// The SHA-256 core's DREQ logic requests one entire block of data +// at once, since there is no FIFO, and data goes straight into +// the core's message schedule and digest hardware. Therefore, +// when transferring data with DMA, CSR_DMA_SIZE must be +// configured in advance so that the correct number of transfers +// can be requested per block. +// 0x0 -> 8bit +// 0x1 -> 16bit +// 0x2 -> 32bit +#define SHA256_CSR_DMA_SIZE_RESET _u(0x2) +#define SHA256_CSR_DMA_SIZE_BITS _u(0x00000300) +#define SHA256_CSR_DMA_SIZE_MSB _u(9) +#define SHA256_CSR_DMA_SIZE_LSB _u(8) +#define SHA256_CSR_DMA_SIZE_ACCESS "RW" +#define SHA256_CSR_DMA_SIZE_VALUE_8BIT _u(0x0) +#define SHA256_CSR_DMA_SIZE_VALUE_16BIT _u(0x1) +#define SHA256_CSR_DMA_SIZE_VALUE_32BIT _u(0x2) +// ----------------------------------------------------------------------------- +// Field : SHA256_CSR_ERR_WDATA_NOT_RDY +// Description : Set when a write occurs whilst the SHA-256 core is not ready +// for data (WDATA_RDY is low). Write one to clear. +#define SHA256_CSR_ERR_WDATA_NOT_RDY_RESET _u(0x0) +#define SHA256_CSR_ERR_WDATA_NOT_RDY_BITS _u(0x00000010) +#define SHA256_CSR_ERR_WDATA_NOT_RDY_MSB _u(4) +#define SHA256_CSR_ERR_WDATA_NOT_RDY_LSB _u(4) +#define SHA256_CSR_ERR_WDATA_NOT_RDY_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SHA256_CSR_SUM_VLD +// Description : If 1, the SHA-256 checksum presented in registers SUM0 through +// SUM7 is currently valid. +// +// Goes low when WDATA is first written, then returns high once 16 +// words have been written and the digest of the current 512-bit +// block has subsequently completed. +#define SHA256_CSR_SUM_VLD_RESET _u(0x1) +#define SHA256_CSR_SUM_VLD_BITS _u(0x00000004) +#define SHA256_CSR_SUM_VLD_MSB _u(2) +#define SHA256_CSR_SUM_VLD_LSB _u(2) +#define SHA256_CSR_SUM_VLD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SHA256_CSR_WDATA_RDY +// Description : If 1, the SHA-256 core is ready to accept more data through the +// WDATA register. +// +// After writing 16 words, this flag will go low for 57 cycles +// whilst the core completes its digest. +#define SHA256_CSR_WDATA_RDY_RESET _u(0x1) +#define SHA256_CSR_WDATA_RDY_BITS _u(0x00000002) +#define SHA256_CSR_WDATA_RDY_MSB _u(1) +#define SHA256_CSR_WDATA_RDY_LSB _u(1) +#define SHA256_CSR_WDATA_RDY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SHA256_CSR_START +// Description : Write 1 to prepare the SHA-256 core for a new checksum. +// +// The SUMx registers are initialised to the proper values +// (fractional bits of square roots of first 8 primes) and +// internal counters are cleared. This immediately forces +// WDATA_RDY and SUM_VLD high. +// +// START must be written before initiating a DMA transfer to the +// SHA-256 core, because the core will always request 16 transfers +// at a time (1 512-bit block). Additionally, the DMA channel +// should be configured for a multiple of 16 32-bit transfers. +#define SHA256_CSR_START_RESET _u(0x0) +#define SHA256_CSR_START_BITS _u(0x00000001) +#define SHA256_CSR_START_MSB _u(0) +#define SHA256_CSR_START_LSB _u(0) +#define SHA256_CSR_START_ACCESS "SC" +// ============================================================================= +// Register : SHA256_WDATA +// Description : Write data register +// After pulsing START and writing 16 words of data to this +// register, WDATA_RDY will go low and the SHA-256 core will +// complete the digest of the current 512-bit block. +// +// Software is responsible for ensuring the data is correctly +// padded and terminated to a whole number of 512-bit blocks. +// +// After this, WDATA_RDY will return high, and more data can be +// written (if any). +// +// This register supports word, halfword and byte writes, so that +// DMA from non-word-aligned buffers can be supported. The total +// amount of data per block remains the same (16 words, 32 +// halfwords or 64 bytes) and byte/halfword transfers must not be +// mixed within a block. +#define SHA256_WDATA_OFFSET _u(0x00000004) +#define SHA256_WDATA_BITS _u(0xffffffff) +#define SHA256_WDATA_RESET _u(0x00000000) +#define SHA256_WDATA_MSB _u(31) +#define SHA256_WDATA_LSB _u(0) +#define SHA256_WDATA_ACCESS "WF" +// ============================================================================= +// Register : SHA256_SUM0 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM0_OFFSET _u(0x00000008) +#define SHA256_SUM0_BITS _u(0xffffffff) +#define SHA256_SUM0_RESET _u(0x00000000) +#define SHA256_SUM0_MSB _u(31) +#define SHA256_SUM0_LSB _u(0) +#define SHA256_SUM0_ACCESS "RO" +// ============================================================================= +// Register : SHA256_SUM1 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM1_OFFSET _u(0x0000000c) +#define SHA256_SUM1_BITS _u(0xffffffff) +#define SHA256_SUM1_RESET _u(0x00000000) +#define SHA256_SUM1_MSB _u(31) +#define SHA256_SUM1_LSB _u(0) +#define SHA256_SUM1_ACCESS "RO" +// ============================================================================= +// Register : SHA256_SUM2 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM2_OFFSET _u(0x00000010) +#define SHA256_SUM2_BITS _u(0xffffffff) +#define SHA256_SUM2_RESET _u(0x00000000) +#define SHA256_SUM2_MSB _u(31) +#define SHA256_SUM2_LSB _u(0) +#define SHA256_SUM2_ACCESS "RO" +// ============================================================================= +// Register : SHA256_SUM3 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM3_OFFSET _u(0x00000014) +#define SHA256_SUM3_BITS _u(0xffffffff) +#define SHA256_SUM3_RESET _u(0x00000000) +#define SHA256_SUM3_MSB _u(31) +#define SHA256_SUM3_LSB _u(0) +#define SHA256_SUM3_ACCESS "RO" +// ============================================================================= +// Register : SHA256_SUM4 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM4_OFFSET _u(0x00000018) +#define SHA256_SUM4_BITS _u(0xffffffff) +#define SHA256_SUM4_RESET _u(0x00000000) +#define SHA256_SUM4_MSB _u(31) +#define SHA256_SUM4_LSB _u(0) +#define SHA256_SUM4_ACCESS "RO" +// ============================================================================= +// Register : SHA256_SUM5 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM5_OFFSET _u(0x0000001c) +#define SHA256_SUM5_BITS _u(0xffffffff) +#define SHA256_SUM5_RESET _u(0x00000000) +#define SHA256_SUM5_MSB _u(31) +#define SHA256_SUM5_LSB _u(0) +#define SHA256_SUM5_ACCESS "RO" +// ============================================================================= +// Register : SHA256_SUM6 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM6_OFFSET _u(0x00000020) +#define SHA256_SUM6_BITS _u(0xffffffff) +#define SHA256_SUM6_RESET _u(0x00000000) +#define SHA256_SUM6_MSB _u(31) +#define SHA256_SUM6_LSB _u(0) +#define SHA256_SUM6_ACCESS "RO" +// ============================================================================= +// Register : SHA256_SUM7 +// Description : 256-bit checksum result. Contents are undefined when +// CSR_SUM_VLD is 0. +#define SHA256_SUM7_OFFSET _u(0x00000024) +#define SHA256_SUM7_BITS _u(0xffffffff) +#define SHA256_SUM7_RESET _u(0x00000000) +#define SHA256_SUM7_MSB _u(31) +#define SHA256_SUM7_LSB _u(0) +#define SHA256_SUM7_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_SHA256_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/sio.h b/lib/pico-sdk/rp2350/hardware/regs/sio.h new file mode 100644 index 000000000000..c4cb29042c23 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/sio.h @@ -0,0 +1,2461 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SIO +// Version : 1 +// Bus type : apb +// Description : Single-cycle IO block +// Provides core-local and inter-core hardware for the two +// processors, with single-cycle access. +// ============================================================================= +#ifndef _HARDWARE_REGS_SIO_H +#define _HARDWARE_REGS_SIO_H +// ============================================================================= +// Register : SIO_CPUID +// Description : Processor core identifier +// Value is 0 when read from processor core 0, and 1 when read +// from processor core 1. +#define SIO_CPUID_OFFSET _u(0x00000000) +#define SIO_CPUID_BITS _u(0xffffffff) +#define SIO_CPUID_RESET "-" +#define SIO_CPUID_MSB _u(31) +#define SIO_CPUID_LSB _u(0) +#define SIO_CPUID_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_IN +// Description : Input value for GPIO0...31. +// +// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) +// appear as zero. +#define SIO_GPIO_IN_OFFSET _u(0x00000004) +#define SIO_GPIO_IN_BITS _u(0xffffffff) +#define SIO_GPIO_IN_RESET _u(0x00000000) +#define SIO_GPIO_IN_MSB _u(31) +#define SIO_GPIO_IN_LSB _u(0) +#define SIO_GPIO_IN_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_HI_IN +// Description : Input value on GPIO32...47, QSPI IOs and USB pins +// +// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) +// appear as zero. +#define SIO_GPIO_HI_IN_OFFSET _u(0x00000008) +#define SIO_GPIO_HI_IN_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_IN_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_IN_QSPI_SD +// Description : Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins +#define SIO_GPIO_HI_IN_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_IN_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_IN_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_IN_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_IN_QSPI_SD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_IN_QSPI_CSN +// Description : Input value on QSPI CSn pin +#define SIO_GPIO_HI_IN_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_IN_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_IN_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_IN_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_IN_QSPI_CSN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_IN_QSPI_SCK +// Description : Input value on QSPI SCK pin +#define SIO_GPIO_HI_IN_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_IN_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_IN_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_IN_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_IN_QSPI_SCK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_IN_USB_DM +// Description : Input value on USB D- pin +#define SIO_GPIO_HI_IN_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_IN_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_IN_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_IN_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_IN_USB_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_IN_USB_DP +// Description : Input value on USB D+ pin +#define SIO_GPIO_HI_IN_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_IN_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_IN_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_IN_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_IN_USB_DP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_IN_GPIO +// Description : Input value on GPIO32...47 +#define SIO_GPIO_HI_IN_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_IN_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_IN_GPIO_MSB _u(15) +#define SIO_GPIO_HI_IN_GPIO_LSB _u(0) +#define SIO_GPIO_HI_IN_GPIO_ACCESS "RO" +// ============================================================================= +// Register : SIO_GPIO_OUT +// Description : GPIO0...31 output value +// Set output level (1/0 -> high/low) for GPIO0...31. Reading back +// gives the last value written, NOT the input value from the +// pins. +// +// If core 0 and core 1 both write to GPIO_OUT simultaneously (or +// to a SET/CLR/XOR alias), the result is as though the write from +// core 0 took place first, and the write from core 1 was then +// applied to that intermediate result. +// +// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) +// ignore writes, and their output status reads back as zero. This +// is also true for SET/CLR/XOR aliases of this register. +#define SIO_GPIO_OUT_OFFSET _u(0x00000010) +#define SIO_GPIO_OUT_BITS _u(0xffffffff) +#define SIO_GPIO_OUT_RESET _u(0x00000000) +#define SIO_GPIO_OUT_MSB _u(31) +#define SIO_GPIO_OUT_LSB _u(0) +#define SIO_GPIO_OUT_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT +// Description : Output value for GPIO32...47, QSPI IOs and USB pins. +// +// Write to set output level (1/0 -> high/low). Reading back gives +// the last value written, NOT the input value from the pins. If +// core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or +// to a SET/CLR/XOR alias), the result is as though the write from +// core 0 took place first, and the write from core 1 was then +// applied to that intermediate result. +// +// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) +// ignore writes, and their output status reads back as zero. This +// is also true for SET/CLR/XOR aliases of this register. +#define SIO_GPIO_HI_OUT_OFFSET _u(0x00000014) +#define SIO_GPIO_HI_OUT_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OUT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_QSPI_SD +// Description : Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins +#define SIO_GPIO_HI_OUT_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OUT_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OUT_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OUT_QSPI_SD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_QSPI_CSN +// Description : Output value for QSPI CSn pin +#define SIO_GPIO_HI_OUT_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OUT_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OUT_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OUT_QSPI_CSN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_QSPI_SCK +// Description : Output value for QSPI SCK pin +#define SIO_GPIO_HI_OUT_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OUT_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OUT_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OUT_QSPI_SCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_USB_DM +// Description : Output value for USB D- pin +#define SIO_GPIO_HI_OUT_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OUT_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OUT_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OUT_USB_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_USB_DP +// Description : Output value for USB D+ pin +#define SIO_GPIO_HI_OUT_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OUT_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OUT_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OUT_USB_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_GPIO +// Description : Output value for GPIO32...47 +#define SIO_GPIO_HI_OUT_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OUT_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OUT_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OUT_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OUT_GPIO_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OUT_SET +// Description : GPIO0...31 output value set +// Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` +#define SIO_GPIO_OUT_SET_OFFSET _u(0x00000018) +#define SIO_GPIO_OUT_SET_BITS _u(0xffffffff) +#define SIO_GPIO_OUT_SET_RESET _u(0x00000000) +#define SIO_GPIO_OUT_SET_MSB _u(31) +#define SIO_GPIO_OUT_SET_LSB _u(0) +#define SIO_GPIO_OUT_SET_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_SET +// Description : Output value set for GPIO32..47, QSPI IOs and USB pins. +// Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= +// wdata` +#define SIO_GPIO_HI_OUT_SET_OFFSET _u(0x0000001c) +#define SIO_GPIO_HI_OUT_SET_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OUT_SET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_SET_QSPI_SD +#define SIO_GPIO_HI_OUT_SET_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_SET_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OUT_SET_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OUT_SET_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OUT_SET_QSPI_SD_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_SET_QSPI_CSN +#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OUT_SET_QSPI_CSN_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_SET_QSPI_SCK +#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OUT_SET_QSPI_SCK_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_SET_USB_DM +#define SIO_GPIO_HI_OUT_SET_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_SET_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OUT_SET_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OUT_SET_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OUT_SET_USB_DM_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_SET_USB_DP +#define SIO_GPIO_HI_OUT_SET_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_SET_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OUT_SET_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OUT_SET_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OUT_SET_USB_DP_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_SET_GPIO +#define SIO_GPIO_HI_OUT_SET_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OUT_SET_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OUT_SET_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OUT_SET_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OUT_SET_GPIO_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OUT_CLR +// Description : GPIO0...31 output value clear +// Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= +// ~wdata` +#define SIO_GPIO_OUT_CLR_OFFSET _u(0x00000020) +#define SIO_GPIO_OUT_CLR_BITS _u(0xffffffff) +#define SIO_GPIO_OUT_CLR_RESET _u(0x00000000) +#define SIO_GPIO_OUT_CLR_MSB _u(31) +#define SIO_GPIO_OUT_CLR_LSB _u(0) +#define SIO_GPIO_OUT_CLR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_CLR +// Description : Output value clear for GPIO32..47, QSPI IOs and USB pins. +// Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT +// &= ~wdata` +#define SIO_GPIO_HI_OUT_CLR_OFFSET _u(0x00000024) +#define SIO_GPIO_HI_OUT_CLR_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OUT_CLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_CLR_QSPI_SD +#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SD_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_CLR_QSPI_CSN +#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_CLR_QSPI_SCK +#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_CLR_USB_DM +#define SIO_GPIO_HI_OUT_CLR_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_CLR_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OUT_CLR_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OUT_CLR_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OUT_CLR_USB_DM_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_CLR_USB_DP +#define SIO_GPIO_HI_OUT_CLR_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_CLR_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OUT_CLR_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OUT_CLR_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OUT_CLR_USB_DP_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_CLR_GPIO +#define SIO_GPIO_HI_OUT_CLR_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OUT_CLR_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OUT_CLR_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OUT_CLR_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OUT_CLR_GPIO_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OUT_XOR +// Description : GPIO0...31 output value XOR +// Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= +// wdata` +#define SIO_GPIO_OUT_XOR_OFFSET _u(0x00000028) +#define SIO_GPIO_OUT_XOR_BITS _u(0xffffffff) +#define SIO_GPIO_OUT_XOR_RESET _u(0x00000000) +#define SIO_GPIO_OUT_XOR_MSB _u(31) +#define SIO_GPIO_OUT_XOR_LSB _u(0) +#define SIO_GPIO_OUT_XOR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OUT_XOR +// Description : Output value XOR for GPIO32..47, QSPI IOs and USB pins. +// Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT +// ^= wdata` +#define SIO_GPIO_HI_OUT_XOR_OFFSET _u(0x0000002c) +#define SIO_GPIO_HI_OUT_XOR_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OUT_XOR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_XOR_QSPI_SD +#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SD_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_XOR_QSPI_CSN +#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_XOR_QSPI_SCK +#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_XOR_USB_DM +#define SIO_GPIO_HI_OUT_XOR_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_XOR_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OUT_XOR_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OUT_XOR_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OUT_XOR_USB_DM_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_XOR_USB_DP +#define SIO_GPIO_HI_OUT_XOR_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OUT_XOR_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OUT_XOR_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OUT_XOR_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OUT_XOR_USB_DP_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OUT_XOR_GPIO +#define SIO_GPIO_HI_OUT_XOR_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OUT_XOR_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OUT_XOR_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OUT_XOR_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OUT_XOR_GPIO_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OE +// Description : GPIO0...31 output enable +// Set output enable (1/0 -> output/input) for GPIO0...31. Reading +// back gives the last value written. +// +// If core 0 and core 1 both write to GPIO_OE simultaneously (or +// to a SET/CLR/XOR alias), the result is as though the write from +// core 0 took place first, and the write from core 1 was then +// applied to that intermediate result. +// +// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) +// ignore writes, and their output status reads back as zero. This +// is also true for SET/CLR/XOR aliases of this register. +#define SIO_GPIO_OE_OFFSET _u(0x00000030) +#define SIO_GPIO_OE_BITS _u(0xffffffff) +#define SIO_GPIO_OE_RESET _u(0x00000000) +#define SIO_GPIO_OE_MSB _u(31) +#define SIO_GPIO_OE_LSB _u(0) +#define SIO_GPIO_OE_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_HI_OE +// Description : Output enable value for GPIO32...47, QSPI IOs and USB pins. +// +// Write output enable (1/0 -> output/input). Reading back gives +// the last value written. If core 0 and core 1 both write to +// GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the +// result is as though the write from core 0 took place first, and +// the write from core 1 was then applied to that intermediate +// result. +// +// In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) +// ignore writes, and their output status reads back as zero. This +// is also true for SET/CLR/XOR aliases of this register. +#define SIO_GPIO_HI_OE_OFFSET _u(0x00000034) +#define SIO_GPIO_HI_OE_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_QSPI_SD +// Description : Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and +// SD3 pins +#define SIO_GPIO_HI_OE_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OE_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OE_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OE_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OE_QSPI_SD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_QSPI_CSN +// Description : Output enable value for QSPI CSn pin +#define SIO_GPIO_HI_OE_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OE_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OE_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OE_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OE_QSPI_CSN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_QSPI_SCK +// Description : Output enable value for QSPI SCK pin +#define SIO_GPIO_HI_OE_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OE_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OE_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OE_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OE_QSPI_SCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_USB_DM +// Description : Output enable value for USB D- pin +#define SIO_GPIO_HI_OE_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OE_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OE_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OE_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OE_USB_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_USB_DP +// Description : Output enable value for USB D+ pin +#define SIO_GPIO_HI_OE_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OE_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OE_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OE_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OE_USB_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_GPIO +// Description : Output enable value for GPIO32...47 +#define SIO_GPIO_HI_OE_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OE_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OE_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OE_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OE_GPIO_ACCESS "RW" +// ============================================================================= +// Register : SIO_GPIO_OE_SET +// Description : GPIO0...31 output enable set +// Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` +#define SIO_GPIO_OE_SET_OFFSET _u(0x00000038) +#define SIO_GPIO_OE_SET_BITS _u(0xffffffff) +#define SIO_GPIO_OE_SET_RESET _u(0x00000000) +#define SIO_GPIO_OE_SET_MSB _u(31) +#define SIO_GPIO_OE_SET_LSB _u(0) +#define SIO_GPIO_OE_SET_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_SET +// Description : Output enable set for GPIO32...47, QSPI IOs and USB pins. +// Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= +// wdata` +#define SIO_GPIO_HI_OE_SET_OFFSET _u(0x0000003c) +#define SIO_GPIO_HI_OE_SET_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OE_SET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_SET_QSPI_SD +#define SIO_GPIO_HI_OE_SET_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OE_SET_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OE_SET_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OE_SET_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OE_SET_QSPI_SD_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_SET_QSPI_CSN +#define SIO_GPIO_HI_OE_SET_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OE_SET_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OE_SET_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OE_SET_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OE_SET_QSPI_CSN_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_SET_QSPI_SCK +#define SIO_GPIO_HI_OE_SET_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OE_SET_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OE_SET_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OE_SET_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OE_SET_QSPI_SCK_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_SET_USB_DM +#define SIO_GPIO_HI_OE_SET_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OE_SET_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OE_SET_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OE_SET_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OE_SET_USB_DM_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_SET_USB_DP +#define SIO_GPIO_HI_OE_SET_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OE_SET_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OE_SET_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OE_SET_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OE_SET_USB_DP_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_SET_GPIO +#define SIO_GPIO_HI_OE_SET_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OE_SET_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OE_SET_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OE_SET_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OE_SET_GPIO_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OE_CLR +// Description : GPIO0...31 output enable clear +// Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= +// ~wdata` +#define SIO_GPIO_OE_CLR_OFFSET _u(0x00000040) +#define SIO_GPIO_OE_CLR_BITS _u(0xffffffff) +#define SIO_GPIO_OE_CLR_RESET _u(0x00000000) +#define SIO_GPIO_OE_CLR_MSB _u(31) +#define SIO_GPIO_OE_CLR_LSB _u(0) +#define SIO_GPIO_OE_CLR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_CLR +// Description : Output enable clear for GPIO32...47, QSPI IOs and USB pins. +// Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= +// ~wdata` +#define SIO_GPIO_HI_OE_CLR_OFFSET _u(0x00000044) +#define SIO_GPIO_HI_OE_CLR_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OE_CLR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_CLR_QSPI_SD +#define SIO_GPIO_HI_OE_CLR_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OE_CLR_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OE_CLR_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OE_CLR_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OE_CLR_QSPI_SD_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_CLR_QSPI_CSN +#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OE_CLR_QSPI_CSN_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_CLR_QSPI_SCK +#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OE_CLR_QSPI_SCK_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_CLR_USB_DM +#define SIO_GPIO_HI_OE_CLR_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OE_CLR_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OE_CLR_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OE_CLR_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OE_CLR_USB_DM_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_CLR_USB_DP +#define SIO_GPIO_HI_OE_CLR_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OE_CLR_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OE_CLR_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OE_CLR_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OE_CLR_USB_DP_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_CLR_GPIO +#define SIO_GPIO_HI_OE_CLR_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OE_CLR_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OE_CLR_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OE_CLR_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OE_CLR_GPIO_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_OE_XOR +// Description : GPIO0...31 output enable XOR +// Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= +// wdata` +#define SIO_GPIO_OE_XOR_OFFSET _u(0x00000048) +#define SIO_GPIO_OE_XOR_BITS _u(0xffffffff) +#define SIO_GPIO_OE_XOR_RESET _u(0x00000000) +#define SIO_GPIO_OE_XOR_MSB _u(31) +#define SIO_GPIO_OE_XOR_LSB _u(0) +#define SIO_GPIO_OE_XOR_ACCESS "WO" +// ============================================================================= +// Register : SIO_GPIO_HI_OE_XOR +// Description : Output enable XOR for GPIO32...47, QSPI IOs and USB pins. +// Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE +// ^= wdata` +#define SIO_GPIO_HI_OE_XOR_OFFSET _u(0x0000004c) +#define SIO_GPIO_HI_OE_XOR_BITS _u(0xff00ffff) +#define SIO_GPIO_HI_OE_XOR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_XOR_QSPI_SD +#define SIO_GPIO_HI_OE_XOR_QSPI_SD_RESET _u(0x0) +#define SIO_GPIO_HI_OE_XOR_QSPI_SD_BITS _u(0xf0000000) +#define SIO_GPIO_HI_OE_XOR_QSPI_SD_MSB _u(31) +#define SIO_GPIO_HI_OE_XOR_QSPI_SD_LSB _u(28) +#define SIO_GPIO_HI_OE_XOR_QSPI_SD_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_XOR_QSPI_CSN +#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_RESET _u(0x0) +#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_BITS _u(0x08000000) +#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_MSB _u(27) +#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_LSB _u(27) +#define SIO_GPIO_HI_OE_XOR_QSPI_CSN_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_XOR_QSPI_SCK +#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_RESET _u(0x0) +#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_BITS _u(0x04000000) +#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_MSB _u(26) +#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_LSB _u(26) +#define SIO_GPIO_HI_OE_XOR_QSPI_SCK_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_XOR_USB_DM +#define SIO_GPIO_HI_OE_XOR_USB_DM_RESET _u(0x0) +#define SIO_GPIO_HI_OE_XOR_USB_DM_BITS _u(0x02000000) +#define SIO_GPIO_HI_OE_XOR_USB_DM_MSB _u(25) +#define SIO_GPIO_HI_OE_XOR_USB_DM_LSB _u(25) +#define SIO_GPIO_HI_OE_XOR_USB_DM_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_XOR_USB_DP +#define SIO_GPIO_HI_OE_XOR_USB_DP_RESET _u(0x0) +#define SIO_GPIO_HI_OE_XOR_USB_DP_BITS _u(0x01000000) +#define SIO_GPIO_HI_OE_XOR_USB_DP_MSB _u(24) +#define SIO_GPIO_HI_OE_XOR_USB_DP_LSB _u(24) +#define SIO_GPIO_HI_OE_XOR_USB_DP_ACCESS "WO" +// ----------------------------------------------------------------------------- +// Field : SIO_GPIO_HI_OE_XOR_GPIO +#define SIO_GPIO_HI_OE_XOR_GPIO_RESET _u(0x0000) +#define SIO_GPIO_HI_OE_XOR_GPIO_BITS _u(0x0000ffff) +#define SIO_GPIO_HI_OE_XOR_GPIO_MSB _u(15) +#define SIO_GPIO_HI_OE_XOR_GPIO_LSB _u(0) +#define SIO_GPIO_HI_OE_XOR_GPIO_ACCESS "WO" +// ============================================================================= +// Register : SIO_FIFO_ST +// Description : Status register for inter-core FIFOs (mailboxes). +// There is one FIFO in the core 0 -> core 1 direction, and one +// core 1 -> core 0. Both are 32 bits wide and 8 words deep. +// Core 0 can see the read side of the 1->0 FIFO (RX), and the +// write side of 0->1 FIFO (TX). +// Core 1 can see the read side of the 0->1 FIFO (RX), and the +// write side of 1->0 FIFO (TX). +// The SIO IRQ for each core is the logical OR of the VLD, WOF and +// ROE fields of its FIFO_ST register. +#define SIO_FIFO_ST_OFFSET _u(0x00000050) +#define SIO_FIFO_ST_BITS _u(0x0000000f) +#define SIO_FIFO_ST_RESET _u(0x00000002) +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_ROE +// Description : Sticky flag indicating the RX FIFO was read when empty. This +// read was ignored by the FIFO. +#define SIO_FIFO_ST_ROE_RESET _u(0x0) +#define SIO_FIFO_ST_ROE_BITS _u(0x00000008) +#define SIO_FIFO_ST_ROE_MSB _u(3) +#define SIO_FIFO_ST_ROE_LSB _u(3) +#define SIO_FIFO_ST_ROE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_WOF +// Description : Sticky flag indicating the TX FIFO was written when full. This +// write was ignored by the FIFO. +#define SIO_FIFO_ST_WOF_RESET _u(0x0) +#define SIO_FIFO_ST_WOF_BITS _u(0x00000004) +#define SIO_FIFO_ST_WOF_MSB _u(2) +#define SIO_FIFO_ST_WOF_LSB _u(2) +#define SIO_FIFO_ST_WOF_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_RDY +// Description : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR +// is ready for more data) +#define SIO_FIFO_ST_RDY_RESET _u(0x1) +#define SIO_FIFO_ST_RDY_BITS _u(0x00000002) +#define SIO_FIFO_ST_RDY_MSB _u(1) +#define SIO_FIFO_ST_RDY_LSB _u(1) +#define SIO_FIFO_ST_RDY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_FIFO_ST_VLD +// Description : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD +// is valid) +#define SIO_FIFO_ST_VLD_RESET _u(0x0) +#define SIO_FIFO_ST_VLD_BITS _u(0x00000001) +#define SIO_FIFO_ST_VLD_MSB _u(0) +#define SIO_FIFO_ST_VLD_LSB _u(0) +#define SIO_FIFO_ST_VLD_ACCESS "RO" +// ============================================================================= +// Register : SIO_FIFO_WR +// Description : Write access to this core's TX FIFO +#define SIO_FIFO_WR_OFFSET _u(0x00000054) +#define SIO_FIFO_WR_BITS _u(0xffffffff) +#define SIO_FIFO_WR_RESET _u(0x00000000) +#define SIO_FIFO_WR_MSB _u(31) +#define SIO_FIFO_WR_LSB _u(0) +#define SIO_FIFO_WR_ACCESS "WF" +// ============================================================================= +// Register : SIO_FIFO_RD +// Description : Read access to this core's RX FIFO +#define SIO_FIFO_RD_OFFSET _u(0x00000058) +#define SIO_FIFO_RD_BITS _u(0xffffffff) +#define SIO_FIFO_RD_RESET "-" +#define SIO_FIFO_RD_MSB _u(31) +#define SIO_FIFO_RD_LSB _u(0) +#define SIO_FIFO_RD_ACCESS "RF" +// ============================================================================= +// Register : SIO_SPINLOCK_ST +// Description : Spinlock state +// A bitmap containing the state of all 32 spinlocks (1=locked). +// Mainly intended for debugging. +#define SIO_SPINLOCK_ST_OFFSET _u(0x0000005c) +#define SIO_SPINLOCK_ST_BITS _u(0xffffffff) +#define SIO_SPINLOCK_ST_RESET _u(0x00000000) +#define SIO_SPINLOCK_ST_MSB _u(31) +#define SIO_SPINLOCK_ST_LSB _u(0) +#define SIO_SPINLOCK_ST_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM0 +// Description : Read/write access to accumulator 0 +#define SIO_INTERP0_ACCUM0_OFFSET _u(0x00000080) +#define SIO_INTERP0_ACCUM0_BITS _u(0xffffffff) +#define SIO_INTERP0_ACCUM0_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM0_MSB _u(31) +#define SIO_INTERP0_ACCUM0_LSB _u(0) +#define SIO_INTERP0_ACCUM0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM1 +// Description : Read/write access to accumulator 1 +#define SIO_INTERP0_ACCUM1_OFFSET _u(0x00000084) +#define SIO_INTERP0_ACCUM1_BITS _u(0xffffffff) +#define SIO_INTERP0_ACCUM1_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM1_MSB _u(31) +#define SIO_INTERP0_ACCUM1_LSB _u(0) +#define SIO_INTERP0_ACCUM1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE0 +// Description : Read/write access to BASE0 register. +#define SIO_INTERP0_BASE0_OFFSET _u(0x00000088) +#define SIO_INTERP0_BASE0_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE0_RESET _u(0x00000000) +#define SIO_INTERP0_BASE0_MSB _u(31) +#define SIO_INTERP0_BASE0_LSB _u(0) +#define SIO_INTERP0_BASE0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE1 +// Description : Read/write access to BASE1 register. +#define SIO_INTERP0_BASE1_OFFSET _u(0x0000008c) +#define SIO_INTERP0_BASE1_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE1_RESET _u(0x00000000) +#define SIO_INTERP0_BASE1_MSB _u(31) +#define SIO_INTERP0_BASE1_LSB _u(0) +#define SIO_INTERP0_BASE1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE2 +// Description : Read/write access to BASE2 register. +#define SIO_INTERP0_BASE2_OFFSET _u(0x00000090) +#define SIO_INTERP0_BASE2_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE2_RESET _u(0x00000000) +#define SIO_INTERP0_BASE2_MSB _u(31) +#define SIO_INTERP0_BASE2_LSB _u(0) +#define SIO_INTERP0_BASE2_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_POP_LANE0 +// Description : Read LANE0 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP0_POP_LANE0_OFFSET _u(0x00000094) +#define SIO_INTERP0_POP_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_LANE0_RESET _u(0x00000000) +#define SIO_INTERP0_POP_LANE0_MSB _u(31) +#define SIO_INTERP0_POP_LANE0_LSB _u(0) +#define SIO_INTERP0_POP_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_POP_LANE1 +// Description : Read LANE1 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP0_POP_LANE1_OFFSET _u(0x00000098) +#define SIO_INTERP0_POP_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_LANE1_RESET _u(0x00000000) +#define SIO_INTERP0_POP_LANE1_MSB _u(31) +#define SIO_INTERP0_POP_LANE1_LSB _u(0) +#define SIO_INTERP0_POP_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_POP_FULL +// Description : Read FULL result, and simultaneously write lane results to both +// accumulators (POP). +#define SIO_INTERP0_POP_FULL_OFFSET _u(0x0000009c) +#define SIO_INTERP0_POP_FULL_BITS _u(0xffffffff) +#define SIO_INTERP0_POP_FULL_RESET _u(0x00000000) +#define SIO_INTERP0_POP_FULL_MSB _u(31) +#define SIO_INTERP0_POP_FULL_LSB _u(0) +#define SIO_INTERP0_POP_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_LANE0 +// Description : Read LANE0 result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_LANE0_OFFSET _u(0x000000a0) +#define SIO_INTERP0_PEEK_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_LANE0_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_LANE0_MSB _u(31) +#define SIO_INTERP0_PEEK_LANE0_LSB _u(0) +#define SIO_INTERP0_PEEK_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_LANE1 +// Description : Read LANE1 result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_LANE1_OFFSET _u(0x000000a4) +#define SIO_INTERP0_PEEK_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_LANE1_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_LANE1_MSB _u(31) +#define SIO_INTERP0_PEEK_LANE1_LSB _u(0) +#define SIO_INTERP0_PEEK_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_PEEK_FULL +// Description : Read FULL result, without altering any internal state (PEEK). +#define SIO_INTERP0_PEEK_FULL_OFFSET _u(0x000000a8) +#define SIO_INTERP0_PEEK_FULL_BITS _u(0xffffffff) +#define SIO_INTERP0_PEEK_FULL_RESET _u(0x00000000) +#define SIO_INTERP0_PEEK_FULL_MSB _u(31) +#define SIO_INTERP0_PEEK_FULL_LSB _u(0) +#define SIO_INTERP0_PEEK_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP0_CTRL_LANE0 +// Description : Control register for lane 0 +#define SIO_INTERP0_CTRL_LANE0_OFFSET _u(0x000000ac) +#define SIO_INTERP0_CTRL_LANE0_BITS _u(0x03bfffff) +#define SIO_INTERP0_CTRL_LANE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF +// Description : Set if either OVERF0 or OVERF1 is set. +#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS _u(0x02000000) +#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB _u(25) +#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB _u(25) +#define SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF1 +// Description : Indicates if any masked-off MSBs in ACCUM1 are set. +#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS _u(0x01000000) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB _u(24) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB _u(24) +#define SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_OVERF0 +// Description : Indicates if any masked-off MSBs in ACCUM0 are set. +#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS _u(0x00800000) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB _u(23) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB _u(23) +#define SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_BLEND +// Description : Only present on INTERP0 on each core. If BLEND mode is enabled: +// - LANE1 result is a linear interpolation between BASE0 and +// BASE1, controlled +// by the 8 LSBs of lane 1 shift and mask value (a fractional +// number between +// 0 and 255/256ths) +// - LANE0 result does not have BASE0 added (yields only the 8 +// LSBs of lane 1 shift+mask value) +// - FULL result does not have lane 1 shift+mask value added +// (BASE2 + lane 0 shift+mask) +// LANE1 SIGNED flag controls whether the interpolation is signed +// or unsigned. +#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS _u(0x00200000) +#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB _u(21) +#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB _u(21) +#define SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB _u(20) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB _u(19) +#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE0 result. This does not +// affect FULL result. +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB _u(18) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB _u(18) +#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB _u(17) +#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB _u(16) +#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE0, and LANE0 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB _u(15) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB _u(15) +#define SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB _u(14) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB _u(10) +#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB _u(9) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB _u(5) +#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE0_SHIFT +// Description : Right-rotate applied to accumulator before masking. By +// appropriately configuring the masks, left and right shifts can +// be synthesised. +#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB _u(4) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB _u(0) +#define SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_CTRL_LANE1 +// Description : Control register for lane 1 +#define SIO_INTERP0_CTRL_LANE1_OFFSET _u(0x000000b0) +#define SIO_INTERP0_CTRL_LANE1_BITS _u(0x001fffff) +#define SIO_INTERP0_CTRL_LANE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB _u(20) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB _u(19) +#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE1 result. This does not +// affect FULL result. +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB _u(18) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB _u(18) +#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB _u(17) +#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB _u(16) +#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE1, and LANE1 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET _u(0x0) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB _u(15) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB _u(15) +#define SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB _u(14) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB _u(10) +#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB _u(9) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB _u(5) +#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP0_CTRL_LANE1_SHIFT +// Description : Right-rotate applied to accumulator before masking. By +// appropriately configuring the masks, left and right shifts can +// be synthesised. +#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET _u(0x00) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB _u(4) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB _u(0) +#define SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM0_ADD +// Description : Values written here are atomically added to ACCUM0 +// Reading yields lane 0's raw shift and mask value (BASE0 not +// added). +#define SIO_INTERP0_ACCUM0_ADD_OFFSET _u(0x000000b4) +#define SIO_INTERP0_ACCUM0_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP0_ACCUM0_ADD_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM0_ADD_MSB _u(23) +#define SIO_INTERP0_ACCUM0_ADD_LSB _u(0) +#define SIO_INTERP0_ACCUM0_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_ACCUM1_ADD +// Description : Values written here are atomically added to ACCUM1 +// Reading yields lane 1's raw shift and mask value (BASE1 not +// added). +#define SIO_INTERP0_ACCUM1_ADD_OFFSET _u(0x000000b8) +#define SIO_INTERP0_ACCUM1_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP0_ACCUM1_ADD_RESET _u(0x00000000) +#define SIO_INTERP0_ACCUM1_ADD_MSB _u(23) +#define SIO_INTERP0_ACCUM1_ADD_LSB _u(0) +#define SIO_INTERP0_ACCUM1_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP0_BASE_1AND0 +// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 +// simultaneously. +// Each half is sign-extended to 32 bits if that lane's SIGNED +// flag is set. +#define SIO_INTERP0_BASE_1AND0_OFFSET _u(0x000000bc) +#define SIO_INTERP0_BASE_1AND0_BITS _u(0xffffffff) +#define SIO_INTERP0_BASE_1AND0_RESET _u(0x00000000) +#define SIO_INTERP0_BASE_1AND0_MSB _u(31) +#define SIO_INTERP0_BASE_1AND0_LSB _u(0) +#define SIO_INTERP0_BASE_1AND0_ACCESS "WO" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM0 +// Description : Read/write access to accumulator 0 +#define SIO_INTERP1_ACCUM0_OFFSET _u(0x000000c0) +#define SIO_INTERP1_ACCUM0_BITS _u(0xffffffff) +#define SIO_INTERP1_ACCUM0_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM0_MSB _u(31) +#define SIO_INTERP1_ACCUM0_LSB _u(0) +#define SIO_INTERP1_ACCUM0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM1 +// Description : Read/write access to accumulator 1 +#define SIO_INTERP1_ACCUM1_OFFSET _u(0x000000c4) +#define SIO_INTERP1_ACCUM1_BITS _u(0xffffffff) +#define SIO_INTERP1_ACCUM1_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM1_MSB _u(31) +#define SIO_INTERP1_ACCUM1_LSB _u(0) +#define SIO_INTERP1_ACCUM1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE0 +// Description : Read/write access to BASE0 register. +#define SIO_INTERP1_BASE0_OFFSET _u(0x000000c8) +#define SIO_INTERP1_BASE0_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE0_RESET _u(0x00000000) +#define SIO_INTERP1_BASE0_MSB _u(31) +#define SIO_INTERP1_BASE0_LSB _u(0) +#define SIO_INTERP1_BASE0_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE1 +// Description : Read/write access to BASE1 register. +#define SIO_INTERP1_BASE1_OFFSET _u(0x000000cc) +#define SIO_INTERP1_BASE1_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE1_RESET _u(0x00000000) +#define SIO_INTERP1_BASE1_MSB _u(31) +#define SIO_INTERP1_BASE1_LSB _u(0) +#define SIO_INTERP1_BASE1_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE2 +// Description : Read/write access to BASE2 register. +#define SIO_INTERP1_BASE2_OFFSET _u(0x000000d0) +#define SIO_INTERP1_BASE2_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE2_RESET _u(0x00000000) +#define SIO_INTERP1_BASE2_MSB _u(31) +#define SIO_INTERP1_BASE2_LSB _u(0) +#define SIO_INTERP1_BASE2_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_POP_LANE0 +// Description : Read LANE0 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP1_POP_LANE0_OFFSET _u(0x000000d4) +#define SIO_INTERP1_POP_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_LANE0_RESET _u(0x00000000) +#define SIO_INTERP1_POP_LANE0_MSB _u(31) +#define SIO_INTERP1_POP_LANE0_LSB _u(0) +#define SIO_INTERP1_POP_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_POP_LANE1 +// Description : Read LANE1 result, and simultaneously write lane results to +// both accumulators (POP). +#define SIO_INTERP1_POP_LANE1_OFFSET _u(0x000000d8) +#define SIO_INTERP1_POP_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_LANE1_RESET _u(0x00000000) +#define SIO_INTERP1_POP_LANE1_MSB _u(31) +#define SIO_INTERP1_POP_LANE1_LSB _u(0) +#define SIO_INTERP1_POP_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_POP_FULL +// Description : Read FULL result, and simultaneously write lane results to both +// accumulators (POP). +#define SIO_INTERP1_POP_FULL_OFFSET _u(0x000000dc) +#define SIO_INTERP1_POP_FULL_BITS _u(0xffffffff) +#define SIO_INTERP1_POP_FULL_RESET _u(0x00000000) +#define SIO_INTERP1_POP_FULL_MSB _u(31) +#define SIO_INTERP1_POP_FULL_LSB _u(0) +#define SIO_INTERP1_POP_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_LANE0 +// Description : Read LANE0 result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_LANE0_OFFSET _u(0x000000e0) +#define SIO_INTERP1_PEEK_LANE0_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_LANE0_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_LANE0_MSB _u(31) +#define SIO_INTERP1_PEEK_LANE0_LSB _u(0) +#define SIO_INTERP1_PEEK_LANE0_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_LANE1 +// Description : Read LANE1 result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_LANE1_OFFSET _u(0x000000e4) +#define SIO_INTERP1_PEEK_LANE1_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_LANE1_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_LANE1_MSB _u(31) +#define SIO_INTERP1_PEEK_LANE1_LSB _u(0) +#define SIO_INTERP1_PEEK_LANE1_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_PEEK_FULL +// Description : Read FULL result, without altering any internal state (PEEK). +#define SIO_INTERP1_PEEK_FULL_OFFSET _u(0x000000e8) +#define SIO_INTERP1_PEEK_FULL_BITS _u(0xffffffff) +#define SIO_INTERP1_PEEK_FULL_RESET _u(0x00000000) +#define SIO_INTERP1_PEEK_FULL_MSB _u(31) +#define SIO_INTERP1_PEEK_FULL_LSB _u(0) +#define SIO_INTERP1_PEEK_FULL_ACCESS "RO" +// ============================================================================= +// Register : SIO_INTERP1_CTRL_LANE0 +// Description : Control register for lane 0 +#define SIO_INTERP1_CTRL_LANE0_OFFSET _u(0x000000ec) +#define SIO_INTERP1_CTRL_LANE0_BITS _u(0x03dfffff) +#define SIO_INTERP1_CTRL_LANE0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF +// Description : Set if either OVERF0 or OVERF1 is set. +#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS _u(0x02000000) +#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB _u(25) +#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB _u(25) +#define SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF1 +// Description : Indicates if any masked-off MSBs in ACCUM1 are set. +#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS _u(0x01000000) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB _u(24) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB _u(24) +#define SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_OVERF0 +// Description : Indicates if any masked-off MSBs in ACCUM0 are set. +#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS _u(0x00800000) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB _u(23) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB _u(23) +#define SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CLAMP +// Description : Only present on INTERP1 on each core. If CLAMP mode is enabled: +// - LANE0 result is shifted and masked ACCUM0, clamped by a lower +// bound of +// BASE0 and an upper bound of BASE1. +// - Signedness of these comparisons is determined by +// LANE0_CTRL_SIGNED +#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS _u(0x00400000) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB _u(22) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB _u(22) +#define SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB _u(20) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB _u(19) +#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE0 result. This does not +// affect FULL result. +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB _u(18) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB _u(18) +#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB _u(17) +#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB _u(16) +#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE0, and LANE0 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB _u(15) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB _u(15) +#define SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB _u(14) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB _u(10) +#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB _u(9) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB _u(5) +#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE0_SHIFT +// Description : Right-rotate applied to accumulator before masking. By +// appropriately configuring the masks, left and right shifts can +// be synthesised. +#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB _u(4) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB _u(0) +#define SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_CTRL_LANE1 +// Description : Control register for lane 1 +#define SIO_INTERP1_CTRL_LANE1_OFFSET _u(0x000000f0) +#define SIO_INTERP1_CTRL_LANE1_BITS _u(0x001fffff) +#define SIO_INTERP1_CTRL_LANE1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_FORCE_MSB +// Description : ORed into bits 29:28 of the lane result presented to the +// processor on the bus. +// No effect on the internal 32-bit datapath. Handy for using a +// lane to generate sequence +// of pointers into flash or SRAM. +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB _u(20) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB _u(19) +#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_ADD_RAW +// Description : If 1, mask + shift is bypassed for LANE1 result. This does not +// affect FULL result. +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB _u(18) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB _u(18) +#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_CROSS_RESULT +// Description : If 1, feed the opposite lane's result into this lane's +// accumulator on POP. +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB _u(17) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB _u(17) +#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_CROSS_INPUT +// Description : If 1, feed the opposite lane's accumulator into this lane's +// shift + mask hardware. +// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is +// before the shift+mask bypass) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB _u(16) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB _u(16) +#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_SIGNED +// Description : If SIGNED is set, the shifted and masked accumulator value is +// sign-extended to 32 bits +// before adding to BASE1, and LANE1 PEEK/POP appear extended to +// 32 bits when read by processor. +#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET _u(0x0) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS _u(0x00008000) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB _u(15) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB _u(15) +#define SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_MASK_MSB +// Description : The most-significant bit allowed to pass by the mask +// (inclusive) +// Setting MSB < LSB may cause chip to turn inside-out +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB _u(14) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB _u(10) +#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_MASK_LSB +// Description : The least-significant bit allowed to pass by the mask +// (inclusive) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB _u(9) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB _u(5) +#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_INTERP1_CTRL_LANE1_SHIFT +// Description : Right-rotate applied to accumulator before masking. By +// appropriately configuring the masks, left and right shifts can +// be synthesised. +#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET _u(0x00) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB _u(4) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB _u(0) +#define SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM0_ADD +// Description : Values written here are atomically added to ACCUM0 +// Reading yields lane 0's raw shift and mask value (BASE0 not +// added). +#define SIO_INTERP1_ACCUM0_ADD_OFFSET _u(0x000000f4) +#define SIO_INTERP1_ACCUM0_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP1_ACCUM0_ADD_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM0_ADD_MSB _u(23) +#define SIO_INTERP1_ACCUM0_ADD_LSB _u(0) +#define SIO_INTERP1_ACCUM0_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_ACCUM1_ADD +// Description : Values written here are atomically added to ACCUM1 +// Reading yields lane 1's raw shift and mask value (BASE1 not +// added). +#define SIO_INTERP1_ACCUM1_ADD_OFFSET _u(0x000000f8) +#define SIO_INTERP1_ACCUM1_ADD_BITS _u(0x00ffffff) +#define SIO_INTERP1_ACCUM1_ADD_RESET _u(0x00000000) +#define SIO_INTERP1_ACCUM1_ADD_MSB _u(23) +#define SIO_INTERP1_ACCUM1_ADD_LSB _u(0) +#define SIO_INTERP1_ACCUM1_ADD_ACCESS "RW" +// ============================================================================= +// Register : SIO_INTERP1_BASE_1AND0 +// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 +// simultaneously. +// Each half is sign-extended to 32 bits if that lane's SIGNED +// flag is set. +#define SIO_INTERP1_BASE_1AND0_OFFSET _u(0x000000fc) +#define SIO_INTERP1_BASE_1AND0_BITS _u(0xffffffff) +#define SIO_INTERP1_BASE_1AND0_RESET _u(0x00000000) +#define SIO_INTERP1_BASE_1AND0_MSB _u(31) +#define SIO_INTERP1_BASE_1AND0_LSB _u(0) +#define SIO_INTERP1_BASE_1AND0_ACCESS "WO" +// ============================================================================= +// Register : SIO_SPINLOCK0 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK0_OFFSET _u(0x00000100) +#define SIO_SPINLOCK0_BITS _u(0xffffffff) +#define SIO_SPINLOCK0_RESET _u(0x00000000) +#define SIO_SPINLOCK0_MSB _u(31) +#define SIO_SPINLOCK0_LSB _u(0) +#define SIO_SPINLOCK0_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK1 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK1_OFFSET _u(0x00000104) +#define SIO_SPINLOCK1_BITS _u(0xffffffff) +#define SIO_SPINLOCK1_RESET _u(0x00000000) +#define SIO_SPINLOCK1_MSB _u(31) +#define SIO_SPINLOCK1_LSB _u(0) +#define SIO_SPINLOCK1_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK2 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK2_OFFSET _u(0x00000108) +#define SIO_SPINLOCK2_BITS _u(0xffffffff) +#define SIO_SPINLOCK2_RESET _u(0x00000000) +#define SIO_SPINLOCK2_MSB _u(31) +#define SIO_SPINLOCK2_LSB _u(0) +#define SIO_SPINLOCK2_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK3 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK3_OFFSET _u(0x0000010c) +#define SIO_SPINLOCK3_BITS _u(0xffffffff) +#define SIO_SPINLOCK3_RESET _u(0x00000000) +#define SIO_SPINLOCK3_MSB _u(31) +#define SIO_SPINLOCK3_LSB _u(0) +#define SIO_SPINLOCK3_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK4 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK4_OFFSET _u(0x00000110) +#define SIO_SPINLOCK4_BITS _u(0xffffffff) +#define SIO_SPINLOCK4_RESET _u(0x00000000) +#define SIO_SPINLOCK4_MSB _u(31) +#define SIO_SPINLOCK4_LSB _u(0) +#define SIO_SPINLOCK4_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK5 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK5_OFFSET _u(0x00000114) +#define SIO_SPINLOCK5_BITS _u(0xffffffff) +#define SIO_SPINLOCK5_RESET _u(0x00000000) +#define SIO_SPINLOCK5_MSB _u(31) +#define SIO_SPINLOCK5_LSB _u(0) +#define SIO_SPINLOCK5_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK6 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK6_OFFSET _u(0x00000118) +#define SIO_SPINLOCK6_BITS _u(0xffffffff) +#define SIO_SPINLOCK6_RESET _u(0x00000000) +#define SIO_SPINLOCK6_MSB _u(31) +#define SIO_SPINLOCK6_LSB _u(0) +#define SIO_SPINLOCK6_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK7 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK7_OFFSET _u(0x0000011c) +#define SIO_SPINLOCK7_BITS _u(0xffffffff) +#define SIO_SPINLOCK7_RESET _u(0x00000000) +#define SIO_SPINLOCK7_MSB _u(31) +#define SIO_SPINLOCK7_LSB _u(0) +#define SIO_SPINLOCK7_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK8 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK8_OFFSET _u(0x00000120) +#define SIO_SPINLOCK8_BITS _u(0xffffffff) +#define SIO_SPINLOCK8_RESET _u(0x00000000) +#define SIO_SPINLOCK8_MSB _u(31) +#define SIO_SPINLOCK8_LSB _u(0) +#define SIO_SPINLOCK8_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK9 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK9_OFFSET _u(0x00000124) +#define SIO_SPINLOCK9_BITS _u(0xffffffff) +#define SIO_SPINLOCK9_RESET _u(0x00000000) +#define SIO_SPINLOCK9_MSB _u(31) +#define SIO_SPINLOCK9_LSB _u(0) +#define SIO_SPINLOCK9_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK10 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK10_OFFSET _u(0x00000128) +#define SIO_SPINLOCK10_BITS _u(0xffffffff) +#define SIO_SPINLOCK10_RESET _u(0x00000000) +#define SIO_SPINLOCK10_MSB _u(31) +#define SIO_SPINLOCK10_LSB _u(0) +#define SIO_SPINLOCK10_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK11 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK11_OFFSET _u(0x0000012c) +#define SIO_SPINLOCK11_BITS _u(0xffffffff) +#define SIO_SPINLOCK11_RESET _u(0x00000000) +#define SIO_SPINLOCK11_MSB _u(31) +#define SIO_SPINLOCK11_LSB _u(0) +#define SIO_SPINLOCK11_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK12 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK12_OFFSET _u(0x00000130) +#define SIO_SPINLOCK12_BITS _u(0xffffffff) +#define SIO_SPINLOCK12_RESET _u(0x00000000) +#define SIO_SPINLOCK12_MSB _u(31) +#define SIO_SPINLOCK12_LSB _u(0) +#define SIO_SPINLOCK12_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK13 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK13_OFFSET _u(0x00000134) +#define SIO_SPINLOCK13_BITS _u(0xffffffff) +#define SIO_SPINLOCK13_RESET _u(0x00000000) +#define SIO_SPINLOCK13_MSB _u(31) +#define SIO_SPINLOCK13_LSB _u(0) +#define SIO_SPINLOCK13_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK14 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK14_OFFSET _u(0x00000138) +#define SIO_SPINLOCK14_BITS _u(0xffffffff) +#define SIO_SPINLOCK14_RESET _u(0x00000000) +#define SIO_SPINLOCK14_MSB _u(31) +#define SIO_SPINLOCK14_LSB _u(0) +#define SIO_SPINLOCK14_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK15 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK15_OFFSET _u(0x0000013c) +#define SIO_SPINLOCK15_BITS _u(0xffffffff) +#define SIO_SPINLOCK15_RESET _u(0x00000000) +#define SIO_SPINLOCK15_MSB _u(31) +#define SIO_SPINLOCK15_LSB _u(0) +#define SIO_SPINLOCK15_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK16 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK16_OFFSET _u(0x00000140) +#define SIO_SPINLOCK16_BITS _u(0xffffffff) +#define SIO_SPINLOCK16_RESET _u(0x00000000) +#define SIO_SPINLOCK16_MSB _u(31) +#define SIO_SPINLOCK16_LSB _u(0) +#define SIO_SPINLOCK16_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK17 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK17_OFFSET _u(0x00000144) +#define SIO_SPINLOCK17_BITS _u(0xffffffff) +#define SIO_SPINLOCK17_RESET _u(0x00000000) +#define SIO_SPINLOCK17_MSB _u(31) +#define SIO_SPINLOCK17_LSB _u(0) +#define SIO_SPINLOCK17_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK18 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK18_OFFSET _u(0x00000148) +#define SIO_SPINLOCK18_BITS _u(0xffffffff) +#define SIO_SPINLOCK18_RESET _u(0x00000000) +#define SIO_SPINLOCK18_MSB _u(31) +#define SIO_SPINLOCK18_LSB _u(0) +#define SIO_SPINLOCK18_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK19 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK19_OFFSET _u(0x0000014c) +#define SIO_SPINLOCK19_BITS _u(0xffffffff) +#define SIO_SPINLOCK19_RESET _u(0x00000000) +#define SIO_SPINLOCK19_MSB _u(31) +#define SIO_SPINLOCK19_LSB _u(0) +#define SIO_SPINLOCK19_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK20 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK20_OFFSET _u(0x00000150) +#define SIO_SPINLOCK20_BITS _u(0xffffffff) +#define SIO_SPINLOCK20_RESET _u(0x00000000) +#define SIO_SPINLOCK20_MSB _u(31) +#define SIO_SPINLOCK20_LSB _u(0) +#define SIO_SPINLOCK20_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK21 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK21_OFFSET _u(0x00000154) +#define SIO_SPINLOCK21_BITS _u(0xffffffff) +#define SIO_SPINLOCK21_RESET _u(0x00000000) +#define SIO_SPINLOCK21_MSB _u(31) +#define SIO_SPINLOCK21_LSB _u(0) +#define SIO_SPINLOCK21_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK22 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK22_OFFSET _u(0x00000158) +#define SIO_SPINLOCK22_BITS _u(0xffffffff) +#define SIO_SPINLOCK22_RESET _u(0x00000000) +#define SIO_SPINLOCK22_MSB _u(31) +#define SIO_SPINLOCK22_LSB _u(0) +#define SIO_SPINLOCK22_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK23 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK23_OFFSET _u(0x0000015c) +#define SIO_SPINLOCK23_BITS _u(0xffffffff) +#define SIO_SPINLOCK23_RESET _u(0x00000000) +#define SIO_SPINLOCK23_MSB _u(31) +#define SIO_SPINLOCK23_LSB _u(0) +#define SIO_SPINLOCK23_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK24 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK24_OFFSET _u(0x00000160) +#define SIO_SPINLOCK24_BITS _u(0xffffffff) +#define SIO_SPINLOCK24_RESET _u(0x00000000) +#define SIO_SPINLOCK24_MSB _u(31) +#define SIO_SPINLOCK24_LSB _u(0) +#define SIO_SPINLOCK24_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK25 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK25_OFFSET _u(0x00000164) +#define SIO_SPINLOCK25_BITS _u(0xffffffff) +#define SIO_SPINLOCK25_RESET _u(0x00000000) +#define SIO_SPINLOCK25_MSB _u(31) +#define SIO_SPINLOCK25_LSB _u(0) +#define SIO_SPINLOCK25_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK26 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK26_OFFSET _u(0x00000168) +#define SIO_SPINLOCK26_BITS _u(0xffffffff) +#define SIO_SPINLOCK26_RESET _u(0x00000000) +#define SIO_SPINLOCK26_MSB _u(31) +#define SIO_SPINLOCK26_LSB _u(0) +#define SIO_SPINLOCK26_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK27 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK27_OFFSET _u(0x0000016c) +#define SIO_SPINLOCK27_BITS _u(0xffffffff) +#define SIO_SPINLOCK27_RESET _u(0x00000000) +#define SIO_SPINLOCK27_MSB _u(31) +#define SIO_SPINLOCK27_LSB _u(0) +#define SIO_SPINLOCK27_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK28 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK28_OFFSET _u(0x00000170) +#define SIO_SPINLOCK28_BITS _u(0xffffffff) +#define SIO_SPINLOCK28_RESET _u(0x00000000) +#define SIO_SPINLOCK28_MSB _u(31) +#define SIO_SPINLOCK28_LSB _u(0) +#define SIO_SPINLOCK28_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK29 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK29_OFFSET _u(0x00000174) +#define SIO_SPINLOCK29_BITS _u(0xffffffff) +#define SIO_SPINLOCK29_RESET _u(0x00000000) +#define SIO_SPINLOCK29_MSB _u(31) +#define SIO_SPINLOCK29_LSB _u(0) +#define SIO_SPINLOCK29_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK30 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK30_OFFSET _u(0x00000178) +#define SIO_SPINLOCK30_BITS _u(0xffffffff) +#define SIO_SPINLOCK30_RESET _u(0x00000000) +#define SIO_SPINLOCK30_MSB _u(31) +#define SIO_SPINLOCK30_LSB _u(0) +#define SIO_SPINLOCK30_ACCESS "RW" +// ============================================================================= +// Register : SIO_SPINLOCK31 +// Description : Reading from a spinlock address will: +// - Return 0 if lock is already locked +// - Otherwise return nonzero, and simultaneously claim the lock +// +// Writing (any value) releases the lock. +// If core 0 and core 1 attempt to claim the same lock +// simultaneously, core 0 wins. +// The value returned on success is 0x1 << lock number. +#define SIO_SPINLOCK31_OFFSET _u(0x0000017c) +#define SIO_SPINLOCK31_BITS _u(0xffffffff) +#define SIO_SPINLOCK31_RESET _u(0x00000000) +#define SIO_SPINLOCK31_MSB _u(31) +#define SIO_SPINLOCK31_LSB _u(0) +#define SIO_SPINLOCK31_ACCESS "RW" +// ============================================================================= +// Register : SIO_DOORBELL_OUT_SET +// Description : Trigger a doorbell interrupt on the opposite core. +// +// Write 1 to a bit to set the corresponding bit in DOORBELL_IN on +// the opposite core. This raises the opposite core's doorbell +// interrupt. +// +// Read to get the status of the doorbells currently asserted on +// the opposite core. This is equivalent to that core reading its +// own DOORBELL_IN status. +#define SIO_DOORBELL_OUT_SET_OFFSET _u(0x00000180) +#define SIO_DOORBELL_OUT_SET_BITS _u(0x000000ff) +#define SIO_DOORBELL_OUT_SET_RESET _u(0x00000000) +#define SIO_DOORBELL_OUT_SET_MSB _u(7) +#define SIO_DOORBELL_OUT_SET_LSB _u(0) +#define SIO_DOORBELL_OUT_SET_ACCESS "RW" +// ============================================================================= +// Register : SIO_DOORBELL_OUT_CLR +// Description : Clear doorbells which have been posted to the opposite core. +// This register is intended for debugging and initialisation +// purposes. +// +// Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding +// bit in DOORBELL_IN on the opposite core. Clearing all bits will +// cause that core's doorbell interrupt to deassert. Since the +// usual order of events is for software to send events using +// DOORBELL_OUT_SET, and acknowledge incoming events by writing to +// DOORBELL_IN_CLR, this register should be used with caution to +// avoid race conditions. +// +// Reading returns the status of the doorbells currently asserted +// on the other core, i.e. is equivalent to that core reading its +// own DOORBELL_IN status. +#define SIO_DOORBELL_OUT_CLR_OFFSET _u(0x00000184) +#define SIO_DOORBELL_OUT_CLR_BITS _u(0x000000ff) +#define SIO_DOORBELL_OUT_CLR_RESET _u(0x00000000) +#define SIO_DOORBELL_OUT_CLR_MSB _u(7) +#define SIO_DOORBELL_OUT_CLR_LSB _u(0) +#define SIO_DOORBELL_OUT_CLR_ACCESS "WC" +// ============================================================================= +// Register : SIO_DOORBELL_IN_SET +// Description : Write 1s to trigger doorbell interrupts on this core. Read to +// get status of doorbells currently asserted on this core. +#define SIO_DOORBELL_IN_SET_OFFSET _u(0x00000188) +#define SIO_DOORBELL_IN_SET_BITS _u(0x000000ff) +#define SIO_DOORBELL_IN_SET_RESET _u(0x00000000) +#define SIO_DOORBELL_IN_SET_MSB _u(7) +#define SIO_DOORBELL_IN_SET_LSB _u(0) +#define SIO_DOORBELL_IN_SET_ACCESS "RW" +// ============================================================================= +// Register : SIO_DOORBELL_IN_CLR +// Description : Check and acknowledge doorbells posted to this core. This +// core's doorbell interrupt is asserted when any bit in this +// register is 1. +// +// Write 1 to each bit to clear that bit. The doorbell interrupt +// deasserts once all bits are cleared. Read to get status of +// doorbells currently asserted on this core. +#define SIO_DOORBELL_IN_CLR_OFFSET _u(0x0000018c) +#define SIO_DOORBELL_IN_CLR_BITS _u(0x000000ff) +#define SIO_DOORBELL_IN_CLR_RESET _u(0x00000000) +#define SIO_DOORBELL_IN_CLR_MSB _u(7) +#define SIO_DOORBELL_IN_CLR_LSB _u(0) +#define SIO_DOORBELL_IN_CLR_ACCESS "WC" +// ============================================================================= +// Register : SIO_PERI_NONSEC +// Description : Detach certain core-local peripherals from Secure SIO, and +// attach them to Non-secure SIO, so that Non-secure software can +// use them. Attempting to access one of these peripherals from +// the Secure SIO when it is attached to the Non-secure SIO, or +// vice versa, will generate a bus error. +// +// This register is per-core, and is only present on the Secure +// SIO. +// +// Most SIO hardware is duplicated across the Secure and Non- +// secure SIO, so is not listed in this register. +#define SIO_PERI_NONSEC_OFFSET _u(0x00000190) +#define SIO_PERI_NONSEC_BITS _u(0x00000023) +#define SIO_PERI_NONSEC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_PERI_NONSEC_TMDS +// Description : IF 1, detach TMDS encoder (of this core) from the Secure SIO, +// and attach to the Non-secure SIO. +#define SIO_PERI_NONSEC_TMDS_RESET _u(0x0) +#define SIO_PERI_NONSEC_TMDS_BITS _u(0x00000020) +#define SIO_PERI_NONSEC_TMDS_MSB _u(5) +#define SIO_PERI_NONSEC_TMDS_LSB _u(5) +#define SIO_PERI_NONSEC_TMDS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_PERI_NONSEC_INTERP1 +// Description : If 1, detach interpolator 1 (of this core) from the Secure SIO, +// and attach to the Non-secure SIO. +#define SIO_PERI_NONSEC_INTERP1_RESET _u(0x0) +#define SIO_PERI_NONSEC_INTERP1_BITS _u(0x00000002) +#define SIO_PERI_NONSEC_INTERP1_MSB _u(1) +#define SIO_PERI_NONSEC_INTERP1_LSB _u(1) +#define SIO_PERI_NONSEC_INTERP1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_PERI_NONSEC_INTERP0 +// Description : If 1, detach interpolator 0 (of this core) from the Secure SIO, +// and attach to the Non-secure SIO. +#define SIO_PERI_NONSEC_INTERP0_RESET _u(0x0) +#define SIO_PERI_NONSEC_INTERP0_BITS _u(0x00000001) +#define SIO_PERI_NONSEC_INTERP0_MSB _u(0) +#define SIO_PERI_NONSEC_INTERP0_LSB _u(0) +#define SIO_PERI_NONSEC_INTERP0_ACCESS "RW" +// ============================================================================= +// Register : SIO_RISCV_SOFTIRQ +// Description : Control the assertion of the standard software interrupt +// (MIP.MSIP) on the RISC-V cores. +// +// Unlike the RISC-V timer, this interrupt is not routed to a +// normal system-level interrupt line, so can not be used by the +// Arm cores. +// +// It is safe for both cores to write to this register on the same +// cycle. The set/clear effect is accumulated across both cores, +// and then applied. If a flag is both set and cleared on the same +// cycle, only the set takes effect. +#define SIO_RISCV_SOFTIRQ_OFFSET _u(0x000001a0) +#define SIO_RISCV_SOFTIRQ_BITS _u(0x00000303) +#define SIO_RISCV_SOFTIRQ_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_RISCV_SOFTIRQ_CORE1_CLR +// Description : Write 1 to atomically clear the core 1 software interrupt flag. +// Read to get the status of this flag. +#define SIO_RISCV_SOFTIRQ_CORE1_CLR_RESET _u(0x0) +#define SIO_RISCV_SOFTIRQ_CORE1_CLR_BITS _u(0x00000200) +#define SIO_RISCV_SOFTIRQ_CORE1_CLR_MSB _u(9) +#define SIO_RISCV_SOFTIRQ_CORE1_CLR_LSB _u(9) +#define SIO_RISCV_SOFTIRQ_CORE1_CLR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_RISCV_SOFTIRQ_CORE0_CLR +// Description : Write 1 to atomically clear the core 0 software interrupt flag. +// Read to get the status of this flag. +#define SIO_RISCV_SOFTIRQ_CORE0_CLR_RESET _u(0x0) +#define SIO_RISCV_SOFTIRQ_CORE0_CLR_BITS _u(0x00000100) +#define SIO_RISCV_SOFTIRQ_CORE0_CLR_MSB _u(8) +#define SIO_RISCV_SOFTIRQ_CORE0_CLR_LSB _u(8) +#define SIO_RISCV_SOFTIRQ_CORE0_CLR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_RISCV_SOFTIRQ_CORE1_SET +// Description : Write 1 to atomically set the core 1 software interrupt flag. +// Read to get the status of this flag. +#define SIO_RISCV_SOFTIRQ_CORE1_SET_RESET _u(0x0) +#define SIO_RISCV_SOFTIRQ_CORE1_SET_BITS _u(0x00000002) +#define SIO_RISCV_SOFTIRQ_CORE1_SET_MSB _u(1) +#define SIO_RISCV_SOFTIRQ_CORE1_SET_LSB _u(1) +#define SIO_RISCV_SOFTIRQ_CORE1_SET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_RISCV_SOFTIRQ_CORE0_SET +// Description : Write 1 to atomically set the core 0 software interrupt flag. +// Read to get the status of this flag. +#define SIO_RISCV_SOFTIRQ_CORE0_SET_RESET _u(0x0) +#define SIO_RISCV_SOFTIRQ_CORE0_SET_BITS _u(0x00000001) +#define SIO_RISCV_SOFTIRQ_CORE0_SET_MSB _u(0) +#define SIO_RISCV_SOFTIRQ_CORE0_SET_LSB _u(0) +#define SIO_RISCV_SOFTIRQ_CORE0_SET_ACCESS "RW" +// ============================================================================= +// Register : SIO_MTIME_CTRL +// Description : Control register for the RISC-V 64-bit Machine-mode timer. This +// timer is only present in the Secure SIO, so is only accessible +// to an Arm core in Secure mode or a RISC-V core in Machine mode. +// +// Note whilst this timer follows the RISC-V privileged +// specification, it is equally usable by the Arm cores. The +// interrupts are routed to normal system-level interrupt lines as +// well as to the MIP.MTIP inputs on the RISC-V cores. +#define SIO_MTIME_CTRL_OFFSET _u(0x000001a4) +#define SIO_MTIME_CTRL_BITS _u(0x0000000f) +#define SIO_MTIME_CTRL_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : SIO_MTIME_CTRL_DBGPAUSE_CORE1 +// Description : If 1, the timer pauses when core 1 is in the debug halt state. +#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_RESET _u(0x1) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_BITS _u(0x00000008) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_MSB _u(3) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_LSB _u(3) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_MTIME_CTRL_DBGPAUSE_CORE0 +// Description : If 1, the timer pauses when core 0 is in the debug halt state. +#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_RESET _u(0x1) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_BITS _u(0x00000004) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_MSB _u(2) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_LSB _u(2) +#define SIO_MTIME_CTRL_DBGPAUSE_CORE0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_MTIME_CTRL_FULLSPEED +// Description : If 1, increment the timer every cycle (i.e. run directly from +// the system clock), rather than incrementing on the system-level +// timer tick input. +#define SIO_MTIME_CTRL_FULLSPEED_RESET _u(0x0) +#define SIO_MTIME_CTRL_FULLSPEED_BITS _u(0x00000002) +#define SIO_MTIME_CTRL_FULLSPEED_MSB _u(1) +#define SIO_MTIME_CTRL_FULLSPEED_LSB _u(1) +#define SIO_MTIME_CTRL_FULLSPEED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_MTIME_CTRL_EN +// Description : Timer enable bit. When 0, the timer will not increment +// automatically. +#define SIO_MTIME_CTRL_EN_RESET _u(0x1) +#define SIO_MTIME_CTRL_EN_BITS _u(0x00000001) +#define SIO_MTIME_CTRL_EN_MSB _u(0) +#define SIO_MTIME_CTRL_EN_LSB _u(0) +#define SIO_MTIME_CTRL_EN_ACCESS "RW" +// ============================================================================= +// Register : SIO_MTIME +// Description : Read/write access to the high half of RISC-V Machine-mode +// timer. This register is shared between both cores. If both +// cores write on the same cycle, core 1 takes precedence. +#define SIO_MTIME_OFFSET _u(0x000001b0) +#define SIO_MTIME_BITS _u(0xffffffff) +#define SIO_MTIME_RESET _u(0x00000000) +#define SIO_MTIME_MSB _u(31) +#define SIO_MTIME_LSB _u(0) +#define SIO_MTIME_ACCESS "RW" +// ============================================================================= +// Register : SIO_MTIMEH +// Description : Read/write access to the high half of RISC-V Machine-mode +// timer. This register is shared between both cores. If both +// cores write on the same cycle, core 1 takes precedence. +#define SIO_MTIMEH_OFFSET _u(0x000001b4) +#define SIO_MTIMEH_BITS _u(0xffffffff) +#define SIO_MTIMEH_RESET _u(0x00000000) +#define SIO_MTIMEH_MSB _u(31) +#define SIO_MTIMEH_LSB _u(0) +#define SIO_MTIMEH_ACCESS "RW" +// ============================================================================= +// Register : SIO_MTIMECMP +// Description : Low half of RISC-V Machine-mode timer comparator. This register +// is core-local, i.e., each core gets a copy of this register, +// with the comparison result routed to its own interrupt line. +// +// The timer interrupt is asserted whenever MTIME is greater than +// or equal to MTIMECMP. This comparison is unsigned, and +// performed on the full 64-bit values. +#define SIO_MTIMECMP_OFFSET _u(0x000001b8) +#define SIO_MTIMECMP_BITS _u(0xffffffff) +#define SIO_MTIMECMP_RESET _u(0xffffffff) +#define SIO_MTIMECMP_MSB _u(31) +#define SIO_MTIMECMP_LSB _u(0) +#define SIO_MTIMECMP_ACCESS "RW" +// ============================================================================= +// Register : SIO_MTIMECMPH +// Description : High half of RISC-V Machine-mode timer comparator. This +// register is core-local. +// +// The timer interrupt is asserted whenever MTIME is greater than +// or equal to MTIMECMP. This comparison is unsigned, and +// performed on the full 64-bit values. +#define SIO_MTIMECMPH_OFFSET _u(0x000001bc) +#define SIO_MTIMECMPH_BITS _u(0xffffffff) +#define SIO_MTIMECMPH_RESET _u(0xffffffff) +#define SIO_MTIMECMPH_MSB _u(31) +#define SIO_MTIMECMPH_LSB _u(0) +#define SIO_MTIMECMPH_ACCESS "RW" +// ============================================================================= +// Register : SIO_TMDS_CTRL +// Description : Control register for TMDS encoder. +#define SIO_TMDS_CTRL_OFFSET _u(0x000001c0) +#define SIO_TMDS_CTRL_BITS _u(0x1f9fffff) +#define SIO_TMDS_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_CLEAR_BALANCE +// Description : Clear the running DC balance state of the TMDS encoders. This +// bit should be written once at the beginning of each scanline. +#define SIO_TMDS_CTRL_CLEAR_BALANCE_RESET _u(0x0) +#define SIO_TMDS_CTRL_CLEAR_BALANCE_BITS _u(0x10000000) +#define SIO_TMDS_CTRL_CLEAR_BALANCE_MSB _u(28) +#define SIO_TMDS_CTRL_CLEAR_BALANCE_LSB _u(28) +#define SIO_TMDS_CTRL_CLEAR_BALANCE_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_PIX2_NOSHIFT +// Description : When encoding two pixels's worth of symbols in one cycle (a +// read of a PEEK/POP_DOUBLE register), the second encoder sees a +// shifted version of the colour data register. +// +// This control disables that shift, so that both encoder layers +// see the same pixel data. This is used for pixel doubling. +#define SIO_TMDS_CTRL_PIX2_NOSHIFT_RESET _u(0x0) +#define SIO_TMDS_CTRL_PIX2_NOSHIFT_BITS _u(0x08000000) +#define SIO_TMDS_CTRL_PIX2_NOSHIFT_MSB _u(27) +#define SIO_TMDS_CTRL_PIX2_NOSHIFT_LSB _u(27) +#define SIO_TMDS_CTRL_PIX2_NOSHIFT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_PIX_SHIFT +// Description : Shift applied to the colour data register with each read of a +// POP alias register. +// +// Reading from the POP_SINGLE register, or reading from the +// POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), +// shifts by the indicated amount. +// +// Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear +// will shift by double the indicated amount. (Shift by 32 means +// no shift.) +// 0x0 -> Do not shift the colour data register. +// 0x1 -> Shift the colour data register by 1 bit +// 0x2 -> Shift the colour data register by 2 bits +// 0x3 -> Shift the colour data register by 4 bits +// 0x4 -> Shift the colour data register by 8 bits +// 0x5 -> Shift the colour data register by 16 bits +#define SIO_TMDS_CTRL_PIX_SHIFT_RESET _u(0x0) +#define SIO_TMDS_CTRL_PIX_SHIFT_BITS _u(0x07000000) +#define SIO_TMDS_CTRL_PIX_SHIFT_MSB _u(26) +#define SIO_TMDS_CTRL_PIX_SHIFT_LSB _u(24) +#define SIO_TMDS_CTRL_PIX_SHIFT_ACCESS "RW" +#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_0 _u(0x0) +#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_1 _u(0x1) +#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_2 _u(0x2) +#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_4 _u(0x3) +#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_8 _u(0x4) +#define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_16 _u(0x5) +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_INTERLEAVE +// Description : Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. +// +// When interleaving is disabled, each of the 3 symbols appears as +// a contiguous 10-bit field, with lane 0 being the least- +// significant and starting at bit 0 of the register. +// +// When interleaving is enabled, the symbols are packed into 5 +// chunks of 3 lanes times 2 bits (30 bits total). Each chunk +// contains two bits of a TMDS symbol per lane, with lane 0 being +// the least significant. +#define SIO_TMDS_CTRL_INTERLEAVE_RESET _u(0x0) +#define SIO_TMDS_CTRL_INTERLEAVE_BITS _u(0x00800000) +#define SIO_TMDS_CTRL_INTERLEAVE_MSB _u(23) +#define SIO_TMDS_CTRL_INTERLEAVE_LSB _u(23) +#define SIO_TMDS_CTRL_INTERLEAVE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_L2_NBITS +// Description : Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 +// through 7). Remaining LSBs are masked to 0 after the rotate. +#define SIO_TMDS_CTRL_L2_NBITS_RESET _u(0x0) +#define SIO_TMDS_CTRL_L2_NBITS_BITS _u(0x001c0000) +#define SIO_TMDS_CTRL_L2_NBITS_MSB _u(20) +#define SIO_TMDS_CTRL_L2_NBITS_LSB _u(18) +#define SIO_TMDS_CTRL_L2_NBITS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_L1_NBITS +// Description : Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 +// through 7). Remaining LSBs are masked to 0 after the rotate. +#define SIO_TMDS_CTRL_L1_NBITS_RESET _u(0x0) +#define SIO_TMDS_CTRL_L1_NBITS_BITS _u(0x00038000) +#define SIO_TMDS_CTRL_L1_NBITS_MSB _u(17) +#define SIO_TMDS_CTRL_L1_NBITS_LSB _u(15) +#define SIO_TMDS_CTRL_L1_NBITS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_L0_NBITS +// Description : Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 +// through 7). Remaining LSBs are masked to 0 after the rotate. +#define SIO_TMDS_CTRL_L0_NBITS_RESET _u(0x0) +#define SIO_TMDS_CTRL_L0_NBITS_BITS _u(0x00007000) +#define SIO_TMDS_CTRL_L0_NBITS_MSB _u(14) +#define SIO_TMDS_CTRL_L0_NBITS_LSB _u(12) +#define SIO_TMDS_CTRL_L0_NBITS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_L2_ROT +// Description : Right-rotate the 16 LSBs of the colour accumulator by 0-15 +// bits, in order to get the MSB of the lane 2 (red) colour data +// aligned with the MSB of the 8-bit encoder input. +// +// For example, for RGB565 (red most significant), red is bits +// 15:11, so should be right-rotated by 8 bits to align with bits +// 7:3 of the encoder input. +#define SIO_TMDS_CTRL_L2_ROT_RESET _u(0x0) +#define SIO_TMDS_CTRL_L2_ROT_BITS _u(0x00000f00) +#define SIO_TMDS_CTRL_L2_ROT_MSB _u(11) +#define SIO_TMDS_CTRL_L2_ROT_LSB _u(8) +#define SIO_TMDS_CTRL_L2_ROT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_L1_ROT +// Description : Right-rotate the 16 LSBs of the colour accumulator by 0-15 +// bits, in order to get the MSB of the lane 1 (green) colour data +// aligned with the MSB of the 8-bit encoder input. +// +// For example, for RGB565, green is bits 10:5, so should be +// right-rotated by 3 bits to align with bits 7:2 of the encoder +// input. +#define SIO_TMDS_CTRL_L1_ROT_RESET _u(0x0) +#define SIO_TMDS_CTRL_L1_ROT_BITS _u(0x000000f0) +#define SIO_TMDS_CTRL_L1_ROT_MSB _u(7) +#define SIO_TMDS_CTRL_L1_ROT_LSB _u(4) +#define SIO_TMDS_CTRL_L1_ROT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SIO_TMDS_CTRL_L0_ROT +// Description : Right-rotate the 16 LSBs of the colour accumulator by 0-15 +// bits, in order to get the MSB of the lane 0 (blue) colour data +// aligned with the MSB of the 8-bit encoder input. +// +// For example, for RGB565 (red most significant), blue is bits +// 4:0, so should be right-rotated by 13 to align with bits 7:3 of +// the encoder input. +#define SIO_TMDS_CTRL_L0_ROT_RESET _u(0x0) +#define SIO_TMDS_CTRL_L0_ROT_BITS _u(0x0000000f) +#define SIO_TMDS_CTRL_L0_ROT_MSB _u(3) +#define SIO_TMDS_CTRL_L0_ROT_LSB _u(0) +#define SIO_TMDS_CTRL_L0_ROT_ACCESS "RW" +// ============================================================================= +// Register : SIO_TMDS_WDATA +// Description : Write-only access to the TMDS colour data register. +#define SIO_TMDS_WDATA_OFFSET _u(0x000001c4) +#define SIO_TMDS_WDATA_BITS _u(0xffffffff) +#define SIO_TMDS_WDATA_RESET _u(0x00000000) +#define SIO_TMDS_WDATA_MSB _u(31) +#define SIO_TMDS_WDATA_LSB _u(0) +#define SIO_TMDS_WDATA_ACCESS "WO" +// ============================================================================= +// Register : SIO_TMDS_PEEK_SINGLE +// Description : Get the encoding of one pixel's worth of colour data, packed +// into a 32-bit value (3x10-bit symbols). +// +// The PEEK alias does not shift the colour register when read, +// but still advances the running DC balance state of each +// encoder. This is useful for pixel doubling. +#define SIO_TMDS_PEEK_SINGLE_OFFSET _u(0x000001c8) +#define SIO_TMDS_PEEK_SINGLE_BITS _u(0xffffffff) +#define SIO_TMDS_PEEK_SINGLE_RESET _u(0x00000000) +#define SIO_TMDS_PEEK_SINGLE_MSB _u(31) +#define SIO_TMDS_PEEK_SINGLE_LSB _u(0) +#define SIO_TMDS_PEEK_SINGLE_ACCESS "RF" +// ============================================================================= +// Register : SIO_TMDS_POP_SINGLE +// Description : Get the encoding of one pixel's worth of colour data, packed +// into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 +// bits (30 bits total). Each chunk contains two bits of a TMDS +// symbol per lane. This format is intended for shifting out with +// the HSTX peripheral on RP2350. +// +// The POP alias shifts the colour register when read, as well as +// advancing the running DC balance state of each encoder. +#define SIO_TMDS_POP_SINGLE_OFFSET _u(0x000001cc) +#define SIO_TMDS_POP_SINGLE_BITS _u(0xffffffff) +#define SIO_TMDS_POP_SINGLE_RESET _u(0x00000000) +#define SIO_TMDS_POP_SINGLE_MSB _u(31) +#define SIO_TMDS_POP_SINGLE_LSB _u(0) +#define SIO_TMDS_POP_SINGLE_ACCESS "RF" +// ============================================================================= +// Register : SIO_TMDS_PEEK_DOUBLE_L0 +// Description : Get lane 0 of the encoding of two pixels' worth of colour data. +// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit +// word. +// +// The PEEK alias does not shift the colour register when read, +// but still advances the lane 0 DC balance state. This is useful +// if all 3 lanes' worth of encode are to be read at once, rather +// than processing the entire scanline for one lane before moving +// to the next lane. +#define SIO_TMDS_PEEK_DOUBLE_L0_OFFSET _u(0x000001d0) +#define SIO_TMDS_PEEK_DOUBLE_L0_BITS _u(0xffffffff) +#define SIO_TMDS_PEEK_DOUBLE_L0_RESET _u(0x00000000) +#define SIO_TMDS_PEEK_DOUBLE_L0_MSB _u(31) +#define SIO_TMDS_PEEK_DOUBLE_L0_LSB _u(0) +#define SIO_TMDS_PEEK_DOUBLE_L0_ACCESS "RF" +// ============================================================================= +// Register : SIO_TMDS_POP_DOUBLE_L0 +// Description : Get lane 0 of the encoding of two pixels' worth of colour data. +// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit +// word. +// +// The POP alias shifts the colour register when read, according +// to the values of PIX_SHIFT and PIX2_NOSHIFT. +#define SIO_TMDS_POP_DOUBLE_L0_OFFSET _u(0x000001d4) +#define SIO_TMDS_POP_DOUBLE_L0_BITS _u(0xffffffff) +#define SIO_TMDS_POP_DOUBLE_L0_RESET _u(0x00000000) +#define SIO_TMDS_POP_DOUBLE_L0_MSB _u(31) +#define SIO_TMDS_POP_DOUBLE_L0_LSB _u(0) +#define SIO_TMDS_POP_DOUBLE_L0_ACCESS "RF" +// ============================================================================= +// Register : SIO_TMDS_PEEK_DOUBLE_L1 +// Description : Get lane 1 of the encoding of two pixels' worth of colour data. +// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit +// word. +// +// The PEEK alias does not shift the colour register when read, +// but still advances the lane 1 DC balance state. This is useful +// if all 3 lanes' worth of encode are to be read at once, rather +// than processing the entire scanline for one lane before moving +// to the next lane. +#define SIO_TMDS_PEEK_DOUBLE_L1_OFFSET _u(0x000001d8) +#define SIO_TMDS_PEEK_DOUBLE_L1_BITS _u(0xffffffff) +#define SIO_TMDS_PEEK_DOUBLE_L1_RESET _u(0x00000000) +#define SIO_TMDS_PEEK_DOUBLE_L1_MSB _u(31) +#define SIO_TMDS_PEEK_DOUBLE_L1_LSB _u(0) +#define SIO_TMDS_PEEK_DOUBLE_L1_ACCESS "RF" +// ============================================================================= +// Register : SIO_TMDS_POP_DOUBLE_L1 +// Description : Get lane 1 of the encoding of two pixels' worth of colour data. +// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit +// word. +// +// The POP alias shifts the colour register when read, according +// to the values of PIX_SHIFT and PIX2_NOSHIFT. +#define SIO_TMDS_POP_DOUBLE_L1_OFFSET _u(0x000001dc) +#define SIO_TMDS_POP_DOUBLE_L1_BITS _u(0xffffffff) +#define SIO_TMDS_POP_DOUBLE_L1_RESET _u(0x00000000) +#define SIO_TMDS_POP_DOUBLE_L1_MSB _u(31) +#define SIO_TMDS_POP_DOUBLE_L1_LSB _u(0) +#define SIO_TMDS_POP_DOUBLE_L1_ACCESS "RF" +// ============================================================================= +// Register : SIO_TMDS_PEEK_DOUBLE_L2 +// Description : Get lane 2 of the encoding of two pixels' worth of colour data. +// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit +// word. +// +// The PEEK alias does not shift the colour register when read, +// but still advances the lane 2 DC balance state. This is useful +// if all 3 lanes' worth of encode are to be read at once, rather +// than processing the entire scanline for one lane before moving +// to the next lane. +#define SIO_TMDS_PEEK_DOUBLE_L2_OFFSET _u(0x000001e0) +#define SIO_TMDS_PEEK_DOUBLE_L2_BITS _u(0xffffffff) +#define SIO_TMDS_PEEK_DOUBLE_L2_RESET _u(0x00000000) +#define SIO_TMDS_PEEK_DOUBLE_L2_MSB _u(31) +#define SIO_TMDS_PEEK_DOUBLE_L2_LSB _u(0) +#define SIO_TMDS_PEEK_DOUBLE_L2_ACCESS "RF" +// ============================================================================= +// Register : SIO_TMDS_POP_DOUBLE_L2 +// Description : Get lane 2 of the encoding of two pixels' worth of colour data. +// Two 10-bit TMDS symbols are packed at the bottom of a 32-bit +// word. +// +// The POP alias shifts the colour register when read, according +// to the values of PIX_SHIFT and PIX2_NOSHIFT. +#define SIO_TMDS_POP_DOUBLE_L2_OFFSET _u(0x000001e4) +#define SIO_TMDS_POP_DOUBLE_L2_BITS _u(0xffffffff) +#define SIO_TMDS_POP_DOUBLE_L2_RESET _u(0x00000000) +#define SIO_TMDS_POP_DOUBLE_L2_MSB _u(31) +#define SIO_TMDS_POP_DOUBLE_L2_LSB _u(0) +#define SIO_TMDS_POP_DOUBLE_L2_ACCESS "RF" +// ============================================================================= +#endif // _HARDWARE_REGS_SIO_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/spi.h b/lib/pico-sdk/rp2350/hardware/regs/spi.h new file mode 100644 index 000000000000..d9d3b14df67a --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/spi.h @@ -0,0 +1,523 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SPI +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_SPI_H +#define _HARDWARE_REGS_SPI_H +// ============================================================================= +// Register : SPI_SSPCR0 +// Description : Control register 0, SSPCR0 on page 3-4 +#define SPI_SSPCR0_OFFSET _u(0x00000000) +#define SPI_SSPCR0_BITS _u(0x0000ffff) +#define SPI_SSPCR0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_SCR +// Description : Serial clock rate. The value SCR is used to generate the +// transmit and receive bit rate of the PrimeCell SSP. The bit +// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even +// value from 2-254, programmed through the SSPCPSR register and +// SCR is a value from 0-255. +#define SPI_SSPCR0_SCR_RESET _u(0x00) +#define SPI_SSPCR0_SCR_BITS _u(0x0000ff00) +#define SPI_SSPCR0_SCR_MSB _u(15) +#define SPI_SSPCR0_SCR_LSB _u(8) +#define SPI_SSPCR0_SCR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_SPH +// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only. +// See Motorola SPI frame format on page 2-10. +#define SPI_SSPCR0_SPH_RESET _u(0x0) +#define SPI_SSPCR0_SPH_BITS _u(0x00000080) +#define SPI_SSPCR0_SPH_MSB _u(7) +#define SPI_SSPCR0_SPH_LSB _u(7) +#define SPI_SSPCR0_SPH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_SPO +// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format +// only. See Motorola SPI frame format on page 2-10. +#define SPI_SSPCR0_SPO_RESET _u(0x0) +#define SPI_SSPCR0_SPO_BITS _u(0x00000040) +#define SPI_SSPCR0_SPO_MSB _u(6) +#define SPI_SSPCR0_SPO_LSB _u(6) +#define SPI_SSPCR0_SPO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_FRF +// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous +// serial frame format. 10 National Microwire frame format. 11 +// Reserved, undefined operation. +#define SPI_SSPCR0_FRF_RESET _u(0x0) +#define SPI_SSPCR0_FRF_BITS _u(0x00000030) +#define SPI_SSPCR0_FRF_MSB _u(5) +#define SPI_SSPCR0_FRF_LSB _u(4) +#define SPI_SSPCR0_FRF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR0_DSS +// Description : Data Size Select: 0000 Reserved, undefined operation. 0001 +// Reserved, undefined operation. 0010 Reserved, undefined +// operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. +// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit +// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. +// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. +#define SPI_SSPCR0_DSS_RESET _u(0x0) +#define SPI_SSPCR0_DSS_BITS _u(0x0000000f) +#define SPI_SSPCR0_DSS_MSB _u(3) +#define SPI_SSPCR0_DSS_LSB _u(0) +#define SPI_SSPCR0_DSS_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPCR1 +// Description : Control register 1, SSPCR1 on page 3-5 +#define SPI_SSPCR1_OFFSET _u(0x00000004) +#define SPI_SSPCR1_BITS _u(0x0000000f) +#define SPI_SSPCR1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_SOD +// Description : Slave-mode output disable. This bit is relevant only in the +// slave mode, MS=1. In multiple-slave systems, it is possible for +// an PrimeCell SSP master to broadcast a message to all slaves in +// the system while ensuring that only one slave drives data onto +// its serial output line. In such systems the RXD lines from +// multiple slaves could be tied together. To operate in such +// systems, the SOD bit can be set if the PrimeCell SSP slave is +// not supposed to drive the SSPTXD line: 0 SSP can drive the +// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD +// output in slave mode. +#define SPI_SSPCR1_SOD_RESET _u(0x0) +#define SPI_SSPCR1_SOD_BITS _u(0x00000008) +#define SPI_SSPCR1_SOD_MSB _u(3) +#define SPI_SSPCR1_SOD_LSB _u(3) +#define SPI_SSPCR1_SOD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_MS +// Description : Master or slave mode select. This bit can be modified only when +// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as +// master, default. 1 Device configured as slave. +#define SPI_SSPCR1_MS_RESET _u(0x0) +#define SPI_SSPCR1_MS_BITS _u(0x00000004) +#define SPI_SSPCR1_MS_MSB _u(2) +#define SPI_SSPCR1_MS_LSB _u(2) +#define SPI_SSPCR1_MS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_SSE +// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP +// operation enabled. +#define SPI_SSPCR1_SSE_RESET _u(0x0) +#define SPI_SSPCR1_SSE_BITS _u(0x00000002) +#define SPI_SSPCR1_SSE_MSB _u(1) +#define SPI_SSPCR1_SSE_LSB _u(1) +#define SPI_SSPCR1_SSE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCR1_LBM +// Description : Loop back mode: 0 Normal serial port operation enabled. 1 +// Output of transmit serial shifter is connected to input of +// receive serial shifter internally. +#define SPI_SSPCR1_LBM_RESET _u(0x0) +#define SPI_SSPCR1_LBM_BITS _u(0x00000001) +#define SPI_SSPCR1_LBM_MSB _u(0) +#define SPI_SSPCR1_LBM_LSB _u(0) +#define SPI_SSPCR1_LBM_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPDR +// Description : Data register, SSPDR on page 3-6 +#define SPI_SSPDR_OFFSET _u(0x00000008) +#define SPI_SSPDR_BITS _u(0x0000ffff) +#define SPI_SSPDR_RESET "-" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPDR_DATA +// Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. +// You must right-justify data when the PrimeCell SSP is +// programmed for a data size that is less than 16 bits. Unused +// bits at the top are ignored by transmit logic. The receive +// logic automatically right-justifies. +#define SPI_SSPDR_DATA_RESET "-" +#define SPI_SSPDR_DATA_BITS _u(0x0000ffff) +#define SPI_SSPDR_DATA_MSB _u(15) +#define SPI_SSPDR_DATA_LSB _u(0) +#define SPI_SSPDR_DATA_ACCESS "RWF" +// ============================================================================= +// Register : SPI_SSPSR +// Description : Status register, SSPSR on page 3-7 +#define SPI_SSPSR_OFFSET _u(0x0000000c) +#define SPI_SSPSR_BITS _u(0x0000001f) +#define SPI_SSPSR_RESET _u(0x00000003) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_BSY +// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently +// transmitting and/or receiving a frame or the transmit FIFO is +// not empty. +#define SPI_SSPSR_BSY_RESET _u(0x0) +#define SPI_SSPSR_BSY_BITS _u(0x00000010) +#define SPI_SSPSR_BSY_MSB _u(4) +#define SPI_SSPSR_BSY_LSB _u(4) +#define SPI_SSPSR_BSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_RFF +// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive +// FIFO is full. +#define SPI_SSPSR_RFF_RESET _u(0x0) +#define SPI_SSPSR_RFF_BITS _u(0x00000008) +#define SPI_SSPSR_RFF_MSB _u(3) +#define SPI_SSPSR_RFF_LSB _u(3) +#define SPI_SSPSR_RFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_RNE +// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive +// FIFO is not empty. +#define SPI_SSPSR_RNE_RESET _u(0x0) +#define SPI_SSPSR_RNE_BITS _u(0x00000004) +#define SPI_SSPSR_RNE_MSB _u(2) +#define SPI_SSPSR_RNE_LSB _u(2) +#define SPI_SSPSR_RNE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_TNF +// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit +// FIFO is not full. +#define SPI_SSPSR_TNF_RESET _u(0x1) +#define SPI_SSPSR_TNF_BITS _u(0x00000002) +#define SPI_SSPSR_TNF_MSB _u(1) +#define SPI_SSPSR_TNF_LSB _u(1) +#define SPI_SSPSR_TNF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPSR_TFE +// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 +// Transmit FIFO is empty. +#define SPI_SSPSR_TFE_RESET _u(0x1) +#define SPI_SSPSR_TFE_BITS _u(0x00000001) +#define SPI_SSPSR_TFE_MSB _u(0) +#define SPI_SSPSR_TFE_LSB _u(0) +#define SPI_SSPSR_TFE_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPCPSR +// Description : Clock prescale register, SSPCPSR on page 3-8 +#define SPI_SSPCPSR_OFFSET _u(0x00000010) +#define SPI_SSPCPSR_BITS _u(0x000000ff) +#define SPI_SSPCPSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPCPSR_CPSDVSR +// Description : Clock prescale divisor. Must be an even number from 2-254, +// depending on the frequency of SSPCLK. The least significant bit +// always returns zero on reads. +#define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00) +#define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff) +#define SPI_SSPCPSR_CPSDVSR_MSB _u(7) +#define SPI_SSPCPSR_CPSDVSR_LSB _u(0) +#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPIMSC +// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9 +#define SPI_SSPIMSC_OFFSET _u(0x00000014) +#define SPI_SSPIMSC_BITS _u(0x0000000f) +#define SPI_SSPIMSC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_TXIM +// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or +// less condition interrupt is masked. 1 Transmit FIFO half empty +// or less condition interrupt is not masked. +#define SPI_SSPIMSC_TXIM_RESET _u(0x0) +#define SPI_SSPIMSC_TXIM_BITS _u(0x00000008) +#define SPI_SSPIMSC_TXIM_MSB _u(3) +#define SPI_SSPIMSC_TXIM_LSB _u(3) +#define SPI_SSPIMSC_TXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_RXIM +// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less +// condition interrupt is masked. 1 Receive FIFO half full or less +// condition interrupt is not masked. +#define SPI_SSPIMSC_RXIM_RESET _u(0x0) +#define SPI_SSPIMSC_RXIM_BITS _u(0x00000004) +#define SPI_SSPIMSC_RXIM_MSB _u(2) +#define SPI_SSPIMSC_RXIM_LSB _u(2) +#define SPI_SSPIMSC_RXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_RTIM +// Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no +// read prior to timeout period interrupt is masked. 1 Receive +// FIFO not empty and no read prior to timeout period interrupt is +// not masked. +#define SPI_SSPIMSC_RTIM_RESET _u(0x0) +#define SPI_SSPIMSC_RTIM_BITS _u(0x00000002) +#define SPI_SSPIMSC_RTIM_MSB _u(1) +#define SPI_SSPIMSC_RTIM_LSB _u(1) +#define SPI_SSPIMSC_RTIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPIMSC_RORIM +// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while +// full condition interrupt is masked. 1 Receive FIFO written to +// while full condition interrupt is not masked. +#define SPI_SSPIMSC_RORIM_RESET _u(0x0) +#define SPI_SSPIMSC_RORIM_BITS _u(0x00000001) +#define SPI_SSPIMSC_RORIM_MSB _u(0) +#define SPI_SSPIMSC_RORIM_LSB _u(0) +#define SPI_SSPIMSC_RORIM_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPRIS +// Description : Raw interrupt status register, SSPRIS on page 3-10 +#define SPI_SSPRIS_OFFSET _u(0x00000018) +#define SPI_SSPRIS_BITS _u(0x0000000f) +#define SPI_SSPRIS_RESET _u(0x00000008) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_TXRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPTXINTR interrupt +#define SPI_SSPRIS_TXRIS_RESET _u(0x1) +#define SPI_SSPRIS_TXRIS_BITS _u(0x00000008) +#define SPI_SSPRIS_TXRIS_MSB _u(3) +#define SPI_SSPRIS_TXRIS_LSB _u(3) +#define SPI_SSPRIS_TXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_RXRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPRXINTR interrupt +#define SPI_SSPRIS_RXRIS_RESET _u(0x0) +#define SPI_SSPRIS_RXRIS_BITS _u(0x00000004) +#define SPI_SSPRIS_RXRIS_MSB _u(2) +#define SPI_SSPRIS_RXRIS_LSB _u(2) +#define SPI_SSPRIS_RXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_RTRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPRTINTR interrupt +#define SPI_SSPRIS_RTRIS_RESET _u(0x0) +#define SPI_SSPRIS_RTRIS_BITS _u(0x00000002) +#define SPI_SSPRIS_RTRIS_MSB _u(1) +#define SPI_SSPRIS_RTRIS_LSB _u(1) +#define SPI_SSPRIS_RTRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPRIS_RORRIS +// Description : Gives the raw interrupt state, prior to masking, of the +// SSPRORINTR interrupt +#define SPI_SSPRIS_RORRIS_RESET _u(0x0) +#define SPI_SSPRIS_RORRIS_BITS _u(0x00000001) +#define SPI_SSPRIS_RORRIS_MSB _u(0) +#define SPI_SSPRIS_RORRIS_LSB _u(0) +#define SPI_SSPRIS_RORRIS_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPMIS +// Description : Masked interrupt status register, SSPMIS on page 3-11 +#define SPI_SSPMIS_OFFSET _u(0x0000001c) +#define SPI_SSPMIS_BITS _u(0x0000000f) +#define SPI_SSPMIS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_TXMIS +// Description : Gives the transmit FIFO masked interrupt state, after masking, +// of the SSPTXINTR interrupt +#define SPI_SSPMIS_TXMIS_RESET _u(0x0) +#define SPI_SSPMIS_TXMIS_BITS _u(0x00000008) +#define SPI_SSPMIS_TXMIS_MSB _u(3) +#define SPI_SSPMIS_TXMIS_LSB _u(3) +#define SPI_SSPMIS_TXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_RXMIS +// Description : Gives the receive FIFO masked interrupt state, after masking, +// of the SSPRXINTR interrupt +#define SPI_SSPMIS_RXMIS_RESET _u(0x0) +#define SPI_SSPMIS_RXMIS_BITS _u(0x00000004) +#define SPI_SSPMIS_RXMIS_MSB _u(2) +#define SPI_SSPMIS_RXMIS_LSB _u(2) +#define SPI_SSPMIS_RXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_RTMIS +// Description : Gives the receive timeout masked interrupt state, after +// masking, of the SSPRTINTR interrupt +#define SPI_SSPMIS_RTMIS_RESET _u(0x0) +#define SPI_SSPMIS_RTMIS_BITS _u(0x00000002) +#define SPI_SSPMIS_RTMIS_MSB _u(1) +#define SPI_SSPMIS_RTMIS_LSB _u(1) +#define SPI_SSPMIS_RTMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPMIS_RORMIS +// Description : Gives the receive over run masked interrupt status, after +// masking, of the SSPRORINTR interrupt +#define SPI_SSPMIS_RORMIS_RESET _u(0x0) +#define SPI_SSPMIS_RORMIS_BITS _u(0x00000001) +#define SPI_SSPMIS_RORMIS_MSB _u(0) +#define SPI_SSPMIS_RORMIS_LSB _u(0) +#define SPI_SSPMIS_RORMIS_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPICR +// Description : Interrupt clear register, SSPICR on page 3-11 +#define SPI_SSPICR_OFFSET _u(0x00000020) +#define SPI_SSPICR_BITS _u(0x00000003) +#define SPI_SSPICR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPICR_RTIC +// Description : Clears the SSPRTINTR interrupt +#define SPI_SSPICR_RTIC_RESET _u(0x0) +#define SPI_SSPICR_RTIC_BITS _u(0x00000002) +#define SPI_SSPICR_RTIC_MSB _u(1) +#define SPI_SSPICR_RTIC_LSB _u(1) +#define SPI_SSPICR_RTIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPICR_RORIC +// Description : Clears the SSPRORINTR interrupt +#define SPI_SSPICR_RORIC_RESET _u(0x0) +#define SPI_SSPICR_RORIC_BITS _u(0x00000001) +#define SPI_SSPICR_RORIC_MSB _u(0) +#define SPI_SSPICR_RORIC_LSB _u(0) +#define SPI_SSPICR_RORIC_ACCESS "WC" +// ============================================================================= +// Register : SPI_SSPDMACR +// Description : DMA control register, SSPDMACR on page 3-12 +#define SPI_SSPDMACR_OFFSET _u(0x00000024) +#define SPI_SSPDMACR_BITS _u(0x00000003) +#define SPI_SSPDMACR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPDMACR_TXDMAE +// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the +// transmit FIFO is enabled. +#define SPI_SSPDMACR_TXDMAE_RESET _u(0x0) +#define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002) +#define SPI_SSPDMACR_TXDMAE_MSB _u(1) +#define SPI_SSPDMACR_TXDMAE_LSB _u(1) +#define SPI_SSPDMACR_TXDMAE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPDMACR_RXDMAE +// Description : Receive DMA Enable. If this bit is set to 1, DMA for the +// receive FIFO is enabled. +#define SPI_SSPDMACR_RXDMAE_RESET _u(0x0) +#define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001) +#define SPI_SSPDMACR_RXDMAE_MSB _u(0) +#define SPI_SSPDMACR_RXDMAE_LSB _u(0) +#define SPI_SSPDMACR_RXDMAE_ACCESS "RW" +// ============================================================================= +// Register : SPI_SSPPERIPHID0 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0) +#define SPI_SSPPERIPHID0_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID0_RESET _u(0x00000022) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID0_PARTNUMBER0 +// Description : These bits read back as 0x22 +#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22) +#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7) +#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0) +#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPERIPHID1 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4) +#define SPI_SSPPERIPHID1_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID1_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID1_DESIGNER0 +// Description : These bits read back as 0x1 +#define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1) +#define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0) +#define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7) +#define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4) +#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID1_PARTNUMBER1 +// Description : These bits read back as 0x0 +#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0) +#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f) +#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3) +#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0) +#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPERIPHID2 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8) +#define SPI_SSPPERIPHID2_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID2_RESET _u(0x00000034) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID2_REVISION +// Description : These bits return the peripheral revision +#define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3) +#define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0) +#define SPI_SSPPERIPHID2_REVISION_MSB _u(7) +#define SPI_SSPPERIPHID2_REVISION_LSB _u(4) +#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID2_DESIGNER1 +// Description : These bits read back as 0x4 +#define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4) +#define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f) +#define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3) +#define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0) +#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPERIPHID3 +// Description : Peripheral identification registers, SSPPeriphID0-3 on page +// 3-13 +#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec) +#define SPI_SSPPERIPHID3_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPERIPHID3_CONFIGURATION +// Description : These bits read back as 0x00 +#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00) +#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff) +#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7) +#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0) +#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID0 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0) +#define SPI_SSPPCELLID0_BITS _u(0x000000ff) +#define SPI_SSPPCELLID0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID0_SSPPCELLID0 +// Description : These bits read back as 0x0D +#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d) +#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff) +#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7) +#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0) +#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID1 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4) +#define SPI_SSPPCELLID1_BITS _u(0x000000ff) +#define SPI_SSPPCELLID1_RESET _u(0x000000f0) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID1_SSPPCELLID1 +// Description : These bits read back as 0xF0 +#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0) +#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff) +#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7) +#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0) +#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID2 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8) +#define SPI_SSPPCELLID2_BITS _u(0x000000ff) +#define SPI_SSPPCELLID2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID2_SSPPCELLID2 +// Description : These bits read back as 0x05 +#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05) +#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff) +#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7) +#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0) +#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO" +// ============================================================================= +// Register : SPI_SSPPCELLID3 +// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16 +#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc) +#define SPI_SSPPCELLID3_BITS _u(0x000000ff) +#define SPI_SSPPCELLID3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : SPI_SSPPCELLID3_SSPPCELLID3 +// Description : These bits read back as 0xB1 +#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1) +#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff) +#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7) +#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0) +#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_SPI_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/syscfg.h b/lib/pico-sdk/rp2350/hardware/regs/syscfg.h new file mode 100644 index 000000000000..455ebf175923 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/syscfg.h @@ -0,0 +1,279 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SYSCFG +// Version : 1 +// Bus type : apb +// Description : Register block for various chip control signals +// ============================================================================= +#ifndef _HARDWARE_REGS_SYSCFG_H +#define _HARDWARE_REGS_SYSCFG_H +// ============================================================================= +// Register : SYSCFG_PROC_CONFIG +// Description : Configuration for processors +#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000000) +#define SYSCFG_PROC_CONFIG_BITS _u(0x00000003) +#define SYSCFG_PROC_CONFIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED +// Description : Indication that proc1 has halted +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0) +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002) +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1) +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1) +#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED +// Description : Indication that proc0 has halted +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0) +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001) +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0) +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0) +#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO" +// ============================================================================= +// Register : SYSCFG_PROC_IN_SYNC_BYPASS +// Description : For each bit, if 1, bypass the input synchronizer between that +// GPIO +// and the GPIO input register in the SIO. The input synchronizers +// should +// generally be unbypassed, to avoid injecting metastabilities +// into processors. +// If you're feeling brave, you can bypass to save two cycles of +// input +// latency. This register applies to GPIO 0...31. +#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x00000004) +#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0xffffffff) +#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_IN_SYNC_BYPASS_GPIO +#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_RESET _u(0x00000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_BITS _u(0xffffffff) +#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_MSB _u(31) +#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_LSB _u(0) +#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_ACCESS "RW" +// ============================================================================= +// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI +// Description : For each bit, if 1, bypass the input synchronizer between that +// GPIO +// and the GPIO input register in the SIO. The input synchronizers +// should +// generally be unbypassed, to avoid injecting metastabilities +// into processors. +// If you're feeling brave, you can bypass to save two cycles of +// input +// latency. This register applies to GPIO 32...47. USB GPIO 56..57 +// QSPI GPIO 58..63 +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000008) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0xff00ffff) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_RESET _u(0x0) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_BITS _u(0xf0000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_MSB _u(31) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_LSB _u(28) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_RESET _u(0x0) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_BITS _u(0x08000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_MSB _u(27) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_LSB _u(27) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_RESET _u(0x0) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_BITS _u(0x04000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_MSB _u(26) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_LSB _u(26) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_RESET _u(0x0) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_BITS _u(0x02000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_MSB _u(25) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_LSB _u(25) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_RESET _u(0x0) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_BITS _u(0x01000000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_MSB _u(24) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_LSB _u(24) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_RESET _u(0x0000) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_BITS _u(0x0000ffff) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_MSB _u(15) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_LSB _u(0) +#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_ACCESS "RW" +// ============================================================================= +// Register : SYSCFG_DBGFORCE +// Description : Directly control the chip SWD debug port +#define SYSCFG_DBGFORCE_OFFSET _u(0x0000000c) +#define SYSCFG_DBGFORCE_BITS _u(0x0000000f) +#define SYSCFG_DBGFORCE_RESET _u(0x00000006) +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_ATTACH +// Description : Attach chip debug port to syscfg controls, and disconnect it +// from external SWD pads. +#define SYSCFG_DBGFORCE_ATTACH_RESET _u(0x0) +#define SYSCFG_DBGFORCE_ATTACH_BITS _u(0x00000008) +#define SYSCFG_DBGFORCE_ATTACH_MSB _u(3) +#define SYSCFG_DBGFORCE_ATTACH_LSB _u(3) +#define SYSCFG_DBGFORCE_ATTACH_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_SWCLK +// Description : Directly drive SWCLK, if ATTACH is set +#define SYSCFG_DBGFORCE_SWCLK_RESET _u(0x1) +#define SYSCFG_DBGFORCE_SWCLK_BITS _u(0x00000004) +#define SYSCFG_DBGFORCE_SWCLK_MSB _u(2) +#define SYSCFG_DBGFORCE_SWCLK_LSB _u(2) +#define SYSCFG_DBGFORCE_SWCLK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_SWDI +// Description : Directly drive SWDIO input, if ATTACH is set +#define SYSCFG_DBGFORCE_SWDI_RESET _u(0x1) +#define SYSCFG_DBGFORCE_SWDI_BITS _u(0x00000002) +#define SYSCFG_DBGFORCE_SWDI_MSB _u(1) +#define SYSCFG_DBGFORCE_SWDI_LSB _u(1) +#define SYSCFG_DBGFORCE_SWDI_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_DBGFORCE_SWDO +// Description : Observe the value of SWDIO output. +#define SYSCFG_DBGFORCE_SWDO_RESET "-" +#define SYSCFG_DBGFORCE_SWDO_BITS _u(0x00000001) +#define SYSCFG_DBGFORCE_SWDO_MSB _u(0) +#define SYSCFG_DBGFORCE_SWDO_LSB _u(0) +#define SYSCFG_DBGFORCE_SWDO_ACCESS "RO" +// ============================================================================= +// Register : SYSCFG_MEMPOWERDOWN +// Description : Control PD pins to memories. +// Set high to put memories to a low power state. In this state +// the memories will retain contents but not be accessible +// Use with caution +#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000010) +#define SYSCFG_MEMPOWERDOWN_BITS _u(0x00001fff) +#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_BOOTRAM +#define SYSCFG_MEMPOWERDOWN_BOOTRAM_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_BOOTRAM_BITS _u(0x00001000) +#define SYSCFG_MEMPOWERDOWN_BOOTRAM_MSB _u(12) +#define SYSCFG_MEMPOWERDOWN_BOOTRAM_LSB _u(12) +#define SYSCFG_MEMPOWERDOWN_BOOTRAM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_ROM +#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000800) +#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(11) +#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(11) +#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_USB +#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000400) +#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(10) +#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(10) +#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM9 +#define SYSCFG_MEMPOWERDOWN_SRAM9_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM9_BITS _u(0x00000200) +#define SYSCFG_MEMPOWERDOWN_SRAM9_MSB _u(9) +#define SYSCFG_MEMPOWERDOWN_SRAM9_LSB _u(9) +#define SYSCFG_MEMPOWERDOWN_SRAM9_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM8 +#define SYSCFG_MEMPOWERDOWN_SRAM8_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM8_BITS _u(0x00000100) +#define SYSCFG_MEMPOWERDOWN_SRAM8_MSB _u(8) +#define SYSCFG_MEMPOWERDOWN_SRAM8_LSB _u(8) +#define SYSCFG_MEMPOWERDOWN_SRAM8_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM7 +#define SYSCFG_MEMPOWERDOWN_SRAM7_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM7_BITS _u(0x00000080) +#define SYSCFG_MEMPOWERDOWN_SRAM7_MSB _u(7) +#define SYSCFG_MEMPOWERDOWN_SRAM7_LSB _u(7) +#define SYSCFG_MEMPOWERDOWN_SRAM7_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM6 +#define SYSCFG_MEMPOWERDOWN_SRAM6_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM6_BITS _u(0x00000040) +#define SYSCFG_MEMPOWERDOWN_SRAM6_MSB _u(6) +#define SYSCFG_MEMPOWERDOWN_SRAM6_LSB _u(6) +#define SYSCFG_MEMPOWERDOWN_SRAM6_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM5 +#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020) +#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5) +#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5) +#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM4 +#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010) +#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4) +#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4) +#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM3 +#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008) +#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3) +#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3) +#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM2 +#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004) +#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2) +#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2) +#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM1 +#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002) +#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1) +#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1) +#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : SYSCFG_MEMPOWERDOWN_SRAM0 +#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0) +#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001) +#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0) +#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0) +#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW" +// ============================================================================= +// Register : SYSCFG_AUXCTRL +// Description : Auxiliary system control register +// * Bits 7:2: Reserved +// +// * Bit 1: When clear, the LPOSC output is XORed into the TRNG +// ROSC output as an additional, uncorrelated entropy source. When +// set, this behaviour is disabled. +// +// * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting +// its WDRESET input. This must be set before initiating a +// watchdog reset of the RSM from a stage that includes CLOCKS, if +// POWMAN is running from clk_ref at the point that the watchdog +// reset takes place. Otherwise, the short pulse generated on +// clk_ref by the reset of the CLOCKS block may affect POWMAN +// register state. +#define SYSCFG_AUXCTRL_OFFSET _u(0x00000014) +#define SYSCFG_AUXCTRL_BITS _u(0x000000ff) +#define SYSCFG_AUXCTRL_RESET _u(0x00000000) +#define SYSCFG_AUXCTRL_MSB _u(7) +#define SYSCFG_AUXCTRL_LSB _u(0) +#define SYSCFG_AUXCTRL_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_SYSCFG_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/sysinfo.h b/lib/pico-sdk/rp2350/hardware/regs/sysinfo.h new file mode 100644 index 000000000000..a6409bc2d230 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/sysinfo.h @@ -0,0 +1,111 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : SYSINFO +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_SYSINFO_H +#define _HARDWARE_REGS_SYSINFO_H +// ============================================================================= +// Register : SYSINFO_CHIP_ID +// Description : JEDEC JEP-106 compliant chip identifier. +#define SYSINFO_CHIP_ID_OFFSET _u(0x00000000) +#define SYSINFO_CHIP_ID_BITS _u(0xffffffff) +#define SYSINFO_CHIP_ID_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : SYSINFO_CHIP_ID_REVISION +#define SYSINFO_CHIP_ID_REVISION_RESET "-" +#define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000) +#define SYSINFO_CHIP_ID_REVISION_MSB _u(31) +#define SYSINFO_CHIP_ID_REVISION_LSB _u(28) +#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_CHIP_ID_PART +#define SYSINFO_CHIP_ID_PART_RESET "-" +#define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000) +#define SYSINFO_CHIP_ID_PART_MSB _u(27) +#define SYSINFO_CHIP_ID_PART_LSB _u(12) +#define SYSINFO_CHIP_ID_PART_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_CHIP_ID_MANUFACTURER +#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-" +#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000ffe) +#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11) +#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(1) +#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_CHIP_ID_STOP_BIT +#define SYSINFO_CHIP_ID_STOP_BIT_RESET _u(0x1) +#define SYSINFO_CHIP_ID_STOP_BIT_BITS _u(0x00000001) +#define SYSINFO_CHIP_ID_STOP_BIT_MSB _u(0) +#define SYSINFO_CHIP_ID_STOP_BIT_LSB _u(0) +#define SYSINFO_CHIP_ID_STOP_BIT_ACCESS "RO" +// ============================================================================= +// Register : SYSINFO_PACKAGE_SEL +#define SYSINFO_PACKAGE_SEL_OFFSET _u(0x00000004) +#define SYSINFO_PACKAGE_SEL_BITS _u(0x00000001) +#define SYSINFO_PACKAGE_SEL_RESET _u(0x00000000) +#define SYSINFO_PACKAGE_SEL_MSB _u(0) +#define SYSINFO_PACKAGE_SEL_LSB _u(0) +#define SYSINFO_PACKAGE_SEL_ACCESS "RO" +// ============================================================================= +// Register : SYSINFO_PLATFORM +// Description : Platform register. Allows software to know what environment it +// is running in during pre-production development. Post- +// production, the PLATFORM is always ASIC, non-SIM. +#define SYSINFO_PLATFORM_OFFSET _u(0x00000008) +#define SYSINFO_PLATFORM_BITS _u(0x0000001f) +#define SYSINFO_PLATFORM_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : SYSINFO_PLATFORM_GATESIM +#define SYSINFO_PLATFORM_GATESIM_RESET "-" +#define SYSINFO_PLATFORM_GATESIM_BITS _u(0x00000010) +#define SYSINFO_PLATFORM_GATESIM_MSB _u(4) +#define SYSINFO_PLATFORM_GATESIM_LSB _u(4) +#define SYSINFO_PLATFORM_GATESIM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_PLATFORM_BATCHSIM +#define SYSINFO_PLATFORM_BATCHSIM_RESET "-" +#define SYSINFO_PLATFORM_BATCHSIM_BITS _u(0x00000008) +#define SYSINFO_PLATFORM_BATCHSIM_MSB _u(3) +#define SYSINFO_PLATFORM_BATCHSIM_LSB _u(3) +#define SYSINFO_PLATFORM_BATCHSIM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_PLATFORM_HDLSIM +#define SYSINFO_PLATFORM_HDLSIM_RESET "-" +#define SYSINFO_PLATFORM_HDLSIM_BITS _u(0x00000004) +#define SYSINFO_PLATFORM_HDLSIM_MSB _u(2) +#define SYSINFO_PLATFORM_HDLSIM_LSB _u(2) +#define SYSINFO_PLATFORM_HDLSIM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_PLATFORM_ASIC +#define SYSINFO_PLATFORM_ASIC_RESET "-" +#define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002) +#define SYSINFO_PLATFORM_ASIC_MSB _u(1) +#define SYSINFO_PLATFORM_ASIC_LSB _u(1) +#define SYSINFO_PLATFORM_ASIC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : SYSINFO_PLATFORM_FPGA +#define SYSINFO_PLATFORM_FPGA_RESET "-" +#define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001) +#define SYSINFO_PLATFORM_FPGA_MSB _u(0) +#define SYSINFO_PLATFORM_FPGA_LSB _u(0) +#define SYSINFO_PLATFORM_FPGA_ACCESS "RO" +// ============================================================================= +// Register : SYSINFO_GITREF_RP2350 +// Description : Git hash of the chip source. Used to identify chip version. +#define SYSINFO_GITREF_RP2350_OFFSET _u(0x00000014) +#define SYSINFO_GITREF_RP2350_BITS _u(0xffffffff) +#define SYSINFO_GITREF_RP2350_RESET "-" +#define SYSINFO_GITREF_RP2350_MSB _u(31) +#define SYSINFO_GITREF_RP2350_LSB _u(0) +#define SYSINFO_GITREF_RP2350_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_SYSINFO_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/tbman.h b/lib/pico-sdk/rp2350/hardware/regs/tbman.h new file mode 100644 index 000000000000..59cf2d1bf129 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/tbman.h @@ -0,0 +1,48 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : TBMAN +// Version : 1 +// Bus type : apb +// Description : For managing simulation testbenches +// ============================================================================= +#ifndef _HARDWARE_REGS_TBMAN_H +#define _HARDWARE_REGS_TBMAN_H +// ============================================================================= +// Register : TBMAN_PLATFORM +// Description : Indicates the type of platform in use +#define TBMAN_PLATFORM_OFFSET _u(0x00000000) +#define TBMAN_PLATFORM_BITS _u(0x00000007) +#define TBMAN_PLATFORM_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : TBMAN_PLATFORM_HDLSIM +// Description : Indicates the platform is a simulation +#define TBMAN_PLATFORM_HDLSIM_RESET _u(0x0) +#define TBMAN_PLATFORM_HDLSIM_BITS _u(0x00000004) +#define TBMAN_PLATFORM_HDLSIM_MSB _u(2) +#define TBMAN_PLATFORM_HDLSIM_LSB _u(2) +#define TBMAN_PLATFORM_HDLSIM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TBMAN_PLATFORM_FPGA +// Description : Indicates the platform is an FPGA +#define TBMAN_PLATFORM_FPGA_RESET _u(0x0) +#define TBMAN_PLATFORM_FPGA_BITS _u(0x00000002) +#define TBMAN_PLATFORM_FPGA_MSB _u(1) +#define TBMAN_PLATFORM_FPGA_LSB _u(1) +#define TBMAN_PLATFORM_FPGA_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TBMAN_PLATFORM_ASIC +// Description : Indicates the platform is an ASIC +#define TBMAN_PLATFORM_ASIC_RESET _u(0x1) +#define TBMAN_PLATFORM_ASIC_BITS _u(0x00000001) +#define TBMAN_PLATFORM_ASIC_MSB _u(0) +#define TBMAN_PLATFORM_ASIC_LSB _u(0) +#define TBMAN_PLATFORM_ASIC_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_TBMAN_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/ticks.h b/lib/pico-sdk/rp2350/hardware/regs/ticks.h new file mode 100644 index 000000000000..79e13523dc7a --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/ticks.h @@ -0,0 +1,275 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : TICKS +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_TICKS_H +#define _HARDWARE_REGS_TICKS_H +// ============================================================================= +// Register : TICKS_PROC0_CTRL +// Description : Controls the tick generator +#define TICKS_PROC0_CTRL_OFFSET _u(0x00000000) +#define TICKS_PROC0_CTRL_BITS _u(0x00000003) +#define TICKS_PROC0_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TICKS_PROC0_CTRL_RUNNING +// Description : Is the tick generator running? +#define TICKS_PROC0_CTRL_RUNNING_RESET "-" +#define TICKS_PROC0_CTRL_RUNNING_BITS _u(0x00000002) +#define TICKS_PROC0_CTRL_RUNNING_MSB _u(1) +#define TICKS_PROC0_CTRL_RUNNING_LSB _u(1) +#define TICKS_PROC0_CTRL_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TICKS_PROC0_CTRL_ENABLE +// Description : start / stop tick generation +#define TICKS_PROC0_CTRL_ENABLE_RESET _u(0x0) +#define TICKS_PROC0_CTRL_ENABLE_BITS _u(0x00000001) +#define TICKS_PROC0_CTRL_ENABLE_MSB _u(0) +#define TICKS_PROC0_CTRL_ENABLE_LSB _u(0) +#define TICKS_PROC0_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : TICKS_PROC0_CYCLES +// Description : None +// Total number of clk_tick cycles before the next tick. +#define TICKS_PROC0_CYCLES_OFFSET _u(0x00000004) +#define TICKS_PROC0_CYCLES_BITS _u(0x000001ff) +#define TICKS_PROC0_CYCLES_RESET _u(0x00000000) +#define TICKS_PROC0_CYCLES_MSB _u(8) +#define TICKS_PROC0_CYCLES_LSB _u(0) +#define TICKS_PROC0_CYCLES_ACCESS "RW" +// ============================================================================= +// Register : TICKS_PROC0_COUNT +// Description : None +// Count down timer: the remaining number clk_tick cycles before +// the next tick is generated. +#define TICKS_PROC0_COUNT_OFFSET _u(0x00000008) +#define TICKS_PROC0_COUNT_BITS _u(0x000001ff) +#define TICKS_PROC0_COUNT_RESET "-" +#define TICKS_PROC0_COUNT_MSB _u(8) +#define TICKS_PROC0_COUNT_LSB _u(0) +#define TICKS_PROC0_COUNT_ACCESS "RO" +// ============================================================================= +// Register : TICKS_PROC1_CTRL +// Description : Controls the tick generator +#define TICKS_PROC1_CTRL_OFFSET _u(0x0000000c) +#define TICKS_PROC1_CTRL_BITS _u(0x00000003) +#define TICKS_PROC1_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TICKS_PROC1_CTRL_RUNNING +// Description : Is the tick generator running? +#define TICKS_PROC1_CTRL_RUNNING_RESET "-" +#define TICKS_PROC1_CTRL_RUNNING_BITS _u(0x00000002) +#define TICKS_PROC1_CTRL_RUNNING_MSB _u(1) +#define TICKS_PROC1_CTRL_RUNNING_LSB _u(1) +#define TICKS_PROC1_CTRL_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TICKS_PROC1_CTRL_ENABLE +// Description : start / stop tick generation +#define TICKS_PROC1_CTRL_ENABLE_RESET _u(0x0) +#define TICKS_PROC1_CTRL_ENABLE_BITS _u(0x00000001) +#define TICKS_PROC1_CTRL_ENABLE_MSB _u(0) +#define TICKS_PROC1_CTRL_ENABLE_LSB _u(0) +#define TICKS_PROC1_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : TICKS_PROC1_CYCLES +// Description : None +// Total number of clk_tick cycles before the next tick. +#define TICKS_PROC1_CYCLES_OFFSET _u(0x00000010) +#define TICKS_PROC1_CYCLES_BITS _u(0x000001ff) +#define TICKS_PROC1_CYCLES_RESET _u(0x00000000) +#define TICKS_PROC1_CYCLES_MSB _u(8) +#define TICKS_PROC1_CYCLES_LSB _u(0) +#define TICKS_PROC1_CYCLES_ACCESS "RW" +// ============================================================================= +// Register : TICKS_PROC1_COUNT +// Description : None +// Count down timer: the remaining number clk_tick cycles before +// the next tick is generated. +#define TICKS_PROC1_COUNT_OFFSET _u(0x00000014) +#define TICKS_PROC1_COUNT_BITS _u(0x000001ff) +#define TICKS_PROC1_COUNT_RESET "-" +#define TICKS_PROC1_COUNT_MSB _u(8) +#define TICKS_PROC1_COUNT_LSB _u(0) +#define TICKS_PROC1_COUNT_ACCESS "RO" +// ============================================================================= +// Register : TICKS_TIMER0_CTRL +// Description : Controls the tick generator +#define TICKS_TIMER0_CTRL_OFFSET _u(0x00000018) +#define TICKS_TIMER0_CTRL_BITS _u(0x00000003) +#define TICKS_TIMER0_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TICKS_TIMER0_CTRL_RUNNING +// Description : Is the tick generator running? +#define TICKS_TIMER0_CTRL_RUNNING_RESET "-" +#define TICKS_TIMER0_CTRL_RUNNING_BITS _u(0x00000002) +#define TICKS_TIMER0_CTRL_RUNNING_MSB _u(1) +#define TICKS_TIMER0_CTRL_RUNNING_LSB _u(1) +#define TICKS_TIMER0_CTRL_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TICKS_TIMER0_CTRL_ENABLE +// Description : start / stop tick generation +#define TICKS_TIMER0_CTRL_ENABLE_RESET _u(0x0) +#define TICKS_TIMER0_CTRL_ENABLE_BITS _u(0x00000001) +#define TICKS_TIMER0_CTRL_ENABLE_MSB _u(0) +#define TICKS_TIMER0_CTRL_ENABLE_LSB _u(0) +#define TICKS_TIMER0_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : TICKS_TIMER0_CYCLES +// Description : None +// Total number of clk_tick cycles before the next tick. +#define TICKS_TIMER0_CYCLES_OFFSET _u(0x0000001c) +#define TICKS_TIMER0_CYCLES_BITS _u(0x000001ff) +#define TICKS_TIMER0_CYCLES_RESET _u(0x00000000) +#define TICKS_TIMER0_CYCLES_MSB _u(8) +#define TICKS_TIMER0_CYCLES_LSB _u(0) +#define TICKS_TIMER0_CYCLES_ACCESS "RW" +// ============================================================================= +// Register : TICKS_TIMER0_COUNT +// Description : None +// Count down timer: the remaining number clk_tick cycles before +// the next tick is generated. +#define TICKS_TIMER0_COUNT_OFFSET _u(0x00000020) +#define TICKS_TIMER0_COUNT_BITS _u(0x000001ff) +#define TICKS_TIMER0_COUNT_RESET "-" +#define TICKS_TIMER0_COUNT_MSB _u(8) +#define TICKS_TIMER0_COUNT_LSB _u(0) +#define TICKS_TIMER0_COUNT_ACCESS "RO" +// ============================================================================= +// Register : TICKS_TIMER1_CTRL +// Description : Controls the tick generator +#define TICKS_TIMER1_CTRL_OFFSET _u(0x00000024) +#define TICKS_TIMER1_CTRL_BITS _u(0x00000003) +#define TICKS_TIMER1_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TICKS_TIMER1_CTRL_RUNNING +// Description : Is the tick generator running? +#define TICKS_TIMER1_CTRL_RUNNING_RESET "-" +#define TICKS_TIMER1_CTRL_RUNNING_BITS _u(0x00000002) +#define TICKS_TIMER1_CTRL_RUNNING_MSB _u(1) +#define TICKS_TIMER1_CTRL_RUNNING_LSB _u(1) +#define TICKS_TIMER1_CTRL_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TICKS_TIMER1_CTRL_ENABLE +// Description : start / stop tick generation +#define TICKS_TIMER1_CTRL_ENABLE_RESET _u(0x0) +#define TICKS_TIMER1_CTRL_ENABLE_BITS _u(0x00000001) +#define TICKS_TIMER1_CTRL_ENABLE_MSB _u(0) +#define TICKS_TIMER1_CTRL_ENABLE_LSB _u(0) +#define TICKS_TIMER1_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : TICKS_TIMER1_CYCLES +// Description : None +// Total number of clk_tick cycles before the next tick. +#define TICKS_TIMER1_CYCLES_OFFSET _u(0x00000028) +#define TICKS_TIMER1_CYCLES_BITS _u(0x000001ff) +#define TICKS_TIMER1_CYCLES_RESET _u(0x00000000) +#define TICKS_TIMER1_CYCLES_MSB _u(8) +#define TICKS_TIMER1_CYCLES_LSB _u(0) +#define TICKS_TIMER1_CYCLES_ACCESS "RW" +// ============================================================================= +// Register : TICKS_TIMER1_COUNT +// Description : None +// Count down timer: the remaining number clk_tick cycles before +// the next tick is generated. +#define TICKS_TIMER1_COUNT_OFFSET _u(0x0000002c) +#define TICKS_TIMER1_COUNT_BITS _u(0x000001ff) +#define TICKS_TIMER1_COUNT_RESET "-" +#define TICKS_TIMER1_COUNT_MSB _u(8) +#define TICKS_TIMER1_COUNT_LSB _u(0) +#define TICKS_TIMER1_COUNT_ACCESS "RO" +// ============================================================================= +// Register : TICKS_WATCHDOG_CTRL +// Description : Controls the tick generator +#define TICKS_WATCHDOG_CTRL_OFFSET _u(0x00000030) +#define TICKS_WATCHDOG_CTRL_BITS _u(0x00000003) +#define TICKS_WATCHDOG_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TICKS_WATCHDOG_CTRL_RUNNING +// Description : Is the tick generator running? +#define TICKS_WATCHDOG_CTRL_RUNNING_RESET "-" +#define TICKS_WATCHDOG_CTRL_RUNNING_BITS _u(0x00000002) +#define TICKS_WATCHDOG_CTRL_RUNNING_MSB _u(1) +#define TICKS_WATCHDOG_CTRL_RUNNING_LSB _u(1) +#define TICKS_WATCHDOG_CTRL_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TICKS_WATCHDOG_CTRL_ENABLE +// Description : start / stop tick generation +#define TICKS_WATCHDOG_CTRL_ENABLE_RESET _u(0x0) +#define TICKS_WATCHDOG_CTRL_ENABLE_BITS _u(0x00000001) +#define TICKS_WATCHDOG_CTRL_ENABLE_MSB _u(0) +#define TICKS_WATCHDOG_CTRL_ENABLE_LSB _u(0) +#define TICKS_WATCHDOG_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : TICKS_WATCHDOG_CYCLES +// Description : None +// Total number of clk_tick cycles before the next tick. +#define TICKS_WATCHDOG_CYCLES_OFFSET _u(0x00000034) +#define TICKS_WATCHDOG_CYCLES_BITS _u(0x000001ff) +#define TICKS_WATCHDOG_CYCLES_RESET _u(0x00000000) +#define TICKS_WATCHDOG_CYCLES_MSB _u(8) +#define TICKS_WATCHDOG_CYCLES_LSB _u(0) +#define TICKS_WATCHDOG_CYCLES_ACCESS "RW" +// ============================================================================= +// Register : TICKS_WATCHDOG_COUNT +// Description : None +// Count down timer: the remaining number clk_tick cycles before +// the next tick is generated. +#define TICKS_WATCHDOG_COUNT_OFFSET _u(0x00000038) +#define TICKS_WATCHDOG_COUNT_BITS _u(0x000001ff) +#define TICKS_WATCHDOG_COUNT_RESET "-" +#define TICKS_WATCHDOG_COUNT_MSB _u(8) +#define TICKS_WATCHDOG_COUNT_LSB _u(0) +#define TICKS_WATCHDOG_COUNT_ACCESS "RO" +// ============================================================================= +// Register : TICKS_RISCV_CTRL +// Description : Controls the tick generator +#define TICKS_RISCV_CTRL_OFFSET _u(0x0000003c) +#define TICKS_RISCV_CTRL_BITS _u(0x00000003) +#define TICKS_RISCV_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TICKS_RISCV_CTRL_RUNNING +// Description : Is the tick generator running? +#define TICKS_RISCV_CTRL_RUNNING_RESET "-" +#define TICKS_RISCV_CTRL_RUNNING_BITS _u(0x00000002) +#define TICKS_RISCV_CTRL_RUNNING_MSB _u(1) +#define TICKS_RISCV_CTRL_RUNNING_LSB _u(1) +#define TICKS_RISCV_CTRL_RUNNING_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TICKS_RISCV_CTRL_ENABLE +// Description : start / stop tick generation +#define TICKS_RISCV_CTRL_ENABLE_RESET _u(0x0) +#define TICKS_RISCV_CTRL_ENABLE_BITS _u(0x00000001) +#define TICKS_RISCV_CTRL_ENABLE_MSB _u(0) +#define TICKS_RISCV_CTRL_ENABLE_LSB _u(0) +#define TICKS_RISCV_CTRL_ENABLE_ACCESS "RW" +// ============================================================================= +// Register : TICKS_RISCV_CYCLES +// Description : None +// Total number of clk_tick cycles before the next tick. +#define TICKS_RISCV_CYCLES_OFFSET _u(0x00000040) +#define TICKS_RISCV_CYCLES_BITS _u(0x000001ff) +#define TICKS_RISCV_CYCLES_RESET _u(0x00000000) +#define TICKS_RISCV_CYCLES_MSB _u(8) +#define TICKS_RISCV_CYCLES_LSB _u(0) +#define TICKS_RISCV_CYCLES_ACCESS "RW" +// ============================================================================= +// Register : TICKS_RISCV_COUNT +// Description : None +// Count down timer: the remaining number clk_tick cycles before +// the next tick is generated. +#define TICKS_RISCV_COUNT_OFFSET _u(0x00000044) +#define TICKS_RISCV_COUNT_BITS _u(0x000001ff) +#define TICKS_RISCV_COUNT_RESET "-" +#define TICKS_RISCV_COUNT_MSB _u(8) +#define TICKS_RISCV_COUNT_LSB _u(0) +#define TICKS_RISCV_COUNT_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_TICKS_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/timer.h b/lib/pico-sdk/rp2350/hardware/regs/timer.h new file mode 100644 index 000000000000..c5f4d05b2c77 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/timer.h @@ -0,0 +1,346 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : TIMER +// Version : 1 +// Bus type : apb +// Description : Controls time and alarms +// +// time is a 64 bit value indicating the time since power-on +// +// timeh is the top 32 bits of time & timel is the bottom 32 +// bits to change time write to timelw before timehw to read +// time read from timelr before timehr +// +// An alarm is set by setting alarm_enable and writing to the +// corresponding alarm register When an alarm is pending, the +// corresponding alarm_running signal will be high An alarm can +// be cancelled before it has finished by clearing the +// alarm_enable When an alarm fires, the corresponding +// alarm_irq is set and alarm_running is cleared To clear the +// interrupt write a 1 to the corresponding alarm_irq The timer +// can be locked to prevent writing +// ============================================================================= +#ifndef _HARDWARE_REGS_TIMER_H +#define _HARDWARE_REGS_TIMER_H +// ============================================================================= +// Register : TIMER_TIMEHW +// Description : Write to bits 63:32 of time always write timelw before timehw +#define TIMER_TIMEHW_OFFSET _u(0x00000000) +#define TIMER_TIMEHW_BITS _u(0xffffffff) +#define TIMER_TIMEHW_RESET _u(0x00000000) +#define TIMER_TIMEHW_MSB _u(31) +#define TIMER_TIMEHW_LSB _u(0) +#define TIMER_TIMEHW_ACCESS "WF" +// ============================================================================= +// Register : TIMER_TIMELW +// Description : Write to bits 31:0 of time writes do not get copied to time +// until timehw is written +#define TIMER_TIMELW_OFFSET _u(0x00000004) +#define TIMER_TIMELW_BITS _u(0xffffffff) +#define TIMER_TIMELW_RESET _u(0x00000000) +#define TIMER_TIMELW_MSB _u(31) +#define TIMER_TIMELW_LSB _u(0) +#define TIMER_TIMELW_ACCESS "WF" +// ============================================================================= +// Register : TIMER_TIMEHR +// Description : Read from bits 63:32 of time always read timelr before timehr +#define TIMER_TIMEHR_OFFSET _u(0x00000008) +#define TIMER_TIMEHR_BITS _u(0xffffffff) +#define TIMER_TIMEHR_RESET _u(0x00000000) +#define TIMER_TIMEHR_MSB _u(31) +#define TIMER_TIMEHR_LSB _u(0) +#define TIMER_TIMEHR_ACCESS "RO" +// ============================================================================= +// Register : TIMER_TIMELR +// Description : Read from bits 31:0 of time +#define TIMER_TIMELR_OFFSET _u(0x0000000c) +#define TIMER_TIMELR_BITS _u(0xffffffff) +#define TIMER_TIMELR_RESET _u(0x00000000) +#define TIMER_TIMELR_MSB _u(31) +#define TIMER_TIMELR_LSB _u(0) +#define TIMER_TIMELR_ACCESS "RO" +// ============================================================================= +// Register : TIMER_ALARM0 +// Description : Arm alarm 0, and configure the time it will fire. Once armed, +// the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will +// disarm itself once it fires, and can be disarmed early using +// the ARMED status register. +#define TIMER_ALARM0_OFFSET _u(0x00000010) +#define TIMER_ALARM0_BITS _u(0xffffffff) +#define TIMER_ALARM0_RESET _u(0x00000000) +#define TIMER_ALARM0_MSB _u(31) +#define TIMER_ALARM0_LSB _u(0) +#define TIMER_ALARM0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ALARM1 +// Description : Arm alarm 1, and configure the time it will fire. Once armed, +// the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will +// disarm itself once it fires, and can be disarmed early using +// the ARMED status register. +#define TIMER_ALARM1_OFFSET _u(0x00000014) +#define TIMER_ALARM1_BITS _u(0xffffffff) +#define TIMER_ALARM1_RESET _u(0x00000000) +#define TIMER_ALARM1_MSB _u(31) +#define TIMER_ALARM1_LSB _u(0) +#define TIMER_ALARM1_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ALARM2 +// Description : Arm alarm 2, and configure the time it will fire. Once armed, +// the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will +// disarm itself once it fires, and can be disarmed early using +// the ARMED status register. +#define TIMER_ALARM2_OFFSET _u(0x00000018) +#define TIMER_ALARM2_BITS _u(0xffffffff) +#define TIMER_ALARM2_RESET _u(0x00000000) +#define TIMER_ALARM2_MSB _u(31) +#define TIMER_ALARM2_LSB _u(0) +#define TIMER_ALARM2_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ALARM3 +// Description : Arm alarm 3, and configure the time it will fire. Once armed, +// the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will +// disarm itself once it fires, and can be disarmed early using +// the ARMED status register. +#define TIMER_ALARM3_OFFSET _u(0x0000001c) +#define TIMER_ALARM3_BITS _u(0xffffffff) +#define TIMER_ALARM3_RESET _u(0x00000000) +#define TIMER_ALARM3_MSB _u(31) +#define TIMER_ALARM3_LSB _u(0) +#define TIMER_ALARM3_ACCESS "RW" +// ============================================================================= +// Register : TIMER_ARMED +// Description : Indicates the armed/disarmed status of each alarm. A write to +// the corresponding ALARMx register arms the alarm. Alarms +// automatically disarm upon firing, but writing ones here will +// disarm immediately without waiting to fire. +#define TIMER_ARMED_OFFSET _u(0x00000020) +#define TIMER_ARMED_BITS _u(0x0000000f) +#define TIMER_ARMED_RESET _u(0x00000000) +#define TIMER_ARMED_MSB _u(3) +#define TIMER_ARMED_LSB _u(0) +#define TIMER_ARMED_ACCESS "WC" +// ============================================================================= +// Register : TIMER_TIMERAWH +// Description : Raw read from bits 63:32 of time (no side effects) +#define TIMER_TIMERAWH_OFFSET _u(0x00000024) +#define TIMER_TIMERAWH_BITS _u(0xffffffff) +#define TIMER_TIMERAWH_RESET _u(0x00000000) +#define TIMER_TIMERAWH_MSB _u(31) +#define TIMER_TIMERAWH_LSB _u(0) +#define TIMER_TIMERAWH_ACCESS "RO" +// ============================================================================= +// Register : TIMER_TIMERAWL +// Description : Raw read from bits 31:0 of time (no side effects) +#define TIMER_TIMERAWL_OFFSET _u(0x00000028) +#define TIMER_TIMERAWL_BITS _u(0xffffffff) +#define TIMER_TIMERAWL_RESET _u(0x00000000) +#define TIMER_TIMERAWL_MSB _u(31) +#define TIMER_TIMERAWL_LSB _u(0) +#define TIMER_TIMERAWL_ACCESS "RO" +// ============================================================================= +// Register : TIMER_DBGPAUSE +// Description : Set bits high to enable pause when the corresponding debug +// ports are active +#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c) +#define TIMER_DBGPAUSE_BITS _u(0x00000006) +#define TIMER_DBGPAUSE_RESET _u(0x00000007) +// ----------------------------------------------------------------------------- +// Field : TIMER_DBGPAUSE_DBG1 +// Description : Pause when processor 1 is in debug mode +#define TIMER_DBGPAUSE_DBG1_RESET _u(0x1) +#define TIMER_DBGPAUSE_DBG1_BITS _u(0x00000004) +#define TIMER_DBGPAUSE_DBG1_MSB _u(2) +#define TIMER_DBGPAUSE_DBG1_LSB _u(2) +#define TIMER_DBGPAUSE_DBG1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_DBGPAUSE_DBG0 +// Description : Pause when processor 0 is in debug mode +#define TIMER_DBGPAUSE_DBG0_RESET _u(0x1) +#define TIMER_DBGPAUSE_DBG0_BITS _u(0x00000002) +#define TIMER_DBGPAUSE_DBG0_MSB _u(1) +#define TIMER_DBGPAUSE_DBG0_LSB _u(1) +#define TIMER_DBGPAUSE_DBG0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_PAUSE +// Description : Set high to pause the timer +#define TIMER_PAUSE_OFFSET _u(0x00000030) +#define TIMER_PAUSE_BITS _u(0x00000001) +#define TIMER_PAUSE_RESET _u(0x00000000) +#define TIMER_PAUSE_MSB _u(0) +#define TIMER_PAUSE_LSB _u(0) +#define TIMER_PAUSE_ACCESS "RW" +// ============================================================================= +// Register : TIMER_LOCKED +// Description : Set locked bit to disable write access to timer Once set, +// cannot be cleared (without a reset) +#define TIMER_LOCKED_OFFSET _u(0x00000034) +#define TIMER_LOCKED_BITS _u(0x00000001) +#define TIMER_LOCKED_RESET _u(0x00000000) +#define TIMER_LOCKED_MSB _u(0) +#define TIMER_LOCKED_LSB _u(0) +#define TIMER_LOCKED_ACCESS "RW" +// ============================================================================= +// Register : TIMER_SOURCE +// Description : Selects the source for the timer. Defaults to the normal tick +// configured in the ticks block (typically configured to 1 +// microsecond). Writing to 1 will ignore the tick and count +// clk_sys cycles instead. +#define TIMER_SOURCE_OFFSET _u(0x00000038) +#define TIMER_SOURCE_BITS _u(0x00000001) +#define TIMER_SOURCE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TIMER_SOURCE_CLK_SYS +// 0x0 -> TICK +// 0x1 -> CLK_SYS +#define TIMER_SOURCE_CLK_SYS_RESET _u(0x0) +#define TIMER_SOURCE_CLK_SYS_BITS _u(0x00000001) +#define TIMER_SOURCE_CLK_SYS_MSB _u(0) +#define TIMER_SOURCE_CLK_SYS_LSB _u(0) +#define TIMER_SOURCE_CLK_SYS_ACCESS "RW" +#define TIMER_SOURCE_CLK_SYS_VALUE_TICK _u(0x0) +#define TIMER_SOURCE_CLK_SYS_VALUE_CLK_SYS _u(0x1) +// ============================================================================= +// Register : TIMER_INTR +// Description : Raw Interrupts +#define TIMER_INTR_OFFSET _u(0x0000003c) +#define TIMER_INTR_BITS _u(0x0000000f) +#define TIMER_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_3 +#define TIMER_INTR_ALARM_3_RESET _u(0x0) +#define TIMER_INTR_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTR_ALARM_3_MSB _u(3) +#define TIMER_INTR_ALARM_3_LSB _u(3) +#define TIMER_INTR_ALARM_3_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_2 +#define TIMER_INTR_ALARM_2_RESET _u(0x0) +#define TIMER_INTR_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTR_ALARM_2_MSB _u(2) +#define TIMER_INTR_ALARM_2_LSB _u(2) +#define TIMER_INTR_ALARM_2_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_1 +#define TIMER_INTR_ALARM_1_RESET _u(0x0) +#define TIMER_INTR_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTR_ALARM_1_MSB _u(1) +#define TIMER_INTR_ALARM_1_LSB _u(1) +#define TIMER_INTR_ALARM_1_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTR_ALARM_0 +#define TIMER_INTR_ALARM_0_RESET _u(0x0) +#define TIMER_INTR_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTR_ALARM_0_MSB _u(0) +#define TIMER_INTR_ALARM_0_LSB _u(0) +#define TIMER_INTR_ALARM_0_ACCESS "WC" +// ============================================================================= +// Register : TIMER_INTE +// Description : Interrupt Enable +#define TIMER_INTE_OFFSET _u(0x00000040) +#define TIMER_INTE_BITS _u(0x0000000f) +#define TIMER_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_3 +#define TIMER_INTE_ALARM_3_RESET _u(0x0) +#define TIMER_INTE_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTE_ALARM_3_MSB _u(3) +#define TIMER_INTE_ALARM_3_LSB _u(3) +#define TIMER_INTE_ALARM_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_2 +#define TIMER_INTE_ALARM_2_RESET _u(0x0) +#define TIMER_INTE_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTE_ALARM_2_MSB _u(2) +#define TIMER_INTE_ALARM_2_LSB _u(2) +#define TIMER_INTE_ALARM_2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_1 +#define TIMER_INTE_ALARM_1_RESET _u(0x0) +#define TIMER_INTE_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTE_ALARM_1_MSB _u(1) +#define TIMER_INTE_ALARM_1_LSB _u(1) +#define TIMER_INTE_ALARM_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTE_ALARM_0 +#define TIMER_INTE_ALARM_0_RESET _u(0x0) +#define TIMER_INTE_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTE_ALARM_0_MSB _u(0) +#define TIMER_INTE_ALARM_0_LSB _u(0) +#define TIMER_INTE_ALARM_0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_INTF +// Description : Interrupt Force +#define TIMER_INTF_OFFSET _u(0x00000044) +#define TIMER_INTF_BITS _u(0x0000000f) +#define TIMER_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_3 +#define TIMER_INTF_ALARM_3_RESET _u(0x0) +#define TIMER_INTF_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTF_ALARM_3_MSB _u(3) +#define TIMER_INTF_ALARM_3_LSB _u(3) +#define TIMER_INTF_ALARM_3_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_2 +#define TIMER_INTF_ALARM_2_RESET _u(0x0) +#define TIMER_INTF_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTF_ALARM_2_MSB _u(2) +#define TIMER_INTF_ALARM_2_LSB _u(2) +#define TIMER_INTF_ALARM_2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_1 +#define TIMER_INTF_ALARM_1_RESET _u(0x0) +#define TIMER_INTF_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTF_ALARM_1_MSB _u(1) +#define TIMER_INTF_ALARM_1_LSB _u(1) +#define TIMER_INTF_ALARM_1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTF_ALARM_0 +#define TIMER_INTF_ALARM_0_RESET _u(0x0) +#define TIMER_INTF_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTF_ALARM_0_MSB _u(0) +#define TIMER_INTF_ALARM_0_LSB _u(0) +#define TIMER_INTF_ALARM_0_ACCESS "RW" +// ============================================================================= +// Register : TIMER_INTS +// Description : Interrupt status after masking & forcing +#define TIMER_INTS_OFFSET _u(0x00000048) +#define TIMER_INTS_BITS _u(0x0000000f) +#define TIMER_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_3 +#define TIMER_INTS_ALARM_3_RESET _u(0x0) +#define TIMER_INTS_ALARM_3_BITS _u(0x00000008) +#define TIMER_INTS_ALARM_3_MSB _u(3) +#define TIMER_INTS_ALARM_3_LSB _u(3) +#define TIMER_INTS_ALARM_3_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_2 +#define TIMER_INTS_ALARM_2_RESET _u(0x0) +#define TIMER_INTS_ALARM_2_BITS _u(0x00000004) +#define TIMER_INTS_ALARM_2_MSB _u(2) +#define TIMER_INTS_ALARM_2_LSB _u(2) +#define TIMER_INTS_ALARM_2_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_1 +#define TIMER_INTS_ALARM_1_RESET _u(0x0) +#define TIMER_INTS_ALARM_1_BITS _u(0x00000002) +#define TIMER_INTS_ALARM_1_MSB _u(1) +#define TIMER_INTS_ALARM_1_LSB _u(1) +#define TIMER_INTS_ALARM_1_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TIMER_INTS_ALARM_0 +#define TIMER_INTS_ALARM_0_RESET _u(0x0) +#define TIMER_INTS_ALARM_0_BITS _u(0x00000001) +#define TIMER_INTS_ALARM_0_MSB _u(0) +#define TIMER_INTS_ALARM_0_LSB _u(0) +#define TIMER_INTS_ALARM_0_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_TIMER_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/trng.h b/lib/pico-sdk/rp2350/hardware/regs/trng.h new file mode 100644 index 000000000000..c84c715b3d2d --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/trng.h @@ -0,0 +1,625 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : TRNG +// Version : 1 +// Bus type : apb +// Description : ARM TrustZone RNG register block +// ============================================================================= +#ifndef _HARDWARE_REGS_TRNG_H +#define _HARDWARE_REGS_TRNG_H +// ============================================================================= +// Register : TRNG_RNG_IMR +// Description : Interrupt masking. +#define TRNG_RNG_IMR_OFFSET _u(0x00000100) +#define TRNG_RNG_IMR_BITS _u(0xffffffff) +#define TRNG_RNG_IMR_RESET _u(0x0000000f) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_IMR_RESERVED +// Description : RESERVED +#define TRNG_RNG_IMR_RESERVED_RESET _u(0x0000000) +#define TRNG_RNG_IMR_RESERVED_BITS _u(0xfffffff0) +#define TRNG_RNG_IMR_RESERVED_MSB _u(31) +#define TRNG_RNG_IMR_RESERVED_LSB _u(4) +#define TRNG_RNG_IMR_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_IMR_VN_ERR_INT_MASK +// Description : 1'b1-mask interrupt, no interrupt will be generated. See +// RNG_ISR for an explanation on this interrupt. +#define TRNG_RNG_IMR_VN_ERR_INT_MASK_RESET _u(0x1) +#define TRNG_RNG_IMR_VN_ERR_INT_MASK_BITS _u(0x00000008) +#define TRNG_RNG_IMR_VN_ERR_INT_MASK_MSB _u(3) +#define TRNG_RNG_IMR_VN_ERR_INT_MASK_LSB _u(3) +#define TRNG_RNG_IMR_VN_ERR_INT_MASK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_IMR_CRNGT_ERR_INT_MASK +// Description : 1'b1-mask interrupt, no interrupt will be generated. See +// RNG_ISR for an explanation on this interrupt. +#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_RESET _u(0x1) +#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_BITS _u(0x00000004) +#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_MSB _u(2) +#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_LSB _u(2) +#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK +// Description : 1'b1-mask interrupt, no interrupt will be generated. See +// RNG_ISR for an explanation on this interrupt. +#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_RESET _u(0x1) +#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_BITS _u(0x00000002) +#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_MSB _u(1) +#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_LSB _u(1) +#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_IMR_EHR_VALID_INT_MASK +// Description : 1'b1-mask interrupt, no interrupt will be generated. See +// RNG_ISR for an explanation on this interrupt. +#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_RESET _u(0x1) +#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_BITS _u(0x00000001) +#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_MSB _u(0) +#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_LSB _u(0) +#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_ACCESS "RW" +// ============================================================================= +// Register : TRNG_RNG_ISR +// Description : RNG status register. If corresponding RNG_IMR bit is unmasked, +// an interrupt will be generated. +#define TRNG_RNG_ISR_OFFSET _u(0x00000104) +#define TRNG_RNG_ISR_BITS _u(0xffffffff) +#define TRNG_RNG_ISR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ISR_RESERVED +// Description : RESERVED +#define TRNG_RNG_ISR_RESERVED_RESET _u(0x0000000) +#define TRNG_RNG_ISR_RESERVED_BITS _u(0xfffffff0) +#define TRNG_RNG_ISR_RESERVED_MSB _u(31) +#define TRNG_RNG_ISR_RESERVED_LSB _u(4) +#define TRNG_RNG_ISR_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ISR_VN_ERR +// Description : 1'b1 indicates Von Neuman error. Error in von Neuman occurs if +// 32 consecutive collected bits are identical, ZERO or ONE. +#define TRNG_RNG_ISR_VN_ERR_RESET _u(0x0) +#define TRNG_RNG_ISR_VN_ERR_BITS _u(0x00000008) +#define TRNG_RNG_ISR_VN_ERR_MSB _u(3) +#define TRNG_RNG_ISR_VN_ERR_LSB _u(3) +#define TRNG_RNG_ISR_VN_ERR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ISR_CRNGT_ERR +// Description : 1'b1 indicates CRNGT in the RNG test failed. Failure occurs +// when two consecutive blocks of 16 collected bits are equal. +#define TRNG_RNG_ISR_CRNGT_ERR_RESET _u(0x0) +#define TRNG_RNG_ISR_CRNGT_ERR_BITS _u(0x00000004) +#define TRNG_RNG_ISR_CRNGT_ERR_MSB _u(2) +#define TRNG_RNG_ISR_CRNGT_ERR_LSB _u(2) +#define TRNG_RNG_ISR_CRNGT_ERR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ISR_AUTOCORR_ERR +// Description : 1'b1 indicates Autocorrelation test failed four times in a row. +// When set, RNG cease from functioning until next reset. +#define TRNG_RNG_ISR_AUTOCORR_ERR_RESET _u(0x0) +#define TRNG_RNG_ISR_AUTOCORR_ERR_BITS _u(0x00000002) +#define TRNG_RNG_ISR_AUTOCORR_ERR_MSB _u(1) +#define TRNG_RNG_ISR_AUTOCORR_ERR_LSB _u(1) +#define TRNG_RNG_ISR_AUTOCORR_ERR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ISR_EHR_VALID +// Description : 1'b1 indicates that 192 bits have been collected in the RNG, +// and are ready to be read. +#define TRNG_RNG_ISR_EHR_VALID_RESET _u(0x0) +#define TRNG_RNG_ISR_EHR_VALID_BITS _u(0x00000001) +#define TRNG_RNG_ISR_EHR_VALID_MSB _u(0) +#define TRNG_RNG_ISR_EHR_VALID_LSB _u(0) +#define TRNG_RNG_ISR_EHR_VALID_ACCESS "RO" +// ============================================================================= +// Register : TRNG_RNG_ICR +// Description : Interrupt/status bit clear Register. +#define TRNG_RNG_ICR_OFFSET _u(0x00000108) +#define TRNG_RNG_ICR_BITS _u(0xffffffff) +#define TRNG_RNG_ICR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ICR_RESERVED +// Description : RESERVED +#define TRNG_RNG_ICR_RESERVED_RESET _u(0x0000000) +#define TRNG_RNG_ICR_RESERVED_BITS _u(0xfffffff0) +#define TRNG_RNG_ICR_RESERVED_MSB _u(31) +#define TRNG_RNG_ICR_RESERVED_LSB _u(4) +#define TRNG_RNG_ICR_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ICR_VN_ERR +// Description : Write 1'b1 - clear corresponding bit in RNG_ISR. +#define TRNG_RNG_ICR_VN_ERR_RESET _u(0x0) +#define TRNG_RNG_ICR_VN_ERR_BITS _u(0x00000008) +#define TRNG_RNG_ICR_VN_ERR_MSB _u(3) +#define TRNG_RNG_ICR_VN_ERR_LSB _u(3) +#define TRNG_RNG_ICR_VN_ERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ICR_CRNGT_ERR +// Description : Write 1'b1 - clear corresponding bit in RNG_ISR. +#define TRNG_RNG_ICR_CRNGT_ERR_RESET _u(0x0) +#define TRNG_RNG_ICR_CRNGT_ERR_BITS _u(0x00000004) +#define TRNG_RNG_ICR_CRNGT_ERR_MSB _u(2) +#define TRNG_RNG_ICR_CRNGT_ERR_LSB _u(2) +#define TRNG_RNG_ICR_CRNGT_ERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ICR_AUTOCORR_ERR +// Description : Cannot be cleared by SW! Only RNG reset clears this bit. +#define TRNG_RNG_ICR_AUTOCORR_ERR_RESET _u(0x0) +#define TRNG_RNG_ICR_AUTOCORR_ERR_BITS _u(0x00000002) +#define TRNG_RNG_ICR_AUTOCORR_ERR_MSB _u(1) +#define TRNG_RNG_ICR_AUTOCORR_ERR_LSB _u(1) +#define TRNG_RNG_ICR_AUTOCORR_ERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_ICR_EHR_VALID +// Description : Write 1'b1 - clear corresponding bit in RNG_ISR. +#define TRNG_RNG_ICR_EHR_VALID_RESET _u(0x0) +#define TRNG_RNG_ICR_EHR_VALID_BITS _u(0x00000001) +#define TRNG_RNG_ICR_EHR_VALID_MSB _u(0) +#define TRNG_RNG_ICR_EHR_VALID_LSB _u(0) +#define TRNG_RNG_ICR_EHR_VALID_ACCESS "RW" +// ============================================================================= +// Register : TRNG_TRNG_CONFIG +// Description : Selecting the inverter-chain length. +#define TRNG_TRNG_CONFIG_OFFSET _u(0x0000010c) +#define TRNG_TRNG_CONFIG_BITS _u(0xffffffff) +#define TRNG_TRNG_CONFIG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_CONFIG_RESERVED +// Description : RESERVED +#define TRNG_TRNG_CONFIG_RESERVED_RESET _u(0x00000000) +#define TRNG_TRNG_CONFIG_RESERVED_BITS _u(0xfffffffc) +#define TRNG_TRNG_CONFIG_RESERVED_MSB _u(31) +#define TRNG_TRNG_CONFIG_RESERVED_LSB _u(2) +#define TRNG_TRNG_CONFIG_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_CONFIG_RND_SRC_SEL +// Description : Selects the number of inverters (out of four possible +// selections) in the ring oscillator (the entropy source). +#define TRNG_TRNG_CONFIG_RND_SRC_SEL_RESET _u(0x0) +#define TRNG_TRNG_CONFIG_RND_SRC_SEL_BITS _u(0x00000003) +#define TRNG_TRNG_CONFIG_RND_SRC_SEL_MSB _u(1) +#define TRNG_TRNG_CONFIG_RND_SRC_SEL_LSB _u(0) +#define TRNG_TRNG_CONFIG_RND_SRC_SEL_ACCESS "RW" +// ============================================================================= +// Register : TRNG_TRNG_VALID +// Description : 192 bit collection indication. +#define TRNG_TRNG_VALID_OFFSET _u(0x00000110) +#define TRNG_TRNG_VALID_BITS _u(0xffffffff) +#define TRNG_TRNG_VALID_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_VALID_RESERVED +// Description : RESERVED +#define TRNG_TRNG_VALID_RESERVED_RESET _u(0x00000000) +#define TRNG_TRNG_VALID_RESERVED_BITS _u(0xfffffffe) +#define TRNG_TRNG_VALID_RESERVED_MSB _u(31) +#define TRNG_TRNG_VALID_RESERVED_LSB _u(1) +#define TRNG_TRNG_VALID_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_VALID_EHR_VALID +// Description : 1'b1 indicates that collection of bits in the RNG is completed, +// and data can be read from EHR_DATA register. +#define TRNG_TRNG_VALID_EHR_VALID_RESET _u(0x0) +#define TRNG_TRNG_VALID_EHR_VALID_BITS _u(0x00000001) +#define TRNG_TRNG_VALID_EHR_VALID_MSB _u(0) +#define TRNG_TRNG_VALID_EHR_VALID_LSB _u(0) +#define TRNG_TRNG_VALID_EHR_VALID_ACCESS "RO" +// ============================================================================= +// Register : TRNG_EHR_DATA0 +// Description : RNG collected bits. +// Bits [31:0] of Entropy Holding Register (EHR) - RNG output +// register +#define TRNG_EHR_DATA0_OFFSET _u(0x00000114) +#define TRNG_EHR_DATA0_BITS _u(0xffffffff) +#define TRNG_EHR_DATA0_RESET _u(0x00000000) +#define TRNG_EHR_DATA0_MSB _u(31) +#define TRNG_EHR_DATA0_LSB _u(0) +#define TRNG_EHR_DATA0_ACCESS "RO" +// ============================================================================= +// Register : TRNG_EHR_DATA1 +// Description : RNG collected bits. +// Bits [63:32] of Entropy Holding Register (EHR) - RNG output +// register +#define TRNG_EHR_DATA1_OFFSET _u(0x00000118) +#define TRNG_EHR_DATA1_BITS _u(0xffffffff) +#define TRNG_EHR_DATA1_RESET _u(0x00000000) +#define TRNG_EHR_DATA1_MSB _u(31) +#define TRNG_EHR_DATA1_LSB _u(0) +#define TRNG_EHR_DATA1_ACCESS "RO" +// ============================================================================= +// Register : TRNG_EHR_DATA2 +// Description : RNG collected bits. +// Bits [95:64] of Entropy Holding Register (EHR) - RNG output +// register +#define TRNG_EHR_DATA2_OFFSET _u(0x0000011c) +#define TRNG_EHR_DATA2_BITS _u(0xffffffff) +#define TRNG_EHR_DATA2_RESET _u(0x00000000) +#define TRNG_EHR_DATA2_MSB _u(31) +#define TRNG_EHR_DATA2_LSB _u(0) +#define TRNG_EHR_DATA2_ACCESS "RO" +// ============================================================================= +// Register : TRNG_EHR_DATA3 +// Description : RNG collected bits. +// Bits [127:96] of Entropy Holding Register (EHR) - RNG output +// register +#define TRNG_EHR_DATA3_OFFSET _u(0x00000120) +#define TRNG_EHR_DATA3_BITS _u(0xffffffff) +#define TRNG_EHR_DATA3_RESET _u(0x00000000) +#define TRNG_EHR_DATA3_MSB _u(31) +#define TRNG_EHR_DATA3_LSB _u(0) +#define TRNG_EHR_DATA3_ACCESS "RO" +// ============================================================================= +// Register : TRNG_EHR_DATA4 +// Description : RNG collected bits. +// Bits [159:128] of Entropy Holding Register (EHR) - RNG output +// register +#define TRNG_EHR_DATA4_OFFSET _u(0x00000124) +#define TRNG_EHR_DATA4_BITS _u(0xffffffff) +#define TRNG_EHR_DATA4_RESET _u(0x00000000) +#define TRNG_EHR_DATA4_MSB _u(31) +#define TRNG_EHR_DATA4_LSB _u(0) +#define TRNG_EHR_DATA4_ACCESS "RO" +// ============================================================================= +// Register : TRNG_EHR_DATA5 +// Description : RNG collected bits. +// Bits [191:160] of Entropy Holding Register (EHR) - RNG output +// register +#define TRNG_EHR_DATA5_OFFSET _u(0x00000128) +#define TRNG_EHR_DATA5_BITS _u(0xffffffff) +#define TRNG_EHR_DATA5_RESET _u(0x00000000) +#define TRNG_EHR_DATA5_MSB _u(31) +#define TRNG_EHR_DATA5_LSB _u(0) +#define TRNG_EHR_DATA5_ACCESS "RO" +// ============================================================================= +// Register : TRNG_RND_SOURCE_ENABLE +// Description : Enable signal for the random source. +#define TRNG_RND_SOURCE_ENABLE_OFFSET _u(0x0000012c) +#define TRNG_RND_SOURCE_ENABLE_BITS _u(0xffffffff) +#define TRNG_RND_SOURCE_ENABLE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RND_SOURCE_ENABLE_RESERVED +// Description : RESERVED +#define TRNG_RND_SOURCE_ENABLE_RESERVED_RESET _u(0x00000000) +#define TRNG_RND_SOURCE_ENABLE_RESERVED_BITS _u(0xfffffffe) +#define TRNG_RND_SOURCE_ENABLE_RESERVED_MSB _u(31) +#define TRNG_RND_SOURCE_ENABLE_RESERVED_LSB _u(1) +#define TRNG_RND_SOURCE_ENABLE_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RND_SOURCE_ENABLE_RND_SRC_EN +// Description : * 1'b1 - entropy source is enabled. *1'b0 - entropy source is +// disabled +#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_RESET _u(0x0) +#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_BITS _u(0x00000001) +#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_MSB _u(0) +#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_LSB _u(0) +#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_ACCESS "RW" +// ============================================================================= +// Register : TRNG_SAMPLE_CNT1 +// Description : Counts clocks between sampling of random bit. +#define TRNG_SAMPLE_CNT1_OFFSET _u(0x00000130) +#define TRNG_SAMPLE_CNT1_BITS _u(0xffffffff) +#define TRNG_SAMPLE_CNT1_RESET _u(0x0000ffff) +// ----------------------------------------------------------------------------- +// Field : TRNG_SAMPLE_CNT1_SAMPLE_CNTR1 +// Description : Sets the number of rng_clk cycles between two consecutive ring +// oscillator samples. Note! If the Von-Neuman is bypassed, the +// minimum value for sample counter must not be less then decimal +// seventeen +#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_RESET _u(0x0000ffff) +#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_BITS _u(0xffffffff) +#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_MSB _u(31) +#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_LSB _u(0) +#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_ACCESS "RW" +// ============================================================================= +// Register : TRNG_AUTOCORR_STATISTIC +// Description : Statistic about Autocorrelation test activations. +#define TRNG_AUTOCORR_STATISTIC_OFFSET _u(0x00000134) +#define TRNG_AUTOCORR_STATISTIC_BITS _u(0xffffffff) +#define TRNG_AUTOCORR_STATISTIC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_AUTOCORR_STATISTIC_RESERVED +// Description : RESERVED +#define TRNG_AUTOCORR_STATISTIC_RESERVED_RESET _u(0x000) +#define TRNG_AUTOCORR_STATISTIC_RESERVED_BITS _u(0xffc00000) +#define TRNG_AUTOCORR_STATISTIC_RESERVED_MSB _u(31) +#define TRNG_AUTOCORR_STATISTIC_RESERVED_LSB _u(22) +#define TRNG_AUTOCORR_STATISTIC_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS +// Description : Count each time an autocorrelation test fails. Any write to the +// register reset the counter. Stop collecting statistic if one of +// the counters reached the limit. +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_RESET _u(0x00) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_BITS _u(0x003fc000) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_MSB _u(21) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_LSB _u(14) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS +// Description : Count each time an autocorrelation test starts. Any write to +// the register reset the counter. Stop collecting statistic if +// one of the counters reached the limit. +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_RESET _u(0x0000) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_BITS _u(0x00003fff) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_MSB _u(13) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_LSB _u(0) +#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_ACCESS "RW" +// ============================================================================= +// Register : TRNG_TRNG_DEBUG_CONTROL +// Description : Debug register. +#define TRNG_TRNG_DEBUG_CONTROL_OFFSET _u(0x00000138) +#define TRNG_TRNG_DEBUG_CONTROL_BITS _u(0x0000000f) +#define TRNG_TRNG_DEBUG_CONTROL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS +// Description : When set, the autocorrelation test in the TRNG module is +// bypassed. +#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_RESET _u(0x0) +#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_BITS _u(0x00000008) +#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_MSB _u(3) +#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_LSB _u(3) +#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS +// Description : When set, the CRNGT test in the RNG is bypassed. +#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_RESET _u(0x0) +#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_BITS _u(0x00000004) +#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_MSB _u(2) +#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_LSB _u(2) +#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS +// Description : When set, the Von-Neuman balancer is bypassed (including the 32 +// consecutive bits test). +#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_RESET _u(0x0) +#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_BITS _u(0x00000002) +#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_MSB _u(1) +#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_LSB _u(1) +#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_DEBUG_CONTROL_RESERVED +// Description : N/A +#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_RESET _u(0x0) +#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_BITS _u(0x00000001) +#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_MSB _u(0) +#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_LSB _u(0) +#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_ACCESS "RO" +// ============================================================================= +// Register : TRNG_TRNG_SW_RESET +// Description : Generate internal SW reset within the RNG block. +#define TRNG_TRNG_SW_RESET_OFFSET _u(0x00000140) +#define TRNG_TRNG_SW_RESET_BITS _u(0xffffffff) +#define TRNG_TRNG_SW_RESET_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_SW_RESET_RESERVED +// Description : RESERVED +#define TRNG_TRNG_SW_RESET_RESERVED_RESET _u(0x00000000) +#define TRNG_TRNG_SW_RESET_RESERVED_BITS _u(0xfffffffe) +#define TRNG_TRNG_SW_RESET_RESERVED_MSB _u(31) +#define TRNG_TRNG_SW_RESET_RESERVED_LSB _u(1) +#define TRNG_TRNG_SW_RESET_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_SW_RESET_TRNG_SW_RESET +// Description : Writing 1'b1 to this register causes an internal RNG reset. +#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_RESET _u(0x0) +#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_BITS _u(0x00000001) +#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_MSB _u(0) +#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_LSB _u(0) +#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_ACCESS "RW" +// ============================================================================= +// Register : TRNG_RNG_DEBUG_EN_INPUT +// Description : Enable the RNG debug mode +#define TRNG_RNG_DEBUG_EN_INPUT_OFFSET _u(0x000001b4) +#define TRNG_RNG_DEBUG_EN_INPUT_BITS _u(0xffffffff) +#define TRNG_RNG_DEBUG_EN_INPUT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_DEBUG_EN_INPUT_RESERVED +// Description : RESERVED +#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_RESET _u(0x00000000) +#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_BITS _u(0xfffffffe) +#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_MSB _u(31) +#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_LSB _u(1) +#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN +// Description : * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled +#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_RESET _u(0x0) +#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_BITS _u(0x00000001) +#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_MSB _u(0) +#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_LSB _u(0) +#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_ACCESS "RW" +// ============================================================================= +// Register : TRNG_TRNG_BUSY +// Description : RNG Busy indication. +#define TRNG_TRNG_BUSY_OFFSET _u(0x000001b8) +#define TRNG_TRNG_BUSY_BITS _u(0xffffffff) +#define TRNG_TRNG_BUSY_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_BUSY_RESERVED +// Description : RESERVED +#define TRNG_TRNG_BUSY_RESERVED_RESET _u(0x00000000) +#define TRNG_TRNG_BUSY_RESERVED_BITS _u(0xfffffffe) +#define TRNG_TRNG_BUSY_RESERVED_MSB _u(31) +#define TRNG_TRNG_BUSY_RESERVED_LSB _u(1) +#define TRNG_TRNG_BUSY_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_TRNG_BUSY_TRNG_BUSY +// Description : Reflects rng_busy status. +#define TRNG_TRNG_BUSY_TRNG_BUSY_RESET _u(0x0) +#define TRNG_TRNG_BUSY_TRNG_BUSY_BITS _u(0x00000001) +#define TRNG_TRNG_BUSY_TRNG_BUSY_MSB _u(0) +#define TRNG_TRNG_BUSY_TRNG_BUSY_LSB _u(0) +#define TRNG_TRNG_BUSY_TRNG_BUSY_ACCESS "RO" +// ============================================================================= +// Register : TRNG_RST_BITS_COUNTER +// Description : Reset the counter of collected bits in the RNG. +#define TRNG_RST_BITS_COUNTER_OFFSET _u(0x000001bc) +#define TRNG_RST_BITS_COUNTER_BITS _u(0xffffffff) +#define TRNG_RST_BITS_COUNTER_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RST_BITS_COUNTER_RESERVED +// Description : RESERVED +#define TRNG_RST_BITS_COUNTER_RESERVED_RESET _u(0x00000000) +#define TRNG_RST_BITS_COUNTER_RESERVED_BITS _u(0xfffffffe) +#define TRNG_RST_BITS_COUNTER_RESERVED_MSB _u(31) +#define TRNG_RST_BITS_COUNTER_RESERVED_LSB _u(1) +#define TRNG_RST_BITS_COUNTER_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER +// Description : Writing any value to this address will reset the bits counter +// and RNG valid registers. RND_SORCE_ENABLE register must be +// unset in order for the reset to take place. +#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_RESET _u(0x0) +#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_BITS _u(0x00000001) +#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_MSB _u(0) +#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_LSB _u(0) +#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_ACCESS "RW" +// ============================================================================= +// Register : TRNG_RNG_VERSION +// Description : Displays the version settings of the TRNG. +#define TRNG_RNG_VERSION_OFFSET _u(0x000001c0) +#define TRNG_RNG_VERSION_BITS _u(0xffffffff) +#define TRNG_RNG_VERSION_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_RESERVED +// Description : RESERVED +#define TRNG_RNG_VERSION_RESERVED_RESET _u(0x000000) +#define TRNG_RNG_VERSION_RESERVED_BITS _u(0xffffff00) +#define TRNG_RNG_VERSION_RESERVED_MSB _u(31) +#define TRNG_RNG_VERSION_RESERVED_LSB _u(8) +#define TRNG_RNG_VERSION_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_RNG_USE_5_SBOXES +// Description : * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES +#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_RESET _u(0x0) +#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_BITS _u(0x00000080) +#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_MSB _u(7) +#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_LSB _u(7) +#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_RESEEDING_EXISTS +// Description : * 1'b1 - Exists. *1'b0 - Does not exist +#define TRNG_RNG_VERSION_RESEEDING_EXISTS_RESET _u(0x0) +#define TRNG_RNG_VERSION_RESEEDING_EXISTS_BITS _u(0x00000040) +#define TRNG_RNG_VERSION_RESEEDING_EXISTS_MSB _u(6) +#define TRNG_RNG_VERSION_RESEEDING_EXISTS_LSB _u(6) +#define TRNG_RNG_VERSION_RESEEDING_EXISTS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_KAT_EXISTS +// Description : * 1'b1 - Exists. *1'b0 - Does not exist +#define TRNG_RNG_VERSION_KAT_EXISTS_RESET _u(0x0) +#define TRNG_RNG_VERSION_KAT_EXISTS_BITS _u(0x00000020) +#define TRNG_RNG_VERSION_KAT_EXISTS_MSB _u(5) +#define TRNG_RNG_VERSION_KAT_EXISTS_LSB _u(5) +#define TRNG_RNG_VERSION_KAT_EXISTS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_PRNG_EXISTS +// Description : * 1'b1 - Exists. *1'b0 - Does not exist +#define TRNG_RNG_VERSION_PRNG_EXISTS_RESET _u(0x0) +#define TRNG_RNG_VERSION_PRNG_EXISTS_BITS _u(0x00000010) +#define TRNG_RNG_VERSION_PRNG_EXISTS_MSB _u(4) +#define TRNG_RNG_VERSION_PRNG_EXISTS_LSB _u(4) +#define TRNG_RNG_VERSION_PRNG_EXISTS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN +// Description : * 1'b1 - Exists. *1'b0 - Does not exist +#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_RESET _u(0x0) +#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_BITS _u(0x00000008) +#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_MSB _u(3) +#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_LSB _u(3) +#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_AUTOCORR_EXISTS +// Description : * 1'b1 - Exists. *1'b0 - Does not exist +#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_RESET _u(0x0) +#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_BITS _u(0x00000004) +#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_MSB _u(2) +#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_LSB _u(2) +#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_CRNGT_EXISTS +// Description : * 1'b1 - Exists. *1'b0 - Does not exist +#define TRNG_RNG_VERSION_CRNGT_EXISTS_RESET _u(0x0) +#define TRNG_RNG_VERSION_CRNGT_EXISTS_BITS _u(0x00000002) +#define TRNG_RNG_VERSION_CRNGT_EXISTS_MSB _u(1) +#define TRNG_RNG_VERSION_CRNGT_EXISTS_LSB _u(1) +#define TRNG_RNG_VERSION_CRNGT_EXISTS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_VERSION_EHR_WIDTH_192 +// Description : * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR +#define TRNG_RNG_VERSION_EHR_WIDTH_192_RESET _u(0x0) +#define TRNG_RNG_VERSION_EHR_WIDTH_192_BITS _u(0x00000001) +#define TRNG_RNG_VERSION_EHR_WIDTH_192_MSB _u(0) +#define TRNG_RNG_VERSION_EHR_WIDTH_192_LSB _u(0) +#define TRNG_RNG_VERSION_EHR_WIDTH_192_ACCESS "RO" +// ============================================================================= +// Register : TRNG_RNG_BIST_CNTR_0 +// Description : Collected BIST results. +#define TRNG_RNG_BIST_CNTR_0_OFFSET _u(0x000001e0) +#define TRNG_RNG_BIST_CNTR_0_BITS _u(0xffffffff) +#define TRNG_RNG_BIST_CNTR_0_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_BIST_CNTR_0_RESERVED +// Description : RESERVED +#define TRNG_RNG_BIST_CNTR_0_RESERVED_RESET _u(0x000) +#define TRNG_RNG_BIST_CNTR_0_RESERVED_BITS _u(0xffc00000) +#define TRNG_RNG_BIST_CNTR_0_RESERVED_MSB _u(31) +#define TRNG_RNG_BIST_CNTR_0_RESERVED_LSB _u(22) +#define TRNG_RNG_BIST_CNTR_0_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL +// Description : Reflects the results of RNG BIST counter. +#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_RESET _u(0x000000) +#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_BITS _u(0x003fffff) +#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_MSB _u(21) +#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_LSB _u(0) +#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_ACCESS "RO" +// ============================================================================= +// Register : TRNG_RNG_BIST_CNTR_1 +// Description : Collected BIST results. +#define TRNG_RNG_BIST_CNTR_1_OFFSET _u(0x000001e4) +#define TRNG_RNG_BIST_CNTR_1_BITS _u(0xffffffff) +#define TRNG_RNG_BIST_CNTR_1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_BIST_CNTR_1_RESERVED +// Description : RESERVED +#define TRNG_RNG_BIST_CNTR_1_RESERVED_RESET _u(0x000) +#define TRNG_RNG_BIST_CNTR_1_RESERVED_BITS _u(0xffc00000) +#define TRNG_RNG_BIST_CNTR_1_RESERVED_MSB _u(31) +#define TRNG_RNG_BIST_CNTR_1_RESERVED_LSB _u(22) +#define TRNG_RNG_BIST_CNTR_1_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL +// Description : Reflects the results of RNG BIST counter. +#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_RESET _u(0x000000) +#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_BITS _u(0x003fffff) +#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_MSB _u(21) +#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_LSB _u(0) +#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_ACCESS "RO" +// ============================================================================= +// Register : TRNG_RNG_BIST_CNTR_2 +// Description : Collected BIST results. +#define TRNG_RNG_BIST_CNTR_2_OFFSET _u(0x000001e8) +#define TRNG_RNG_BIST_CNTR_2_BITS _u(0xffffffff) +#define TRNG_RNG_BIST_CNTR_2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_BIST_CNTR_2_RESERVED +// Description : RESERVED +#define TRNG_RNG_BIST_CNTR_2_RESERVED_RESET _u(0x000) +#define TRNG_RNG_BIST_CNTR_2_RESERVED_BITS _u(0xffc00000) +#define TRNG_RNG_BIST_CNTR_2_RESERVED_MSB _u(31) +#define TRNG_RNG_BIST_CNTR_2_RESERVED_LSB _u(22) +#define TRNG_RNG_BIST_CNTR_2_RESERVED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL +// Description : Reflects the results of RNG BIST counter. +#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_RESET _u(0x000000) +#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_BITS _u(0x003fffff) +#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_MSB _u(21) +#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_LSB _u(0) +#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_TRNG_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/uart.h b/lib/pico-sdk/rp2350/hardware/regs/uart.h new file mode 100644 index 000000000000..0f7f17ec0fcf --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/uart.h @@ -0,0 +1,1150 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : UART +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_UART_H +#define _HARDWARE_REGS_UART_H +// ============================================================================= +// Register : UART_UARTDR +// Description : Data Register, UARTDR +#define UART_UARTDR_OFFSET _u(0x00000000) +#define UART_UARTDR_BITS _u(0x00000fff) +#define UART_UARTDR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_OE +// Description : Overrun error. This bit is set to 1 if data is received and the +// receive FIFO is already full. This is cleared to 0 once there +// is an empty space in the FIFO and a new character can be +// written to it. +#define UART_UARTDR_OE_RESET "-" +#define UART_UARTDR_OE_BITS _u(0x00000800) +#define UART_UARTDR_OE_MSB _u(11) +#define UART_UARTDR_OE_LSB _u(11) +#define UART_UARTDR_OE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_BE +// Description : Break error. This bit is set to 1 if a break condition was +// detected, indicating that the received data input was held LOW +// for longer than a full-word transmission time (defined as +// start, data, parity and stop bits). In FIFO mode, this error is +// associated with the character at the top of the FIFO. When a +// break occurs, only one 0 character is loaded into the FIFO. The +// next character is only enabled after the receive data input +// goes to a 1 (marking state), and the next valid start bit is +// received. +#define UART_UARTDR_BE_RESET "-" +#define UART_UARTDR_BE_BITS _u(0x00000400) +#define UART_UARTDR_BE_MSB _u(10) +#define UART_UARTDR_BE_LSB _u(10) +#define UART_UARTDR_BE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_PE +// Description : Parity error. When set to 1, it indicates that the parity of +// the received data character does not match the parity that the +// EPS and SPS bits in the Line Control Register, UARTLCR_H. In +// FIFO mode, this error is associated with the character at the +// top of the FIFO. +#define UART_UARTDR_PE_RESET "-" +#define UART_UARTDR_PE_BITS _u(0x00000200) +#define UART_UARTDR_PE_MSB _u(9) +#define UART_UARTDR_PE_LSB _u(9) +#define UART_UARTDR_PE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_FE +// Description : Framing error. When set to 1, it indicates that the received +// character did not have a valid stop bit (a valid stop bit is +// 1). In FIFO mode, this error is associated with the character +// at the top of the FIFO. +#define UART_UARTDR_FE_RESET "-" +#define UART_UARTDR_FE_BITS _u(0x00000100) +#define UART_UARTDR_FE_MSB _u(8) +#define UART_UARTDR_FE_LSB _u(8) +#define UART_UARTDR_FE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDR_DATA +// Description : Receive (read) data character. Transmit (write) data character. +#define UART_UARTDR_DATA_RESET "-" +#define UART_UARTDR_DATA_BITS _u(0x000000ff) +#define UART_UARTDR_DATA_MSB _u(7) +#define UART_UARTDR_DATA_LSB _u(0) +#define UART_UARTDR_DATA_ACCESS "RWF" +// ============================================================================= +// Register : UART_UARTRSR +// Description : Receive Status Register/Error Clear Register, UARTRSR/UARTECR +#define UART_UARTRSR_OFFSET _u(0x00000004) +#define UART_UARTRSR_BITS _u(0x0000000f) +#define UART_UARTRSR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_OE +// Description : Overrun error. This bit is set to 1 if data is received and the +// FIFO is already full. This bit is cleared to 0 by a write to +// UARTECR. The FIFO contents remain valid because no more data is +// written when the FIFO is full, only the contents of the shift +// register are overwritten. The CPU must now read the data, to +// empty the FIFO. +#define UART_UARTRSR_OE_RESET _u(0x0) +#define UART_UARTRSR_OE_BITS _u(0x00000008) +#define UART_UARTRSR_OE_MSB _u(3) +#define UART_UARTRSR_OE_LSB _u(3) +#define UART_UARTRSR_OE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_BE +// Description : Break error. This bit is set to 1 if a break condition was +// detected, indicating that the received data input was held LOW +// for longer than a full-word transmission time (defined as +// start, data, parity, and stop bits). This bit is cleared to 0 +// after a write to UARTECR. In FIFO mode, this error is +// associated with the character at the top of the FIFO. When a +// break occurs, only one 0 character is loaded into the FIFO. The +// next character is only enabled after the receive data input +// goes to a 1 (marking state) and the next valid start bit is +// received. +#define UART_UARTRSR_BE_RESET _u(0x0) +#define UART_UARTRSR_BE_BITS _u(0x00000004) +#define UART_UARTRSR_BE_MSB _u(2) +#define UART_UARTRSR_BE_LSB _u(2) +#define UART_UARTRSR_BE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_PE +// Description : Parity error. When set to 1, it indicates that the parity of +// the received data character does not match the parity that the +// EPS and SPS bits in the Line Control Register, UARTLCR_H. This +// bit is cleared to 0 by a write to UARTECR. In FIFO mode, this +// error is associated with the character at the top of the FIFO. +#define UART_UARTRSR_PE_RESET _u(0x0) +#define UART_UARTRSR_PE_BITS _u(0x00000002) +#define UART_UARTRSR_PE_MSB _u(1) +#define UART_UARTRSR_PE_LSB _u(1) +#define UART_UARTRSR_PE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRSR_FE +// Description : Framing error. When set to 1, it indicates that the received +// character did not have a valid stop bit (a valid stop bit is +// 1). This bit is cleared to 0 by a write to UARTECR. In FIFO +// mode, this error is associated with the character at the top of +// the FIFO. +#define UART_UARTRSR_FE_RESET _u(0x0) +#define UART_UARTRSR_FE_BITS _u(0x00000001) +#define UART_UARTRSR_FE_MSB _u(0) +#define UART_UARTRSR_FE_LSB _u(0) +#define UART_UARTRSR_FE_ACCESS "WC" +// ============================================================================= +// Register : UART_UARTFR +// Description : Flag Register, UARTFR +#define UART_UARTFR_OFFSET _u(0x00000018) +#define UART_UARTFR_BITS _u(0x000001ff) +#define UART_UARTFR_RESET _u(0x00000090) +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_RI +// Description : Ring indicator. This bit is the complement of the UART ring +// indicator, nUARTRI, modem status input. That is, the bit is 1 +// when nUARTRI is LOW. +#define UART_UARTFR_RI_RESET "-" +#define UART_UARTFR_RI_BITS _u(0x00000100) +#define UART_UARTFR_RI_MSB _u(8) +#define UART_UARTFR_RI_LSB _u(8) +#define UART_UARTFR_RI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_TXFE +// Description : Transmit FIFO empty. The meaning of this bit depends on the +// state of the FEN bit in the Line Control Register, UARTLCR_H. +// If the FIFO is disabled, this bit is set when the transmit +// holding register is empty. If the FIFO is enabled, the TXFE bit +// is set when the transmit FIFO is empty. This bit does not +// indicate if there is data in the transmit shift register. +#define UART_UARTFR_TXFE_RESET _u(0x1) +#define UART_UARTFR_TXFE_BITS _u(0x00000080) +#define UART_UARTFR_TXFE_MSB _u(7) +#define UART_UARTFR_TXFE_LSB _u(7) +#define UART_UARTFR_TXFE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_RXFF +// Description : Receive FIFO full. The meaning of this bit depends on the state +// of the FEN bit in the UARTLCR_H Register. If the FIFO is +// disabled, this bit is set when the receive holding register is +// full. If the FIFO is enabled, the RXFF bit is set when the +// receive FIFO is full. +#define UART_UARTFR_RXFF_RESET _u(0x0) +#define UART_UARTFR_RXFF_BITS _u(0x00000040) +#define UART_UARTFR_RXFF_MSB _u(6) +#define UART_UARTFR_RXFF_LSB _u(6) +#define UART_UARTFR_RXFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_TXFF +// Description : Transmit FIFO full. The meaning of this bit depends on the +// state of the FEN bit in the UARTLCR_H Register. If the FIFO is +// disabled, this bit is set when the transmit holding register is +// full. If the FIFO is enabled, the TXFF bit is set when the +// transmit FIFO is full. +#define UART_UARTFR_TXFF_RESET _u(0x0) +#define UART_UARTFR_TXFF_BITS _u(0x00000020) +#define UART_UARTFR_TXFF_MSB _u(5) +#define UART_UARTFR_TXFF_LSB _u(5) +#define UART_UARTFR_TXFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_RXFE +// Description : Receive FIFO empty. The meaning of this bit depends on the +// state of the FEN bit in the UARTLCR_H Register. If the FIFO is +// disabled, this bit is set when the receive holding register is +// empty. If the FIFO is enabled, the RXFE bit is set when the +// receive FIFO is empty. +#define UART_UARTFR_RXFE_RESET _u(0x1) +#define UART_UARTFR_RXFE_BITS _u(0x00000010) +#define UART_UARTFR_RXFE_MSB _u(4) +#define UART_UARTFR_RXFE_LSB _u(4) +#define UART_UARTFR_RXFE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_BUSY +// Description : UART busy. If this bit is set to 1, the UART is busy +// transmitting data. This bit remains set until the complete +// byte, including all the stop bits, has been sent from the shift +// register. This bit is set as soon as the transmit FIFO becomes +// non-empty, regardless of whether the UART is enabled or not. +#define UART_UARTFR_BUSY_RESET _u(0x0) +#define UART_UARTFR_BUSY_BITS _u(0x00000008) +#define UART_UARTFR_BUSY_MSB _u(3) +#define UART_UARTFR_BUSY_LSB _u(3) +#define UART_UARTFR_BUSY_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_DCD +// Description : Data carrier detect. This bit is the complement of the UART +// data carrier detect, nUARTDCD, modem status input. That is, the +// bit is 1 when nUARTDCD is LOW. +#define UART_UARTFR_DCD_RESET "-" +#define UART_UARTFR_DCD_BITS _u(0x00000004) +#define UART_UARTFR_DCD_MSB _u(2) +#define UART_UARTFR_DCD_LSB _u(2) +#define UART_UARTFR_DCD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_DSR +// Description : Data set ready. This bit is the complement of the UART data set +// ready, nUARTDSR, modem status input. That is, the bit is 1 when +// nUARTDSR is LOW. +#define UART_UARTFR_DSR_RESET "-" +#define UART_UARTFR_DSR_BITS _u(0x00000002) +#define UART_UARTFR_DSR_MSB _u(1) +#define UART_UARTFR_DSR_LSB _u(1) +#define UART_UARTFR_DSR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTFR_CTS +// Description : Clear to send. This bit is the complement of the UART clear to +// send, nUARTCTS, modem status input. That is, the bit is 1 when +// nUARTCTS is LOW. +#define UART_UARTFR_CTS_RESET "-" +#define UART_UARTFR_CTS_BITS _u(0x00000001) +#define UART_UARTFR_CTS_MSB _u(0) +#define UART_UARTFR_CTS_LSB _u(0) +#define UART_UARTFR_CTS_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTILPR +// Description : IrDA Low-Power Counter Register, UARTILPR +#define UART_UARTILPR_OFFSET _u(0x00000020) +#define UART_UARTILPR_BITS _u(0x000000ff) +#define UART_UARTILPR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTILPR_ILPDVSR +// Description : 8-bit low-power divisor value. These bits are cleared to 0 at +// reset. +#define UART_UARTILPR_ILPDVSR_RESET _u(0x00) +#define UART_UARTILPR_ILPDVSR_BITS _u(0x000000ff) +#define UART_UARTILPR_ILPDVSR_MSB _u(7) +#define UART_UARTILPR_ILPDVSR_LSB _u(0) +#define UART_UARTILPR_ILPDVSR_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTIBRD +// Description : Integer Baud Rate Register, UARTIBRD +#define UART_UARTIBRD_OFFSET _u(0x00000024) +#define UART_UARTIBRD_BITS _u(0x0000ffff) +#define UART_UARTIBRD_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTIBRD_BAUD_DIVINT +// Description : The integer baud rate divisor. These bits are cleared to 0 on +// reset. +#define UART_UARTIBRD_BAUD_DIVINT_RESET _u(0x0000) +#define UART_UARTIBRD_BAUD_DIVINT_BITS _u(0x0000ffff) +#define UART_UARTIBRD_BAUD_DIVINT_MSB _u(15) +#define UART_UARTIBRD_BAUD_DIVINT_LSB _u(0) +#define UART_UARTIBRD_BAUD_DIVINT_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTFBRD +// Description : Fractional Baud Rate Register, UARTFBRD +#define UART_UARTFBRD_OFFSET _u(0x00000028) +#define UART_UARTFBRD_BITS _u(0x0000003f) +#define UART_UARTFBRD_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTFBRD_BAUD_DIVFRAC +// Description : The fractional baud rate divisor. These bits are cleared to 0 +// on reset. +#define UART_UARTFBRD_BAUD_DIVFRAC_RESET _u(0x00) +#define UART_UARTFBRD_BAUD_DIVFRAC_BITS _u(0x0000003f) +#define UART_UARTFBRD_BAUD_DIVFRAC_MSB _u(5) +#define UART_UARTFBRD_BAUD_DIVFRAC_LSB _u(0) +#define UART_UARTFBRD_BAUD_DIVFRAC_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTLCR_H +// Description : Line Control Register, UARTLCR_H +#define UART_UARTLCR_H_OFFSET _u(0x0000002c) +#define UART_UARTLCR_H_BITS _u(0x000000ff) +#define UART_UARTLCR_H_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_SPS +// Description : Stick parity select. 0 = stick parity is disabled 1 = either: * +// if the EPS bit is 0 then the parity bit is transmitted and +// checked as a 1 * if the EPS bit is 1 then the parity bit is +// transmitted and checked as a 0. This bit has no effect when the +// PEN bit disables parity checking and generation. +#define UART_UARTLCR_H_SPS_RESET _u(0x0) +#define UART_UARTLCR_H_SPS_BITS _u(0x00000080) +#define UART_UARTLCR_H_SPS_MSB _u(7) +#define UART_UARTLCR_H_SPS_LSB _u(7) +#define UART_UARTLCR_H_SPS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_WLEN +// Description : Word length. These bits indicate the number of data bits +// transmitted or received in a frame as follows: b11 = 8 bits b10 +// = 7 bits b01 = 6 bits b00 = 5 bits. +#define UART_UARTLCR_H_WLEN_RESET _u(0x0) +#define UART_UARTLCR_H_WLEN_BITS _u(0x00000060) +#define UART_UARTLCR_H_WLEN_MSB _u(6) +#define UART_UARTLCR_H_WLEN_LSB _u(5) +#define UART_UARTLCR_H_WLEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_FEN +// Description : Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, +// the FIFOs become 1-byte-deep holding registers 1 = transmit and +// receive FIFO buffers are enabled (FIFO mode). +#define UART_UARTLCR_H_FEN_RESET _u(0x0) +#define UART_UARTLCR_H_FEN_BITS _u(0x00000010) +#define UART_UARTLCR_H_FEN_MSB _u(4) +#define UART_UARTLCR_H_FEN_LSB _u(4) +#define UART_UARTLCR_H_FEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_STP2 +// Description : Two stop bits select. If this bit is set to 1, two stop bits +// are transmitted at the end of the frame. The receive logic does +// not check for two stop bits being received. +#define UART_UARTLCR_H_STP2_RESET _u(0x0) +#define UART_UARTLCR_H_STP2_BITS _u(0x00000008) +#define UART_UARTLCR_H_STP2_MSB _u(3) +#define UART_UARTLCR_H_STP2_LSB _u(3) +#define UART_UARTLCR_H_STP2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_EPS +// Description : Even parity select. Controls the type of parity the UART uses +// during transmission and reception: 0 = odd parity. The UART +// generates or checks for an odd number of 1s in the data and +// parity bits. 1 = even parity. The UART generates or checks for +// an even number of 1s in the data and parity bits. This bit has +// no effect when the PEN bit disables parity checking and +// generation. +#define UART_UARTLCR_H_EPS_RESET _u(0x0) +#define UART_UARTLCR_H_EPS_BITS _u(0x00000004) +#define UART_UARTLCR_H_EPS_MSB _u(2) +#define UART_UARTLCR_H_EPS_LSB _u(2) +#define UART_UARTLCR_H_EPS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_PEN +// Description : Parity enable: 0 = parity is disabled and no parity bit added +// to the data frame 1 = parity checking and generation is +// enabled. +#define UART_UARTLCR_H_PEN_RESET _u(0x0) +#define UART_UARTLCR_H_PEN_BITS _u(0x00000002) +#define UART_UARTLCR_H_PEN_MSB _u(1) +#define UART_UARTLCR_H_PEN_LSB _u(1) +#define UART_UARTLCR_H_PEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTLCR_H_BRK +// Description : Send break. If this bit is set to 1, a low-level is continually +// output on the UARTTXD output, after completing transmission of +// the current character. For the proper execution of the break +// command, the software must set this bit for at least two +// complete frames. For normal use, this bit must be cleared to 0. +#define UART_UARTLCR_H_BRK_RESET _u(0x0) +#define UART_UARTLCR_H_BRK_BITS _u(0x00000001) +#define UART_UARTLCR_H_BRK_MSB _u(0) +#define UART_UARTLCR_H_BRK_LSB _u(0) +#define UART_UARTLCR_H_BRK_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTCR +// Description : Control Register, UARTCR +#define UART_UARTCR_OFFSET _u(0x00000030) +#define UART_UARTCR_BITS _u(0x0000ff87) +#define UART_UARTCR_RESET _u(0x00000300) +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_CTSEN +// Description : CTS hardware flow control enable. If this bit is set to 1, CTS +// hardware flow control is enabled. Data is only transmitted when +// the nUARTCTS signal is asserted. +#define UART_UARTCR_CTSEN_RESET _u(0x0) +#define UART_UARTCR_CTSEN_BITS _u(0x00008000) +#define UART_UARTCR_CTSEN_MSB _u(15) +#define UART_UARTCR_CTSEN_LSB _u(15) +#define UART_UARTCR_CTSEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_RTSEN +// Description : RTS hardware flow control enable. If this bit is set to 1, RTS +// hardware flow control is enabled. Data is only requested when +// there is space in the receive FIFO for it to be received. +#define UART_UARTCR_RTSEN_RESET _u(0x0) +#define UART_UARTCR_RTSEN_BITS _u(0x00004000) +#define UART_UARTCR_RTSEN_MSB _u(14) +#define UART_UARTCR_RTSEN_LSB _u(14) +#define UART_UARTCR_RTSEN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_OUT2 +// Description : This bit is the complement of the UART Out2 (nUARTOut2) modem +// status output. That is, when the bit is programmed to a 1, the +// output is 0. For DTE this can be used as Ring Indicator (RI). +#define UART_UARTCR_OUT2_RESET _u(0x0) +#define UART_UARTCR_OUT2_BITS _u(0x00002000) +#define UART_UARTCR_OUT2_MSB _u(13) +#define UART_UARTCR_OUT2_LSB _u(13) +#define UART_UARTCR_OUT2_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_OUT1 +// Description : This bit is the complement of the UART Out1 (nUARTOut1) modem +// status output. That is, when the bit is programmed to a 1 the +// output is 0. For DTE this can be used as Data Carrier Detect +// (DCD). +#define UART_UARTCR_OUT1_RESET _u(0x0) +#define UART_UARTCR_OUT1_BITS _u(0x00001000) +#define UART_UARTCR_OUT1_MSB _u(12) +#define UART_UARTCR_OUT1_LSB _u(12) +#define UART_UARTCR_OUT1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_RTS +// Description : Request to send. This bit is the complement of the UART request +// to send, nUARTRTS, modem status output. That is, when the bit +// is programmed to a 1 then nUARTRTS is LOW. +#define UART_UARTCR_RTS_RESET _u(0x0) +#define UART_UARTCR_RTS_BITS _u(0x00000800) +#define UART_UARTCR_RTS_MSB _u(11) +#define UART_UARTCR_RTS_LSB _u(11) +#define UART_UARTCR_RTS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_DTR +// Description : Data transmit ready. This bit is the complement of the UART +// data transmit ready, nUARTDTR, modem status output. That is, +// when the bit is programmed to a 1 then nUARTDTR is LOW. +#define UART_UARTCR_DTR_RESET _u(0x0) +#define UART_UARTCR_DTR_BITS _u(0x00000400) +#define UART_UARTCR_DTR_MSB _u(10) +#define UART_UARTCR_DTR_LSB _u(10) +#define UART_UARTCR_DTR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_RXE +// Description : Receive enable. If this bit is set to 1, the receive section of +// the UART is enabled. Data reception occurs for either UART +// signals or SIR signals depending on the setting of the SIREN +// bit. When the UART is disabled in the middle of reception, it +// completes the current character before stopping. +#define UART_UARTCR_RXE_RESET _u(0x1) +#define UART_UARTCR_RXE_BITS _u(0x00000200) +#define UART_UARTCR_RXE_MSB _u(9) +#define UART_UARTCR_RXE_LSB _u(9) +#define UART_UARTCR_RXE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_TXE +// Description : Transmit enable. If this bit is set to 1, the transmit section +// of the UART is enabled. Data transmission occurs for either +// UART signals, or SIR signals depending on the setting of the +// SIREN bit. When the UART is disabled in the middle of +// transmission, it completes the current character before +// stopping. +#define UART_UARTCR_TXE_RESET _u(0x1) +#define UART_UARTCR_TXE_BITS _u(0x00000100) +#define UART_UARTCR_TXE_MSB _u(8) +#define UART_UARTCR_TXE_LSB _u(8) +#define UART_UARTCR_TXE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_LBE +// Description : Loopback enable. If this bit is set to 1 and the SIREN bit is +// set to 1 and the SIRTEST bit in the Test Control Register, +// UARTTCR is set to 1, then the nSIROUT path is inverted, and fed +// through to the SIRIN path. The SIRTEST bit in the test register +// must be set to 1 to override the normal half-duplex SIR +// operation. This must be the requirement for accessing the test +// registers during normal operation, and SIRTEST must be cleared +// to 0 when loopback testing is finished. This feature reduces +// the amount of external coupling required during system test. If +// this bit is set to 1, and the SIRTEST bit is set to 0, the +// UARTTXD path is fed through to the UARTRXD path. In either SIR +// mode or UART mode, when this bit is set, the modem outputs are +// also fed through to the modem inputs. This bit is cleared to 0 +// on reset, to disable loopback. +#define UART_UARTCR_LBE_RESET _u(0x0) +#define UART_UARTCR_LBE_BITS _u(0x00000080) +#define UART_UARTCR_LBE_MSB _u(7) +#define UART_UARTCR_LBE_LSB _u(7) +#define UART_UARTCR_LBE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_SIRLP +// Description : SIR low-power IrDA mode. This bit selects the IrDA encoding +// mode. If this bit is cleared to 0, low-level bits are +// transmitted as an active high pulse with a width of 3 / 16th of +// the bit period. If this bit is set to 1, low-level bits are +// transmitted with a pulse width that is 3 times the period of +// the IrLPBaud16 input signal, regardless of the selected bit +// rate. Setting this bit uses less power, but might reduce +// transmission distances. +#define UART_UARTCR_SIRLP_RESET _u(0x0) +#define UART_UARTCR_SIRLP_BITS _u(0x00000004) +#define UART_UARTCR_SIRLP_MSB _u(2) +#define UART_UARTCR_SIRLP_LSB _u(2) +#define UART_UARTCR_SIRLP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_SIREN +// Description : SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW +// (no light pulse generated), and signal transitions on SIRIN +// have no effect. 1 = IrDA SIR ENDEC is enabled. Data is +// transmitted and received on nSIROUT and SIRIN. UARTTXD remains +// HIGH, in the marking state. Signal transitions on UARTRXD or +// modem status inputs have no effect. This bit has no effect if +// the UARTEN bit disables the UART. +#define UART_UARTCR_SIREN_RESET _u(0x0) +#define UART_UARTCR_SIREN_BITS _u(0x00000002) +#define UART_UARTCR_SIREN_MSB _u(1) +#define UART_UARTCR_SIREN_LSB _u(1) +#define UART_UARTCR_SIREN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTCR_UARTEN +// Description : UART enable: 0 = UART is disabled. If the UART is disabled in +// the middle of transmission or reception, it completes the +// current character before stopping. 1 = the UART is enabled. +// Data transmission and reception occurs for either UART signals +// or SIR signals depending on the setting of the SIREN bit. +#define UART_UARTCR_UARTEN_RESET _u(0x0) +#define UART_UARTCR_UARTEN_BITS _u(0x00000001) +#define UART_UARTCR_UARTEN_MSB _u(0) +#define UART_UARTCR_UARTEN_LSB _u(0) +#define UART_UARTCR_UARTEN_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTIFLS +// Description : Interrupt FIFO Level Select Register, UARTIFLS +#define UART_UARTIFLS_OFFSET _u(0x00000034) +#define UART_UARTIFLS_BITS _u(0x0000003f) +#define UART_UARTIFLS_RESET _u(0x00000012) +// ----------------------------------------------------------------------------- +// Field : UART_UARTIFLS_RXIFLSEL +// Description : Receive interrupt FIFO level select. The trigger points for the +// receive interrupt are as follows: b000 = Receive FIFO becomes +// >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = +// Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes +// >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full +// b101-b111 = reserved. +#define UART_UARTIFLS_RXIFLSEL_RESET _u(0x2) +#define UART_UARTIFLS_RXIFLSEL_BITS _u(0x00000038) +#define UART_UARTIFLS_RXIFLSEL_MSB _u(5) +#define UART_UARTIFLS_RXIFLSEL_LSB _u(3) +#define UART_UARTIFLS_RXIFLSEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIFLS_TXIFLSEL +// Description : Transmit interrupt FIFO level select. The trigger points for +// the transmit interrupt are as follows: b000 = Transmit FIFO +// becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 +// full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit +// FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / +// 8 full b101-b111 = reserved. +#define UART_UARTIFLS_TXIFLSEL_RESET _u(0x2) +#define UART_UARTIFLS_TXIFLSEL_BITS _u(0x00000007) +#define UART_UARTIFLS_TXIFLSEL_MSB _u(2) +#define UART_UARTIFLS_TXIFLSEL_LSB _u(0) +#define UART_UARTIFLS_TXIFLSEL_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTIMSC +// Description : Interrupt Mask Set/Clear Register, UARTIMSC +#define UART_UARTIMSC_OFFSET _u(0x00000038) +#define UART_UARTIMSC_BITS _u(0x000007ff) +#define UART_UARTIMSC_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_OEIM +// Description : Overrun error interrupt mask. A read returns the current mask +// for the UARTOEINTR interrupt. On a write of 1, the mask of the +// UARTOEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_OEIM_RESET _u(0x0) +#define UART_UARTIMSC_OEIM_BITS _u(0x00000400) +#define UART_UARTIMSC_OEIM_MSB _u(10) +#define UART_UARTIMSC_OEIM_LSB _u(10) +#define UART_UARTIMSC_OEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_BEIM +// Description : Break error interrupt mask. A read returns the current mask for +// the UARTBEINTR interrupt. On a write of 1, the mask of the +// UARTBEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_BEIM_RESET _u(0x0) +#define UART_UARTIMSC_BEIM_BITS _u(0x00000200) +#define UART_UARTIMSC_BEIM_MSB _u(9) +#define UART_UARTIMSC_BEIM_LSB _u(9) +#define UART_UARTIMSC_BEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_PEIM +// Description : Parity error interrupt mask. A read returns the current mask +// for the UARTPEINTR interrupt. On a write of 1, the mask of the +// UARTPEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_PEIM_RESET _u(0x0) +#define UART_UARTIMSC_PEIM_BITS _u(0x00000100) +#define UART_UARTIMSC_PEIM_MSB _u(8) +#define UART_UARTIMSC_PEIM_LSB _u(8) +#define UART_UARTIMSC_PEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_FEIM +// Description : Framing error interrupt mask. A read returns the current mask +// for the UARTFEINTR interrupt. On a write of 1, the mask of the +// UARTFEINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_FEIM_RESET _u(0x0) +#define UART_UARTIMSC_FEIM_BITS _u(0x00000080) +#define UART_UARTIMSC_FEIM_MSB _u(7) +#define UART_UARTIMSC_FEIM_LSB _u(7) +#define UART_UARTIMSC_FEIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_RTIM +// Description : Receive timeout interrupt mask. A read returns the current mask +// for the UARTRTINTR interrupt. On a write of 1, the mask of the +// UARTRTINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_RTIM_RESET _u(0x0) +#define UART_UARTIMSC_RTIM_BITS _u(0x00000040) +#define UART_UARTIMSC_RTIM_MSB _u(6) +#define UART_UARTIMSC_RTIM_LSB _u(6) +#define UART_UARTIMSC_RTIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_TXIM +// Description : Transmit interrupt mask. A read returns the current mask for +// the UARTTXINTR interrupt. On a write of 1, the mask of the +// UARTTXINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_TXIM_RESET _u(0x0) +#define UART_UARTIMSC_TXIM_BITS _u(0x00000020) +#define UART_UARTIMSC_TXIM_MSB _u(5) +#define UART_UARTIMSC_TXIM_LSB _u(5) +#define UART_UARTIMSC_TXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_RXIM +// Description : Receive interrupt mask. A read returns the current mask for the +// UARTRXINTR interrupt. On a write of 1, the mask of the +// UARTRXINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_RXIM_RESET _u(0x0) +#define UART_UARTIMSC_RXIM_BITS _u(0x00000010) +#define UART_UARTIMSC_RXIM_MSB _u(4) +#define UART_UARTIMSC_RXIM_LSB _u(4) +#define UART_UARTIMSC_RXIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_DSRMIM +// Description : nUARTDSR modem interrupt mask. A read returns the current mask +// for the UARTDSRINTR interrupt. On a write of 1, the mask of the +// UARTDSRINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_DSRMIM_RESET _u(0x0) +#define UART_UARTIMSC_DSRMIM_BITS _u(0x00000008) +#define UART_UARTIMSC_DSRMIM_MSB _u(3) +#define UART_UARTIMSC_DSRMIM_LSB _u(3) +#define UART_UARTIMSC_DSRMIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_DCDMIM +// Description : nUARTDCD modem interrupt mask. A read returns the current mask +// for the UARTDCDINTR interrupt. On a write of 1, the mask of the +// UARTDCDINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_DCDMIM_RESET _u(0x0) +#define UART_UARTIMSC_DCDMIM_BITS _u(0x00000004) +#define UART_UARTIMSC_DCDMIM_MSB _u(2) +#define UART_UARTIMSC_DCDMIM_LSB _u(2) +#define UART_UARTIMSC_DCDMIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_CTSMIM +// Description : nUARTCTS modem interrupt mask. A read returns the current mask +// for the UARTCTSINTR interrupt. On a write of 1, the mask of the +// UARTCTSINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_CTSMIM_RESET _u(0x0) +#define UART_UARTIMSC_CTSMIM_BITS _u(0x00000002) +#define UART_UARTIMSC_CTSMIM_MSB _u(1) +#define UART_UARTIMSC_CTSMIM_LSB _u(1) +#define UART_UARTIMSC_CTSMIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTIMSC_RIMIM +// Description : nUARTRI modem interrupt mask. A read returns the current mask +// for the UARTRIINTR interrupt. On a write of 1, the mask of the +// UARTRIINTR interrupt is set. A write of 0 clears the mask. +#define UART_UARTIMSC_RIMIM_RESET _u(0x0) +#define UART_UARTIMSC_RIMIM_BITS _u(0x00000001) +#define UART_UARTIMSC_RIMIM_MSB _u(0) +#define UART_UARTIMSC_RIMIM_LSB _u(0) +#define UART_UARTIMSC_RIMIM_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTRIS +// Description : Raw Interrupt Status Register, UARTRIS +#define UART_UARTRIS_OFFSET _u(0x0000003c) +#define UART_UARTRIS_BITS _u(0x000007ff) +#define UART_UARTRIS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_OERIS +// Description : Overrun error interrupt status. Returns the raw interrupt state +// of the UARTOEINTR interrupt. +#define UART_UARTRIS_OERIS_RESET _u(0x0) +#define UART_UARTRIS_OERIS_BITS _u(0x00000400) +#define UART_UARTRIS_OERIS_MSB _u(10) +#define UART_UARTRIS_OERIS_LSB _u(10) +#define UART_UARTRIS_OERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_BERIS +// Description : Break error interrupt status. Returns the raw interrupt state +// of the UARTBEINTR interrupt. +#define UART_UARTRIS_BERIS_RESET _u(0x0) +#define UART_UARTRIS_BERIS_BITS _u(0x00000200) +#define UART_UARTRIS_BERIS_MSB _u(9) +#define UART_UARTRIS_BERIS_LSB _u(9) +#define UART_UARTRIS_BERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_PERIS +// Description : Parity error interrupt status. Returns the raw interrupt state +// of the UARTPEINTR interrupt. +#define UART_UARTRIS_PERIS_RESET _u(0x0) +#define UART_UARTRIS_PERIS_BITS _u(0x00000100) +#define UART_UARTRIS_PERIS_MSB _u(8) +#define UART_UARTRIS_PERIS_LSB _u(8) +#define UART_UARTRIS_PERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_FERIS +// Description : Framing error interrupt status. Returns the raw interrupt state +// of the UARTFEINTR interrupt. +#define UART_UARTRIS_FERIS_RESET _u(0x0) +#define UART_UARTRIS_FERIS_BITS _u(0x00000080) +#define UART_UARTRIS_FERIS_MSB _u(7) +#define UART_UARTRIS_FERIS_LSB _u(7) +#define UART_UARTRIS_FERIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_RTRIS +// Description : Receive timeout interrupt status. Returns the raw interrupt +// state of the UARTRTINTR interrupt. a +#define UART_UARTRIS_RTRIS_RESET _u(0x0) +#define UART_UARTRIS_RTRIS_BITS _u(0x00000040) +#define UART_UARTRIS_RTRIS_MSB _u(6) +#define UART_UARTRIS_RTRIS_LSB _u(6) +#define UART_UARTRIS_RTRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_TXRIS +// Description : Transmit interrupt status. Returns the raw interrupt state of +// the UARTTXINTR interrupt. +#define UART_UARTRIS_TXRIS_RESET _u(0x0) +#define UART_UARTRIS_TXRIS_BITS _u(0x00000020) +#define UART_UARTRIS_TXRIS_MSB _u(5) +#define UART_UARTRIS_TXRIS_LSB _u(5) +#define UART_UARTRIS_TXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_RXRIS +// Description : Receive interrupt status. Returns the raw interrupt state of +// the UARTRXINTR interrupt. +#define UART_UARTRIS_RXRIS_RESET _u(0x0) +#define UART_UARTRIS_RXRIS_BITS _u(0x00000010) +#define UART_UARTRIS_RXRIS_MSB _u(4) +#define UART_UARTRIS_RXRIS_LSB _u(4) +#define UART_UARTRIS_RXRIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_DSRRMIS +// Description : nUARTDSR modem interrupt status. Returns the raw interrupt +// state of the UARTDSRINTR interrupt. +#define UART_UARTRIS_DSRRMIS_RESET "-" +#define UART_UARTRIS_DSRRMIS_BITS _u(0x00000008) +#define UART_UARTRIS_DSRRMIS_MSB _u(3) +#define UART_UARTRIS_DSRRMIS_LSB _u(3) +#define UART_UARTRIS_DSRRMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_DCDRMIS +// Description : nUARTDCD modem interrupt status. Returns the raw interrupt +// state of the UARTDCDINTR interrupt. +#define UART_UARTRIS_DCDRMIS_RESET "-" +#define UART_UARTRIS_DCDRMIS_BITS _u(0x00000004) +#define UART_UARTRIS_DCDRMIS_MSB _u(2) +#define UART_UARTRIS_DCDRMIS_LSB _u(2) +#define UART_UARTRIS_DCDRMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_CTSRMIS +// Description : nUARTCTS modem interrupt status. Returns the raw interrupt +// state of the UARTCTSINTR interrupt. +#define UART_UARTRIS_CTSRMIS_RESET "-" +#define UART_UARTRIS_CTSRMIS_BITS _u(0x00000002) +#define UART_UARTRIS_CTSRMIS_MSB _u(1) +#define UART_UARTRIS_CTSRMIS_LSB _u(1) +#define UART_UARTRIS_CTSRMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTRIS_RIRMIS +// Description : nUARTRI modem interrupt status. Returns the raw interrupt state +// of the UARTRIINTR interrupt. +#define UART_UARTRIS_RIRMIS_RESET "-" +#define UART_UARTRIS_RIRMIS_BITS _u(0x00000001) +#define UART_UARTRIS_RIRMIS_MSB _u(0) +#define UART_UARTRIS_RIRMIS_LSB _u(0) +#define UART_UARTRIS_RIRMIS_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTMIS +// Description : Masked Interrupt Status Register, UARTMIS +#define UART_UARTMIS_OFFSET _u(0x00000040) +#define UART_UARTMIS_BITS _u(0x000007ff) +#define UART_UARTMIS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_OEMIS +// Description : Overrun error masked interrupt status. Returns the masked +// interrupt state of the UARTOEINTR interrupt. +#define UART_UARTMIS_OEMIS_RESET _u(0x0) +#define UART_UARTMIS_OEMIS_BITS _u(0x00000400) +#define UART_UARTMIS_OEMIS_MSB _u(10) +#define UART_UARTMIS_OEMIS_LSB _u(10) +#define UART_UARTMIS_OEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_BEMIS +// Description : Break error masked interrupt status. Returns the masked +// interrupt state of the UARTBEINTR interrupt. +#define UART_UARTMIS_BEMIS_RESET _u(0x0) +#define UART_UARTMIS_BEMIS_BITS _u(0x00000200) +#define UART_UARTMIS_BEMIS_MSB _u(9) +#define UART_UARTMIS_BEMIS_LSB _u(9) +#define UART_UARTMIS_BEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_PEMIS +// Description : Parity error masked interrupt status. Returns the masked +// interrupt state of the UARTPEINTR interrupt. +#define UART_UARTMIS_PEMIS_RESET _u(0x0) +#define UART_UARTMIS_PEMIS_BITS _u(0x00000100) +#define UART_UARTMIS_PEMIS_MSB _u(8) +#define UART_UARTMIS_PEMIS_LSB _u(8) +#define UART_UARTMIS_PEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_FEMIS +// Description : Framing error masked interrupt status. Returns the masked +// interrupt state of the UARTFEINTR interrupt. +#define UART_UARTMIS_FEMIS_RESET _u(0x0) +#define UART_UARTMIS_FEMIS_BITS _u(0x00000080) +#define UART_UARTMIS_FEMIS_MSB _u(7) +#define UART_UARTMIS_FEMIS_LSB _u(7) +#define UART_UARTMIS_FEMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_RTMIS +// Description : Receive timeout masked interrupt status. Returns the masked +// interrupt state of the UARTRTINTR interrupt. +#define UART_UARTMIS_RTMIS_RESET _u(0x0) +#define UART_UARTMIS_RTMIS_BITS _u(0x00000040) +#define UART_UARTMIS_RTMIS_MSB _u(6) +#define UART_UARTMIS_RTMIS_LSB _u(6) +#define UART_UARTMIS_RTMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_TXMIS +// Description : Transmit masked interrupt status. Returns the masked interrupt +// state of the UARTTXINTR interrupt. +#define UART_UARTMIS_TXMIS_RESET _u(0x0) +#define UART_UARTMIS_TXMIS_BITS _u(0x00000020) +#define UART_UARTMIS_TXMIS_MSB _u(5) +#define UART_UARTMIS_TXMIS_LSB _u(5) +#define UART_UARTMIS_TXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_RXMIS +// Description : Receive masked interrupt status. Returns the masked interrupt +// state of the UARTRXINTR interrupt. +#define UART_UARTMIS_RXMIS_RESET _u(0x0) +#define UART_UARTMIS_RXMIS_BITS _u(0x00000010) +#define UART_UARTMIS_RXMIS_MSB _u(4) +#define UART_UARTMIS_RXMIS_LSB _u(4) +#define UART_UARTMIS_RXMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_DSRMMIS +// Description : nUARTDSR modem masked interrupt status. Returns the masked +// interrupt state of the UARTDSRINTR interrupt. +#define UART_UARTMIS_DSRMMIS_RESET "-" +#define UART_UARTMIS_DSRMMIS_BITS _u(0x00000008) +#define UART_UARTMIS_DSRMMIS_MSB _u(3) +#define UART_UARTMIS_DSRMMIS_LSB _u(3) +#define UART_UARTMIS_DSRMMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_DCDMMIS +// Description : nUARTDCD modem masked interrupt status. Returns the masked +// interrupt state of the UARTDCDINTR interrupt. +#define UART_UARTMIS_DCDMMIS_RESET "-" +#define UART_UARTMIS_DCDMMIS_BITS _u(0x00000004) +#define UART_UARTMIS_DCDMMIS_MSB _u(2) +#define UART_UARTMIS_DCDMMIS_LSB _u(2) +#define UART_UARTMIS_DCDMMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_CTSMMIS +// Description : nUARTCTS modem masked interrupt status. Returns the masked +// interrupt state of the UARTCTSINTR interrupt. +#define UART_UARTMIS_CTSMMIS_RESET "-" +#define UART_UARTMIS_CTSMMIS_BITS _u(0x00000002) +#define UART_UARTMIS_CTSMMIS_MSB _u(1) +#define UART_UARTMIS_CTSMMIS_LSB _u(1) +#define UART_UARTMIS_CTSMMIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTMIS_RIMMIS +// Description : nUARTRI modem masked interrupt status. Returns the masked +// interrupt state of the UARTRIINTR interrupt. +#define UART_UARTMIS_RIMMIS_RESET "-" +#define UART_UARTMIS_RIMMIS_BITS _u(0x00000001) +#define UART_UARTMIS_RIMMIS_MSB _u(0) +#define UART_UARTMIS_RIMMIS_LSB _u(0) +#define UART_UARTMIS_RIMMIS_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTICR +// Description : Interrupt Clear Register, UARTICR +#define UART_UARTICR_OFFSET _u(0x00000044) +#define UART_UARTICR_BITS _u(0x000007ff) +#define UART_UARTICR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_OEIC +// Description : Overrun error interrupt clear. Clears the UARTOEINTR interrupt. +#define UART_UARTICR_OEIC_RESET "-" +#define UART_UARTICR_OEIC_BITS _u(0x00000400) +#define UART_UARTICR_OEIC_MSB _u(10) +#define UART_UARTICR_OEIC_LSB _u(10) +#define UART_UARTICR_OEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_BEIC +// Description : Break error interrupt clear. Clears the UARTBEINTR interrupt. +#define UART_UARTICR_BEIC_RESET "-" +#define UART_UARTICR_BEIC_BITS _u(0x00000200) +#define UART_UARTICR_BEIC_MSB _u(9) +#define UART_UARTICR_BEIC_LSB _u(9) +#define UART_UARTICR_BEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_PEIC +// Description : Parity error interrupt clear. Clears the UARTPEINTR interrupt. +#define UART_UARTICR_PEIC_RESET "-" +#define UART_UARTICR_PEIC_BITS _u(0x00000100) +#define UART_UARTICR_PEIC_MSB _u(8) +#define UART_UARTICR_PEIC_LSB _u(8) +#define UART_UARTICR_PEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_FEIC +// Description : Framing error interrupt clear. Clears the UARTFEINTR interrupt. +#define UART_UARTICR_FEIC_RESET "-" +#define UART_UARTICR_FEIC_BITS _u(0x00000080) +#define UART_UARTICR_FEIC_MSB _u(7) +#define UART_UARTICR_FEIC_LSB _u(7) +#define UART_UARTICR_FEIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_RTIC +// Description : Receive timeout interrupt clear. Clears the UARTRTINTR +// interrupt. +#define UART_UARTICR_RTIC_RESET "-" +#define UART_UARTICR_RTIC_BITS _u(0x00000040) +#define UART_UARTICR_RTIC_MSB _u(6) +#define UART_UARTICR_RTIC_LSB _u(6) +#define UART_UARTICR_RTIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_TXIC +// Description : Transmit interrupt clear. Clears the UARTTXINTR interrupt. +#define UART_UARTICR_TXIC_RESET "-" +#define UART_UARTICR_TXIC_BITS _u(0x00000020) +#define UART_UARTICR_TXIC_MSB _u(5) +#define UART_UARTICR_TXIC_LSB _u(5) +#define UART_UARTICR_TXIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_RXIC +// Description : Receive interrupt clear. Clears the UARTRXINTR interrupt. +#define UART_UARTICR_RXIC_RESET "-" +#define UART_UARTICR_RXIC_BITS _u(0x00000010) +#define UART_UARTICR_RXIC_MSB _u(4) +#define UART_UARTICR_RXIC_LSB _u(4) +#define UART_UARTICR_RXIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_DSRMIC +// Description : nUARTDSR modem interrupt clear. Clears the UARTDSRINTR +// interrupt. +#define UART_UARTICR_DSRMIC_RESET "-" +#define UART_UARTICR_DSRMIC_BITS _u(0x00000008) +#define UART_UARTICR_DSRMIC_MSB _u(3) +#define UART_UARTICR_DSRMIC_LSB _u(3) +#define UART_UARTICR_DSRMIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_DCDMIC +// Description : nUARTDCD modem interrupt clear. Clears the UARTDCDINTR +// interrupt. +#define UART_UARTICR_DCDMIC_RESET "-" +#define UART_UARTICR_DCDMIC_BITS _u(0x00000004) +#define UART_UARTICR_DCDMIC_MSB _u(2) +#define UART_UARTICR_DCDMIC_LSB _u(2) +#define UART_UARTICR_DCDMIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_CTSMIC +// Description : nUARTCTS modem interrupt clear. Clears the UARTCTSINTR +// interrupt. +#define UART_UARTICR_CTSMIC_RESET "-" +#define UART_UARTICR_CTSMIC_BITS _u(0x00000002) +#define UART_UARTICR_CTSMIC_MSB _u(1) +#define UART_UARTICR_CTSMIC_LSB _u(1) +#define UART_UARTICR_CTSMIC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : UART_UARTICR_RIMIC +// Description : nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. +#define UART_UARTICR_RIMIC_RESET "-" +#define UART_UARTICR_RIMIC_BITS _u(0x00000001) +#define UART_UARTICR_RIMIC_MSB _u(0) +#define UART_UARTICR_RIMIC_LSB _u(0) +#define UART_UARTICR_RIMIC_ACCESS "WC" +// ============================================================================= +// Register : UART_UARTDMACR +// Description : DMA Control Register, UARTDMACR +#define UART_UARTDMACR_OFFSET _u(0x00000048) +#define UART_UARTDMACR_BITS _u(0x00000007) +#define UART_UARTDMACR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTDMACR_DMAONERR +// Description : DMA on error. If this bit is set to 1, the DMA receive request +// outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the +// UART error interrupt is asserted. +#define UART_UARTDMACR_DMAONERR_RESET _u(0x0) +#define UART_UARTDMACR_DMAONERR_BITS _u(0x00000004) +#define UART_UARTDMACR_DMAONERR_MSB _u(2) +#define UART_UARTDMACR_DMAONERR_LSB _u(2) +#define UART_UARTDMACR_DMAONERR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDMACR_TXDMAE +// Description : Transmit DMA enable. If this bit is set to 1, DMA for the +// transmit FIFO is enabled. +#define UART_UARTDMACR_TXDMAE_RESET _u(0x0) +#define UART_UARTDMACR_TXDMAE_BITS _u(0x00000002) +#define UART_UARTDMACR_TXDMAE_MSB _u(1) +#define UART_UARTDMACR_TXDMAE_LSB _u(1) +#define UART_UARTDMACR_TXDMAE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : UART_UARTDMACR_RXDMAE +// Description : Receive DMA enable. If this bit is set to 1, DMA for the +// receive FIFO is enabled. +#define UART_UARTDMACR_RXDMAE_RESET _u(0x0) +#define UART_UARTDMACR_RXDMAE_BITS _u(0x00000001) +#define UART_UARTDMACR_RXDMAE_MSB _u(0) +#define UART_UARTDMACR_RXDMAE_LSB _u(0) +#define UART_UARTDMACR_RXDMAE_ACCESS "RW" +// ============================================================================= +// Register : UART_UARTPERIPHID0 +// Description : UARTPeriphID0 Register +#define UART_UARTPERIPHID0_OFFSET _u(0x00000fe0) +#define UART_UARTPERIPHID0_BITS _u(0x000000ff) +#define UART_UARTPERIPHID0_RESET _u(0x00000011) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID0_PARTNUMBER0 +// Description : These bits read back as 0x11 +#define UART_UARTPERIPHID0_PARTNUMBER0_RESET _u(0x11) +#define UART_UARTPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff) +#define UART_UARTPERIPHID0_PARTNUMBER0_MSB _u(7) +#define UART_UARTPERIPHID0_PARTNUMBER0_LSB _u(0) +#define UART_UARTPERIPHID0_PARTNUMBER0_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPERIPHID1 +// Description : UARTPeriphID1 Register +#define UART_UARTPERIPHID1_OFFSET _u(0x00000fe4) +#define UART_UARTPERIPHID1_BITS _u(0x000000ff) +#define UART_UARTPERIPHID1_RESET _u(0x00000010) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID1_DESIGNER0 +// Description : These bits read back as 0x1 +#define UART_UARTPERIPHID1_DESIGNER0_RESET _u(0x1) +#define UART_UARTPERIPHID1_DESIGNER0_BITS _u(0x000000f0) +#define UART_UARTPERIPHID1_DESIGNER0_MSB _u(7) +#define UART_UARTPERIPHID1_DESIGNER0_LSB _u(4) +#define UART_UARTPERIPHID1_DESIGNER0_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID1_PARTNUMBER1 +// Description : These bits read back as 0x0 +#define UART_UARTPERIPHID1_PARTNUMBER1_RESET _u(0x0) +#define UART_UARTPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f) +#define UART_UARTPERIPHID1_PARTNUMBER1_MSB _u(3) +#define UART_UARTPERIPHID1_PARTNUMBER1_LSB _u(0) +#define UART_UARTPERIPHID1_PARTNUMBER1_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPERIPHID2 +// Description : UARTPeriphID2 Register +#define UART_UARTPERIPHID2_OFFSET _u(0x00000fe8) +#define UART_UARTPERIPHID2_BITS _u(0x000000ff) +#define UART_UARTPERIPHID2_RESET _u(0x00000034) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID2_REVISION +// Description : This field depends on the revision of the UART: r1p0 0x0 r1p1 +// 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 +#define UART_UARTPERIPHID2_REVISION_RESET _u(0x3) +#define UART_UARTPERIPHID2_REVISION_BITS _u(0x000000f0) +#define UART_UARTPERIPHID2_REVISION_MSB _u(7) +#define UART_UARTPERIPHID2_REVISION_LSB _u(4) +#define UART_UARTPERIPHID2_REVISION_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID2_DESIGNER1 +// Description : These bits read back as 0x4 +#define UART_UARTPERIPHID2_DESIGNER1_RESET _u(0x4) +#define UART_UARTPERIPHID2_DESIGNER1_BITS _u(0x0000000f) +#define UART_UARTPERIPHID2_DESIGNER1_MSB _u(3) +#define UART_UARTPERIPHID2_DESIGNER1_LSB _u(0) +#define UART_UARTPERIPHID2_DESIGNER1_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPERIPHID3 +// Description : UARTPeriphID3 Register +#define UART_UARTPERIPHID3_OFFSET _u(0x00000fec) +#define UART_UARTPERIPHID3_BITS _u(0x000000ff) +#define UART_UARTPERIPHID3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPERIPHID3_CONFIGURATION +// Description : These bits read back as 0x00 +#define UART_UARTPERIPHID3_CONFIGURATION_RESET _u(0x00) +#define UART_UARTPERIPHID3_CONFIGURATION_BITS _u(0x000000ff) +#define UART_UARTPERIPHID3_CONFIGURATION_MSB _u(7) +#define UART_UARTPERIPHID3_CONFIGURATION_LSB _u(0) +#define UART_UARTPERIPHID3_CONFIGURATION_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID0 +// Description : UARTPCellID0 Register +#define UART_UARTPCELLID0_OFFSET _u(0x00000ff0) +#define UART_UARTPCELLID0_BITS _u(0x000000ff) +#define UART_UARTPCELLID0_RESET _u(0x0000000d) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID0_UARTPCELLID0 +// Description : These bits read back as 0x0D +#define UART_UARTPCELLID0_UARTPCELLID0_RESET _u(0x0d) +#define UART_UARTPCELLID0_UARTPCELLID0_BITS _u(0x000000ff) +#define UART_UARTPCELLID0_UARTPCELLID0_MSB _u(7) +#define UART_UARTPCELLID0_UARTPCELLID0_LSB _u(0) +#define UART_UARTPCELLID0_UARTPCELLID0_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID1 +// Description : UARTPCellID1 Register +#define UART_UARTPCELLID1_OFFSET _u(0x00000ff4) +#define UART_UARTPCELLID1_BITS _u(0x000000ff) +#define UART_UARTPCELLID1_RESET _u(0x000000f0) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID1_UARTPCELLID1 +// Description : These bits read back as 0xF0 +#define UART_UARTPCELLID1_UARTPCELLID1_RESET _u(0xf0) +#define UART_UARTPCELLID1_UARTPCELLID1_BITS _u(0x000000ff) +#define UART_UARTPCELLID1_UARTPCELLID1_MSB _u(7) +#define UART_UARTPCELLID1_UARTPCELLID1_LSB _u(0) +#define UART_UARTPCELLID1_UARTPCELLID1_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID2 +// Description : UARTPCellID2 Register +#define UART_UARTPCELLID2_OFFSET _u(0x00000ff8) +#define UART_UARTPCELLID2_BITS _u(0x000000ff) +#define UART_UARTPCELLID2_RESET _u(0x00000005) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID2_UARTPCELLID2 +// Description : These bits read back as 0x05 +#define UART_UARTPCELLID2_UARTPCELLID2_RESET _u(0x05) +#define UART_UARTPCELLID2_UARTPCELLID2_BITS _u(0x000000ff) +#define UART_UARTPCELLID2_UARTPCELLID2_MSB _u(7) +#define UART_UARTPCELLID2_UARTPCELLID2_LSB _u(0) +#define UART_UARTPCELLID2_UARTPCELLID2_ACCESS "RO" +// ============================================================================= +// Register : UART_UARTPCELLID3 +// Description : UARTPCellID3 Register +#define UART_UARTPCELLID3_OFFSET _u(0x00000ffc) +#define UART_UARTPCELLID3_BITS _u(0x000000ff) +#define UART_UARTPCELLID3_RESET _u(0x000000b1) +// ----------------------------------------------------------------------------- +// Field : UART_UARTPCELLID3_UARTPCELLID3 +// Description : These bits read back as 0xB1 +#define UART_UARTPCELLID3_UARTPCELLID3_RESET _u(0xb1) +#define UART_UARTPCELLID3_UARTPCELLID3_BITS _u(0x000000ff) +#define UART_UARTPCELLID3_UARTPCELLID3_MSB _u(7) +#define UART_UARTPCELLID3_UARTPCELLID3_LSB _u(0) +#define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO" +// ============================================================================= +#endif // _HARDWARE_REGS_UART_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/usb.h b/lib/pico-sdk/rp2350/hardware/regs/usb.h new file mode 100644 index 000000000000..fbf1b7b3636e --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/usb.h @@ -0,0 +1,4209 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : USB +// Version : 1 +// Bus type : ahbl +// Description : USB FS/LS controller device registers +// ============================================================================= +#ifndef _HARDWARE_REGS_USB_H +#define _HARDWARE_REGS_USB_H +// ============================================================================= +// Register : USB_ADDR_ENDP +// Description : Device address and endpoint control +#define USB_ADDR_ENDP_OFFSET _u(0x00000000) +#define USB_ADDR_ENDP_BITS _u(0x000f007f) +#define USB_ADDR_ENDP_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP_ENDPOINT +// Description : Device endpoint to send data to. Only valid for HOST mode. +#define USB_ADDR_ENDP_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP_ADDRESS +// Description : In device mode, the address that the device should respond to. +// Set in response to a SET_ADDR setup packet from the host. In +// host mode set to the address of the device to communicate with. +#define USB_ADDR_ENDP_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP1 +// Description : Interrupt endpoint 1. Only valid for HOST mode. +#define USB_ADDR_ENDP1_OFFSET _u(0x00000004) +#define USB_ADDR_ENDP1_BITS _u(0x060f007f) +#define USB_ADDR_ENDP1_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP1_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP1_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP1_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP1_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP1_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP1_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP1_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP1_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP1_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP1_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP1_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP1_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP1_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP1_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP1_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP1_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP1_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP2 +// Description : Interrupt endpoint 2. Only valid for HOST mode. +#define USB_ADDR_ENDP2_OFFSET _u(0x00000008) +#define USB_ADDR_ENDP2_BITS _u(0x060f007f) +#define USB_ADDR_ENDP2_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP2_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP2_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP2_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP2_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP2_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP2_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP2_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP2_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP2_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP2_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP2_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP2_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP2_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP2_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP2_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP2_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP2_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP3 +// Description : Interrupt endpoint 3. Only valid for HOST mode. +#define USB_ADDR_ENDP3_OFFSET _u(0x0000000c) +#define USB_ADDR_ENDP3_BITS _u(0x060f007f) +#define USB_ADDR_ENDP3_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP3_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP3_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP3_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP3_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP3_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP3_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP3_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP3_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP3_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP3_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP3_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP3_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP3_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP3_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP3_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP3_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP3_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP4 +// Description : Interrupt endpoint 4. Only valid for HOST mode. +#define USB_ADDR_ENDP4_OFFSET _u(0x00000010) +#define USB_ADDR_ENDP4_BITS _u(0x060f007f) +#define USB_ADDR_ENDP4_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP4_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP4_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP4_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP4_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP4_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP4_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP4_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP4_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP4_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP4_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP4_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP4_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP4_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP4_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP4_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP4_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP4_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP5 +// Description : Interrupt endpoint 5. Only valid for HOST mode. +#define USB_ADDR_ENDP5_OFFSET _u(0x00000014) +#define USB_ADDR_ENDP5_BITS _u(0x060f007f) +#define USB_ADDR_ENDP5_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP5_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP5_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP5_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP5_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP5_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP5_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP5_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP5_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP5_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP5_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP5_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP5_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP5_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP5_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP5_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP5_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP5_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP6 +// Description : Interrupt endpoint 6. Only valid for HOST mode. +#define USB_ADDR_ENDP6_OFFSET _u(0x00000018) +#define USB_ADDR_ENDP6_BITS _u(0x060f007f) +#define USB_ADDR_ENDP6_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP6_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP6_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP6_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP6_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP6_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP6_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP6_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP6_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP6_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP6_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP6_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP6_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP6_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP6_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP6_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP6_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP6_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP7 +// Description : Interrupt endpoint 7. Only valid for HOST mode. +#define USB_ADDR_ENDP7_OFFSET _u(0x0000001c) +#define USB_ADDR_ENDP7_BITS _u(0x060f007f) +#define USB_ADDR_ENDP7_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP7_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP7_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP7_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP7_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP7_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP7_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP7_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP7_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP7_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP7_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP7_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP7_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP7_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP7_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP7_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP7_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP7_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP8 +// Description : Interrupt endpoint 8. Only valid for HOST mode. +#define USB_ADDR_ENDP8_OFFSET _u(0x00000020) +#define USB_ADDR_ENDP8_BITS _u(0x060f007f) +#define USB_ADDR_ENDP8_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP8_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP8_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP8_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP8_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP8_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP8_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP8_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP8_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP8_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP8_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP8_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP8_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP8_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP8_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP8_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP8_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP8_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP9 +// Description : Interrupt endpoint 9. Only valid for HOST mode. +#define USB_ADDR_ENDP9_OFFSET _u(0x00000024) +#define USB_ADDR_ENDP9_BITS _u(0x060f007f) +#define USB_ADDR_ENDP9_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP9_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP9_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP9_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP9_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP9_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP9_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP9_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP9_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP9_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP9_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP9_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP9_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP9_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP9_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP9_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP9_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP9_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP10 +// Description : Interrupt endpoint 10. Only valid for HOST mode. +#define USB_ADDR_ENDP10_OFFSET _u(0x00000028) +#define USB_ADDR_ENDP10_BITS _u(0x060f007f) +#define USB_ADDR_ENDP10_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP10_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP10_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP10_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP10_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP10_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP10_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP10_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP10_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP10_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP10_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP10_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP10_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP10_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP10_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP10_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP10_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP10_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP11 +// Description : Interrupt endpoint 11. Only valid for HOST mode. +#define USB_ADDR_ENDP11_OFFSET _u(0x0000002c) +#define USB_ADDR_ENDP11_BITS _u(0x060f007f) +#define USB_ADDR_ENDP11_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP11_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP11_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP11_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP11_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP11_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP11_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP11_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP11_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP11_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP11_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP11_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP11_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP11_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP11_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP11_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP11_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP11_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP12 +// Description : Interrupt endpoint 12. Only valid for HOST mode. +#define USB_ADDR_ENDP12_OFFSET _u(0x00000030) +#define USB_ADDR_ENDP12_BITS _u(0x060f007f) +#define USB_ADDR_ENDP12_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP12_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP12_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP12_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP12_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP12_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP12_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP12_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP12_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP12_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP12_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP12_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP12_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP12_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP12_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP12_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP12_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP12_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP13 +// Description : Interrupt endpoint 13. Only valid for HOST mode. +#define USB_ADDR_ENDP13_OFFSET _u(0x00000034) +#define USB_ADDR_ENDP13_BITS _u(0x060f007f) +#define USB_ADDR_ENDP13_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP13_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP13_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP13_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP13_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP13_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP13_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP13_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP13_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP13_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP13_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP13_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP13_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP13_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP13_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP13_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP13_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP13_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP14 +// Description : Interrupt endpoint 14. Only valid for HOST mode. +#define USB_ADDR_ENDP14_OFFSET _u(0x00000038) +#define USB_ADDR_ENDP14_BITS _u(0x060f007f) +#define USB_ADDR_ENDP14_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP14_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP14_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP14_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP14_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP14_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP14_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP14_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP14_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP14_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP14_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP14_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP14_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP14_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP14_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP14_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP14_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP14_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_ADDR_ENDP15 +// Description : Interrupt endpoint 15. Only valid for HOST mode. +#define USB_ADDR_ENDP15_OFFSET _u(0x0000003c) +#define USB_ADDR_ENDP15_BITS _u(0x060f007f) +#define USB_ADDR_ENDP15_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_INTEP_PREAMBLE +// Description : Interrupt EP requires preamble (is a low speed device on a full +// speed hub) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET _u(0x0) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS _u(0x04000000) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB _u(26) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB _u(26) +#define USB_ADDR_ENDP15_INTEP_PREAMBLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_INTEP_DIR +// Description : Direction of the interrupt endpoint. In=0, Out=1 +#define USB_ADDR_ENDP15_INTEP_DIR_RESET _u(0x0) +#define USB_ADDR_ENDP15_INTEP_DIR_BITS _u(0x02000000) +#define USB_ADDR_ENDP15_INTEP_DIR_MSB _u(25) +#define USB_ADDR_ENDP15_INTEP_DIR_LSB _u(25) +#define USB_ADDR_ENDP15_INTEP_DIR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_ENDPOINT +// Description : Endpoint number of the interrupt endpoint +#define USB_ADDR_ENDP15_ENDPOINT_RESET _u(0x0) +#define USB_ADDR_ENDP15_ENDPOINT_BITS _u(0x000f0000) +#define USB_ADDR_ENDP15_ENDPOINT_MSB _u(19) +#define USB_ADDR_ENDP15_ENDPOINT_LSB _u(16) +#define USB_ADDR_ENDP15_ENDPOINT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_ADDR_ENDP15_ADDRESS +// Description : Device address +#define USB_ADDR_ENDP15_ADDRESS_RESET _u(0x00) +#define USB_ADDR_ENDP15_ADDRESS_BITS _u(0x0000007f) +#define USB_ADDR_ENDP15_ADDRESS_MSB _u(6) +#define USB_ADDR_ENDP15_ADDRESS_LSB _u(0) +#define USB_ADDR_ENDP15_ADDRESS_ACCESS "RW" +// ============================================================================= +// Register : USB_MAIN_CTRL +// Description : Main control register +#define USB_MAIN_CTRL_OFFSET _u(0x00000040) +#define USB_MAIN_CTRL_BITS _u(0x80000007) +#define USB_MAIN_CTRL_RESET _u(0x00000004) +// ----------------------------------------------------------------------------- +// Field : USB_MAIN_CTRL_SIM_TIMING +// Description : Reduced timings for simulation +#define USB_MAIN_CTRL_SIM_TIMING_RESET _u(0x0) +#define USB_MAIN_CTRL_SIM_TIMING_BITS _u(0x80000000) +#define USB_MAIN_CTRL_SIM_TIMING_MSB _u(31) +#define USB_MAIN_CTRL_SIM_TIMING_LSB _u(31) +#define USB_MAIN_CTRL_SIM_TIMING_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_MAIN_CTRL_PHY_ISO +// Description : Isolates USB phy after controller power-up +// Remove isolation once software has configured the controller +// Not isolated = 0, Isolated = 1 +#define USB_MAIN_CTRL_PHY_ISO_RESET _u(0x1) +#define USB_MAIN_CTRL_PHY_ISO_BITS _u(0x00000004) +#define USB_MAIN_CTRL_PHY_ISO_MSB _u(2) +#define USB_MAIN_CTRL_PHY_ISO_LSB _u(2) +#define USB_MAIN_CTRL_PHY_ISO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_MAIN_CTRL_HOST_NDEVICE +// Description : Device mode = 0, Host mode = 1 +#define USB_MAIN_CTRL_HOST_NDEVICE_RESET _u(0x0) +#define USB_MAIN_CTRL_HOST_NDEVICE_BITS _u(0x00000002) +#define USB_MAIN_CTRL_HOST_NDEVICE_MSB _u(1) +#define USB_MAIN_CTRL_HOST_NDEVICE_LSB _u(1) +#define USB_MAIN_CTRL_HOST_NDEVICE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_MAIN_CTRL_CONTROLLER_EN +// Description : Enable controller +#define USB_MAIN_CTRL_CONTROLLER_EN_RESET _u(0x0) +#define USB_MAIN_CTRL_CONTROLLER_EN_BITS _u(0x00000001) +#define USB_MAIN_CTRL_CONTROLLER_EN_MSB _u(0) +#define USB_MAIN_CTRL_CONTROLLER_EN_LSB _u(0) +#define USB_MAIN_CTRL_CONTROLLER_EN_ACCESS "RW" +// ============================================================================= +// Register : USB_SOF_WR +// Description : Set the SOF (Start of Frame) frame number in the host +// controller. The SOF packet is sent every 1ms and the host will +// increment the frame number by 1 each time. +#define USB_SOF_WR_OFFSET _u(0x00000044) +#define USB_SOF_WR_BITS _u(0x000007ff) +#define USB_SOF_WR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_SOF_WR_COUNT +#define USB_SOF_WR_COUNT_RESET _u(0x000) +#define USB_SOF_WR_COUNT_BITS _u(0x000007ff) +#define USB_SOF_WR_COUNT_MSB _u(10) +#define USB_SOF_WR_COUNT_LSB _u(0) +#define USB_SOF_WR_COUNT_ACCESS "WF" +// ============================================================================= +// Register : USB_SOF_RD +// Description : Read the last SOF (Start of Frame) frame number seen. In device +// mode the last SOF received from the host. In host mode the last +// SOF sent by the host. +#define USB_SOF_RD_OFFSET _u(0x00000048) +#define USB_SOF_RD_BITS _u(0x000007ff) +#define USB_SOF_RD_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_SOF_RD_COUNT +#define USB_SOF_RD_COUNT_RESET _u(0x000) +#define USB_SOF_RD_COUNT_BITS _u(0x000007ff) +#define USB_SOF_RD_COUNT_MSB _u(10) +#define USB_SOF_RD_COUNT_LSB _u(0) +#define USB_SOF_RD_COUNT_ACCESS "RO" +// ============================================================================= +// Register : USB_SIE_CTRL +// Description : SIE control register +#define USB_SIE_CTRL_OFFSET _u(0x0000004c) +#define USB_SIE_CTRL_BITS _u(0xff0fbf5f) +#define USB_SIE_CTRL_RESET _u(0x00008000) +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_STALL +// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL +#define USB_SIE_CTRL_EP0_INT_STALL_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_STALL_BITS _u(0x80000000) +#define USB_SIE_CTRL_EP0_INT_STALL_MSB _u(31) +#define USB_SIE_CTRL_EP0_INT_STALL_LSB _u(31) +#define USB_SIE_CTRL_EP0_INT_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_DOUBLE_BUF +// Description : Device: EP0 single buffered = 0, double buffered = 1 +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS _u(0x40000000) +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB _u(30) +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB _u(30) +#define USB_SIE_CTRL_EP0_DOUBLE_BUF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_1BUF +// Description : Device: Set bit in BUFF_STATUS for every buffer completed on +// EP0 +#define USB_SIE_CTRL_EP0_INT_1BUF_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_1BUF_BITS _u(0x20000000) +#define USB_SIE_CTRL_EP0_INT_1BUF_MSB _u(29) +#define USB_SIE_CTRL_EP0_INT_1BUF_LSB _u(29) +#define USB_SIE_CTRL_EP0_INT_1BUF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_2BUF +// Description : Device: Set bit in BUFF_STATUS for every 2 buffers completed on +// EP0 +#define USB_SIE_CTRL_EP0_INT_2BUF_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_2BUF_BITS _u(0x10000000) +#define USB_SIE_CTRL_EP0_INT_2BUF_MSB _u(28) +#define USB_SIE_CTRL_EP0_INT_2BUF_LSB _u(28) +#define USB_SIE_CTRL_EP0_INT_2BUF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_INT_NAK +// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK +#define USB_SIE_CTRL_EP0_INT_NAK_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_INT_NAK_BITS _u(0x08000000) +#define USB_SIE_CTRL_EP0_INT_NAK_MSB _u(27) +#define USB_SIE_CTRL_EP0_INT_NAK_LSB _u(27) +#define USB_SIE_CTRL_EP0_INT_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_DIRECT_EN +// Description : Direct bus drive enable +#define USB_SIE_CTRL_DIRECT_EN_RESET _u(0x0) +#define USB_SIE_CTRL_DIRECT_EN_BITS _u(0x04000000) +#define USB_SIE_CTRL_DIRECT_EN_MSB _u(26) +#define USB_SIE_CTRL_DIRECT_EN_LSB _u(26) +#define USB_SIE_CTRL_DIRECT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_DIRECT_DP +// Description : Direct control of DP +#define USB_SIE_CTRL_DIRECT_DP_RESET _u(0x0) +#define USB_SIE_CTRL_DIRECT_DP_BITS _u(0x02000000) +#define USB_SIE_CTRL_DIRECT_DP_MSB _u(25) +#define USB_SIE_CTRL_DIRECT_DP_LSB _u(25) +#define USB_SIE_CTRL_DIRECT_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_DIRECT_DM +// Description : Direct control of DM +#define USB_SIE_CTRL_DIRECT_DM_RESET _u(0x0) +#define USB_SIE_CTRL_DIRECT_DM_BITS _u(0x01000000) +#define USB_SIE_CTRL_DIRECT_DM_MSB _u(24) +#define USB_SIE_CTRL_DIRECT_DM_LSB _u(24) +#define USB_SIE_CTRL_DIRECT_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET +// Description : Device: Stop EP0 on a short packet. +#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_RESET _u(0x0) +#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_BITS _u(0x00080000) +#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_MSB _u(19) +#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_LSB _u(19) +#define USB_SIE_CTRL_EP0_STOP_ON_SHORT_PACKET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_TRANSCEIVER_PD +// Description : Power down bus transceiver +#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET _u(0x0) +#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS _u(0x00040000) +#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB _u(18) +#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB _u(18) +#define USB_SIE_CTRL_TRANSCEIVER_PD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RPU_OPT +// Description : Device: Pull-up strength (0=1K2, 1=2k3) +#define USB_SIE_CTRL_RPU_OPT_RESET _u(0x0) +#define USB_SIE_CTRL_RPU_OPT_BITS _u(0x00020000) +#define USB_SIE_CTRL_RPU_OPT_MSB _u(17) +#define USB_SIE_CTRL_RPU_OPT_LSB _u(17) +#define USB_SIE_CTRL_RPU_OPT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_PULLUP_EN +// Description : Device: Enable pull up resistor +#define USB_SIE_CTRL_PULLUP_EN_RESET _u(0x0) +#define USB_SIE_CTRL_PULLUP_EN_BITS _u(0x00010000) +#define USB_SIE_CTRL_PULLUP_EN_MSB _u(16) +#define USB_SIE_CTRL_PULLUP_EN_LSB _u(16) +#define USB_SIE_CTRL_PULLUP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_PULLDOWN_EN +// Description : Host: Enable pull down resistors +#define USB_SIE_CTRL_PULLDOWN_EN_RESET _u(0x1) +#define USB_SIE_CTRL_PULLDOWN_EN_BITS _u(0x00008000) +#define USB_SIE_CTRL_PULLDOWN_EN_MSB _u(15) +#define USB_SIE_CTRL_PULLDOWN_EN_LSB _u(15) +#define USB_SIE_CTRL_PULLDOWN_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RESET_BUS +// Description : Host: Reset bus +#define USB_SIE_CTRL_RESET_BUS_RESET _u(0x0) +#define USB_SIE_CTRL_RESET_BUS_BITS _u(0x00002000) +#define USB_SIE_CTRL_RESET_BUS_MSB _u(13) +#define USB_SIE_CTRL_RESET_BUS_LSB _u(13) +#define USB_SIE_CTRL_RESET_BUS_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RESUME +// Description : Device: Remote wakeup. Device can initiate its own resume after +// suspend. +#define USB_SIE_CTRL_RESUME_RESET _u(0x0) +#define USB_SIE_CTRL_RESUME_BITS _u(0x00001000) +#define USB_SIE_CTRL_RESUME_MSB _u(12) +#define USB_SIE_CTRL_RESUME_LSB _u(12) +#define USB_SIE_CTRL_RESUME_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_VBUS_EN +// Description : Host: Enable VBUS +#define USB_SIE_CTRL_VBUS_EN_RESET _u(0x0) +#define USB_SIE_CTRL_VBUS_EN_BITS _u(0x00000800) +#define USB_SIE_CTRL_VBUS_EN_MSB _u(11) +#define USB_SIE_CTRL_VBUS_EN_LSB _u(11) +#define USB_SIE_CTRL_VBUS_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_KEEP_ALIVE_EN +// Description : Host: Enable keep alive packet (for low speed bus) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET _u(0x0) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS _u(0x00000400) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB _u(10) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB _u(10) +#define USB_SIE_CTRL_KEEP_ALIVE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SOF_EN +// Description : Host: Enable SOF generation (for full speed bus) +#define USB_SIE_CTRL_SOF_EN_RESET _u(0x0) +#define USB_SIE_CTRL_SOF_EN_BITS _u(0x00000200) +#define USB_SIE_CTRL_SOF_EN_MSB _u(9) +#define USB_SIE_CTRL_SOF_EN_LSB _u(9) +#define USB_SIE_CTRL_SOF_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SOF_SYNC +// Description : Host: Delay packet(s) until after SOF +#define USB_SIE_CTRL_SOF_SYNC_RESET _u(0x0) +#define USB_SIE_CTRL_SOF_SYNC_BITS _u(0x00000100) +#define USB_SIE_CTRL_SOF_SYNC_MSB _u(8) +#define USB_SIE_CTRL_SOF_SYNC_LSB _u(8) +#define USB_SIE_CTRL_SOF_SYNC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_PREAMBLE_EN +// Description : Host: Preable enable for LS device on FS hub +#define USB_SIE_CTRL_PREAMBLE_EN_RESET _u(0x0) +#define USB_SIE_CTRL_PREAMBLE_EN_BITS _u(0x00000040) +#define USB_SIE_CTRL_PREAMBLE_EN_MSB _u(6) +#define USB_SIE_CTRL_PREAMBLE_EN_LSB _u(6) +#define USB_SIE_CTRL_PREAMBLE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_STOP_TRANS +// Description : Host: Stop transaction +#define USB_SIE_CTRL_STOP_TRANS_RESET _u(0x0) +#define USB_SIE_CTRL_STOP_TRANS_BITS _u(0x00000010) +#define USB_SIE_CTRL_STOP_TRANS_MSB _u(4) +#define USB_SIE_CTRL_STOP_TRANS_LSB _u(4) +#define USB_SIE_CTRL_STOP_TRANS_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_RECEIVE_DATA +// Description : Host: Receive transaction (IN to host) +#define USB_SIE_CTRL_RECEIVE_DATA_RESET _u(0x0) +#define USB_SIE_CTRL_RECEIVE_DATA_BITS _u(0x00000008) +#define USB_SIE_CTRL_RECEIVE_DATA_MSB _u(3) +#define USB_SIE_CTRL_RECEIVE_DATA_LSB _u(3) +#define USB_SIE_CTRL_RECEIVE_DATA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SEND_DATA +// Description : Host: Send transaction (OUT from host) +#define USB_SIE_CTRL_SEND_DATA_RESET _u(0x0) +#define USB_SIE_CTRL_SEND_DATA_BITS _u(0x00000004) +#define USB_SIE_CTRL_SEND_DATA_MSB _u(2) +#define USB_SIE_CTRL_SEND_DATA_LSB _u(2) +#define USB_SIE_CTRL_SEND_DATA_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_SEND_SETUP +// Description : Host: Send Setup packet +#define USB_SIE_CTRL_SEND_SETUP_RESET _u(0x0) +#define USB_SIE_CTRL_SEND_SETUP_BITS _u(0x00000002) +#define USB_SIE_CTRL_SEND_SETUP_MSB _u(1) +#define USB_SIE_CTRL_SEND_SETUP_LSB _u(1) +#define USB_SIE_CTRL_SEND_SETUP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_CTRL_START_TRANS +// Description : Host: Start transaction +#define USB_SIE_CTRL_START_TRANS_RESET _u(0x0) +#define USB_SIE_CTRL_START_TRANS_BITS _u(0x00000001) +#define USB_SIE_CTRL_START_TRANS_MSB _u(0) +#define USB_SIE_CTRL_START_TRANS_LSB _u(0) +#define USB_SIE_CTRL_START_TRANS_ACCESS "SC" +// ============================================================================= +// Register : USB_SIE_STATUS +// Description : SIE status register +#define USB_SIE_STATUS_OFFSET _u(0x00000050) +#define USB_SIE_STATUS_BITS _u(0xff8f1f1d) +#define USB_SIE_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_DATA_SEQ_ERROR +// Description : Data Sequence Error. +// +// The device can raise a sequence error in the following +// conditions: +// +// * A SETUP packet is received followed by a DATA1 packet (data +// phase should always be DATA0) * An OUT packet is received from +// the host but doesn't match the data pid in the buffer control +// register read from DPSRAM +// +// The host can raise a data sequence error in the following +// conditions: +// +// * An IN packet from the device has the wrong data PID +#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET _u(0x0) +#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS _u(0x80000000) +#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB _u(31) +#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB _u(31) +#define USB_SIE_STATUS_DATA_SEQ_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_ACK_REC +// Description : ACK received. Raised by both host and device. +#define USB_SIE_STATUS_ACK_REC_RESET _u(0x0) +#define USB_SIE_STATUS_ACK_REC_BITS _u(0x40000000) +#define USB_SIE_STATUS_ACK_REC_MSB _u(30) +#define USB_SIE_STATUS_ACK_REC_LSB _u(30) +#define USB_SIE_STATUS_ACK_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_STALL_REC +// Description : Host: STALL received +#define USB_SIE_STATUS_STALL_REC_RESET _u(0x0) +#define USB_SIE_STATUS_STALL_REC_BITS _u(0x20000000) +#define USB_SIE_STATUS_STALL_REC_MSB _u(29) +#define USB_SIE_STATUS_STALL_REC_LSB _u(29) +#define USB_SIE_STATUS_STALL_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_NAK_REC +// Description : Host: NAK received +#define USB_SIE_STATUS_NAK_REC_RESET _u(0x0) +#define USB_SIE_STATUS_NAK_REC_BITS _u(0x10000000) +#define USB_SIE_STATUS_NAK_REC_MSB _u(28) +#define USB_SIE_STATUS_NAK_REC_LSB _u(28) +#define USB_SIE_STATUS_NAK_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_RX_TIMEOUT +// Description : RX timeout is raised by both the host and device if an ACK is +// not received in the maximum time specified by the USB spec. +#define USB_SIE_STATUS_RX_TIMEOUT_RESET _u(0x0) +#define USB_SIE_STATUS_RX_TIMEOUT_BITS _u(0x08000000) +#define USB_SIE_STATUS_RX_TIMEOUT_MSB _u(27) +#define USB_SIE_STATUS_RX_TIMEOUT_LSB _u(27) +#define USB_SIE_STATUS_RX_TIMEOUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_RX_OVERFLOW +// Description : RX overflow is raised by the Serial RX engine if the incoming +// data is too fast. +#define USB_SIE_STATUS_RX_OVERFLOW_RESET _u(0x0) +#define USB_SIE_STATUS_RX_OVERFLOW_BITS _u(0x04000000) +#define USB_SIE_STATUS_RX_OVERFLOW_MSB _u(26) +#define USB_SIE_STATUS_RX_OVERFLOW_LSB _u(26) +#define USB_SIE_STATUS_RX_OVERFLOW_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_BIT_STUFF_ERROR +// Description : Bit Stuff Error. Raised by the Serial RX engine. +#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET _u(0x0) +#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS _u(0x02000000) +#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB _u(25) +#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB _u(25) +#define USB_SIE_STATUS_BIT_STUFF_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_CRC_ERROR +// Description : CRC Error. Raised by the Serial RX engine. +#define USB_SIE_STATUS_CRC_ERROR_RESET _u(0x0) +#define USB_SIE_STATUS_CRC_ERROR_BITS _u(0x01000000) +#define USB_SIE_STATUS_CRC_ERROR_MSB _u(24) +#define USB_SIE_STATUS_CRC_ERROR_LSB _u(24) +#define USB_SIE_STATUS_CRC_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_ENDPOINT_ERROR +// Description : An endpoint has encountered an error. Read the ep_rx_error and +// ep_tx_error registers to find out which endpoint had an error. +#define USB_SIE_STATUS_ENDPOINT_ERROR_RESET _u(0x0) +#define USB_SIE_STATUS_ENDPOINT_ERROR_BITS _u(0x00800000) +#define USB_SIE_STATUS_ENDPOINT_ERROR_MSB _u(23) +#define USB_SIE_STATUS_ENDPOINT_ERROR_LSB _u(23) +#define USB_SIE_STATUS_ENDPOINT_ERROR_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_BUS_RESET +// Description : Device: bus reset received +#define USB_SIE_STATUS_BUS_RESET_RESET _u(0x0) +#define USB_SIE_STATUS_BUS_RESET_BITS _u(0x00080000) +#define USB_SIE_STATUS_BUS_RESET_MSB _u(19) +#define USB_SIE_STATUS_BUS_RESET_LSB _u(19) +#define USB_SIE_STATUS_BUS_RESET_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_TRANS_COMPLETE +// Description : Transaction complete. +// +// Raised by device if: +// +// * An IN or OUT packet is sent with the `LAST_BUFF` bit set in +// the buffer control register +// +// Raised by host if: +// +// * A setup packet is sent when no data in or data out +// transaction follows * An IN packet is received and the +// `LAST_BUFF` bit is set in the buffer control register * An IN +// packet is received with zero length * An OUT packet is sent and +// the `LAST_BUFF` bit is set +#define USB_SIE_STATUS_TRANS_COMPLETE_RESET _u(0x0) +#define USB_SIE_STATUS_TRANS_COMPLETE_BITS _u(0x00040000) +#define USB_SIE_STATUS_TRANS_COMPLETE_MSB _u(18) +#define USB_SIE_STATUS_TRANS_COMPLETE_LSB _u(18) +#define USB_SIE_STATUS_TRANS_COMPLETE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_SETUP_REC +// Description : Device: Setup packet received +#define USB_SIE_STATUS_SETUP_REC_RESET _u(0x0) +#define USB_SIE_STATUS_SETUP_REC_BITS _u(0x00020000) +#define USB_SIE_STATUS_SETUP_REC_MSB _u(17) +#define USB_SIE_STATUS_SETUP_REC_LSB _u(17) +#define USB_SIE_STATUS_SETUP_REC_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_CONNECTED +// Description : Device: connected +#define USB_SIE_STATUS_CONNECTED_RESET _u(0x0) +#define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000) +#define USB_SIE_STATUS_CONNECTED_MSB _u(16) +#define USB_SIE_STATUS_CONNECTED_LSB _u(16) +#define USB_SIE_STATUS_CONNECTED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_RX_SHORT_PACKET +// Description : Device or Host has received a short packet. This is when the +// data received is less than configured in the buffer control +// register. Device: If using double buffered mode on device the +// buffer select will not be toggled after writing status back to +// the buffer control register. This is to prevent any further +// transactions on that endpoint until the user has reset the +// buffer control registers. Host: the current transfer will be +// stopped early. +#define USB_SIE_STATUS_RX_SHORT_PACKET_RESET _u(0x0) +#define USB_SIE_STATUS_RX_SHORT_PACKET_BITS _u(0x00001000) +#define USB_SIE_STATUS_RX_SHORT_PACKET_MSB _u(12) +#define USB_SIE_STATUS_RX_SHORT_PACKET_LSB _u(12) +#define USB_SIE_STATUS_RX_SHORT_PACKET_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_RESUME +// Description : Host: Device has initiated a remote resume. Device: host has +// initiated a resume. +#define USB_SIE_STATUS_RESUME_RESET _u(0x0) +#define USB_SIE_STATUS_RESUME_BITS _u(0x00000800) +#define USB_SIE_STATUS_RESUME_MSB _u(11) +#define USB_SIE_STATUS_RESUME_LSB _u(11) +#define USB_SIE_STATUS_RESUME_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_VBUS_OVER_CURR +// Description : VBUS over current detected +#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET _u(0x0) +#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS _u(0x00000400) +#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB _u(10) +#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB _u(10) +#define USB_SIE_STATUS_VBUS_OVER_CURR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_SPEED +// Description : Host: device speed. Disconnected = 00, LS = 01, FS = 10 +#define USB_SIE_STATUS_SPEED_RESET _u(0x0) +#define USB_SIE_STATUS_SPEED_BITS _u(0x00000300) +#define USB_SIE_STATUS_SPEED_MSB _u(9) +#define USB_SIE_STATUS_SPEED_LSB _u(8) +#define USB_SIE_STATUS_SPEED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_SUSPENDED +// Description : Bus in suspended state. Valid for device. Device will go into +// suspend if neither Keep Alive / SOF frames are enabled. +#define USB_SIE_STATUS_SUSPENDED_RESET _u(0x0) +#define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010) +#define USB_SIE_STATUS_SUSPENDED_MSB _u(4) +#define USB_SIE_STATUS_SUSPENDED_LSB _u(4) +#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_LINE_STATE +// Description : USB bus line state +#define USB_SIE_STATUS_LINE_STATE_RESET _u(0x0) +#define USB_SIE_STATUS_LINE_STATE_BITS _u(0x0000000c) +#define USB_SIE_STATUS_LINE_STATE_MSB _u(3) +#define USB_SIE_STATUS_LINE_STATE_LSB _u(2) +#define USB_SIE_STATUS_LINE_STATE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SIE_STATUS_VBUS_DETECTED +// Description : Device: VBUS Detected +#define USB_SIE_STATUS_VBUS_DETECTED_RESET _u(0x0) +#define USB_SIE_STATUS_VBUS_DETECTED_BITS _u(0x00000001) +#define USB_SIE_STATUS_VBUS_DETECTED_MSB _u(0) +#define USB_SIE_STATUS_VBUS_DETECTED_LSB _u(0) +#define USB_SIE_STATUS_VBUS_DETECTED_ACCESS "RO" +// ============================================================================= +// Register : USB_INT_EP_CTRL +// Description : interrupt endpoint control register +#define USB_INT_EP_CTRL_OFFSET _u(0x00000054) +#define USB_INT_EP_CTRL_BITS _u(0x0000fffe) +#define USB_INT_EP_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_INT_EP_CTRL_INT_EP_ACTIVE +// Description : Host: Enable interrupt endpoint 1 -> 15 +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET _u(0x0000) +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS _u(0x0000fffe) +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB _u(15) +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB _u(1) +#define USB_INT_EP_CTRL_INT_EP_ACTIVE_ACCESS "RW" +// ============================================================================= +// Register : USB_BUFF_STATUS +// Description : Buffer status register. A bit set here indicates that a buffer +// has completed on the endpoint (if the buffer interrupt is +// enabled). It is possible for 2 buffers to be completed, so +// clearing the buffer status bit may instantly re set it on the +// next clock cycle. +#define USB_BUFF_STATUS_OFFSET _u(0x00000058) +#define USB_BUFF_STATUS_BITS _u(0xffffffff) +#define USB_BUFF_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP15_OUT +#define USB_BUFF_STATUS_EP15_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP15_OUT_BITS _u(0x80000000) +#define USB_BUFF_STATUS_EP15_OUT_MSB _u(31) +#define USB_BUFF_STATUS_EP15_OUT_LSB _u(31) +#define USB_BUFF_STATUS_EP15_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP15_IN +#define USB_BUFF_STATUS_EP15_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP15_IN_BITS _u(0x40000000) +#define USB_BUFF_STATUS_EP15_IN_MSB _u(30) +#define USB_BUFF_STATUS_EP15_IN_LSB _u(30) +#define USB_BUFF_STATUS_EP15_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP14_OUT +#define USB_BUFF_STATUS_EP14_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP14_OUT_BITS _u(0x20000000) +#define USB_BUFF_STATUS_EP14_OUT_MSB _u(29) +#define USB_BUFF_STATUS_EP14_OUT_LSB _u(29) +#define USB_BUFF_STATUS_EP14_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP14_IN +#define USB_BUFF_STATUS_EP14_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP14_IN_BITS _u(0x10000000) +#define USB_BUFF_STATUS_EP14_IN_MSB _u(28) +#define USB_BUFF_STATUS_EP14_IN_LSB _u(28) +#define USB_BUFF_STATUS_EP14_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP13_OUT +#define USB_BUFF_STATUS_EP13_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP13_OUT_BITS _u(0x08000000) +#define USB_BUFF_STATUS_EP13_OUT_MSB _u(27) +#define USB_BUFF_STATUS_EP13_OUT_LSB _u(27) +#define USB_BUFF_STATUS_EP13_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP13_IN +#define USB_BUFF_STATUS_EP13_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP13_IN_BITS _u(0x04000000) +#define USB_BUFF_STATUS_EP13_IN_MSB _u(26) +#define USB_BUFF_STATUS_EP13_IN_LSB _u(26) +#define USB_BUFF_STATUS_EP13_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP12_OUT +#define USB_BUFF_STATUS_EP12_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP12_OUT_BITS _u(0x02000000) +#define USB_BUFF_STATUS_EP12_OUT_MSB _u(25) +#define USB_BUFF_STATUS_EP12_OUT_LSB _u(25) +#define USB_BUFF_STATUS_EP12_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP12_IN +#define USB_BUFF_STATUS_EP12_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP12_IN_BITS _u(0x01000000) +#define USB_BUFF_STATUS_EP12_IN_MSB _u(24) +#define USB_BUFF_STATUS_EP12_IN_LSB _u(24) +#define USB_BUFF_STATUS_EP12_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP11_OUT +#define USB_BUFF_STATUS_EP11_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP11_OUT_BITS _u(0x00800000) +#define USB_BUFF_STATUS_EP11_OUT_MSB _u(23) +#define USB_BUFF_STATUS_EP11_OUT_LSB _u(23) +#define USB_BUFF_STATUS_EP11_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP11_IN +#define USB_BUFF_STATUS_EP11_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP11_IN_BITS _u(0x00400000) +#define USB_BUFF_STATUS_EP11_IN_MSB _u(22) +#define USB_BUFF_STATUS_EP11_IN_LSB _u(22) +#define USB_BUFF_STATUS_EP11_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP10_OUT +#define USB_BUFF_STATUS_EP10_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP10_OUT_BITS _u(0x00200000) +#define USB_BUFF_STATUS_EP10_OUT_MSB _u(21) +#define USB_BUFF_STATUS_EP10_OUT_LSB _u(21) +#define USB_BUFF_STATUS_EP10_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP10_IN +#define USB_BUFF_STATUS_EP10_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP10_IN_BITS _u(0x00100000) +#define USB_BUFF_STATUS_EP10_IN_MSB _u(20) +#define USB_BUFF_STATUS_EP10_IN_LSB _u(20) +#define USB_BUFF_STATUS_EP10_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP9_OUT +#define USB_BUFF_STATUS_EP9_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP9_OUT_BITS _u(0x00080000) +#define USB_BUFF_STATUS_EP9_OUT_MSB _u(19) +#define USB_BUFF_STATUS_EP9_OUT_LSB _u(19) +#define USB_BUFF_STATUS_EP9_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP9_IN +#define USB_BUFF_STATUS_EP9_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP9_IN_BITS _u(0x00040000) +#define USB_BUFF_STATUS_EP9_IN_MSB _u(18) +#define USB_BUFF_STATUS_EP9_IN_LSB _u(18) +#define USB_BUFF_STATUS_EP9_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP8_OUT +#define USB_BUFF_STATUS_EP8_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP8_OUT_BITS _u(0x00020000) +#define USB_BUFF_STATUS_EP8_OUT_MSB _u(17) +#define USB_BUFF_STATUS_EP8_OUT_LSB _u(17) +#define USB_BUFF_STATUS_EP8_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP8_IN +#define USB_BUFF_STATUS_EP8_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP8_IN_BITS _u(0x00010000) +#define USB_BUFF_STATUS_EP8_IN_MSB _u(16) +#define USB_BUFF_STATUS_EP8_IN_LSB _u(16) +#define USB_BUFF_STATUS_EP8_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP7_OUT +#define USB_BUFF_STATUS_EP7_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP7_OUT_BITS _u(0x00008000) +#define USB_BUFF_STATUS_EP7_OUT_MSB _u(15) +#define USB_BUFF_STATUS_EP7_OUT_LSB _u(15) +#define USB_BUFF_STATUS_EP7_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP7_IN +#define USB_BUFF_STATUS_EP7_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP7_IN_BITS _u(0x00004000) +#define USB_BUFF_STATUS_EP7_IN_MSB _u(14) +#define USB_BUFF_STATUS_EP7_IN_LSB _u(14) +#define USB_BUFF_STATUS_EP7_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP6_OUT +#define USB_BUFF_STATUS_EP6_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP6_OUT_BITS _u(0x00002000) +#define USB_BUFF_STATUS_EP6_OUT_MSB _u(13) +#define USB_BUFF_STATUS_EP6_OUT_LSB _u(13) +#define USB_BUFF_STATUS_EP6_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP6_IN +#define USB_BUFF_STATUS_EP6_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP6_IN_BITS _u(0x00001000) +#define USB_BUFF_STATUS_EP6_IN_MSB _u(12) +#define USB_BUFF_STATUS_EP6_IN_LSB _u(12) +#define USB_BUFF_STATUS_EP6_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP5_OUT +#define USB_BUFF_STATUS_EP5_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP5_OUT_BITS _u(0x00000800) +#define USB_BUFF_STATUS_EP5_OUT_MSB _u(11) +#define USB_BUFF_STATUS_EP5_OUT_LSB _u(11) +#define USB_BUFF_STATUS_EP5_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP5_IN +#define USB_BUFF_STATUS_EP5_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP5_IN_BITS _u(0x00000400) +#define USB_BUFF_STATUS_EP5_IN_MSB _u(10) +#define USB_BUFF_STATUS_EP5_IN_LSB _u(10) +#define USB_BUFF_STATUS_EP5_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP4_OUT +#define USB_BUFF_STATUS_EP4_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP4_OUT_BITS _u(0x00000200) +#define USB_BUFF_STATUS_EP4_OUT_MSB _u(9) +#define USB_BUFF_STATUS_EP4_OUT_LSB _u(9) +#define USB_BUFF_STATUS_EP4_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP4_IN +#define USB_BUFF_STATUS_EP4_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP4_IN_BITS _u(0x00000100) +#define USB_BUFF_STATUS_EP4_IN_MSB _u(8) +#define USB_BUFF_STATUS_EP4_IN_LSB _u(8) +#define USB_BUFF_STATUS_EP4_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP3_OUT +#define USB_BUFF_STATUS_EP3_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP3_OUT_BITS _u(0x00000080) +#define USB_BUFF_STATUS_EP3_OUT_MSB _u(7) +#define USB_BUFF_STATUS_EP3_OUT_LSB _u(7) +#define USB_BUFF_STATUS_EP3_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP3_IN +#define USB_BUFF_STATUS_EP3_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP3_IN_BITS _u(0x00000040) +#define USB_BUFF_STATUS_EP3_IN_MSB _u(6) +#define USB_BUFF_STATUS_EP3_IN_LSB _u(6) +#define USB_BUFF_STATUS_EP3_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP2_OUT +#define USB_BUFF_STATUS_EP2_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP2_OUT_BITS _u(0x00000020) +#define USB_BUFF_STATUS_EP2_OUT_MSB _u(5) +#define USB_BUFF_STATUS_EP2_OUT_LSB _u(5) +#define USB_BUFF_STATUS_EP2_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP2_IN +#define USB_BUFF_STATUS_EP2_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP2_IN_BITS _u(0x00000010) +#define USB_BUFF_STATUS_EP2_IN_MSB _u(4) +#define USB_BUFF_STATUS_EP2_IN_LSB _u(4) +#define USB_BUFF_STATUS_EP2_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP1_OUT +#define USB_BUFF_STATUS_EP1_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP1_OUT_BITS _u(0x00000008) +#define USB_BUFF_STATUS_EP1_OUT_MSB _u(3) +#define USB_BUFF_STATUS_EP1_OUT_LSB _u(3) +#define USB_BUFF_STATUS_EP1_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP1_IN +#define USB_BUFF_STATUS_EP1_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP1_IN_BITS _u(0x00000004) +#define USB_BUFF_STATUS_EP1_IN_MSB _u(2) +#define USB_BUFF_STATUS_EP1_IN_LSB _u(2) +#define USB_BUFF_STATUS_EP1_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP0_OUT +#define USB_BUFF_STATUS_EP0_OUT_RESET _u(0x0) +#define USB_BUFF_STATUS_EP0_OUT_BITS _u(0x00000002) +#define USB_BUFF_STATUS_EP0_OUT_MSB _u(1) +#define USB_BUFF_STATUS_EP0_OUT_LSB _u(1) +#define USB_BUFF_STATUS_EP0_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_STATUS_EP0_IN +#define USB_BUFF_STATUS_EP0_IN_RESET _u(0x0) +#define USB_BUFF_STATUS_EP0_IN_BITS _u(0x00000001) +#define USB_BUFF_STATUS_EP0_IN_MSB _u(0) +#define USB_BUFF_STATUS_EP0_IN_LSB _u(0) +#define USB_BUFF_STATUS_EP0_IN_ACCESS "WC" +// ============================================================================= +// Register : USB_BUFF_CPU_SHOULD_HANDLE +// Description : Which of the double buffers should be handled. Only valid if +// using an interrupt per buffer (i.e. not per 2 buffers). Not +// valid for host interrupt endpoint polling because they are only +// single buffered. +#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET _u(0x0000005c) +#define USB_BUFF_CPU_SHOULD_HANDLE_BITS _u(0xffffffff) +#define USB_BUFF_CPU_SHOULD_HANDLE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS _u(0x80000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB _u(31) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB _u(31) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS _u(0x40000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB _u(30) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB _u(30) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS _u(0x20000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB _u(29) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB _u(29) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS _u(0x10000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB _u(28) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB _u(28) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS _u(0x08000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB _u(27) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB _u(27) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS _u(0x04000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB _u(26) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB _u(26) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS _u(0x02000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB _u(25) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB _u(25) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS _u(0x01000000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB _u(24) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB _u(24) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS _u(0x00800000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB _u(23) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB _u(23) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS _u(0x00400000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB _u(22) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB _u(22) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS _u(0x00200000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB _u(21) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB _u(21) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS _u(0x00100000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB _u(20) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB _u(20) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS _u(0x00080000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB _u(19) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB _u(19) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS _u(0x00040000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB _u(18) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB _u(18) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS _u(0x00020000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB _u(17) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB _u(17) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS _u(0x00010000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB _u(16) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB _u(16) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS _u(0x00008000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB _u(15) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB _u(15) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS _u(0x00004000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB _u(14) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB _u(14) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS _u(0x00002000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB _u(13) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB _u(13) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS _u(0x00001000) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB _u(12) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB _u(12) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS _u(0x00000800) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB _u(11) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB _u(11) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS _u(0x00000400) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB _u(10) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB _u(10) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS _u(0x00000200) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB _u(9) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB _u(9) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS _u(0x00000100) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB _u(8) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB _u(8) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS _u(0x00000080) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB _u(7) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB _u(7) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS _u(0x00000040) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB _u(6) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB _u(6) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS _u(0x00000020) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB _u(5) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB _u(5) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS _u(0x00000010) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB _u(4) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB _u(4) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS _u(0x00000008) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB _u(3) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB _u(3) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS _u(0x00000004) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB _u(2) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB _u(2) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS _u(0x00000002) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB _u(1) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB _u(1) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET _u(0x0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS _u(0x00000001) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB _u(0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB _u(0) +#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_ACCESS "RO" +// ============================================================================= +// Register : USB_EP_ABORT +// Description : Device only: Can be set to ignore the buffer control register +// for this endpoint in case you would like to revoke a buffer. A +// NAK will be sent for every access to the endpoint until this +// bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set +// when it is safe to modify the buffer control register. +#define USB_EP_ABORT_OFFSET _u(0x00000060) +#define USB_EP_ABORT_BITS _u(0xffffffff) +#define USB_EP_ABORT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP15_OUT +#define USB_EP_ABORT_EP15_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP15_OUT_BITS _u(0x80000000) +#define USB_EP_ABORT_EP15_OUT_MSB _u(31) +#define USB_EP_ABORT_EP15_OUT_LSB _u(31) +#define USB_EP_ABORT_EP15_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP15_IN +#define USB_EP_ABORT_EP15_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP15_IN_BITS _u(0x40000000) +#define USB_EP_ABORT_EP15_IN_MSB _u(30) +#define USB_EP_ABORT_EP15_IN_LSB _u(30) +#define USB_EP_ABORT_EP15_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP14_OUT +#define USB_EP_ABORT_EP14_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP14_OUT_BITS _u(0x20000000) +#define USB_EP_ABORT_EP14_OUT_MSB _u(29) +#define USB_EP_ABORT_EP14_OUT_LSB _u(29) +#define USB_EP_ABORT_EP14_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP14_IN +#define USB_EP_ABORT_EP14_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP14_IN_BITS _u(0x10000000) +#define USB_EP_ABORT_EP14_IN_MSB _u(28) +#define USB_EP_ABORT_EP14_IN_LSB _u(28) +#define USB_EP_ABORT_EP14_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP13_OUT +#define USB_EP_ABORT_EP13_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP13_OUT_BITS _u(0x08000000) +#define USB_EP_ABORT_EP13_OUT_MSB _u(27) +#define USB_EP_ABORT_EP13_OUT_LSB _u(27) +#define USB_EP_ABORT_EP13_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP13_IN +#define USB_EP_ABORT_EP13_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP13_IN_BITS _u(0x04000000) +#define USB_EP_ABORT_EP13_IN_MSB _u(26) +#define USB_EP_ABORT_EP13_IN_LSB _u(26) +#define USB_EP_ABORT_EP13_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP12_OUT +#define USB_EP_ABORT_EP12_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP12_OUT_BITS _u(0x02000000) +#define USB_EP_ABORT_EP12_OUT_MSB _u(25) +#define USB_EP_ABORT_EP12_OUT_LSB _u(25) +#define USB_EP_ABORT_EP12_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP12_IN +#define USB_EP_ABORT_EP12_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP12_IN_BITS _u(0x01000000) +#define USB_EP_ABORT_EP12_IN_MSB _u(24) +#define USB_EP_ABORT_EP12_IN_LSB _u(24) +#define USB_EP_ABORT_EP12_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP11_OUT +#define USB_EP_ABORT_EP11_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP11_OUT_BITS _u(0x00800000) +#define USB_EP_ABORT_EP11_OUT_MSB _u(23) +#define USB_EP_ABORT_EP11_OUT_LSB _u(23) +#define USB_EP_ABORT_EP11_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP11_IN +#define USB_EP_ABORT_EP11_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP11_IN_BITS _u(0x00400000) +#define USB_EP_ABORT_EP11_IN_MSB _u(22) +#define USB_EP_ABORT_EP11_IN_LSB _u(22) +#define USB_EP_ABORT_EP11_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP10_OUT +#define USB_EP_ABORT_EP10_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP10_OUT_BITS _u(0x00200000) +#define USB_EP_ABORT_EP10_OUT_MSB _u(21) +#define USB_EP_ABORT_EP10_OUT_LSB _u(21) +#define USB_EP_ABORT_EP10_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP10_IN +#define USB_EP_ABORT_EP10_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP10_IN_BITS _u(0x00100000) +#define USB_EP_ABORT_EP10_IN_MSB _u(20) +#define USB_EP_ABORT_EP10_IN_LSB _u(20) +#define USB_EP_ABORT_EP10_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP9_OUT +#define USB_EP_ABORT_EP9_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP9_OUT_BITS _u(0x00080000) +#define USB_EP_ABORT_EP9_OUT_MSB _u(19) +#define USB_EP_ABORT_EP9_OUT_LSB _u(19) +#define USB_EP_ABORT_EP9_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP9_IN +#define USB_EP_ABORT_EP9_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP9_IN_BITS _u(0x00040000) +#define USB_EP_ABORT_EP9_IN_MSB _u(18) +#define USB_EP_ABORT_EP9_IN_LSB _u(18) +#define USB_EP_ABORT_EP9_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP8_OUT +#define USB_EP_ABORT_EP8_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP8_OUT_BITS _u(0x00020000) +#define USB_EP_ABORT_EP8_OUT_MSB _u(17) +#define USB_EP_ABORT_EP8_OUT_LSB _u(17) +#define USB_EP_ABORT_EP8_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP8_IN +#define USB_EP_ABORT_EP8_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP8_IN_BITS _u(0x00010000) +#define USB_EP_ABORT_EP8_IN_MSB _u(16) +#define USB_EP_ABORT_EP8_IN_LSB _u(16) +#define USB_EP_ABORT_EP8_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP7_OUT +#define USB_EP_ABORT_EP7_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP7_OUT_BITS _u(0x00008000) +#define USB_EP_ABORT_EP7_OUT_MSB _u(15) +#define USB_EP_ABORT_EP7_OUT_LSB _u(15) +#define USB_EP_ABORT_EP7_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP7_IN +#define USB_EP_ABORT_EP7_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP7_IN_BITS _u(0x00004000) +#define USB_EP_ABORT_EP7_IN_MSB _u(14) +#define USB_EP_ABORT_EP7_IN_LSB _u(14) +#define USB_EP_ABORT_EP7_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP6_OUT +#define USB_EP_ABORT_EP6_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP6_OUT_BITS _u(0x00002000) +#define USB_EP_ABORT_EP6_OUT_MSB _u(13) +#define USB_EP_ABORT_EP6_OUT_LSB _u(13) +#define USB_EP_ABORT_EP6_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP6_IN +#define USB_EP_ABORT_EP6_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP6_IN_BITS _u(0x00001000) +#define USB_EP_ABORT_EP6_IN_MSB _u(12) +#define USB_EP_ABORT_EP6_IN_LSB _u(12) +#define USB_EP_ABORT_EP6_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP5_OUT +#define USB_EP_ABORT_EP5_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP5_OUT_BITS _u(0x00000800) +#define USB_EP_ABORT_EP5_OUT_MSB _u(11) +#define USB_EP_ABORT_EP5_OUT_LSB _u(11) +#define USB_EP_ABORT_EP5_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP5_IN +#define USB_EP_ABORT_EP5_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP5_IN_BITS _u(0x00000400) +#define USB_EP_ABORT_EP5_IN_MSB _u(10) +#define USB_EP_ABORT_EP5_IN_LSB _u(10) +#define USB_EP_ABORT_EP5_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP4_OUT +#define USB_EP_ABORT_EP4_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP4_OUT_BITS _u(0x00000200) +#define USB_EP_ABORT_EP4_OUT_MSB _u(9) +#define USB_EP_ABORT_EP4_OUT_LSB _u(9) +#define USB_EP_ABORT_EP4_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP4_IN +#define USB_EP_ABORT_EP4_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP4_IN_BITS _u(0x00000100) +#define USB_EP_ABORT_EP4_IN_MSB _u(8) +#define USB_EP_ABORT_EP4_IN_LSB _u(8) +#define USB_EP_ABORT_EP4_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP3_OUT +#define USB_EP_ABORT_EP3_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP3_OUT_BITS _u(0x00000080) +#define USB_EP_ABORT_EP3_OUT_MSB _u(7) +#define USB_EP_ABORT_EP3_OUT_LSB _u(7) +#define USB_EP_ABORT_EP3_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP3_IN +#define USB_EP_ABORT_EP3_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP3_IN_BITS _u(0x00000040) +#define USB_EP_ABORT_EP3_IN_MSB _u(6) +#define USB_EP_ABORT_EP3_IN_LSB _u(6) +#define USB_EP_ABORT_EP3_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP2_OUT +#define USB_EP_ABORT_EP2_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP2_OUT_BITS _u(0x00000020) +#define USB_EP_ABORT_EP2_OUT_MSB _u(5) +#define USB_EP_ABORT_EP2_OUT_LSB _u(5) +#define USB_EP_ABORT_EP2_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP2_IN +#define USB_EP_ABORT_EP2_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP2_IN_BITS _u(0x00000010) +#define USB_EP_ABORT_EP2_IN_MSB _u(4) +#define USB_EP_ABORT_EP2_IN_LSB _u(4) +#define USB_EP_ABORT_EP2_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP1_OUT +#define USB_EP_ABORT_EP1_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP1_OUT_BITS _u(0x00000008) +#define USB_EP_ABORT_EP1_OUT_MSB _u(3) +#define USB_EP_ABORT_EP1_OUT_LSB _u(3) +#define USB_EP_ABORT_EP1_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP1_IN +#define USB_EP_ABORT_EP1_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP1_IN_BITS _u(0x00000004) +#define USB_EP_ABORT_EP1_IN_MSB _u(2) +#define USB_EP_ABORT_EP1_IN_LSB _u(2) +#define USB_EP_ABORT_EP1_IN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP0_OUT +#define USB_EP_ABORT_EP0_OUT_RESET _u(0x0) +#define USB_EP_ABORT_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_ABORT_EP0_OUT_MSB _u(1) +#define USB_EP_ABORT_EP0_OUT_LSB _u(1) +#define USB_EP_ABORT_EP0_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_EP0_IN +#define USB_EP_ABORT_EP0_IN_RESET _u(0x0) +#define USB_EP_ABORT_EP0_IN_BITS _u(0x00000001) +#define USB_EP_ABORT_EP0_IN_MSB _u(0) +#define USB_EP_ABORT_EP0_IN_LSB _u(0) +#define USB_EP_ABORT_EP0_IN_ACCESS "RW" +// ============================================================================= +// Register : USB_EP_ABORT_DONE +// Description : Device only: Used in conjunction with `EP_ABORT`. Set once an +// endpoint is idle so the programmer knows it is safe to modify +// the buffer control register. +#define USB_EP_ABORT_DONE_OFFSET _u(0x00000064) +#define USB_EP_ABORT_DONE_BITS _u(0xffffffff) +#define USB_EP_ABORT_DONE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP15_OUT +#define USB_EP_ABORT_DONE_EP15_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP15_OUT_BITS _u(0x80000000) +#define USB_EP_ABORT_DONE_EP15_OUT_MSB _u(31) +#define USB_EP_ABORT_DONE_EP15_OUT_LSB _u(31) +#define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP15_IN +#define USB_EP_ABORT_DONE_EP15_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP15_IN_BITS _u(0x40000000) +#define USB_EP_ABORT_DONE_EP15_IN_MSB _u(30) +#define USB_EP_ABORT_DONE_EP15_IN_LSB _u(30) +#define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP14_OUT +#define USB_EP_ABORT_DONE_EP14_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP14_OUT_BITS _u(0x20000000) +#define USB_EP_ABORT_DONE_EP14_OUT_MSB _u(29) +#define USB_EP_ABORT_DONE_EP14_OUT_LSB _u(29) +#define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP14_IN +#define USB_EP_ABORT_DONE_EP14_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP14_IN_BITS _u(0x10000000) +#define USB_EP_ABORT_DONE_EP14_IN_MSB _u(28) +#define USB_EP_ABORT_DONE_EP14_IN_LSB _u(28) +#define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP13_OUT +#define USB_EP_ABORT_DONE_EP13_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP13_OUT_BITS _u(0x08000000) +#define USB_EP_ABORT_DONE_EP13_OUT_MSB _u(27) +#define USB_EP_ABORT_DONE_EP13_OUT_LSB _u(27) +#define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP13_IN +#define USB_EP_ABORT_DONE_EP13_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP13_IN_BITS _u(0x04000000) +#define USB_EP_ABORT_DONE_EP13_IN_MSB _u(26) +#define USB_EP_ABORT_DONE_EP13_IN_LSB _u(26) +#define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP12_OUT +#define USB_EP_ABORT_DONE_EP12_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP12_OUT_BITS _u(0x02000000) +#define USB_EP_ABORT_DONE_EP12_OUT_MSB _u(25) +#define USB_EP_ABORT_DONE_EP12_OUT_LSB _u(25) +#define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP12_IN +#define USB_EP_ABORT_DONE_EP12_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP12_IN_BITS _u(0x01000000) +#define USB_EP_ABORT_DONE_EP12_IN_MSB _u(24) +#define USB_EP_ABORT_DONE_EP12_IN_LSB _u(24) +#define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP11_OUT +#define USB_EP_ABORT_DONE_EP11_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP11_OUT_BITS _u(0x00800000) +#define USB_EP_ABORT_DONE_EP11_OUT_MSB _u(23) +#define USB_EP_ABORT_DONE_EP11_OUT_LSB _u(23) +#define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP11_IN +#define USB_EP_ABORT_DONE_EP11_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP11_IN_BITS _u(0x00400000) +#define USB_EP_ABORT_DONE_EP11_IN_MSB _u(22) +#define USB_EP_ABORT_DONE_EP11_IN_LSB _u(22) +#define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP10_OUT +#define USB_EP_ABORT_DONE_EP10_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP10_OUT_BITS _u(0x00200000) +#define USB_EP_ABORT_DONE_EP10_OUT_MSB _u(21) +#define USB_EP_ABORT_DONE_EP10_OUT_LSB _u(21) +#define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP10_IN +#define USB_EP_ABORT_DONE_EP10_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP10_IN_BITS _u(0x00100000) +#define USB_EP_ABORT_DONE_EP10_IN_MSB _u(20) +#define USB_EP_ABORT_DONE_EP10_IN_LSB _u(20) +#define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP9_OUT +#define USB_EP_ABORT_DONE_EP9_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP9_OUT_BITS _u(0x00080000) +#define USB_EP_ABORT_DONE_EP9_OUT_MSB _u(19) +#define USB_EP_ABORT_DONE_EP9_OUT_LSB _u(19) +#define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP9_IN +#define USB_EP_ABORT_DONE_EP9_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP9_IN_BITS _u(0x00040000) +#define USB_EP_ABORT_DONE_EP9_IN_MSB _u(18) +#define USB_EP_ABORT_DONE_EP9_IN_LSB _u(18) +#define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP8_OUT +#define USB_EP_ABORT_DONE_EP8_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP8_OUT_BITS _u(0x00020000) +#define USB_EP_ABORT_DONE_EP8_OUT_MSB _u(17) +#define USB_EP_ABORT_DONE_EP8_OUT_LSB _u(17) +#define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP8_IN +#define USB_EP_ABORT_DONE_EP8_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP8_IN_BITS _u(0x00010000) +#define USB_EP_ABORT_DONE_EP8_IN_MSB _u(16) +#define USB_EP_ABORT_DONE_EP8_IN_LSB _u(16) +#define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP7_OUT +#define USB_EP_ABORT_DONE_EP7_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP7_OUT_BITS _u(0x00008000) +#define USB_EP_ABORT_DONE_EP7_OUT_MSB _u(15) +#define USB_EP_ABORT_DONE_EP7_OUT_LSB _u(15) +#define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP7_IN +#define USB_EP_ABORT_DONE_EP7_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP7_IN_BITS _u(0x00004000) +#define USB_EP_ABORT_DONE_EP7_IN_MSB _u(14) +#define USB_EP_ABORT_DONE_EP7_IN_LSB _u(14) +#define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP6_OUT +#define USB_EP_ABORT_DONE_EP6_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP6_OUT_BITS _u(0x00002000) +#define USB_EP_ABORT_DONE_EP6_OUT_MSB _u(13) +#define USB_EP_ABORT_DONE_EP6_OUT_LSB _u(13) +#define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP6_IN +#define USB_EP_ABORT_DONE_EP6_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP6_IN_BITS _u(0x00001000) +#define USB_EP_ABORT_DONE_EP6_IN_MSB _u(12) +#define USB_EP_ABORT_DONE_EP6_IN_LSB _u(12) +#define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP5_OUT +#define USB_EP_ABORT_DONE_EP5_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP5_OUT_BITS _u(0x00000800) +#define USB_EP_ABORT_DONE_EP5_OUT_MSB _u(11) +#define USB_EP_ABORT_DONE_EP5_OUT_LSB _u(11) +#define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP5_IN +#define USB_EP_ABORT_DONE_EP5_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP5_IN_BITS _u(0x00000400) +#define USB_EP_ABORT_DONE_EP5_IN_MSB _u(10) +#define USB_EP_ABORT_DONE_EP5_IN_LSB _u(10) +#define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP4_OUT +#define USB_EP_ABORT_DONE_EP4_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP4_OUT_BITS _u(0x00000200) +#define USB_EP_ABORT_DONE_EP4_OUT_MSB _u(9) +#define USB_EP_ABORT_DONE_EP4_OUT_LSB _u(9) +#define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP4_IN +#define USB_EP_ABORT_DONE_EP4_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP4_IN_BITS _u(0x00000100) +#define USB_EP_ABORT_DONE_EP4_IN_MSB _u(8) +#define USB_EP_ABORT_DONE_EP4_IN_LSB _u(8) +#define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP3_OUT +#define USB_EP_ABORT_DONE_EP3_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP3_OUT_BITS _u(0x00000080) +#define USB_EP_ABORT_DONE_EP3_OUT_MSB _u(7) +#define USB_EP_ABORT_DONE_EP3_OUT_LSB _u(7) +#define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP3_IN +#define USB_EP_ABORT_DONE_EP3_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP3_IN_BITS _u(0x00000040) +#define USB_EP_ABORT_DONE_EP3_IN_MSB _u(6) +#define USB_EP_ABORT_DONE_EP3_IN_LSB _u(6) +#define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP2_OUT +#define USB_EP_ABORT_DONE_EP2_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP2_OUT_BITS _u(0x00000020) +#define USB_EP_ABORT_DONE_EP2_OUT_MSB _u(5) +#define USB_EP_ABORT_DONE_EP2_OUT_LSB _u(5) +#define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP2_IN +#define USB_EP_ABORT_DONE_EP2_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP2_IN_BITS _u(0x00000010) +#define USB_EP_ABORT_DONE_EP2_IN_MSB _u(4) +#define USB_EP_ABORT_DONE_EP2_IN_LSB _u(4) +#define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP1_OUT +#define USB_EP_ABORT_DONE_EP1_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP1_OUT_BITS _u(0x00000008) +#define USB_EP_ABORT_DONE_EP1_OUT_MSB _u(3) +#define USB_EP_ABORT_DONE_EP1_OUT_LSB _u(3) +#define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP1_IN +#define USB_EP_ABORT_DONE_EP1_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP1_IN_BITS _u(0x00000004) +#define USB_EP_ABORT_DONE_EP1_IN_MSB _u(2) +#define USB_EP_ABORT_DONE_EP1_IN_LSB _u(2) +#define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP0_OUT +#define USB_EP_ABORT_DONE_EP0_OUT_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_ABORT_DONE_EP0_OUT_MSB _u(1) +#define USB_EP_ABORT_DONE_EP0_OUT_LSB _u(1) +#define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_ABORT_DONE_EP0_IN +#define USB_EP_ABORT_DONE_EP0_IN_RESET _u(0x0) +#define USB_EP_ABORT_DONE_EP0_IN_BITS _u(0x00000001) +#define USB_EP_ABORT_DONE_EP0_IN_MSB _u(0) +#define USB_EP_ABORT_DONE_EP0_IN_LSB _u(0) +#define USB_EP_ABORT_DONE_EP0_IN_ACCESS "WC" +// ============================================================================= +// Register : USB_EP_STALL_ARM +// Description : Device: this bit must be set in conjunction with the `STALL` +// bit in the buffer control register to send a STALL on EP0. The +// device controller clears these bits when a SETUP packet is +// received because the USB spec requires that a STALL condition +// is cleared when a SETUP packet is received. +#define USB_EP_STALL_ARM_OFFSET _u(0x00000068) +#define USB_EP_STALL_ARM_BITS _u(0x00000003) +#define USB_EP_STALL_ARM_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_EP_STALL_ARM_EP0_OUT +#define USB_EP_STALL_ARM_EP0_OUT_RESET _u(0x0) +#define USB_EP_STALL_ARM_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_STALL_ARM_EP0_OUT_MSB _u(1) +#define USB_EP_STALL_ARM_EP0_OUT_LSB _u(1) +#define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STALL_ARM_EP0_IN +#define USB_EP_STALL_ARM_EP0_IN_RESET _u(0x0) +#define USB_EP_STALL_ARM_EP0_IN_BITS _u(0x00000001) +#define USB_EP_STALL_ARM_EP0_IN_MSB _u(0) +#define USB_EP_STALL_ARM_EP0_IN_LSB _u(0) +#define USB_EP_STALL_ARM_EP0_IN_ACCESS "RW" +// ============================================================================= +// Register : USB_NAK_POLL +// Description : Used by the host controller. Sets the wait time in microseconds +// before trying again if the device replies with a NAK. +#define USB_NAK_POLL_OFFSET _u(0x0000006c) +#define USB_NAK_POLL_BITS _u(0xffffffff) +#define USB_NAK_POLL_RESET _u(0x00100010) +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_RETRY_COUNT_HI +// Description : Bits 9:6 of nak_retry count +#define USB_NAK_POLL_RETRY_COUNT_HI_RESET _u(0x0) +#define USB_NAK_POLL_RETRY_COUNT_HI_BITS _u(0xf0000000) +#define USB_NAK_POLL_RETRY_COUNT_HI_MSB _u(31) +#define USB_NAK_POLL_RETRY_COUNT_HI_LSB _u(28) +#define USB_NAK_POLL_RETRY_COUNT_HI_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_EPX_STOPPED_ON_NAK +// Description : EPX polling has stopped because a nak was received +#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_RESET _u(0x0) +#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_BITS _u(0x08000000) +#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_MSB _u(27) +#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_LSB _u(27) +#define USB_NAK_POLL_EPX_STOPPED_ON_NAK_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_STOP_EPX_ON_NAK +// Description : Stop polling epx when a nak is received +#define USB_NAK_POLL_STOP_EPX_ON_NAK_RESET _u(0x0) +#define USB_NAK_POLL_STOP_EPX_ON_NAK_BITS _u(0x04000000) +#define USB_NAK_POLL_STOP_EPX_ON_NAK_MSB _u(26) +#define USB_NAK_POLL_STOP_EPX_ON_NAK_LSB _u(26) +#define USB_NAK_POLL_STOP_EPX_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_DELAY_FS +// Description : NAK polling interval for a full speed device +#define USB_NAK_POLL_DELAY_FS_RESET _u(0x010) +#define USB_NAK_POLL_DELAY_FS_BITS _u(0x03ff0000) +#define USB_NAK_POLL_DELAY_FS_MSB _u(25) +#define USB_NAK_POLL_DELAY_FS_LSB _u(16) +#define USB_NAK_POLL_DELAY_FS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_RETRY_COUNT_LO +// Description : Bits 5:0 of nak_retry_count +#define USB_NAK_POLL_RETRY_COUNT_LO_RESET _u(0x00) +#define USB_NAK_POLL_RETRY_COUNT_LO_BITS _u(0x0000fc00) +#define USB_NAK_POLL_RETRY_COUNT_LO_MSB _u(15) +#define USB_NAK_POLL_RETRY_COUNT_LO_LSB _u(10) +#define USB_NAK_POLL_RETRY_COUNT_LO_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_NAK_POLL_DELAY_LS +// Description : NAK polling interval for a low speed device +#define USB_NAK_POLL_DELAY_LS_RESET _u(0x010) +#define USB_NAK_POLL_DELAY_LS_BITS _u(0x000003ff) +#define USB_NAK_POLL_DELAY_LS_MSB _u(9) +#define USB_NAK_POLL_DELAY_LS_LSB _u(0) +#define USB_NAK_POLL_DELAY_LS_ACCESS "RW" +// ============================================================================= +// Register : USB_EP_STATUS_STALL_NAK +// Description : Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` +// bits are set. For EP0 this comes from `SIE_CTRL`. For all other +// endpoints it comes from the endpoint control register. +#define USB_EP_STATUS_STALL_NAK_OFFSET _u(0x00000070) +#define USB_EP_STATUS_STALL_NAK_BITS _u(0xffffffff) +#define USB_EP_STATUS_STALL_NAK_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP15_OUT +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS _u(0x80000000) +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB _u(31) +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB _u(31) +#define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP15_IN +#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS _u(0x40000000) +#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB _u(30) +#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB _u(30) +#define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP14_OUT +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS _u(0x20000000) +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB _u(29) +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB _u(29) +#define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP14_IN +#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS _u(0x10000000) +#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB _u(28) +#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB _u(28) +#define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP13_OUT +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS _u(0x08000000) +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB _u(27) +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB _u(27) +#define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP13_IN +#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS _u(0x04000000) +#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB _u(26) +#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB _u(26) +#define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP12_OUT +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS _u(0x02000000) +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB _u(25) +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB _u(25) +#define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP12_IN +#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS _u(0x01000000) +#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB _u(24) +#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB _u(24) +#define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP11_OUT +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS _u(0x00800000) +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB _u(23) +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB _u(23) +#define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP11_IN +#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS _u(0x00400000) +#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB _u(22) +#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB _u(22) +#define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP10_OUT +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS _u(0x00200000) +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB _u(21) +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB _u(21) +#define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP10_IN +#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS _u(0x00100000) +#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB _u(20) +#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB _u(20) +#define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP9_OUT +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS _u(0x00080000) +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB _u(19) +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB _u(19) +#define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP9_IN +#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS _u(0x00040000) +#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB _u(18) +#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB _u(18) +#define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP8_OUT +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS _u(0x00020000) +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB _u(17) +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB _u(17) +#define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP8_IN +#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS _u(0x00010000) +#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB _u(16) +#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB _u(16) +#define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP7_OUT +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS _u(0x00008000) +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB _u(15) +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB _u(15) +#define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP7_IN +#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS _u(0x00004000) +#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB _u(14) +#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB _u(14) +#define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP6_OUT +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS _u(0x00002000) +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB _u(13) +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB _u(13) +#define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP6_IN +#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS _u(0x00001000) +#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB _u(12) +#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB _u(12) +#define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP5_OUT +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS _u(0x00000800) +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB _u(11) +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB _u(11) +#define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP5_IN +#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS _u(0x00000400) +#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB _u(10) +#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB _u(10) +#define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP4_OUT +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS _u(0x00000200) +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB _u(9) +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB _u(9) +#define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP4_IN +#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS _u(0x00000100) +#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB _u(8) +#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB _u(8) +#define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP3_OUT +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS _u(0x00000080) +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB _u(7) +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB _u(7) +#define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP3_IN +#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS _u(0x00000040) +#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB _u(6) +#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB _u(6) +#define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP2_OUT +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS _u(0x00000020) +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB _u(5) +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB _u(5) +#define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP2_IN +#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS _u(0x00000010) +#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB _u(4) +#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB _u(4) +#define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP1_OUT +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS _u(0x00000008) +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB _u(3) +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB _u(3) +#define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP1_IN +#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS _u(0x00000004) +#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB _u(2) +#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB _u(2) +#define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP0_OUT +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS _u(0x00000002) +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB _u(1) +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB _u(1) +#define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_STATUS_STALL_NAK_EP0_IN +#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET _u(0x0) +#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS _u(0x00000001) +#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB _u(0) +#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB _u(0) +#define USB_EP_STATUS_STALL_NAK_EP0_IN_ACCESS "WC" +// ============================================================================= +// Register : USB_USB_MUXING +// Description : Where to connect the USB controller. Should be to_phy by +// default. +#define USB_USB_MUXING_OFFSET _u(0x00000074) +#define USB_USB_MUXING_BITS _u(0x8000001f) +#define USB_USB_MUXING_RESET _u(0x00000001) +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_SWAP_DPDM +// Description : Swap the USB PHY DP and DM pins and all related controls and +// flip receive differential data. Can be used to switch USB DP/DP +// on the PCB. +// This is done at a low level so overrides all other controls. +#define USB_USB_MUXING_SWAP_DPDM_RESET _u(0x0) +#define USB_USB_MUXING_SWAP_DPDM_BITS _u(0x80000000) +#define USB_USB_MUXING_SWAP_DPDM_MSB _u(31) +#define USB_USB_MUXING_SWAP_DPDM_LSB _u(31) +#define USB_USB_MUXING_SWAP_DPDM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_USBPHY_AS_GPIO +// Description : Use the usb DP and DM pins as GPIO pins instead of connecting +// them to the USB controller. +#define USB_USB_MUXING_USBPHY_AS_GPIO_RESET _u(0x0) +#define USB_USB_MUXING_USBPHY_AS_GPIO_BITS _u(0x00000010) +#define USB_USB_MUXING_USBPHY_AS_GPIO_MSB _u(4) +#define USB_USB_MUXING_USBPHY_AS_GPIO_LSB _u(4) +#define USB_USB_MUXING_USBPHY_AS_GPIO_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_SOFTCON +#define USB_USB_MUXING_SOFTCON_RESET _u(0x0) +#define USB_USB_MUXING_SOFTCON_BITS _u(0x00000008) +#define USB_USB_MUXING_SOFTCON_MSB _u(3) +#define USB_USB_MUXING_SOFTCON_LSB _u(3) +#define USB_USB_MUXING_SOFTCON_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_TO_DIGITAL_PAD +#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET _u(0x0) +#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS _u(0x00000004) +#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB _u(2) +#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB _u(2) +#define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_TO_EXTPHY +#define USB_USB_MUXING_TO_EXTPHY_RESET _u(0x0) +#define USB_USB_MUXING_TO_EXTPHY_BITS _u(0x00000002) +#define USB_USB_MUXING_TO_EXTPHY_MSB _u(1) +#define USB_USB_MUXING_TO_EXTPHY_LSB _u(1) +#define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_MUXING_TO_PHY +#define USB_USB_MUXING_TO_PHY_RESET _u(0x1) +#define USB_USB_MUXING_TO_PHY_BITS _u(0x00000001) +#define USB_USB_MUXING_TO_PHY_MSB _u(0) +#define USB_USB_MUXING_TO_PHY_LSB _u(0) +#define USB_USB_MUXING_TO_PHY_ACCESS "RW" +// ============================================================================= +// Register : USB_USB_PWR +// Description : Overrides for the power signals in the event that the VBUS +// signals are not hooked up to GPIO. Set the value of the +// override and then the override enable to switch over to the +// override value. +#define USB_USB_PWR_OFFSET _u(0x00000078) +#define USB_USB_PWR_BITS _u(0x0000003f) +#define USB_USB_PWR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_OVERCURR_DETECT_EN +#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET _u(0x0) +#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS _u(0x00000020) +#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB _u(5) +#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB _u(5) +#define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_OVERCURR_DETECT +#define USB_USB_PWR_OVERCURR_DETECT_RESET _u(0x0) +#define USB_USB_PWR_OVERCURR_DETECT_BITS _u(0x00000010) +#define USB_USB_PWR_OVERCURR_DETECT_MSB _u(4) +#define USB_USB_PWR_OVERCURR_DETECT_LSB _u(4) +#define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET _u(0x0) +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS _u(0x00000008) +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB _u(3) +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB _u(3) +#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_DETECT +#define USB_USB_PWR_VBUS_DETECT_RESET _u(0x0) +#define USB_USB_PWR_VBUS_DETECT_BITS _u(0x00000004) +#define USB_USB_PWR_VBUS_DETECT_MSB _u(2) +#define USB_USB_PWR_VBUS_DETECT_LSB _u(2) +#define USB_USB_PWR_VBUS_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_EN_OVERRIDE_EN +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS _u(0x00000002) +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB _u(1) +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB _u(1) +#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USB_PWR_VBUS_EN +#define USB_USB_PWR_VBUS_EN_RESET _u(0x0) +#define USB_USB_PWR_VBUS_EN_BITS _u(0x00000001) +#define USB_USB_PWR_VBUS_EN_MSB _u(0) +#define USB_USB_PWR_VBUS_EN_LSB _u(0) +#define USB_USB_PWR_VBUS_EN_ACCESS "RW" +// ============================================================================= +// Register : USB_USBPHY_DIRECT +// Description : This register allows for direct control of the USB phy. Use in +// conjunction with usbphy_direct_override register to enable each +// override bit. +#define USB_USBPHY_DIRECT_OFFSET _u(0x0000007c) +#define USB_USBPHY_DIRECT_BITS _u(0x03ffff77) +#define USB_USBPHY_DIRECT_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DM_OVERRIDE +// Description : Override rx_dm value into controller +#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_BITS _u(0x02000000) +#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_MSB _u(25) +#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_LSB _u(25) +#define USB_USBPHY_DIRECT_RX_DM_OVERRIDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DP_OVERRIDE +// Description : Override rx_dp value into controller +#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_BITS _u(0x01000000) +#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_MSB _u(24) +#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_LSB _u(24) +#define USB_USBPHY_DIRECT_RX_DP_OVERRIDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DD_OVERRIDE +// Description : Override rx_dd value into controller +#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_BITS _u(0x00800000) +#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_MSB _u(23) +#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_LSB _u(23) +#define USB_USBPHY_DIRECT_RX_DD_OVERRIDE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_OVV +// Description : DM over voltage +#define USB_USBPHY_DIRECT_DM_OVV_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_OVV_BITS _u(0x00400000) +#define USB_USBPHY_DIRECT_DM_OVV_MSB _u(22) +#define USB_USBPHY_DIRECT_DM_OVV_LSB _u(22) +#define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_OVV +// Description : DP over voltage +#define USB_USBPHY_DIRECT_DP_OVV_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_OVV_BITS _u(0x00200000) +#define USB_USBPHY_DIRECT_DP_OVV_MSB _u(21) +#define USB_USBPHY_DIRECT_DP_OVV_LSB _u(21) +#define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_OVCN +// Description : DM overcurrent +#define USB_USBPHY_DIRECT_DM_OVCN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_OVCN_BITS _u(0x00100000) +#define USB_USBPHY_DIRECT_DM_OVCN_MSB _u(20) +#define USB_USBPHY_DIRECT_DM_OVCN_LSB _u(20) +#define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_OVCN +// Description : DP overcurrent +#define USB_USBPHY_DIRECT_DP_OVCN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_OVCN_BITS _u(0x00080000) +#define USB_USBPHY_DIRECT_DP_OVCN_MSB _u(19) +#define USB_USBPHY_DIRECT_DP_OVCN_LSB _u(19) +#define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DM +// Description : DPM pin state +#define USB_USBPHY_DIRECT_RX_DM_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DM_BITS _u(0x00040000) +#define USB_USBPHY_DIRECT_RX_DM_MSB _u(18) +#define USB_USBPHY_DIRECT_RX_DM_LSB _u(18) +#define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DP +// Description : DPP pin state +#define USB_USBPHY_DIRECT_RX_DP_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DP_BITS _u(0x00020000) +#define USB_USBPHY_DIRECT_RX_DP_MSB _u(17) +#define USB_USBPHY_DIRECT_RX_DP_LSB _u(17) +#define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_DD +// Description : Differential RX +#define USB_USBPHY_DIRECT_RX_DD_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_DD_BITS _u(0x00010000) +#define USB_USBPHY_DIRECT_RX_DD_MSB _u(16) +#define USB_USBPHY_DIRECT_RX_DD_LSB _u(16) +#define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DIFFMODE +// Description : TX_DIFFMODE=0: Single ended mode +// TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE +// ignored) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS _u(0x00008000) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB _u(15) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB _u(15) +#define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_FSSLEW +// Description : TX_FSSLEW=0: Low speed slew rate +// TX_FSSLEW=1: Full speed slew rate +#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS _u(0x00004000) +#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB _u(14) +#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB _u(14) +#define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_PD +// Description : TX power down override (if override enable is set). 1 = powered +// down. +#define USB_USBPHY_DIRECT_TX_PD_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_PD_BITS _u(0x00002000) +#define USB_USBPHY_DIRECT_TX_PD_MSB _u(13) +#define USB_USBPHY_DIRECT_TX_PD_LSB _u(13) +#define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_RX_PD +// Description : RX power down override (if override enable is set). 1 = powered +// down. +#define USB_USBPHY_DIRECT_RX_PD_RESET _u(0x0) +#define USB_USBPHY_DIRECT_RX_PD_BITS _u(0x00001000) +#define USB_USBPHY_DIRECT_RX_PD_MSB _u(12) +#define USB_USBPHY_DIRECT_RX_PD_LSB _u(12) +#define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DM +// Description : Output data. TX_DIFFMODE=1, Ignored +// TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. +// DPM=TX_DM +#define USB_USBPHY_DIRECT_TX_DM_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DM_BITS _u(0x00000800) +#define USB_USBPHY_DIRECT_TX_DM_MSB _u(11) +#define USB_USBPHY_DIRECT_TX_DM_LSB _u(11) +#define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DP +// Description : Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. +// TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP +// If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. +// DPP=TX_DP +#define USB_USBPHY_DIRECT_TX_DP_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DP_BITS _u(0x00000400) +#define USB_USBPHY_DIRECT_TX_DP_MSB _u(10) +#define USB_USBPHY_DIRECT_TX_DP_LSB _u(10) +#define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DM_OE +// Description : Output enable. If TX_DIFFMODE=1, Ignored. +// If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - +// DPM driving +#define USB_USBPHY_DIRECT_TX_DM_OE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DM_OE_BITS _u(0x00000200) +#define USB_USBPHY_DIRECT_TX_DM_OE_MSB _u(9) +#define USB_USBPHY_DIRECT_TX_DM_OE_LSB _u(9) +#define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_TX_DP_OE +// Description : Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - +// DPP/DPM in Hi-Z state; 1 - DPP/DPM driving +// If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - +// DPP driving +#define USB_USBPHY_DIRECT_TX_DP_OE_RESET _u(0x0) +#define USB_USBPHY_DIRECT_TX_DP_OE_BITS _u(0x00000100) +#define USB_USBPHY_DIRECT_TX_DP_OE_MSB _u(8) +#define USB_USBPHY_DIRECT_TX_DP_OE_LSB _u(8) +#define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_PULLDN_EN +// Description : DM pull down enable +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS _u(0x00000040) +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB _u(6) +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB _u(6) +#define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_PULLUP_EN +// Description : DM pull up enable +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS _u(0x00000020) +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB _u(5) +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB _u(5) +#define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DM_PULLUP_HISEL +// Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - +// Pull = Rpu1 + Rpu2 +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS _u(0x00000010) +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB _u(4) +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB _u(4) +#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_PULLDN_EN +// Description : DP pull down enable +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS _u(0x00000004) +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB _u(2) +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB _u(2) +#define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_PULLUP_EN +// Description : DP pull up enable +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS _u(0x00000002) +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB _u(1) +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB _u(1) +#define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_DP_PULLUP_HISEL +// Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - +// Pull = Rpu1 + Rpu2 +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET _u(0x0) +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS _u(0x00000001) +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB _u(0) +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB _u(0) +#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW" +// ============================================================================= +// Register : USB_USBPHY_DIRECT_OVERRIDE +// Description : Override enable for each control in usbphy_direct +#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _u(0x00000080) +#define USB_USBPHY_DIRECT_OVERRIDE_BITS _u(0x00079fff) +#define USB_USBPHY_DIRECT_OVERRIDE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_BITS _u(0x00040000) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_MSB _u(18) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_LSB _u(18) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DM_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_BITS _u(0x00020000) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_MSB _u(17) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_LSB _u(17) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DP_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_BITS _u(0x00010000) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_MSB _u(16) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_LSB _u(16) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_DD_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS _u(0x00008000) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB _u(15) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB _u(15) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS _u(0x00001000) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB _u(12) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB _u(12) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS _u(0x00000800) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB _u(11) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB _u(11) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS _u(0x00000400) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB _u(10) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB _u(10) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS _u(0x00000200) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB _u(9) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB _u(9) +#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS _u(0x00000100) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB _u(8) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB _u(8) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS _u(0x00000080) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB _u(7) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB _u(7) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS _u(0x00000040) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB _u(6) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB _u(6) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS _u(0x00000020) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB _u(5) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB _u(5) +#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000010) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB _u(4) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB _u(4) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000008) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB _u(3) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB _u(3) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS _u(0x00000004) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB _u(2) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB _u(2) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000002) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB _u(1) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB _u(1) +#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000001) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB _u(0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB _u(0) +#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW" +// ============================================================================= +// Register : USB_USBPHY_TRIM +// Description : Used to adjust trim values of USB phy pull down resistors. +#define USB_USBPHY_TRIM_OFFSET _u(0x00000084) +#define USB_USBPHY_TRIM_BITS _u(0x00001f1f) +#define USB_USBPHY_TRIM_RESET _u(0x00001f1f) +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_TRIM_DM_PULLDN_TRIM +// Description : Value to drive to USB PHY +// DM pulldown resistor trim control +// Experimental data suggests that the reset value will work, but +// this register allows adjustment if required +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET _u(0x1f) +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS _u(0x00001f00) +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB _u(12) +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB _u(8) +#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_USBPHY_TRIM_DP_PULLDN_TRIM +// Description : Value to drive to USB PHY +// DP pulldown resistor trim control +// Experimental data suggests that the reset value will work, but +// this register allows adjustment if required +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET _u(0x1f) +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS _u(0x0000001f) +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB _u(4) +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB _u(0) +#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_ACCESS "RW" +// ============================================================================= +// Register : USB_LINESTATE_TUNING +// Description : Used for debug only. +#define USB_LINESTATE_TUNING_OFFSET _u(0x00000088) +#define USB_LINESTATE_TUNING_BITS _u(0x00000fff) +#define USB_LINESTATE_TUNING_RESET _u(0x000000f8) +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_SPARE_FIX +#define USB_LINESTATE_TUNING_SPARE_FIX_RESET _u(0x0) +#define USB_LINESTATE_TUNING_SPARE_FIX_BITS _u(0x00000f00) +#define USB_LINESTATE_TUNING_SPARE_FIX_MSB _u(11) +#define USB_LINESTATE_TUNING_SPARE_FIX_LSB _u(8) +#define USB_LINESTATE_TUNING_SPARE_FIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX +// Description : Device - exit suspend on any non-idle signalling, not qualified +// with a 1ms timer +#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_RESET _u(0x1) +#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_BITS _u(0x00000080) +#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_MSB _u(7) +#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_LSB _u(7) +#define USB_LINESTATE_TUNING_DEV_LS_WAKE_FIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE +// Description : Device - suppress repeated errors until the device FSM is next +// in the process of decoding an inbound packet. +#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_RESET _u(0x1) +#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_BITS _u(0x00000040) +#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_MSB _u(6) +#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_LSB _u(6) +#define USB_LINESTATE_TUNING_DEV_RX_ERR_QUIESCE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX +// Description : RX - when recovering from line chatter or bitstuff errors, +// treat SE0 as the end of chatter as well as +// 8 consecutive idle bits. +#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_RESET _u(0x1) +#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_BITS _u(0x00000020) +#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_MSB _u(5) +#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_LSB _u(5) +#define USB_LINESTATE_TUNING_SIE_RX_CHATTER_SE0_FIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX +// Description : RX - when a bitstuff error is signalled by rx_dasm, +// unconditionally terminate RX decode to +// avoid a hang during certain packet phases. +#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_RESET _u(0x1) +#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_BITS _u(0x00000010) +#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_MSB _u(4) +#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_LSB _u(4) +#define USB_LINESTATE_TUNING_SIE_RX_BITSTUFF_FIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX +// Description : Device - the controller FSM performs two reads of the buffer +// status memory address to +// avoid sampling metastable data. An enabled buffer is only used +// if both reads match. +#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_RESET _u(0x1) +#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_BITS _u(0x00000008) +#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_MSB _u(3) +#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_LSB _u(3) +#define USB_LINESTATE_TUNING_DEV_BUFF_CONTROL_DOUBLE_READ_FIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_MULTI_HUB_FIX +// Description : Host - increase inter-packet and turnaround timeouts to +// accommodate worst-case hub delays. +#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_RESET _u(0x0) +#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_BITS _u(0x00000004) +#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_MSB _u(2) +#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_LSB _u(2) +#define USB_LINESTATE_TUNING_MULTI_HUB_FIX_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_LINESTATE_DELAY +// Description : Device/Host - add an extra 1-bit debounce of linestate +// sampling. +#define USB_LINESTATE_TUNING_LINESTATE_DELAY_RESET _u(0x0) +#define USB_LINESTATE_TUNING_LINESTATE_DELAY_BITS _u(0x00000002) +#define USB_LINESTATE_TUNING_LINESTATE_DELAY_MSB _u(1) +#define USB_LINESTATE_TUNING_LINESTATE_DELAY_LSB _u(1) +#define USB_LINESTATE_TUNING_LINESTATE_DELAY_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_LINESTATE_TUNING_RCV_DELAY +// Description : Device - register the received data to account for hub bit +// dribble before EOP. Only affects certain hubs. +#define USB_LINESTATE_TUNING_RCV_DELAY_RESET _u(0x0) +#define USB_LINESTATE_TUNING_RCV_DELAY_BITS _u(0x00000001) +#define USB_LINESTATE_TUNING_RCV_DELAY_MSB _u(0) +#define USB_LINESTATE_TUNING_RCV_DELAY_LSB _u(0) +#define USB_LINESTATE_TUNING_RCV_DELAY_ACCESS "RW" +// ============================================================================= +// Register : USB_INTR +// Description : Raw Interrupts +#define USB_INTR_OFFSET _u(0x0000008c) +#define USB_INTR_BITS _u(0x00ffffff) +#define USB_INTR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_INTR_EPX_STOPPED_ON_NAK +// Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK +#define USB_INTR_EPX_STOPPED_ON_NAK_RESET _u(0x0) +#define USB_INTR_EPX_STOPPED_ON_NAK_BITS _u(0x00800000) +#define USB_INTR_EPX_STOPPED_ON_NAK_MSB _u(23) +#define USB_INTR_EPX_STOPPED_ON_NAK_LSB _u(23) +#define USB_INTR_EPX_STOPPED_ON_NAK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_SM_WATCHDOG_FIRED +// Description : Source: DEV_SM_WATCHDOG.FIRED +#define USB_INTR_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) +#define USB_INTR_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00400000) +#define USB_INTR_DEV_SM_WATCHDOG_FIRED_MSB _u(22) +#define USB_INTR_DEV_SM_WATCHDOG_FIRED_LSB _u(22) +#define USB_INTR_DEV_SM_WATCHDOG_FIRED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ENDPOINT_ERROR +// Description : Source: SIE_STATUS.ENDPOINT_ERROR +#define USB_INTR_ENDPOINT_ERROR_RESET _u(0x0) +#define USB_INTR_ENDPOINT_ERROR_BITS _u(0x00200000) +#define USB_INTR_ENDPOINT_ERROR_MSB _u(21) +#define USB_INTR_ENDPOINT_ERROR_LSB _u(21) +#define USB_INTR_ENDPOINT_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_RX_SHORT_PACKET +// Description : Source: SIE_STATUS.RX_SHORT_PACKET +#define USB_INTR_RX_SHORT_PACKET_RESET _u(0x0) +#define USB_INTR_RX_SHORT_PACKET_BITS _u(0x00100000) +#define USB_INTR_RX_SHORT_PACKET_MSB _u(20) +#define USB_INTR_RX_SHORT_PACKET_LSB _u(20) +#define USB_INTR_RX_SHORT_PACKET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTR_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTR_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTR_EP_STALL_NAK_MSB _u(19) +#define USB_INTR_EP_STALL_NAK_LSB _u(19) +#define USB_INTR_EP_STALL_NAK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTR_ABORT_DONE_RESET _u(0x0) +#define USB_INTR_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTR_ABORT_DONE_MSB _u(18) +#define USB_INTR_ABORT_DONE_LSB _u(18) +#define USB_INTR_ABORT_DONE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTR_DEV_SOF_RESET _u(0x0) +#define USB_INTR_DEV_SOF_BITS _u(0x00020000) +#define USB_INTR_DEV_SOF_MSB _u(17) +#define USB_INTR_DEV_SOF_LSB _u(17) +#define USB_INTR_DEV_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTR_SETUP_REQ_RESET _u(0x0) +#define USB_INTR_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTR_SETUP_REQ_MSB _u(16) +#define USB_INTR_SETUP_REQ_LSB _u(16) +#define USB_INTR_SETUP_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTR_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTR_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTR_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTR_DEV_RESUME_FROM_HOST_LSB _u(15) +#define USB_INTR_DEV_RESUME_FROM_HOST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTR_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTR_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTR_DEV_SUSPEND_MSB _u(14) +#define USB_INTR_DEV_SUSPEND_LSB _u(14) +#define USB_INTR_DEV_SUSPEND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTR_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTR_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTR_DEV_CONN_DIS_MSB _u(13) +#define USB_INTR_DEV_CONN_DIS_LSB _u(13) +#define USB_INTR_DEV_CONN_DIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTR_BUS_RESET_RESET _u(0x0) +#define USB_INTR_BUS_RESET_BITS _u(0x00001000) +#define USB_INTR_BUS_RESET_MSB _u(12) +#define USB_INTR_BUS_RESET_LSB _u(12) +#define USB_INTR_BUS_RESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTR_VBUS_DETECT_RESET _u(0x0) +#define USB_INTR_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTR_VBUS_DETECT_MSB _u(11) +#define USB_INTR_VBUS_DETECT_LSB _u(11) +#define USB_INTR_VBUS_DETECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTR_STALL_RESET _u(0x0) +#define USB_INTR_STALL_BITS _u(0x00000400) +#define USB_INTR_STALL_MSB _u(10) +#define USB_INTR_STALL_LSB _u(10) +#define USB_INTR_STALL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTR_ERROR_CRC_RESET _u(0x0) +#define USB_INTR_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTR_ERROR_CRC_MSB _u(9) +#define USB_INTR_ERROR_CRC_LSB _u(9) +#define USB_INTR_ERROR_CRC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTR_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTR_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTR_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTR_ERROR_BIT_STUFF_LSB _u(8) +#define USB_INTR_ERROR_BIT_STUFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTR_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTR_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTR_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTR_ERROR_RX_OVERFLOW_LSB _u(7) +#define USB_INTR_ERROR_RX_OVERFLOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTR_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTR_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTR_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTR_ERROR_RX_TIMEOUT_LSB _u(6) +#define USB_INTR_ERROR_RX_TIMEOUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTR_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTR_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTR_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTR_ERROR_DATA_SEQ_LSB _u(5) +#define USB_INTR_ERROR_DATA_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTR_BUFF_STATUS_RESET _u(0x0) +#define USB_INTR_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTR_BUFF_STATUS_MSB _u(4) +#define USB_INTR_BUFF_STATUS_LSB _u(4) +#define USB_INTR_BUFF_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTR_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTR_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTR_TRANS_COMPLETE_MSB _u(3) +#define USB_INTR_TRANS_COMPLETE_LSB _u(3) +#define USB_INTR_TRANS_COMPLETE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTR_HOST_SOF_RESET _u(0x0) +#define USB_INTR_HOST_SOF_BITS _u(0x00000004) +#define USB_INTR_HOST_SOF_MSB _u(2) +#define USB_INTR_HOST_SOF_LSB _u(2) +#define USB_INTR_HOST_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTR_HOST_RESUME_RESET _u(0x0) +#define USB_INTR_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTR_HOST_RESUME_MSB _u(1) +#define USB_INTR_HOST_RESUME_LSB _u(1) +#define USB_INTR_HOST_RESUME_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTR_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTR_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTR_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTR_HOST_CONN_DIS_MSB _u(0) +#define USB_INTR_HOST_CONN_DIS_LSB _u(0) +#define USB_INTR_HOST_CONN_DIS_ACCESS "RO" +// ============================================================================= +// Register : USB_INTE +// Description : Interrupt Enable +#define USB_INTE_OFFSET _u(0x00000090) +#define USB_INTE_BITS _u(0x00ffffff) +#define USB_INTE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_INTE_EPX_STOPPED_ON_NAK +// Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK +#define USB_INTE_EPX_STOPPED_ON_NAK_RESET _u(0x0) +#define USB_INTE_EPX_STOPPED_ON_NAK_BITS _u(0x00800000) +#define USB_INTE_EPX_STOPPED_ON_NAK_MSB _u(23) +#define USB_INTE_EPX_STOPPED_ON_NAK_LSB _u(23) +#define USB_INTE_EPX_STOPPED_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_SM_WATCHDOG_FIRED +// Description : Source: DEV_SM_WATCHDOG.FIRED +#define USB_INTE_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) +#define USB_INTE_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00400000) +#define USB_INTE_DEV_SM_WATCHDOG_FIRED_MSB _u(22) +#define USB_INTE_DEV_SM_WATCHDOG_FIRED_LSB _u(22) +#define USB_INTE_DEV_SM_WATCHDOG_FIRED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ENDPOINT_ERROR +// Description : Source: SIE_STATUS.ENDPOINT_ERROR +#define USB_INTE_ENDPOINT_ERROR_RESET _u(0x0) +#define USB_INTE_ENDPOINT_ERROR_BITS _u(0x00200000) +#define USB_INTE_ENDPOINT_ERROR_MSB _u(21) +#define USB_INTE_ENDPOINT_ERROR_LSB _u(21) +#define USB_INTE_ENDPOINT_ERROR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_RX_SHORT_PACKET +// Description : Source: SIE_STATUS.RX_SHORT_PACKET +#define USB_INTE_RX_SHORT_PACKET_RESET _u(0x0) +#define USB_INTE_RX_SHORT_PACKET_BITS _u(0x00100000) +#define USB_INTE_RX_SHORT_PACKET_MSB _u(20) +#define USB_INTE_RX_SHORT_PACKET_LSB _u(20) +#define USB_INTE_RX_SHORT_PACKET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTE_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTE_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTE_EP_STALL_NAK_MSB _u(19) +#define USB_INTE_EP_STALL_NAK_LSB _u(19) +#define USB_INTE_EP_STALL_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTE_ABORT_DONE_RESET _u(0x0) +#define USB_INTE_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTE_ABORT_DONE_MSB _u(18) +#define USB_INTE_ABORT_DONE_LSB _u(18) +#define USB_INTE_ABORT_DONE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTE_DEV_SOF_RESET _u(0x0) +#define USB_INTE_DEV_SOF_BITS _u(0x00020000) +#define USB_INTE_DEV_SOF_MSB _u(17) +#define USB_INTE_DEV_SOF_LSB _u(17) +#define USB_INTE_DEV_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTE_SETUP_REQ_RESET _u(0x0) +#define USB_INTE_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTE_SETUP_REQ_MSB _u(16) +#define USB_INTE_SETUP_REQ_LSB _u(16) +#define USB_INTE_SETUP_REQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTE_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTE_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTE_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTE_DEV_RESUME_FROM_HOST_LSB _u(15) +#define USB_INTE_DEV_RESUME_FROM_HOST_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTE_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTE_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTE_DEV_SUSPEND_MSB _u(14) +#define USB_INTE_DEV_SUSPEND_LSB _u(14) +#define USB_INTE_DEV_SUSPEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTE_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTE_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTE_DEV_CONN_DIS_MSB _u(13) +#define USB_INTE_DEV_CONN_DIS_LSB _u(13) +#define USB_INTE_DEV_CONN_DIS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTE_BUS_RESET_RESET _u(0x0) +#define USB_INTE_BUS_RESET_BITS _u(0x00001000) +#define USB_INTE_BUS_RESET_MSB _u(12) +#define USB_INTE_BUS_RESET_LSB _u(12) +#define USB_INTE_BUS_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTE_VBUS_DETECT_RESET _u(0x0) +#define USB_INTE_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTE_VBUS_DETECT_MSB _u(11) +#define USB_INTE_VBUS_DETECT_LSB _u(11) +#define USB_INTE_VBUS_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTE_STALL_RESET _u(0x0) +#define USB_INTE_STALL_BITS _u(0x00000400) +#define USB_INTE_STALL_MSB _u(10) +#define USB_INTE_STALL_LSB _u(10) +#define USB_INTE_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTE_ERROR_CRC_RESET _u(0x0) +#define USB_INTE_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTE_ERROR_CRC_MSB _u(9) +#define USB_INTE_ERROR_CRC_LSB _u(9) +#define USB_INTE_ERROR_CRC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTE_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTE_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTE_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTE_ERROR_BIT_STUFF_LSB _u(8) +#define USB_INTE_ERROR_BIT_STUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTE_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTE_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTE_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTE_ERROR_RX_OVERFLOW_LSB _u(7) +#define USB_INTE_ERROR_RX_OVERFLOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTE_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTE_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTE_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTE_ERROR_RX_TIMEOUT_LSB _u(6) +#define USB_INTE_ERROR_RX_TIMEOUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTE_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTE_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTE_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTE_ERROR_DATA_SEQ_LSB _u(5) +#define USB_INTE_ERROR_DATA_SEQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTE_BUFF_STATUS_RESET _u(0x0) +#define USB_INTE_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTE_BUFF_STATUS_MSB _u(4) +#define USB_INTE_BUFF_STATUS_LSB _u(4) +#define USB_INTE_BUFF_STATUS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTE_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTE_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTE_TRANS_COMPLETE_MSB _u(3) +#define USB_INTE_TRANS_COMPLETE_LSB _u(3) +#define USB_INTE_TRANS_COMPLETE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTE_HOST_SOF_RESET _u(0x0) +#define USB_INTE_HOST_SOF_BITS _u(0x00000004) +#define USB_INTE_HOST_SOF_MSB _u(2) +#define USB_INTE_HOST_SOF_LSB _u(2) +#define USB_INTE_HOST_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTE_HOST_RESUME_RESET _u(0x0) +#define USB_INTE_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTE_HOST_RESUME_MSB _u(1) +#define USB_INTE_HOST_RESUME_LSB _u(1) +#define USB_INTE_HOST_RESUME_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTE_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTE_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTE_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTE_HOST_CONN_DIS_MSB _u(0) +#define USB_INTE_HOST_CONN_DIS_LSB _u(0) +#define USB_INTE_HOST_CONN_DIS_ACCESS "RW" +// ============================================================================= +// Register : USB_INTF +// Description : Interrupt Force +#define USB_INTF_OFFSET _u(0x00000094) +#define USB_INTF_BITS _u(0x00ffffff) +#define USB_INTF_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_INTF_EPX_STOPPED_ON_NAK +// Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK +#define USB_INTF_EPX_STOPPED_ON_NAK_RESET _u(0x0) +#define USB_INTF_EPX_STOPPED_ON_NAK_BITS _u(0x00800000) +#define USB_INTF_EPX_STOPPED_ON_NAK_MSB _u(23) +#define USB_INTF_EPX_STOPPED_ON_NAK_LSB _u(23) +#define USB_INTF_EPX_STOPPED_ON_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_SM_WATCHDOG_FIRED +// Description : Source: DEV_SM_WATCHDOG.FIRED +#define USB_INTF_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) +#define USB_INTF_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00400000) +#define USB_INTF_DEV_SM_WATCHDOG_FIRED_MSB _u(22) +#define USB_INTF_DEV_SM_WATCHDOG_FIRED_LSB _u(22) +#define USB_INTF_DEV_SM_WATCHDOG_FIRED_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ENDPOINT_ERROR +// Description : Source: SIE_STATUS.ENDPOINT_ERROR +#define USB_INTF_ENDPOINT_ERROR_RESET _u(0x0) +#define USB_INTF_ENDPOINT_ERROR_BITS _u(0x00200000) +#define USB_INTF_ENDPOINT_ERROR_MSB _u(21) +#define USB_INTF_ENDPOINT_ERROR_LSB _u(21) +#define USB_INTF_ENDPOINT_ERROR_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_RX_SHORT_PACKET +// Description : Source: SIE_STATUS.RX_SHORT_PACKET +#define USB_INTF_RX_SHORT_PACKET_RESET _u(0x0) +#define USB_INTF_RX_SHORT_PACKET_BITS _u(0x00100000) +#define USB_INTF_RX_SHORT_PACKET_MSB _u(20) +#define USB_INTF_RX_SHORT_PACKET_LSB _u(20) +#define USB_INTF_RX_SHORT_PACKET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTF_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTF_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTF_EP_STALL_NAK_MSB _u(19) +#define USB_INTF_EP_STALL_NAK_LSB _u(19) +#define USB_INTF_EP_STALL_NAK_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTF_ABORT_DONE_RESET _u(0x0) +#define USB_INTF_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTF_ABORT_DONE_MSB _u(18) +#define USB_INTF_ABORT_DONE_LSB _u(18) +#define USB_INTF_ABORT_DONE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTF_DEV_SOF_RESET _u(0x0) +#define USB_INTF_DEV_SOF_BITS _u(0x00020000) +#define USB_INTF_DEV_SOF_MSB _u(17) +#define USB_INTF_DEV_SOF_LSB _u(17) +#define USB_INTF_DEV_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTF_SETUP_REQ_RESET _u(0x0) +#define USB_INTF_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTF_SETUP_REQ_MSB _u(16) +#define USB_INTF_SETUP_REQ_LSB _u(16) +#define USB_INTF_SETUP_REQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTF_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTF_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTF_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTF_DEV_RESUME_FROM_HOST_LSB _u(15) +#define USB_INTF_DEV_RESUME_FROM_HOST_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTF_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTF_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTF_DEV_SUSPEND_MSB _u(14) +#define USB_INTF_DEV_SUSPEND_LSB _u(14) +#define USB_INTF_DEV_SUSPEND_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTF_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTF_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTF_DEV_CONN_DIS_MSB _u(13) +#define USB_INTF_DEV_CONN_DIS_LSB _u(13) +#define USB_INTF_DEV_CONN_DIS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTF_BUS_RESET_RESET _u(0x0) +#define USB_INTF_BUS_RESET_BITS _u(0x00001000) +#define USB_INTF_BUS_RESET_MSB _u(12) +#define USB_INTF_BUS_RESET_LSB _u(12) +#define USB_INTF_BUS_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTF_VBUS_DETECT_RESET _u(0x0) +#define USB_INTF_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTF_VBUS_DETECT_MSB _u(11) +#define USB_INTF_VBUS_DETECT_LSB _u(11) +#define USB_INTF_VBUS_DETECT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTF_STALL_RESET _u(0x0) +#define USB_INTF_STALL_BITS _u(0x00000400) +#define USB_INTF_STALL_MSB _u(10) +#define USB_INTF_STALL_LSB _u(10) +#define USB_INTF_STALL_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTF_ERROR_CRC_RESET _u(0x0) +#define USB_INTF_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTF_ERROR_CRC_MSB _u(9) +#define USB_INTF_ERROR_CRC_LSB _u(9) +#define USB_INTF_ERROR_CRC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTF_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTF_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTF_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTF_ERROR_BIT_STUFF_LSB _u(8) +#define USB_INTF_ERROR_BIT_STUFF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTF_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTF_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTF_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTF_ERROR_RX_OVERFLOW_LSB _u(7) +#define USB_INTF_ERROR_RX_OVERFLOW_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTF_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTF_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTF_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTF_ERROR_RX_TIMEOUT_LSB _u(6) +#define USB_INTF_ERROR_RX_TIMEOUT_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTF_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTF_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTF_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTF_ERROR_DATA_SEQ_LSB _u(5) +#define USB_INTF_ERROR_DATA_SEQ_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTF_BUFF_STATUS_RESET _u(0x0) +#define USB_INTF_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTF_BUFF_STATUS_MSB _u(4) +#define USB_INTF_BUFF_STATUS_LSB _u(4) +#define USB_INTF_BUFF_STATUS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTF_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTF_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTF_TRANS_COMPLETE_MSB _u(3) +#define USB_INTF_TRANS_COMPLETE_LSB _u(3) +#define USB_INTF_TRANS_COMPLETE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTF_HOST_SOF_RESET _u(0x0) +#define USB_INTF_HOST_SOF_BITS _u(0x00000004) +#define USB_INTF_HOST_SOF_MSB _u(2) +#define USB_INTF_HOST_SOF_LSB _u(2) +#define USB_INTF_HOST_SOF_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTF_HOST_RESUME_RESET _u(0x0) +#define USB_INTF_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTF_HOST_RESUME_MSB _u(1) +#define USB_INTF_HOST_RESUME_LSB _u(1) +#define USB_INTF_HOST_RESUME_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_INTF_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTF_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTF_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTF_HOST_CONN_DIS_MSB _u(0) +#define USB_INTF_HOST_CONN_DIS_LSB _u(0) +#define USB_INTF_HOST_CONN_DIS_ACCESS "RW" +// ============================================================================= +// Register : USB_INTS +// Description : Interrupt status after masking & forcing +#define USB_INTS_OFFSET _u(0x00000098) +#define USB_INTS_BITS _u(0x00ffffff) +#define USB_INTS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_INTS_EPX_STOPPED_ON_NAK +// Description : Source: NAK_POLL.EPX_STOPPED_ON_NAK +#define USB_INTS_EPX_STOPPED_ON_NAK_RESET _u(0x0) +#define USB_INTS_EPX_STOPPED_ON_NAK_BITS _u(0x00800000) +#define USB_INTS_EPX_STOPPED_ON_NAK_MSB _u(23) +#define USB_INTS_EPX_STOPPED_ON_NAK_LSB _u(23) +#define USB_INTS_EPX_STOPPED_ON_NAK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_SM_WATCHDOG_FIRED +// Description : Source: DEV_SM_WATCHDOG.FIRED +#define USB_INTS_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) +#define USB_INTS_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00400000) +#define USB_INTS_DEV_SM_WATCHDOG_FIRED_MSB _u(22) +#define USB_INTS_DEV_SM_WATCHDOG_FIRED_LSB _u(22) +#define USB_INTS_DEV_SM_WATCHDOG_FIRED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ENDPOINT_ERROR +// Description : Source: SIE_STATUS.ENDPOINT_ERROR +#define USB_INTS_ENDPOINT_ERROR_RESET _u(0x0) +#define USB_INTS_ENDPOINT_ERROR_BITS _u(0x00200000) +#define USB_INTS_ENDPOINT_ERROR_MSB _u(21) +#define USB_INTS_ENDPOINT_ERROR_LSB _u(21) +#define USB_INTS_ENDPOINT_ERROR_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_RX_SHORT_PACKET +// Description : Source: SIE_STATUS.RX_SHORT_PACKET +#define USB_INTS_RX_SHORT_PACKET_RESET _u(0x0) +#define USB_INTS_RX_SHORT_PACKET_BITS _u(0x00100000) +#define USB_INTS_RX_SHORT_PACKET_MSB _u(20) +#define USB_INTS_RX_SHORT_PACKET_LSB _u(20) +#define USB_INTS_RX_SHORT_PACKET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_EP_STALL_NAK +// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by +// clearing all bits in EP_STATUS_STALL_NAK. +#define USB_INTS_EP_STALL_NAK_RESET _u(0x0) +#define USB_INTS_EP_STALL_NAK_BITS _u(0x00080000) +#define USB_INTS_EP_STALL_NAK_MSB _u(19) +#define USB_INTS_EP_STALL_NAK_LSB _u(19) +#define USB_INTS_EP_STALL_NAK_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ABORT_DONE +// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all +// bits in ABORT_DONE. +#define USB_INTS_ABORT_DONE_RESET _u(0x0) +#define USB_INTS_ABORT_DONE_BITS _u(0x00040000) +#define USB_INTS_ABORT_DONE_MSB _u(18) +#define USB_INTS_ABORT_DONE_LSB _u(18) +#define USB_INTS_ABORT_DONE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_SOF +// Description : Set every time the device receives a SOF (Start of Frame) +// packet. Cleared by reading SOF_RD +#define USB_INTS_DEV_SOF_RESET _u(0x0) +#define USB_INTS_DEV_SOF_BITS _u(0x00020000) +#define USB_INTS_DEV_SOF_MSB _u(17) +#define USB_INTS_DEV_SOF_LSB _u(17) +#define USB_INTS_DEV_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_SETUP_REQ +// Description : Device. Source: SIE_STATUS.SETUP_REC +#define USB_INTS_SETUP_REQ_RESET _u(0x0) +#define USB_INTS_SETUP_REQ_BITS _u(0x00010000) +#define USB_INTS_SETUP_REQ_MSB _u(16) +#define USB_INTS_SETUP_REQ_LSB _u(16) +#define USB_INTS_SETUP_REQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_RESUME_FROM_HOST +// Description : Set when the device receives a resume from the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTS_DEV_RESUME_FROM_HOST_RESET _u(0x0) +#define USB_INTS_DEV_RESUME_FROM_HOST_BITS _u(0x00008000) +#define USB_INTS_DEV_RESUME_FROM_HOST_MSB _u(15) +#define USB_INTS_DEV_RESUME_FROM_HOST_LSB _u(15) +#define USB_INTS_DEV_RESUME_FROM_HOST_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_SUSPEND +// Description : Set when the device suspend state changes. Cleared by writing +// to SIE_STATUS.SUSPENDED +#define USB_INTS_DEV_SUSPEND_RESET _u(0x0) +#define USB_INTS_DEV_SUSPEND_BITS _u(0x00004000) +#define USB_INTS_DEV_SUSPEND_MSB _u(14) +#define USB_INTS_DEV_SUSPEND_LSB _u(14) +#define USB_INTS_DEV_SUSPEND_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_DEV_CONN_DIS +// Description : Set when the device connection state changes. Cleared by +// writing to SIE_STATUS.CONNECTED +#define USB_INTS_DEV_CONN_DIS_RESET _u(0x0) +#define USB_INTS_DEV_CONN_DIS_BITS _u(0x00002000) +#define USB_INTS_DEV_CONN_DIS_MSB _u(13) +#define USB_INTS_DEV_CONN_DIS_LSB _u(13) +#define USB_INTS_DEV_CONN_DIS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_BUS_RESET +// Description : Source: SIE_STATUS.BUS_RESET +#define USB_INTS_BUS_RESET_RESET _u(0x0) +#define USB_INTS_BUS_RESET_BITS _u(0x00001000) +#define USB_INTS_BUS_RESET_MSB _u(12) +#define USB_INTS_BUS_RESET_LSB _u(12) +#define USB_INTS_BUS_RESET_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_VBUS_DETECT +// Description : Source: SIE_STATUS.VBUS_DETECTED +#define USB_INTS_VBUS_DETECT_RESET _u(0x0) +#define USB_INTS_VBUS_DETECT_BITS _u(0x00000800) +#define USB_INTS_VBUS_DETECT_MSB _u(11) +#define USB_INTS_VBUS_DETECT_LSB _u(11) +#define USB_INTS_VBUS_DETECT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_STALL +// Description : Source: SIE_STATUS.STALL_REC +#define USB_INTS_STALL_RESET _u(0x0) +#define USB_INTS_STALL_BITS _u(0x00000400) +#define USB_INTS_STALL_MSB _u(10) +#define USB_INTS_STALL_LSB _u(10) +#define USB_INTS_STALL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_CRC +// Description : Source: SIE_STATUS.CRC_ERROR +#define USB_INTS_ERROR_CRC_RESET _u(0x0) +#define USB_INTS_ERROR_CRC_BITS _u(0x00000200) +#define USB_INTS_ERROR_CRC_MSB _u(9) +#define USB_INTS_ERROR_CRC_LSB _u(9) +#define USB_INTS_ERROR_CRC_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_BIT_STUFF +// Description : Source: SIE_STATUS.BIT_STUFF_ERROR +#define USB_INTS_ERROR_BIT_STUFF_RESET _u(0x0) +#define USB_INTS_ERROR_BIT_STUFF_BITS _u(0x00000100) +#define USB_INTS_ERROR_BIT_STUFF_MSB _u(8) +#define USB_INTS_ERROR_BIT_STUFF_LSB _u(8) +#define USB_INTS_ERROR_BIT_STUFF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_RX_OVERFLOW +// Description : Source: SIE_STATUS.RX_OVERFLOW +#define USB_INTS_ERROR_RX_OVERFLOW_RESET _u(0x0) +#define USB_INTS_ERROR_RX_OVERFLOW_BITS _u(0x00000080) +#define USB_INTS_ERROR_RX_OVERFLOW_MSB _u(7) +#define USB_INTS_ERROR_RX_OVERFLOW_LSB _u(7) +#define USB_INTS_ERROR_RX_OVERFLOW_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_RX_TIMEOUT +// Description : Source: SIE_STATUS.RX_TIMEOUT +#define USB_INTS_ERROR_RX_TIMEOUT_RESET _u(0x0) +#define USB_INTS_ERROR_RX_TIMEOUT_BITS _u(0x00000040) +#define USB_INTS_ERROR_RX_TIMEOUT_MSB _u(6) +#define USB_INTS_ERROR_RX_TIMEOUT_LSB _u(6) +#define USB_INTS_ERROR_RX_TIMEOUT_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_ERROR_DATA_SEQ +// Description : Source: SIE_STATUS.DATA_SEQ_ERROR +#define USB_INTS_ERROR_DATA_SEQ_RESET _u(0x0) +#define USB_INTS_ERROR_DATA_SEQ_BITS _u(0x00000020) +#define USB_INTS_ERROR_DATA_SEQ_MSB _u(5) +#define USB_INTS_ERROR_DATA_SEQ_LSB _u(5) +#define USB_INTS_ERROR_DATA_SEQ_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_BUFF_STATUS +// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing +// all bits in BUFF_STATUS. +#define USB_INTS_BUFF_STATUS_RESET _u(0x0) +#define USB_INTS_BUFF_STATUS_BITS _u(0x00000010) +#define USB_INTS_BUFF_STATUS_MSB _u(4) +#define USB_INTS_BUFF_STATUS_LSB _u(4) +#define USB_INTS_BUFF_STATUS_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_TRANS_COMPLETE +// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by +// writing to this bit. +#define USB_INTS_TRANS_COMPLETE_RESET _u(0x0) +#define USB_INTS_TRANS_COMPLETE_BITS _u(0x00000008) +#define USB_INTS_TRANS_COMPLETE_MSB _u(3) +#define USB_INTS_TRANS_COMPLETE_LSB _u(3) +#define USB_INTS_TRANS_COMPLETE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_HOST_SOF +// Description : Host: raised every time the host sends a SOF (Start of Frame). +// Cleared by reading SOF_RD +#define USB_INTS_HOST_SOF_RESET _u(0x0) +#define USB_INTS_HOST_SOF_BITS _u(0x00000004) +#define USB_INTS_HOST_SOF_MSB _u(2) +#define USB_INTS_HOST_SOF_LSB _u(2) +#define USB_INTS_HOST_SOF_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_HOST_RESUME +// Description : Host: raised when a device wakes up the host. Cleared by +// writing to SIE_STATUS.RESUME +#define USB_INTS_HOST_RESUME_RESET _u(0x0) +#define USB_INTS_HOST_RESUME_BITS _u(0x00000002) +#define USB_INTS_HOST_RESUME_MSB _u(1) +#define USB_INTS_HOST_RESUME_LSB _u(1) +#define USB_INTS_HOST_RESUME_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_INTS_HOST_CONN_DIS +// Description : Host: raised when a device is connected or disconnected (i.e. +// when SIE_STATUS.SPEED changes). Cleared by writing to +// SIE_STATUS.SPEED +#define USB_INTS_HOST_CONN_DIS_RESET _u(0x0) +#define USB_INTS_HOST_CONN_DIS_BITS _u(0x00000001) +#define USB_INTS_HOST_CONN_DIS_MSB _u(0) +#define USB_INTS_HOST_CONN_DIS_LSB _u(0) +#define USB_INTS_HOST_CONN_DIS_ACCESS "RO" +// ============================================================================= +// Register : USB_SOF_TIMESTAMP_RAW +// Description : Device only. Raw value of free-running PHY clock counter +// @48MHz. Used to calculate time between SOF events. +#define USB_SOF_TIMESTAMP_RAW_OFFSET _u(0x00000100) +#define USB_SOF_TIMESTAMP_RAW_BITS _u(0x001fffff) +#define USB_SOF_TIMESTAMP_RAW_RESET _u(0x00000000) +#define USB_SOF_TIMESTAMP_RAW_MSB _u(20) +#define USB_SOF_TIMESTAMP_RAW_LSB _u(0) +#define USB_SOF_TIMESTAMP_RAW_ACCESS "RO" +// ============================================================================= +// Register : USB_SOF_TIMESTAMP_LAST +// Description : Device only. Value of free-running PHY clock counter @48MHz +// when last SOF event occurred. +#define USB_SOF_TIMESTAMP_LAST_OFFSET _u(0x00000104) +#define USB_SOF_TIMESTAMP_LAST_BITS _u(0x001fffff) +#define USB_SOF_TIMESTAMP_LAST_RESET _u(0x00000000) +#define USB_SOF_TIMESTAMP_LAST_MSB _u(20) +#define USB_SOF_TIMESTAMP_LAST_LSB _u(0) +#define USB_SOF_TIMESTAMP_LAST_ACCESS "RO" +// ============================================================================= +// Register : USB_SM_STATE +#define USB_SM_STATE_OFFSET _u(0x00000108) +#define USB_SM_STATE_BITS _u(0x00000fff) +#define USB_SM_STATE_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_SM_STATE_RX_DASM +#define USB_SM_STATE_RX_DASM_RESET _u(0x0) +#define USB_SM_STATE_RX_DASM_BITS _u(0x00000f00) +#define USB_SM_STATE_RX_DASM_MSB _u(11) +#define USB_SM_STATE_RX_DASM_LSB _u(8) +#define USB_SM_STATE_RX_DASM_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SM_STATE_BC_STATE +#define USB_SM_STATE_BC_STATE_RESET _u(0x0) +#define USB_SM_STATE_BC_STATE_BITS _u(0x000000e0) +#define USB_SM_STATE_BC_STATE_MSB _u(7) +#define USB_SM_STATE_BC_STATE_LSB _u(5) +#define USB_SM_STATE_BC_STATE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : USB_SM_STATE_STATE +#define USB_SM_STATE_STATE_RESET _u(0x00) +#define USB_SM_STATE_STATE_BITS _u(0x0000001f) +#define USB_SM_STATE_STATE_MSB _u(4) +#define USB_SM_STATE_STATE_LSB _u(0) +#define USB_SM_STATE_STATE_ACCESS "RO" +// ============================================================================= +// Register : USB_EP_TX_ERROR +// Description : TX error count for each endpoint. Write to each field to reset +// the counter to 0. +#define USB_EP_TX_ERROR_OFFSET _u(0x0000010c) +#define USB_EP_TX_ERROR_BITS _u(0xffffffff) +#define USB_EP_TX_ERROR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP15 +#define USB_EP_TX_ERROR_EP15_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP15_BITS _u(0xc0000000) +#define USB_EP_TX_ERROR_EP15_MSB _u(31) +#define USB_EP_TX_ERROR_EP15_LSB _u(30) +#define USB_EP_TX_ERROR_EP15_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP14 +#define USB_EP_TX_ERROR_EP14_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP14_BITS _u(0x30000000) +#define USB_EP_TX_ERROR_EP14_MSB _u(29) +#define USB_EP_TX_ERROR_EP14_LSB _u(28) +#define USB_EP_TX_ERROR_EP14_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP13 +#define USB_EP_TX_ERROR_EP13_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP13_BITS _u(0x0c000000) +#define USB_EP_TX_ERROR_EP13_MSB _u(27) +#define USB_EP_TX_ERROR_EP13_LSB _u(26) +#define USB_EP_TX_ERROR_EP13_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP12 +#define USB_EP_TX_ERROR_EP12_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP12_BITS _u(0x03000000) +#define USB_EP_TX_ERROR_EP12_MSB _u(25) +#define USB_EP_TX_ERROR_EP12_LSB _u(24) +#define USB_EP_TX_ERROR_EP12_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP11 +#define USB_EP_TX_ERROR_EP11_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP11_BITS _u(0x00c00000) +#define USB_EP_TX_ERROR_EP11_MSB _u(23) +#define USB_EP_TX_ERROR_EP11_LSB _u(22) +#define USB_EP_TX_ERROR_EP11_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP10 +#define USB_EP_TX_ERROR_EP10_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP10_BITS _u(0x00300000) +#define USB_EP_TX_ERROR_EP10_MSB _u(21) +#define USB_EP_TX_ERROR_EP10_LSB _u(20) +#define USB_EP_TX_ERROR_EP10_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP9 +#define USB_EP_TX_ERROR_EP9_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP9_BITS _u(0x000c0000) +#define USB_EP_TX_ERROR_EP9_MSB _u(19) +#define USB_EP_TX_ERROR_EP9_LSB _u(18) +#define USB_EP_TX_ERROR_EP9_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP8 +#define USB_EP_TX_ERROR_EP8_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP8_BITS _u(0x00030000) +#define USB_EP_TX_ERROR_EP8_MSB _u(17) +#define USB_EP_TX_ERROR_EP8_LSB _u(16) +#define USB_EP_TX_ERROR_EP8_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP7 +#define USB_EP_TX_ERROR_EP7_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP7_BITS _u(0x0000c000) +#define USB_EP_TX_ERROR_EP7_MSB _u(15) +#define USB_EP_TX_ERROR_EP7_LSB _u(14) +#define USB_EP_TX_ERROR_EP7_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP6 +#define USB_EP_TX_ERROR_EP6_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP6_BITS _u(0x00003000) +#define USB_EP_TX_ERROR_EP6_MSB _u(13) +#define USB_EP_TX_ERROR_EP6_LSB _u(12) +#define USB_EP_TX_ERROR_EP6_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP5 +#define USB_EP_TX_ERROR_EP5_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP5_BITS _u(0x00000c00) +#define USB_EP_TX_ERROR_EP5_MSB _u(11) +#define USB_EP_TX_ERROR_EP5_LSB _u(10) +#define USB_EP_TX_ERROR_EP5_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP4 +#define USB_EP_TX_ERROR_EP4_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP4_BITS _u(0x00000300) +#define USB_EP_TX_ERROR_EP4_MSB _u(9) +#define USB_EP_TX_ERROR_EP4_LSB _u(8) +#define USB_EP_TX_ERROR_EP4_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP3 +#define USB_EP_TX_ERROR_EP3_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP3_BITS _u(0x000000c0) +#define USB_EP_TX_ERROR_EP3_MSB _u(7) +#define USB_EP_TX_ERROR_EP3_LSB _u(6) +#define USB_EP_TX_ERROR_EP3_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP2 +#define USB_EP_TX_ERROR_EP2_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP2_BITS _u(0x00000030) +#define USB_EP_TX_ERROR_EP2_MSB _u(5) +#define USB_EP_TX_ERROR_EP2_LSB _u(4) +#define USB_EP_TX_ERROR_EP2_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP1 +#define USB_EP_TX_ERROR_EP1_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP1_BITS _u(0x0000000c) +#define USB_EP_TX_ERROR_EP1_MSB _u(3) +#define USB_EP_TX_ERROR_EP1_LSB _u(2) +#define USB_EP_TX_ERROR_EP1_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_TX_ERROR_EP0 +#define USB_EP_TX_ERROR_EP0_RESET _u(0x0) +#define USB_EP_TX_ERROR_EP0_BITS _u(0x00000003) +#define USB_EP_TX_ERROR_EP0_MSB _u(1) +#define USB_EP_TX_ERROR_EP0_LSB _u(0) +#define USB_EP_TX_ERROR_EP0_ACCESS "WC" +// ============================================================================= +// Register : USB_EP_RX_ERROR +// Description : RX error count for each endpoint. Write to each field to reset +// the counter to 0. +#define USB_EP_RX_ERROR_OFFSET _u(0x00000110) +#define USB_EP_RX_ERROR_BITS _u(0xffffffff) +#define USB_EP_RX_ERROR_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP15_SEQ +#define USB_EP_RX_ERROR_EP15_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP15_SEQ_BITS _u(0x80000000) +#define USB_EP_RX_ERROR_EP15_SEQ_MSB _u(31) +#define USB_EP_RX_ERROR_EP15_SEQ_LSB _u(31) +#define USB_EP_RX_ERROR_EP15_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP15_TRANSACTION +#define USB_EP_RX_ERROR_EP15_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP15_TRANSACTION_BITS _u(0x40000000) +#define USB_EP_RX_ERROR_EP15_TRANSACTION_MSB _u(30) +#define USB_EP_RX_ERROR_EP15_TRANSACTION_LSB _u(30) +#define USB_EP_RX_ERROR_EP15_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP14_SEQ +#define USB_EP_RX_ERROR_EP14_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP14_SEQ_BITS _u(0x20000000) +#define USB_EP_RX_ERROR_EP14_SEQ_MSB _u(29) +#define USB_EP_RX_ERROR_EP14_SEQ_LSB _u(29) +#define USB_EP_RX_ERROR_EP14_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP14_TRANSACTION +#define USB_EP_RX_ERROR_EP14_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP14_TRANSACTION_BITS _u(0x10000000) +#define USB_EP_RX_ERROR_EP14_TRANSACTION_MSB _u(28) +#define USB_EP_RX_ERROR_EP14_TRANSACTION_LSB _u(28) +#define USB_EP_RX_ERROR_EP14_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP13_SEQ +#define USB_EP_RX_ERROR_EP13_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP13_SEQ_BITS _u(0x08000000) +#define USB_EP_RX_ERROR_EP13_SEQ_MSB _u(27) +#define USB_EP_RX_ERROR_EP13_SEQ_LSB _u(27) +#define USB_EP_RX_ERROR_EP13_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP13_TRANSACTION +#define USB_EP_RX_ERROR_EP13_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP13_TRANSACTION_BITS _u(0x04000000) +#define USB_EP_RX_ERROR_EP13_TRANSACTION_MSB _u(26) +#define USB_EP_RX_ERROR_EP13_TRANSACTION_LSB _u(26) +#define USB_EP_RX_ERROR_EP13_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP12_SEQ +#define USB_EP_RX_ERROR_EP12_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP12_SEQ_BITS _u(0x02000000) +#define USB_EP_RX_ERROR_EP12_SEQ_MSB _u(25) +#define USB_EP_RX_ERROR_EP12_SEQ_LSB _u(25) +#define USB_EP_RX_ERROR_EP12_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP12_TRANSACTION +#define USB_EP_RX_ERROR_EP12_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP12_TRANSACTION_BITS _u(0x01000000) +#define USB_EP_RX_ERROR_EP12_TRANSACTION_MSB _u(24) +#define USB_EP_RX_ERROR_EP12_TRANSACTION_LSB _u(24) +#define USB_EP_RX_ERROR_EP12_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP11_SEQ +#define USB_EP_RX_ERROR_EP11_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP11_SEQ_BITS _u(0x00800000) +#define USB_EP_RX_ERROR_EP11_SEQ_MSB _u(23) +#define USB_EP_RX_ERROR_EP11_SEQ_LSB _u(23) +#define USB_EP_RX_ERROR_EP11_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP11_TRANSACTION +#define USB_EP_RX_ERROR_EP11_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP11_TRANSACTION_BITS _u(0x00400000) +#define USB_EP_RX_ERROR_EP11_TRANSACTION_MSB _u(22) +#define USB_EP_RX_ERROR_EP11_TRANSACTION_LSB _u(22) +#define USB_EP_RX_ERROR_EP11_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP10_SEQ +#define USB_EP_RX_ERROR_EP10_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP10_SEQ_BITS _u(0x00200000) +#define USB_EP_RX_ERROR_EP10_SEQ_MSB _u(21) +#define USB_EP_RX_ERROR_EP10_SEQ_LSB _u(21) +#define USB_EP_RX_ERROR_EP10_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP10_TRANSACTION +#define USB_EP_RX_ERROR_EP10_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP10_TRANSACTION_BITS _u(0x00100000) +#define USB_EP_RX_ERROR_EP10_TRANSACTION_MSB _u(20) +#define USB_EP_RX_ERROR_EP10_TRANSACTION_LSB _u(20) +#define USB_EP_RX_ERROR_EP10_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP9_SEQ +#define USB_EP_RX_ERROR_EP9_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP9_SEQ_BITS _u(0x00080000) +#define USB_EP_RX_ERROR_EP9_SEQ_MSB _u(19) +#define USB_EP_RX_ERROR_EP9_SEQ_LSB _u(19) +#define USB_EP_RX_ERROR_EP9_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP9_TRANSACTION +#define USB_EP_RX_ERROR_EP9_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP9_TRANSACTION_BITS _u(0x00040000) +#define USB_EP_RX_ERROR_EP9_TRANSACTION_MSB _u(18) +#define USB_EP_RX_ERROR_EP9_TRANSACTION_LSB _u(18) +#define USB_EP_RX_ERROR_EP9_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP8_SEQ +#define USB_EP_RX_ERROR_EP8_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP8_SEQ_BITS _u(0x00020000) +#define USB_EP_RX_ERROR_EP8_SEQ_MSB _u(17) +#define USB_EP_RX_ERROR_EP8_SEQ_LSB _u(17) +#define USB_EP_RX_ERROR_EP8_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP8_TRANSACTION +#define USB_EP_RX_ERROR_EP8_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP8_TRANSACTION_BITS _u(0x00010000) +#define USB_EP_RX_ERROR_EP8_TRANSACTION_MSB _u(16) +#define USB_EP_RX_ERROR_EP8_TRANSACTION_LSB _u(16) +#define USB_EP_RX_ERROR_EP8_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP7_SEQ +#define USB_EP_RX_ERROR_EP7_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP7_SEQ_BITS _u(0x00008000) +#define USB_EP_RX_ERROR_EP7_SEQ_MSB _u(15) +#define USB_EP_RX_ERROR_EP7_SEQ_LSB _u(15) +#define USB_EP_RX_ERROR_EP7_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP7_TRANSACTION +#define USB_EP_RX_ERROR_EP7_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP7_TRANSACTION_BITS _u(0x00004000) +#define USB_EP_RX_ERROR_EP7_TRANSACTION_MSB _u(14) +#define USB_EP_RX_ERROR_EP7_TRANSACTION_LSB _u(14) +#define USB_EP_RX_ERROR_EP7_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP6_SEQ +#define USB_EP_RX_ERROR_EP6_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP6_SEQ_BITS _u(0x00002000) +#define USB_EP_RX_ERROR_EP6_SEQ_MSB _u(13) +#define USB_EP_RX_ERROR_EP6_SEQ_LSB _u(13) +#define USB_EP_RX_ERROR_EP6_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP6_TRANSACTION +#define USB_EP_RX_ERROR_EP6_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP6_TRANSACTION_BITS _u(0x00001000) +#define USB_EP_RX_ERROR_EP6_TRANSACTION_MSB _u(12) +#define USB_EP_RX_ERROR_EP6_TRANSACTION_LSB _u(12) +#define USB_EP_RX_ERROR_EP6_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP5_SEQ +#define USB_EP_RX_ERROR_EP5_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP5_SEQ_BITS _u(0x00000800) +#define USB_EP_RX_ERROR_EP5_SEQ_MSB _u(11) +#define USB_EP_RX_ERROR_EP5_SEQ_LSB _u(11) +#define USB_EP_RX_ERROR_EP5_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP5_TRANSACTION +#define USB_EP_RX_ERROR_EP5_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP5_TRANSACTION_BITS _u(0x00000400) +#define USB_EP_RX_ERROR_EP5_TRANSACTION_MSB _u(10) +#define USB_EP_RX_ERROR_EP5_TRANSACTION_LSB _u(10) +#define USB_EP_RX_ERROR_EP5_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP4_SEQ +#define USB_EP_RX_ERROR_EP4_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP4_SEQ_BITS _u(0x00000200) +#define USB_EP_RX_ERROR_EP4_SEQ_MSB _u(9) +#define USB_EP_RX_ERROR_EP4_SEQ_LSB _u(9) +#define USB_EP_RX_ERROR_EP4_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP4_TRANSACTION +#define USB_EP_RX_ERROR_EP4_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP4_TRANSACTION_BITS _u(0x00000100) +#define USB_EP_RX_ERROR_EP4_TRANSACTION_MSB _u(8) +#define USB_EP_RX_ERROR_EP4_TRANSACTION_LSB _u(8) +#define USB_EP_RX_ERROR_EP4_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP3_SEQ +#define USB_EP_RX_ERROR_EP3_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP3_SEQ_BITS _u(0x00000080) +#define USB_EP_RX_ERROR_EP3_SEQ_MSB _u(7) +#define USB_EP_RX_ERROR_EP3_SEQ_LSB _u(7) +#define USB_EP_RX_ERROR_EP3_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP3_TRANSACTION +#define USB_EP_RX_ERROR_EP3_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP3_TRANSACTION_BITS _u(0x00000040) +#define USB_EP_RX_ERROR_EP3_TRANSACTION_MSB _u(6) +#define USB_EP_RX_ERROR_EP3_TRANSACTION_LSB _u(6) +#define USB_EP_RX_ERROR_EP3_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP2_SEQ +#define USB_EP_RX_ERROR_EP2_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP2_SEQ_BITS _u(0x00000020) +#define USB_EP_RX_ERROR_EP2_SEQ_MSB _u(5) +#define USB_EP_RX_ERROR_EP2_SEQ_LSB _u(5) +#define USB_EP_RX_ERROR_EP2_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP2_TRANSACTION +#define USB_EP_RX_ERROR_EP2_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP2_TRANSACTION_BITS _u(0x00000010) +#define USB_EP_RX_ERROR_EP2_TRANSACTION_MSB _u(4) +#define USB_EP_RX_ERROR_EP2_TRANSACTION_LSB _u(4) +#define USB_EP_RX_ERROR_EP2_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP1_SEQ +#define USB_EP_RX_ERROR_EP1_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP1_SEQ_BITS _u(0x00000008) +#define USB_EP_RX_ERROR_EP1_SEQ_MSB _u(3) +#define USB_EP_RX_ERROR_EP1_SEQ_LSB _u(3) +#define USB_EP_RX_ERROR_EP1_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP1_TRANSACTION +#define USB_EP_RX_ERROR_EP1_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP1_TRANSACTION_BITS _u(0x00000004) +#define USB_EP_RX_ERROR_EP1_TRANSACTION_MSB _u(2) +#define USB_EP_RX_ERROR_EP1_TRANSACTION_LSB _u(2) +#define USB_EP_RX_ERROR_EP1_TRANSACTION_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP0_SEQ +#define USB_EP_RX_ERROR_EP0_SEQ_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP0_SEQ_BITS _u(0x00000002) +#define USB_EP_RX_ERROR_EP0_SEQ_MSB _u(1) +#define USB_EP_RX_ERROR_EP0_SEQ_LSB _u(1) +#define USB_EP_RX_ERROR_EP0_SEQ_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_EP_RX_ERROR_EP0_TRANSACTION +#define USB_EP_RX_ERROR_EP0_TRANSACTION_RESET _u(0x0) +#define USB_EP_RX_ERROR_EP0_TRANSACTION_BITS _u(0x00000001) +#define USB_EP_RX_ERROR_EP0_TRANSACTION_MSB _u(0) +#define USB_EP_RX_ERROR_EP0_TRANSACTION_LSB _u(0) +#define USB_EP_RX_ERROR_EP0_TRANSACTION_ACCESS "WC" +// ============================================================================= +// Register : USB_DEV_SM_WATCHDOG +// Description : Watchdog that forces the device state machine to idle and +// raises an interrupt if the device stays in a state that isn't +// idle for the configured limit. The counter is reset on every +// state transition. +// Set limit while enable is low and then set the enable. +#define USB_DEV_SM_WATCHDOG_OFFSET _u(0x00000114) +#define USB_DEV_SM_WATCHDOG_BITS _u(0x001fffff) +#define USB_DEV_SM_WATCHDOG_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : USB_DEV_SM_WATCHDOG_FIRED +#define USB_DEV_SM_WATCHDOG_FIRED_RESET _u(0x0) +#define USB_DEV_SM_WATCHDOG_FIRED_BITS _u(0x00100000) +#define USB_DEV_SM_WATCHDOG_FIRED_MSB _u(20) +#define USB_DEV_SM_WATCHDOG_FIRED_LSB _u(20) +#define USB_DEV_SM_WATCHDOG_FIRED_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : USB_DEV_SM_WATCHDOG_RESET +// Description : Set to 1 to forcibly reset the device state machine on watchdog +// expiry +#define USB_DEV_SM_WATCHDOG_RESET_RESET _u(0x0) +#define USB_DEV_SM_WATCHDOG_RESET_BITS _u(0x00080000) +#define USB_DEV_SM_WATCHDOG_RESET_MSB _u(19) +#define USB_DEV_SM_WATCHDOG_RESET_LSB _u(19) +#define USB_DEV_SM_WATCHDOG_RESET_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEV_SM_WATCHDOG_ENABLE +#define USB_DEV_SM_WATCHDOG_ENABLE_RESET _u(0x0) +#define USB_DEV_SM_WATCHDOG_ENABLE_BITS _u(0x00040000) +#define USB_DEV_SM_WATCHDOG_ENABLE_MSB _u(18) +#define USB_DEV_SM_WATCHDOG_ENABLE_LSB _u(18) +#define USB_DEV_SM_WATCHDOG_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : USB_DEV_SM_WATCHDOG_LIMIT +#define USB_DEV_SM_WATCHDOG_LIMIT_RESET _u(0x00000) +#define USB_DEV_SM_WATCHDOG_LIMIT_BITS _u(0x0003ffff) +#define USB_DEV_SM_WATCHDOG_LIMIT_MSB _u(17) +#define USB_DEV_SM_WATCHDOG_LIMIT_LSB _u(0) +#define USB_DEV_SM_WATCHDOG_LIMIT_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_USB_H + diff --git a/lib/rp2040/hardware/regs/usb_device_dpram.h b/lib/pico-sdk/rp2350/hardware/regs/usb_device_dpram.h similarity index 95% rename from lib/rp2040/hardware/regs/usb_device_dpram.h rename to lib/pico-sdk/rp2350/hardware/regs/usb_device_dpram.h index 6422774c4908..27203f4e1955 100644 --- a/lib/rp2040/hardware/regs/usb_device_dpram.h +++ b/lib/pico-sdk/rp2350/hardware/regs/usb_device_dpram.h @@ -1,5 +1,7 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + /** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. + * Copyright (c) 2024 Raspberry Pi Ltd. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,8 +11,8 @@ // Bus type : ahbl // Description : DPRAM layout for USB device. // ============================================================================= -#ifndef HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED -#define HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED +#ifndef _HARDWARE_REGS_USB_DEVICE_DPRAM_H +#define _HARDWARE_REGS_USB_DEVICE_DPRAM_H // ============================================================================= // Register : USB_DEVICE_DPRAM_SETUP_PACKET_LOW // Description : Bytes 0-3 of the SETUP packet from the host. @@ -19,7 +21,6 @@ #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE -// Description : None #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_RESET _u(0x0000) #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_BITS _u(0xffff0000) #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_MSB _u(31) @@ -27,7 +28,6 @@ #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST -// Description : None #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_RESET _u(0x00) #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_BITS _u(0x0000ff00) #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_MSB _u(15) @@ -35,7 +35,6 @@ #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE -// Description : None #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_RESET _u(0x00) #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_BITS _u(0x000000ff) #define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_MSB _u(7) @@ -49,7 +48,6 @@ #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_RESET _u(0x00000000) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH -// Description : None #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_RESET _u(0x0000) #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_BITS _u(0xffff0000) #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_MSB _u(31) @@ -57,7 +55,6 @@ #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX -// Description : None #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_RESET _u(0x0000) #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_BITS _u(0x0000ffff) #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_MSB _u(15) @@ -65,7 +62,6 @@ #define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP1_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_OFFSET _u(0x00000008) #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_RESET _u(0x00000000) @@ -105,19 +101,19 @@ #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -146,7 +142,6 @@ #define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP1_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_OFFSET _u(0x0000000c) #define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_RESET _u(0x00000000) @@ -186,19 +181,19 @@ #define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -227,7 +222,6 @@ #define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP2_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP2_IN_CONTROL_OFFSET _u(0x00000010) #define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP2_IN_CONTROL_RESET _u(0x00000000) @@ -267,19 +261,19 @@ #define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -308,7 +302,6 @@ #define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP2_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_OFFSET _u(0x00000014) #define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_RESET _u(0x00000000) @@ -348,19 +341,19 @@ #define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -389,7 +382,6 @@ #define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP3_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP3_IN_CONTROL_OFFSET _u(0x00000018) #define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP3_IN_CONTROL_RESET _u(0x00000000) @@ -429,19 +421,19 @@ #define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -470,7 +462,6 @@ #define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP3_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_OFFSET _u(0x0000001c) #define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_RESET _u(0x00000000) @@ -510,19 +501,19 @@ #define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -551,7 +542,6 @@ #define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP4_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP4_IN_CONTROL_OFFSET _u(0x00000020) #define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP4_IN_CONTROL_RESET _u(0x00000000) @@ -591,19 +581,19 @@ #define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -632,7 +622,6 @@ #define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP4_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_OFFSET _u(0x00000024) #define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_RESET _u(0x00000000) @@ -672,19 +661,19 @@ #define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -713,7 +702,6 @@ #define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP5_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP5_IN_CONTROL_OFFSET _u(0x00000028) #define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP5_IN_CONTROL_RESET _u(0x00000000) @@ -753,19 +741,19 @@ #define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -794,7 +782,6 @@ #define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP5_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_OFFSET _u(0x0000002c) #define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_RESET _u(0x00000000) @@ -834,19 +821,19 @@ #define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -875,7 +862,6 @@ #define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP6_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP6_IN_CONTROL_OFFSET _u(0x00000030) #define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP6_IN_CONTROL_RESET _u(0x00000000) @@ -915,19 +901,19 @@ #define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -956,7 +942,6 @@ #define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP6_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_OFFSET _u(0x00000034) #define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_RESET _u(0x00000000) @@ -996,19 +981,19 @@ #define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1037,7 +1022,6 @@ #define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP7_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP7_IN_CONTROL_OFFSET _u(0x00000038) #define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP7_IN_CONTROL_RESET _u(0x00000000) @@ -1077,19 +1061,19 @@ #define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1118,7 +1102,6 @@ #define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP7_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_OFFSET _u(0x0000003c) #define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_RESET _u(0x00000000) @@ -1158,19 +1141,19 @@ #define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1199,7 +1182,6 @@ #define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP8_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP8_IN_CONTROL_OFFSET _u(0x00000040) #define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP8_IN_CONTROL_RESET _u(0x00000000) @@ -1239,19 +1221,19 @@ #define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1280,7 +1262,6 @@ #define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP8_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_OFFSET _u(0x00000044) #define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_RESET _u(0x00000000) @@ -1320,19 +1301,19 @@ #define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1361,7 +1342,6 @@ #define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP9_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP9_IN_CONTROL_OFFSET _u(0x00000048) #define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP9_IN_CONTROL_RESET _u(0x00000000) @@ -1401,19 +1381,19 @@ #define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1442,7 +1422,6 @@ #define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP9_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_OFFSET _u(0x0000004c) #define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_RESET _u(0x00000000) @@ -1482,19 +1461,19 @@ #define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1523,7 +1502,6 @@ #define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP10_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP10_IN_CONTROL_OFFSET _u(0x00000050) #define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP10_IN_CONTROL_RESET _u(0x00000000) @@ -1563,19 +1541,19 @@ #define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1604,7 +1582,6 @@ #define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP10_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_OFFSET _u(0x00000054) #define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_RESET _u(0x00000000) @@ -1644,19 +1621,19 @@ #define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1685,7 +1662,6 @@ #define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP11_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP11_IN_CONTROL_OFFSET _u(0x00000058) #define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP11_IN_CONTROL_RESET _u(0x00000000) @@ -1725,19 +1701,19 @@ #define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1766,7 +1742,6 @@ #define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP11_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_OFFSET _u(0x0000005c) #define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_RESET _u(0x00000000) @@ -1806,19 +1781,19 @@ #define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1847,7 +1822,6 @@ #define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP12_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP12_IN_CONTROL_OFFSET _u(0x00000060) #define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP12_IN_CONTROL_RESET _u(0x00000000) @@ -1887,19 +1861,19 @@ #define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -1928,7 +1902,6 @@ #define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP12_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_OFFSET _u(0x00000064) #define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_RESET _u(0x00000000) @@ -1968,19 +1941,19 @@ #define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -2009,7 +1982,6 @@ #define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP13_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP13_IN_CONTROL_OFFSET _u(0x00000068) #define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP13_IN_CONTROL_RESET _u(0x00000000) @@ -2049,19 +2021,19 @@ #define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -2090,7 +2062,6 @@ #define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP13_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_OFFSET _u(0x0000006c) #define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_RESET _u(0x00000000) @@ -2130,19 +2101,19 @@ #define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -2171,7 +2142,6 @@ #define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP14_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP14_IN_CONTROL_OFFSET _u(0x00000070) #define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP14_IN_CONTROL_RESET _u(0x00000000) @@ -2211,19 +2181,19 @@ #define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -2252,7 +2222,6 @@ #define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP14_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_OFFSET _u(0x00000074) #define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_RESET _u(0x00000000) @@ -2292,19 +2261,19 @@ #define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -2333,7 +2302,6 @@ #define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP15_IN_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP15_IN_CONTROL_OFFSET _u(0x00000078) #define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP15_IN_CONTROL_RESET _u(0x00000000) @@ -2373,19 +2341,19 @@ #define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -2414,7 +2382,6 @@ #define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW" // ============================================================================= // Register : USB_DEVICE_DPRAM_EP15_OUT_CONTROL -// Description : None #define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_OFFSET _u(0x0000007c) #define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BITS _u(0xfc03ffff) #define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_RESET _u(0x00000000) @@ -2454,19 +2421,19 @@ #define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE -// Description : 0x0 -> Control +// 0x0 -> Control // 0x1 -> Isochronous // 0x2 -> Bulk // 0x3 -> Interrupt -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0) #define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) -#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2) +#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL // Description : Trigger an interrupt if a STALL is sent. Intended for debug @@ -2539,14 +2506,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -2664,8 +2631,7 @@ #define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -2674,14 +2640,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -2808,14 +2774,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -2933,8 +2899,7 @@ #define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -2943,14 +2908,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -3077,14 +3042,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -3202,8 +3167,7 @@ #define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -3212,14 +3176,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -3346,14 +3310,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -3471,8 +3435,7 @@ #define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -3481,14 +3444,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -3615,14 +3578,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -3740,8 +3703,7 @@ #define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -3750,14 +3712,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -3884,14 +3846,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -4009,8 +3971,7 @@ #define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -4019,14 +3980,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -4153,14 +4114,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -4278,8 +4239,7 @@ #define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -4288,14 +4248,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -4422,14 +4382,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -4547,8 +4507,7 @@ #define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -4557,14 +4516,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -4691,14 +4650,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -4816,8 +4775,7 @@ #define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -4826,14 +4784,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -4960,14 +4918,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -5085,8 +5043,7 @@ #define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -5095,14 +5052,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -5220,8 +5177,7 @@ #define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -5230,14 +5186,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -5355,8 +5311,7 @@ #define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS -// ET +// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -5365,14 +5320,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -5490,8 +5445,7 @@ #define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -5500,14 +5454,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -5625,8 +5579,7 @@ #define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS -// ET +// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -5635,14 +5588,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -5760,8 +5713,7 @@ #define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -5770,14 +5722,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -5895,8 +5847,7 @@ #define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS -// ET +// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -5905,14 +5856,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -6030,8 +5981,7 @@ #define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -6040,14 +5990,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -6165,8 +6115,7 @@ #define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS -// ET +// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -6175,14 +6124,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -6300,8 +6249,7 @@ #define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -6310,14 +6258,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -6435,8 +6383,7 @@ #define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS -// ET +// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -6445,14 +6392,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -6570,8 +6517,7 @@ #define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE -// T +// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -6580,14 +6526,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1 @@ -6705,8 +6651,7 @@ #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_LSB _u(29) #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW" // ----------------------------------------------------------------------------- -// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS -// ET +// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET // Description : The number of bytes buffer 1 is offset from buffer 0 in // Isochronous mode. Only valid in double buffered mode for an // Isochronous endpoint. @@ -6715,14 +6660,14 @@ // 0x1 -> 256 // 0x2 -> 512 // 0x3 -> 1024 -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) -#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW" +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1) +#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2) #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3) // ----------------------------------------------------------------------------- // Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1 @@ -6804,4 +6749,5 @@ #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0) #define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW" // ============================================================================= -#endif // HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED +#endif // _HARDWARE_REGS_USB_DEVICE_DPRAM_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/watchdog.h b/lib/pico-sdk/rp2350/hardware/regs/watchdog.h new file mode 100644 index 000000000000..07e5b405e0fa --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/watchdog.h @@ -0,0 +1,192 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : WATCHDOG +// Version : 1 +// Bus type : apb +// ============================================================================= +#ifndef _HARDWARE_REGS_WATCHDOG_H +#define _HARDWARE_REGS_WATCHDOG_H +// ============================================================================= +// Register : WATCHDOG_CTRL +// Description : Watchdog control +// The rst_wdsel register determines which subsystems are reset +// when the watchdog is triggered. +// The watchdog can be triggered in software. +#define WATCHDOG_CTRL_OFFSET _u(0x00000000) +#define WATCHDOG_CTRL_BITS _u(0xc7ffffff) +#define WATCHDOG_CTRL_RESET _u(0x07000000) +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_TRIGGER +// Description : Trigger a watchdog reset +#define WATCHDOG_CTRL_TRIGGER_RESET _u(0x0) +#define WATCHDOG_CTRL_TRIGGER_BITS _u(0x80000000) +#define WATCHDOG_CTRL_TRIGGER_MSB _u(31) +#define WATCHDOG_CTRL_TRIGGER_LSB _u(31) +#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_ENABLE +// Description : When not enabled the watchdog timer is paused +#define WATCHDOG_CTRL_ENABLE_RESET _u(0x0) +#define WATCHDOG_CTRL_ENABLE_BITS _u(0x40000000) +#define WATCHDOG_CTRL_ENABLE_MSB _u(30) +#define WATCHDOG_CTRL_ENABLE_LSB _u(30) +#define WATCHDOG_CTRL_ENABLE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_PAUSE_DBG1 +// Description : Pause the watchdog timer when processor 1 is in debug mode +#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _u(0x1) +#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _u(0x04000000) +#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _u(26) +#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _u(26) +#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_PAUSE_DBG0 +// Description : Pause the watchdog timer when processor 0 is in debug mode +#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _u(0x1) +#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _u(0x02000000) +#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _u(25) +#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _u(25) +#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_PAUSE_JTAG +// Description : Pause the watchdog timer when JTAG is accessing the bus fabric +#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _u(0x1) +#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _u(0x01000000) +#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _u(24) +#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _u(24) +#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_CTRL_TIME +// Description : Indicates the time in usec before a watchdog reset will be +// triggered +#define WATCHDOG_CTRL_TIME_RESET _u(0x000000) +#define WATCHDOG_CTRL_TIME_BITS _u(0x00ffffff) +#define WATCHDOG_CTRL_TIME_MSB _u(23) +#define WATCHDOG_CTRL_TIME_LSB _u(0) +#define WATCHDOG_CTRL_TIME_ACCESS "RO" +// ============================================================================= +// Register : WATCHDOG_LOAD +// Description : Load the watchdog timer. The maximum setting is 0xffffff which +// corresponds to approximately 16 seconds. +#define WATCHDOG_LOAD_OFFSET _u(0x00000004) +#define WATCHDOG_LOAD_BITS _u(0x00ffffff) +#define WATCHDOG_LOAD_RESET _u(0x00000000) +#define WATCHDOG_LOAD_MSB _u(23) +#define WATCHDOG_LOAD_LSB _u(0) +#define WATCHDOG_LOAD_ACCESS "WF" +// ============================================================================= +// Register : WATCHDOG_REASON +// Description : Logs the reason for the last reset. Both bits are zero for the +// case of a hardware reset. +// +// Additionally, as of RP2350, a debugger warm reset of either +// core (SYSRESETREQ or hartreset) will also clear the watchdog +// reason register, so that software loaded under the debugger +// following a watchdog timeout will not continue to see the +// timeout condition. +#define WATCHDOG_REASON_OFFSET _u(0x00000008) +#define WATCHDOG_REASON_BITS _u(0x00000003) +#define WATCHDOG_REASON_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_REASON_FORCE +#define WATCHDOG_REASON_FORCE_RESET _u(0x0) +#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002) +#define WATCHDOG_REASON_FORCE_MSB _u(1) +#define WATCHDOG_REASON_FORCE_LSB _u(1) +#define WATCHDOG_REASON_FORCE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : WATCHDOG_REASON_TIMER +#define WATCHDOG_REASON_TIMER_RESET _u(0x0) +#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001) +#define WATCHDOG_REASON_TIMER_MSB _u(0) +#define WATCHDOG_REASON_TIMER_LSB _u(0) +#define WATCHDOG_REASON_TIMER_ACCESS "RO" +// ============================================================================= +// Register : WATCHDOG_SCRATCH0 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c) +#define WATCHDOG_SCRATCH0_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH0_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH0_MSB _u(31) +#define WATCHDOG_SCRATCH0_LSB _u(0) +#define WATCHDOG_SCRATCH0_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH1 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010) +#define WATCHDOG_SCRATCH1_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH1_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH1_MSB _u(31) +#define WATCHDOG_SCRATCH1_LSB _u(0) +#define WATCHDOG_SCRATCH1_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH2 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014) +#define WATCHDOG_SCRATCH2_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH2_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH2_MSB _u(31) +#define WATCHDOG_SCRATCH2_LSB _u(0) +#define WATCHDOG_SCRATCH2_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH3 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018) +#define WATCHDOG_SCRATCH3_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH3_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH3_MSB _u(31) +#define WATCHDOG_SCRATCH3_LSB _u(0) +#define WATCHDOG_SCRATCH3_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH4 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c) +#define WATCHDOG_SCRATCH4_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH4_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH4_MSB _u(31) +#define WATCHDOG_SCRATCH4_LSB _u(0) +#define WATCHDOG_SCRATCH4_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH5 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020) +#define WATCHDOG_SCRATCH5_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH5_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH5_MSB _u(31) +#define WATCHDOG_SCRATCH5_LSB _u(0) +#define WATCHDOG_SCRATCH5_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH6 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024) +#define WATCHDOG_SCRATCH6_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH6_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH6_MSB _u(31) +#define WATCHDOG_SCRATCH6_LSB _u(0) +#define WATCHDOG_SCRATCH6_ACCESS "RW" +// ============================================================================= +// Register : WATCHDOG_SCRATCH7 +// Description : Scratch register. Information persists through soft reset of +// the chip. +#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028) +#define WATCHDOG_SCRATCH7_BITS _u(0xffffffff) +#define WATCHDOG_SCRATCH7_RESET _u(0x00000000) +#define WATCHDOG_SCRATCH7_MSB _u(31) +#define WATCHDOG_SCRATCH7_LSB _u(0) +#define WATCHDOG_SCRATCH7_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_WATCHDOG_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/xip.h b/lib/pico-sdk/rp2350/hardware/regs/xip.h new file mode 100644 index 000000000000..7487ec63f2e7 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/xip.h @@ -0,0 +1,313 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : XIP +// Version : 1 +// Bus type : ahb +// Description : QSPI flash execute-in-place block +// ============================================================================= +#ifndef _HARDWARE_REGS_XIP_H +#define _HARDWARE_REGS_XIP_H +// ============================================================================= +// Register : XIP_CTRL +// Description : Cache control register. Read-only from a Non-secure context. +#define XIP_CTRL_OFFSET _u(0x00000000) +#define XIP_CTRL_BITS _u(0x00000ffb) +#define XIP_CTRL_RESET _u(0x00000083) +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_WRITABLE_M1 +// Description : If 1, enable writes to XIP memory window 1 (addresses +// 0x11000000 through 0x11ffffff, and their uncached mirrors). If +// 0, this region is read-only. +// +// XIP memory is *read-only by default*. This bit must be set to +// enable writes if a RAM device is attached on QSPI chip select +// 1. +// +// The default read-only behaviour avoids two issues with writing +// to a read-only QSPI device (e.g. flash). First, a write will +// initially appear to succeed due to caching, but the data will +// eventually be lost when the written line is evicted, causing +// unpredictable behaviour. +// +// Second, when a written line is evicted, it will cause a write +// command to be issued to the flash, which can break the flash +// out of its continuous read mode. After this point, flash reads +// will return garbage. This is a security concern, as it allows +// Non-secure software to break Secure flash reads if it has +// permission to write to any flash address. +// +// Note the read-only behaviour is implemented by downgrading +// writes to reads, so writes will still cause allocation of an +// address, but have no other effect. +#define XIP_CTRL_WRITABLE_M1_RESET _u(0x0) +#define XIP_CTRL_WRITABLE_M1_BITS _u(0x00000800) +#define XIP_CTRL_WRITABLE_M1_MSB _u(11) +#define XIP_CTRL_WRITABLE_M1_LSB _u(11) +#define XIP_CTRL_WRITABLE_M1_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_WRITABLE_M0 +// Description : If 1, enable writes to XIP memory window 0 (addresses +// 0x10000000 through 0x10ffffff, and their uncached mirrors). If +// 0, this region is read-only. +// +// XIP memory is *read-only by default*. This bit must be set to +// enable writes if a RAM device is attached on QSPI chip select +// 0. +// +// The default read-only behaviour avoids two issues with writing +// to a read-only QSPI device (e.g. flash). First, a write will +// initially appear to succeed due to caching, but the data will +// eventually be lost when the written line is evicted, causing +// unpredictable behaviour. +// +// Second, when a written line is evicted, it will cause a write +// command to be issued to the flash, which can break the flash +// out of its continuous read mode. After this point, flash reads +// will return garbage. This is a security concern, as it allows +// Non-secure software to break Secure flash reads if it has +// permission to write to any flash address. +// +// Note the read-only behaviour is implemented by downgrading +// writes to reads, so writes will still cause allocation of an +// address, but have no other effect. +#define XIP_CTRL_WRITABLE_M0_RESET _u(0x0) +#define XIP_CTRL_WRITABLE_M0_BITS _u(0x00000400) +#define XIP_CTRL_WRITABLE_M0_MSB _u(10) +#define XIP_CTRL_WRITABLE_M0_LSB _u(10) +#define XIP_CTRL_WRITABLE_M0_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_SPLIT_WAYS +// Description : When 1, route all cached+Secure accesses to way 0 of the cache, +// and route all cached+Non-secure accesses to way 1 of the cache. +// +// This partitions the cache into two half-sized direct-mapped +// regions, such that Non-secure code can not observe cache line +// state changes caused by Secure execution. +// +// A full cache flush is required when changing the value of +// SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is +// 0, so that both cache ways are accessible for invalidation. +#define XIP_CTRL_SPLIT_WAYS_RESET _u(0x0) +#define XIP_CTRL_SPLIT_WAYS_BITS _u(0x00000200) +#define XIP_CTRL_SPLIT_WAYS_MSB _u(9) +#define XIP_CTRL_SPLIT_WAYS_LSB _u(9) +#define XIP_CTRL_SPLIT_WAYS_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_MAINT_NONSEC +// Description : When 0, Non-secure accesses to the cache maintenance address +// window (addr[27] == 1, addr[26] == 0) will generate a bus +// error. When 1, Non-secure accesses can perform cache +// maintenance operations by writing to the cache maintenance +// address window. +// +// Cache maintenance operations may be used to corrupt Secure data +// by invalidating cache lines inappropriately, or map Secure +// content into a Non-secure region by pinning cache lines. +// Therefore this bit should generally be set to 0, unless Secure +// code is not using the cache. +// +// Care should also be taken to clear the cache data memory and +// tag memory before granting maintenance operations to Non-secure +// code. +#define XIP_CTRL_MAINT_NONSEC_RESET _u(0x0) +#define XIP_CTRL_MAINT_NONSEC_BITS _u(0x00000100) +#define XIP_CTRL_MAINT_NONSEC_MSB _u(8) +#define XIP_CTRL_MAINT_NONSEC_LSB _u(8) +#define XIP_CTRL_MAINT_NONSEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_NO_UNTRANSLATED_NONSEC +// Description : When 1, Non-secure accesses to the uncached, untranslated +// window (addr[27:26] == 3) will generate a bus error. +#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_RESET _u(0x1) +#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_BITS _u(0x00000080) +#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_MSB _u(7) +#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_LSB _u(7) +#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_NO_UNTRANSLATED_SEC +// Description : When 1, Secure accesses to the uncached, untranslated window +// (addr[27:26] == 3) will generate a bus error. +#define XIP_CTRL_NO_UNTRANSLATED_SEC_RESET _u(0x0) +#define XIP_CTRL_NO_UNTRANSLATED_SEC_BITS _u(0x00000040) +#define XIP_CTRL_NO_UNTRANSLATED_SEC_MSB _u(6) +#define XIP_CTRL_NO_UNTRANSLATED_SEC_LSB _u(6) +#define XIP_CTRL_NO_UNTRANSLATED_SEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_NO_UNCACHED_NONSEC +// Description : When 1, Non-secure accesses to the uncached window (addr[27:26] +// == 1) will generate a bus error. This may reduce the number of +// SAU/MPU/PMP regions required to protect flash contents. +// +// Note this does not disable access to the uncached, untranslated +// window -- see NO_UNTRANSLATED_SEC. +#define XIP_CTRL_NO_UNCACHED_NONSEC_RESET _u(0x0) +#define XIP_CTRL_NO_UNCACHED_NONSEC_BITS _u(0x00000020) +#define XIP_CTRL_NO_UNCACHED_NONSEC_MSB _u(5) +#define XIP_CTRL_NO_UNCACHED_NONSEC_LSB _u(5) +#define XIP_CTRL_NO_UNCACHED_NONSEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_NO_UNCACHED_SEC +// Description : When 1, Secure accesses to the uncached window (addr[27:26] == +// 1) will generate a bus error. This may reduce the number of +// SAU/MPU/PMP regions required to protect flash contents. +// +// Note this does not disable access to the uncached, untranslated +// window -- see NO_UNTRANSLATED_SEC. +#define XIP_CTRL_NO_UNCACHED_SEC_RESET _u(0x0) +#define XIP_CTRL_NO_UNCACHED_SEC_BITS _u(0x00000010) +#define XIP_CTRL_NO_UNCACHED_SEC_MSB _u(4) +#define XIP_CTRL_NO_UNCACHED_SEC_LSB _u(4) +#define XIP_CTRL_NO_UNCACHED_SEC_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_POWER_DOWN +// Description : When 1, the cache memories are powered down. They retain state, +// but can not be accessed. This reduces static power dissipation. +// Writing 1 to this bit forces CTRL_EN_SECURE and +// CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when +// powered down. +#define XIP_CTRL_POWER_DOWN_RESET _u(0x0) +#define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008) +#define XIP_CTRL_POWER_DOWN_MSB _u(3) +#define XIP_CTRL_POWER_DOWN_LSB _u(3) +#define XIP_CTRL_POWER_DOWN_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_EN_NONSECURE +// Description : When 1, enable the cache for Non-secure accesses. When enabled, +// Non-secure XIP accesses to the cached (addr[26] == 0) window +// will query the cache, and QSPI accesses are performed only if +// the requested data is not present. When disabled, Secure access +// ignore the cache contents, and always access the QSPI +// interface. +// +// Accesses to the uncached (addr[26] == 1) window will never +// query the cache, irrespective of this bit. +#define XIP_CTRL_EN_NONSECURE_RESET _u(0x1) +#define XIP_CTRL_EN_NONSECURE_BITS _u(0x00000002) +#define XIP_CTRL_EN_NONSECURE_MSB _u(1) +#define XIP_CTRL_EN_NONSECURE_LSB _u(1) +#define XIP_CTRL_EN_NONSECURE_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XIP_CTRL_EN_SECURE +// Description : When 1, enable the cache for Secure accesses. When enabled, +// Secure XIP accesses to the cached (addr[26] == 0) window will +// query the cache, and QSPI accesses are performed only if the +// requested data is not present. When disabled, Secure access +// ignore the cache contents, and always access the QSPI +// interface. +// +// Accesses to the uncached (addr[26] == 1) window will never +// query the cache, irrespective of this bit. +// +// There is no cache-as-SRAM address window. Cache lines are +// allocated for SRAM-like use by individually pinning them, and +// keeping the cache enabled. +#define XIP_CTRL_EN_SECURE_RESET _u(0x1) +#define XIP_CTRL_EN_SECURE_BITS _u(0x00000001) +#define XIP_CTRL_EN_SECURE_MSB _u(0) +#define XIP_CTRL_EN_SECURE_LSB _u(0) +#define XIP_CTRL_EN_SECURE_ACCESS "RW" +// ============================================================================= +// Register : XIP_STAT +#define XIP_STAT_OFFSET _u(0x00000008) +#define XIP_STAT_BITS _u(0x00000006) +#define XIP_STAT_RESET _u(0x00000002) +// ----------------------------------------------------------------------------- +// Field : XIP_STAT_FIFO_FULL +// Description : When 1, indicates the XIP streaming FIFO is completely full. +// The streaming FIFO is 2 entries deep, so the full and empty +// flag allow its level to be ascertained. +#define XIP_STAT_FIFO_FULL_RESET _u(0x0) +#define XIP_STAT_FIFO_FULL_BITS _u(0x00000004) +#define XIP_STAT_FIFO_FULL_MSB _u(2) +#define XIP_STAT_FIFO_FULL_LSB _u(2) +#define XIP_STAT_FIFO_FULL_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : XIP_STAT_FIFO_EMPTY +// Description : When 1, indicates the XIP streaming FIFO is completely empty. +#define XIP_STAT_FIFO_EMPTY_RESET _u(0x1) +#define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002) +#define XIP_STAT_FIFO_EMPTY_MSB _u(1) +#define XIP_STAT_FIFO_EMPTY_LSB _u(1) +#define XIP_STAT_FIFO_EMPTY_ACCESS "RO" +// ============================================================================= +// Register : XIP_CTR_HIT +// Description : Cache Hit counter +// A 32 bit saturating counter that increments upon each cache +// hit, +// i.e. when an XIP access is serviced directly from cached data. +// Write any value to clear. +#define XIP_CTR_HIT_OFFSET _u(0x0000000c) +#define XIP_CTR_HIT_BITS _u(0xffffffff) +#define XIP_CTR_HIT_RESET _u(0x00000000) +#define XIP_CTR_HIT_MSB _u(31) +#define XIP_CTR_HIT_LSB _u(0) +#define XIP_CTR_HIT_ACCESS "WC" +// ============================================================================= +// Register : XIP_CTR_ACC +// Description : Cache Access counter +// A 32 bit saturating counter that increments upon each XIP +// access, +// whether the cache is hit or not. This includes noncacheable +// accesses. +// Write any value to clear. +#define XIP_CTR_ACC_OFFSET _u(0x00000010) +#define XIP_CTR_ACC_BITS _u(0xffffffff) +#define XIP_CTR_ACC_RESET _u(0x00000000) +#define XIP_CTR_ACC_MSB _u(31) +#define XIP_CTR_ACC_LSB _u(0) +#define XIP_CTR_ACC_ACCESS "WC" +// ============================================================================= +// Register : XIP_STREAM_ADDR +// Description : FIFO stream address +// The address of the next word to be streamed from flash to the +// streaming FIFO. +// Increments automatically after each flash access. +// Write the initial access address here before starting a +// streaming read. +#define XIP_STREAM_ADDR_OFFSET _u(0x00000014) +#define XIP_STREAM_ADDR_BITS _u(0xfffffffc) +#define XIP_STREAM_ADDR_RESET _u(0x00000000) +#define XIP_STREAM_ADDR_MSB _u(31) +#define XIP_STREAM_ADDR_LSB _u(2) +#define XIP_STREAM_ADDR_ACCESS "RW" +// ============================================================================= +// Register : XIP_STREAM_CTR +// Description : FIFO stream control +// Write a nonzero value to start a streaming read. This will then +// progress in the background, using flash idle cycles to transfer +// a linear data block from flash to the streaming FIFO. +// Decrements automatically (1 at a time) as the stream +// progresses, and halts on reaching 0. +// Write 0 to halt an in-progress stream, and discard any in- +// flight +// read, so that a new stream can immediately be started (after +// draining the FIFO and reinitialising STREAM_ADDR) +#define XIP_STREAM_CTR_OFFSET _u(0x00000018) +#define XIP_STREAM_CTR_BITS _u(0x003fffff) +#define XIP_STREAM_CTR_RESET _u(0x00000000) +#define XIP_STREAM_CTR_MSB _u(21) +#define XIP_STREAM_CTR_LSB _u(0) +#define XIP_STREAM_CTR_ACCESS "RW" +// ============================================================================= +// Register : XIP_STREAM_FIFO +// Description : FIFO stream data +// Streamed data is buffered here, for retrieval by the system +// DMA. +// This FIFO can also be accessed via the XIP_AUX slave, to avoid +// exposing +// the DMA to bus stalls caused by other XIP traffic. +#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c) +#define XIP_STREAM_FIFO_BITS _u(0xffffffff) +#define XIP_STREAM_FIFO_RESET _u(0x00000000) +#define XIP_STREAM_FIFO_MSB _u(31) +#define XIP_STREAM_FIFO_LSB _u(0) +#define XIP_STREAM_FIFO_ACCESS "RF" +// ============================================================================= +#endif // _HARDWARE_REGS_XIP_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/xip_aux.h b/lib/pico-sdk/rp2350/hardware/regs/xip_aux.h new file mode 100644 index 000000000000..07940ca442f0 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/xip_aux.h @@ -0,0 +1,123 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : XIP_AUX +// Version : 1 +// Bus type : ahb +// Description : Auxiliary DMA access to XIP FIFOs, via fast AHB bus access +// ============================================================================= +#ifndef _HARDWARE_REGS_XIP_AUX_H +#define _HARDWARE_REGS_XIP_AUX_H +// ============================================================================= +// Register : XIP_AUX_STREAM +// Description : Read the XIP stream FIFO (fast bus access to +// XIP_CTRL_STREAM_FIFO) +#define XIP_AUX_STREAM_OFFSET _u(0x00000000) +#define XIP_AUX_STREAM_BITS _u(0xffffffff) +#define XIP_AUX_STREAM_RESET _u(0x00000000) +#define XIP_AUX_STREAM_MSB _u(31) +#define XIP_AUX_STREAM_LSB _u(0) +#define XIP_AUX_STREAM_ACCESS "RF" +// ============================================================================= +// Register : XIP_AUX_QMI_DIRECT_TX +// Description : Write to the QMI direct-mode TX FIFO (fast bus access to +// QMI_DIRECT_TX) +#define XIP_AUX_QMI_DIRECT_TX_OFFSET _u(0x00000004) +#define XIP_AUX_QMI_DIRECT_TX_BITS _u(0x001fffff) +#define XIP_AUX_QMI_DIRECT_TX_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : XIP_AUX_QMI_DIRECT_TX_NOPUSH +// Description : Inhibit the RX FIFO push that would correspond to this TX FIFO +// entry. +// +// Useful to avoid garbage appearing in the RX FIFO when pushing +// the command at the beginning of a SPI transfer. +#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_RESET _u(0x0) +#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_BITS _u(0x00100000) +#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_MSB _u(20) +#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_LSB _u(20) +#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_ACCESS "WF" +// ----------------------------------------------------------------------------- +// Field : XIP_AUX_QMI_DIRECT_TX_OE +// Description : Output enable (active-high). For single width (SPI), this field +// is ignored, and SD0 is always set to output, with SD1 always +// set to input. +// +// For dual and quad width (DSPI/QSPI), this sets whether the +// relevant SDx pads are set to output whilst transferring this +// FIFO record. In this case the command/address should have OE +// set, and the data transfer should have OE set or clear +// depending on the direction of the transfer. +#define XIP_AUX_QMI_DIRECT_TX_OE_RESET _u(0x0) +#define XIP_AUX_QMI_DIRECT_TX_OE_BITS _u(0x00080000) +#define XIP_AUX_QMI_DIRECT_TX_OE_MSB _u(19) +#define XIP_AUX_QMI_DIRECT_TX_OE_LSB _u(19) +#define XIP_AUX_QMI_DIRECT_TX_OE_ACCESS "WF" +// ----------------------------------------------------------------------------- +// Field : XIP_AUX_QMI_DIRECT_TX_DWIDTH +// Description : Data width. If 0, hardware will transmit the 8 LSBs of the +// DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs +// of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and +// 16-bit transfers can be mixed freely. +#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_RESET _u(0x0) +#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_BITS _u(0x00040000) +#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_MSB _u(18) +#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_LSB _u(18) +#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_ACCESS "WF" +// ----------------------------------------------------------------------------- +// Field : XIP_AUX_QMI_DIRECT_TX_IWIDTH +// Description : Configure whether this FIFO record is transferred with +// single/dual/quad interface width (0/1/2). Different widths can +// be mixed freely. +// 0x0 -> Single width +// 0x1 -> Dual width +// 0x2 -> Quad width +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_RESET _u(0x0) +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_BITS _u(0x00030000) +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_MSB _u(17) +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_LSB _u(16) +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_ACCESS "WF" +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_S _u(0x0) +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_D _u(0x1) +#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_Q _u(0x2) +// ----------------------------------------------------------------------------- +// Field : XIP_AUX_QMI_DIRECT_TX_DATA +// Description : Data pushed here will be clocked out falling edges of SCK (or +// before the very first rising edge of SCK, if this is the first +// pulse). For each byte clocked out, the interface will +// simultaneously sample one byte, on rising edges of SCK, and +// push this to the DIRECT_RX FIFO. +// +// For 16-bit data, the least-significant byte is transmitted +// first. +#define XIP_AUX_QMI_DIRECT_TX_DATA_RESET _u(0x0000) +#define XIP_AUX_QMI_DIRECT_TX_DATA_BITS _u(0x0000ffff) +#define XIP_AUX_QMI_DIRECT_TX_DATA_MSB _u(15) +#define XIP_AUX_QMI_DIRECT_TX_DATA_LSB _u(0) +#define XIP_AUX_QMI_DIRECT_TX_DATA_ACCESS "WF" +// ============================================================================= +// Register : XIP_AUX_QMI_DIRECT_RX +// Description : Read from the QMI direct-mode RX FIFO (fast bus access to +// QMI_DIRECT_RX) +// With each byte clocked out on the serial interface, one byte +// will simultaneously be clocked in, and will appear in this +// FIFO. The serial interface will stall when this FIFO is full, +// to avoid dropping data. +// +// When 16-bit data is pushed into the TX FIFO, the corresponding +// RX FIFO push will also contain 16 bits of data. The least- +// significant byte is the first one received. +#define XIP_AUX_QMI_DIRECT_RX_OFFSET _u(0x00000008) +#define XIP_AUX_QMI_DIRECT_RX_BITS _u(0x0000ffff) +#define XIP_AUX_QMI_DIRECT_RX_RESET _u(0x00000000) +#define XIP_AUX_QMI_DIRECT_RX_MSB _u(15) +#define XIP_AUX_QMI_DIRECT_RX_LSB _u(0) +#define XIP_AUX_QMI_DIRECT_RX_ACCESS "RF" +// ============================================================================= +#endif // _HARDWARE_REGS_XIP_AUX_H + diff --git a/lib/pico-sdk/rp2350/hardware/regs/xosc.h b/lib/pico-sdk/rp2350/hardware/regs/xosc.h new file mode 100644 index 000000000000..782c30ca1b4d --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/regs/xosc.h @@ -0,0 +1,175 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +// ============================================================================= +// Register block : XOSC +// Version : 1 +// Bus type : apb +// Description : Controls the crystal oscillator +// ============================================================================= +#ifndef _HARDWARE_REGS_XOSC_H +#define _HARDWARE_REGS_XOSC_H +// ============================================================================= +// Register : XOSC_CTRL +// Description : Crystal Oscillator Control +#define XOSC_CTRL_OFFSET _u(0x00000000) +#define XOSC_CTRL_BITS _u(0x00ffffff) +#define XOSC_CTRL_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : XOSC_CTRL_ENABLE +// Description : On power-up this field is initialised to DISABLE and the chip +// runs from the ROSC. +// If the chip has subsequently been programmed to run from the +// XOSC then setting this field to DISABLE may lock-up the chip. +// If this is a concern then run the clk_ref from the ROSC and +// enable the clk_sys RESUS feature. +// The 12-bit code is intended to give some protection against +// accidental writes. An invalid setting will retain the previous +// value. The actual value being used can be read from +// STATUS_ENABLED +// 0xd1e -> DISABLE +// 0xfab -> ENABLE +#define XOSC_CTRL_ENABLE_RESET "-" +#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000) +#define XOSC_CTRL_ENABLE_MSB _u(23) +#define XOSC_CTRL_ENABLE_LSB _u(12) +#define XOSC_CTRL_ENABLE_ACCESS "RW" +#define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e) +#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab) +// ----------------------------------------------------------------------------- +// Field : XOSC_CTRL_FREQ_RANGE +// Description : The 12-bit code is intended to give some protection against +// accidental writes. An invalid setting will retain the previous +// value. The actual value being used can be read from +// STATUS_FREQ_RANGE +// 0xaa0 -> 1_15MHZ +// 0xaa1 -> 10_30MHZ +// 0xaa2 -> 25_60MHZ +// 0xaa3 -> 40_100MHZ +#define XOSC_CTRL_FREQ_RANGE_RESET "-" +#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff) +#define XOSC_CTRL_FREQ_RANGE_MSB _u(11) +#define XOSC_CTRL_FREQ_RANGE_LSB _u(0) +#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW" +#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0) +#define XOSC_CTRL_FREQ_RANGE_VALUE_10_30MHZ _u(0xaa1) +#define XOSC_CTRL_FREQ_RANGE_VALUE_25_60MHZ _u(0xaa2) +#define XOSC_CTRL_FREQ_RANGE_VALUE_40_100MHZ _u(0xaa3) +// ============================================================================= +// Register : XOSC_STATUS +// Description : Crystal Oscillator Status +#define XOSC_STATUS_OFFSET _u(0x00000004) +#define XOSC_STATUS_BITS _u(0x81001003) +#define XOSC_STATUS_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_STABLE +// Description : Oscillator is running and stable +#define XOSC_STATUS_STABLE_RESET _u(0x0) +#define XOSC_STATUS_STABLE_BITS _u(0x80000000) +#define XOSC_STATUS_STABLE_MSB _u(31) +#define XOSC_STATUS_STABLE_LSB _u(31) +#define XOSC_STATUS_STABLE_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_BADWRITE +// Description : An invalid value has been written to CTRL_ENABLE or +// CTRL_FREQ_RANGE or DORMANT +#define XOSC_STATUS_BADWRITE_RESET _u(0x0) +#define XOSC_STATUS_BADWRITE_BITS _u(0x01000000) +#define XOSC_STATUS_BADWRITE_MSB _u(24) +#define XOSC_STATUS_BADWRITE_LSB _u(24) +#define XOSC_STATUS_BADWRITE_ACCESS "WC" +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_ENABLED +// Description : Oscillator is enabled but not necessarily running and stable, +// resets to 0 +#define XOSC_STATUS_ENABLED_RESET "-" +#define XOSC_STATUS_ENABLED_BITS _u(0x00001000) +#define XOSC_STATUS_ENABLED_MSB _u(12) +#define XOSC_STATUS_ENABLED_LSB _u(12) +#define XOSC_STATUS_ENABLED_ACCESS "RO" +// ----------------------------------------------------------------------------- +// Field : XOSC_STATUS_FREQ_RANGE +// Description : The current frequency range setting +// 0x0 -> 1_15MHZ +// 0x1 -> 10_30MHZ +// 0x2 -> 25_60MHZ +// 0x3 -> 40_100MHZ +#define XOSC_STATUS_FREQ_RANGE_RESET "-" +#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003) +#define XOSC_STATUS_FREQ_RANGE_MSB _u(1) +#define XOSC_STATUS_FREQ_RANGE_LSB _u(0) +#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO" +#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0) +#define XOSC_STATUS_FREQ_RANGE_VALUE_10_30MHZ _u(0x1) +#define XOSC_STATUS_FREQ_RANGE_VALUE_25_60MHZ _u(0x2) +#define XOSC_STATUS_FREQ_RANGE_VALUE_40_100MHZ _u(0x3) +// ============================================================================= +// Register : XOSC_DORMANT +// Description : Crystal Oscillator pause control +// This is used to save power by pausing the XOSC +// On power-up this field is initialised to WAKE +// An invalid write will also select WAKE +// Warning: stop the PLLs before selecting dormant mode +// Warning: setup the irq before selecting dormant mode +// 0x636f6d61 -> dormant +// 0x77616b65 -> WAKE +#define XOSC_DORMANT_OFFSET _u(0x00000008) +#define XOSC_DORMANT_BITS _u(0xffffffff) +#define XOSC_DORMANT_RESET "-" +#define XOSC_DORMANT_MSB _u(31) +#define XOSC_DORMANT_LSB _u(0) +#define XOSC_DORMANT_ACCESS "RW" +#define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61) +#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65) +// ============================================================================= +// Register : XOSC_STARTUP +// Description : Controls the startup delay +#define XOSC_STARTUP_OFFSET _u(0x0000000c) +#define XOSC_STARTUP_BITS _u(0x00103fff) +#define XOSC_STARTUP_RESET _u(0x00000000) +// ----------------------------------------------------------------------------- +// Field : XOSC_STARTUP_X4 +// Description : Multiplies the startup_delay by 4, just in case. The reset +// value is controlled by a mask-programmable tiecell and is +// provided in case we are booting from XOSC and the default +// startup delay is insufficient. The reset value is 0x0. +#define XOSC_STARTUP_X4_RESET "-" +#define XOSC_STARTUP_X4_BITS _u(0x00100000) +#define XOSC_STARTUP_X4_MSB _u(20) +#define XOSC_STARTUP_X4_LSB _u(20) +#define XOSC_STARTUP_X4_ACCESS "RW" +// ----------------------------------------------------------------------------- +// Field : XOSC_STARTUP_DELAY +// Description : in multiples of 256*xtal_period. The reset value of 0xc4 +// corresponds to approx 50 000 cycles. +#define XOSC_STARTUP_DELAY_RESET "-" +#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff) +#define XOSC_STARTUP_DELAY_MSB _u(13) +#define XOSC_STARTUP_DELAY_LSB _u(0) +#define XOSC_STARTUP_DELAY_ACCESS "RW" +// ============================================================================= +// Register : XOSC_COUNT +// Description : A down counter running at the xosc frequency which counts to +// zero and stops. +// Can be used for short software pauses when setting up time +// sensitive hardware. +// To start the counter, write a non-zero value. Reads will return +// 1 while the count is running and 0 when it has finished. +// Minimum count value is 4. Count values <4 will be treated as +// count value =4. +// Note that synchronisation to the register clock domain costs 2 +// register clock cycles and the counter cannot compensate for +// that. +#define XOSC_COUNT_OFFSET _u(0x00000010) +#define XOSC_COUNT_BITS _u(0x0000ffff) +#define XOSC_COUNT_RESET _u(0x00000000) +#define XOSC_COUNT_MSB _u(15) +#define XOSC_COUNT_LSB _u(0) +#define XOSC_COUNT_ACCESS "RW" +// ============================================================================= +#endif // _HARDWARE_REGS_XOSC_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/accessctrl.h b/lib/pico-sdk/rp2350/hardware/structs/accessctrl.h new file mode 100644 index 000000000000..5fd30cb2d95a --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/accessctrl.h @@ -0,0 +1,519 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_ACCESSCTRL_H +#define _HARDWARE_STRUCTS_ACCESSCTRL_H + +/** + * \file rp2350/accessctrl.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/accessctrl.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_accessctrl +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/accessctrl.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(ACCESSCTRL_LOCK_OFFSET) // ACCESSCTRL_LOCK + // Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master + // 0x00000008 [3] DEBUG (0) + // 0x00000004 [2] DMA (1) + // 0x00000002 [1] CORE1 (0) + // 0x00000001 [0] CORE0 (0) + io_rw_32 lock; + + _REG_(ACCESSCTRL_FORCE_CORE_NS_OFFSET) // ACCESSCTRL_FORCE_CORE_NS + // Force core 1's bus accesses to always be Non-secure, no matter the core's internal state + // 0x00000002 [1] CORE1 (0) + io_rw_32 force_core_ns; + + _REG_(ACCESSCTRL_CFGRESET_OFFSET) // ACCESSCTRL_CFGRESET + // Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers + // 0x00000001 [0] CFGRESET (0) + io_wo_32 cfgreset; + + // (Description copied from array index 0 register ACCESSCTRL_GPIO_NSMASK0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_GPIO_NSMASK0_OFFSET) // ACCESSCTRL_GPIO_NSMASK0 + // Control whether GPIO0 + // 0xffffffff [31:0] GPIO_NSMASK0 (0x00000000) + io_rw_32 gpio_nsmask[2]; + + _REG_(ACCESSCTRL_ROM_OFFSET) // ACCESSCTRL_ROM + // Control access to ROM. Defaults to fully open access. + // 0x00000080 [7] DBG (1) If 1, ROM can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, ROM can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, ROM can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, ROM can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, ROM can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, ROM can be accessed from a... + // 0x00000002 [1] NSP (1) If 1, ROM can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (1) If 1, and NSP is also set, ROM can be accessed from a... + io_rw_32 rom; + + _REG_(ACCESSCTRL_XIP_MAIN_OFFSET) // ACCESSCTRL_XIP_MAIN + // Control access to XIP_MAIN. Defaults to fully open access. + // 0x00000080 [7] DBG (1) If 1, XIP_MAIN can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, XIP_MAIN can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XIP_MAIN can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XIP_MAIN can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XIP_MAIN can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, XIP_MAIN can be accessed from... + // 0x00000002 [1] NSP (1) If 1, XIP_MAIN can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (1) If 1, and NSP is also set, XIP_MAIN can be accessed from... + io_rw_32 xip_main; + + // (Description copied from array index 0 register ACCESSCTRL_SRAM0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_SRAM0_OFFSET) // ACCESSCTRL_SRAM0 + // Control access to SRAM0. Defaults to fully open access. + // 0x00000080 [7] DBG (1) If 1, SRAM0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, SRAM0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SRAM0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SRAM0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SRAM0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, SRAM0 can be accessed from a... + // 0x00000002 [1] NSP (1) If 1, SRAM0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (1) If 1, and NSP is also set, SRAM0 can be accessed from a... + io_rw_32 sram[10]; + + _REG_(ACCESSCTRL_DMA_OFFSET) // ACCESSCTRL_DMA + // Control access to DMA. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, DMA can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, DMA can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, DMA can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, DMA can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, DMA can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, DMA can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, DMA can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, DMA can be accessed from a... + io_rw_32 dma; + + _REG_(ACCESSCTRL_USBCTRL_OFFSET) // ACCESSCTRL_USBCTRL + // Control access to USBCTRL. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, USBCTRL can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, USBCTRL can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, USBCTRL can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, USBCTRL can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, USBCTRL can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, USBCTRL can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, USBCTRL can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, USBCTRL can be accessed from... + io_rw_32 usbctrl; + + // (Description copied from array index 0 register ACCESSCTRL_PIO0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_PIO0_OFFSET) // ACCESSCTRL_PIO0 + // Control access to PIO0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, PIO0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, PIO0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PIO0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PIO0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PIO0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, PIO0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, PIO0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PIO0 can be accessed from a... + io_rw_32 pio[3]; + + _REG_(ACCESSCTRL_CORESIGHT_TRACE_OFFSET) // ACCESSCTRL_CORESIGHT_TRACE + // Control access to CORESIGHT_TRACE. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, CORESIGHT_TRACE can be accessed by the debugger,... + // 0x00000040 [6] DMA (0) If 1, CORESIGHT_TRACE can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, CORESIGHT_TRACE can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, CORESIGHT_TRACE can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, CORESIGHT_TRACE can be accessed from a Secure,... + // 0x00000004 [2] SU (0) If 1, and SP is also set, CORESIGHT_TRACE can be... + // 0x00000002 [1] NSP (0) If 1, CORESIGHT_TRACE can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CORESIGHT_TRACE can be... + io_rw_32 coresight_trace; + + _REG_(ACCESSCTRL_CORESIGHT_PERIPH_OFFSET) // ACCESSCTRL_CORESIGHT_PERIPH + // Control access to CORESIGHT_PERIPH. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, CORESIGHT_PERIPH can be accessed by the debugger,... + // 0x00000040 [6] DMA (0) If 1, CORESIGHT_PERIPH can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, CORESIGHT_PERIPH can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, CORESIGHT_PERIPH can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, CORESIGHT_PERIPH can be accessed from a Secure,... + // 0x00000004 [2] SU (0) If 1, and SP is also set, CORESIGHT_PERIPH can be... + // 0x00000002 [1] NSP (0) If 1, CORESIGHT_PERIPH can be accessed from a... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CORESIGHT_PERIPH can be... + io_rw_32 coresight_periph; + + _REG_(ACCESSCTRL_SYSINFO_OFFSET) // ACCESSCTRL_SYSINFO + // Control access to SYSINFO. Defaults to fully open access. + // 0x00000080 [7] DBG (1) If 1, SYSINFO can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, SYSINFO can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SYSINFO can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SYSINFO can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SYSINFO can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, SYSINFO can be accessed from a... + // 0x00000002 [1] NSP (1) If 1, SYSINFO can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (1) If 1, and NSP is also set, SYSINFO can be accessed from... + io_rw_32 sysinfo; + + _REG_(ACCESSCTRL_RESETS_OFFSET) // ACCESSCTRL_RESETS + // Control access to RESETS. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, RESETS can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, RESETS can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, RESETS can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, RESETS can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, RESETS can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, RESETS can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, RESETS can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, RESETS can be accessed from a... + io_rw_32 resets; + + // (Description copied from array index 0 register ACCESSCTRL_IO_BANK0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_IO_BANK0_OFFSET) // ACCESSCTRL_IO_BANK0 + // Control access to IO_BANK0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, IO_BANK0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, IO_BANK0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, IO_BANK0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, IO_BANK0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, IO_BANK0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, IO_BANK0 can be accessed from... + // 0x00000002 [1] NSP (0) If 1, IO_BANK0 can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, IO_BANK0 can be accessed from... + io_rw_32 io_bank[2]; + + _REG_(ACCESSCTRL_PADS_BANK0_OFFSET) // ACCESSCTRL_PADS_BANK0 + // Control access to PADS_BANK0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, PADS_BANK0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, PADS_BANK0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PADS_BANK0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PADS_BANK0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PADS_BANK0 can be accessed from a Secure,... + // 0x00000004 [2] SU (1) If 1, and SP is also set, PADS_BANK0 can be accessed... + // 0x00000002 [1] NSP (0) If 1, PADS_BANK0 can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PADS_BANK0 can be accessed... + io_rw_32 pads_bank0; + + _REG_(ACCESSCTRL_PADS_QSPI_OFFSET) // ACCESSCTRL_PADS_QSPI + // Control access to PADS_QSPI. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, PADS_QSPI can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, PADS_QSPI can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PADS_QSPI can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PADS_QSPI can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PADS_QSPI can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, PADS_QSPI can be accessed from... + // 0x00000002 [1] NSP (0) If 1, PADS_QSPI can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PADS_QSPI can be accessed... + io_rw_32 pads_qspi; + + _REG_(ACCESSCTRL_BUSCTRL_OFFSET) // ACCESSCTRL_BUSCTRL + // Control access to BUSCTRL. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, BUSCTRL can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, BUSCTRL can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, BUSCTRL can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, BUSCTRL can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, BUSCTRL can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, BUSCTRL can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, BUSCTRL can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, BUSCTRL can be accessed from... + io_rw_32 busctrl; + + _REG_(ACCESSCTRL_ADC0_OFFSET) // ACCESSCTRL_ADC0 + // Control access to ADC0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, ADC0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, ADC0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, ADC0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, ADC0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, ADC0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, ADC0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, ADC0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, ADC0 can be accessed from a... + io_rw_32 adc0; + + _REG_(ACCESSCTRL_HSTX_OFFSET) // ACCESSCTRL_HSTX + // Control access to HSTX. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, HSTX can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, HSTX can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, HSTX can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, HSTX can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, HSTX can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, HSTX can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, HSTX can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, HSTX can be accessed from a... + io_rw_32 hstx; + + // (Description copied from array index 0 register ACCESSCTRL_I2C0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_I2C0_OFFSET) // ACCESSCTRL_I2C0 + // Control access to I2C0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, I2C0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, I2C0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, I2C0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, I2C0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, I2C0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, I2C0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, I2C0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, I2C0 can be accessed from a... + io_rw_32 i2c[2]; + + _REG_(ACCESSCTRL_PWM_OFFSET) // ACCESSCTRL_PWM + // Control access to PWM. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, PWM can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, PWM can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PWM can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PWM can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PWM can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, PWM can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, PWM can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PWM can be accessed from a... + io_rw_32 pwm; + + // (Description copied from array index 0 register ACCESSCTRL_SPI0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_SPI0_OFFSET) // ACCESSCTRL_SPI0 + // Control access to SPI0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, SPI0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, SPI0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SPI0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SPI0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SPI0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, SPI0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, SPI0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SPI0 can be accessed from a... + io_rw_32 spi[2]; + + // (Description copied from array index 0 register ACCESSCTRL_TIMER0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_TIMER0_OFFSET) // ACCESSCTRL_TIMER0 + // Control access to TIMER0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, TIMER0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, TIMER0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, TIMER0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, TIMER0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, TIMER0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, TIMER0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, TIMER0 can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TIMER0 can be accessed from a... + io_rw_32 timer[2]; + + // (Description copied from array index 0 register ACCESSCTRL_UART0 applies similarly to other array indexes) + _REG_(ACCESSCTRL_UART0_OFFSET) // ACCESSCTRL_UART0 + // Control access to UART0. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, UART0 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, UART0 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, UART0 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, UART0 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, UART0 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, UART0 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, UART0 can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, UART0 can be accessed from a... + io_rw_32 uart[2]; + + _REG_(ACCESSCTRL_OTP_OFFSET) // ACCESSCTRL_OTP + // Control access to OTP. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, OTP can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, OTP can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, OTP can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, OTP can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, OTP can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, OTP can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, OTP can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, OTP can be accessed from a... + io_rw_32 otp; + + _REG_(ACCESSCTRL_TBMAN_OFFSET) // ACCESSCTRL_TBMAN + // Control access to TBMAN. Defaults to Secure access from any master. + // 0x00000080 [7] DBG (1) If 1, TBMAN can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, TBMAN can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, TBMAN can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, TBMAN can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, TBMAN can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (1) If 1, and SP is also set, TBMAN can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, TBMAN can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TBMAN can be accessed from a... + io_rw_32 tbman; + + _REG_(ACCESSCTRL_POWMAN_OFFSET) // ACCESSCTRL_POWMAN + // Control access to POWMAN. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, POWMAN can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, POWMAN can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, POWMAN can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, POWMAN can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, POWMAN can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, POWMAN can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, POWMAN can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, POWMAN can be accessed from a... + io_rw_32 powman; + + _REG_(ACCESSCTRL_TRNG_OFFSET) // ACCESSCTRL_TRNG + // Control access to TRNG. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, TRNG can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, TRNG can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, TRNG can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, TRNG can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, TRNG can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, TRNG can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, TRNG can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TRNG can be accessed from a... + io_rw_32 trng; + + _REG_(ACCESSCTRL_SHA256_OFFSET) // ACCESSCTRL_SHA256 + // Control access to SHA256. Defaults to Secure, Privileged access only. + // 0x00000080 [7] DBG (1) If 1, SHA256 can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, SHA256 can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SHA256 can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SHA256 can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SHA256 can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, SHA256 can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, SHA256 can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SHA256 can be accessed from a... + io_rw_32 sha256; + + _REG_(ACCESSCTRL_SYSCFG_OFFSET) // ACCESSCTRL_SYSCFG + // Control access to SYSCFG. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, SYSCFG can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, SYSCFG can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, SYSCFG can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, SYSCFG can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, SYSCFG can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, SYSCFG can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, SYSCFG can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, SYSCFG can be accessed from a... + io_rw_32 syscfg; + + _REG_(ACCESSCTRL_CLOCKS_OFFSET) // ACCESSCTRL_CLOCKS + // Control access to CLOCKS. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, CLOCKS can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, CLOCKS can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, CLOCKS can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, CLOCKS can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, CLOCKS can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, CLOCKS can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, CLOCKS can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, CLOCKS can be accessed from a... + io_rw_32 clocks; + + _REG_(ACCESSCTRL_XOSC_OFFSET) // ACCESSCTRL_XOSC + // Control access to XOSC. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, XOSC can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, XOSC can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XOSC can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XOSC can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XOSC can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, XOSC can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, XOSC can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XOSC can be accessed from a... + io_rw_32 xosc; + + _REG_(ACCESSCTRL_ROSC_OFFSET) // ACCESSCTRL_ROSC + // Control access to ROSC. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, ROSC can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, ROSC can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, ROSC can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, ROSC can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, ROSC can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, ROSC can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, ROSC can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, ROSC can be accessed from a... + io_rw_32 rosc; + + _REG_(ACCESSCTRL_PLL_SYS_OFFSET) // ACCESSCTRL_PLL_SYS + // Control access to PLL_SYS. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, PLL_SYS can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, PLL_SYS can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PLL_SYS can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PLL_SYS can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PLL_SYS can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, PLL_SYS can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, PLL_SYS can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PLL_SYS can be accessed from... + io_rw_32 pll_sys; + + _REG_(ACCESSCTRL_PLL_USB_OFFSET) // ACCESSCTRL_PLL_USB + // Control access to PLL_USB. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, PLL_USB can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, PLL_USB can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, PLL_USB can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, PLL_USB can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, PLL_USB can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, PLL_USB can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, PLL_USB can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, PLL_USB can be accessed from... + io_rw_32 pll_usb; + + _REG_(ACCESSCTRL_TICKS_OFFSET) // ACCESSCTRL_TICKS + // Control access to TICKS. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, TICKS can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, TICKS can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, TICKS can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, TICKS can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, TICKS can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, TICKS can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, TICKS can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, TICKS can be accessed from a... + io_rw_32 ticks; + + _REG_(ACCESSCTRL_WATCHDOG_OFFSET) // ACCESSCTRL_WATCHDOG + // Control access to WATCHDOG. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, WATCHDOG can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, WATCHDOG can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, WATCHDOG can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, WATCHDOG can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, WATCHDOG can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, WATCHDOG can be accessed from... + // 0x00000002 [1] NSP (0) If 1, WATCHDOG can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, WATCHDOG can be accessed from... + io_rw_32 watchdog; + + _REG_(ACCESSCTRL_RSM_OFFSET) // ACCESSCTRL_RSM + // Control access to RSM. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, RSM can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, RSM can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, RSM can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, RSM can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, RSM can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, RSM can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, RSM can be accessed from a Non-secure, Privileged context + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, RSM can be accessed from a... + io_rw_32 rsm; + + _REG_(ACCESSCTRL_XIP_CTRL_OFFSET) // ACCESSCTRL_XIP_CTRL + // Control access to XIP_CTRL. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, XIP_CTRL can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, XIP_CTRL can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XIP_CTRL can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XIP_CTRL can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XIP_CTRL can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_CTRL can be accessed from... + // 0x00000002 [1] NSP (0) If 1, XIP_CTRL can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_CTRL can be accessed from... + io_rw_32 xip_ctrl; + + _REG_(ACCESSCTRL_XIP_QMI_OFFSET) // ACCESSCTRL_XIP_QMI + // Control access to XIP_QMI. Defaults to Secure, Privileged processor or debug access only. + // 0x00000080 [7] DBG (1) If 1, XIP_QMI can be accessed by the debugger, at... + // 0x00000040 [6] DMA (0) If 1, XIP_QMI can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XIP_QMI can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XIP_QMI can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XIP_QMI can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_QMI can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, XIP_QMI can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_QMI can be accessed from... + io_rw_32 xip_qmi; + + _REG_(ACCESSCTRL_XIP_AUX_OFFSET) // ACCESSCTRL_XIP_AUX + // Control access to XIP_AUX. Defaults to Secure, Privileged access only. + // 0x00000080 [7] DBG (1) If 1, XIP_AUX can be accessed by the debugger, at... + // 0x00000040 [6] DMA (1) If 1, XIP_AUX can be accessed by the DMA, at... + // 0x00000020 [5] CORE1 (1) If 1, XIP_AUX can be accessed by core 1, at... + // 0x00000010 [4] CORE0 (1) If 1, XIP_AUX can be accessed by core 0, at... + // 0x00000008 [3] SP (1) If 1, XIP_AUX can be accessed from a Secure, Privileged context + // 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_AUX can be accessed from a... + // 0x00000002 [1] NSP (0) If 1, XIP_AUX can be accessed from a Non-secure,... + // 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_AUX can be accessed from... + io_rw_32 xip_aux; +} accessctrl_hw_t; + +#define accessctrl_hw ((accessctrl_hw_t *)ACCESSCTRL_BASE) +static_assert(sizeof (accessctrl_hw_t) == 0x00ec, ""); + +#endif // _HARDWARE_STRUCTS_ACCESSCTRL_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/adc.h b/lib/pico-sdk/rp2350/hardware/structs/adc.h new file mode 100644 index 000000000000..687128eba3c1 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/adc.h @@ -0,0 +1,96 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_ADC_H +#define _HARDWARE_STRUCTS_ADC_H + +/** + * \file rp2350/adc.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/adc.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_adc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/adc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(ADC_CS_OFFSET) // ADC_CS + // ADC Control and Status + // 0x01ff0000 [24:16] RROBIN (0x000) Round-robin sampling + // 0x0000f000 [15:12] AINSEL (0x0) Select analog mux input + // 0x00000400 [10] ERR_STICKY (0) Some past ADC conversion encountered an error + // 0x00000200 [9] ERR (0) The most recent ADC conversion encountered an error;... + // 0x00000100 [8] READY (0) 1 if the ADC is ready to start a new conversion + // 0x00000008 [3] START_MANY (0) Continuously perform conversions whilst this bit is 1 + // 0x00000004 [2] START_ONCE (0) Start a single conversion + // 0x00000002 [1] TS_EN (0) Power on temperature sensor + // 0x00000001 [0] EN (0) Power on ADC and enable its clock + io_rw_32 cs; + + _REG_(ADC_RESULT_OFFSET) // ADC_RESULT + // Result of most recent ADC conversion + // 0x00000fff [11:0] RESULT (0x000) + io_ro_32 result; + + _REG_(ADC_FCS_OFFSET) // ADC_FCS + // FIFO control and status + // 0x0f000000 [27:24] THRESH (0x0) DREQ/IRQ asserted when level >= threshold + // 0x000f0000 [19:16] LEVEL (0x0) The number of conversion results currently waiting in the FIFO + // 0x00000800 [11] OVER (0) 1 if the FIFO has been overflowed + // 0x00000400 [10] UNDER (0) 1 if the FIFO has been underflowed + // 0x00000200 [9] FULL (0) + // 0x00000100 [8] EMPTY (0) + // 0x00000008 [3] DREQ_EN (0) If 1: assert DMA requests when FIFO contains data + // 0x00000004 [2] ERR (0) If 1: conversion error bit appears in the FIFO alongside... + // 0x00000002 [1] SHIFT (0) If 1: FIFO results are right-shifted to be one byte in size + // 0x00000001 [0] EN (0) If 1: write result to the FIFO after each conversion + io_rw_32 fcs; + + _REG_(ADC_FIFO_OFFSET) // ADC_FIFO + // Conversion result FIFO + // 0x00008000 [15] ERR (-) 1 if this particular sample experienced a conversion error + // 0x00000fff [11:0] VAL (-) + io_ro_32 fifo; + + _REG_(ADC_DIV_OFFSET) // ADC_DIV + // Clock divider + // 0x00ffff00 [23:8] INT (0x0000) Integer part of clock divisor + // 0x000000ff [7:0] FRAC (0x00) Fractional part of clock divisor + io_rw_32 div; + + _REG_(ADC_INTR_OFFSET) // ADC_INTR + // Raw Interrupts + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_ro_32 intr; + + _REG_(ADC_INTE_OFFSET) // ADC_INTE + // Interrupt Enable + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_rw_32 inte; + + _REG_(ADC_INTF_OFFSET) // ADC_INTF + // Interrupt Force + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_rw_32 intf; + + _REG_(ADC_INTS_OFFSET) // ADC_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level + io_ro_32 ints; +} adc_hw_t; + +#define adc_hw ((adc_hw_t *)ADC_BASE) +static_assert(sizeof (adc_hw_t) == 0x0024, ""); + +#endif // _HARDWARE_STRUCTS_ADC_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/bootram.h b/lib/pico-sdk/rp2350/hardware/structs/bootram.h new file mode 100644 index 000000000000..b40a0393f388 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/bootram.h @@ -0,0 +1,49 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_BOOTRAM_H +#define _HARDWARE_STRUCTS_BOOTRAM_H + +/** + * \file rp2350/bootram.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/bootram.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_bootram +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/bootram.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + // (Description copied from array index 0 register BOOTRAM_WRITE_ONCE0 applies similarly to other array indexes) + _REG_(BOOTRAM_WRITE_ONCE0_OFFSET) // BOOTRAM_WRITE_ONCE0 + // This registers always ORs writes into its current contents + // 0xffffffff [31:0] WRITE_ONCE0 (0x00000000) + io_rw_32 write_once[2]; + + _REG_(BOOTRAM_BOOTLOCK_STAT_OFFSET) // BOOTRAM_BOOTLOCK_STAT + // Bootlock status register + // 0x000000ff [7:0] BOOTLOCK_STAT (0xff) + io_rw_32 bootlock_stat; + + // (Description copied from array index 0 register BOOTRAM_BOOTLOCK0 applies similarly to other array indexes) + _REG_(BOOTRAM_BOOTLOCK0_OFFSET) // BOOTRAM_BOOTLOCK0 + // Read to claim and check + // 0xffffffff [31:0] BOOTLOCK0 (0x00000000) + io_rw_32 bootlock[8]; +} bootram_hw_t; + +#define bootram_hw ((bootram_hw_t *)(BOOTRAM_BASE + BOOTRAM_WRITE_ONCE0_OFFSET)) +static_assert(sizeof (bootram_hw_t) == 0x002c, ""); + +#endif // _HARDWARE_STRUCTS_BOOTRAM_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/bus_ctrl.h b/lib/pico-sdk/rp2350/hardware/structs/bus_ctrl.h new file mode 100644 index 000000000000..b94a40459c0f --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/bus_ctrl.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/busctrl.h" +#define bus_ctrl_hw busctrl_hw \ No newline at end of file diff --git a/lib/pico-sdk/rp2350/hardware/structs/busctrl.h b/lib/pico-sdk/rp2350/hardware/structs/busctrl.h new file mode 100644 index 000000000000..2eb83a992507 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/busctrl.h @@ -0,0 +1,90 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_BUSCTRL_H +#define _HARDWARE_STRUCTS_BUSCTRL_H + +/** + * \file rp2350/busctrl.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/busctrl.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_busctrl +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** \brief Bus fabric performance counters on RP2350 (used as typedef \ref bus_ctrl_perf_counter_t) + * \ingroup hardware_busctrl + */ +typedef enum bus_ctrl_perf_counter_rp2350 { + arbiter_rom_perf_event_access = 19, + arbiter_rom_perf_event_access_contested = 18, + arbiter_xip_main_perf_event_access = 17, + arbiter_xip_main_perf_event_access_contested = 16, + arbiter_sram0_perf_event_access = 15, + arbiter_sram0_perf_event_access_contested = 14, + arbiter_sram1_perf_event_access = 13, + arbiter_sram1_perf_event_access_contested = 12, + arbiter_sram2_perf_event_access = 11, + arbiter_sram2_perf_event_access_contested = 10, + arbiter_sram3_perf_event_access = 9, + arbiter_sram3_perf_event_access_contested = 8, + arbiter_sram4_perf_event_access = 7, + arbiter_sram4_perf_event_access_contested = 6, + arbiter_sram5_perf_event_access = 5, + arbiter_sram5_perf_event_access_contested = 4, + arbiter_fastperi_perf_event_access = 3, + arbiter_fastperi_perf_event_access_contested = 2, + arbiter_apb_perf_event_access = 1, + arbiter_apb_perf_event_access_contested = 0 +} bus_ctrl_perf_counter_t; + +typedef struct { + _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0 + // Bus fabric performance counter 0 + // 0x00ffffff [23:0] PERFCTR0 (0x000000) Busfabric saturating performance counter 0 + + io_rw_32 value; + + _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0 + // Bus fabric performance event select for PERFCTR0 + // 0x0000007f [6:0] PERFSEL0 (0x1f) Select an event for PERFCTR0 + io_rw_32 sel; +} bus_ctrl_perf_hw_t; + +typedef struct { + _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY + // Set the priority of each master for bus arbitration + // 0x00001000 [12] DMA_W (0) 0 - low priority, 1 - high priority + // 0x00000100 [8] DMA_R (0) 0 - low priority, 1 - high priority + // 0x00000010 [4] PROC1 (0) 0 - low priority, 1 - high priority + // 0x00000001 [0] PROC0 (0) 0 - low priority, 1 - high priority + io_rw_32 priority; + + _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK + // Bus priority acknowledge + // 0x00000001 [0] BUS_PRIORITY_ACK (0) Goes to 1 once all arbiters have registered the new... + io_ro_32 priority_ack; + + _REG_(BUSCTRL_PERFCTR_EN_OFFSET) // BUSCTRL_PERFCTR_EN + // Enable the performance counters + // 0x00000001 [0] PERFCTR_EN (0) + io_rw_32 perfctr_en; + + bus_ctrl_perf_hw_t counter[4]; +} busctrl_hw_t; + +#define busctrl_hw ((busctrl_hw_t *)BUSCTRL_BASE) +static_assert(sizeof (busctrl_hw_t) == 0x002c, ""); + +#endif // _HARDWARE_STRUCTS_BUSCTRL_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/clocks.h b/lib/pico-sdk/rp2350/hardware/structs/clocks.h new file mode 100644 index 000000000000..2cdc1b824e7f --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/clocks.h @@ -0,0 +1,580 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_CLOCKS_H +#define _HARDWARE_STRUCTS_CLOCKS_H + +/** + * \file rp2350/clocks.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/clocks.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_clocks +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** \brief Clock numbers on RP2350 (used as typedef \ref clock_num_t) + * \ingroup hardware_clocks + */ +/// \tag::clkenum[] +typedef enum clock_num_rp2350 { + clk_gpout0 = 0, ///< Select CLK_GPOUT0 as clock source + clk_gpout1 = 1, ///< Select CLK_GPOUT1 as clock source + clk_gpout2 = 2, ///< Select CLK_GPOUT2 as clock source + clk_gpout3 = 3, ///< Select CLK_GPOUT3 as clock source + clk_ref = 4, ///< Select CLK_REF as clock source + clk_sys = 5, ///< Select CLK_SYS as clock source + clk_peri = 6, ///< Select CLK_PERI as clock source + clk_hstx = 7, ///< Select CLK_HSTX as clock source + clk_usb = 8, ///< Select CLK_USB as clock source + clk_adc = 9, ///< Select CLK_ADC as clock source + CLK_COUNT +} clock_num_t; +/// \end::clkenum[] + +/** \brief Clock destination numbers on RP2350 (used as typedef \ref clock_dest_num_t) + * \ingroup hardware_clocks + */ +typedef enum clock_dest_num_rp2350 { + CLK_DEST_SYS_CLOCKS = 0, ///< Select SYS_CLOCKS as clock destination + CLK_DEST_SYS_ACCESSCTRL = 1, ///< Select SYS_ACCESSCTRL as clock destination + CLK_DEST_ADC = 2, ///< Select ADC as clock destination + CLK_DEST_SYS_ADC = 3, ///< Select SYS_ADC as clock destination + CLK_DEST_SYS_BOOTRAM = 4, ///< Select SYS_BOOTRAM as clock destination + CLK_DEST_SYS_BUSCTRL = 5, ///< Select SYS_BUSCTRL as clock destination + CLK_DEST_SYS_BUSFABRIC = 6, ///< Select SYS_BUSFABRIC as clock destination + CLK_DEST_SYS_DMA = 7, ///< Select SYS_DMA as clock destination + CLK_DEST_SYS_GLITCH_DETECTOR = 8, ///< Select SYS_GLITCH_DETECTOR as clock destination + CLK_DEST_HSTX = 9, ///< Select HSTX as clock destination + CLK_DEST_SYS_HSTX = 10, ///< Select SYS_HSTX as clock destination + CLK_DEST_SYS_I2C0 = 11, ///< Select SYS_I2C0 as clock destination + CLK_DEST_SYS_I2C1 = 12, ///< Select SYS_I2C1 as clock destination + CLK_DEST_SYS_IO = 13, ///< Select SYS_IO as clock destination + CLK_DEST_SYS_JTAG = 14, ///< Select SYS_JTAG as clock destination + CLK_DEST_REF_OTP = 15, ///< Select REF_OTP as clock destination + CLK_DEST_SYS_OTP = 16, ///< Select SYS_OTP as clock destination + CLK_DEST_SYS_PADS = 17, ///< Select SYS_PADS as clock destination + CLK_DEST_SYS_PIO0 = 18, ///< Select SYS_PIO0 as clock destination + CLK_DEST_SYS_PIO1 = 19, ///< Select SYS_PIO1 as clock destination + CLK_DEST_SYS_PIO2 = 20, ///< Select SYS_PIO2 as clock destination + CLK_DEST_SYS_PLL_SYS = 21, ///< Select SYS_PLL_SYS as clock destination + CLK_DEST_SYS_PLL_USB = 22, ///< Select SYS_PLL_USB as clock destination + CLK_DEST_REF_POWMAN = 23, ///< Select REF_POWMAN as clock destination + CLK_DEST_SYS_POWMAN = 24, ///< Select SYS_POWMAN as clock destination + CLK_DEST_SYS_PWM = 25, ///< Select SYS_PWM as clock destination + CLK_DEST_SYS_RESETS = 26, ///< Select SYS_RESETS as clock destination + CLK_DEST_SYS_ROM = 27, ///< Select SYS_ROM as clock destination + CLK_DEST_SYS_ROSC = 28, ///< Select SYS_ROSC as clock destination + CLK_DEST_SYS_PSM = 29, ///< Select SYS_PSM as clock destination + CLK_DEST_SYS_SHA256 = 30, ///< Select SYS_SHA256 as clock destination + CLK_DEST_SYS_SIO = 31, ///< Select SYS_SIO as clock destination + CLK_DEST_PERI_SPI0 = 32, ///< Select PERI_SPI0 as clock destination + CLK_DEST_SYS_SPI0 = 33, ///< Select SYS_SPI0 as clock destination + CLK_DEST_PERI_SPI1 = 34, ///< Select PERI_SPI1 as clock destination + CLK_DEST_SYS_SPI1 = 35, ///< Select SYS_SPI1 as clock destination + CLK_DEST_SYS_SRAM0 = 36, ///< Select SYS_SRAM0 as clock destination + CLK_DEST_SYS_SRAM1 = 37, ///< Select SYS_SRAM1 as clock destination + CLK_DEST_SYS_SRAM2 = 38, ///< Select SYS_SRAM2 as clock destination + CLK_DEST_SYS_SRAM3 = 39, ///< Select SYS_SRAM3 as clock destination + CLK_DEST_SYS_SRAM4 = 40, ///< Select SYS_SRAM4 as clock destination + CLK_DEST_SYS_SRAM5 = 41, ///< Select SYS_SRAM5 as clock destination + CLK_DEST_SYS_SRAM6 = 42, ///< Select SYS_SRAM6 as clock destination + CLK_DEST_SYS_SRAM7 = 43, ///< Select SYS_SRAM7 as clock destination + CLK_DEST_SYS_SRAM8 = 44, ///< Select SYS_SRAM8 as clock destination + CLK_DEST_SYS_SRAM9 = 45, ///< Select SYS_SRAM9 as clock destination + CLK_DEST_SYS_SYSCFG = 46, ///< Select SYS_SYSCFG as clock destination + CLK_DEST_SYS_SYSINFO = 47, ///< Select SYS_SYSINFO as clock destination + CLK_DEST_SYS_TBMAN = 48, ///< Select SYS_TBMAN as clock destination + CLK_DEST_REF_TICKS = 49, ///< Select REF_TICKS as clock destination + CLK_DEST_SYS_TICKS = 50, ///< Select SYS_TICKS as clock destination + CLK_DEST_SYS_TIMER0 = 51, ///< Select SYS_TIMER0 as clock destination + CLK_DEST_SYS_TIMER1 = 52, ///< Select SYS_TIMER1 as clock destination + CLK_DEST_SYS_TRNG = 53, ///< Select SYS_TRNG as clock destination + CLK_DEST_PERI_UART0 = 54, ///< Select PERI_UART0 as clock destination + CLK_DEST_SYS_UART0 = 55, ///< Select SYS_UART0 as clock destination + CLK_DEST_PERI_UART1 = 56, ///< Select PERI_UART1 as clock destination + CLK_DEST_SYS_UART1 = 57, ///< Select SYS_UART1 as clock destination + CLK_DEST_SYS_USBCTRL = 58, ///< Select SYS_USBCTRL as clock destination + CLK_DEST_USB = 59, ///< Select USB as clock destination + CLK_DEST_SYS_WATCHDOG = 60, ///< Select SYS_WATCHDOG as clock destination + CLK_DEST_SYS_XIP = 61, ///< Select SYS_XIP as clock destination + CLK_DEST_SYS_XOSC = 62, ///< Select SYS_XOSC as clock destination + NUM_CLOCK_DESTINATIONS +} clock_dest_num_t; + +/// \tag::clock_hw[] +typedef struct { + _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL + // Clock control, can be changed on-the-fly (except for auxsrc) + // 0x10000000 [28] ENABLED (0) clock generator is enabled + // 0x00100000 [20] NUDGE (0) An edge on this signal shifts the phase of the output by... + // 0x00030000 [17:16] PHASE (0x0) This delays the enable signal by up to 3 cycles of the... + // 0x00001000 [12] DC50 (0) Enables duty cycle correction for odd divisors, can be... + // 0x00000800 [11] ENABLE (0) Starts and stops the clock generator cleanly + // 0x00000400 [10] KILL (0) Asynchronously kills the clock generator, enable must be... + // 0x000001e0 [8:5] AUXSRC (0x0) Selects the auxiliary clock source, will glitch when switching + io_rw_32 ctrl; + + _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV + // 0xffff0000 [31:16] INT (0x0001) Integer part of clock divisor, 0 -> max+1, can be... + // 0x0000ffff [15:0] FRAC (0x0000) Fractional component of the divisor, can be changed on-the-fly + io_rw_32 div; + + _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED + // Indicates which src is currently selected (one-hot) + // 0x00000001 [0] CLK_GPOUT0_SELECTED (1) This slice does not have a glitchless mux (only the... + io_ro_32 selected; +} clock_hw_t; +/// \end::clock_hw[] + +typedef struct { + _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL + // 0x00010000 [16] CLEAR (0) For clearing the resus after the fault that triggered it... + // 0x00001000 [12] FRCE (0) Force a resus, for test purposes only + // 0x00000100 [8] ENABLE (0) Enable resus + // 0x000000ff [7:0] TIMEOUT (0xff) This is expressed as a number of clk_ref cycles + + io_rw_32 ctrl; + + _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS + // 0x00000001 [0] RESUSSED (0) Clock has been resuscitated, correct the error then send... + io_ro_32 status; +} clock_resus_hw_t; + +typedef struct { + _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ + // Reference clock frequency in kHz + // 0x000fffff [19:0] FC0_REF_KHZ (0x00000) + io_rw_32 ref_khz; + + _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ + // Minimum pass frequency in kHz + // 0x01ffffff [24:0] FC0_MIN_KHZ (0x0000000) + io_rw_32 min_khz; + + _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ + // Maximum pass frequency in kHz + // 0x01ffffff [24:0] FC0_MAX_KHZ (0x1ffffff) + io_rw_32 max_khz; + + _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY + // Delays the start of frequency counting to allow the mux to settle + + // 0x00000007 [2:0] FC0_DELAY (0x1) + io_rw_32 delay; + + _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL + // The test interval is 0 + // 0x0000000f [3:0] FC0_INTERVAL (0x8) + io_rw_32 interval; + + _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC + // Clock sent to frequency counter, set to 0 when not required + + // 0x000000ff [7:0] FC0_SRC (0x00) + io_rw_32 src; + + _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS + // Frequency counter status + // 0x10000000 [28] DIED (0) Test clock stopped during test + // 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_done=1 + // 0x00100000 [20] SLOW (0) Test clock slower than expected, only valid when status_done=1 + // 0x00010000 [16] FAIL (0) Test failed + // 0x00001000 [12] WAITING (0) Waiting for test clock to start + // 0x00000100 [8] RUNNING (0) Test running + // 0x00000010 [4] DONE (0) Test complete + // 0x00000001 [0] PASS (0) Test passed + io_ro_32 status; + + _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT + // Result of frequency measurement, only valid when status_done=1 + // 0x3fffffe0 [29:5] KHZ (0x0000000) + // 0x0000001f [4:0] FRAC (0x00) + io_ro_32 result; +} fc_hw_t; + +typedef struct { + clock_hw_t clk[10]; + + _REG_(CLOCKS_DFTCLK_XOSC_CTRL_OFFSET) // CLOCKS_DFTCLK_XOSC_CTRL + // 0x00000003 [1:0] SRC (0x0) + io_rw_32 dftclk_xosc_ctrl; + + _REG_(CLOCKS_DFTCLK_ROSC_CTRL_OFFSET) // CLOCKS_DFTCLK_ROSC_CTRL + // 0x00000003 [1:0] SRC (0x0) + io_rw_32 dftclk_rosc_ctrl; + + _REG_(CLOCKS_DFTCLK_LPOSC_CTRL_OFFSET) // CLOCKS_DFTCLK_LPOSC_CTRL + // 0x00000003 [1:0] SRC (0x0) + io_rw_32 dftclk_lposc_ctrl; + + clock_resus_hw_t resus; + + fc_hw_t fc0; + + union { + struct { + _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 + // enable clock in wake mode + // 0x80000000 [31] CLK_SYS_SIOB (1) + // 0x40000000 [30] CLK_SYS_SHA256 (1) + // 0x20000000 [29] CLK_SYS_RSM (1) + // 0x10000000 [28] CLK_SYS_ROSC (1) + // 0x08000000 [27] CLK_SYS_ROM (1) + // 0x04000000 [26] CLK_SYS_RESETS (1) + // 0x02000000 [25] CLK_SYS_PWM (1) + // 0x01000000 [24] CLK_SYS_POWMAN (1) + // 0x00800000 [23] CLK_REF_POWMAN (1) + // 0x00400000 [22] CLK_SYS_PLL_USB (1) + // 0x00200000 [21] CLK_SYS_PLL_SYS (1) + // 0x00100000 [20] CLK_SYS_PIO2 (1) + // 0x00080000 [19] CLK_SYS_PIO1 (1) + // 0x00040000 [18] CLK_SYS_PIO0 (1) + // 0x00020000 [17] CLK_SYS_PADS (1) + // 0x00010000 [16] CLK_SYS_OTP (1) + // 0x00008000 [15] CLK_REF_OTP (1) + // 0x00004000 [14] CLK_SYS_JTAG (1) + // 0x00002000 [13] CLK_SYS_IO (1) + // 0x00001000 [12] CLK_SYS_I2C1 (1) + // 0x00000800 [11] CLK_SYS_I2C0 (1) + // 0x00000400 [10] CLK_SYS_HSTX (1) + // 0x00000200 [9] CLK_HSTX (1) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) + // 0x00000080 [7] CLK_SYS_DMA (1) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) + // 0x00000020 [5] CLK_SYS_BUSCTRL (1) + // 0x00000010 [4] CLK_SYS_BOOTRAM (1) + // 0x00000008 [3] CLK_SYS_ADC (1) + // 0x00000004 [2] CLK_ADC (1) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 wake_en0; + + _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1 + // enable clock in wake mode + // 0x40000000 [30] CLK_SYS_XOSC (1) + // 0x20000000 [29] CLK_SYS_XIP (1) + // 0x10000000 [28] CLK_SYS_WATCHDOG (1) + // 0x08000000 [27] CLK_USB (1) + // 0x04000000 [26] CLK_SYS_USBCTRL (1) + // 0x02000000 [25] CLK_SYS_UART1 (1) + // 0x01000000 [24] CLK_PERI_UART1 (1) + // 0x00800000 [23] CLK_SYS_UART0 (1) + // 0x00400000 [22] CLK_PERI_UART0 (1) + // 0x00200000 [21] CLK_SYS_TRNG (1) + // 0x00100000 [20] CLK_SYS_TIMER1 (1) + // 0x00080000 [19] CLK_SYS_TIMER0 (1) + // 0x00040000 [18] CLK_SYS_TICKS (1) + // 0x00020000 [17] CLK_REF_TICKS (1) + // 0x00010000 [16] CLK_SYS_TBMAN (1) + // 0x00008000 [15] CLK_SYS_SYSINFO (1) + // 0x00004000 [14] CLK_SYS_SYSCFG (1) + // 0x00002000 [13] CLK_SYS_SRAM9 (1) + // 0x00001000 [12] CLK_SYS_SRAM8 (1) + // 0x00000800 [11] CLK_SYS_SRAM7 (1) + // 0x00000400 [10] CLK_SYS_SRAM6 (1) + // 0x00000200 [9] CLK_SYS_SRAM5 (1) + // 0x00000100 [8] CLK_SYS_SRAM4 (1) + // 0x00000080 [7] CLK_SYS_SRAM3 (1) + // 0x00000040 [6] CLK_SYS_SRAM2 (1) + // 0x00000020 [5] CLK_SYS_SRAM1 (1) + // 0x00000010 [4] CLK_SYS_SRAM0 (1) + // 0x00000008 [3] CLK_SYS_SPI1 (1) + // 0x00000004 [2] CLK_PERI_SPI1 (1) + // 0x00000002 [1] CLK_SYS_SPI0 (1) + // 0x00000001 [0] CLK_PERI_SPI0 (1) + io_rw_32 wake_en1; + }; + // (Description copied from array index 0 register CLOCKS_WAKE_EN0 applies similarly to other array indexes) + _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0 + // enable clock in wake mode + // 0x80000000 [31] CLK_SYS_SIO (1) + // 0x40000000 [30] CLK_SYS_SHA256 (1) + // 0x20000000 [29] CLK_SYS_PSM (1) + // 0x10000000 [28] CLK_SYS_ROSC (1) + // 0x08000000 [27] CLK_SYS_ROM (1) + // 0x04000000 [26] CLK_SYS_RESETS (1) + // 0x02000000 [25] CLK_SYS_PWM (1) + // 0x01000000 [24] CLK_SYS_POWMAN (1) + // 0x00800000 [23] CLK_REF_POWMAN (1) + // 0x00400000 [22] CLK_SYS_PLL_USB (1) + // 0x00200000 [21] CLK_SYS_PLL_SYS (1) + // 0x00100000 [20] CLK_SYS_PIO2 (1) + // 0x00080000 [19] CLK_SYS_PIO1 (1) + // 0x00040000 [18] CLK_SYS_PIO0 (1) + // 0x00020000 [17] CLK_SYS_PADS (1) + // 0x00010000 [16] CLK_SYS_OTP (1) + // 0x00008000 [15] CLK_REF_OTP (1) + // 0x00004000 [14] CLK_SYS_JTAG (1) + // 0x00002000 [13] CLK_SYS_IO (1) + // 0x00001000 [12] CLK_SYS_I2C1 (1) + // 0x00000800 [11] CLK_SYS_I2C0 (1) + // 0x00000400 [10] CLK_SYS_HSTX (1) + // 0x00000200 [9] CLK_HSTX (1) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) + // 0x00000080 [7] CLK_SYS_DMA (1) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) + // 0x00000020 [5] CLK_SYS_BUSCTRL (1) + // 0x00000010 [4] CLK_SYS_BOOTRAM (1) + // 0x00000008 [3] CLK_SYS_ADC (1) + // 0x00000004 [2] CLK_ADC (1) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 wake_en[2]; + }; + + union { + struct { + _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 + // enable clock in sleep mode + // 0x80000000 [31] CLK_SYS_SIOB (1) + // 0x40000000 [30] CLK_SYS_SHA256 (1) + // 0x20000000 [29] CLK_SYS_RSM (1) + // 0x10000000 [28] CLK_SYS_ROSC (1) + // 0x08000000 [27] CLK_SYS_ROM (1) + // 0x04000000 [26] CLK_SYS_RESETS (1) + // 0x02000000 [25] CLK_SYS_PWM (1) + // 0x01000000 [24] CLK_SYS_POWMAN (1) + // 0x00800000 [23] CLK_REF_POWMAN (1) + // 0x00400000 [22] CLK_SYS_PLL_USB (1) + // 0x00200000 [21] CLK_SYS_PLL_SYS (1) + // 0x00100000 [20] CLK_SYS_PIO2 (1) + // 0x00080000 [19] CLK_SYS_PIO1 (1) + // 0x00040000 [18] CLK_SYS_PIO0 (1) + // 0x00020000 [17] CLK_SYS_PADS (1) + // 0x00010000 [16] CLK_SYS_OTP (1) + // 0x00008000 [15] CLK_REF_OTP (1) + // 0x00004000 [14] CLK_SYS_JTAG (1) + // 0x00002000 [13] CLK_SYS_IO (1) + // 0x00001000 [12] CLK_SYS_I2C1 (1) + // 0x00000800 [11] CLK_SYS_I2C0 (1) + // 0x00000400 [10] CLK_SYS_HSTX (1) + // 0x00000200 [9] CLK_HSTX (1) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) + // 0x00000080 [7] CLK_SYS_DMA (1) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) + // 0x00000020 [5] CLK_SYS_BUSCTRL (1) + // 0x00000010 [4] CLK_SYS_BOOTRAM (1) + // 0x00000008 [3] CLK_SYS_ADC (1) + // 0x00000004 [2] CLK_ADC (1) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 sleep_en0; + + _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1 + // enable clock in sleep mode + // 0x40000000 [30] CLK_SYS_XOSC (1) + // 0x20000000 [29] CLK_SYS_XIP (1) + // 0x10000000 [28] CLK_SYS_WATCHDOG (1) + // 0x08000000 [27] CLK_USB (1) + // 0x04000000 [26] CLK_SYS_USBCTRL (1) + // 0x02000000 [25] CLK_SYS_UART1 (1) + // 0x01000000 [24] CLK_PERI_UART1 (1) + // 0x00800000 [23] CLK_SYS_UART0 (1) + // 0x00400000 [22] CLK_PERI_UART0 (1) + // 0x00200000 [21] CLK_SYS_TRNG (1) + // 0x00100000 [20] CLK_SYS_TIMER1 (1) + // 0x00080000 [19] CLK_SYS_TIMER0 (1) + // 0x00040000 [18] CLK_SYS_TICKS (1) + // 0x00020000 [17] CLK_REF_TICKS (1) + // 0x00010000 [16] CLK_SYS_TBMAN (1) + // 0x00008000 [15] CLK_SYS_SYSINFO (1) + // 0x00004000 [14] CLK_SYS_SYSCFG (1) + // 0x00002000 [13] CLK_SYS_SRAM9 (1) + // 0x00001000 [12] CLK_SYS_SRAM8 (1) + // 0x00000800 [11] CLK_SYS_SRAM7 (1) + // 0x00000400 [10] CLK_SYS_SRAM6 (1) + // 0x00000200 [9] CLK_SYS_SRAM5 (1) + // 0x00000100 [8] CLK_SYS_SRAM4 (1) + // 0x00000080 [7] CLK_SYS_SRAM3 (1) + // 0x00000040 [6] CLK_SYS_SRAM2 (1) + // 0x00000020 [5] CLK_SYS_SRAM1 (1) + // 0x00000010 [4] CLK_SYS_SRAM0 (1) + // 0x00000008 [3] CLK_SYS_SPI1 (1) + // 0x00000004 [2] CLK_PERI_SPI1 (1) + // 0x00000002 [1] CLK_SYS_SPI0 (1) + // 0x00000001 [0] CLK_PERI_SPI0 (1) + io_rw_32 sleep_en1; + }; + // (Description copied from array index 0 register CLOCKS_SLEEP_EN0 applies similarly to other array indexes) + _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0 + // enable clock in sleep mode + // 0x80000000 [31] CLK_SYS_SIO (1) + // 0x40000000 [30] CLK_SYS_SHA256 (1) + // 0x20000000 [29] CLK_SYS_PSM (1) + // 0x10000000 [28] CLK_SYS_ROSC (1) + // 0x08000000 [27] CLK_SYS_ROM (1) + // 0x04000000 [26] CLK_SYS_RESETS (1) + // 0x02000000 [25] CLK_SYS_PWM (1) + // 0x01000000 [24] CLK_SYS_POWMAN (1) + // 0x00800000 [23] CLK_REF_POWMAN (1) + // 0x00400000 [22] CLK_SYS_PLL_USB (1) + // 0x00200000 [21] CLK_SYS_PLL_SYS (1) + // 0x00100000 [20] CLK_SYS_PIO2 (1) + // 0x00080000 [19] CLK_SYS_PIO1 (1) + // 0x00040000 [18] CLK_SYS_PIO0 (1) + // 0x00020000 [17] CLK_SYS_PADS (1) + // 0x00010000 [16] CLK_SYS_OTP (1) + // 0x00008000 [15] CLK_REF_OTP (1) + // 0x00004000 [14] CLK_SYS_JTAG (1) + // 0x00002000 [13] CLK_SYS_IO (1) + // 0x00001000 [12] CLK_SYS_I2C1 (1) + // 0x00000800 [11] CLK_SYS_I2C0 (1) + // 0x00000400 [10] CLK_SYS_HSTX (1) + // 0x00000200 [9] CLK_HSTX (1) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1) + // 0x00000080 [7] CLK_SYS_DMA (1) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (1) + // 0x00000020 [5] CLK_SYS_BUSCTRL (1) + // 0x00000010 [4] CLK_SYS_BOOTRAM (1) + // 0x00000008 [3] CLK_SYS_ADC (1) + // 0x00000004 [2] CLK_ADC (1) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (1) + // 0x00000001 [0] CLK_SYS_CLOCKS (1) + io_rw_32 sleep_en[2]; + }; + + union { + struct { + _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 + // indicates the state of the clock enable + // 0x80000000 [31] CLK_SYS_SIOB (0) + // 0x40000000 [30] CLK_SYS_SHA256 (0) + // 0x20000000 [29] CLK_SYS_RSM (0) + // 0x10000000 [28] CLK_SYS_ROSC (0) + // 0x08000000 [27] CLK_SYS_ROM (0) + // 0x04000000 [26] CLK_SYS_RESETS (0) + // 0x02000000 [25] CLK_SYS_PWM (0) + // 0x01000000 [24] CLK_SYS_POWMAN (0) + // 0x00800000 [23] CLK_REF_POWMAN (0) + // 0x00400000 [22] CLK_SYS_PLL_USB (0) + // 0x00200000 [21] CLK_SYS_PLL_SYS (0) + // 0x00100000 [20] CLK_SYS_PIO2 (0) + // 0x00080000 [19] CLK_SYS_PIO1 (0) + // 0x00040000 [18] CLK_SYS_PIO0 (0) + // 0x00020000 [17] CLK_SYS_PADS (0) + // 0x00010000 [16] CLK_SYS_OTP (0) + // 0x00008000 [15] CLK_REF_OTP (0) + // 0x00004000 [14] CLK_SYS_JTAG (0) + // 0x00002000 [13] CLK_SYS_IO (0) + // 0x00001000 [12] CLK_SYS_I2C1 (0) + // 0x00000800 [11] CLK_SYS_I2C0 (0) + // 0x00000400 [10] CLK_SYS_HSTX (0) + // 0x00000200 [9] CLK_HSTX (0) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (0) + // 0x00000080 [7] CLK_SYS_DMA (0) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (0) + // 0x00000020 [5] CLK_SYS_BUSCTRL (0) + // 0x00000010 [4] CLK_SYS_BOOTRAM (0) + // 0x00000008 [3] CLK_SYS_ADC (0) + // 0x00000004 [2] CLK_ADC (0) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (0) + // 0x00000001 [0] CLK_SYS_CLOCKS (0) + io_ro_32 enabled0; + + _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1 + // indicates the state of the clock enable + // 0x40000000 [30] CLK_SYS_XOSC (0) + // 0x20000000 [29] CLK_SYS_XIP (0) + // 0x10000000 [28] CLK_SYS_WATCHDOG (0) + // 0x08000000 [27] CLK_USB (0) + // 0x04000000 [26] CLK_SYS_USBCTRL (0) + // 0x02000000 [25] CLK_SYS_UART1 (0) + // 0x01000000 [24] CLK_PERI_UART1 (0) + // 0x00800000 [23] CLK_SYS_UART0 (0) + // 0x00400000 [22] CLK_PERI_UART0 (0) + // 0x00200000 [21] CLK_SYS_TRNG (0) + // 0x00100000 [20] CLK_SYS_TIMER1 (0) + // 0x00080000 [19] CLK_SYS_TIMER0 (0) + // 0x00040000 [18] CLK_SYS_TICKS (0) + // 0x00020000 [17] CLK_REF_TICKS (0) + // 0x00010000 [16] CLK_SYS_TBMAN (0) + // 0x00008000 [15] CLK_SYS_SYSINFO (0) + // 0x00004000 [14] CLK_SYS_SYSCFG (0) + // 0x00002000 [13] CLK_SYS_SRAM9 (0) + // 0x00001000 [12] CLK_SYS_SRAM8 (0) + // 0x00000800 [11] CLK_SYS_SRAM7 (0) + // 0x00000400 [10] CLK_SYS_SRAM6 (0) + // 0x00000200 [9] CLK_SYS_SRAM5 (0) + // 0x00000100 [8] CLK_SYS_SRAM4 (0) + // 0x00000080 [7] CLK_SYS_SRAM3 (0) + // 0x00000040 [6] CLK_SYS_SRAM2 (0) + // 0x00000020 [5] CLK_SYS_SRAM1 (0) + // 0x00000010 [4] CLK_SYS_SRAM0 (0) + // 0x00000008 [3] CLK_SYS_SPI1 (0) + // 0x00000004 [2] CLK_PERI_SPI1 (0) + // 0x00000002 [1] CLK_SYS_SPI0 (0) + // 0x00000001 [0] CLK_PERI_SPI0 (0) + io_ro_32 enabled1; + }; + // (Description copied from array index 0 register CLOCKS_ENABLED0 applies similarly to other array indexes) + _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0 + // indicates the state of the clock enable + // 0x80000000 [31] CLK_SYS_SIO (0) + // 0x40000000 [30] CLK_SYS_SHA256 (0) + // 0x20000000 [29] CLK_SYS_PSM (0) + // 0x10000000 [28] CLK_SYS_ROSC (0) + // 0x08000000 [27] CLK_SYS_ROM (0) + // 0x04000000 [26] CLK_SYS_RESETS (0) + // 0x02000000 [25] CLK_SYS_PWM (0) + // 0x01000000 [24] CLK_SYS_POWMAN (0) + // 0x00800000 [23] CLK_REF_POWMAN (0) + // 0x00400000 [22] CLK_SYS_PLL_USB (0) + // 0x00200000 [21] CLK_SYS_PLL_SYS (0) + // 0x00100000 [20] CLK_SYS_PIO2 (0) + // 0x00080000 [19] CLK_SYS_PIO1 (0) + // 0x00040000 [18] CLK_SYS_PIO0 (0) + // 0x00020000 [17] CLK_SYS_PADS (0) + // 0x00010000 [16] CLK_SYS_OTP (0) + // 0x00008000 [15] CLK_REF_OTP (0) + // 0x00004000 [14] CLK_SYS_JTAG (0) + // 0x00002000 [13] CLK_SYS_IO (0) + // 0x00001000 [12] CLK_SYS_I2C1 (0) + // 0x00000800 [11] CLK_SYS_I2C0 (0) + // 0x00000400 [10] CLK_SYS_HSTX (0) + // 0x00000200 [9] CLK_HSTX (0) + // 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (0) + // 0x00000080 [7] CLK_SYS_DMA (0) + // 0x00000040 [6] CLK_SYS_BUSFABRIC (0) + // 0x00000020 [5] CLK_SYS_BUSCTRL (0) + // 0x00000010 [4] CLK_SYS_BOOTRAM (0) + // 0x00000008 [3] CLK_SYS_ADC (0) + // 0x00000004 [2] CLK_ADC (0) + // 0x00000002 [1] CLK_SYS_ACCESSCTRL (0) + // 0x00000001 [0] CLK_SYS_CLOCKS (0) + io_ro_32 enabled[2]; + }; + + _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR + // Raw Interrupts + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_ro_32 intr; + + _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE + // Interrupt Enable + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_rw_32 inte; + + _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF + // Interrupt Force + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_rw_32 intf; + + _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] CLK_SYS_RESUS (0) + io_ro_32 ints; +} clocks_hw_t; + +#define clocks_hw ((clocks_hw_t *)CLOCKS_BASE) +static_assert(sizeof (clocks_hw_t) == 0x00d4, ""); + +#endif // _HARDWARE_STRUCTS_CLOCKS_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/coresight_trace.h b/lib/pico-sdk/rp2350/hardware/structs/coresight_trace.h new file mode 100644 index 000000000000..61ffb06234d6 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/coresight_trace.h @@ -0,0 +1,43 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_CORESIGHT_TRACE_H +#define _HARDWARE_STRUCTS_CORESIGHT_TRACE_H + +/** + * \file rp2350/coresight_trace.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/coresight_trace.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_coresight_trace +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/coresight_trace.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(CORESIGHT_TRACE_CTRL_STATUS_OFFSET) // CORESIGHT_TRACE_CTRL_STATUS + // Control and status register + // 0x00000002 [1] TRACE_CAPTURE_FIFO_OVERFLOW (0) This status flag is set high when trace data has been... + // 0x00000001 [0] TRACE_CAPTURE_FIFO_FLUSH (1) Set to 1 to continuously hold the trace FIFO in a... + io_rw_32 ctrl_status; + + _REG_(CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET) // CORESIGHT_TRACE_TRACE_CAPTURE_FIFO + // FIFO for trace data captured from the TPIU + // 0xffffffff [31:0] RDATA (0x00000000) Read from an 8 x 32-bit FIFO containing trace data... + io_ro_32 trace_capture_fifo; +} coresight_trace_hw_t; + +#define coresight_trace_hw ((coresight_trace_hw_t *)CORESIGHT_TRACE_BASE) +static_assert(sizeof (coresight_trace_hw_t) == 0x0008, ""); + +#endif // _HARDWARE_STRUCTS_CORESIGHT_TRACE_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/dma.h b/lib/pico-sdk/rp2350/hardware/structs/dma.h new file mode 100644 index 000000000000..6097a98440e0 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/dma.h @@ -0,0 +1,336 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_DMA_H +#define _HARDWARE_STRUCTS_DMA_H + +/** + * \file rp2350/dma.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/dma.h" +#include "hardware/structs/dma_debug.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_dma +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR + // DMA Channel 0 Read Address pointer + // 0xffffffff [31:0] CH0_READ_ADDR (0x00000000) This register updates automatically each time a read completes + io_rw_32 read_addr; + + _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR + // DMA Channel 0 Write Address pointer + // 0xffffffff [31:0] CH0_WRITE_ADDR (0x00000000) This register updates automatically each time a write completes + io_rw_32 write_addr; + + _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT + // DMA Channel 0 Transfer Count + // 0xf0000000 [31:28] MODE (0x0) When MODE is 0x0, the transfer count decrements with... + // 0x0fffffff [27:0] COUNT (0x0000000) 28-bit transfer count (256 million transfers maximum) + io_rw_32 transfer_count; + + _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG + // DMA Channel 0 Control and Status + // 0x80000000 [31] AHB_ERROR (0) Logical OR of the READ_ERROR and WRITE_ERROR flags + // 0x40000000 [30] READ_ERROR (0) If 1, the channel received a read bus error + // 0x20000000 [29] WRITE_ERROR (0) If 1, the channel received a write bus error + // 0x04000000 [26] BUSY (0) This flag goes high when the channel starts a new... + // 0x02000000 [25] SNIFF_EN (0) If 1, this channel's data transfers are visible to the... + // 0x01000000 [24] BSWAP (0) Apply byte-swap transformation to DMA data + // 0x00800000 [23] IRQ_QUIET (0) In QUIET mode, the channel does not generate IRQs at the... + // 0x007e0000 [22:17] TREQ_SEL (0x00) Select a Transfer Request signal + // 0x0001e000 [16:13] CHAIN_TO (0x0) When this channel completes, it will trigger the channel... + // 0x00001000 [12] RING_SEL (0) Select whether RING_SIZE applies to read or write addresses + // 0x00000f00 [11:8] RING_SIZE (0x0) Size of address wrap region + // 0x00000080 [7] INCR_WRITE_REV (0) If 1, and INCR_WRITE is 1, the write address is... + // 0x00000040 [6] INCR_WRITE (0) If 1, the write address increments with each transfer + // 0x00000020 [5] INCR_READ_REV (0) If 1, and INCR_READ is 1, the read address is... + // 0x00000010 [4] INCR_READ (0) If 1, the read address increments with each transfer + // 0x0000000c [3:2] DATA_SIZE (0x0) Set the size of each bus transfer (byte/halfword/word) + // 0x00000002 [1] HIGH_PRIORITY (0) HIGH_PRIORITY gives a channel preferential treatment in... + // 0x00000001 [0] EN (0) DMA Channel Enable + io_rw_32 ctrl_trig; + + _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL + // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL1_CTRL (-) + io_rw_32 al1_ctrl; + + _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR + // Alias for channel 0 READ_ADDR register + // 0xffffffff [31:0] CH0_AL1_READ_ADDR (-) + io_rw_32 al1_read_addr; + + _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR + // Alias for channel 0 WRITE_ADDR register + // 0xffffffff [31:0] CH0_AL1_WRITE_ADDR (-) + io_rw_32 al1_write_addr; + + _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG + // Alias for channel 0 TRANS_COUNT register + + // 0xffffffff [31:0] CH0_AL1_TRANS_COUNT_TRIG (-) + io_rw_32 al1_transfer_count_trig; + + _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL + // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL2_CTRL (-) + io_rw_32 al2_ctrl; + + _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT + // Alias for channel 0 TRANS_COUNT register + // 0xffffffff [31:0] CH0_AL2_TRANS_COUNT (-) + io_rw_32 al2_transfer_count; + + _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR + // Alias for channel 0 READ_ADDR register + // 0xffffffff [31:0] CH0_AL2_READ_ADDR (-) + io_rw_32 al2_read_addr; + + _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG + // Alias for channel 0 WRITE_ADDR register + + // 0xffffffff [31:0] CH0_AL2_WRITE_ADDR_TRIG (-) + io_rw_32 al2_write_addr_trig; + + _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL + // Alias for channel 0 CTRL register + // 0xffffffff [31:0] CH0_AL3_CTRL (-) + io_rw_32 al3_ctrl; + + _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR + // Alias for channel 0 WRITE_ADDR register + // 0xffffffff [31:0] CH0_AL3_WRITE_ADDR (-) + io_rw_32 al3_write_addr; + + _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT + // Alias for channel 0 TRANS_COUNT register + // 0xffffffff [31:0] CH0_AL3_TRANS_COUNT (-) + io_rw_32 al3_transfer_count; + + _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG + // Alias for channel 0 READ_ADDR register + + // 0xffffffff [31:0] CH0_AL3_READ_ADDR_TRIG (-) + io_rw_32 al3_read_addr_trig; +} dma_channel_hw_t; + +typedef struct { + _REG_(DMA_MPU_BAR0_OFFSET) // DMA_MPU_BAR0 + // Base address register for MPU region 0 + // 0xffffffe0 [31:5] ADDR (0x0000000) This MPU region matches addresses where addr[31:5] (the... + io_rw_32 bar; + + _REG_(DMA_MPU_LAR0_OFFSET) // DMA_MPU_LAR0 + // Limit address register for MPU region 0 + // 0xffffffe0 [31:5] ADDR (0x0000000) Limit address bits 31:5 + // 0x00000004 [2] S (0) Determines the Secure/Non-secure (=1/0) status of... + // 0x00000002 [1] P (0) Determines the Privileged/Unprivileged (=1/0) status of... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 lar; +} dma_mpu_region_hw_t; + +typedef struct { + _REG_(DMA_INTR_OFFSET) // DMA_INTR + // Interrupt Status (raw) + // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 + io_rw_32 intr; + + _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 + // Interrupt Enables for IRQ 0 + // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 + io_rw_32 inte; + + _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 + // Force Interrupts + // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTS0 + io_rw_32 intf; + + _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 + // Interrupt Status for IRQ 0 + // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints; +} dma_irq_ctrl_hw_t; + +typedef struct { + dma_channel_hw_t ch[16]; + + union { + struct { + _REG_(DMA_INTR_OFFSET) // DMA_INTR + // Interrupt Status (raw) + // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 + io_rw_32 intr; + + _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 + // Interrupt Enables for IRQ 0 + // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 + io_rw_32 inte0; + + _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 + // Force Interrupts + // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0 + io_rw_32 intf0; + + _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 + // Interrupt Status for IRQ 0 + // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints0; + + uint32_t __pad0; + + _REG_(DMA_INTE1_OFFSET) // DMA_INTE1 + // Interrupt Enables for IRQ 1 + // 0x0000ffff [15:0] INTE1 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 1 + io_rw_32 inte1; + + _REG_(DMA_INTF1_OFFSET) // DMA_INTF1 + // Force Interrupts for IRQ 1 + // 0x0000ffff [15:0] INTF1 (0x0000) Write 1s to force the corresponding bits in INTF1 + io_rw_32 intf1; + + _REG_(DMA_INTS1_OFFSET) // DMA_INTS1 + // Interrupt Status (masked) for IRQ 1 + // 0x0000ffff [15:0] INTS1 (0x0000) Indicates active channel interrupt requests which are... + io_rw_32 ints1; + + uint32_t __pad1; + + _REG_(DMA_INTE2_OFFSET) // DMA_INTE2 + // Interrupt Enables for IRQ 2 + // 0x0000ffff [15:0] INTE2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2 + io_rw_32 inte2; + + _REG_(DMA_INTF2_OFFSET) // DMA_INTF2 + // Force Interrupts for IRQ 2 + // 0x0000ffff [15:0] INTF2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2 + io_rw_32 intf2; + + _REG_(DMA_INTS2_OFFSET) // DMA_INTS2 + // Interrupt Status (masked) for IRQ 2 + // 0x0000ffff [15:0] INTS2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2 + io_rw_32 ints2; + + uint32_t __pad2; + + _REG_(DMA_INTE3_OFFSET) // DMA_INTE3 + // Interrupt Enables for IRQ 3 + // 0x0000ffff [15:0] INTE3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3 + io_rw_32 inte3; + + _REG_(DMA_INTF3_OFFSET) // DMA_INTF3 + // Force Interrupts for IRQ 3 + // 0x0000ffff [15:0] INTF3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3 + io_rw_32 intf3; + + _REG_(DMA_INTS3_OFFSET) // DMA_INTS3 + // Interrupt Status (masked) for IRQ 3 + // 0x0000ffff [15:0] INTS3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3 + io_rw_32 ints3; + }; + dma_irq_ctrl_hw_t irq_ctrl[4]; + }; + + // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes) + _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0 + // Pacing timer (generate periodic TREQs) + // 0xffff0000 [31:16] X (0x0000) Pacing Timer Dividend + // 0x0000ffff [15:0] Y (0x0000) Pacing Timer Divisor + io_rw_32 timer[4]; + + _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER + // Trigger one or more channels simultaneously + // 0x0000ffff [15:0] MULTI_CHAN_TRIGGER (0x0000) Each bit in this register corresponds to a DMA channel + io_wo_32 multi_channel_trigger; + + _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL + // Sniffer Control + // 0x00000800 [11] OUT_INV (0) If set, the result appears inverted (bitwise complement)... + // 0x00000400 [10] OUT_REV (0) If set, the result appears bit-reversed when read + // 0x00000200 [9] BSWAP (0) Locally perform a byte reverse on the sniffed data,... + // 0x000001e0 [8:5] CALC (0x0) + // 0x0000001e [4:1] DMACH (0x0) DMA channel for Sniffer to observe + // 0x00000001 [0] EN (0) Enable sniffer + io_rw_32 sniff_ctrl; + + _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA + // Data accumulator for sniff hardware + // 0xffffffff [31:0] SNIFF_DATA (0x00000000) Write an initial seed value here before starting a DMA... + io_rw_32 sniff_data; + + uint32_t _pad0; + + _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS + // Debug RAF, WAF, TDF levels + // 0x00ff0000 [23:16] RAF_LVL (0x00) Current Read-Address-FIFO fill level + // 0x0000ff00 [15:8] WAF_LVL (0x00) Current Write-Address-FIFO fill level + // 0x000000ff [7:0] TDF_LVL (0x00) Current Transfer-Data-FIFO fill level + io_ro_32 fifo_levels; + + _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT + // Abort an in-progress transfer sequence on one or more channels + // 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel + io_wo_32 abort; + + _REG_(DMA_N_CHANNELS_OFFSET) // DMA_N_CHANNELS + // The number of channels this DMA instance is equipped with + // 0x0000001f [4:0] N_CHANNELS (-) + io_ro_32 n_channels; + + uint32_t _pad1[5]; + + // (Description copied from array index 0 register DMA_SECCFG_CH0 applies similarly to other array indexes) + _REG_(DMA_SECCFG_CH0_OFFSET) // DMA_SECCFG_CH0 + // Security level configuration for channel 0. + // 0x00000004 [2] LOCK (0) LOCK is 0 at reset, and is set to 1 automatically upon a... + // 0x00000002 [1] S (1) Secure channel + // 0x00000001 [0] P (1) Privileged channel + io_rw_32 seccfg_ch[16]; + + // (Description copied from array index 0 register DMA_SECCFG_IRQ0 applies similarly to other array indexes) + _REG_(DMA_SECCFG_IRQ0_OFFSET) // DMA_SECCFG_IRQ0 + // Security configuration for IRQ 0 + // 0x00000002 [1] S (1) Secure IRQ + // 0x00000001 [0] P (1) Privileged IRQ + io_rw_32 seccfg_irq[4]; + + _REG_(DMA_SECCFG_MISC_OFFSET) // DMA_SECCFG_MISC + // Miscellaneous security configuration + // 0x00000200 [9] TIMER3_S (1) If 1, the TIMER3 register is only accessible from a... + // 0x00000100 [8] TIMER3_P (1) If 1, the TIMER3 register is only accessible from a... + // 0x00000080 [7] TIMER2_S (1) If 1, the TIMER2 register is only accessible from a... + // 0x00000040 [6] TIMER2_P (1) If 1, the TIMER2 register is only accessible from a... + // 0x00000020 [5] TIMER1_S (1) If 1, the TIMER1 register is only accessible from a... + // 0x00000010 [4] TIMER1_P (1) If 1, the TIMER1 register is only accessible from a... + // 0x00000008 [3] TIMER0_S (1) If 1, the TIMER0 register is only accessible from a... + // 0x00000004 [2] TIMER0_P (1) If 1, the TIMER0 register is only accessible from a... + // 0x00000002 [1] SNIFF_S (1) If 1, the sniffer can see data transfers from Secure... + // 0x00000001 [0] SNIFF_P (1) If 1, the sniffer can see data transfers from Privileged... + io_rw_32 seccfg_misc; + + uint32_t _pad2[11]; + + _REG_(DMA_MPU_CTRL_OFFSET) // DMA_MPU_CTRL + // Control register for DMA MPU + // 0x00000008 [3] NS_HIDE_ADDR (0) By default, when a region's S bit is clear,... + // 0x00000004 [2] S (0) Determine whether an address not covered by an active... + // 0x00000002 [1] P (0) Determine whether an address not covered by an active... + io_rw_32 mpu_ctrl; + + dma_mpu_region_hw_t mpu_region[8]; +} dma_hw_t; + +#define dma_hw ((dma_hw_t *)DMA_BASE) +static_assert(sizeof (dma_hw_t) == 0x0544, ""); + +#endif // _HARDWARE_STRUCTS_DMA_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/dma_debug.h b/lib/pico-sdk/rp2350/hardware/structs/dma_debug.h new file mode 100644 index 000000000000..73c8bf43e048 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/dma_debug.h @@ -0,0 +1,47 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_DMA_DEBUG_H +#define _HARDWARE_STRUCTS_DMA_DEBUG_H + +/** + * \file rp2350/dma_debug.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/dma.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_dma +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/dma.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(DMA_CH0_DBG_CTDREQ_OFFSET) // DMA_CH0_DBG_CTDREQ + // Read: get channel DREQ counter (i + // 0x0000003f [5:0] CH0_DBG_CTDREQ (0x00) + io_rw_32 dbg_ctdreq; + + _REG_(DMA_CH0_DBG_TCR_OFFSET) // DMA_CH0_DBG_TCR + // Read to get channel TRANS_COUNT reload value, i + // 0xffffffff [31:0] CH0_DBG_TCR (0x00000000) + io_ro_32 dbg_tcr; + + uint32_t _pad0[14]; +} dma_debug_channel_hw_t; + +typedef struct { + dma_debug_channel_hw_t ch[16]; +} dma_debug_hw_t; + +#define dma_debug_hw ((dma_debug_hw_t *)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) + +#endif // _HARDWARE_STRUCTS_DMA_DEBUG_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/glitch_detector.h b/lib/pico-sdk/rp2350/hardware/structs/glitch_detector.h new file mode 100644 index 000000000000..f25ebb23a194 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/glitch_detector.h @@ -0,0 +1,71 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_GLITCH_DETECTOR_H +#define _HARDWARE_STRUCTS_GLITCH_DETECTOR_H + +/** + * \file rp2350/glitch_detector.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/glitch_detector.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_glitch_detector +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/glitch_detector.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(GLITCH_DETECTOR_ARM_OFFSET) // GLITCH_DETECTOR_ARM + // Forcibly arm the glitch detectors, if they are not already armed by OTP + // 0x0000ffff [15:0] ARM (0x5bad) + io_rw_32 arm; + + _REG_(GLITCH_DETECTOR_DISARM_OFFSET) // GLITCH_DETECTOR_DISARM + // 0x0000ffff [15:0] DISARM (0x0000) Forcibly disarm the glitch detectors, if they are armed by OTP + io_rw_32 disarm; + + _REG_(GLITCH_DETECTOR_SENSITIVITY_OFFSET) // GLITCH_DETECTOR_SENSITIVITY + // Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults + // 0xff000000 [31:24] DEFAULT (0x00) + // 0x0000c000 [15:14] DET3_INV (0x0) Must be the inverse of DET3, else the default value is used + // 0x00003000 [13:12] DET2_INV (0x0) Must be the inverse of DET2, else the default value is used + // 0x00000c00 [11:10] DET1_INV (0x0) Must be the inverse of DET1, else the default value is used + // 0x00000300 [9:8] DET0_INV (0x0) Must be the inverse of DET0, else the default value is used + // 0x000000c0 [7:6] DET3 (0x0) Set sensitivity for detector 3 + // 0x00000030 [5:4] DET2 (0x0) Set sensitivity for detector 2 + // 0x0000000c [3:2] DET1 (0x0) Set sensitivity for detector 1 + // 0x00000003 [1:0] DET0 (0x0) Set sensitivity for detector 0 + io_rw_32 sensitivity; + + _REG_(GLITCH_DETECTOR_LOCK_OFFSET) // GLITCH_DETECTOR_LOCK + // 0x000000ff [7:0] LOCK (0x00) Write any nonzero value to disable writes to ARM,... + io_rw_32 lock; + + _REG_(GLITCH_DETECTOR_TRIG_STATUS_OFFSET) // GLITCH_DETECTOR_TRIG_STATUS + // Set when a detector output triggers + // 0x00000008 [3] DET3 (0) + // 0x00000004 [2] DET2 (0) + // 0x00000002 [1] DET1 (0) + // 0x00000001 [0] DET0 (0) + io_rw_32 trig_status; + + _REG_(GLITCH_DETECTOR_TRIG_FORCE_OFFSET) // GLITCH_DETECTOR_TRIG_FORCE + // Simulate the firing of one or more detectors + // 0x0000000f [3:0] TRIG_FORCE (0x0) + io_wo_32 trig_force; +} glitch_detector_hw_t; + +#define glitch_detector_hw ((glitch_detector_hw_t *)GLITCH_DETECTOR_BASE) +static_assert(sizeof (glitch_detector_hw_t) == 0x0018, ""); + +#endif // _HARDWARE_STRUCTS_GLITCH_DETECTOR_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/hstx_ctrl.h b/lib/pico-sdk/rp2350/hardware/structs/hstx_ctrl.h new file mode 100644 index 000000000000..735ecee7e9a8 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/hstx_ctrl.h @@ -0,0 +1,70 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_HSTX_CTRL_H +#define _HARDWARE_STRUCTS_HSTX_CTRL_H + +/** + * \file rp2350/hstx_ctrl.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/hstx_ctrl.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_hstx_ctrl +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/hstx_ctrl.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(HSTX_CTRL_CSR_OFFSET) // HSTX_CTRL_CSR + // 0xf0000000 [31:28] CLKDIV (0x1) Clock period of the generated clock, measured in HSTX... + // 0x0f000000 [27:24] CLKPHASE (0x0) Set the initial phase of the generated clock + // 0x001f0000 [20:16] N_SHIFTS (0x05) Number of times to shift the shift register before... + // 0x00001f00 [12:8] SHIFT (0x06) How many bits to right-rotate the shift register by each cycle + // 0x00000060 [6:5] COUPLED_SEL (0x0) Select which PIO to use for coupled mode operation + // 0x00000010 [4] COUPLED_MODE (0) Enable the PIO-to-HSTX 1:1 connection + // 0x00000002 [1] EXPAND_EN (0) Enable the command expander + // 0x00000001 [0] EN (0) When EN is 1, the HSTX will shift out data as it appears... + io_rw_32 csr; + + // (Description copied from array index 0 register HSTX_CTRL_BIT0 applies similarly to other array indexes) + _REG_(HSTX_CTRL_BIT0_OFFSET) // HSTX_CTRL_BIT0 + // Data control register for output bit 0 + // 0x00020000 [17] CLK (0) Connect this output to the generated clock, rather than... + // 0x00010000 [16] INV (0) Invert this data output (logical NOT) + // 0x00001f00 [12:8] SEL_N (0x00) Shift register data bit select for the second half of... + // 0x0000001f [4:0] SEL_P (0x00) Shift register data bit select for the first half of the... + io_rw_32 bit[8]; + + _REG_(HSTX_CTRL_EXPAND_SHIFT_OFFSET) // HSTX_CTRL_EXPAND_SHIFT + // Configure the optional shifter inside the command expander + // 0x1f000000 [28:24] ENC_N_SHIFTS (0x01) Number of times to consume from the shift register... + // 0x001f0000 [20:16] ENC_SHIFT (0x00) How many bits to right-rotate the shift register by each... + // 0x00001f00 [12:8] RAW_N_SHIFTS (0x01) Number of times to consume from the shift register... + // 0x0000001f [4:0] RAW_SHIFT (0x00) How many bits to right-rotate the shift register by each... + io_rw_32 expand_shift; + + _REG_(HSTX_CTRL_EXPAND_TMDS_OFFSET) // HSTX_CTRL_EXPAND_TMDS + // Configure the optional TMDS encoder inside the command expander + // 0x00e00000 [23:21] L2_NBITS (0x0) Number of valid data bits for the lane 2 TMDS encoder,... + // 0x001f0000 [20:16] L2_ROT (0x00) Right-rotate applied to the current shifter data before... + // 0x0000e000 [15:13] L1_NBITS (0x0) Number of valid data bits for the lane 1 TMDS encoder,... + // 0x00001f00 [12:8] L1_ROT (0x00) Right-rotate applied to the current shifter data before... + // 0x000000e0 [7:5] L0_NBITS (0x0) Number of valid data bits for the lane 0 TMDS encoder,... + // 0x0000001f [4:0] L0_ROT (0x00) Right-rotate applied to the current shifter data before... + io_rw_32 expand_tmds; +} hstx_ctrl_hw_t; + +#define hstx_ctrl_hw ((hstx_ctrl_hw_t *)HSTX_CTRL_BASE) +static_assert(sizeof (hstx_ctrl_hw_t) == 0x002c, ""); + +#endif // _HARDWARE_STRUCTS_HSTX_CTRL_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/hstx_fifo.h b/lib/pico-sdk/rp2350/hardware/structs/hstx_fifo.h new file mode 100644 index 000000000000..a8399fad3650 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/hstx_fifo.h @@ -0,0 +1,45 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_HSTX_FIFO_H +#define _HARDWARE_STRUCTS_HSTX_FIFO_H + +/** + * \file rp2350/hstx_fifo.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/hstx_fifo.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_hstx_fifo +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/hstx_fifo.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(HSTX_FIFO_STAT_OFFSET) // HSTX_FIFO_STAT + // FIFO status + // 0x00000400 [10] WOF (0) FIFO was written when full + // 0x00000200 [9] EMPTY (-) + // 0x00000100 [8] FULL (-) + // 0x000000ff [7:0] LEVEL (0x00) + io_rw_32 stat; + + _REG_(HSTX_FIFO_FIFO_OFFSET) // HSTX_FIFO_FIFO + // Write access to FIFO + // 0xffffffff [31:0] FIFO (0x00000000) + io_wo_32 fifo; +} hstx_fifo_hw_t; + +#define hstx_fifo_hw ((hstx_fifo_hw_t *)HSTX_FIFO_BASE) +static_assert(sizeof (hstx_fifo_hw_t) == 0x0008, ""); + +#endif // _HARDWARE_STRUCTS_HSTX_FIFO_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/i2c.h b/lib/pico-sdk/rp2350/hardware/structs/i2c.h new file mode 100644 index 000000000000..7cd990dbfa18 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/i2c.h @@ -0,0 +1,338 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_I2C_H +#define _HARDWARE_STRUCTS_I2C_H + +/** + * \file rp2350/i2c.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/i2c.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_i2c +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON + // I2C Control Register + // 0x00000400 [10] STOP_DET_IF_MASTER_ACTIVE (0) Master issues the STOP_DET interrupt irrespective of... + // 0x00000200 [9] RX_FIFO_FULL_HLD_CTRL (0) This bit controls whether DW_apb_i2c should hold the bus... + // 0x00000100 [8] TX_EMPTY_CTRL (0) This bit controls the generation of the TX_EMPTY... + // 0x00000080 [7] STOP_DET_IFADDRESSED (0) In slave mode: - 1'b1: issues the STOP_DET interrupt... + // 0x00000040 [6] IC_SLAVE_DISABLE (1) This bit controls whether I2C has its slave disabled,... + // 0x00000020 [5] IC_RESTART_EN (1) Determines whether RESTART conditions may be sent when... + // 0x00000010 [4] IC_10BITADDR_MASTER (0) Controls whether the DW_apb_i2c starts its transfers in... + // 0x00000008 [3] IC_10BITADDR_SLAVE (0) When acting as a slave, this bit controls whether the... + // 0x00000006 [2:1] SPEED (0x2) These bits control at which speed the DW_apb_i2c... + // 0x00000001 [0] MASTER_MODE (1) This bit controls whether the DW_apb_i2c master is enabled + io_rw_32 con; + + _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR + // I2C Target Address Register + // 0x00000800 [11] SPECIAL (0) This bit indicates whether software performs a Device-ID... + // 0x00000400 [10] GC_OR_START (0) If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is... + // 0x000003ff [9:0] IC_TAR (0x055) This is the target address for any master transaction + io_rw_32 tar; + + _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR + // I2C Slave Address Register + // 0x000003ff [9:0] IC_SAR (0x055) The IC_SAR holds the slave address when the I2C is... + io_rw_32 sar; + + uint32_t _pad0; + + _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD + // I2C Rx/Tx Data Buffer and Command Register + // 0x00000800 [11] FIRST_DATA_BYTE (0) Indicates the first data byte received after the address... + // 0x00000400 [10] RESTART (0) This bit controls whether a RESTART is issued before the... + // 0x00000200 [9] STOP (0) This bit controls whether a STOP is issued after the... + // 0x00000100 [8] CMD (0) This bit controls whether a read or a write is performed + // 0x000000ff [7:0] DAT (0x00) This register contains the data to be transmitted or... + io_rw_32 data_cmd; + + _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT + // Standard Speed I2C Clock SCL High Count Register + // 0x0000ffff [15:0] IC_SS_SCL_HCNT (0x0028) This register must be set before any I2C bus transaction... + io_rw_32 ss_scl_hcnt; + + _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT + // Standard Speed I2C Clock SCL Low Count Register + // 0x0000ffff [15:0] IC_SS_SCL_LCNT (0x002f) This register must be set before any I2C bus transaction... + io_rw_32 ss_scl_lcnt; + + _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT + // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + // 0x0000ffff [15:0] IC_FS_SCL_HCNT (0x0006) This register must be set before any I2C bus transaction... + io_rw_32 fs_scl_hcnt; + + _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT + // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + // 0x0000ffff [15:0] IC_FS_SCL_LCNT (0x000d) This register must be set before any I2C bus transaction... + io_rw_32 fs_scl_lcnt; + + uint32_t _pad1[2]; + + _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT + // I2C Interrupt Status Register + // 0x00001000 [12] R_RESTART_DET (0) See IC_RAW_INTR_STAT for a detailed description of... + // 0x00000800 [11] R_GEN_CALL (0) See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit + // 0x00000400 [10] R_START_DET (0) See IC_RAW_INTR_STAT for a detailed description of... + // 0x00000200 [9] R_STOP_DET (0) See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit + // 0x00000100 [8] R_ACTIVITY (0) See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit + // 0x00000080 [7] R_RX_DONE (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit + // 0x00000040 [6] R_TX_ABRT (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit + // 0x00000020 [5] R_RD_REQ (0) See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit + // 0x00000010 [4] R_TX_EMPTY (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit + // 0x00000008 [3] R_TX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit + // 0x00000004 [2] R_RX_FULL (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit + // 0x00000002 [1] R_RX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit + // 0x00000001 [0] R_RX_UNDER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit + io_ro_32 intr_stat; + + _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK + // I2C Interrupt Mask Register + // 0x00001000 [12] M_RESTART_DET (0) This bit masks the R_RESTART_DET interrupt in... + // 0x00000800 [11] M_GEN_CALL (1) This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register + // 0x00000400 [10] M_START_DET (0) This bit masks the R_START_DET interrupt in IC_INTR_STAT register + // 0x00000200 [9] M_STOP_DET (0) This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register + // 0x00000100 [8] M_ACTIVITY (0) This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register + // 0x00000080 [7] M_RX_DONE (1) This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register + // 0x00000040 [6] M_TX_ABRT (1) This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register + // 0x00000020 [5] M_RD_REQ (1) This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register + // 0x00000010 [4] M_TX_EMPTY (1) This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register + // 0x00000008 [3] M_TX_OVER (1) This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register + // 0x00000004 [2] M_RX_FULL (1) This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register + // 0x00000002 [1] M_RX_OVER (1) This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register + // 0x00000001 [0] M_RX_UNDER (1) This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register + io_rw_32 intr_mask; + + _REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT + // I2C Raw Interrupt Status Register + // 0x00001000 [12] RESTART_DET (0) Indicates whether a RESTART condition has occurred on... + // 0x00000800 [11] GEN_CALL (0) Set only when a General Call address is received and it... + // 0x00000400 [10] START_DET (0) Indicates whether a START or RESTART condition has... + // 0x00000200 [9] STOP_DET (0) Indicates whether a STOP condition has occurred on the... + // 0x00000100 [8] ACTIVITY (0) This bit captures DW_apb_i2c activity and stays set... + // 0x00000080 [7] RX_DONE (0) When the DW_apb_i2c is acting as a slave-transmitter,... + // 0x00000040 [6] TX_ABRT (0) This bit indicates if DW_apb_i2c, as an I2C transmitter,... + // 0x00000020 [5] RD_REQ (0) This bit is set to 1 when DW_apb_i2c is acting as a... + // 0x00000010 [4] TX_EMPTY (0) The behavior of the TX_EMPTY interrupt status differs... + // 0x00000008 [3] TX_OVER (0) Set during transmit if the transmit buffer is filled to... + // 0x00000004 [2] RX_FULL (0) Set when the receive buffer reaches or goes above the... + // 0x00000002 [1] RX_OVER (0) Set if the receive buffer is completely filled to... + // 0x00000001 [0] RX_UNDER (0) Set if the processor attempts to read the receive buffer... + io_ro_32 raw_intr_stat; + + _REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL + // I2C Receive FIFO Threshold Register + // 0x000000ff [7:0] RX_TL (0x00) Receive FIFO Threshold Level + io_rw_32 rx_tl; + + _REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL + // I2C Transmit FIFO Threshold Register + // 0x000000ff [7:0] TX_TL (0x00) Transmit FIFO Threshold Level + io_rw_32 tx_tl; + + _REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR + // Clear Combined and Individual Interrupt Register + // 0x00000001 [0] CLR_INTR (0) Read this register to clear the combined interrupt, all... + io_ro_32 clr_intr; + + _REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER + // Clear RX_UNDER Interrupt Register + // 0x00000001 [0] CLR_RX_UNDER (0) Read this register to clear the RX_UNDER interrupt (bit... + io_ro_32 clr_rx_under; + + _REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER + // Clear RX_OVER Interrupt Register + // 0x00000001 [0] CLR_RX_OVER (0) Read this register to clear the RX_OVER interrupt (bit... + io_ro_32 clr_rx_over; + + _REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER + // Clear TX_OVER Interrupt Register + // 0x00000001 [0] CLR_TX_OVER (0) Read this register to clear the TX_OVER interrupt (bit... + io_ro_32 clr_tx_over; + + _REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ + // Clear RD_REQ Interrupt Register + // 0x00000001 [0] CLR_RD_REQ (0) Read this register to clear the RD_REQ interrupt (bit 5)... + io_ro_32 clr_rd_req; + + _REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT + // Clear TX_ABRT Interrupt Register + // 0x00000001 [0] CLR_TX_ABRT (0) Read this register to clear the TX_ABRT interrupt (bit... + io_ro_32 clr_tx_abrt; + + _REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE + // Clear RX_DONE Interrupt Register + // 0x00000001 [0] CLR_RX_DONE (0) Read this register to clear the RX_DONE interrupt (bit... + io_ro_32 clr_rx_done; + + _REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY + // Clear ACTIVITY Interrupt Register + // 0x00000001 [0] CLR_ACTIVITY (0) Reading this register clears the ACTIVITY interrupt if... + io_ro_32 clr_activity; + + _REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET + // Clear STOP_DET Interrupt Register + // 0x00000001 [0] CLR_STOP_DET (0) Read this register to clear the STOP_DET interrupt (bit... + io_ro_32 clr_stop_det; + + _REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET + // Clear START_DET Interrupt Register + // 0x00000001 [0] CLR_START_DET (0) Read this register to clear the START_DET interrupt (bit... + io_ro_32 clr_start_det; + + _REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL + // Clear GEN_CALL Interrupt Register + // 0x00000001 [0] CLR_GEN_CALL (0) Read this register to clear the GEN_CALL interrupt (bit... + io_ro_32 clr_gen_call; + + _REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE + // I2C ENABLE Register + // 0x00000004 [2] TX_CMD_BLOCK (0) In Master mode: - 1'b1: Blocks the transmission of data... + // 0x00000002 [1] ABORT (0) When set, the controller initiates the transfer abort + // 0x00000001 [0] ENABLE (0) Controls whether the DW_apb_i2c is enabled + io_rw_32 enable; + + _REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS + // I2C STATUS Register + // 0x00000040 [6] SLV_ACTIVITY (0) Slave FSM Activity Status + // 0x00000020 [5] MST_ACTIVITY (0) Master FSM Activity Status + // 0x00000010 [4] RFF (0) Receive FIFO Completely Full + // 0x00000008 [3] RFNE (0) Receive FIFO Not Empty + // 0x00000004 [2] TFE (1) Transmit FIFO Completely Empty + // 0x00000002 [1] TFNF (1) Transmit FIFO Not Full + // 0x00000001 [0] ACTIVITY (0) I2C Activity Status + io_ro_32 status; + + _REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR + // I2C Transmit FIFO Level Register + // 0x0000001f [4:0] TXFLR (0x00) Transmit FIFO Level + io_ro_32 txflr; + + _REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR + // I2C Receive FIFO Level Register + // 0x0000001f [4:0] RXFLR (0x00) Receive FIFO Level + io_ro_32 rxflr; + + _REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD + // I2C SDA Hold Time Length Register + // 0x00ff0000 [23:16] IC_SDA_RX_HOLD (0x00) Sets the required SDA hold time in units of ic_clk... + // 0x0000ffff [15:0] IC_SDA_TX_HOLD (0x0001) Sets the required SDA hold time in units of ic_clk... + io_rw_32 sda_hold; + + _REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE + // I2C Transmit Abort Source Register + // 0xff800000 [31:23] TX_FLUSH_CNT (0x000) This field indicates the number of Tx FIFO Data Commands... + // 0x00010000 [16] ABRT_USER_ABRT (0) This is a master-mode-only bit + // 0x00008000 [15] ABRT_SLVRD_INTX (0) 1: When the processor side responds to a slave mode... + // 0x00004000 [14] ABRT_SLV_ARBLOST (0) This field indicates that a Slave has lost the bus while... + // 0x00002000 [13] ABRT_SLVFLUSH_TXFIFO (0) This field specifies that the Slave has received a read... + // 0x00001000 [12] ARB_LOST (0) This field specifies that the Master has lost... + // 0x00000800 [11] ABRT_MASTER_DIS (0) This field indicates that the User tries to initiate a... + // 0x00000400 [10] ABRT_10B_RD_NORSTRT (0) This field indicates that the restart is disabled... + // 0x00000200 [9] ABRT_SBYTE_NORSTRT (0) To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT... + // 0x00000100 [8] ABRT_HS_NORSTRT (0) This field indicates that the restart is disabled... + // 0x00000080 [7] ABRT_SBYTE_ACKDET (0) This field indicates that the Master has sent a START... + // 0x00000040 [6] ABRT_HS_ACKDET (0) This field indicates that the Master is in High Speed... + // 0x00000020 [5] ABRT_GCALL_READ (0) This field indicates that DW_apb_i2c in the master mode... + // 0x00000010 [4] ABRT_GCALL_NOACK (0) This field indicates that DW_apb_i2c in master mode has... + // 0x00000008 [3] ABRT_TXDATA_NOACK (0) This field indicates the master-mode only bit + // 0x00000004 [2] ABRT_10ADDR2_NOACK (0) This field indicates that the Master is in 10-bit... + // 0x00000002 [1] ABRT_10ADDR1_NOACK (0) This field indicates that the Master is in 10-bit... + // 0x00000001 [0] ABRT_7B_ADDR_NOACK (0) This field indicates that the Master is in 7-bit... + io_ro_32 tx_abrt_source; + + _REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY + // Generate Slave Data NACK Register + // 0x00000001 [0] NACK (0) Generate NACK + io_rw_32 slv_data_nack_only; + + _REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR + // DMA Control Register + // 0x00000002 [1] TDMAE (0) Transmit DMA Enable + // 0x00000001 [0] RDMAE (0) Receive DMA Enable + io_rw_32 dma_cr; + + _REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR + // DMA Transmit Data Level Register + // 0x0000000f [3:0] DMATDL (0x0) Transmit Data Level + io_rw_32 dma_tdlr; + + _REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR + // DMA Transmit Data Level Register + // 0x0000000f [3:0] DMARDL (0x0) Receive Data Level + io_rw_32 dma_rdlr; + + _REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP + // I2C SDA Setup Register + // 0x000000ff [7:0] SDA_SETUP (0x64) SDA Setup + io_rw_32 sda_setup; + + _REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL + // I2C ACK General Call Register + // 0x00000001 [0] ACK_GEN_CALL (1) ACK General Call + io_rw_32 ack_general_call; + + _REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS + // I2C Enable Status Register + // 0x00000004 [2] SLV_RX_DATA_LOST (0) Slave Received Data Lost + // 0x00000002 [1] SLV_DISABLED_WHILE_BUSY (0) Slave Disabled While Busy (Transmit, Receive) + // 0x00000001 [0] IC_EN (0) ic_en Status + io_ro_32 enable_status; + + _REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN + // I2C SS, FS or FM+ spike suppression limit + // 0x000000ff [7:0] IC_FS_SPKLEN (0x07) This register must be set before any I2C bus transaction... + io_rw_32 fs_spklen; + + uint32_t _pad2; + + _REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET + // Clear RESTART_DET Interrupt Register + // 0x00000001 [0] CLR_RESTART_DET (0) Read this register to clear the RESTART_DET interrupt... + io_ro_32 clr_restart_det; + + uint32_t _pad3[18]; + + _REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1 + // Component Parameter Register 1 + // 0x00ff0000 [23:16] TX_BUFFER_DEPTH (0x00) TX Buffer Depth = 16 + // 0x0000ff00 [15:8] RX_BUFFER_DEPTH (0x00) RX Buffer Depth = 16 + // 0x00000080 [7] ADD_ENCODED_PARAMS (0) Encoded parameters not visible + // 0x00000040 [6] HAS_DMA (0) DMA handshaking signals are enabled + // 0x00000020 [5] INTR_IO (0) COMBINED Interrupt outputs + // 0x00000010 [4] HC_COUNT_VALUES (0) Programmable count values for each mode + // 0x0000000c [3:2] MAX_SPEED_MODE (0x0) MAX SPEED MODE = FAST MODE + // 0x00000003 [1:0] APB_DATA_WIDTH (0x0) APB data bus width is 32 bits + io_ro_32 comp_param_1; + + _REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION + // I2C Component Version Register + // 0xffffffff [31:0] IC_COMP_VERSION (0x3230312a) + io_ro_32 comp_version; + + _REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE + // I2C Component Type Register + // 0xffffffff [31:0] IC_COMP_TYPE (0x44570140) Designware Component Type number = 0x44_57_01_40 + io_ro_32 comp_type; +} i2c_hw_t; + +#define i2c0_hw ((i2c_hw_t *)I2C0_BASE) +#define i2c1_hw ((i2c_hw_t *)I2C1_BASE) +static_assert(sizeof (i2c_hw_t) == 0x0100, ""); + +#endif // _HARDWARE_STRUCTS_I2C_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/interp.h b/lib/pico-sdk/rp2350/hardware/structs/interp.h new file mode 100644 index 000000000000..eec0e3da6303 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/interp.h @@ -0,0 +1,87 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_INTERP_H +#define _HARDWARE_STRUCTS_INTERP_H + +/** + * \file rp2350/interp.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0 + // Read/write access to accumulator 0 + // 0xffffffff [31:0] INTERP0_ACCUM0 (0x00000000) + io_rw_32 accum[2]; + + // (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0 + // Read/write access to BASE0 register + // 0xffffffff [31:0] INTERP0_BASE0 (0x00000000) + io_rw_32 base[3]; + + // (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0 + // Read LANE0 result, and simultaneously write lane results to both accumulators (POP) + // 0xffffffff [31:0] INTERP0_POP_LANE0 (0x00000000) + io_ro_32 pop[3]; + + // (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0 + // Read LANE0 result, without altering any internal state (PEEK) + // 0xffffffff [31:0] INTERP0_PEEK_LANE0 (0x00000000) + io_ro_32 peek[3]; + + // (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes) + _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0 + // Control register for lane 0 + // 0x02000000 [25] OVERF (0) Set if either OVERF0 or OVERF1 is set + // 0x01000000 [24] OVERF1 (0) Indicates if any masked-off MSBs in ACCUM1 are set + // 0x00800000 [23] OVERF0 (0) Indicates if any masked-off MSBs in ACCUM0 are set + // 0x00200000 [21] BLEND (0) Only present on INTERP0 on each core + // 0x00180000 [20:19] FORCE_MSB (0x0) ORed into bits 29:28 of the lane result presented to the... + // 0x00040000 [18] ADD_RAW (0) If 1, mask + shift is bypassed for LANE0 result + // 0x00020000 [17] CROSS_RESULT (0) If 1, feed the opposite lane's result into this lane's... + // 0x00010000 [16] CROSS_INPUT (0) If 1, feed the opposite lane's accumulator into this... + // 0x00008000 [15] SIGNED (0) If SIGNED is set, the shifted and masked accumulator... + // 0x00007c00 [14:10] MASK_MSB (0x00) The most-significant bit allowed to pass by the mask... + // 0x000003e0 [9:5] MASK_LSB (0x00) The least-significant bit allowed to pass by the mask (inclusive) + // 0x0000001f [4:0] SHIFT (0x00) Right-rotate applied to accumulator before masking + io_rw_32 ctrl[2]; + + // (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes) + _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD + // Values written here are atomically added to ACCUM0 + // 0x00ffffff [23:0] INTERP0_ACCUM0_ADD (0x000000) + io_rw_32 add_raw[2]; + + _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0 + // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. + // 0xffffffff [31:0] INTERP0_BASE_1AND0 (0x00000000) + io_wo_32 base01; +} interp_hw_t; + +#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)) +#define interp_hw_array_ns ((interp_hw_t *)(SIO_NONSEC_BASE + SIO_INTERP0_ACCUM0_OFFSET)) +static_assert(sizeof (interp_hw_t) == 0x0040, ""); +#define interp0_hw (&interp_hw_array[0]) +#define interp1_hw (&interp_hw_array[1]) + +#endif // _HARDWARE_STRUCTS_INTERP_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/io_bank0.h b/lib/pico-sdk/rp2350/hardware/structs/io_bank0.h new file mode 100644 index 000000000000..c5020e23252c --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/io_bank0.h @@ -0,0 +1,452 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_IO_BANK0_H +#define _HARDWARE_STRUCTS_IO_BANK0_H + +/** + * \file rp2350/io_bank0.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/io_bank0.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_io_bank0 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** + * \brief GPIO pin function selectors on RP2350 (used as typedef \ref gpio_function_t) + * \ingroup hardware_gpio + */ +typedef enum gpio_function_rp2350 { + GPIO_FUNC_HSTX = 0, ///< Select HSTX as GPIO pin function + GPIO_FUNC_SPI = 1, ///< Select SPI as GPIO pin function + GPIO_FUNC_UART = 2, ///< Select UART as GPIO pin function + GPIO_FUNC_I2C = 3, ///< Select I2C as GPIO pin function + GPIO_FUNC_PWM = 4, ///< Select PWM as GPIO pin function + GPIO_FUNC_SIO = 5, ///< Select SIO as GPIO pin function + GPIO_FUNC_PIO0 = 6, ///< Select PIO0 as GPIO pin function + GPIO_FUNC_PIO1 = 7, ///< Select PIO1 as GPIO pin function + GPIO_FUNC_PIO2 = 8, ///< Select PIO2 as GPIO pin function + GPIO_FUNC_GPCK = 9, ///< Select GPCK as GPIO pin function + GPIO_FUNC_XIP_CS1 = 9, ///< Select XIP CS1 as GPIO pin function + GPIO_FUNC_CORESIGHT_TRACE = 9, ///< Select CORESIGHT TRACE as GPIO pin function + GPIO_FUNC_USB = 10, ///< Select USB as GPIO pin function + GPIO_FUNC_UART_AUX = 11, ///< Select UART_AUX as GPIO pin function + GPIO_FUNC_NULL = 0x1f, ///< Select NULL as GPIO pin function +} gpio_function_t; + +typedef struct { + _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + io_ro_32 status; + + _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x0000c000 [15:14] OEOVER (0x0) + // 0x00003000 [13:12] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 ctrl; +} io_bank0_status_ctrl_hw_t; + +typedef struct { + // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0 + // Interrupt Enable for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 inte[6]; + + // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0 + // Interrupt Force for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 intf[6]; + + // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes) + _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0 + // Interrupt status after masking & forcing for proc0 + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_ro_32 ints[6]; +} io_bank0_irq_ctrl_hw_t; + +/// \tag::io_bank0_hw[] +typedef struct { + io_bank0_status_ctrl_hw_t io[48]; + + uint32_t _pad0[32]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC0_SECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_PROC0_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC0_SECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_proc0_secure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_proc0_nonsecure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC1_SECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_PROC1_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC1_SECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_proc1_secure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_proc1_nonsecure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_dormant_wake_secure[2]; + + // (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0 applies similarly to other array indexes) + _REG_(IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0 + // 0x80000000 [31] GPIO31 (0) + // 0x40000000 [30] GPIO30 (0) + // 0x20000000 [29] GPIO29 (0) + // 0x10000000 [28] GPIO28 (0) + // 0x08000000 [27] GPIO27 (0) + // 0x04000000 [26] GPIO26 (0) + // 0x02000000 [25] GPIO25 (0) + // 0x01000000 [24] GPIO24 (0) + // 0x00800000 [23] GPIO23 (0) + // 0x00400000 [22] GPIO22 (0) + // 0x00200000 [21] GPIO21 (0) + // 0x00100000 [20] GPIO20 (0) + // 0x00080000 [19] GPIO19 (0) + // 0x00040000 [18] GPIO18 (0) + // 0x00020000 [17] GPIO17 (0) + // 0x00010000 [16] GPIO16 (0) + // 0x00008000 [15] GPIO15 (0) + // 0x00004000 [14] GPIO14 (0) + // 0x00002000 [13] GPIO13 (0) + // 0x00001000 [12] GPIO12 (0) + // 0x00000800 [11] GPIO11 (0) + // 0x00000400 [10] GPIO10 (0) + // 0x00000200 [9] GPIO9 (0) + // 0x00000100 [8] GPIO8 (0) + // 0x00000080 [7] GPIO7 (0) + // 0x00000040 [6] GPIO6 (0) + // 0x00000020 [5] GPIO5 (0) + // 0x00000010 [4] GPIO4 (0) + // 0x00000008 [3] GPIO3 (0) + // 0x00000004 [2] GPIO2 (0) + // 0x00000002 [1] GPIO1 (0) + // 0x00000001 [0] GPIO0 (0) + io_ro_32 irqsummary_dormant_wake_nonsecure[2]; + + // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes) + _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0 + // Raw Interrupts + // 0x80000000 [31] GPIO7_EDGE_HIGH (0) + // 0x40000000 [30] GPIO7_EDGE_LOW (0) + // 0x20000000 [29] GPIO7_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO7_LEVEL_LOW (0) + // 0x08000000 [27] GPIO6_EDGE_HIGH (0) + // 0x04000000 [26] GPIO6_EDGE_LOW (0) + // 0x02000000 [25] GPIO6_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO6_LEVEL_LOW (0) + // 0x00800000 [23] GPIO5_EDGE_HIGH (0) + // 0x00400000 [22] GPIO5_EDGE_LOW (0) + // 0x00200000 [21] GPIO5_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO5_LEVEL_LOW (0) + // 0x00080000 [19] GPIO4_EDGE_HIGH (0) + // 0x00040000 [18] GPIO4_EDGE_LOW (0) + // 0x00020000 [17] GPIO4_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO4_LEVEL_LOW (0) + // 0x00008000 [15] GPIO3_EDGE_HIGH (0) + // 0x00004000 [14] GPIO3_EDGE_LOW (0) + // 0x00002000 [13] GPIO3_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO3_LEVEL_LOW (0) + // 0x00000800 [11] GPIO2_EDGE_HIGH (0) + // 0x00000400 [10] GPIO2_EDGE_LOW (0) + // 0x00000200 [9] GPIO2_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO2_LEVEL_LOW (0) + // 0x00000080 [7] GPIO1_EDGE_HIGH (0) + // 0x00000040 [6] GPIO1_EDGE_LOW (0) + // 0x00000020 [5] GPIO1_LEVEL_HIGH (0) + // 0x00000010 [4] GPIO1_LEVEL_LOW (0) + // 0x00000008 [3] GPIO0_EDGE_HIGH (0) + // 0x00000004 [2] GPIO0_EDGE_LOW (0) + // 0x00000002 [1] GPIO0_LEVEL_HIGH (0) + // 0x00000001 [0] GPIO0_LEVEL_LOW (0) + io_rw_32 intr[6]; + + union { + struct { + io_bank0_irq_ctrl_hw_t proc0_irq_ctrl; + io_bank0_irq_ctrl_hw_t proc1_irq_ctrl; + io_bank0_irq_ctrl_hw_t dormant_wake_irq_ctrl; + }; + io_bank0_irq_ctrl_hw_t irq_ctrl[3]; + }; +} io_bank0_hw_t; +/// \end::io_bank0_hw[] + +#define io_bank0_hw ((io_bank0_hw_t *)IO_BANK0_BASE) +static_assert(sizeof (io_bank0_hw_t) == 0x0320, ""); + +#endif // _HARDWARE_STRUCTS_IO_BANK0_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/io_qspi.h b/lib/pico-sdk/rp2350/hardware/structs/io_qspi.h new file mode 100644 index 000000000000..cec2bba65664 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/io_qspi.h @@ -0,0 +1,316 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_IO_QSPI_H +#define _HARDWARE_STRUCTS_IO_QSPI_H + +/** + * \file rp2350/io_qspi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/io_qspi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_io_qspi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** + * \brief QSPI pin function selectors on RP2350 (used as typedef \ref gpio_function1_t) + */ +typedef enum gpio_function1_rp2350 { + GPIO_FUNC1_XIP = 0, ///< Select XIP as QSPI pin function + GPIO_FUNC1_UART = 2, ///< Select UART as QSPI pin function + GPIO_FUNC1_I2C = 3, ///< Select I2C as QSPI pin function + GPIO_FUNC1_SIO = 5, ///< Select SIO as QSPI pin function + GPIO_FUNC1_UART_AUX = 11, ///< Select UART_AUX as QSPI pin function + GPIO_FUNC1_NULL = 0x1f, ///< Select NULL as QSPI pin function +} gpio_function1_t; + +typedef struct { + _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + io_ro_32 status; + + _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x0000c000 [15:14] OEOVER (0x0) + // 0x00003000 [13:12] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 ctrl; +} io_qspi_status_ctrl_hw_t; + +typedef struct { + _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE + // Interrupt Enable for proc0 + // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) + // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) + // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) + // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) + // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) + // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) + // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) + // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) + // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) + io_rw_32 inte; + + _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF + // Interrupt Force for proc0 + // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) + // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) + // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) + // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) + // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) + // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) + // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) + // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) + // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) + io_rw_32 intf; + + _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS + // Interrupt status after masking & forcing for proc0 + // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) + // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) + // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) + // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) + // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) + // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) + // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) + // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) + // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) + io_ro_32 ints; +} io_qspi_irq_ctrl_hw_t; + +typedef struct { + _REG_(IO_QSPI_USBPHY_DP_STATUS_OFFSET) // IO_QSPI_USBPHY_DP_STATUS + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + io_ro_32 usbphy_dp_status; + + _REG_(IO_QSPI_USBPHY_DP_CTRL_OFFSET) // IO_QSPI_USBPHY_DP_CTRL + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x0000c000 [15:14] OEOVER (0x0) + // 0x00003000 [13:12] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 usbphy_dp_ctrl; + + _REG_(IO_QSPI_USBPHY_DM_STATUS_OFFSET) // IO_QSPI_USBPHY_DM_STATUS + // 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied + // 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied + // 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied + // 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied + io_ro_32 usbphy_dm_status; + + _REG_(IO_QSPI_USBPHY_DM_CTRL_OFFSET) // IO_QSPI_USBPHY_DM_CTRL + // 0x30000000 [29:28] IRQOVER (0x0) + // 0x00030000 [17:16] INOVER (0x0) + // 0x0000c000 [15:14] OEOVER (0x0) + // 0x00003000 [13:12] OUTOVER (0x0) + // 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table + + io_rw_32 usbphy_dm_ctrl; + + io_qspi_status_ctrl_hw_t io[6]; + + uint32_t _pad0[112]; + + _REG_(IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_SECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_proc0_secure; + + _REG_(IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_NONSECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_proc0_nonsecure; + + _REG_(IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_SECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_proc1_secure; + + _REG_(IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_NONSECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_proc1_nonsecure; + + _REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_dormant_wake_secure; + + _REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE + // 0x00000080 [7] GPIO_QSPI_SD3 (0) + // 0x00000040 [6] GPIO_QSPI_SD2 (0) + // 0x00000020 [5] GPIO_QSPI_SD1 (0) + // 0x00000010 [4] GPIO_QSPI_SD0 (0) + // 0x00000008 [3] GPIO_QSPI_SS (0) + // 0x00000004 [2] GPIO_QSPI_SCLK (0) + // 0x00000002 [1] USBPHY_DM (0) + // 0x00000001 [0] USBPHY_DP (0) + io_ro_32 irqsummary_dormant_wake_nonsecure; + + _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR + // Raw Interrupts + // 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0) + // 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0) + // 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0) + // 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0) + // 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0) + // 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0) + // 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0) + // 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0) + // 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0) + // 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0) + // 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0) + // 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0) + // 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0) + // 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0) + // 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0) + // 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0) + // 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0) + // 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0) + // 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0) + // 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0) + // 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0) + // 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0) + // 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0) + // 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0) + // 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0) + // 0x00000040 [6] USBPHY_DM_EDGE_LOW (0) + // 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0) + // 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0) + // 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0) + // 0x00000004 [2] USBPHY_DP_EDGE_LOW (0) + // 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0) + // 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0) + io_rw_32 intr; + + union { + struct { + io_qspi_irq_ctrl_hw_t proc0_irq_ctrl; + io_qspi_irq_ctrl_hw_t proc1_irq_ctrl; + io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl; + }; + io_qspi_irq_ctrl_hw_t irq_ctrl[3]; + }; +} io_qspi_hw_t; + +#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE) +static_assert(sizeof (io_qspi_hw_t) == 0x0240, ""); + +#endif // _HARDWARE_STRUCTS_IO_QSPI_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/iobank0.h b/lib/pico-sdk/rp2350/hardware/structs/iobank0.h new file mode 100644 index 000000000000..2dc31e38d432 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/iobank0.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/io_bank0.h" +#define iobank0_hw io_bank0_hw \ No newline at end of file diff --git a/lib/pico-sdk/rp2350/hardware/structs/ioqspi.h b/lib/pico-sdk/rp2350/hardware/structs/ioqspi.h new file mode 100644 index 000000000000..20cc74c79b48 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/ioqspi.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/io_qspi.h" +#define ioqspi_hw io_qspi_hw \ No newline at end of file diff --git a/lib/pico-sdk/rp2350/hardware/structs/m33.h b/lib/pico-sdk/rp2350/hardware/structs/m33.h new file mode 100644 index 000000000000..d527c917fa92 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/m33.h @@ -0,0 +1,1651 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_M33_H +#define _HARDWARE_STRUCTS_M33_H + +/** + * \file rp2350/m33.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + // (Description copied from array index 0 register M33_ITM_STIM0 applies similarly to other array indexes) + _REG_(M33_ITM_STIM0_OFFSET) // M33_ITM_STIM0 + // ITM Stimulus Port Register 0 + // 0xffffffff [31:0] STIMULUS (0x00000000) Data to write to the Stimulus Port FIFO, for forwarding... + io_rw_32 itm_stim[32]; + + uint32_t _pad0[864]; + + _REG_(M33_ITM_TER0_OFFSET) // M33_ITM_TER0 + // Provide an individual enable bit for each ITM_STIM register + // 0xffffffff [31:0] STIMENA (0x00000000) For STIMENA[m] in ITM_TER*n, controls whether... + io_rw_32 itm_ter0; + + uint32_t _pad1[15]; + + _REG_(M33_ITM_TPR_OFFSET) // M33_ITM_TPR + // Controls which stimulus ports can be accessed by unprivileged code + // 0x0000000f [3:0] PRIVMASK (0x0) Bit mask to enable tracing on ITM stimulus ports + io_rw_32 itm_tpr; + + uint32_t _pad2[15]; + + _REG_(M33_ITM_TCR_OFFSET) // M33_ITM_TCR + // Configures and controls transfers through the ITM interface + // 0x00800000 [23] BUSY (0) Indicates whether the ITM is currently processing events + // 0x007f0000 [22:16] TRACEBUSID (0x00) Identifier for multi-source trace stream formatting + // 0x00000c00 [11:10] GTSFREQ (0x0) Defines how often the ITM generates a global timestamp,... + // 0x00000300 [9:8] TSPRESCALE (0x0) Local timestamp prescaler, used with the trace packet... + // 0x00000020 [5] STALLENA (0) Stall the PE to guarantee delivery of Data Trace packets + // 0x00000010 [4] SWOENA (0) Enables asynchronous clocking of the timestamp counter + // 0x00000008 [3] TXENA (0) Enables forwarding of hardware event packet from the DWT... + // 0x00000004 [2] SYNCENA (0) Enables Synchronization packet transmission for a... + // 0x00000002 [1] TSENA (0) Enables Local timestamp generation + // 0x00000001 [0] ITMENA (0) Enables the ITM + io_rw_32 itm_tcr; + + uint32_t _pad3[27]; + + _REG_(M33_INT_ATREADY_OFFSET) // M33_INT_ATREADY + // Integration Mode: Read ATB Ready + // 0x00000002 [1] AFVALID (0) A read of this bit returns the value of AFVALID + // 0x00000001 [0] ATREADY (0) A read of this bit returns the value of ATREADY + io_ro_32 int_atready; + + uint32_t _pad4; + + _REG_(M33_INT_ATVALID_OFFSET) // M33_INT_ATVALID + // Integration Mode: Write ATB Valid + // 0x00000002 [1] AFREADY (0) A write to this bit gives the value of AFREADY + // 0x00000001 [0] ATREADY (0) A write to this bit gives the value of ATVALID + io_rw_32 int_atvalid; + + uint32_t _pad5; + + _REG_(M33_ITM_ITCTRL_OFFSET) // M33_ITM_ITCTRL + // Integration Mode Control Register + // 0x00000001 [0] IME (0) Integration mode enable bit - The possible values are: ... + io_rw_32 itm_itctrl; + + uint32_t _pad6[46]; + + _REG_(M33_ITM_DEVARCH_OFFSET) // M33_ITM_DEVARCH + // Provides CoreSight discovery information for the ITM + // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component + // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component + // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component + // 0x00000fff [11:0] ARCHPART (0xa01) Defines the architecture of the component + io_ro_32 itm_devarch; + + uint32_t _pad7[3]; + + _REG_(M33_ITM_DEVTYPE_OFFSET) // M33_ITM_DEVTYPE + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] SUB (0x4) Component sub-type + // 0x0000000f [3:0] MAJOR (0x3) Component major type + io_ro_32 itm_devtype; + + _REG_(M33_ITM_PIDR4_OFFSET) // M33_ITM_PIDR4 + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification + io_ro_32 itm_pidr4; + + _REG_(M33_ITM_PIDR5_OFFSET) // M33_ITM_PIDR5 + // Provides CoreSight discovery information for the ITM + // 0x00000000 [31:0] ITM_PIDR5 (0x00000000) + io_rw_32 itm_pidr5; + + _REG_(M33_ITM_PIDR6_OFFSET) // M33_ITM_PIDR6 + // Provides CoreSight discovery information for the ITM + // 0x00000000 [31:0] ITM_PIDR6 (0x00000000) + io_rw_32 itm_pidr6; + + _REG_(M33_ITM_PIDR7_OFFSET) // M33_ITM_PIDR7 + // Provides CoreSight discovery information for the ITM + // 0x00000000 [31:0] ITM_PIDR7 (0x00000000) + io_rw_32 itm_pidr7; + + _REG_(M33_ITM_PIDR0_OFFSET) // M33_ITM_PIDR0 + // Provides CoreSight discovery information for the ITM + // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification + io_ro_32 itm_pidr0; + + _REG_(M33_ITM_PIDR1_OFFSET) // M33_ITM_PIDR1 + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification + // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification + io_ro_32 itm_pidr1; + + _REG_(M33_ITM_PIDR2_OFFSET) // M33_ITM_PIDR2 + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification + // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification + // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification + io_ro_32 itm_pidr2; + + _REG_(M33_ITM_PIDR3_OFFSET) // M33_ITM_PIDR3 + // Provides CoreSight discovery information for the ITM + // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification + io_ro_32 itm_pidr3; + + // (Description copied from array index 0 register M33_ITM_CIDR0 applies similarly to other array indexes) + _REG_(M33_ITM_CIDR0_OFFSET) // M33_ITM_CIDR0 + // Provides CoreSight discovery information for the ITM + // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification + io_ro_32 itm_cidr[4]; + + _REG_(M33_DWT_CTRL_OFFSET) // M33_DWT_CTRL + // Provides configuration and status information for the DWT unit, and used to control features of the unit + // 0xf0000000 [31:28] NUMCOMP (0x7) Number of DWT comparators implemented + // 0x08000000 [27] NOTRCPKT (0) Indicates whether the implementation does not support trace + // 0x04000000 [26] NOEXTTRIG (0) Reserved, RAZ + // 0x02000000 [25] NOCYCCNT (1) Indicates whether the implementation does not include a... + // 0x01000000 [24] NOPRFCNT (1) Indicates whether the implementation does not include... + // 0x00800000 [23] CYCDISS (0) Controls whether the cycle counter is disabled in Secure state + // 0x00400000 [22] CYCEVTENA (1) Enables Event Counter packet generation on POSTCNT underflow + // 0x00200000 [21] FOLDEVTENA (1) Enables DWT_FOLDCNT counter + // 0x00100000 [20] LSUEVTENA (1) Enables DWT_LSUCNT counter + // 0x00080000 [19] SLEEPEVTENA (0) Enable DWT_SLEEPCNT counter + // 0x00040000 [18] EXCEVTENA (1) Enables DWT_EXCCNT counter + // 0x00020000 [17] CPIEVTENA (0) Enables DWT_CPICNT counter + // 0x00010000 [16] EXTTRCENA (0) Enables generation of Exception Trace packets + // 0x00001000 [12] PCSAMPLENA (1) Enables use of POSTCNT counter as a timer for Periodic... + // 0x00000c00 [11:10] SYNCTAP (0x2) Selects the position of the synchronization packet... + // 0x00000200 [9] CYCTAP (0) Selects the position of the POSTCNT tap on the CYCCNT counter + // 0x000001e0 [8:5] POSTINIT (0x1) Initial value for the POSTCNT counter + // 0x0000001e [4:1] POSTPRESET (0x2) Reload value for the POSTCNT counter + // 0x00000001 [0] CYCCNTENA (0) Enables CYCCNT + io_rw_32 dwt_ctrl; + + _REG_(M33_DWT_CYCCNT_OFFSET) // M33_DWT_CYCCNT + // Shows or sets the value of the processor cycle counter, CYCCNT + // 0xffffffff [31:0] CYCCNT (0x00000000) Increments one on each processor clock cycle when DWT_CTRL + io_rw_32 dwt_cyccnt; + + uint32_t _pad8; + + _REG_(M33_DWT_EXCCNT_OFFSET) // M33_DWT_EXCCNT + // Counts the total cycles spent in exception processing + // 0x000000ff [7:0] EXCCNT (0x00) Counts one on each cycle when all of the following are... + io_rw_32 dwt_exccnt; + + uint32_t _pad9; + + _REG_(M33_DWT_LSUCNT_OFFSET) // M33_DWT_LSUCNT + // Increments on the additional cycles required to execute all load or store instructions + // 0x000000ff [7:0] LSUCNT (0x00) Counts one on each cycle when all of the following are... + io_rw_32 dwt_lsucnt; + + _REG_(M33_DWT_FOLDCNT_OFFSET) // M33_DWT_FOLDCNT + // Increments on the additional cycles required to execute all load or store instructions + // 0x000000ff [7:0] FOLDCNT (0x00) Counts on each cycle when all of the following are true:... + io_rw_32 dwt_foldcnt; + + uint32_t _pad10; + + _REG_(M33_DWT_COMP0_OFFSET) // M33_DWT_COMP0 + // Provides a reference value for use by watchpoint comparator 0 + // 0xffffffff [31:0] DWT_COMP0 (0x00000000) + io_rw_32 dwt_comp0; + + uint32_t _pad11; + + _REG_(M33_DWT_FUNCTION0_OFFSET) // M33_DWT_FUNCTION0 + // Controls the operation of watchpoint comparator 0 + // 0xf8000000 [31:27] ID (0x0b) Identifies the capabilities for MATCH for comparator *n + // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches + // 0x00000c00 [11:10] DATAVSIZE (0x0) Defines the size of the object being watched for by Data... + // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match + // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator + io_rw_32 dwt_function0; + + uint32_t _pad12; + + _REG_(M33_DWT_COMP1_OFFSET) // M33_DWT_COMP1 + // Provides a reference value for use by watchpoint comparator 1 + // 0xffffffff [31:0] DWT_COMP1 (0x00000000) + io_rw_32 dwt_comp1; + + uint32_t _pad13; + + _REG_(M33_DWT_FUNCTION1_OFFSET) // M33_DWT_FUNCTION1 + // Controls the operation of watchpoint comparator 1 + // 0xf8000000 [31:27] ID (0x11) Identifies the capabilities for MATCH for comparator *n + // 0x01000000 [24] MATCHED (1) Set to 1 when the comparator matches + // 0x00000c00 [11:10] DATAVSIZE (0x2) Defines the size of the object being watched for by Data... + // 0x00000030 [5:4] ACTION (0x2) Defines the action on a match + // 0x0000000f [3:0] MATCH (0x8) Controls the type of match generated by this comparator + io_rw_32 dwt_function1; + + uint32_t _pad14; + + _REG_(M33_DWT_COMP2_OFFSET) // M33_DWT_COMP2 + // Provides a reference value for use by watchpoint comparator 2 + // 0xffffffff [31:0] DWT_COMP2 (0x00000000) + io_rw_32 dwt_comp2; + + uint32_t _pad15; + + _REG_(M33_DWT_FUNCTION2_OFFSET) // M33_DWT_FUNCTION2 + // Controls the operation of watchpoint comparator 2 + // 0xf8000000 [31:27] ID (0x0a) Identifies the capabilities for MATCH for comparator *n + // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches + // 0x00000c00 [11:10] DATAVSIZE (0x0) Defines the size of the object being watched for by Data... + // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match + // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator + io_rw_32 dwt_function2; + + uint32_t _pad16; + + _REG_(M33_DWT_COMP3_OFFSET) // M33_DWT_COMP3 + // Provides a reference value for use by watchpoint comparator 3 + // 0xffffffff [31:0] DWT_COMP3 (0x00000000) + io_rw_32 dwt_comp3; + + uint32_t _pad17; + + _REG_(M33_DWT_FUNCTION3_OFFSET) // M33_DWT_FUNCTION3 + // Controls the operation of watchpoint comparator 3 + // 0xf8000000 [31:27] ID (0x04) Identifies the capabilities for MATCH for comparator *n + // 0x01000000 [24] MATCHED (0) Set to 1 when the comparator matches + // 0x00000c00 [11:10] DATAVSIZE (0x2) Defines the size of the object being watched for by Data... + // 0x00000030 [5:4] ACTION (0x0) Defines the action on a match + // 0x0000000f [3:0] MATCH (0x0) Controls the type of match generated by this comparator + io_rw_32 dwt_function3; + + uint32_t _pad18[984]; + + _REG_(M33_DWT_DEVARCH_OFFSET) // M33_DWT_DEVARCH + // Provides CoreSight discovery information for the DWT + // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component + // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component + // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component + // 0x00000fff [11:0] ARCHPART (0xa02) Defines the architecture of the component + io_ro_32 dwt_devarch; + + uint32_t _pad19[3]; + + _REG_(M33_DWT_DEVTYPE_OFFSET) // M33_DWT_DEVTYPE + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] SUB (0x0) Component sub-type + // 0x0000000f [3:0] MAJOR (0x0) Component major type + io_ro_32 dwt_devtype; + + _REG_(M33_DWT_PIDR4_OFFSET) // M33_DWT_PIDR4 + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification + io_ro_32 dwt_pidr4; + + _REG_(M33_DWT_PIDR5_OFFSET) // M33_DWT_PIDR5 + // Provides CoreSight discovery information for the DWT + // 0x00000000 [31:0] DWT_PIDR5 (0x00000000) + io_rw_32 dwt_pidr5; + + _REG_(M33_DWT_PIDR6_OFFSET) // M33_DWT_PIDR6 + // Provides CoreSight discovery information for the DWT + // 0x00000000 [31:0] DWT_PIDR6 (0x00000000) + io_rw_32 dwt_pidr6; + + _REG_(M33_DWT_PIDR7_OFFSET) // M33_DWT_PIDR7 + // Provides CoreSight discovery information for the DWT + // 0x00000000 [31:0] DWT_PIDR7 (0x00000000) + io_rw_32 dwt_pidr7; + + _REG_(M33_DWT_PIDR0_OFFSET) // M33_DWT_PIDR0 + // Provides CoreSight discovery information for the DWT + // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification + io_ro_32 dwt_pidr0; + + _REG_(M33_DWT_PIDR1_OFFSET) // M33_DWT_PIDR1 + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification + // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification + io_ro_32 dwt_pidr1; + + _REG_(M33_DWT_PIDR2_OFFSET) // M33_DWT_PIDR2 + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification + // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification + // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification + io_ro_32 dwt_pidr2; + + _REG_(M33_DWT_PIDR3_OFFSET) // M33_DWT_PIDR3 + // Provides CoreSight discovery information for the DWT + // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification + io_ro_32 dwt_pidr3; + + // (Description copied from array index 0 register M33_DWT_CIDR0 applies similarly to other array indexes) + _REG_(M33_DWT_CIDR0_OFFSET) // M33_DWT_CIDR0 + // Provides CoreSight discovery information for the DWT + // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification + io_ro_32 dwt_cidr[4]; + + _REG_(M33_FP_CTRL_OFFSET) // M33_FP_CTRL + // Provides FPB implementation information, and the global enable for the FPB unit + // 0xf0000000 [31:28] REV (0x6) Flash Patch and Breakpoint Unit architecture revision + // 0x00007000 [14:12] NUM_CODE_14_12_ (0x5) Indicates the number of implemented instruction address... + // 0x00000f00 [11:8] NUM_LIT (0x5) Indicates the number of implemented literal address comparators + // 0x000000f0 [7:4] NUM_CODE_7_4_ (0x8) Indicates the number of implemented instruction address... + // 0x00000002 [1] KEY (0) Writes to the FP_CTRL are ignored unless KEY is... + // 0x00000001 [0] ENABLE (0) Enables the FPB + io_rw_32 fp_ctrl; + + _REG_(M33_FP_REMAP_OFFSET) // M33_FP_REMAP + // Indicates whether the implementation supports Flash Patch remap and, if it does, holds the... + // 0x20000000 [29] RMPSPT (0) Indicates whether the FPB unit supports the Flash Patch... + // 0x1fffffe0 [28:5] REMAP (0x000000) Holds the bits[28:5] of the Flash Patch remap address + io_ro_32 fp_remap; + + // (Description copied from array index 0 register M33_FP_COMP0 applies similarly to other array indexes) + _REG_(M33_FP_COMP0_OFFSET) // M33_FP_COMP0 + // Holds an address for comparison + // 0x00000001 [0] BE (0) Selects between flashpatch and breakpoint functionality + io_rw_32 fp_comp[8]; + + uint32_t _pad20[997]; + + _REG_(M33_FP_DEVARCH_OFFSET) // M33_FP_DEVARCH + // Provides CoreSight discovery information for the FPB + // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component + // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component + // 0x0000f000 [15:12] ARCHVER (0x1) Defines the architecture version of the component + // 0x00000fff [11:0] ARCHPART (0xa03) Defines the architecture of the component + io_ro_32 fp_devarch; + + uint32_t _pad21[3]; + + _REG_(M33_FP_DEVTYPE_OFFSET) // M33_FP_DEVTYPE + // Provides CoreSight discovery information for the FPB + // 0x000000f0 [7:4] SUB (0x0) Component sub-type + // 0x0000000f [3:0] MAJOR (0x0) Component major type + io_ro_32 fp_devtype; + + _REG_(M33_FP_PIDR4_OFFSET) // M33_FP_PIDR4 + // Provides CoreSight discovery information for the FP + // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification + io_ro_32 fp_pidr4; + + _REG_(M33_FP_PIDR5_OFFSET) // M33_FP_PIDR5 + // Provides CoreSight discovery information for the FP + // 0x00000000 [31:0] FP_PIDR5 (0x00000000) + io_rw_32 fp_pidr5; + + _REG_(M33_FP_PIDR6_OFFSET) // M33_FP_PIDR6 + // Provides CoreSight discovery information for the FP + // 0x00000000 [31:0] FP_PIDR6 (0x00000000) + io_rw_32 fp_pidr6; + + _REG_(M33_FP_PIDR7_OFFSET) // M33_FP_PIDR7 + // Provides CoreSight discovery information for the FP + // 0x00000000 [31:0] FP_PIDR7 (0x00000000) + io_rw_32 fp_pidr7; + + _REG_(M33_FP_PIDR0_OFFSET) // M33_FP_PIDR0 + // Provides CoreSight discovery information for the FP + // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification + io_ro_32 fp_pidr0; + + _REG_(M33_FP_PIDR1_OFFSET) // M33_FP_PIDR1 + // Provides CoreSight discovery information for the FP + // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification + // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification + io_ro_32 fp_pidr1; + + _REG_(M33_FP_PIDR2_OFFSET) // M33_FP_PIDR2 + // Provides CoreSight discovery information for the FP + // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification + // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification + // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification + io_ro_32 fp_pidr2; + + _REG_(M33_FP_PIDR3_OFFSET) // M33_FP_PIDR3 + // Provides CoreSight discovery information for the FP + // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification + io_ro_32 fp_pidr3; + + // (Description copied from array index 0 register M33_FP_CIDR0 applies similarly to other array indexes) + _REG_(M33_FP_CIDR0_OFFSET) // M33_FP_CIDR0 + // Provides CoreSight discovery information for the FP + // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification + io_ro_32 fp_cidr[4]; + + uint32_t _pad22[11265]; + + _REG_(M33_ICTR_OFFSET) // M33_ICTR + // Provides information about the interrupt controller + // 0x0000000f [3:0] INTLINESNUM (0x1) Indicates the number of the highest implemented register... + io_ro_32 ictr; + + _REG_(M33_ACTLR_OFFSET) // M33_ACTLR + // Provides IMPLEMENTATION DEFINED configuration and control options + // 0x20000000 [29] EXTEXCLALL (0) External Exclusives Allowed with no MPU + // 0x00001000 [12] DISITMATBFLUSH (0) Disable ATB Flush + // 0x00000400 [10] FPEXCODIS (0) Disable FPU exception outputs + // 0x00000200 [9] DISOOFP (0) Disable out-of-order FP instruction completion + // 0x00000004 [2] DISFOLD (0) Disable dual-issue + // 0x00000001 [0] DISMCYCINT (0) Disable dual-issue + io_rw_32 actlr; + + uint32_t _pad23; + + _REG_(M33_SYST_CSR_OFFSET) // M33_SYST_CSR + // SysTick Control and Status Register + // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read + // 0x00000004 [2] CLKSOURCE (0) SysTick clock source + // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + + // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + + io_rw_32 syst_csr; + + _REG_(M33_SYST_RVR_OFFSET) // M33_SYST_RVR + // SysTick Reload Value Register + // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... + io_rw_32 syst_rvr; + + _REG_(M33_SYST_CVR_OFFSET) // M33_SYST_CVR + // SysTick Current Value Register + // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter + io_rw_32 syst_cvr; + + _REG_(M33_SYST_CALIB_OFFSET) // M33_SYST_CALIB + // SysTick Calibration Value Register + // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... + // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... + // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... + io_ro_32 syst_calib; + + uint32_t _pad24[56]; + + // (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes) + _REG_(M33_NVIC_ISER0_OFFSET) // M33_NVIC_ISER0 + // Enables or reads the enabled state of each group of 32 interrupts + // 0xffffffff [31:0] SETENA (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether... + io_rw_32 nvic_iser[2]; + + uint32_t _pad25[30]; + + // (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes) + _REG_(M33_NVIC_ICER0_OFFSET) // M33_NVIC_ICER0 + // Clears or reads the enabled state of each group of 32 interrupts + // 0xffffffff [31:0] CLRENA (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether... + io_rw_32 nvic_icer[2]; + + uint32_t _pad26[30]; + + // (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_ISPR0_OFFSET) // M33_NVIC_ISPR0 + // Enables or reads the pending state of each group of 32 interrupts + // 0xffffffff [31:0] SETPEND (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether... + io_rw_32 nvic_ispr[2]; + + uint32_t _pad27[30]; + + // (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_ICPR0_OFFSET) // M33_NVIC_ICPR0 + // Clears or reads the pending state of each group of 32 interrupts + // 0xffffffff [31:0] CLRPEND (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether... + io_rw_32 nvic_icpr[2]; + + uint32_t _pad28[30]; + + // (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes) + _REG_(M33_NVIC_IABR0_OFFSET) // M33_NVIC_IABR0 + // For each group of 32 interrupts, shows the active state of each interrupt + // 0xffffffff [31:0] ACTIVE (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state... + io_rw_32 nvic_iabr[2]; + + uint32_t _pad29[30]; + + // (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes) + _REG_(M33_NVIC_ITNS0_OFFSET) // M33_NVIC_ITNS0 + // For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + // 0xffffffff [31:0] ITNS (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security... + io_rw_32 nvic_itns[2]; + + uint32_t _pad30[30]; + + // (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_IPR0_OFFSET) // M33_NVIC_IPR0 + // Sets or reads interrupt priorities + // 0xf0000000 [31:28] PRI_N3 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x00f00000 [23:20] PRI_N2 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x0000f000 [15:12] PRI_N1 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x000000f0 [7:4] PRI_N0 (0x0) For register NVIC_IPRn, the priority of interrupt number... + io_rw_32 nvic_ipr[16]; + + uint32_t _pad31[560]; + + _REG_(M33_CPUID_OFFSET) // M33_CPUID + // Provides identification information for the PE, including an implementer code for the device and... + // 0xff000000 [31:24] IMPLEMENTER (0x41) This field must hold an implementer code that has been... + // 0x00f00000 [23:20] VARIANT (0x1) IMPLEMENTATION DEFINED variant number + // 0x000f0000 [19:16] ARCHITECTURE (0xf) Defines the Architecture implemented by the PE + // 0x0000fff0 [15:4] PARTNO (0xd21) IMPLEMENTATION DEFINED primary part number for the device + // 0x0000000f [3:0] REVISION (0x0) IMPLEMENTATION DEFINED revision number for the device + io_ro_32 cpuid; + + _REG_(M33_ICSR_OFFSET) // M33_ICSR + // Controls and provides status information for NMI, PendSV, SysTick and interrupts + // 0x80000000 [31] PENDNMISET (0) Indicates whether the NMI exception is pending + // 0x40000000 [30] PENDNMICLR (0) Allows the NMI exception pend state to be cleared + // 0x10000000 [28] PENDSVSET (0) Indicates whether the PendSV `FTSSS exception is pending + // 0x08000000 [27] PENDSVCLR (0) Allows the PendSV exception pend state to be cleared `FTSSS + // 0x04000000 [26] PENDSTSET (0) Indicates whether the SysTick `FTSSS exception is pending + // 0x02000000 [25] PENDSTCLR (0) Allows the SysTick exception pend state to be cleared `FTSSS + // 0x01000000 [24] STTNS (0) Controls whether in a single SysTick implementation, the... + // 0x00800000 [23] ISRPREEMPT (0) Indicates whether a pending exception will be serviced... + // 0x00400000 [22] ISRPENDING (0) Indicates whether an external interrupt, generated by... + // 0x001ff000 [20:12] VECTPENDING (0x000) The exception number of the highest priority pending and... + // 0x00000800 [11] RETTOBASE (0) In Handler mode, indicates whether there is more than... + // 0x000001ff [8:0] VECTACTIVE (0x000) The exception number of the current executing exception + io_rw_32 icsr; + + _REG_(M33_VTOR_OFFSET) // M33_VTOR + // Vector Table Offset Register + // 0xffffff80 [31:7] TBLOFF (0x0000000) Vector table base offset field + io_rw_32 vtor; + + _REG_(M33_AIRCR_OFFSET) // M33_AIRCR + // Application Interrupt and Reset Control Register + // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + + // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + + // 0x00004000 [14] PRIS (0) Prioritize Secure exceptions + // 0x00002000 [13] BFHFNMINS (0) BusFault, HardFault, and NMI Non-secure enable + // 0x00000700 [10:8] PRIGROUP (0x0) Interrupt priority grouping field + // 0x00000008 [3] SYSRESETREQS (0) System reset request, Secure state only + // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... + // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... + io_rw_32 aircr; + + _REG_(M33_SCR_OFFSET) // M33_SCR + // System Control Register + // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + + // 0x00000008 [3] SLEEPDEEPS (0) 0 SLEEPDEEP is available to both security states + + // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... + // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... + io_rw_32 scr; + + _REG_(M33_CCR_OFFSET) // M33_CCR + // Sets or returns configuration and control data + // 0x00040000 [18] BP (0) Enables program flow prediction `FTSSS + // 0x00020000 [17] IC (0) This is a global enable bit for instruction caches in... + // 0x00010000 [16] DC (0) Enables data caching of all data accesses to Normal memory `FTSSS + // 0x00000400 [10] STKOFHFNMIGN (0) Controls the effect of a stack limit violation while... + // 0x00000200 [9] RES1 (1) Reserved, RES1 + // 0x00000100 [8] BFHFNMIGN (0) Determines the effect of precise BusFaults on handlers... + // 0x00000010 [4] DIV_0_TRP (0) Controls the generation of a DIVBYZERO UsageFault when... + // 0x00000008 [3] UNALIGN_TRP (0) Controls the trapping of unaligned word or halfword accesses + // 0x00000002 [1] USERSETMPEND (0) Determines whether unprivileged accesses are permitted... + // 0x00000001 [0] RES1_1 (1) Reserved, RES1 + io_rw_32 ccr; + + // (Description copied from array index 0 register M33_SHPR1 applies similarly to other array indexes) + _REG_(M33_SHPR1_OFFSET) // M33_SHPR1 + // Sets or returns priority for system handlers 4 - 7 + // 0xe0000000 [31:29] PRI_7_3 (0x0) Priority of system handler 7, SecureFault + // 0x00e00000 [23:21] PRI_6_3 (0x0) Priority of system handler 6, SecureFault + // 0x0000e000 [15:13] PRI_5_3 (0x0) Priority of system handler 5, SecureFault + // 0x000000e0 [7:5] PRI_4_3 (0x0) Priority of system handler 4, SecureFault + io_rw_32 shpr[3]; + + _REG_(M33_SHCSR_OFFSET) // M33_SHCSR + // Provides access to the active and pending status of system exceptions + // 0x00200000 [21] HARDFAULTPENDED (0) `IAAMO the pending state of the HardFault exception `CTTSSS + // 0x00100000 [20] SECUREFAULTPENDED (0) `IAAMO the pending state of the SecureFault exception + // 0x00080000 [19] SECUREFAULTENA (0) `DW the SecureFault exception is enabled + // 0x00040000 [18] USGFAULTENA (0) `DW the UsageFault exception is enabled `FTSSS + // 0x00020000 [17] BUSFAULTENA (0) `DW the BusFault exception is enabled + // 0x00010000 [16] MEMFAULTENA (0) `DW the MemManage exception is enabled `FTSSS + // 0x00008000 [15] SVCALLPENDED (0) `IAAMO the pending state of the SVCall exception `FTSSS + // 0x00004000 [14] BUSFAULTPENDED (0) `IAAMO the pending state of the BusFault exception + // 0x00002000 [13] MEMFAULTPENDED (0) `IAAMO the pending state of the MemManage exception `FTSSS + // 0x00001000 [12] USGFAULTPENDED (0) The UsageFault exception is banked between Security... + // 0x00000800 [11] SYSTICKACT (0) `IAAMO the active state of the SysTick exception `FTSSS + // 0x00000400 [10] PENDSVACT (0) `IAAMO the active state of the PendSV exception `FTSSS + // 0x00000100 [8] MONITORACT (0) `IAAMO the active state of the DebugMonitor exception + // 0x00000080 [7] SVCALLACT (0) `IAAMO the active state of the SVCall exception `FTSSS + // 0x00000020 [5] NMIACT (0) `IAAMO the active state of the NMI exception + // 0x00000010 [4] SECUREFAULTACT (0) `IAAMO the active state of the SecureFault exception + // 0x00000008 [3] USGFAULTACT (0) `IAAMO the active state of the UsageFault exception `FTSSS + // 0x00000004 [2] HARDFAULTACT (0) Indicates and allows limited modification of the active... + // 0x00000002 [1] BUSFAULTACT (0) `IAAMO the active state of the BusFault exception + // 0x00000001 [0] MEMFAULTACT (0) `IAAMO the active state of the MemManage exception `FTSSS + io_rw_32 shcsr; + + _REG_(M33_CFSR_OFFSET) // M33_CFSR + // Contains the three Configurable Fault Status Registers + // 0x02000000 [25] UFSR_DIVBYZERO (0) Sticky flag indicating whether an integer division by... + // 0x01000000 [24] UFSR_UNALIGNED (0) Sticky flag indicating whether an unaligned access error... + // 0x00100000 [20] UFSR_STKOF (0) Sticky flag indicating whether a stack overflow error... + // 0x00080000 [19] UFSR_NOCP (0) Sticky flag indicating whether a coprocessor disabled or... + // 0x00040000 [18] UFSR_INVPC (0) Sticky flag indicating whether an integrity check error... + // 0x00020000 [17] UFSR_INVSTATE (0) Sticky flag indicating whether an EPSR + // 0x00010000 [16] UFSR_UNDEFINSTR (0) Sticky flag indicating whether an undefined instruction... + // 0x00008000 [15] BFSR_BFARVALID (0) Indicates validity of the contents of the BFAR register + // 0x00002000 [13] BFSR_LSPERR (0) Records whether a BusFault occurred during FP lazy state... + // 0x00001000 [12] BFSR_STKERR (0) Records whether a derived BusFault occurred during... + // 0x00000800 [11] BFSR_UNSTKERR (0) Records whether a derived BusFault occurred during... + // 0x00000400 [10] BFSR_IMPRECISERR (0) Records whether an imprecise data access error has occurred + // 0x00000200 [9] BFSR_PRECISERR (0) Records whether a precise data access error has occurred + // 0x00000100 [8] BFSR_IBUSERR (0) Records whether a BusFault on an instruction prefetch... + // 0x000000ff [7:0] MMFSR (0x00) Provides information on MemManage exceptions + io_rw_32 cfsr; + + _REG_(M33_HFSR_OFFSET) // M33_HFSR + // Shows the cause of any HardFaults + // 0x80000000 [31] DEBUGEVT (0) Indicates when a Debug event has occurred + // 0x40000000 [30] FORCED (0) Indicates that a fault with configurable priority has... + // 0x00000002 [1] VECTTBL (0) Indicates when a fault has occurred because of a vector... + io_rw_32 hfsr; + + _REG_(M33_DFSR_OFFSET) // M33_DFSR + // Shows which debug event occurred + // 0x00000010 [4] EXTERNAL (0) Sticky flag indicating whether an External debug request... + // 0x00000008 [3] VCATCH (0) Sticky flag indicating whether a Vector catch debug... + // 0x00000004 [2] DWTTRAP (0) Sticky flag indicating whether a Watchpoint debug event... + // 0x00000002 [1] BKPT (0) Sticky flag indicating whether a Breakpoint debug event... + // 0x00000001 [0] HALTED (0) Sticky flag indicating that a Halt request debug event... + io_rw_32 dfsr; + + _REG_(M33_MMFAR_OFFSET) // M33_MMFAR + // Shows the address of the memory location that caused an MPU fault + // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... + io_rw_32 mmfar; + + _REG_(M33_BFAR_OFFSET) // M33_BFAR + // Shows the address associated with a precise data access BusFault + // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... + io_rw_32 bfar; + + uint32_t _pad32; + + // (Description copied from array index 0 register M33_ID_PFR0 applies similarly to other array indexes) + _REG_(M33_ID_PFR0_OFFSET) // M33_ID_PFR0 + // Gives top-level information about the instruction set supported by the PE + // 0x000000f0 [7:4] STATE1 (0x3) T32 instruction set support + // 0x0000000f [3:0] STATE0 (0x0) A32 instruction set support + io_ro_32 id_pfr[2]; + + _REG_(M33_ID_DFR0_OFFSET) // M33_ID_DFR0 + // Provides top level information about the debug system + // 0x00f00000 [23:20] MPROFDBG (0x2) Indicates the supported M-profile debug architecture + io_ro_32 id_dfr0; + + _REG_(M33_ID_AFR0_OFFSET) // M33_ID_AFR0 + // Provides information about the IMPLEMENTATION DEFINED features of the PE + // 0x0000f000 [15:12] IMPDEF3 (0x0) IMPLEMENTATION DEFINED meaning + // 0x00000f00 [11:8] IMPDEF2 (0x0) IMPLEMENTATION DEFINED meaning + // 0x000000f0 [7:4] IMPDEF1 (0x0) IMPLEMENTATION DEFINED meaning + // 0x0000000f [3:0] IMPDEF0 (0x0) IMPLEMENTATION DEFINED meaning + io_ro_32 id_afr0; + + // (Description copied from array index 0 register M33_ID_MMFR0 applies similarly to other array indexes) + _REG_(M33_ID_MMFR0_OFFSET) // M33_ID_MMFR0 + // Provides information about the implemented memory model and memory management support + // 0x00f00000 [23:20] AUXREG (0x1) Indicates support for Auxiliary Control Registers + // 0x000f0000 [19:16] TCM (0x0) Indicates support for tightly coupled memories (TCMs) + // 0x0000f000 [15:12] SHARELVL (0x1) Indicates the number of shareability levels implemented + // 0x00000f00 [11:8] OUTERSHR (0xf) Indicates the outermost shareability domain implemented + // 0x000000f0 [7:4] PMSA (0x4) Indicates support for the protected memory system... + io_ro_32 id_mmfr[4]; + + // (Description copied from array index 0 register M33_ID_ISAR0 applies similarly to other array indexes) + _REG_(M33_ID_ISAR0_OFFSET) // M33_ID_ISAR0 + // Provides information about the instruction set implemented by the PE + // 0x0f000000 [27:24] DIVIDE (0x8) Indicates the supported Divide instructions + // 0x00f00000 [23:20] DEBUG (0x0) Indicates the implemented Debug instructions + // 0x000f0000 [19:16] COPROC (0x9) Indicates the supported Coprocessor instructions + // 0x0000f000 [15:12] CMPBRANCH (0x2) Indicates the supported combined Compare and Branch instructions + // 0x00000f00 [11:8] BITFIELD (0x3) Indicates the supported bit field instructions + // 0x000000f0 [7:4] BITCOUNT (0x0) Indicates the supported bit count instructions + io_ro_32 id_isar[6]; + + uint32_t _pad33; + + _REG_(M33_CTR_OFFSET) // M33_CTR + // Provides information about the architecture of the caches + // 0x80000000 [31] RES1 (1) Reserved, RES1 + // 0x0f000000 [27:24] CWG (0x0) Log2 of the number of words of the maximum size of... + // 0x00f00000 [23:20] ERG (0x0) Log2 of the number of words of the maximum size of the... + // 0x000f0000 [19:16] DMINLINE (0x0) Log2 of the number of words in the smallest cache line... + // 0x0000c000 [15:14] RES1_1 (0x3) Reserved, RES1 + // 0x0000000f [3:0] IMINLINE (0x0) Log2 of the number of words in the smallest cache line... + io_ro_32 ctr; + + uint32_t _pad34[2]; + + _REG_(M33_CPACR_OFFSET) // M33_CPACR + // Specifies the access privileges for coprocessors and the FP Extension + // 0x00c00000 [23:22] CP11 (0x0) The value in this field is ignored + // 0x00300000 [21:20] CP10 (0x0) Defines the access rights for the floating-point functionality + // 0x0000c000 [15:14] CP7 (0x0) Controls access privileges for coprocessor 7 + // 0x00003000 [13:12] CP6 (0x0) Controls access privileges for coprocessor 6 + // 0x00000c00 [11:10] CP5 (0x0) Controls access privileges for coprocessor 5 + // 0x00000300 [9:8] CP4 (0x0) Controls access privileges for coprocessor 4 + // 0x000000c0 [7:6] CP3 (0x0) Controls access privileges for coprocessor 3 + // 0x00000030 [5:4] CP2 (0x0) Controls access privileges for coprocessor 2 + // 0x0000000c [3:2] CP1 (0x0) Controls access privileges for coprocessor 1 + // 0x00000003 [1:0] CP0 (0x0) Controls access privileges for coprocessor 0 + io_rw_32 cpacr; + + _REG_(M33_NSACR_OFFSET) // M33_NSACR + // Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 + // 0x00000800 [11] CP11 (0) Enables Non-secure access to the Floating-point Extension + // 0x00000400 [10] CP10 (0) Enables Non-secure access to the Floating-point Extension + // 0x00000080 [7] CP7 (0) Enables Non-secure access to coprocessor CP7 + // 0x00000040 [6] CP6 (0) Enables Non-secure access to coprocessor CP6 + // 0x00000020 [5] CP5 (0) Enables Non-secure access to coprocessor CP5 + // 0x00000010 [4] CP4 (0) Enables Non-secure access to coprocessor CP4 + // 0x00000008 [3] CP3 (0) Enables Non-secure access to coprocessor CP3 + // 0x00000004 [2] CP2 (0) Enables Non-secure access to coprocessor CP2 + // 0x00000002 [1] CP1 (0) Enables Non-secure access to coprocessor CP1 + // 0x00000001 [0] CP0 (0) Enables Non-secure access to coprocessor CP0 + io_rw_32 nsacr; + + _REG_(M33_MPU_TYPE_OFFSET) // M33_MPU_TYPE + // The MPU Type Register indicates how many regions the MPU `FTSSS supports + // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU + // 0x00000001 [0] SEPARATE (0) Indicates support for separate instructions and data... + io_ro_32 mpu_type; + + _REG_(M33_MPU_CTRL_OFFSET) // M33_MPU_CTRL + // Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled... + // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled for... + // 0x00000002 [1] HFNMIENA (0) Controls whether handlers executing with priority less... + // 0x00000001 [0] ENABLE (0) Enables the MPU + io_rw_32 mpu_ctrl; + + _REG_(M33_MPU_RNR_OFFSET) // M33_MPU_RNR + // Selects the region currently accessed by MPU_RBAR and MPU_RLAR + // 0x00000007 [2:0] REGION (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR + io_rw_32 mpu_rnr; + + _REG_(M33_MPU_RBAR_OFFSET) // M33_MPU_RBAR + // Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 mpu_rbar; + + _REG_(M33_MPU_RLAR_OFFSET) // M33_MPU_RLAR + // Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 mpu_rlar; + + _REG_(M33_MPU_RBAR_A1_OFFSET) // M33_MPU_RBAR_A1 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 mpu_rbar_a1; + + _REG_(M33_MPU_RLAR_A1_OFFSET) // M33_MPU_RLAR_A1 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 mpu_rlar_a1; + + _REG_(M33_MPU_RBAR_A2_OFFSET) // M33_MPU_RBAR_A2 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 mpu_rbar_a2; + + _REG_(M33_MPU_RLAR_A2_OFFSET) // M33_MPU_RLAR_A2 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 mpu_rlar_a2; + + _REG_(M33_MPU_RBAR_A3_OFFSET) // M33_MPU_RBAR_A3 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 mpu_rbar_a3; + + _REG_(M33_MPU_RLAR_A3_OFFSET) // M33_MPU_RLAR_A3 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 mpu_rlar_a3; + + uint32_t _pad35; + + // (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes) + _REG_(M33_MPU_MAIR0_OFFSET) // M33_MPU_MAIR0 + // Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values + // 0xff000000 [31:24] ATTR3 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3 + // 0x00ff0000 [23:16] ATTR2 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2 + // 0x0000ff00 [15:8] ATTR1 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1 + // 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0 + io_rw_32 mpu_mair[2]; + + uint32_t _pad36[2]; + + _REG_(M33_SAU_CTRL_OFFSET) // M33_SAU_CTRL + // Allows enabling of the Security Attribution Unit + // 0x00000002 [1] ALLNS (0) When SAU_CTRL + // 0x00000001 [0] ENABLE (0) Enables the SAU + io_rw_32 sau_ctrl; + + _REG_(M33_SAU_TYPE_OFFSET) // M33_SAU_TYPE + // Indicates the number of regions implemented by the Security Attribution Unit + // 0x000000ff [7:0] SREGION (0x08) The number of implemented SAU regions + io_ro_32 sau_type; + + _REG_(M33_SAU_RNR_OFFSET) // M33_SAU_RNR + // Selects the region currently accessed by SAU_RBAR and SAU_RLAR + // 0x000000ff [7:0] REGION (0x00) Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR + io_rw_32 sau_rnr; + + _REG_(M33_SAU_RBAR_OFFSET) // M33_SAU_RBAR + // Provides indirect read and write access to the base address of the currently selected SAU region + // 0xffffffe0 [31:5] BADDR (0x0000000) Holds bits [31:5] of the base address for the selected SAU region + io_rw_32 sau_rbar; + + _REG_(M33_SAU_RLAR_OFFSET) // M33_SAU_RLAR + // Provides indirect read and write access to the limit address of the currently selected SAU region + // 0xffffffe0 [31:5] LADDR (0x0000000) Holds bits [31:5] of the limit address for the selected... + // 0x00000002 [1] NSC (0) Controls whether Non-secure state is permitted to... + // 0x00000001 [0] ENABLE (0) SAU region enable + io_rw_32 sau_rlar; + + _REG_(M33_SFSR_OFFSET) // M33_SFSR + // Provides information about any security related faults + // 0x00000080 [7] LSERR (0) Sticky flag indicating that an error occurred during... + // 0x00000040 [6] SFARVALID (0) This bit is set when the SFAR register contains a valid value + // 0x00000020 [5] LSPERR (0) Stick flag indicating that an SAU or IDAU violation... + // 0x00000010 [4] INVTRAN (0) Sticky flag indicating that an exception was raised due... + // 0x00000008 [3] AUVIOL (0) Sticky flag indicating that an attempt was made to... + // 0x00000004 [2] INVER (0) This can be caused by EXC_RETURN + // 0x00000002 [1] INVIS (0) This bit is set if the integrity signature in an... + // 0x00000001 [0] INVEP (0) This bit is set if a function call from the Non-secure... + io_rw_32 sfsr; + + _REG_(M33_SFAR_OFFSET) // M33_SFAR + // Shows the address of the memory location that caused a Security violation + // 0xffffffff [31:0] ADDRESS (0x00000000) The address of an access that caused a attribution unit violation + io_rw_32 sfar; + + uint32_t _pad37; + + _REG_(M33_DHCSR_OFFSET) // M33_DHCSR + // Controls halting debug + // 0x04000000 [26] S_RESTART_ST (0) Indicates the PE has processed a request to clear DHCSR + // 0x02000000 [25] S_RESET_ST (0) Indicates whether the PE has been reset since the last... + // 0x01000000 [24] S_RETIRE_ST (0) Set to 1 every time the PE retires one of more instructions + // 0x00100000 [20] S_SDE (0) Indicates whether Secure invasive debug is allowed + // 0x00080000 [19] S_LOCKUP (0) Indicates whether the PE is in Lockup state + // 0x00040000 [18] S_SLEEP (0) Indicates whether the PE is sleeping + // 0x00020000 [17] S_HALT (0) Indicates whether the PE is in Debug state + // 0x00010000 [16] S_REGRDY (0) Handshake flag to transfers through the DCRDR + // 0x00000020 [5] C_SNAPSTALL (0) Allow imprecise entry to Debug state + // 0x00000008 [3] C_MASKINTS (0) When debug is enabled, the debugger can write to this... + // 0x00000004 [2] C_STEP (0) Enable single instruction step + // 0x00000002 [1] C_HALT (0) PE enter Debug state halt request + // 0x00000001 [0] C_DEBUGEN (0) Enable Halting debug + io_rw_32 dhcsr; + + _REG_(M33_DCRSR_OFFSET) // M33_DCRSR + // With the DCRDR, provides debug access to the general-purpose registers, special-purpose... + // 0x00010000 [16] REGWNR (0) Specifies the access type for the transfer + // 0x0000007f [6:0] REGSEL (0x00) Specifies the general-purpose register, special-purpose... + io_rw_32 dcrsr; + + _REG_(M33_DCRDR_OFFSET) // M33_DCRDR + // With the DCRSR, provides debug access to the general-purpose registers, special-purpose... + // 0xffffffff [31:0] DBGTMP (0x00000000) Provides debug access for reading and writing the... + io_rw_32 dcrdr; + + _REG_(M33_DEMCR_OFFSET) // M33_DEMCR + // Manages vector catch behavior and DebugMonitor handling when debugging + // 0x01000000 [24] TRCENA (0) Global enable for all DWT and ITM features + // 0x00100000 [20] SDME (0) Indicates whether the DebugMonitor targets the Secure or... + // 0x00080000 [19] MON_REQ (0) DebugMonitor semaphore bit + // 0x00040000 [18] MON_STEP (0) Enable DebugMonitor stepping + // 0x00020000 [17] MON_PEND (0) Sets or clears the pending state of the DebugMonitor exception + // 0x00010000 [16] MON_EN (0) Enable the DebugMonitor exception + // 0x00000800 [11] VC_SFERR (0) SecureFault exception halting debug vector catch enable + // 0x00000400 [10] VC_HARDERR (0) HardFault exception halting debug vector catch enable + // 0x00000200 [9] VC_INTERR (0) Enable halting debug vector catch for faults during... + // 0x00000100 [8] VC_BUSERR (0) BusFault exception halting debug vector catch enable + // 0x00000080 [7] VC_STATERR (0) Enable halting debug trap on a UsageFault exception... + // 0x00000040 [6] VC_CHKERR (0) Enable halting debug trap on a UsageFault exception... + // 0x00000020 [5] VC_NOCPERR (0) Enable halting debug trap on a UsageFault caused by an... + // 0x00000010 [4] VC_MMERR (0) Enable halting debug trap on a MemManage exception + // 0x00000001 [0] VC_CORERESET (0) Enable Reset Vector Catch + io_rw_32 demcr; + + uint32_t _pad38[2]; + + _REG_(M33_DSCSR_OFFSET) // M33_DSCSR + // Provides control and status information for Secure debug + // 0x00020000 [17] CDSKEY (0) Writes to the CDS bit are ignored unless CDSKEY is... + // 0x00010000 [16] CDS (0) This field indicates the current Security state of the processor + // 0x00000002 [1] SBRSEL (0) If SBRSELEN is 1 this bit selects whether the Non-secure... + // 0x00000001 [0] SBRSELEN (0) Controls whether the SBRSEL field or the current... + io_rw_32 dscsr; + + uint32_t _pad39[61]; + + _REG_(M33_STIR_OFFSET) // M33_STIR + // Provides a mechanism for software to generate an interrupt + // 0x000001ff [8:0] INTID (0x000) Indicates the interrupt to be pended + io_rw_32 stir; + + uint32_t _pad40[12]; + + _REG_(M33_FPCCR_OFFSET) // M33_FPCCR + // Holds control data for the Floating-point extension + // 0x80000000 [31] ASPEN (0) When this bit is set to 1, execution of a floating-point... + // 0x40000000 [30] LSPEN (0) Enables lazy context save of floating-point state + // 0x20000000 [29] LSPENS (1) This bit controls whether the LSPEN bit is writeable... + // 0x10000000 [28] CLRONRET (0) Clear floating-point caller saved registers on exception return + // 0x08000000 [27] CLRONRETS (0) This bit controls whether the CLRONRET bit is writeable... + // 0x04000000 [26] TS (0) Treat floating-point registers as Secure enable + // 0x00000400 [10] UFRDY (1) Indicates whether the software executing when the PE... + // 0x00000200 [9] SPLIMVIOL (0) This bit is banked between the Security states and... + // 0x00000100 [8] MONRDY (0) Indicates whether the software executing when the PE... + // 0x00000080 [7] SFRDY (0) Indicates whether the software executing when the PE... + // 0x00000040 [6] BFRDY (1) Indicates whether the software executing when the PE... + // 0x00000020 [5] MMRDY (1) Indicates whether the software executing when the PE... + // 0x00000010 [4] HFRDY (1) Indicates whether the software executing when the PE... + // 0x00000008 [3] THREAD (0) Indicates the PE mode when it allocated the... + // 0x00000004 [2] S (0) Security status of the floating-point context + // 0x00000002 [1] USER (1) Indicates the privilege level of the software executing... + // 0x00000001 [0] LSPACT (0) Indicates whether lazy preservation of the... + io_rw_32 fpccr; + + _REG_(M33_FPCAR_OFFSET) // M33_FPCAR + // Holds the location of the unpopulated floating-point register space allocated on an exception stack frame + // 0xfffffff8 [31:3] ADDRESS (0x00000000) The location of the unpopulated floating-point register... + io_rw_32 fpcar; + + _REG_(M33_FPDSCR_OFFSET) // M33_FPDSCR + // Holds the default values for the floating-point status control data that the PE assigns to the... + // 0x04000000 [26] AHP (0) Default value for FPSCR + // 0x02000000 [25] DN (0) Default value for FPSCR + // 0x01000000 [24] FZ (0) Default value for FPSCR + // 0x00c00000 [23:22] RMODE (0x0) Default value for FPSCR + io_rw_32 fpdscr; + + // (Description copied from array index 0 register M33_MVFR0 applies similarly to other array indexes) + _REG_(M33_MVFR0_OFFSET) // M33_MVFR0 + // Describes the features provided by the Floating-point Extension + // 0xf0000000 [31:28] FPROUND (0x6) Indicates the rounding modes supported by the FP Extension + // 0x00f00000 [23:20] FPSQRT (0x5) Indicates the support for FP square root operations + // 0x000f0000 [19:16] FPDIVIDE (0x4) Indicates the support for FP divide operations + // 0x00000f00 [11:8] FPDP (0x6) Indicates support for FP double-precision operations + // 0x000000f0 [7:4] FPSP (0x0) Indicates support for FP single-precision operations + // 0x0000000f [3:0] SIMDREG (0x1) Indicates size of FP register file + io_ro_32 mvfr[3]; + + uint32_t _pad41[28]; + + _REG_(M33_DDEVARCH_OFFSET) // M33_DDEVARCH + // Provides CoreSight discovery information for the SCS + // 0xffe00000 [31:21] ARCHITECT (0x23b) Defines the architect of the component + // 0x00100000 [20] PRESENT (1) Defines that the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Defines the architecture revision of the component + // 0x0000f000 [15:12] ARCHVER (0x2) Defines the architecture version of the component + // 0x00000fff [11:0] ARCHPART (0xa04) Defines the architecture of the component + io_ro_32 ddevarch; + + uint32_t _pad42[3]; + + _REG_(M33_DDEVTYPE_OFFSET) // M33_DDEVTYPE + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] SUB (0x0) Component sub-type + // 0x0000000f [3:0] MAJOR (0x0) CoreSight major type + io_ro_32 ddevtype; + + _REG_(M33_DPIDR4_OFFSET) // M33_DPIDR4 + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] SIZE (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] DES_2 (0x4) See CoreSight Architecture Specification + io_ro_32 dpidr4; + + _REG_(M33_DPIDR5_OFFSET) // M33_DPIDR5 + // Provides CoreSight discovery information for the SCS + // 0x00000000 [31:0] DPIDR5 (0x00000000) + io_rw_32 dpidr5; + + _REG_(M33_DPIDR6_OFFSET) // M33_DPIDR6 + // Provides CoreSight discovery information for the SCS + // 0x00000000 [31:0] DPIDR6 (0x00000000) + io_rw_32 dpidr6; + + _REG_(M33_DPIDR7_OFFSET) // M33_DPIDR7 + // Provides CoreSight discovery information for the SCS + // 0x00000000 [31:0] DPIDR7 (0x00000000) + io_rw_32 dpidr7; + + _REG_(M33_DPIDR0_OFFSET) // M33_DPIDR0 + // Provides CoreSight discovery information for the SCS + // 0x000000ff [7:0] PART_0 (0x21) See CoreSight Architecture Specification + io_ro_32 dpidr0; + + _REG_(M33_DPIDR1_OFFSET) // M33_DPIDR1 + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] DES_0 (0xb) See CoreSight Architecture Specification + // 0x0000000f [3:0] PART_1 (0xd) See CoreSight Architecture Specification + io_ro_32 dpidr1; + + _REG_(M33_DPIDR2_OFFSET) // M33_DPIDR2 + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] REVISION (0x0) See CoreSight Architecture Specification + // 0x00000008 [3] JEDEC (1) See CoreSight Architecture Specification + // 0x00000007 [2:0] DES_1 (0x3) See CoreSight Architecture Specification + io_ro_32 dpidr2; + + _REG_(M33_DPIDR3_OFFSET) // M33_DPIDR3 + // Provides CoreSight discovery information for the SCS + // 0x000000f0 [7:4] REVAND (0x0) See CoreSight Architecture Specification + // 0x0000000f [3:0] CMOD (0x0) See CoreSight Architecture Specification + io_ro_32 dpidr3; + + // (Description copied from array index 0 register M33_DCIDR0 applies similarly to other array indexes) + _REG_(M33_DCIDR0_OFFSET) // M33_DCIDR0 + // Provides CoreSight discovery information for the SCS + // 0x000000ff [7:0] PRMBL_0 (0x0d) See CoreSight Architecture Specification + io_ro_32 dcidr[4]; + + uint32_t _pad43[51201]; + + _REG_(M33_TRCPRGCTLR_OFFSET) // M33_TRCPRGCTLR + // Programming Control Register + // 0x00000001 [0] EN (0) Trace Unit Enable + io_rw_32 trcprgctlr; + + uint32_t _pad44; + + _REG_(M33_TRCSTATR_OFFSET) // M33_TRCSTATR + // The TRCSTATR indicates the ETM-Teal status + // 0x00000002 [1] PMSTABLE (0) Indicates whether the ETM-Teal registers are stable and... + // 0x00000001 [0] IDLE (0) Indicates that the trace unit is inactive + io_ro_32 trcstatr; + + _REG_(M33_TRCCONFIGR_OFFSET) // M33_TRCCONFIGR + // The TRCCONFIGR sets the basic tracing options for the trace unit + // 0x00001000 [12] RS (0) Return stack enable + // 0x00000800 [11] TS (0) Global timestamp tracing + // 0x000007e0 [10:5] COND (0x00) Conditional instruction tracing + // 0x00000010 [4] CCI (0) Cycle counting in instruction trace + // 0x00000008 [3] BB (0) Branch broadcast mode + io_rw_32 trcconfigr; + + uint32_t _pad45[3]; + + _REG_(M33_TRCEVENTCTL0R_OFFSET) // M33_TRCEVENTCTL0R + // The TRCEVENTCTL0R controls the tracing of events in the trace stream + // 0x00008000 [15] TYPE1 (0) Selects the resource type for event 1 + // 0x00000700 [10:8] SEL1 (0x0) Selects the resource number, based on the value of... + // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 + // 0x00000007 [2:0] SEL0 (0x0) Selects the resource number, based on the value of... + io_rw_32 trceventctl0r; + + _REG_(M33_TRCEVENTCTL1R_OFFSET) // M33_TRCEVENTCTL1R + // The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave + // 0x00001000 [12] LPOVERRIDE (0) Low power state behavior override + // 0x00000800 [11] ATB (0) ATB enabled + // 0x00000002 [1] INSTEN1 (0) One bit per event, to enable generation of an event... + // 0x00000001 [0] INSTEN0 (0) One bit per event, to enable generation of an event... + io_rw_32 trceventctl1r; + + uint32_t _pad46; + + _REG_(M33_TRCSTALLCTLR_OFFSET) // M33_TRCSTALLCTLR + // The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the... + // 0x00000400 [10] INSTPRIORITY (0) Reserved, RES0 + // 0x00000100 [8] ISTALL (0) Stall processor based on instruction trace buffer space + // 0x0000000c [3:2] LEVEL (0x0) Threshold at which stalling becomes active + io_rw_32 trcstallctlr; + + _REG_(M33_TRCTSCTLR_OFFSET) // M33_TRCTSCTLR + // The TRCTSCTLR controls the insertion of global timestamps into the trace stream + // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 + // 0x00000003 [1:0] SEL0 (0x0) Selects the resource number, based on the value of... + io_rw_32 trctsctlr; + + _REG_(M33_TRCSYNCPR_OFFSET) // M33_TRCSYNCPR + // The TRCSYNCPR specifies the period of trace synchronization of the trace streams + // 0x0000001f [4:0] PERIOD (0x0a) Defines the number of bytes of trace between trace... + io_ro_32 trcsyncpr; + + _REG_(M33_TRCCCCTLR_OFFSET) // M33_TRCCCCTLR + // The TRCCCCTLR sets the threshold value for instruction trace cycle counting + // 0x00000fff [11:0] THRESHOLD (0x000) Instruction trace cycle count threshold + io_rw_32 trcccctlr; + + uint32_t _pad47[17]; + + _REG_(M33_TRCVICTLR_OFFSET) // M33_TRCVICTLR + // The TRCVICTLR controls instruction trace filtering + // 0x00080000 [19] EXLEVEL_S3 (0) In Secure state, each bit controls whether instruction... + // 0x00010000 [16] EXLEVEL_S0 (0) In Secure state, each bit controls whether instruction... + // 0x00000800 [11] TRCERR (0) Selects whether a system error exception must always be traced + // 0x00000400 [10] TRCRESET (0) Selects whether a reset exception must always be traced + // 0x00000200 [9] SSSTATUS (0) Indicates the current status of the start/stop logic + // 0x00000080 [7] TYPE0 (0) Selects the resource type for event 0 + // 0x00000003 [1:0] SEL0 (0x0) Selects the resource number, based on the value of... + io_rw_32 trcvictlr; + + uint32_t _pad48[47]; + + _REG_(M33_TRCCNTRLDVR0_OFFSET) // M33_TRCCNTRLDVR0 + // The TRCCNTRLDVR defines the reload value for the reduced function counter + // 0x0000ffff [15:0] VALUE (0x0000) Defines the reload value for the counter + io_rw_32 trccntrldvr0; + + uint32_t _pad49[15]; + + _REG_(M33_TRCIDR8_OFFSET) // M33_TRCIDR8 + // TRCIDR8 + // 0xffffffff [31:0] MAXSPEC (0x00000000) reads as `ImpDef + io_ro_32 trcidr8; + + _REG_(M33_TRCIDR9_OFFSET) // M33_TRCIDR9 + // TRCIDR9 + // 0xffffffff [31:0] NUMP0KEY (0x00000000) reads as `ImpDef + io_ro_32 trcidr9; + + _REG_(M33_TRCIDR10_OFFSET) // M33_TRCIDR10 + // TRCIDR10 + // 0xffffffff [31:0] NUMP1KEY (0x00000000) reads as `ImpDef + io_ro_32 trcidr10; + + _REG_(M33_TRCIDR11_OFFSET) // M33_TRCIDR11 + // TRCIDR11 + // 0xffffffff [31:0] NUMP1SPC (0x00000000) reads as `ImpDef + io_ro_32 trcidr11; + + _REG_(M33_TRCIDR12_OFFSET) // M33_TRCIDR12 + // TRCIDR12 + // 0xffffffff [31:0] NUMCONDKEY (0x00000001) reads as `ImpDef + io_ro_32 trcidr12; + + _REG_(M33_TRCIDR13_OFFSET) // M33_TRCIDR13 + // TRCIDR13 + // 0xffffffff [31:0] NUMCONDSPC (0x00000000) reads as `ImpDef + io_ro_32 trcidr13; + + uint32_t _pad50[10]; + + _REG_(M33_TRCIMSPEC_OFFSET) // M33_TRCIMSPEC + // The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any... + // 0x0000000f [3:0] SUPPORT (0x0) Reserved, RES0 + io_ro_32 trcimspec; + + uint32_t _pad51[7]; + + _REG_(M33_TRCIDR0_OFFSET) // M33_TRCIDR0 + // TRCIDR0 + // 0x20000000 [29] COMMOPT (1) reads as `ImpDef + // 0x1f000000 [28:24] TSSIZE (0x08) reads as `ImpDef + // 0x00020000 [17] TRCEXDATA (0) reads as `ImpDef + // 0x00018000 [16:15] QSUPP (0x0) reads as `ImpDef + // 0x00004000 [14] QFILT (0) reads as `ImpDef + // 0x00003000 [13:12] CONDTYPE (0x0) reads as `ImpDef + // 0x00000c00 [11:10] NUMEVENT (0x1) reads as `ImpDef + // 0x00000200 [9] RETSTACK (1) reads as `ImpDef + // 0x00000080 [7] TRCCCI (1) reads as `ImpDef + // 0x00000040 [6] TRCCOND (1) reads as `ImpDef + // 0x00000020 [5] TRCBB (1) reads as `ImpDef + // 0x00000018 [4:3] TRCDATA (0x0) reads as `ImpDef + // 0x00000006 [2:1] INSTP0 (0x0) reads as `ImpDef + // 0x00000001 [0] RES1 (1) Reserved, RES1 + io_ro_32 trcidr0; + + _REG_(M33_TRCIDR1_OFFSET) // M33_TRCIDR1 + // TRCIDR1 + // 0xff000000 [31:24] DESIGNER (0x41) reads as `ImpDef + // 0x0000f000 [15:12] RES1 (0xf) Reserved, RES1 + // 0x00000f00 [11:8] TRCARCHMAJ (0x4) reads as 0b0100 + // 0x000000f0 [7:4] TRCARCHMIN (0x2) reads as 0b0000 + // 0x0000000f [3:0] REVISION (0x1) reads as `ImpDef + io_ro_32 trcidr1; + + _REG_(M33_TRCIDR2_OFFSET) // M33_TRCIDR2 + // TRCIDR2 + // 0x1e000000 [28:25] CCSIZE (0x0) reads as `ImpDef + // 0x01f00000 [24:20] DVSIZE (0x00) reads as `ImpDef + // 0x000f8000 [19:15] DASIZE (0x00) reads as `ImpDef + // 0x00007c00 [14:10] VMIDSIZE (0x00) reads as `ImpDef + // 0x000003e0 [9:5] CIDSIZE (0x00) reads as `ImpDef + // 0x0000001f [4:0] IASIZE (0x04) reads as `ImpDef + io_ro_32 trcidr2; + + _REG_(M33_TRCIDR3_OFFSET) // M33_TRCIDR3 + // TRCIDR3 + // 0x80000000 [31] NOOVERFLOW (0) reads as `ImpDef + // 0x70000000 [30:28] NUMPROC (0x0) reads as `ImpDef + // 0x08000000 [27] SYSSTALL (1) reads as `ImpDef + // 0x04000000 [26] STALLCTL (1) reads as `ImpDef + // 0x02000000 [25] SYNCPR (1) reads as `ImpDef + // 0x01000000 [24] TRCERR (1) reads as `ImpDef + // 0x00f00000 [23:20] EXLEVEL_NS (0x0) reads as `ImpDef + // 0x000f0000 [19:16] EXLEVEL_S (0x9) reads as `ImpDef + // 0x00000fff [11:0] CCITMIN (0x004) reads as `ImpDef + io_ro_32 trcidr3; + + _REG_(M33_TRCIDR4_OFFSET) // M33_TRCIDR4 + // TRCIDR4 + // 0xf0000000 [31:28] NUMVMIDC (0x0) reads as `ImpDef + // 0x0f000000 [27:24] NUMCIDC (0x0) reads as `ImpDef + // 0x00f00000 [23:20] NUMSSCC (0x1) reads as `ImpDef + // 0x000f0000 [19:16] NUMRSPAIR (0x1) reads as `ImpDef + // 0x0000f000 [15:12] NUMPC (0x4) reads as `ImpDef + // 0x00000100 [8] SUPPDAC (0) reads as `ImpDef + // 0x000000f0 [7:4] NUMDVC (0x0) reads as `ImpDef + // 0x0000000f [3:0] NUMACPAIRS (0x0) reads as `ImpDef + io_ro_32 trcidr4; + + _REG_(M33_TRCIDR5_OFFSET) // M33_TRCIDR5 + // TRCIDR5 + // 0x80000000 [31] REDFUNCNTR (1) reads as `ImpDef + // 0x70000000 [30:28] NUMCNTR (0x1) reads as `ImpDef + // 0x0e000000 [27:25] NUMSEQSTATE (0x0) reads as `ImpDef + // 0x00800000 [23] LPOVERRIDE (1) reads as `ImpDef + // 0x00400000 [22] ATBTRIG (1) reads as `ImpDef + // 0x003f0000 [21:16] TRACEIDSIZE (0x07) reads as 0x07 + // 0x00000e00 [11:9] NUMEXTINSEL (0x0) reads as `ImpDef + // 0x000001ff [8:0] NUMEXTIN (0x004) reads as `ImpDef + io_ro_32 trcidr5; + + _REG_(M33_TRCIDR6_OFFSET) // M33_TRCIDR6 + // TRCIDR6 + // 0x00000000 [31:0] TRCIDR6 (0x00000000) + io_rw_32 trcidr6; + + _REG_(M33_TRCIDR7_OFFSET) // M33_TRCIDR7 + // TRCIDR7 + // 0x00000000 [31:0] TRCIDR7 (0x00000000) + io_rw_32 trcidr7; + + uint32_t _pad52[2]; + + // (Description copied from array index 0 register M33_TRCRSCTLR2 applies similarly to other array indexes) + _REG_(M33_TRCRSCTLR2_OFFSET) // M33_TRCRSCTLR2 + // The TRCRSCTLR controls the trace resources + // 0x00200000 [21] PAIRINV (0) Inverts the result of a combined pair of resources + // 0x00100000 [20] INV (0) Inverts the selected resources + // 0x00070000 [18:16] GROUP (0x0) Selects a group of resource + // 0x000000ff [7:0] SELECT (0x00) Selects one or more resources from the wanted group + io_rw_32 trcrsctlr[2]; + + uint32_t _pad53[36]; + + _REG_(M33_TRCSSCSR_OFFSET) // M33_TRCSSCSR + // Controls the corresponding single-shot comparator resource + // 0x80000000 [31] STATUS (0) Single-shot status bit + // 0x00000008 [3] PC (0) Reserved, RES1 + // 0x00000004 [2] DV (0) Reserved, RES0 + // 0x00000002 [1] DA (0) Reserved, RES0 + // 0x00000001 [0] INST (0) Reserved, RES0 + io_rw_32 trcsscsr; + + uint32_t _pad54[7]; + + _REG_(M33_TRCSSPCICR_OFFSET) // M33_TRCSSPCICR + // Selects the PE comparator inputs for Single-shot control + // 0x0000000f [3:0] PC (0x0) Selects one or more PE comparator inputs for Single-shot control + io_rw_32 trcsspcicr; + + uint32_t _pad55[19]; + + _REG_(M33_TRCPDCR_OFFSET) // M33_TRCPDCR + // Requests the system to provide power to the trace unit + // 0x00000008 [3] PU (0) Powerup request bit: + io_rw_32 trcpdcr; + + _REG_(M33_TRCPDSR_OFFSET) // M33_TRCPDSR + // Returns the following information about the trace unit: - OS Lock status + // 0x00000020 [5] OSLK (0) OS Lock status bit: + // 0x00000002 [1] STICKYPD (1) Sticky powerdown status bit + // 0x00000001 [0] POWER (1) Power status bit: + io_ro_32 trcpdsr; + + uint32_t _pad56[755]; + + _REG_(M33_TRCITATBIDR_OFFSET) // M33_TRCITATBIDR + // Trace Integration ATB Identification Register + // 0x0000007f [6:0] ID (0x00) Trace ID + io_rw_32 trcitatbidr; + + uint32_t _pad57[3]; + + _REG_(M33_TRCITIATBINR_OFFSET) // M33_TRCITIATBINR + // Trace Integration Instruction ATB In Register + // 0x00000002 [1] AFVALIDM (0) Integration Mode instruction AFVALIDM in + // 0x00000001 [0] ATREADYM (0) Integration Mode instruction ATREADYM in + io_rw_32 trcitiatbinr; + + uint32_t _pad58; + + _REG_(M33_TRCITIATBOUTR_OFFSET) // M33_TRCITIATBOUTR + // Trace Integration Instruction ATB Out Register + // 0x00000002 [1] AFREADY (0) Integration Mode instruction AFREADY out + // 0x00000001 [0] ATVALID (0) Integration Mode instruction ATVALID out + io_rw_32 trcitiatboutr; + + uint32_t _pad59[40]; + + _REG_(M33_TRCCLAIMSET_OFFSET) // M33_TRCCLAIMSET + // Claim Tag Set Register + // 0x00000008 [3] SET3 (1) When a write to one of these bits occurs, with the value: + // 0x00000004 [2] SET2 (1) When a write to one of these bits occurs, with the value: + // 0x00000002 [1] SET1 (1) When a write to one of these bits occurs, with the value: + // 0x00000001 [0] SET0 (1) When a write to one of these bits occurs, with the value: + io_rw_32 trcclaimset; + + _REG_(M33_TRCCLAIMCLR_OFFSET) // M33_TRCCLAIMCLR + // Claim Tag Clear Register + // 0x00000008 [3] CLR3 (0) When a write to one of these bits occurs, with the value: + // 0x00000004 [2] CLR2 (0) When a write to one of these bits occurs, with the value: + // 0x00000002 [1] CLR1 (0) When a write to one of these bits occurs, with the value: + // 0x00000001 [0] CLR0 (0) When a write to one of these bits occurs, with the value: + io_rw_32 trcclaimclr; + + uint32_t _pad60[4]; + + _REG_(M33_TRCAUTHSTATUS_OFFSET) // M33_TRCAUTHSTATUS + // Returns the level of tracing that the trace unit can support + // 0x000000c0 [7:6] SNID (0x0) Indicates whether the system enables the trace unit to... + // 0x00000030 [5:4] SID (0x0) Indicates whether the trace unit supports Secure invasive debug: + // 0x0000000c [3:2] NSNID (0x0) Indicates whether the system enables the trace unit to... + // 0x00000003 [1:0] NSID (0x0) Indicates whether the trace unit supports Non-secure... + io_ro_32 trcauthstatus; + + _REG_(M33_TRCDEVARCH_OFFSET) // M33_TRCDEVARCH + // TRCDEVARCH + // 0xffe00000 [31:21] ARCHITECT (0x23b) reads as 0b01000111011 + // 0x00100000 [20] PRESENT (1) reads as 0b1 + // 0x000f0000 [19:16] REVISION (0x2) reads as 0b0000 + // 0x0000ffff [15:0] ARCHID (0x4a13) reads as 0b0100101000010011 + io_ro_32 trcdevarch; + + uint32_t _pad61[2]; + + _REG_(M33_TRCDEVID_OFFSET) // M33_TRCDEVID + // TRCDEVID + // 0x00000000 [31:0] TRCDEVID (0x00000000) + io_rw_32 trcdevid; + + _REG_(M33_TRCDEVTYPE_OFFSET) // M33_TRCDEVTYPE + // TRCDEVTYPE + // 0x000000f0 [7:4] SUB (0x1) reads as 0b0001 + // 0x0000000f [3:0] MAJOR (0x3) reads as 0b0011 + io_ro_32 trcdevtype; + + _REG_(M33_TRCPIDR4_OFFSET) // M33_TRCPIDR4 + // TRCPIDR4 + // 0x000000f0 [7:4] SIZE (0x0) reads as `ImpDef + // 0x0000000f [3:0] DES_2 (0x4) reads as `ImpDef + io_ro_32 trcpidr4; + + _REG_(M33_TRCPIDR5_OFFSET) // M33_TRCPIDR5 + // TRCPIDR5 + // 0x00000000 [31:0] TRCPIDR5 (0x00000000) + io_rw_32 trcpidr5; + + _REG_(M33_TRCPIDR6_OFFSET) // M33_TRCPIDR6 + // TRCPIDR6 + // 0x00000000 [31:0] TRCPIDR6 (0x00000000) + io_rw_32 trcpidr6; + + _REG_(M33_TRCPIDR7_OFFSET) // M33_TRCPIDR7 + // TRCPIDR7 + // 0x00000000 [31:0] TRCPIDR7 (0x00000000) + io_rw_32 trcpidr7; + + _REG_(M33_TRCPIDR0_OFFSET) // M33_TRCPIDR0 + // TRCPIDR0 + // 0x000000ff [7:0] PART_0 (0x21) reads as `ImpDef + io_ro_32 trcpidr0; + + _REG_(M33_TRCPIDR1_OFFSET) // M33_TRCPIDR1 + // TRCPIDR1 + // 0x000000f0 [7:4] DES_0 (0xb) reads as `ImpDef + // 0x0000000f [3:0] PART_0 (0xd) reads as `ImpDef + io_ro_32 trcpidr1; + + _REG_(M33_TRCPIDR2_OFFSET) // M33_TRCPIDR2 + // TRCPIDR2 + // 0x000000f0 [7:4] REVISION (0x2) reads as `ImpDef + // 0x00000008 [3] JEDEC (1) reads as 0b1 + // 0x00000007 [2:0] DES_0 (0x3) reads as `ImpDef + io_ro_32 trcpidr2; + + _REG_(M33_TRCPIDR3_OFFSET) // M33_TRCPIDR3 + // TRCPIDR3 + // 0x000000f0 [7:4] REVAND (0x0) reads as `ImpDef + // 0x0000000f [3:0] CMOD (0x0) reads as `ImpDef + io_ro_32 trcpidr3; + + // (Description copied from array index 0 register M33_TRCCIDR0 applies similarly to other array indexes) + _REG_(M33_TRCCIDR0_OFFSET) // M33_TRCCIDR0 + // TRCCIDR0 + // 0x000000ff [7:0] PRMBL_0 (0x0d) reads as 0b00001101 + io_ro_32 trccidr[4]; + + _REG_(M33_CTICONTROL_OFFSET) // M33_CTICONTROL + // CTI Control Register + // 0x00000001 [0] GLBEN (0) Enables or disables the CTI + io_rw_32 cticontrol; + + uint32_t _pad62[3]; + + _REG_(M33_CTIINTACK_OFFSET) // M33_CTIINTACK + // CTI Interrupt Acknowledge Register + // 0x000000ff [7:0] INTACK (0x00) Acknowledges the corresponding ctitrigout output + io_rw_32 ctiintack; + + _REG_(M33_CTIAPPSET_OFFSET) // M33_CTIAPPSET + // CTI Application Trigger Set Register + // 0x0000000f [3:0] APPSET (0x0) Setting a bit HIGH generates a channel event for the... + io_rw_32 ctiappset; + + _REG_(M33_CTIAPPCLEAR_OFFSET) // M33_CTIAPPCLEAR + // CTI Application Trigger Clear Register + // 0x0000000f [3:0] APPCLEAR (0x0) Sets the corresponding bits in the CTIAPPSET to 0 + io_rw_32 ctiappclear; + + _REG_(M33_CTIAPPPULSE_OFFSET) // M33_CTIAPPPULSE + // CTI Application Pulse Register + // 0x0000000f [3:0] APPULSE (0x0) Setting a bit HIGH generates a channel event pulse for... + io_rw_32 ctiapppulse; + + // (Description copied from array index 0 register M33_CTIINEN0 applies similarly to other array indexes) + _REG_(M33_CTIINEN0_OFFSET) // M33_CTIINEN0 + // CTI Trigger to Channel Enable Registers + // 0x0000000f [3:0] TRIGINEN (0x0) Enables a cross trigger event to the corresponding... + io_rw_32 ctiinen[8]; + + uint32_t _pad63[24]; + + // (Description copied from array index 0 register M33_CTIOUTEN0 applies similarly to other array indexes) + _REG_(M33_CTIOUTEN0_OFFSET) // M33_CTIOUTEN0 + // CTI Trigger to Channel Enable Registers + // 0x0000000f [3:0] TRIGOUTEN (0x0) Enables a cross trigger event to ctitrigout when the... + io_rw_32 ctiouten[8]; + + uint32_t _pad64[28]; + + _REG_(M33_CTITRIGINSTATUS_OFFSET) // M33_CTITRIGINSTATUS + // CTI Trigger to Channel Enable Registers + // 0x000000ff [7:0] TRIGINSTATUS (0x00) Shows the status of the ctitrigin inputs + io_ro_32 ctitriginstatus; + + _REG_(M33_CTITRIGOUTSTATUS_OFFSET) // M33_CTITRIGOUTSTATUS + // CTI Trigger In Status Register + // 0x000000ff [7:0] TRIGOUTSTATUS (0x00) Shows the status of the ctitrigout outputs + io_ro_32 ctitrigoutstatus; + + _REG_(M33_CTICHINSTATUS_OFFSET) // M33_CTICHINSTATUS + // CTI Channel In Status Register + // 0x0000000f [3:0] CTICHOUTSTATUS (0x0) Shows the status of the ctichout outputs + io_ro_32 ctichinstatus; + + uint32_t _pad65; + + _REG_(M33_CTIGATE_OFFSET) // M33_CTIGATE + // Enable CTI Channel Gate register + // 0x00000008 [3] CTIGATEEN3 (1) Enable ctichout3 + // 0x00000004 [2] CTIGATEEN2 (1) Enable ctichout2 + // 0x00000002 [1] CTIGATEEN1 (1) Enable ctichout1 + // 0x00000001 [0] CTIGATEEN0 (1) Enable ctichout0 + io_rw_32 ctigate; + + _REG_(M33_ASICCTL_OFFSET) // M33_ASICCTL + // External Multiplexer Control register + // 0x00000000 [31:0] ASICCTL (0x00000000) + io_rw_32 asicctl; + + uint32_t _pad66[871]; + + _REG_(M33_ITCHOUT_OFFSET) // M33_ITCHOUT + // Integration Test Channel Output register + // 0x0000000f [3:0] CTCHOUT (0x0) Sets the value of the ctichout outputs + io_rw_32 itchout; + + _REG_(M33_ITTRIGOUT_OFFSET) // M33_ITTRIGOUT + // Integration Test Trigger Output register + // 0x000000ff [7:0] CTTRIGOUT (0x00) Sets the value of the ctitrigout outputs + io_rw_32 ittrigout; + + uint32_t _pad67[2]; + + _REG_(M33_ITCHIN_OFFSET) // M33_ITCHIN + // Integration Test Channel Input register + // 0x0000000f [3:0] CTCHIN (0x0) Reads the value of the ctichin inputs + io_ro_32 itchin; + + uint32_t _pad68[2]; + + _REG_(M33_ITCTRL_OFFSET) // M33_ITCTRL + // Integration Mode Control register + // 0x00000001 [0] IME (0) Integration Mode Enable + io_rw_32 itctrl; + + uint32_t _pad69[46]; + + _REG_(M33_DEVARCH_OFFSET) // M33_DEVARCH + // Device Architecture register + // 0xffe00000 [31:21] ARCHITECT (0x23b) Indicates the component architect + // 0x00100000 [20] PRESENT (1) Indicates whether the DEVARCH register is present + // 0x000f0000 [19:16] REVISION (0x0) Indicates the architecture revision + // 0x0000ffff [15:0] ARCHID (0x1a14) Indicates the component + io_ro_32 devarch; + + uint32_t _pad70[2]; + + _REG_(M33_DEVID_OFFSET) // M33_DEVID + // Device Configuration register + // 0x000f0000 [19:16] NUMCH (0x4) Number of ECT channels available + // 0x0000ff00 [15:8] NUMTRIG (0x08) Number of ECT triggers available + // 0x0000001f [4:0] EXTMUXNUM (0x00) Indicates the number of multiplexers available on... + io_ro_32 devid; + + _REG_(M33_DEVTYPE_OFFSET) // M33_DEVTYPE + // Device Type Identifier register + // 0x000000f0 [7:4] SUB (0x1) Sub-classification of the type of the debug component as... + // 0x0000000f [3:0] MAJOR (0x4) Major classification of the type of the debug component... + io_ro_32 devtype; + + _REG_(M33_PIDR4_OFFSET) // M33_PIDR4 + // CoreSight Peripheral ID4 + // 0x000000f0 [7:4] SIZE (0x0) Always 0b0000 + // 0x0000000f [3:0] DES_2 (0x4) Together, PIDR1 + io_ro_32 pidr4; + + _REG_(M33_PIDR5_OFFSET) // M33_PIDR5 + // CoreSight Peripheral ID5 + // 0x00000000 [31:0] PIDR5 (0x00000000) + io_rw_32 pidr5; + + _REG_(M33_PIDR6_OFFSET) // M33_PIDR6 + // CoreSight Peripheral ID6 + // 0x00000000 [31:0] PIDR6 (0x00000000) + io_rw_32 pidr6; + + _REG_(M33_PIDR7_OFFSET) // M33_PIDR7 + // CoreSight Peripheral ID7 + // 0x00000000 [31:0] PIDR7 (0x00000000) + io_rw_32 pidr7; + + _REG_(M33_PIDR0_OFFSET) // M33_PIDR0 + // CoreSight Peripheral ID0 + // 0x000000ff [7:0] PART_0 (0x21) Bits[7:0] of the 12-bit part number of the component + io_ro_32 pidr0; + + _REG_(M33_PIDR1_OFFSET) // M33_PIDR1 + // CoreSight Peripheral ID1 + // 0x000000f0 [7:4] DES_0 (0xb) Together, PIDR1 + // 0x0000000f [3:0] PART_1 (0xd) Bits[11:8] of the 12-bit part number of the component + io_ro_32 pidr1; + + _REG_(M33_PIDR2_OFFSET) // M33_PIDR2 + // CoreSight Peripheral ID2 + // 0x000000f0 [7:4] REVISION (0x0) This device is at r1p0 + // 0x00000008 [3] JEDEC (1) Always 1 + // 0x00000007 [2:0] DES_1 (0x3) Together, PIDR1 + io_ro_32 pidr2; + + _REG_(M33_PIDR3_OFFSET) // M33_PIDR3 + // CoreSight Peripheral ID3 + // 0x000000f0 [7:4] REVAND (0x0) Indicates minor errata fixes specific to the revision of... + // 0x0000000f [3:0] CMOD (0x0) Customer Modified + io_ro_32 pidr3; + + // (Description copied from array index 0 register M33_CIDR0 applies similarly to other array indexes) + _REG_(M33_CIDR0_OFFSET) // M33_CIDR0 + // CoreSight Component ID0 + // 0x000000ff [7:0] PRMBL_0 (0x0d) Preamble[0] + io_ro_32 cidr[4]; +} m33_hw_t; + +#define m33_hw ((m33_hw_t *)PPB_BASE) +#define m33_ns_hw ((m33_hw_t *)PPB_NONSEC_BASE) +static_assert(sizeof (m33_hw_t) == 0x43000, ""); + +#endif // _HARDWARE_STRUCTS_M33_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/m33_eppb.h b/lib/pico-sdk/rp2350/hardware/structs/m33_eppb.h new file mode 100644 index 000000000000..3b271e6f008b --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/m33_eppb.h @@ -0,0 +1,50 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_M33_EPPB_H +#define _HARDWARE_STRUCTS_M33_EPPB_H + +/** + * \file rp2350/m33_eppb.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33_eppb.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33_eppb +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33_eppb.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + + +typedef struct { + // (Description copied from array index 0 register M33_EPPB_NMI_MASK0 applies similarly to other array indexes) + _REG_(M33_EPPB_NMI_MASK0_OFFSET) // M33_EPPB_NMI_MASK0 + // NMI mask for IRQs 0 through 31 + // 0xffffffff [31:0] NMI_MASK0 (0x00000000) + io_rw_32 nmi_mask[2]; + + _REG_(M33_EPPB_SLEEPCTRL_OFFSET) // M33_EPPB_SLEEPCTRL + // Nonstandard sleep control register + // 0x00000004 [2] WICENACK (0) Status signal from the processor's interrupt controller + // 0x00000002 [1] WICENREQ (1) Request that the next processor deep sleep is a WIC sleep + // 0x00000001 [0] LIGHT_SLEEP (0) By default, any processor sleep will deassert the... + io_rw_32 sleepctrl; +} m33_eppb_hw_t; + +#define eppb_hw ((m33_eppb_hw_t *)EPPB_BASE) +static_assert(sizeof (m33_eppb_hw_t) == 0x000c, ""); + +#endif // _HARDWARE_STRUCTS_M33_EPPB_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/mpu.h b/lib/pico-sdk/rp2350/hardware/structs/mpu.h new file mode 100644 index 000000000000..e3bf920d1931 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/mpu.h @@ -0,0 +1,126 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_MPU_H +#define _HARDWARE_STRUCTS_MPU_H + +/** + * \file rp2350/mpu.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + _REG_(M33_MPU_TYPE_OFFSET) // M33_MPU_TYPE + // The MPU Type Register indicates how many regions the MPU `FTSSS supports + // 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU + // 0x00000001 [0] SEPARATE (0) Indicates support for separate instructions and data... + io_ro_32 type; + + _REG_(M33_MPU_CTRL_OFFSET) // M33_MPU_CTRL + // Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled... + // 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled for... + // 0x00000002 [1] HFNMIENA (0) Controls whether handlers executing with priority less... + // 0x00000001 [0] ENABLE (0) Enables the MPU + io_rw_32 ctrl; + + _REG_(M33_MPU_RNR_OFFSET) // M33_MPU_RNR + // Selects the region currently accessed by MPU_RBAR and MPU_RLAR + // 0x00000007 [2:0] REGION (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR + io_rw_32 rnr; + + _REG_(M33_MPU_RBAR_OFFSET) // M33_MPU_RBAR + // Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 rbar; + + _REG_(M33_MPU_RLAR_OFFSET) // M33_MPU_RLAR + // Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 rlar; + + _REG_(M33_MPU_RBAR_A1_OFFSET) // M33_MPU_RBAR_A1 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 rbar_a1; + + _REG_(M33_MPU_RLAR_A1_OFFSET) // M33_MPU_RLAR_A1 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 rlar_a1; + + _REG_(M33_MPU_RBAR_A2_OFFSET) // M33_MPU_RBAR_A2 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 rbar_a2; + + _REG_(M33_MPU_RLAR_A2_OFFSET) // M33_MPU_RLAR_A2 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 rlar_a2; + + _REG_(M33_MPU_RBAR_A3_OFFSET) // M33_MPU_RBAR_A3 + // Provides indirect read and write access to the base address of the MPU region selected by... + // 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the... + // 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory + // 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region + // 0x00000001 [0] XN (0) Defines whether code can be executed from this region + io_rw_32 rbar_a3; + + _REG_(M33_MPU_RLAR_A3_OFFSET) // M33_MPU_RLAR_A3 + // Provides indirect read and write access to the limit address of the currently selected MPU... + // 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the... + // 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and... + // 0x00000001 [0] EN (0) Region enable + io_rw_32 rlar_a3; + + uint32_t _pad0; + + // (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes) + _REG_(M33_MPU_MAIR0_OFFSET) // M33_MPU_MAIR0 + // Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values + // 0xff000000 [31:24] ATTR3 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3 + // 0x00ff0000 [23:16] ATTR2 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2 + // 0x0000ff00 [15:8] ATTR1 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1 + // 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0 + io_rw_32 mair[2]; +} mpu_hw_t; + +#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M33_MPU_TYPE_OFFSET)) +#define mpu_ns_hw ((mpu_hw_t *)(PPB_NONSEC_BASE + M33_MPU_TYPE_OFFSET)) +static_assert(sizeof (mpu_hw_t) == 0x0038, ""); + +#endif // _HARDWARE_STRUCTS_MPU_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/nvic.h b/lib/pico-sdk/rp2350/hardware/structs/nvic.h new file mode 100644 index 000000000000..c0c7b76bdec0 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/nvic.h @@ -0,0 +1,94 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_NVIC_H +#define _HARDWARE_STRUCTS_NVIC_H + +/** + * \file rp2350/nvic.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + // (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes) + _REG_(M33_NVIC_ISER0_OFFSET) // M33_NVIC_ISER0 + // Enables or reads the enabled state of each group of 32 interrupts + // 0xffffffff [31:0] SETENA (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether... + io_rw_32 iser[2]; + + uint32_t _pad0[30]; + + // (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes) + _REG_(M33_NVIC_ICER0_OFFSET) // M33_NVIC_ICER0 + // Clears or reads the enabled state of each group of 32 interrupts + // 0xffffffff [31:0] CLRENA (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether... + io_rw_32 icer[2]; + + uint32_t _pad1[30]; + + // (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_ISPR0_OFFSET) // M33_NVIC_ISPR0 + // Enables or reads the pending state of each group of 32 interrupts + // 0xffffffff [31:0] SETPEND (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether... + io_rw_32 ispr[2]; + + uint32_t _pad2[30]; + + // (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_ICPR0_OFFSET) // M33_NVIC_ICPR0 + // Clears or reads the pending state of each group of 32 interrupts + // 0xffffffff [31:0] CLRPEND (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether... + io_rw_32 icpr[2]; + + uint32_t _pad3[30]; + + // (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes) + _REG_(M33_NVIC_IABR0_OFFSET) // M33_NVIC_IABR0 + // For each group of 32 interrupts, shows the active state of each interrupt + // 0xffffffff [31:0] ACTIVE (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state... + io_rw_32 iabr[2]; + + uint32_t _pad4[30]; + + // (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes) + _REG_(M33_NVIC_ITNS0_OFFSET) // M33_NVIC_ITNS0 + // For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state + // 0xffffffff [31:0] ITNS (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security... + io_rw_32 itns[2]; + + uint32_t _pad5[30]; + + // (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes) + _REG_(M33_NVIC_IPR0_OFFSET) // M33_NVIC_IPR0 + // Sets or reads interrupt priorities + // 0xf0000000 [31:28] PRI_N3 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x00f00000 [23:20] PRI_N2 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x0000f000 [15:12] PRI_N1 (0x0) For register NVIC_IPRn, the priority of interrupt number... + // 0x000000f0 [7:4] PRI_N0 (0x0) For register NVIC_IPRn, the priority of interrupt number... + io_rw_32 ipr[16]; +} nvic_hw_t; + +#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M33_NVIC_ISER0_OFFSET)) +#define nvic_ns_hw ((nvic_hw_t *)(PPB_NONSEC_BASE + M33_NVIC_ISER0_OFFSET)) +static_assert(sizeof (nvic_hw_t) == 0x0340, ""); + +#endif // _HARDWARE_STRUCTS_NVIC_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/otp.h b/lib/pico-sdk/rp2350/hardware/structs/otp.h new file mode 100644 index 000000000000..803643b86e9e --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/otp.h @@ -0,0 +1,192 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_OTP_H +#define _HARDWARE_STRUCTS_OTP_H + +/** + * \file rp2350/otp.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/otp.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_otp +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/otp.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + // (Description copied from array index 0 register OTP_SW_LOCK0 applies similarly to other array indexes) + _REG_(OTP_SW_LOCK0_OFFSET) // OTP_SW_LOCK0 + // Software lock register for page 0. + // 0x0000000c [3:2] NSEC (-) Non-secure lock status + // 0x00000003 [1:0] SEC (-) Secure lock status + io_rw_32 sw_lock[64]; + + _REG_(OTP_SBPI_INSTR_OFFSET) // OTP_SBPI_INSTR + // Dispatch instructions to the SBPI interface, used for programming the OTP fuses + // 0x40000000 [30] EXEC (0) Execute instruction + // 0x20000000 [29] IS_WR (0) Payload type is write + // 0x10000000 [28] HAS_PAYLOAD (0) Instruction has payload (data to be written or to be read) + // 0x0f000000 [27:24] PAYLOAD_SIZE_M1 (0x0) Instruction payload size in bytes minus 1 + // 0x00ff0000 [23:16] TARGET (0x00) Instruction target, it can be PMC (0x3a) or DAP (0x02) + // 0x0000ff00 [15:8] CMD (0x00) + // 0x000000ff [7:0] SHORT_WDATA (0x00) wdata to be used only when payload_size_m1=0 + io_rw_32 sbpi_instr; + + // (Description copied from array index 0 register OTP_SBPI_WDATA_0 applies similarly to other array indexes) + _REG_(OTP_SBPI_WDATA_0_OFFSET) // OTP_SBPI_WDATA_0 + // SBPI write payload bytes 3 + // 0xffffffff [31:0] SBPI_WDATA_0 (0x00000000) + io_rw_32 sbpi_wdata[4]; + + // (Description copied from array index 0 register OTP_SBPI_RDATA_0 applies similarly to other array indexes) + _REG_(OTP_SBPI_RDATA_0_OFFSET) // OTP_SBPI_RDATA_0 + // Read payload bytes 3 + // 0xffffffff [31:0] SBPI_RDATA_0 (0x00000000) + io_ro_32 sbpi_rdata[4]; + + _REG_(OTP_SBPI_STATUS_OFFSET) // OTP_SBPI_STATUS + // 0x00ff0000 [23:16] MISO (-) SBPI MISO (master in - slave out): response from SBPI + // 0x00001000 [12] FLAG (-) SBPI flag + // 0x00000100 [8] INSTR_MISS (0) Last instruction missed (dropped), as the previous has... + // 0x00000010 [4] INSTR_DONE (0) Last instruction done + // 0x00000001 [0] RDATA_VLD (0) Read command has returned data + io_rw_32 sbpi_status; + + _REG_(OTP_USR_OFFSET) // OTP_USR + // Controls for APB data read interface (USER interface) + // 0x00000010 [4] PD (0) Power-down; 1 disables current reference + // 0x00000001 [0] DCTRL (1) 1 enables USER interface; 0 disables USER interface... + io_rw_32 usr; + + _REG_(OTP_DBG_OFFSET) // OTP_DBG + // Debug for OTP power-on state machine + // 0x00001000 [12] CUSTOMER_RMA_FLAG (-) The chip is in RMA mode + // 0x000000f0 [7:4] PSM_STATE (-) Monitor the PSM FSM's state + // 0x00000008 [3] ROSC_UP (-) Ring oscillator is up and running + // 0x00000004 [2] ROSC_UP_SEEN (0) Ring oscillator was seen up and running + // 0x00000002 [1] BOOT_DONE (-) PSM boot done status flag + // 0x00000001 [0] PSM_DONE (-) PSM done status flag + io_rw_32 dbg; + + uint32_t _pad0; + + _REG_(OTP_BIST_OFFSET) // OTP_BIST + // During BIST, count address locations that have at least one leaky bit + // 0x40000000 [30] CNT_FAIL (-) Flag if the count of address locations with at least one... + // 0x20000000 [29] CNT_CLR (0) Clear counter before use + // 0x10000000 [28] CNT_ENA (0) Enable the counter before the BIST function is initiated + // 0x0fff0000 [27:16] CNT_MAX (0xfff) The cnt_fail flag will be set if the number of leaky... + // 0x00001fff [12:0] CNT (-) Number of locations that have at least one leaky bit + io_rw_32 bist; + + // (Description copied from array index 0 register OTP_CRT_KEY_W0 applies similarly to other array indexes) + _REG_(OTP_CRT_KEY_W0_OFFSET) // OTP_CRT_KEY_W0 + // Word 0 (bits 31 + // 0xffffffff [31:0] CRT_KEY_W0 (0x00000000) + io_wo_32 crt_key_w[4]; + + _REG_(OTP_CRITICAL_OFFSET) // OTP_CRITICAL + // Quickly check values of critical flags read during boot up + // 0x00020000 [17] RISCV_DISABLE (0) + // 0x00010000 [16] ARM_DISABLE (0) + // 0x00000060 [6:5] GLITCH_DETECTOR_SENS (0x0) + // 0x00000010 [4] GLITCH_DETECTOR_ENABLE (0) + // 0x00000008 [3] DEFAULT_ARCHSEL (0) + // 0x00000004 [2] DEBUG_DISABLE (0) + // 0x00000002 [1] SECURE_DEBUG_DISABLE (0) + // 0x00000001 [0] SECURE_BOOT_ENABLE (0) + io_ro_32 critical; + + _REG_(OTP_KEY_VALID_OFFSET) // OTP_KEY_VALID + // Which keys were valid (enrolled) at boot time + // 0x000000ff [7:0] KEY_VALID (0x00) + io_ro_32 key_valid; + + _REG_(OTP_DEBUGEN_OFFSET) // OTP_DEBUGEN + // Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. + // 0x00000100 [8] MISC (0) Enable other debug components + // 0x00000008 [3] PROC1_SECURE (0) Permit core 1's Mem-AP to generate Secure accesses,... + // 0x00000004 [2] PROC1 (0) Enable core 1's Mem-AP if it is currently disabled + // 0x00000002 [1] PROC0_SECURE (0) Permit core 0's Mem-AP to generate Secure accesses,... + // 0x00000001 [0] PROC0 (0) Enable core 0's Mem-AP if it is currently disabled + io_rw_32 debugen; + + _REG_(OTP_DEBUGEN_LOCK_OFFSET) // OTP_DEBUGEN_LOCK + // Write 1s to lock corresponding bits in DEBUGEN + // 0x00000100 [8] MISC (0) Write 1 to lock the MISC bit of DEBUGEN + // 0x00000008 [3] PROC1_SECURE (0) Write 1 to lock the PROC1_SECURE bit of DEBUGEN + // 0x00000004 [2] PROC1 (0) Write 1 to lock the PROC1 bit of DEBUGEN + // 0x00000002 [1] PROC0_SECURE (0) Write 1 to lock the PROC0_SECURE bit of DEBUGEN + // 0x00000001 [0] PROC0 (0) Write 1 to lock the PROC0 bit of DEBUGEN + io_rw_32 debugen_lock; + + _REG_(OTP_ARCHSEL_OFFSET) // OTP_ARCHSEL + // Architecture select (Arm/RISC-V), applied on next processor reset. The default and allowable values of this register are constrained by the critical boot flags. + // 0x00000002 [1] CORE1 (0) Select architecture for core 1 + // 0x00000001 [0] CORE0 (0) Select architecture for core 0 + io_rw_32 archsel; + + _REG_(OTP_ARCHSEL_STATUS_OFFSET) // OTP_ARCHSEL_STATUS + // Get the current architecture select state of each core + // 0x00000002 [1] CORE1 (0) Current architecture for core 0 + // 0x00000001 [0] CORE0 (0) Current architecture for core 0 + io_ro_32 archsel_status; + + _REG_(OTP_BOOTDIS_OFFSET) // OTP_BOOTDIS + // Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. + // 0x00000002 [1] NEXT (0) This flag always ORs writes into its current contents + // 0x00000001 [0] NOW (0) When the core is powered down, the current value of... + io_rw_32 bootdis; + + _REG_(OTP_INTR_OFFSET) // OTP_INTR + // Raw Interrupts + // 0x00000010 [4] APB_RD_NSEC_FAIL (0) + // 0x00000008 [3] APB_RD_SEC_FAIL (0) + // 0x00000004 [2] APB_DCTRL_FAIL (0) + // 0x00000002 [1] SBPI_WR_FAIL (0) + // 0x00000001 [0] SBPI_FLAG_N (0) + io_rw_32 intr; + + _REG_(OTP_INTE_OFFSET) // OTP_INTE + // Interrupt Enable + // 0x00000010 [4] APB_RD_NSEC_FAIL (0) + // 0x00000008 [3] APB_RD_SEC_FAIL (0) + // 0x00000004 [2] APB_DCTRL_FAIL (0) + // 0x00000002 [1] SBPI_WR_FAIL (0) + // 0x00000001 [0] SBPI_FLAG_N (0) + io_rw_32 inte; + + _REG_(OTP_INTF_OFFSET) // OTP_INTF + // Interrupt Force + // 0x00000010 [4] APB_RD_NSEC_FAIL (0) + // 0x00000008 [3] APB_RD_SEC_FAIL (0) + // 0x00000004 [2] APB_DCTRL_FAIL (0) + // 0x00000002 [1] SBPI_WR_FAIL (0) + // 0x00000001 [0] SBPI_FLAG_N (0) + io_rw_32 intf; + + _REG_(OTP_INTS_OFFSET) // OTP_INTS + // Interrupt status after masking & forcing + // 0x00000010 [4] APB_RD_NSEC_FAIL (0) + // 0x00000008 [3] APB_RD_SEC_FAIL (0) + // 0x00000004 [2] APB_DCTRL_FAIL (0) + // 0x00000002 [1] SBPI_WR_FAIL (0) + // 0x00000001 [0] SBPI_FLAG_N (0) + io_ro_32 ints; +} otp_hw_t; + +#define otp_hw ((otp_hw_t *)OTP_BASE) +static_assert(sizeof (otp_hw_t) == 0x0174, ""); + +#endif // _HARDWARE_STRUCTS_OTP_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/pads_bank0.h b/lib/pico-sdk/rp2350/hardware/structs/pads_bank0.h new file mode 100644 index 000000000000..bf0f4a53f191 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/pads_bank0.h @@ -0,0 +1,49 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PADS_BANK0_H +#define _HARDWARE_STRUCTS_PADS_BANK0_H + +/** + * \file rp2350/pads_bank0.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pads_bank0.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pads_bank0 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT + // Voltage select + // 0x00000001 [0] VOLTAGE_SELECT (0) + io_rw_32 voltage_select; + + // (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes) + _REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0 + // 0x00000100 [8] ISO (1) Pad isolation control + // 0x00000080 [7] OD (0) Output disable + // 0x00000040 [6] IE (0) Input enable + // 0x00000030 [5:4] DRIVE (0x1) Drive strength + // 0x00000008 [3] PUE (0) Pull up enable + // 0x00000004 [2] PDE (1) Pull down enable + // 0x00000002 [1] SCHMITT (1) Enable schmitt trigger + // 0x00000001 [0] SLEWFAST (0) Slew rate control + io_rw_32 io[48]; +} pads_bank0_hw_t; + +#define pads_bank0_hw ((pads_bank0_hw_t *)PADS_BANK0_BASE) +static_assert(sizeof (pads_bank0_hw_t) == 0x00c4, ""); + +#endif // _HARDWARE_STRUCTS_PADS_BANK0_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/pads_qspi.h b/lib/pico-sdk/rp2350/hardware/structs/pads_qspi.h new file mode 100644 index 000000000000..e6b0f68100e8 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/pads_qspi.h @@ -0,0 +1,49 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H +#define _HARDWARE_STRUCTS_PADS_QSPI_H + +/** + * \file rp2350/pads_qspi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pads_qspi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pads_qspi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT + // Voltage select + // 0x00000001 [0] VOLTAGE_SELECT (0) + io_rw_32 voltage_select; + + // (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes) + _REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK + // 0x00000100 [8] ISO (1) Pad isolation control + // 0x00000080 [7] OD (0) Output disable + // 0x00000040 [6] IE (1) Input enable + // 0x00000030 [5:4] DRIVE (0x1) Drive strength + // 0x00000008 [3] PUE (0) Pull up enable + // 0x00000004 [2] PDE (1) Pull down enable + // 0x00000002 [1] SCHMITT (1) Enable schmitt trigger + // 0x00000001 [0] SLEWFAST (0) Slew rate control + io_rw_32 io[6]; +} pads_qspi_hw_t; + +#define pads_qspi_hw ((pads_qspi_hw_t *)PADS_QSPI_BASE) +static_assert(sizeof (pads_qspi_hw_t) == 0x001c, ""); + +#endif // _HARDWARE_STRUCTS_PADS_QSPI_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/padsbank0.h b/lib/pico-sdk/rp2350/hardware/structs/padsbank0.h new file mode 100644 index 000000000000..cb14e792b739 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/padsbank0.h @@ -0,0 +1,9 @@ +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/pads_bank0.h" +#define padsbank0_hw pads_bank0_hw \ No newline at end of file diff --git a/lib/pico-sdk/rp2350/hardware/structs/pio.h b/lib/pico-sdk/rp2350/hardware/structs/pio.h new file mode 100644 index 000000000000..68e5bac08687 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/pio.h @@ -0,0 +1,380 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PIO_H +#define _HARDWARE_STRUCTS_PIO_H + +/** + * \file rp2350/pio.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pio.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV + // Clock divisor register for state machine 0 + + // 0xffff0000 [31:16] INT (0x0001) Effective frequency is sysclk/(int + frac/256) + // 0x0000ff00 [15:8] FRAC (0x00) Fractional part of clock divisor + io_rw_32 clkdiv; + + _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL + // Execution/behavioural settings for state machine 0 + // 0x80000000 [31] EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,... + // 0x40000000 [30] SIDE_EN (0) If 1, the MSB of the Delay/Side-set instruction field is... + // 0x20000000 [29] SIDE_PINDIR (0) If 1, side-set data is asserted to pin directions,... + // 0x1f000000 [28:24] JMP_PIN (0x00) The GPIO number to use as condition for JMP PIN + // 0x00f80000 [23:19] OUT_EN_SEL (0x00) Which data bit to use for inline OUT enable + // 0x00040000 [18] INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable + + // 0x00020000 [17] OUT_STICKY (0) Continuously assert the most recent OUT/SET to the pins + // 0x0001f000 [16:12] WRAP_TOP (0x1f) After reaching this address, execution is wrapped to wrap_bottom + // 0x00000f80 [11:7] WRAP_BOTTOM (0x00) After reaching wrap_top, execution is wrapped to this address + // 0x00000060 [6:5] STATUS_SEL (0x0) Comparison used for the MOV x, STATUS instruction + // 0x0000001f [4:0] STATUS_N (0x00) Comparison level or IRQ index for the MOV x, STATUS instruction + io_rw_32 execctrl; + + _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL + // Control behaviour of the input/output shift registers for state machine 0 + // 0x80000000 [31] FJOIN_RX (0) When 1, RX FIFO steals the TX FIFO's storage, and... + // 0x40000000 [30] FJOIN_TX (0) When 1, TX FIFO steals the RX FIFO's storage, and... + // 0x3e000000 [29:25] PULL_THRESH (0x00) Number of bits shifted out of OSR before autopull, or... + // 0x01f00000 [24:20] PUSH_THRESH (0x00) Number of bits shifted into ISR before autopush, or... + // 0x00080000 [19] OUT_SHIFTDIR (1) 1 = shift out of output shift register to right + // 0x00040000 [18] IN_SHIFTDIR (1) 1 = shift input shift register to right (data enters from left) + // 0x00020000 [17] AUTOPULL (0) Pull automatically when the output shift register is emptied, i + // 0x00010000 [16] AUTOPUSH (0) Push automatically when the input shift register is filled, i + // 0x00008000 [15] FJOIN_RX_PUT (0) If 1, disable this state machine's RX FIFO, make its... + // 0x00004000 [14] FJOIN_RX_GET (0) If 1, disable this state machine's RX FIFO, make its... + // 0x0000001f [4:0] IN_COUNT (0x00) Set the number of pins which are not masked to 0 when... + io_rw_32 shiftctrl; + + _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR + // Current instruction address of state machine 0 + // 0x0000001f [4:0] SM0_ADDR (0x00) + io_ro_32 addr; + + _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR + // Read to see the instruction currently addressed by state machine 0's program counter + + // 0x0000ffff [15:0] SM0_INSTR (-) + io_rw_32 instr; + + _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL + // State machine pin control + // 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction... + // 0x1c000000 [28:26] SET_COUNT (0x5) The number of pins asserted by a SET + // 0x03f00000 [25:20] OUT_COUNT (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS... + // 0x000f8000 [19:15] IN_BASE (0x00) The pin which is mapped to the least-significant bit of... + // 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a... + // 0x000003e0 [9:5] SET_BASE (0x00) The lowest-numbered pin that will be affected by a SET... + // 0x0000001f [4:0] OUT_BASE (0x00) The lowest-numbered pin that will be affected by an OUT... + io_rw_32 pinctrl; +} pio_sm_hw_t; + +typedef struct { + _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00008000 [15] SM7 (0) + // 0x00004000 [14] SM6 (0) + // 0x00002000 [13] SM5 (0) + // 0x00001000 [12] SM4 (0) + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte; + + _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00008000 [15] SM7 (0) + // 0x00004000 [14] SM6 (0) + // 0x00002000 [13] SM5 (0) + // 0x00001000 [12] SM4 (0) + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf; + + _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00008000 [15] SM7 (0) + // 0x00004000 [14] SM6 (0) + // 0x00002000 [13] SM5 (0) + // 0x00001000 [12] SM4 (0) + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints; +} pio_irq_ctrl_hw_t; + +typedef struct { + _REG_(PIO_CTRL_OFFSET) // PIO_CTRL + // PIO control register + // 0x04000000 [26] NEXTPREV_CLKDIV_RESTART (0) Write 1 to restart the clock dividers of state machines... + // 0x02000000 [25] NEXTPREV_SM_DISABLE (0) Write 1 to disable state machines in neighbouring PIO... + // 0x01000000 [24] NEXTPREV_SM_ENABLE (0) Write 1 to enable state machines in neighbouring PIO... + // 0x00f00000 [23:20] NEXT_PIO_MASK (0x0) A mask of state machines in the neighbouring... + // 0x000f0000 [19:16] PREV_PIO_MASK (0x0) A mask of state machines in the neighbouring... + // 0x00000f00 [11:8] CLKDIV_RESTART (0x0) Restart a state machine's clock divider from an initial... + // 0x000000f0 [7:4] SM_RESTART (0x0) Write 1 to instantly clear internal SM state which may... + // 0x0000000f [3:0] SM_ENABLE (0x0) Enable/disable each of the four state machines by... + io_rw_32 ctrl; + + _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT + // FIFO status register + // 0x0f000000 [27:24] TXEMPTY (0xf) State machine TX FIFO is empty + // 0x000f0000 [19:16] TXFULL (0x0) State machine TX FIFO is full + // 0x00000f00 [11:8] RXEMPTY (0xf) State machine RX FIFO is empty + // 0x0000000f [3:0] RXFULL (0x0) State machine RX FIFO is full + io_ro_32 fstat; + + _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG + // FIFO debug register + // 0x0f000000 [27:24] TXSTALL (0x0) State machine has stalled on empty TX FIFO during a... + // 0x000f0000 [19:16] TXOVER (0x0) TX FIFO overflow (i + // 0x00000f00 [11:8] RXUNDER (0x0) RX FIFO underflow (i + // 0x0000000f [3:0] RXSTALL (0x0) State machine has stalled on full RX FIFO during a... + io_rw_32 fdebug; + + _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL + // FIFO levels + // 0xf0000000 [31:28] RX3 (0x0) + // 0x0f000000 [27:24] TX3 (0x0) + // 0x00f00000 [23:20] RX2 (0x0) + // 0x000f0000 [19:16] TX2 (0x0) + // 0x0000f000 [15:12] RX1 (0x0) + // 0x00000f00 [11:8] TX1 (0x0) + // 0x000000f0 [7:4] RX0 (0x0) + // 0x0000000f [3:0] TX0 (0x0) + io_ro_32 flevel; + + // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes) + _REG_(PIO_TXF0_OFFSET) // PIO_TXF0 + // Direct write access to the TX FIFO for this state machine + // 0xffffffff [31:0] TXF0 (0x00000000) + io_wo_32 txf[4]; + + // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes) + _REG_(PIO_RXF0_OFFSET) // PIO_RXF0 + // Direct read access to the RX FIFO for this state machine + // 0xffffffff [31:0] RXF0 (-) + io_ro_32 rxf[4]; + + _REG_(PIO_IRQ_OFFSET) // PIO_IRQ + // State machine IRQ flags register + // 0x000000ff [7:0] IRQ (0x00) + io_rw_32 irq; + + _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE + // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ + // 0x000000ff [7:0] IRQ_FORCE (0x00) + io_wo_32 irq_force; + + _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS + // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities + // 0xffffffff [31:0] INPUT_SYNC_BYPASS (0x00000000) + io_rw_32 input_sync_bypass; + + _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT + // Read to sample the pad output values PIO is currently driving to the GPIOs + // 0xffffffff [31:0] DBG_PADOUT (0x00000000) + io_ro_32 dbg_padout; + + _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE + // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs + // 0xffffffff [31:0] DBG_PADOE (0x00000000) + io_ro_32 dbg_padoe; + + _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO + // The PIO hardware has some free parameters that may vary between chip products + // 0xf0000000 [31:28] VERSION (0x1) Version of the core PIO hardware + // 0x003f0000 [21:16] IMEM_SIZE (-) The size of the instruction memory, measured in units of... + // 0x00000f00 [11:8] SM_COUNT (-) The number of state machines this PIO instance is equipped with + // 0x0000003f [5:0] FIFO_DEPTH (-) The depth of the state machine TX/RX FIFOs, measured in words + io_ro_32 dbg_cfginfo; + + // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes) + _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0 + // Write-only access to instruction memory location 0 + // 0x0000ffff [15:0] INSTR_MEM0 (0x0000) + io_wo_32 instr_mem[32]; + + pio_sm_hw_t sm[4]; + + // (Description copied from array index 0 register PIO_RXF0_PUTGET0 applies similarly to other array indexes) + _REG_(PIO_RXF0_PUTGET0_OFFSET) // PIO_RXF0_PUTGET0 + // Direct read/write access to the RX FIFO on all SMs, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set + // 0xffffffff [31:0] RXF0_PUTGET0 (0x00000000) + io_rw_32 rxf_putget[4][4]; + + _REG_(PIO_GPIOBASE_OFFSET) // PIO_GPIOBASE + // Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32... + // 0x00000010 [4] GPIOBASE (0) + io_rw_32 gpiobase; + + _REG_(PIO_INTR_OFFSET) // PIO_INTR + // Raw Interrupts + // 0x00008000 [15] SM7 (0) + // 0x00004000 [14] SM6 (0) + // 0x00002000 [13] SM5 (0) + // 0x00001000 [12] SM4 (0) + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 intr; + + union { + struct { + _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte0; + + _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf0; + + _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints0; + + _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE + // Interrupt Enable for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 inte1; + + _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF + // Interrupt Force for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_rw_32 intf1; + + _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS + // Interrupt status after masking & forcing for irq1 + // 0x00000800 [11] SM3 (0) + // 0x00000400 [10] SM2 (0) + // 0x00000200 [9] SM1 (0) + // 0x00000100 [8] SM0 (0) + // 0x00000080 [7] SM3_TXNFULL (0) + // 0x00000040 [6] SM2_TXNFULL (0) + // 0x00000020 [5] SM1_TXNFULL (0) + // 0x00000010 [4] SM0_TXNFULL (0) + // 0x00000008 [3] SM3_RXNEMPTY (0) + // 0x00000004 [2] SM2_RXNEMPTY (0) + // 0x00000002 [1] SM1_RXNEMPTY (0) + // 0x00000001 [0] SM0_RXNEMPTY (0) + io_ro_32 ints1; + }; + pio_irq_ctrl_hw_t irq_ctrl[2]; + }; +} pio_hw_t; + +#define pio0_hw ((pio_hw_t *)PIO0_BASE) +#define pio1_hw ((pio_hw_t *)PIO1_BASE) +#define pio2_hw ((pio_hw_t *)PIO2_BASE) +static_assert(sizeof (pio_hw_t) == 0x0188, ""); + +#endif // _HARDWARE_STRUCTS_PIO_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/pll.h b/lib/pico-sdk/rp2350/hardware/structs/pll.h new file mode 100644 index 000000000000..8a7276048d89 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/pll.h @@ -0,0 +1,82 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PLL_H +#define _HARDWARE_STRUCTS_PLL_H + +/** + * \file rp2350/pll.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pll.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pll +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pll.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/// \tag::pll_hw[] +typedef struct { + _REG_(PLL_CS_OFFSET) // PLL_CS + // Control and Status + // 0x80000000 [31] LOCK (0) PLL is locked + // 0x40000000 [30] LOCK_N (0) PLL is not locked + + // 0x00000100 [8] BYPASS (0) Passes the reference clock to the output instead of the... + // 0x0000003f [5:0] REFDIV (0x01) Divides the PLL input reference clock + io_rw_32 cs; + + _REG_(PLL_PWR_OFFSET) // PLL_PWR + // Controls the PLL power modes + // 0x00000020 [5] VCOPD (1) PLL VCO powerdown + + // 0x00000008 [3] POSTDIVPD (1) PLL post divider powerdown + + // 0x00000004 [2] DSMPD (1) PLL DSM powerdown + + // 0x00000001 [0] PD (1) PLL powerdown + + io_rw_32 pwr; + + _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT + // Feedback divisor + // 0x00000fff [11:0] FBDIV_INT (0x000) see ctrl reg description for constraints + io_rw_32 fbdiv_int; + + _REG_(PLL_PRIM_OFFSET) // PLL_PRIM + // Controls the PLL post dividers for the primary output + // 0x00070000 [18:16] POSTDIV1 (0x7) divide by 1-7 + // 0x00007000 [14:12] POSTDIV2 (0x7) divide by 1-7 + io_rw_32 prim; + + _REG_(PLL_INTR_OFFSET) // PLL_INTR + // Raw Interrupts + // 0x00000001 [0] LOCK_N_STICKY (0) + io_rw_32 intr; + + _REG_(PLL_INTE_OFFSET) // PLL_INTE + // Interrupt Enable + // 0x00000001 [0] LOCK_N_STICKY (0) + io_rw_32 inte; + + _REG_(PLL_INTF_OFFSET) // PLL_INTF + // Interrupt Force + // 0x00000001 [0] LOCK_N_STICKY (0) + io_rw_32 intf; + + _REG_(PLL_INTS_OFFSET) // PLL_INTS + // Interrupt status after masking & forcing + // 0x00000001 [0] LOCK_N_STICKY (0) + io_ro_32 ints; +} pll_hw_t; +/// \end::pll_hw[] + +#define pll_sys_hw ((pll_hw_t *)PLL_SYS_BASE) +#define pll_usb_hw ((pll_hw_t *)PLL_USB_BASE) +static_assert(sizeof (pll_hw_t) == 0x0020, ""); + +#endif // _HARDWARE_STRUCTS_PLL_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/powman.h b/lib/pico-sdk/rp2350/hardware/structs/powman.h new file mode 100644 index 000000000000..a81890e3cf52 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/powman.h @@ -0,0 +1,338 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_POWMAN_H +#define _HARDWARE_STRUCTS_POWMAN_H + +/** + * \file rp2350/powman.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/powman.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_powman +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/powman.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(POWMAN_BADPASSWD_OFFSET) // POWMAN_BADPASSWD + // Indicates a bad password has been used + // 0x00000001 [0] BADPASSWD (0) + io_rw_32 badpasswd; + + _REG_(POWMAN_VREG_CTRL_OFFSET) // POWMAN_VREG_CTRL + // Voltage Regulator Control + // 0x00008000 [15] RST_N (1) returns the regulator to its startup settings + + // 0x00002000 [13] UNLOCK (0) unlocks the VREG control interface after power up + + // 0x00001000 [12] ISOLATE (0) isolates the VREG control interface + + // 0x00000100 [8] DISABLE_VOLTAGE_LIMIT (0) 0=not disabled, 1=enabled + // 0x00000070 [6:4] HT_TH (0x5) high temperature protection threshold + + io_rw_32 vreg_ctrl; + + _REG_(POWMAN_VREG_STS_OFFSET) // POWMAN_VREG_STS + // Voltage Regulator Status + // 0x00000010 [4] VOUT_OK (0) output regulation status + + // 0x00000001 [0] STARTUP (0) startup status + + io_ro_32 vreg_sts; + + _REG_(POWMAN_VREG_OFFSET) // POWMAN_VREG + // Voltage Regulator Settings + // 0x00008000 [15] UPDATE_IN_PROGRESS (0) regulator state is being updated + + // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + + // 0x00000002 [1] HIZ (0) high impedance mode select + + io_rw_32 vreg; + + _REG_(POWMAN_VREG_LP_ENTRY_OFFSET) // POWMAN_VREG_LP_ENTRY + // Voltage Regulator Low Power Entry Settings + // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + + // 0x00000004 [2] MODE (1) selects either normal (switching) mode or low power... + // 0x00000002 [1] HIZ (0) high impedance mode select + + io_rw_32 vreg_lp_entry; + + _REG_(POWMAN_VREG_LP_EXIT_OFFSET) // POWMAN_VREG_LP_EXIT + // Voltage Regulator Low Power Exit Settings + // 0x000001f0 [8:4] VSEL (0x0b) output voltage select + + // 0x00000004 [2] MODE (0) selects either normal (switching) mode or low power... + // 0x00000002 [1] HIZ (0) high impedance mode select + + io_rw_32 vreg_lp_exit; + + _REG_(POWMAN_BOD_CTRL_OFFSET) // POWMAN_BOD_CTRL + // Brown-out Detection Control + // 0x00001000 [12] ISOLATE (0) isolates the brown-out detection control interface + + io_rw_32 bod_ctrl; + + _REG_(POWMAN_BOD_OFFSET) // POWMAN_BOD + // Brown-out Detection Settings + // 0x000001f0 [8:4] VSEL (0x0b) threshold select + + // 0x00000001 [0] EN (1) enable brown-out detection + + io_rw_32 bod; + + _REG_(POWMAN_BOD_LP_ENTRY_OFFSET) // POWMAN_BOD_LP_ENTRY + // Brown-out Detection Low Power Entry Settings + // 0x000001f0 [8:4] VSEL (0x0b) threshold select + + // 0x00000001 [0] EN (0) enable brown-out detection + + io_rw_32 bod_lp_entry; + + _REG_(POWMAN_BOD_LP_EXIT_OFFSET) // POWMAN_BOD_LP_EXIT + // Brown-out Detection Low Power Exit Settings + // 0x000001f0 [8:4] VSEL (0x0b) threshold select + + // 0x00000001 [0] EN (1) enable brown-out detection + + io_rw_32 bod_lp_exit; + + _REG_(POWMAN_LPOSC_OFFSET) // POWMAN_LPOSC + // Low power oscillator control register + // 0x000003f0 [9:4] TRIM (0x20) Frequency trim - the trim step is typically 1% of the... + // 0x00000003 [1:0] MODE (0x3) This feature has been removed + io_rw_32 lposc; + + _REG_(POWMAN_CHIP_RESET_OFFSET) // POWMAN_CHIP_RESET + // Chip reset control and status + // 0x10000000 [28] HAD_WATCHDOG_RESET_RSM (0) Last reset was a watchdog timeout which was configured... + // 0x08000000 [27] HAD_HZD_SYS_RESET_REQ (0) Last reset was a system reset from the hazard debugger + + // 0x04000000 [26] HAD_GLITCH_DETECT (0) Last reset was due to a power supply glitch + + // 0x02000000 [25] HAD_SWCORE_PD (0) Last reset was a switched core powerdown + + // 0x01000000 [24] HAD_WATCHDOG_RESET_SWCORE (0) Last reset was a watchdog timeout which was configured... + // 0x00800000 [23] HAD_WATCHDOG_RESET_POWMAN (0) Last reset was a watchdog timeout which was configured... + // 0x00400000 [22] HAD_WATCHDOG_RESET_POWMAN_ASYNC (0) Last reset was a watchdog timeout which was configured... + // 0x00200000 [21] HAD_RESCUE (0) Last reset was a rescue reset from the debugger + + // 0x00080000 [19] HAD_DP_RESET_REQ (0) Last reset was an reset request from the arm debugger + + // 0x00040000 [18] HAD_RUN_LOW (0) Last reset was from the RUN pin + + // 0x00020000 [17] HAD_BOR (0) Last reset was from the brown-out detection block + + // 0x00010000 [16] HAD_POR (0) Last reset was from the power-on reset + + // 0x00000010 [4] RESCUE_FLAG (0) This is set by a rescue reset from the RP-AP + // 0x00000001 [0] DOUBLE_TAP (0) This flag is set by double-tapping RUN + io_rw_32 chip_reset; + + _REG_(POWMAN_WDSEL_OFFSET) // POWMAN_WDSEL + // Allows a watchdog reset to reset the internal state of powman in addition to the power-on state... + // 0x00001000 [12] RESET_RSM (0) If set to 1, a watchdog reset will run the full power-on... + // 0x00000100 [8] RESET_SWCORE (0) If set to 1, a watchdog reset will reset the switched... + // 0x00000010 [4] RESET_POWMAN (0) If set to 1, a watchdog reset will restore powman... + // 0x00000001 [0] RESET_POWMAN_ASYNC (0) If set to 1, a watchdog reset will restore powman... + io_rw_32 wdsel; + + _REG_(POWMAN_SEQ_CFG_OFFSET) // POWMAN_SEQ_CFG + // For configuration of the power sequencer + + // 0x00100000 [20] USING_FAST_POWCK (1) 0 indicates the POWMAN clock is running from the low... + // 0x00020000 [17] USING_BOD_LP (0) Indicates the brown-out detector (BOD) mode + + // 0x00010000 [16] USING_VREG_LP (0) Indicates the voltage regulator (VREG) mode + + // 0x00001000 [12] USE_FAST_POWCK (1) selects the reference clock (clk_ref) as the source of... + // 0x00000100 [8] RUN_LPOSC_IN_LP (1) Set to 0 to stop the low power osc when the... + // 0x00000080 [7] USE_BOD_HP (1) Set to 0 to prevent automatic switching to bod high... + // 0x00000040 [6] USE_BOD_LP (1) Set to 0 to prevent automatic switching to bod low power... + // 0x00000020 [5] USE_VREG_HP (1) Set to 0 to prevent automatic switching to vreg high... + // 0x00000010 [4] USE_VREG_LP (1) Set to 0 to prevent automatic switching to vreg low... + // 0x00000002 [1] HW_PWRUP_SRAM0 (0) Specifies the power state of SRAM0 when powering up... + // 0x00000001 [0] HW_PWRUP_SRAM1 (0) Specifies the power state of SRAM1 when powering up... + io_rw_32 seq_cfg; + + _REG_(POWMAN_STATE_OFFSET) // POWMAN_STATE + // This register controls the power state of the 4 power domains + // 0x00002000 [13] CHANGING (0) + // 0x00001000 [12] WAITING (0) + // 0x00000800 [11] BAD_HW_REQ (0) Bad hardware initiated state request + // 0x00000400 [10] BAD_SW_REQ (0) Bad software initiated state request + // 0x00000200 [9] PWRUP_WHILE_WAITING (0) Request ignored because of a pending pwrup request + // 0x00000100 [8] REQ_IGNORED (0) + // 0x000000f0 [7:4] REQ (0x0) + // 0x0000000f [3:0] CURRENT (0xf) + io_rw_32 state; + + _REG_(POWMAN_POW_FASTDIV_OFFSET) // POWMAN_POW_FASTDIV + // 0x000007ff [10:0] POW_FASTDIV (0x040) divides the POWMAN clock to provide a tick for the delay... + io_rw_32 pow_fastdiv; + + _REG_(POWMAN_POW_DELAY_OFFSET) // POWMAN_POW_DELAY + // power state machine delays + // 0x0000ff00 [15:8] SRAM_STEP (0x20) timing between the sram0 and sram1 power state machine steps + + // 0x000000f0 [7:4] XIP_STEP (0x1) timing between the xip power state machine steps + + // 0x0000000f [3:0] SWCORE_STEP (0x1) timing between the swcore power state machine steps + + io_rw_32 pow_delay; + + // (Description copied from array index 0 register POWMAN_EXT_CTRL0 applies similarly to other array indexes) + _REG_(POWMAN_EXT_CTRL0_OFFSET) // POWMAN_EXT_CTRL0 + // Configures a gpio as a power mode aware control output + // 0x00004000 [14] LP_EXIT_STATE (0) output level when exiting the low power state + // 0x00002000 [13] LP_ENTRY_STATE (0) output level when entering the low power state + // 0x00001000 [12] INIT_STATE (0) + // 0x00000100 [8] INIT (0) + // 0x0000003f [5:0] GPIO_SELECT (0x3f) selects from gpio 0->30 + + io_rw_32 ext_ctrl[2]; + + _REG_(POWMAN_EXT_TIME_REF_OFFSET) // POWMAN_EXT_TIME_REF + // Select a GPIO to use as a time reference, the source can be used to drive the low power clock at... + // 0x00000010 [4] DRIVE_LPCK (0) Use the selected GPIO to drive the 32kHz low power... + // 0x00000003 [1:0] SOURCE_SEL (0x0) 0 -> gpio12 + + io_rw_32 ext_time_ref; + + _REG_(POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET) // POWMAN_LPOSC_FREQ_KHZ_INT + // Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC + // 0x0000003f [5:0] LPOSC_FREQ_KHZ_INT (0x20) Integer component of the LPOSC or GPIO clock source... + io_rw_32 lposc_freq_khz_int; + + _REG_(POWMAN_LPOSC_FREQ_KHZ_FRAC_OFFSET) // POWMAN_LPOSC_FREQ_KHZ_FRAC + // Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC + // 0x0000ffff [15:0] LPOSC_FREQ_KHZ_FRAC (0xc49c) Fractional component of the LPOSC or GPIO clock source... + io_rw_32 lposc_freq_khz_frac; + + _REG_(POWMAN_XOSC_FREQ_KHZ_INT_OFFSET) // POWMAN_XOSC_FREQ_KHZ_INT + // Informs the AON Timer of the integer component of the clock frequency when running off the XOSC + // 0x0000ffff [15:0] XOSC_FREQ_KHZ_INT (0x2ee0) Integer component of the XOSC frequency in kHz + io_rw_32 xosc_freq_khz_int; + + _REG_(POWMAN_XOSC_FREQ_KHZ_FRAC_OFFSET) // POWMAN_XOSC_FREQ_KHZ_FRAC + // Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC + // 0x0000ffff [15:0] XOSC_FREQ_KHZ_FRAC (0x0000) Fractional component of the XOSC frequency in kHz + io_rw_32 xosc_freq_khz_frac; + + _REG_(POWMAN_SET_TIME_63TO48_OFFSET) // POWMAN_SET_TIME_63TO48 + // 0x0000ffff [15:0] SET_TIME_63TO48 (0x0000) For setting the time, do not use for reading the time,... + io_rw_32 set_time_63to48; + + _REG_(POWMAN_SET_TIME_47TO32_OFFSET) // POWMAN_SET_TIME_47TO32 + // 0x0000ffff [15:0] SET_TIME_47TO32 (0x0000) For setting the time, do not use for reading the time,... + io_rw_32 set_time_47to32; + + _REG_(POWMAN_SET_TIME_31TO16_OFFSET) // POWMAN_SET_TIME_31TO16 + // 0x0000ffff [15:0] SET_TIME_31TO16 (0x0000) For setting the time, do not use for reading the time,... + io_rw_32 set_time_31to16; + + _REG_(POWMAN_SET_TIME_15TO0_OFFSET) // POWMAN_SET_TIME_15TO0 + // 0x0000ffff [15:0] SET_TIME_15TO0 (0x0000) For setting the time, do not use for reading the time,... + io_rw_32 set_time_15to0; + + _REG_(POWMAN_READ_TIME_UPPER_OFFSET) // POWMAN_READ_TIME_UPPER + // 0xffffffff [31:0] READ_TIME_UPPER (0x00000000) For reading bits 63:32 of the timer + io_ro_32 read_time_upper; + + _REG_(POWMAN_READ_TIME_LOWER_OFFSET) // POWMAN_READ_TIME_LOWER + // 0xffffffff [31:0] READ_TIME_LOWER (0x00000000) For reading bits 31:0 of the timer + io_ro_32 read_time_lower; + + _REG_(POWMAN_ALARM_TIME_63TO48_OFFSET) // POWMAN_ALARM_TIME_63TO48 + // 0x0000ffff [15:0] ALARM_TIME_63TO48 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 + io_rw_32 alarm_time_63to48; + + _REG_(POWMAN_ALARM_TIME_47TO32_OFFSET) // POWMAN_ALARM_TIME_47TO32 + // 0x0000ffff [15:0] ALARM_TIME_47TO32 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 + io_rw_32 alarm_time_47to32; + + _REG_(POWMAN_ALARM_TIME_31TO16_OFFSET) // POWMAN_ALARM_TIME_31TO16 + // 0x0000ffff [15:0] ALARM_TIME_31TO16 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 + io_rw_32 alarm_time_31to16; + + _REG_(POWMAN_ALARM_TIME_15TO0_OFFSET) // POWMAN_ALARM_TIME_15TO0 + // 0x0000ffff [15:0] ALARM_TIME_15TO0 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0 + io_rw_32 alarm_time_15to0; + + _REG_(POWMAN_TIMER_OFFSET) // POWMAN_TIMER + // 0x00080000 [19] USING_GPIO_1HZ (0) Timer is synchronised to a 1hz gpio source + // 0x00040000 [18] USING_GPIO_1KHZ (0) Timer is running from a 1khz gpio source + // 0x00020000 [17] USING_LPOSC (0) Timer is running from lposc + // 0x00010000 [16] USING_XOSC (0) Timer is running from xosc + // 0x00002000 [13] USE_GPIO_1HZ (0) Selects the gpio source as the reference for the sec counter + // 0x00000400 [10] USE_GPIO_1KHZ (0) switch to gpio as the source of the 1kHz timer tick + // 0x00000200 [9] USE_XOSC (0) switch to xosc as the source of the 1kHz timer tick + // 0x00000100 [8] USE_LPOSC (0) Switch to lposc as the source of the 1kHz timer tick + // 0x00000040 [6] ALARM (0) Alarm has fired + // 0x00000020 [5] PWRUP_ON_ALARM (0) Alarm wakes the chip from low power mode + // 0x00000010 [4] ALARM_ENAB (0) Enables the alarm + // 0x00000004 [2] CLEAR (0) Clears the timer, does not disable the timer and does... + // 0x00000002 [1] RUN (0) Timer enable + // 0x00000001 [0] NONSEC_WRITE (0) Control whether Non-secure software can write to the... + io_rw_32 timer; + + // (Description copied from array index 0 register POWMAN_PWRUP0 applies similarly to other array indexes) + _REG_(POWMAN_PWRUP0_OFFSET) // POWMAN_PWRUP0 + // 4 GPIO powerup events can be configured to wake the chip up from a low power state + // 0x00000400 [10] RAW_STATUS (0) Value of selected gpio pin (only if enable == 1) + // 0x00000200 [9] STATUS (0) Status of gpio wakeup + // 0x00000100 [8] MODE (0) Edge or level detect + // 0x00000080 [7] DIRECTION (0) + // 0x00000040 [6] ENABLE (0) Set to 1 to enable the wakeup source + // 0x0000003f [5:0] SOURCE (0x3f) + io_rw_32 pwrup[4]; + + _REG_(POWMAN_CURRENT_PWRUP_REQ_OFFSET) // POWMAN_CURRENT_PWRUP_REQ + // Indicates current powerup request state + + // 0x0000007f [6:0] CURRENT_PWRUP_REQ (0x00) + io_ro_32 current_pwrup_req; + + _REG_(POWMAN_LAST_SWCORE_PWRUP_OFFSET) // POWMAN_LAST_SWCORE_PWRUP + // Indicates which pwrup source triggered the last switched-core power up + + // 0x0000007f [6:0] LAST_SWCORE_PWRUP (0x00) + io_ro_32 last_swcore_pwrup; + + _REG_(POWMAN_DBG_PWRCFG_OFFSET) // POWMAN_DBG_PWRCFG + // 0x00000001 [0] IGNORE (0) Ignore pwrup req from debugger + io_rw_32 dbg_pwrcfg; + + _REG_(POWMAN_BOOTDIS_OFFSET) // POWMAN_BOOTDIS + // Tell the bootrom to ignore the BOOT0 + // 0x00000002 [1] NEXT (0) This flag always ORs writes into its current contents + // 0x00000001 [0] NOW (0) When powman resets the RSM, the current value of... + io_rw_32 bootdis; + + _REG_(POWMAN_DBGCONFIG_OFFSET) // POWMAN_DBGCONFIG + // 0x0000000f [3:0] DP_INSTID (0x0) Configure DP instance ID for SWD multidrop selection + io_rw_32 dbgconfig; + + // (Description copied from array index 0 register POWMAN_SCRATCH0 applies similarly to other array indexes) + _REG_(POWMAN_SCRATCH0_OFFSET) // POWMAN_SCRATCH0 + // Scratch register + // 0xffffffff [31:0] SCRATCH0 (0x00000000) + io_rw_32 scratch[8]; + + // (Description copied from array index 0 register POWMAN_BOOT0 applies similarly to other array indexes) + _REG_(POWMAN_BOOT0_OFFSET) // POWMAN_BOOT0 + // Scratch register + // 0xffffffff [31:0] BOOT0 (0x00000000) + io_rw_32 boot[4]; + + _REG_(POWMAN_INTR_OFFSET) // POWMAN_INTR + // Raw Interrupts + // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state + // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state + // 0x00000002 [1] TIMER (0) + // 0x00000001 [0] VREG_OUTPUT_LOW (0) + io_rw_32 intr; + + _REG_(POWMAN_INTE_OFFSET) // POWMAN_INTE + // Interrupt Enable + // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state + // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state + // 0x00000002 [1] TIMER (0) + // 0x00000001 [0] VREG_OUTPUT_LOW (0) + io_rw_32 inte; + + _REG_(POWMAN_INTF_OFFSET) // POWMAN_INTF + // Interrupt Force + // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state + // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state + // 0x00000002 [1] TIMER (0) + // 0x00000001 [0] VREG_OUTPUT_LOW (0) + io_rw_32 intf; + + _REG_(POWMAN_INTS_OFFSET) // POWMAN_INTS + // Interrupt status after masking & forcing + // 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state + // 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state + // 0x00000002 [1] TIMER (0) + // 0x00000001 [0] VREG_OUTPUT_LOW (0) + io_ro_32 ints; +} powman_hw_t; + +#define powman_hw ((powman_hw_t *)POWMAN_BASE) +static_assert(sizeof (powman_hw_t) == 0x00f0, ""); + +#endif // _HARDWARE_STRUCTS_POWMAN_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/psm.h b/lib/pico-sdk/rp2350/hardware/structs/psm.h new file mode 100644 index 000000000000..92144ac630cd --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/psm.h @@ -0,0 +1,148 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PSM_H +#define _HARDWARE_STRUCTS_PSM_H + +/** + * \file rp2350/psm.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/psm.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_psm +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/psm.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON + // Force block out of reset (i + // 0x01000000 [24] PROC1 (0) + // 0x00800000 [23] PROC0 (0) + // 0x00400000 [22] ACCESSCTRL (0) + // 0x00200000 [21] SIO (0) + // 0x00100000 [20] XIP (0) + // 0x00080000 [19] SRAM9 (0) + // 0x00040000 [18] SRAM8 (0) + // 0x00020000 [17] SRAM7 (0) + // 0x00010000 [16] SRAM6 (0) + // 0x00008000 [15] SRAM5 (0) + // 0x00004000 [14] SRAM4 (0) + // 0x00002000 [13] SRAM3 (0) + // 0x00001000 [12] SRAM2 (0) + // 0x00000800 [11] SRAM1 (0) + // 0x00000400 [10] SRAM0 (0) + // 0x00000200 [9] BOOTRAM (0) + // 0x00000100 [8] ROM (0) + // 0x00000080 [7] BUSFABRIC (0) + // 0x00000040 [6] PSM_READY (0) + // 0x00000020 [5] CLOCKS (0) + // 0x00000010 [4] RESETS (0) + // 0x00000008 [3] XOSC (0) + // 0x00000004 [2] ROSC (0) + // 0x00000002 [1] OTP (0) + // 0x00000001 [0] PROC_COLD (0) + io_rw_32 frce_on; + + _REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF + // Force into reset (i + // 0x01000000 [24] PROC1 (0) + // 0x00800000 [23] PROC0 (0) + // 0x00400000 [22] ACCESSCTRL (0) + // 0x00200000 [21] SIO (0) + // 0x00100000 [20] XIP (0) + // 0x00080000 [19] SRAM9 (0) + // 0x00040000 [18] SRAM8 (0) + // 0x00020000 [17] SRAM7 (0) + // 0x00010000 [16] SRAM6 (0) + // 0x00008000 [15] SRAM5 (0) + // 0x00004000 [14] SRAM4 (0) + // 0x00002000 [13] SRAM3 (0) + // 0x00001000 [12] SRAM2 (0) + // 0x00000800 [11] SRAM1 (0) + // 0x00000400 [10] SRAM0 (0) + // 0x00000200 [9] BOOTRAM (0) + // 0x00000100 [8] ROM (0) + // 0x00000080 [7] BUSFABRIC (0) + // 0x00000040 [6] PSM_READY (0) + // 0x00000020 [5] CLOCKS (0) + // 0x00000010 [4] RESETS (0) + // 0x00000008 [3] XOSC (0) + // 0x00000004 [2] ROSC (0) + // 0x00000002 [1] OTP (0) + // 0x00000001 [0] PROC_COLD (0) + io_rw_32 frce_off; + + _REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL + // Set to 1 if the watchdog should reset this + // 0x01000000 [24] PROC1 (0) + // 0x00800000 [23] PROC0 (0) + // 0x00400000 [22] ACCESSCTRL (0) + // 0x00200000 [21] SIO (0) + // 0x00100000 [20] XIP (0) + // 0x00080000 [19] SRAM9 (0) + // 0x00040000 [18] SRAM8 (0) + // 0x00020000 [17] SRAM7 (0) + // 0x00010000 [16] SRAM6 (0) + // 0x00008000 [15] SRAM5 (0) + // 0x00004000 [14] SRAM4 (0) + // 0x00002000 [13] SRAM3 (0) + // 0x00001000 [12] SRAM2 (0) + // 0x00000800 [11] SRAM1 (0) + // 0x00000400 [10] SRAM0 (0) + // 0x00000200 [9] BOOTRAM (0) + // 0x00000100 [8] ROM (0) + // 0x00000080 [7] BUSFABRIC (0) + // 0x00000040 [6] PSM_READY (0) + // 0x00000020 [5] CLOCKS (0) + // 0x00000010 [4] RESETS (0) + // 0x00000008 [3] XOSC (0) + // 0x00000004 [2] ROSC (0) + // 0x00000002 [1] OTP (0) + // 0x00000001 [0] PROC_COLD (0) + io_rw_32 wdsel; + + _REG_(PSM_DONE_OFFSET) // PSM_DONE + // Is the subsystem ready? + // 0x01000000 [24] PROC1 (0) + // 0x00800000 [23] PROC0 (0) + // 0x00400000 [22] ACCESSCTRL (0) + // 0x00200000 [21] SIO (0) + // 0x00100000 [20] XIP (0) + // 0x00080000 [19] SRAM9 (0) + // 0x00040000 [18] SRAM8 (0) + // 0x00020000 [17] SRAM7 (0) + // 0x00010000 [16] SRAM6 (0) + // 0x00008000 [15] SRAM5 (0) + // 0x00004000 [14] SRAM4 (0) + // 0x00002000 [13] SRAM3 (0) + // 0x00001000 [12] SRAM2 (0) + // 0x00000800 [11] SRAM1 (0) + // 0x00000400 [10] SRAM0 (0) + // 0x00000200 [9] BOOTRAM (0) + // 0x00000100 [8] ROM (0) + // 0x00000080 [7] BUSFABRIC (0) + // 0x00000040 [6] PSM_READY (0) + // 0x00000020 [5] CLOCKS (0) + // 0x00000010 [4] RESETS (0) + // 0x00000008 [3] XOSC (0) + // 0x00000004 [2] ROSC (0) + // 0x00000002 [1] OTP (0) + // 0x00000001 [0] PROC_COLD (0) + io_ro_32 done; +} psm_hw_t; + +#define psm_hw ((psm_hw_t *)PSM_BASE) +static_assert(sizeof (psm_hw_t) == 0x0010, ""); + +#endif // _HARDWARE_STRUCTS_PSM_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/pwm.h b/lib/pico-sdk/rp2350/hardware/structs/pwm.h new file mode 100644 index 000000000000..be0e24e5dde9 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/pwm.h @@ -0,0 +1,252 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_PWM_H +#define _HARDWARE_STRUCTS_PWM_H + +/** + * \file rp2350/pwm.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/pwm.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pwm +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR + // Control and status register + // 0x00000080 [7] PH_ADV (0) Advance the phase of the counter by 1 count, while it is running + // 0x00000040 [6] PH_RET (0) Retard the phase of the counter by 1 count, while it is running + // 0x00000030 [5:4] DIVMODE (0x0) + // 0x00000008 [3] B_INV (0) Invert output B + // 0x00000004 [2] A_INV (0) Invert output A + // 0x00000002 [1] PH_CORRECT (0) 1: Enable phase-correct modulation + // 0x00000001 [0] EN (0) Enable the PWM channel + io_rw_32 csr; + + _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV + // INT and FRAC form a fixed-point fractional number + // 0x00000ff0 [11:4] INT (0x01) + // 0x0000000f [3:0] FRAC (0x0) + io_rw_32 div; + + _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR + // Direct access to the PWM counter + // 0x0000ffff [15:0] CH0_CTR (0x0000) + io_rw_32 ctr; + + _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC + // Counter compare values + // 0xffff0000 [31:16] B (0x0000) + // 0x0000ffff [15:0] A (0x0000) + io_rw_32 cc; + + _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP + // Counter wrap value + // 0x0000ffff [15:0] CH0_TOP (0xffff) + io_rw_32 top; +} pwm_slice_hw_t; + +typedef struct { + _REG_(PWM_IRQ0_INTE_OFFSET) // PWM_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 inte; + + _REG_(PWM_IRQ0_INTF_OFFSET) // PWM_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intf; + + _REG_(PWM_IRQ0_INTS_OFFSET) // PWM_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_ro_32 ints; +} pwm_irq_ctrl_hw_t; + +typedef struct { + pwm_slice_hw_t slice[12]; + + _REG_(PWM_EN_OFFSET) // PWM_EN + // This register aliases the CSR_EN bits for all channels + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 en; + + _REG_(PWM_INTR_OFFSET) // PWM_INTR + // Raw Interrupts + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intr; + + union { + struct { + _REG_(PWM_IRQ0_INTE_OFFSET) // PWM_IRQ0_INTE + // Interrupt Enable for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 inte; + + _REG_(PWM_IRQ0_INTF_OFFSET) // PWM_IRQ0_INTF + // Interrupt Force for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intf; + + _REG_(PWM_IRQ0_INTS_OFFSET) // PWM_IRQ0_INTS + // Interrupt status after masking & forcing for irq0 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 ints; + + _REG_(PWM_IRQ1_INTE_OFFSET) // PWM_IRQ1_INTE + // Interrupt Enable for irq1 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 inte1; + + _REG_(PWM_IRQ1_INTF_OFFSET) // PWM_IRQ1_INTF + // Interrupt Force for irq1 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 intf1; + + _REG_(PWM_IRQ1_INTS_OFFSET) // PWM_IRQ1_INTS + // Interrupt status after masking & forcing for irq1 + // 0x00000800 [11] CH11 (0) + // 0x00000400 [10] CH10 (0) + // 0x00000200 [9] CH9 (0) + // 0x00000100 [8] CH8 (0) + // 0x00000080 [7] CH7 (0) + // 0x00000040 [6] CH6 (0) + // 0x00000020 [5] CH5 (0) + // 0x00000010 [4] CH4 (0) + // 0x00000008 [3] CH3 (0) + // 0x00000004 [2] CH2 (0) + // 0x00000002 [1] CH1 (0) + // 0x00000001 [0] CH0 (0) + io_rw_32 ints1; + }; + pwm_irq_ctrl_hw_t irq_ctrl[2]; + }; +} pwm_hw_t; + +#define pwm_hw ((pwm_hw_t *)PWM_BASE) +static_assert(sizeof (pwm_hw_t) == 0x0110, ""); + +#endif // _HARDWARE_STRUCTS_PWM_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/qmi.h b/lib/pico-sdk/rp2350/hardware/structs/qmi.h new file mode 100644 index 000000000000..bbcbd7698569 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/qmi.h @@ -0,0 +1,125 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_QMI_H +#define _HARDWARE_STRUCTS_QMI_H + +/** + * \file rp2350/qmi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/qmi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_qmi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/qmi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(QMI_M0_TIMING_OFFSET) // QMI_M0_TIMING + // Timing configuration register for memory address window 0 + // 0xc0000000 [31:30] COOLDOWN (0x1) Chip select cooldown period + // 0x30000000 [29:28] PAGEBREAK (0x0) When page break is enabled, chip select will... + // 0x02000000 [25] SELECT_SETUP (0) Add up to one additional system clock cycle of setup... + // 0x01800000 [24:23] SELECT_HOLD (0x0) Add up to three additional system clock cycles of active... + // 0x007e0000 [22:17] MAX_SELECT (0x00) Enforce a maximum assertion duration for this window's... + // 0x0001f000 [16:12] MIN_DESELECT (0x00) After this window's chip select is deasserted, it... + // 0x00000700 [10:8] RXDELAY (0x0) Delay the read data sample timing, in units of one half... + // 0x000000ff [7:0] CLKDIV (0x04) Clock divisor + io_rw_32 timing; + + _REG_(QMI_M0_RFMT_OFFSET) // QMI_M0_RFMT + // Read transfer format configuration for memory address window 0. + // 0x10000000 [28] DTR (0) Enable double transfer rate (DTR) for read commands:... + // 0x00070000 [18:16] DUMMY_LEN (0x0) Length of dummy phase between command suffix and data... + // 0x0000c000 [15:14] SUFFIX_LEN (0x0) Length of post-address command suffix, in units of 4 bits + // 0x00001000 [12] PREFIX_LEN (1) Length of command prefix, in units of 8 bits + // 0x00000300 [9:8] DATA_WIDTH (0x0) The width used for the data transfer + // 0x000000c0 [7:6] DUMMY_WIDTH (0x0) The width used for the dummy phase, if any + // 0x00000030 [5:4] SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any + // 0x0000000c [3:2] ADDR_WIDTH (0x0) The transfer width used for the address + // 0x00000003 [1:0] PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any + io_rw_32 rfmt; + + _REG_(QMI_M0_RCMD_OFFSET) // QMI_M0_RCMD + // Command constants used for reads from memory address window 0. + // 0x0000ff00 [15:8] SUFFIX (0xa0) The command suffix bits following the address, if... + // 0x000000ff [7:0] PREFIX (0x03) The command prefix bits to prepend on each new transfer,... + io_rw_32 rcmd; + + _REG_(QMI_M0_WFMT_OFFSET) // QMI_M0_WFMT + // Write transfer format configuration for memory address window 0. + // 0x10000000 [28] DTR (0) Enable double transfer rate (DTR) for write commands:... + // 0x00070000 [18:16] DUMMY_LEN (0x0) Length of dummy phase between command suffix and data... + // 0x0000c000 [15:14] SUFFIX_LEN (0x0) Length of post-address command suffix, in units of 4 bits + // 0x00001000 [12] PREFIX_LEN (1) Length of command prefix, in units of 8 bits + // 0x00000300 [9:8] DATA_WIDTH (0x0) The width used for the data transfer + // 0x000000c0 [7:6] DUMMY_WIDTH (0x0) The width used for the dummy phase, if any + // 0x00000030 [5:4] SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any + // 0x0000000c [3:2] ADDR_WIDTH (0x0) The transfer width used for the address + // 0x00000003 [1:0] PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any + io_rw_32 wfmt; + + _REG_(QMI_M0_WCMD_OFFSET) // QMI_M0_WCMD + // Command constants used for writes to memory address window 0. + // 0x0000ff00 [15:8] SUFFIX (0xa0) The command suffix bits following the address, if... + // 0x000000ff [7:0] PREFIX (0x02) The command prefix bits to prepend on each new transfer,... + io_rw_32 wcmd; +} qmi_mem_hw_t; + +typedef struct { + _REG_(QMI_DIRECT_CSR_OFFSET) // QMI_DIRECT_CSR + // Control and status for direct serial mode + // 0xc0000000 [31:30] RXDELAY (0x0) Delay the read data sample timing, in units of one half... + // 0x3fc00000 [29:22] CLKDIV (0x06) Clock divisor for direct serial mode + // 0x001c0000 [20:18] RXLEVEL (0x0) Current level of DIRECT_RX FIFO + // 0x00020000 [17] RXFULL (0) When 1, the DIRECT_RX FIFO is currently full + // 0x00010000 [16] RXEMPTY (0) When 1, the DIRECT_RX FIFO is currently empty + // 0x00007000 [14:12] TXLEVEL (0x0) Current level of DIRECT_TX FIFO + // 0x00000800 [11] TXEMPTY (0) When 1, the DIRECT_TX FIFO is currently empty + // 0x00000400 [10] TXFULL (0) When 1, the DIRECT_TX FIFO is currently full + // 0x00000080 [7] AUTO_CS1N (0) When 1, automatically assert the CS1n chip select line... + // 0x00000040 [6] AUTO_CS0N (0) When 1, automatically assert the CS0n chip select line... + // 0x00000008 [3] ASSERT_CS1N (0) When 1, assert (i + // 0x00000004 [2] ASSERT_CS0N (0) When 1, assert (i + // 0x00000002 [1] BUSY (0) Direct mode busy flag + // 0x00000001 [0] EN (0) Enable direct mode + io_rw_32 direct_csr; + + _REG_(QMI_DIRECT_TX_OFFSET) // QMI_DIRECT_TX + // Transmit FIFO for direct mode + // 0x00100000 [20] NOPUSH (0) Inhibit the RX FIFO push that would correspond to this... + // 0x00080000 [19] OE (0) Output enable (active-high) + // 0x00040000 [18] DWIDTH (0) Data width + // 0x00030000 [17:16] IWIDTH (0x0) Configure whether this FIFO record is transferred with... + // 0x0000ffff [15:0] DATA (0x0000) Data pushed here will be clocked out falling edges of... + io_wo_32 direct_tx; + + _REG_(QMI_DIRECT_RX_OFFSET) // QMI_DIRECT_RX + // Receive FIFO for direct mode + // 0x0000ffff [15:0] DIRECT_RX (0x0000) With each byte clocked out on the serial interface, one... + io_ro_32 direct_rx; + + qmi_mem_hw_t m[2]; + + // (Description copied from array index 0 register QMI_ATRANS0 applies similarly to other array indexes) + _REG_(QMI_ATRANS0_OFFSET) // QMI_ATRANS0 + // Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). + // 0x07ff0000 [26:16] SIZE (0x400) Translation aperture size for this virtual address... + // 0x00000fff [11:0] BASE (0x000) Physical address base for this virtual address range, in... + io_rw_32 atrans[8]; +} qmi_hw_t; + +#define qmi_hw ((qmi_hw_t *)XIP_QMI_BASE) +static_assert(sizeof (qmi_hw_t) == 0x0054, ""); + +#endif // _HARDWARE_STRUCTS_QMI_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/resets.h b/lib/pico-sdk/rp2350/hardware/structs/resets.h new file mode 100644 index 000000000000..5d5d0e6983bf --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/resets.h @@ -0,0 +1,166 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_RESETS_H +#define _HARDWARE_STRUCTS_RESETS_H + +/** + * \file rp2350/resets.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/resets.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_resets +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/resets.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/** \brief Resettable component numbers on RP2350 (used as typedef \ref reset_num_t) + * \ingroup hardware_resets + */ +typedef enum reset_num_rp2350 { + RESET_ADC = 0, ///< Select ADC to be reset + RESET_BUSCTRL = 1, ///< Select BUSCTRL to be reset + RESET_DMA = 2, ///< Select DMA to be reset + RESET_HSTX = 3, ///< Select HSTX to be reset + RESET_I2C0 = 4, ///< Select I2C0 to be reset + RESET_I2C1 = 5, ///< Select I2C1 to be reset + RESET_IO_BANK0 = 6, ///< Select IO_BANK0 to be reset + RESET_IO_QSPI = 7, ///< Select IO_QSPI to be reset + RESET_JTAG = 8, ///< Select JTAG to be reset + RESET_PADS_BANK0 = 9, ///< Select PADS_BANK0 to be reset + RESET_PADS_QSPI = 10, ///< Select PADS_QSPI to be reset + RESET_PIO0 = 11, ///< Select PIO0 to be reset + RESET_PIO1 = 12, ///< Select PIO1 to be reset + RESET_PIO2 = 13, ///< Select PIO2 to be reset + RESET_PLL_SYS = 14, ///< Select PLL_SYS to be reset + RESET_PLL_USB = 15, ///< Select PLL_USB to be reset + RESET_PWM = 16, ///< Select PWM to be reset + RESET_SHA256 = 17, ///< Select SHA256 to be reset + RESET_SPI0 = 18, ///< Select SPI0 to be reset + RESET_SPI1 = 19, ///< Select SPI1 to be reset + RESET_SYSCFG = 20, ///< Select SYSCFG to be reset + RESET_SYSINFO = 21, ///< Select SYSINFO to be reset + RESET_TBMAN = 22, ///< Select TBMAN to be reset + RESET_TIMER0 = 23, ///< Select TIMER0 to be reset + RESET_TIMER1 = 24, ///< Select TIMER1 to be reset + RESET_TRNG = 25, ///< Select TRNG to be reset + RESET_UART0 = 26, ///< Select UART0 to be reset + RESET_UART1 = 27, ///< Select UART1 to be reset + RESET_USBCTRL = 28, ///< Select USBCTRL to be reset + RESET_COUNT +} reset_num_t; + +/// \tag::resets_hw[] +typedef struct { + _REG_(RESETS_RESET_OFFSET) // RESETS_RESET + // 0x10000000 [28] USBCTRL (1) + // 0x08000000 [27] UART1 (1) + // 0x04000000 [26] UART0 (1) + // 0x02000000 [25] TRNG (1) + // 0x01000000 [24] TIMER1 (1) + // 0x00800000 [23] TIMER0 (1) + // 0x00400000 [22] TBMAN (1) + // 0x00200000 [21] SYSINFO (1) + // 0x00100000 [20] SYSCFG (1) + // 0x00080000 [19] SPI1 (1) + // 0x00040000 [18] SPI0 (1) + // 0x00020000 [17] SHA256 (1) + // 0x00010000 [16] PWM (1) + // 0x00008000 [15] PLL_USB (1) + // 0x00004000 [14] PLL_SYS (1) + // 0x00002000 [13] PIO2 (1) + // 0x00001000 [12] PIO1 (1) + // 0x00000800 [11] PIO0 (1) + // 0x00000400 [10] PADS_QSPI (1) + // 0x00000200 [9] PADS_BANK0 (1) + // 0x00000100 [8] JTAG (1) + // 0x00000080 [7] IO_QSPI (1) + // 0x00000040 [6] IO_BANK0 (1) + // 0x00000020 [5] I2C1 (1) + // 0x00000010 [4] I2C0 (1) + // 0x00000008 [3] HSTX (1) + // 0x00000004 [2] DMA (1) + // 0x00000002 [1] BUSCTRL (1) + // 0x00000001 [0] ADC (1) + io_rw_32 reset; + + _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL + // 0x10000000 [28] USBCTRL (0) + // 0x08000000 [27] UART1 (0) + // 0x04000000 [26] UART0 (0) + // 0x02000000 [25] TRNG (0) + // 0x01000000 [24] TIMER1 (0) + // 0x00800000 [23] TIMER0 (0) + // 0x00400000 [22] TBMAN (0) + // 0x00200000 [21] SYSINFO (0) + // 0x00100000 [20] SYSCFG (0) + // 0x00080000 [19] SPI1 (0) + // 0x00040000 [18] SPI0 (0) + // 0x00020000 [17] SHA256 (0) + // 0x00010000 [16] PWM (0) + // 0x00008000 [15] PLL_USB (0) + // 0x00004000 [14] PLL_SYS (0) + // 0x00002000 [13] PIO2 (0) + // 0x00001000 [12] PIO1 (0) + // 0x00000800 [11] PIO0 (0) + // 0x00000400 [10] PADS_QSPI (0) + // 0x00000200 [9] PADS_BANK0 (0) + // 0x00000100 [8] JTAG (0) + // 0x00000080 [7] IO_QSPI (0) + // 0x00000040 [6] IO_BANK0 (0) + // 0x00000020 [5] I2C1 (0) + // 0x00000010 [4] I2C0 (0) + // 0x00000008 [3] HSTX (0) + // 0x00000004 [2] DMA (0) + // 0x00000002 [1] BUSCTRL (0) + // 0x00000001 [0] ADC (0) + io_rw_32 wdsel; + + _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE + // 0x10000000 [28] USBCTRL (0) + // 0x08000000 [27] UART1 (0) + // 0x04000000 [26] UART0 (0) + // 0x02000000 [25] TRNG (0) + // 0x01000000 [24] TIMER1 (0) + // 0x00800000 [23] TIMER0 (0) + // 0x00400000 [22] TBMAN (0) + // 0x00200000 [21] SYSINFO (0) + // 0x00100000 [20] SYSCFG (0) + // 0x00080000 [19] SPI1 (0) + // 0x00040000 [18] SPI0 (0) + // 0x00020000 [17] SHA256 (0) + // 0x00010000 [16] PWM (0) + // 0x00008000 [15] PLL_USB (0) + // 0x00004000 [14] PLL_SYS (0) + // 0x00002000 [13] PIO2 (0) + // 0x00001000 [12] PIO1 (0) + // 0x00000800 [11] PIO0 (0) + // 0x00000400 [10] PADS_QSPI (0) + // 0x00000200 [9] PADS_BANK0 (0) + // 0x00000100 [8] JTAG (0) + // 0x00000080 [7] IO_QSPI (0) + // 0x00000040 [6] IO_BANK0 (0) + // 0x00000020 [5] I2C1 (0) + // 0x00000010 [4] I2C0 (0) + // 0x00000008 [3] HSTX (0) + // 0x00000004 [2] DMA (0) + // 0x00000002 [1] BUSCTRL (0) + // 0x00000001 [0] ADC (0) + io_ro_32 reset_done; +} resets_hw_t; +/// \end::resets_hw[] + +#define resets_hw ((resets_hw_t *)RESETS_BASE) +static_assert(sizeof (resets_hw_t) == 0x000c, ""); + +#endif // _HARDWARE_STRUCTS_RESETS_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/rosc.h b/lib/pico-sdk/rp2350/hardware/structs/rosc.h new file mode 100644 index 000000000000..73503cc15572 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/rosc.h @@ -0,0 +1,99 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_ROSC_H +#define _HARDWARE_STRUCTS_ROSC_H + +/** + * \file rp2350/rosc.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/rosc.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_rosc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL + // Ring Oscillator control + // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to ENABLE + + // 0x00000fff [11:0] FREQ_RANGE (0xaa0) Controls the number of delay stages in the ROSC ring + + io_rw_32 ctrl; + + _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA + // Ring Oscillator frequency control A + // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings + + // 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength + // 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength + // 0x00000080 [7] DS1_RANDOM (0) Randomises the stage 1 drive strength + // 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength + // 0x00000008 [3] DS0_RANDOM (0) Randomises the stage 0 drive strength + // 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength + io_rw_32 freqa; + + _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB + // Ring Oscillator frequency control B + // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings + + // 0x00007000 [14:12] DS7 (0x0) Stage 7 drive strength + // 0x00000700 [10:8] DS6 (0x0) Stage 6 drive strength + // 0x00000070 [6:4] DS5 (0x0) Stage 5 drive strength + // 0x00000007 [2:0] DS4 (0x0) Stage 4 drive strength + io_rw_32 freqb; + + _REG_(ROSC_RANDOM_OFFSET) // ROSC_RANDOM + // Loads a value to the LFSR randomiser + // 0xffffffff [31:0] SEED (0x3f04b16d) + io_rw_32 random; + + _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT + // Ring Oscillator pause control + // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the ROSC + + io_rw_32 dormant; + + _REG_(ROSC_DIV_OFFSET) // ROSC_DIV + // Controls the output divider + // 0x0000ffff [15:0] DIV (-) set to 0xaa00 + div where + + io_rw_32 div; + + _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE + // Controls the phase shifted output + // 0x00000ff0 [11:4] PASSWD (0x00) set to 0xaa + + // 0x00000008 [3] ENABLE (1) enable the phase-shifted output + + // 0x00000004 [2] FLIP (0) invert the phase-shifted output + + // 0x00000003 [1:0] SHIFT (0x0) phase shift the phase-shifted output by SHIFT input clocks + + io_rw_32 phase; + + _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS + // Ring Oscillator Status + // 0x80000000 [31] STABLE (0) Oscillator is running and stable + // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or... + // 0x00010000 [16] DIV_RUNNING (-) post-divider is running + + // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and stable + + io_rw_32 status; + + _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT + // Returns a 1 bit random value + // 0x00000001 [0] RANDOMBIT (1) + io_ro_32 randombit; + + _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT + // A down counter running at the ROSC frequency which counts to zero and stops. + // 0x0000ffff [15:0] COUNT (0x0000) + io_rw_32 count; +} rosc_hw_t; + +#define rosc_hw ((rosc_hw_t *)ROSC_BASE) +static_assert(sizeof (rosc_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_ROSC_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/sau.h b/lib/pico-sdk/rp2350/hardware/structs/sau.h new file mode 100644 index 000000000000..803f35637d1d --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/sau.h @@ -0,0 +1,65 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SAU_H +#define _HARDWARE_STRUCTS_SAU_H + +/** + * \file rp2350/sau.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + _REG_(M33_SAU_CTRL_OFFSET) // M33_SAU_CTRL + // Allows enabling of the Security Attribution Unit + // 0x00000002 [1] ALLNS (0) When SAU_CTRL + // 0x00000001 [0] ENABLE (0) Enables the SAU + io_rw_32 ctrl; + + _REG_(M33_SAU_TYPE_OFFSET) // M33_SAU_TYPE + // Indicates the number of regions implemented by the Security Attribution Unit + // 0x000000ff [7:0] SREGION (0x08) The number of implemented SAU regions + io_ro_32 type; + + _REG_(M33_SAU_RNR_OFFSET) // M33_SAU_RNR + // Selects the region currently accessed by SAU_RBAR and SAU_RLAR + // 0x000000ff [7:0] REGION (0x00) Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR + io_rw_32 rnr; + + _REG_(M33_SAU_RBAR_OFFSET) // M33_SAU_RBAR + // Provides indirect read and write access to the base address of the currently selected SAU region + // 0xffffffe0 [31:5] BADDR (0x0000000) Holds bits [31:5] of the base address for the selected SAU region + io_rw_32 rbar; + + _REG_(M33_SAU_RLAR_OFFSET) // M33_SAU_RLAR + // Provides indirect read and write access to the limit address of the currently selected SAU region + // 0xffffffe0 [31:5] LADDR (0x0000000) Holds bits [31:5] of the limit address for the selected... + // 0x00000002 [1] NSC (0) Controls whether Non-secure state is permitted to... + // 0x00000001 [0] ENABLE (0) SAU region enable + io_rw_32 rlar; +} armv8m_sau_hw_t; + +#define sau_hw ((armv8m_sau_hw_t *)(PPB_BASE + M33_SAU_CTRL_OFFSET)) +#define sau_ns_hw ((armv8m_sau_hw_t *)(PPB_NONSEC_BASE + M33_SAU_CTRL_OFFSET)) +static_assert(sizeof (armv8m_sau_hw_t) == 0x0014, ""); + +#endif // _HARDWARE_STRUCTS_SAU_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/scb.h b/lib/pico-sdk/rp2350/hardware/structs/scb.h new file mode 100644 index 000000000000..9777023dc9df --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/scb.h @@ -0,0 +1,264 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SCB_H +#define _HARDWARE_STRUCTS_SCB_H + +/** + * \file rp2350/scb.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + _REG_(M33_CPUID_OFFSET) // M33_CPUID + // Provides identification information for the PE, including an implementer code for the device and... + // 0xff000000 [31:24] IMPLEMENTER (0x41) This field must hold an implementer code that has been... + // 0x00f00000 [23:20] VARIANT (0x1) IMPLEMENTATION DEFINED variant number + // 0x000f0000 [19:16] ARCHITECTURE (0xf) Defines the Architecture implemented by the PE + // 0x0000fff0 [15:4] PARTNO (0xd21) IMPLEMENTATION DEFINED primary part number for the device + // 0x0000000f [3:0] REVISION (0x0) IMPLEMENTATION DEFINED revision number for the device + io_ro_32 cpuid; + + _REG_(M33_ICSR_OFFSET) // M33_ICSR + // Controls and provides status information for NMI, PendSV, SysTick and interrupts + // 0x80000000 [31] PENDNMISET (0) Indicates whether the NMI exception is pending + // 0x40000000 [30] PENDNMICLR (0) Allows the NMI exception pend state to be cleared + // 0x10000000 [28] PENDSVSET (0) Indicates whether the PendSV `FTSSS exception is pending + // 0x08000000 [27] PENDSVCLR (0) Allows the PendSV exception pend state to be cleared `FTSSS + // 0x04000000 [26] PENDSTSET (0) Indicates whether the SysTick `FTSSS exception is pending + // 0x02000000 [25] PENDSTCLR (0) Allows the SysTick exception pend state to be cleared `FTSSS + // 0x01000000 [24] STTNS (0) Controls whether in a single SysTick implementation, the... + // 0x00800000 [23] ISRPREEMPT (0) Indicates whether a pending exception will be serviced... + // 0x00400000 [22] ISRPENDING (0) Indicates whether an external interrupt, generated by... + // 0x001ff000 [20:12] VECTPENDING (0x000) The exception number of the highest priority pending and... + // 0x00000800 [11] RETTOBASE (0) In Handler mode, indicates whether there is more than... + // 0x000001ff [8:0] VECTACTIVE (0x000) The exception number of the current executing exception + io_rw_32 icsr; + + _REG_(M33_VTOR_OFFSET) // M33_VTOR + // Vector Table Offset Register + // 0xffffff80 [31:7] TBLOFF (0x0000000) Vector table base offset field + io_rw_32 vtor; + + _REG_(M33_AIRCR_OFFSET) // M33_AIRCR + // Application Interrupt and Reset Control Register + // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + + // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + + // 0x00004000 [14] PRIS (0) Prioritize Secure exceptions + // 0x00002000 [13] BFHFNMINS (0) BusFault, HardFault, and NMI Non-secure enable + // 0x00000700 [10:8] PRIGROUP (0x0) Interrupt priority grouping field + // 0x00000008 [3] SYSRESETREQS (0) System reset request, Secure state only + // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... + // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... + io_rw_32 aircr; + + _REG_(M33_SCR_OFFSET) // M33_SCR + // System Control Register + // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + + // 0x00000008 [3] SLEEPDEEPS (0) 0 SLEEPDEEP is available to both security states + + // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... + // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... + io_rw_32 scr; + + _REG_(M33_CCR_OFFSET) // M33_CCR + // Sets or returns configuration and control data + // 0x00040000 [18] BP (0) Enables program flow prediction `FTSSS + // 0x00020000 [17] IC (0) This is a global enable bit for instruction caches in... + // 0x00010000 [16] DC (0) Enables data caching of all data accesses to Normal memory `FTSSS + // 0x00000400 [10] STKOFHFNMIGN (0) Controls the effect of a stack limit violation while... + // 0x00000200 [9] RES1 (1) Reserved, RES1 + // 0x00000100 [8] BFHFNMIGN (0) Determines the effect of precise BusFaults on handlers... + // 0x00000010 [4] DIV_0_TRP (0) Controls the generation of a DIVBYZERO UsageFault when... + // 0x00000008 [3] UNALIGN_TRP (0) Controls the trapping of unaligned word or halfword accesses + // 0x00000002 [1] USERSETMPEND (0) Determines whether unprivileged accesses are permitted... + // 0x00000001 [0] RES1_1 (1) Reserved, RES1 + io_rw_32 ccr; + + // (Description copied from array index 0 register M33_SHPR1 applies similarly to other array indexes) + _REG_(M33_SHPR1_OFFSET) // M33_SHPR1 + // Sets or returns priority for system handlers 4 - 7 + // 0xe0000000 [31:29] PRI_7_3 (0x0) Priority of system handler 7, SecureFault + // 0x00e00000 [23:21] PRI_6_3 (0x0) Priority of system handler 6, SecureFault + // 0x0000e000 [15:13] PRI_5_3 (0x0) Priority of system handler 5, SecureFault + // 0x000000e0 [7:5] PRI_4_3 (0x0) Priority of system handler 4, SecureFault + io_rw_32 shpr[3]; + + _REG_(M33_SHCSR_OFFSET) // M33_SHCSR + // Provides access to the active and pending status of system exceptions + // 0x00200000 [21] HARDFAULTPENDED (0) `IAAMO the pending state of the HardFault exception `CTTSSS + // 0x00100000 [20] SECUREFAULTPENDED (0) `IAAMO the pending state of the SecureFault exception + // 0x00080000 [19] SECUREFAULTENA (0) `DW the SecureFault exception is enabled + // 0x00040000 [18] USGFAULTENA (0) `DW the UsageFault exception is enabled `FTSSS + // 0x00020000 [17] BUSFAULTENA (0) `DW the BusFault exception is enabled + // 0x00010000 [16] MEMFAULTENA (0) `DW the MemManage exception is enabled `FTSSS + // 0x00008000 [15] SVCALLPENDED (0) `IAAMO the pending state of the SVCall exception `FTSSS + // 0x00004000 [14] BUSFAULTPENDED (0) `IAAMO the pending state of the BusFault exception + // 0x00002000 [13] MEMFAULTPENDED (0) `IAAMO the pending state of the MemManage exception `FTSSS + // 0x00001000 [12] USGFAULTPENDED (0) The UsageFault exception is banked between Security... + // 0x00000800 [11] SYSTICKACT (0) `IAAMO the active state of the SysTick exception `FTSSS + // 0x00000400 [10] PENDSVACT (0) `IAAMO the active state of the PendSV exception `FTSSS + // 0x00000100 [8] MONITORACT (0) `IAAMO the active state of the DebugMonitor exception + // 0x00000080 [7] SVCALLACT (0) `IAAMO the active state of the SVCall exception `FTSSS + // 0x00000020 [5] NMIACT (0) `IAAMO the active state of the NMI exception + // 0x00000010 [4] SECUREFAULTACT (0) `IAAMO the active state of the SecureFault exception + // 0x00000008 [3] USGFAULTACT (0) `IAAMO the active state of the UsageFault exception `FTSSS + // 0x00000004 [2] HARDFAULTACT (0) Indicates and allows limited modification of the active... + // 0x00000002 [1] BUSFAULTACT (0) `IAAMO the active state of the BusFault exception + // 0x00000001 [0] MEMFAULTACT (0) `IAAMO the active state of the MemManage exception `FTSSS + io_rw_32 shcsr; + + _REG_(M33_CFSR_OFFSET) // M33_CFSR + // Contains the three Configurable Fault Status Registers + // 0x02000000 [25] UFSR_DIVBYZERO (0) Sticky flag indicating whether an integer division by... + // 0x01000000 [24] UFSR_UNALIGNED (0) Sticky flag indicating whether an unaligned access error... + // 0x00100000 [20] UFSR_STKOF (0) Sticky flag indicating whether a stack overflow error... + // 0x00080000 [19] UFSR_NOCP (0) Sticky flag indicating whether a coprocessor disabled or... + // 0x00040000 [18] UFSR_INVPC (0) Sticky flag indicating whether an integrity check error... + // 0x00020000 [17] UFSR_INVSTATE (0) Sticky flag indicating whether an EPSR + // 0x00010000 [16] UFSR_UNDEFINSTR (0) Sticky flag indicating whether an undefined instruction... + // 0x00008000 [15] BFSR_BFARVALID (0) Indicates validity of the contents of the BFAR register + // 0x00002000 [13] BFSR_LSPERR (0) Records whether a BusFault occurred during FP lazy state... + // 0x00001000 [12] BFSR_STKERR (0) Records whether a derived BusFault occurred during... + // 0x00000800 [11] BFSR_UNSTKERR (0) Records whether a derived BusFault occurred during... + // 0x00000400 [10] BFSR_IMPRECISERR (0) Records whether an imprecise data access error has occurred + // 0x00000200 [9] BFSR_PRECISERR (0) Records whether a precise data access error has occurred + // 0x00000100 [8] BFSR_IBUSERR (0) Records whether a BusFault on an instruction prefetch... + // 0x000000ff [7:0] MMFSR (0x00) Provides information on MemManage exceptions + io_rw_32 cfsr; + + _REG_(M33_HFSR_OFFSET) // M33_HFSR + // Shows the cause of any HardFaults + // 0x80000000 [31] DEBUGEVT (0) Indicates when a Debug event has occurred + // 0x40000000 [30] FORCED (0) Indicates that a fault with configurable priority has... + // 0x00000002 [1] VECTTBL (0) Indicates when a fault has occurred because of a vector... + io_rw_32 hfsr; + + _REG_(M33_DFSR_OFFSET) // M33_DFSR + // Shows which debug event occurred + // 0x00000010 [4] EXTERNAL (0) Sticky flag indicating whether an External debug request... + // 0x00000008 [3] VCATCH (0) Sticky flag indicating whether a Vector catch debug... + // 0x00000004 [2] DWTTRAP (0) Sticky flag indicating whether a Watchpoint debug event... + // 0x00000002 [1] BKPT (0) Sticky flag indicating whether a Breakpoint debug event... + // 0x00000001 [0] HALTED (0) Sticky flag indicating that a Halt request debug event... + io_rw_32 dfsr; + + _REG_(M33_MMFAR_OFFSET) // M33_MMFAR + // Shows the address of the memory location that caused an MPU fault + // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... + io_rw_32 mmfar; + + _REG_(M33_BFAR_OFFSET) // M33_BFAR + // Shows the address associated with a precise data access BusFault + // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... + io_rw_32 bfar; + + uint32_t _pad0; + + // (Description copied from array index 0 register M33_ID_PFR0 applies similarly to other array indexes) + _REG_(M33_ID_PFR0_OFFSET) // M33_ID_PFR0 + // Gives top-level information about the instruction set supported by the PE + // 0x000000f0 [7:4] STATE1 (0x3) T32 instruction set support + // 0x0000000f [3:0] STATE0 (0x0) A32 instruction set support + io_ro_32 id_pfr[2]; + + _REG_(M33_ID_DFR0_OFFSET) // M33_ID_DFR0 + // Provides top level information about the debug system + // 0x00f00000 [23:20] MPROFDBG (0x2) Indicates the supported M-profile debug architecture + io_ro_32 id_dfr0; + + _REG_(M33_ID_AFR0_OFFSET) // M33_ID_AFR0 + // Provides information about the IMPLEMENTATION DEFINED features of the PE + // 0x0000f000 [15:12] IMPDEF3 (0x0) IMPLEMENTATION DEFINED meaning + // 0x00000f00 [11:8] IMPDEF2 (0x0) IMPLEMENTATION DEFINED meaning + // 0x000000f0 [7:4] IMPDEF1 (0x0) IMPLEMENTATION DEFINED meaning + // 0x0000000f [3:0] IMPDEF0 (0x0) IMPLEMENTATION DEFINED meaning + io_ro_32 id_afr0; + + // (Description copied from array index 0 register M33_ID_MMFR0 applies similarly to other array indexes) + _REG_(M33_ID_MMFR0_OFFSET) // M33_ID_MMFR0 + // Provides information about the implemented memory model and memory management support + // 0x00f00000 [23:20] AUXREG (0x1) Indicates support for Auxiliary Control Registers + // 0x000f0000 [19:16] TCM (0x0) Indicates support for tightly coupled memories (TCMs) + // 0x0000f000 [15:12] SHARELVL (0x1) Indicates the number of shareability levels implemented + // 0x00000f00 [11:8] OUTERSHR (0xf) Indicates the outermost shareability domain implemented + // 0x000000f0 [7:4] PMSA (0x4) Indicates support for the protected memory system... + io_ro_32 id_mmfr[4]; + + // (Description copied from array index 0 register M33_ID_ISAR0 applies similarly to other array indexes) + _REG_(M33_ID_ISAR0_OFFSET) // M33_ID_ISAR0 + // Provides information about the instruction set implemented by the PE + // 0x0f000000 [27:24] DIVIDE (0x8) Indicates the supported Divide instructions + // 0x00f00000 [23:20] DEBUG (0x0) Indicates the implemented Debug instructions + // 0x000f0000 [19:16] COPROC (0x9) Indicates the supported Coprocessor instructions + // 0x0000f000 [15:12] CMPBRANCH (0x2) Indicates the supported combined Compare and Branch instructions + // 0x00000f00 [11:8] BITFIELD (0x3) Indicates the supported bit field instructions + // 0x000000f0 [7:4] BITCOUNT (0x0) Indicates the supported bit count instructions + io_ro_32 id_isar[6]; + + uint32_t _pad1; + + _REG_(M33_CTR_OFFSET) // M33_CTR + // Provides information about the architecture of the caches + // 0x80000000 [31] RES1 (1) Reserved, RES1 + // 0x0f000000 [27:24] CWG (0x0) Log2 of the number of words of the maximum size of... + // 0x00f00000 [23:20] ERG (0x0) Log2 of the number of words of the maximum size of the... + // 0x000f0000 [19:16] DMINLINE (0x0) Log2 of the number of words in the smallest cache line... + // 0x0000c000 [15:14] RES1_1 (0x3) Reserved, RES1 + // 0x0000000f [3:0] IMINLINE (0x0) Log2 of the number of words in the smallest cache line... + io_ro_32 ctr; + + uint32_t _pad2[2]; + + _REG_(M33_CPACR_OFFSET) // M33_CPACR + // Specifies the access privileges for coprocessors and the FP Extension + // 0x00c00000 [23:22] CP11 (0x0) The value in this field is ignored + // 0x00300000 [21:20] CP10 (0x0) Defines the access rights for the floating-point functionality + // 0x0000c000 [15:14] CP7 (0x0) Controls access privileges for coprocessor 7 + // 0x00003000 [13:12] CP6 (0x0) Controls access privileges for coprocessor 6 + // 0x00000c00 [11:10] CP5 (0x0) Controls access privileges for coprocessor 5 + // 0x00000300 [9:8] CP4 (0x0) Controls access privileges for coprocessor 4 + // 0x000000c0 [7:6] CP3 (0x0) Controls access privileges for coprocessor 3 + // 0x00000030 [5:4] CP2 (0x0) Controls access privileges for coprocessor 2 + // 0x0000000c [3:2] CP1 (0x0) Controls access privileges for coprocessor 1 + // 0x00000003 [1:0] CP0 (0x0) Controls access privileges for coprocessor 0 + io_rw_32 cpacr; + + _REG_(M33_NSACR_OFFSET) // M33_NSACR + // Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 + // 0x00000800 [11] CP11 (0) Enables Non-secure access to the Floating-point Extension + // 0x00000400 [10] CP10 (0) Enables Non-secure access to the Floating-point Extension + // 0x00000080 [7] CP7 (0) Enables Non-secure access to coprocessor CP7 + // 0x00000040 [6] CP6 (0) Enables Non-secure access to coprocessor CP6 + // 0x00000020 [5] CP5 (0) Enables Non-secure access to coprocessor CP5 + // 0x00000010 [4] CP4 (0) Enables Non-secure access to coprocessor CP4 + // 0x00000008 [3] CP3 (0) Enables Non-secure access to coprocessor CP3 + // 0x00000004 [2] CP2 (0) Enables Non-secure access to coprocessor CP2 + // 0x00000002 [1] CP1 (0) Enables Non-secure access to coprocessor CP1 + // 0x00000001 [0] CP0 (0) Enables Non-secure access to coprocessor CP0 + io_rw_32 nsacr; +} armv8m_scb_hw_t; + +#define scb_hw ((armv8m_scb_hw_t *)(PPB_BASE + M33_CPUID_OFFSET)) +#define scb_ns_hw ((armv8m_scb_hw_t *)(PPB_NONSEC_BASE + M33_CPUID_OFFSET)) +static_assert(sizeof (armv8m_scb_hw_t) == 0x0090, ""); + +#endif // _HARDWARE_STRUCTS_SCB_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/sha256.h b/lib/pico-sdk/rp2350/hardware/structs/sha256.h new file mode 100644 index 000000000000..248a00ab4b73 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/sha256.h @@ -0,0 +1,53 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SHA256_H +#define _HARDWARE_STRUCTS_SHA256_H + +/** + * \file rp2350/sha256.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sha256.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sha256 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sha256.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SHA256_CSR_OFFSET) // SHA256_CSR + // Control and status register + // 0x00001000 [12] BSWAP (1) Enable byte swapping of 32-bit values at the point they... + // 0x00000300 [9:8] DMA_SIZE (0x2) Configure DREQ logic for the correct DMA data size + // 0x00000010 [4] ERR_WDATA_NOT_RDY (0) Set when a write occurs whilst the SHA-256 core is not... + // 0x00000004 [2] SUM_VLD (1) If 1, the SHA-256 checksum presented in registers SUM0... + // 0x00000002 [1] WDATA_RDY (1) If 1, the SHA-256 core is ready to accept more data... + // 0x00000001 [0] START (0) Write 1 to prepare the SHA-256 core for a new checksum + io_rw_32 csr; + + _REG_(SHA256_WDATA_OFFSET) // SHA256_WDATA + // Write data register + // 0xffffffff [31:0] WDATA (0x00000000) After pulsing START and writing 16 words of data to this... + io_wo_32 wdata; + + // (Description copied from array index 0 register SHA256_SUM0 applies similarly to other array indexes) + _REG_(SHA256_SUM0_OFFSET) // SHA256_SUM0 + // 256-bit checksum result + // 0xffffffff [31:0] SUM0 (0x00000000) + io_ro_32 sum[8]; +} sha256_hw_t; + +#define sha256_hw ((sha256_hw_t *)SHA256_BASE) +static_assert(sizeof (sha256_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_SHA256_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/sio.h b/lib/pico-sdk/rp2350/hardware/structs/sio.h new file mode 100644 index 000000000000..49a452c8adb2 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/sio.h @@ -0,0 +1,336 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SIO_H +#define _HARDWARE_STRUCTS_SIO_H + +/** + * \file rp2350/sio.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" +#include "hardware/structs/interp.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + + +typedef struct { + _REG_(SIO_CPUID_OFFSET) // SIO_CPUID + // Processor core identifier + // 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when... + io_ro_32 cpuid; + + _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN + // Input value for GPIO0 + // 0xffffffff [31:0] GPIO_IN (0x00000000) + io_ro_32 gpio_in; + + _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN + // Input value on GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + // 0x08000000 [27] QSPI_CSN (0) Input value on QSPI CSn pin + // 0x04000000 [26] QSPI_SCK (0) Input value on QSPI SCK pin + // 0x02000000 [25] USB_DM (0) Input value on USB D- pin + // 0x01000000 [24] USB_DP (0) Input value on USB D+ pin + // 0x0000ffff [15:0] GPIO (0x0000) Input value on GPIO32 + io_ro_32 gpio_hi_in; + + uint32_t _pad0; + + _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT + // GPIO0 + // 0xffffffff [31:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0 + io_rw_32 gpio_out; + + _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT + // Output value for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins + // 0x08000000 [27] QSPI_CSN (0) Output value for QSPI CSn pin + // 0x04000000 [26] QSPI_SCK (0) Output value for QSPI SCK pin + // 0x02000000 [25] USB_DM (0) Output value for USB D- pin + // 0x01000000 [24] USB_DP (0) Output value for USB D+ pin + // 0x0000ffff [15:0] GPIO (0x0000) Output value for GPIO32 + io_rw_32 gpio_hi_out; + + _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET + // GPIO0 + // 0xffffffff [31:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i + io_wo_32 gpio_set; + + _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET + // Output value set for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_set; + + _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR + // GPIO0 + // 0xffffffff [31:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i + io_wo_32 gpio_clr; + + _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR + // Output value clear for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_clr; + + _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR + // GPIO0 + // 0xffffffff [31:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i + io_wo_32 gpio_togl; + + _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR + // Output value XOR for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_togl; + + _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE + // GPIO0 + // 0xffffffff [31:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0 + io_rw_32 gpio_oe; + + _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE + // Output enable value for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2... + // 0x08000000 [27] QSPI_CSN (0) Output enable value for QSPI CSn pin + // 0x04000000 [26] QSPI_SCK (0) Output enable value for QSPI SCK pin + // 0x02000000 [25] USB_DM (0) Output enable value for USB D- pin + // 0x01000000 [24] USB_DP (0) Output enable value for USB D+ pin + // 0x0000ffff [15:0] GPIO (0x0000) Output enable value for GPIO32 + io_rw_32 gpio_hi_oe; + + _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET + // GPIO0 + // 0xffffffff [31:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i + io_wo_32 gpio_oe_set; + + _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET + // Output enable set for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_oe_set; + + _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR + // GPIO0 + // 0xffffffff [31:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i + io_wo_32 gpio_oe_clr; + + _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR + // Output enable clear for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_oe_clr; + + _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR + // GPIO0 + // 0xffffffff [31:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i + io_wo_32 gpio_oe_togl; + + _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR + // Output enable XOR for GPIO32 + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_wo_32 gpio_hi_oe_togl; + + _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST + // Status register for inter-core FIFOs (mailboxes). + // 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty + // 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full + // 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i + // 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i + io_rw_32 fifo_st; + + _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR + // Write access to this core's TX FIFO + // 0xffffffff [31:0] FIFO_WR (0x00000000) + io_wo_32 fifo_wr; + + _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD + // Read access to this core's RX FIFO + // 0xffffffff [31:0] FIFO_RD (-) + io_ro_32 fifo_rd; + + _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST + // Spinlock state + // 0xffffffff [31:0] SPINLOCK_ST (0x00000000) + io_ro_32 spinlock_st; + + uint32_t _pad1[8]; + + interp_hw_t interp[2]; + + // (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes) + _REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0 + // Spinlock register 0 + // 0xffffffff [31:0] SPINLOCK0 (0x00000000) + io_rw_32 spinlock[32]; + + _REG_(SIO_DOORBELL_OUT_SET_OFFSET) // SIO_DOORBELL_OUT_SET + // Trigger a doorbell interrupt on the opposite core + // 0x000000ff [7:0] DOORBELL_OUT_SET (0x00) + io_rw_32 doorbell_out_set; + + _REG_(SIO_DOORBELL_OUT_CLR_OFFSET) // SIO_DOORBELL_OUT_CLR + // Clear doorbells which have been posted to the opposite core + // 0x000000ff [7:0] DOORBELL_OUT_CLR (0x00) + io_rw_32 doorbell_out_clr; + + _REG_(SIO_DOORBELL_IN_SET_OFFSET) // SIO_DOORBELL_IN_SET + // Write 1s to trigger doorbell interrupts on this core + // 0x000000ff [7:0] DOORBELL_IN_SET (0x00) + io_rw_32 doorbell_in_set; + + _REG_(SIO_DOORBELL_IN_CLR_OFFSET) // SIO_DOORBELL_IN_CLR + // Check and acknowledge doorbells posted to this core + // 0x000000ff [7:0] DOORBELL_IN_CLR (0x00) + io_rw_32 doorbell_in_clr; + + _REG_(SIO_PERI_NONSEC_OFFSET) // SIO_PERI_NONSEC + // Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so... + // 0x00000020 [5] TMDS (0) IF 1, detach TMDS encoder (of this core) from the Secure... + // 0x00000002 [1] INTERP1 (0) If 1, detach interpolator 1 (of this core) from the... + // 0x00000001 [0] INTERP0 (0) If 1, detach interpolator 0 (of this core) from the... + io_rw_32 peri_nonsec; + + uint32_t _pad2[3]; + + _REG_(SIO_RISCV_SOFTIRQ_OFFSET) // SIO_RISCV_SOFTIRQ + // Control the assertion of the standard software interrupt (MIP + // 0x00000200 [9] CORE1_CLR (0) Write 1 to atomically clear the core 1 software interrupt flag + // 0x00000100 [8] CORE0_CLR (0) Write 1 to atomically clear the core 0 software interrupt flag + // 0x00000002 [1] CORE1_SET (0) Write 1 to atomically set the core 1 software interrupt flag + // 0x00000001 [0] CORE0_SET (0) Write 1 to atomically set the core 0 software interrupt flag + io_rw_32 riscv_softirq; + + _REG_(SIO_MTIME_CTRL_OFFSET) // SIO_MTIME_CTRL + // Control register for the RISC-V 64-bit Machine-mode timer + // 0x00000008 [3] DBGPAUSE_CORE1 (1) If 1, the timer pauses when core 1 is in the debug halt state + // 0x00000004 [2] DBGPAUSE_CORE0 (1) If 1, the timer pauses when core 0 is in the debug halt state + // 0x00000002 [1] FULLSPEED (0) If 1, increment the timer every cycle (i + // 0x00000001 [0] EN (1) Timer enable bit + io_rw_32 mtime_ctrl; + + uint32_t _pad3[2]; + + _REG_(SIO_MTIME_OFFSET) // SIO_MTIME + // Read/write access to the high half of RISC-V Machine-mode timer + // 0xffffffff [31:0] MTIME (0x00000000) + io_rw_32 mtime; + + _REG_(SIO_MTIMEH_OFFSET) // SIO_MTIMEH + // Read/write access to the high half of RISC-V Machine-mode timer + // 0xffffffff [31:0] MTIMEH (0x00000000) + io_rw_32 mtimeh; + + _REG_(SIO_MTIMECMP_OFFSET) // SIO_MTIMECMP + // Low half of RISC-V Machine-mode timer comparator + // 0xffffffff [31:0] MTIMECMP (0xffffffff) + io_rw_32 mtimecmp; + + _REG_(SIO_MTIMECMPH_OFFSET) // SIO_MTIMECMPH + // High half of RISC-V Machine-mode timer comparator + // 0xffffffff [31:0] MTIMECMPH (0xffffffff) + io_rw_32 mtimecmph; + + _REG_(SIO_TMDS_CTRL_OFFSET) // SIO_TMDS_CTRL + // Control register for TMDS encoder + // 0x10000000 [28] CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders + // 0x08000000 [27] PIX2_NOSHIFT (0) When encoding two pixels's worth of symbols in one cycle... + // 0x07000000 [26:24] PIX_SHIFT (0x0) Shift applied to the colour data register with each read... + // 0x00800000 [23] INTERLEAVE (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE + // 0x001c0000 [20:18] L2_NBITS (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,... + // 0x00038000 [17:15] L1_NBITS (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,... + // 0x00007000 [14:12] L0_NBITS (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,... + // 0x00000f00 [11:8] L2_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + // 0x000000f0 [7:4] L1_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + // 0x0000000f [3:0] L0_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + io_rw_32 tmds_ctrl; + + _REG_(SIO_TMDS_WDATA_OFFSET) // SIO_TMDS_WDATA + // Write-only access to the TMDS colour data register + // 0xffffffff [31:0] TMDS_WDATA (0x00000000) + io_wo_32 tmds_wdata; + + _REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) // SIO_TMDS_PEEK_SINGLE + // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols) + // 0xffffffff [31:0] TMDS_PEEK_SINGLE (0x00000000) + io_ro_32 tmds_peek_single; + + _REG_(SIO_TMDS_POP_SINGLE_OFFSET) // SIO_TMDS_POP_SINGLE + // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value + // 0xffffffff [31:0] TMDS_POP_SINGLE (0x00000000) + io_ro_32 tmds_pop_single; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L0 + // Get lane 0 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L0 (0x00000000) + io_ro_32 tmds_peek_double_l0; + + _REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) // SIO_TMDS_POP_DOUBLE_L0 + // Get lane 0 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L0 (0x00000000) + io_ro_32 tmds_pop_double_l0; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L1 + // Get lane 1 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L1 (0x00000000) + io_ro_32 tmds_peek_double_l1; + + _REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) // SIO_TMDS_POP_DOUBLE_L1 + // Get lane 1 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L1 (0x00000000) + io_ro_32 tmds_pop_double_l1; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L2 + // Get lane 2 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L2 (0x00000000) + io_ro_32 tmds_peek_double_l2; + + _REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) // SIO_TMDS_POP_DOUBLE_L2 + // Get lane 2 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L2 (0x00000000) + io_ro_32 tmds_pop_double_l2; +} sio_hw_t; + +#define sio_hw ((sio_hw_t *)SIO_BASE) +#define sio_ns_hw ((sio_hw_t *)SIO_NONSEC_BASE) +static_assert(sizeof (sio_hw_t) == 0x01e8, ""); + +#endif // _HARDWARE_STRUCTS_SIO_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/spi.h b/lib/pico-sdk/rp2350/hardware/structs/spi.h new file mode 100644 index 000000000000..454128ea262c --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/spi.h @@ -0,0 +1,105 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SPI_H +#define _HARDWARE_STRUCTS_SPI_H + +/** + * \file rp2350/spi.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/spi.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_spi +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/spi.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0 + // Control register 0, SSPCR0 on page 3-4 + // 0x0000ff00 [15:8] SCR (0x00) Serial clock rate + // 0x00000080 [7] SPH (0) SSPCLKOUT phase, applicable to Motorola SPI frame format only + // 0x00000040 [6] SPO (0) SSPCLKOUT polarity, applicable to Motorola SPI frame format only + // 0x00000030 [5:4] FRF (0x0) Frame format: 00 Motorola SPI frame format + // 0x0000000f [3:0] DSS (0x0) Data Size Select: 0000 Reserved, undefined operation + io_rw_32 cr0; + + _REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1 + // Control register 1, SSPCR1 on page 3-5 + // 0x00000008 [3] SOD (0) Slave-mode output disable + // 0x00000004 [2] MS (0) Master or slave mode select + // 0x00000002 [1] SSE (0) Synchronous serial port enable: 0 SSP operation disabled + // 0x00000001 [0] LBM (0) Loop back mode: 0 Normal serial port operation enabled + io_rw_32 cr1; + + _REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR + // Data register, SSPDR on page 3-6 + // 0x0000ffff [15:0] DATA (-) Transmit/Receive FIFO: Read Receive FIFO + io_rw_32 dr; + + _REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR + // Status register, SSPSR on page 3-7 + // 0x00000010 [4] BSY (0) PrimeCell SSP busy flag, RO: 0 SSP is idle + // 0x00000008 [3] RFF (0) Receive FIFO full, RO: 0 Receive FIFO is not full + // 0x00000004 [2] RNE (0) Receive FIFO not empty, RO: 0 Receive FIFO is empty + // 0x00000002 [1] TNF (1) Transmit FIFO not full, RO: 0 Transmit FIFO is full + // 0x00000001 [0] TFE (1) Transmit FIFO empty, RO: 0 Transmit FIFO is not empty + io_ro_32 sr; + + _REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR + // Clock prescale register, SSPCPSR on page 3-8 + // 0x000000ff [7:0] CPSDVSR (0x00) Clock prescale divisor + io_rw_32 cpsr; + + _REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC + // Interrupt mask set or clear register, SSPIMSC on page 3-9 + // 0x00000008 [3] TXIM (0) Transmit FIFO interrupt mask: 0 Transmit FIFO half empty... + // 0x00000004 [2] RXIM (0) Receive FIFO interrupt mask: 0 Receive FIFO half full or... + // 0x00000002 [1] RTIM (0) Receive timeout interrupt mask: 0 Receive FIFO not empty... + // 0x00000001 [0] RORIM (0) Receive overrun interrupt mask: 0 Receive FIFO written... + io_rw_32 imsc; + + _REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS + // Raw interrupt status register, SSPRIS on page 3-10 + // 0x00000008 [3] TXRIS (1) Gives the raw interrupt state, prior to masking, of the... + // 0x00000004 [2] RXRIS (0) Gives the raw interrupt state, prior to masking, of the... + // 0x00000002 [1] RTRIS (0) Gives the raw interrupt state, prior to masking, of the... + // 0x00000001 [0] RORRIS (0) Gives the raw interrupt state, prior to masking, of the... + io_ro_32 ris; + + _REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS + // Masked interrupt status register, SSPMIS on page 3-11 + // 0x00000008 [3] TXMIS (0) Gives the transmit FIFO masked interrupt state, after... + // 0x00000004 [2] RXMIS (0) Gives the receive FIFO masked interrupt state, after... + // 0x00000002 [1] RTMIS (0) Gives the receive timeout masked interrupt state, after... + // 0x00000001 [0] RORMIS (0) Gives the receive over run masked interrupt status,... + io_ro_32 mis; + + _REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR + // Interrupt clear register, SSPICR on page 3-11 + // 0x00000002 [1] RTIC (0) Clears the SSPRTINTR interrupt + // 0x00000001 [0] RORIC (0) Clears the SSPRORINTR interrupt + io_rw_32 icr; + + _REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR + // DMA control register, SSPDMACR on page 3-12 + // 0x00000002 [1] TXDMAE (0) Transmit DMA Enable + // 0x00000001 [0] RXDMAE (0) Receive DMA Enable + io_rw_32 dmacr; +} spi_hw_t; + +#define spi0_hw ((spi_hw_t *)SPI0_BASE) +#define spi1_hw ((spi_hw_t *)SPI1_BASE) +static_assert(sizeof (spi_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_SPI_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/syscfg.h b/lib/pico-sdk/rp2350/hardware/structs/syscfg.h new file mode 100644 index 000000000000..8909c0dbf91a --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/syscfg.h @@ -0,0 +1,83 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SYSCFG_H +#define _HARDWARE_STRUCTS_SYSCFG_H + +/** + * \file rp2350/syscfg.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/syscfg.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_syscfg +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG + // Configuration for processors + // 0x00000002 [1] PROC1_HALTED (0) Indication that proc1 has halted + // 0x00000001 [0] PROC0_HALTED (0) Indication that proc0 has halted + io_ro_32 proc_config; + + _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS + // For each bit, if 1, bypass the input synchronizer between that GPIO + + // 0xffffffff [31:0] GPIO (0x00000000) + io_rw_32 proc_in_sync_bypass; + + _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI + // For each bit, if 1, bypass the input synchronizer between that GPIO + + // 0xf0000000 [31:28] QSPI_SD (0x0) + // 0x08000000 [27] QSPI_CSN (0) + // 0x04000000 [26] QSPI_SCK (0) + // 0x02000000 [25] USB_DM (0) + // 0x01000000 [24] USB_DP (0) + // 0x0000ffff [15:0] GPIO (0x0000) + io_rw_32 proc_in_sync_bypass_hi; + + _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE + // Directly control the chip SWD debug port + // 0x00000008 [3] ATTACH (0) Attach chip debug port to syscfg controls, and... + // 0x00000004 [2] SWCLK (1) Directly drive SWCLK, if ATTACH is set + // 0x00000002 [1] SWDI (1) Directly drive SWDIO input, if ATTACH is set + // 0x00000001 [0] SWDO (-) Observe the value of SWDIO output + io_rw_32 dbgforce; + + _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN + // Control PD pins to memories + // 0x00001000 [12] BOOTRAM (0) + // 0x00000800 [11] ROM (0) + // 0x00000400 [10] USB (0) + // 0x00000200 [9] SRAM9 (0) + // 0x00000100 [8] SRAM8 (0) + // 0x00000080 [7] SRAM7 (0) + // 0x00000040 [6] SRAM6 (0) + // 0x00000020 [5] SRAM5 (0) + // 0x00000010 [4] SRAM4 (0) + // 0x00000008 [3] SRAM3 (0) + // 0x00000004 [2] SRAM2 (0) + // 0x00000002 [1] SRAM1 (0) + // 0x00000001 [0] SRAM0 (0) + io_rw_32 mempowerdown; + + _REG_(SYSCFG_AUXCTRL_OFFSET) // SYSCFG_AUXCTRL + // Auxiliary system control register + // 0x000000ff [7:0] AUXCTRL (0x00) * Bits 7:2: Reserved + io_rw_32 auxctrl; +} syscfg_hw_t; + +#define syscfg_hw ((syscfg_hw_t *)SYSCFG_BASE) +static_assert(sizeof (syscfg_hw_t) == 0x0018, ""); + +#endif // _HARDWARE_STRUCTS_SYSCFG_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/sysinfo.h b/lib/pico-sdk/rp2350/hardware/structs/sysinfo.h new file mode 100644 index 000000000000..688b577e4d30 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/sysinfo.h @@ -0,0 +1,60 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SYSINFO_H +#define _HARDWARE_STRUCTS_SYSINFO_H + +/** + * \file rp2350/sysinfo.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sysinfo.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sysinfo +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sysinfo.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SYSINFO_CHIP_ID_OFFSET) // SYSINFO_CHIP_ID + // JEDEC JEP-106 compliant chip identifier + // 0xf0000000 [31:28] REVISION (-) + // 0x0ffff000 [27:12] PART (-) + // 0x00000ffe [11:1] MANUFACTURER (-) + // 0x00000001 [0] STOP_BIT (1) + io_ro_32 chip_id; + + _REG_(SYSINFO_PACKAGE_SEL_OFFSET) // SYSINFO_PACKAGE_SEL + // 0x00000001 [0] PACKAGE_SEL (0) + io_ro_32 package_sel; + + _REG_(SYSINFO_PLATFORM_OFFSET) // SYSINFO_PLATFORM + // Platform register + // 0x00000010 [4] GATESIM (-) + // 0x00000008 [3] BATCHSIM (-) + // 0x00000004 [2] HDLSIM (-) + // 0x00000002 [1] ASIC (-) + // 0x00000001 [0] FPGA (-) + io_ro_32 platform; + + uint32_t _pad0[2]; + + _REG_(SYSINFO_GITREF_RP2350_OFFSET) // SYSINFO_GITREF_RP2350 + // Git hash of the chip source + // 0xffffffff [31:0] GITREF_RP2350 (-) + io_ro_32 gitref_rp2350; +} sysinfo_hw_t; + +#define sysinfo_hw ((sysinfo_hw_t *)SYSINFO_BASE) +static_assert(sizeof (sysinfo_hw_t) == 0x0018, ""); + +#endif // _HARDWARE_STRUCTS_SYSINFO_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/systick.h b/lib/pico-sdk/rp2350/hardware/structs/systick.h new file mode 100644 index 000000000000..f6024b1e93f6 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/systick.h @@ -0,0 +1,62 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_SYSTICK_H +#define _HARDWARE_STRUCTS_SYSTICK_H + +/** + * \file rp2350/systick.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/m33.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/m33.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV +#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" +#endif + +typedef struct { + _REG_(M33_SYST_CSR_OFFSET) // M33_SYST_CSR + // SysTick Control and Status Register + // 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read + // 0x00000004 [2] CLKSOURCE (0) SysTick clock source + // 0x00000002 [1] TICKINT (0) Enables SysTick exception request: + + // 0x00000001 [0] ENABLE (0) Enable SysTick counter: + + io_rw_32 csr; + + _REG_(M33_SYST_RVR_OFFSET) // M33_SYST_RVR + // SysTick Reload Value Register + // 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register... + io_rw_32 rvr; + + _REG_(M33_SYST_CVR_OFFSET) // M33_SYST_CVR + // SysTick Current Value Register + // 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter + io_rw_32 cvr; + + _REG_(M33_SYST_CALIB_OFFSET) // M33_SYST_CALIB + // SysTick Calibration Value Register + // 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the... + // 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact... + // 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)... + io_ro_32 calib; +} systick_hw_t; + +#define systick_hw ((systick_hw_t *)(PPB_BASE + M33_SYST_CSR_OFFSET)) +#define systick_ns_hw ((systick_hw_t *)(PPB_NONSEC_BASE + M33_SYST_CSR_OFFSET)) +static_assert(sizeof (systick_hw_t) == 0x0010, ""); + +#endif // _HARDWARE_STRUCTS_SYSTICK_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/tbman.h b/lib/pico-sdk/rp2350/hardware/structs/tbman.h new file mode 100644 index 000000000000..58d80dd86ede --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/tbman.h @@ -0,0 +1,39 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TBMAN_H +#define _HARDWARE_STRUCTS_TBMAN_H + +/** + * \file rp2350/tbman.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/tbman.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_tbman +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/tbman.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(TBMAN_PLATFORM_OFFSET) // TBMAN_PLATFORM + // Indicates the type of platform in use + // 0x00000004 [2] HDLSIM (0) Indicates the platform is a simulation + // 0x00000002 [1] FPGA (0) Indicates the platform is an FPGA + // 0x00000001 [0] ASIC (1) Indicates the platform is an ASIC + io_ro_32 platform; +} tbman_hw_t; + +#define tbman_hw ((tbman_hw_t *)TBMAN_BASE) +static_assert(sizeof (tbman_hw_t) == 0x0004, ""); + +#endif // _HARDWARE_STRUCTS_TBMAN_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/ticks.h b/lib/pico-sdk/rp2350/hardware/structs/ticks.h new file mode 100644 index 000000000000..b436484a3b64 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/ticks.h @@ -0,0 +1,63 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TICKS_H +#define _HARDWARE_STRUCTS_TICKS_H + +/** + * \file rp2350/ticks.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/ticks.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_ticks +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/ticks.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/*! \brief Tick generator numbers on RP2350 (used as typedef \ref tick_gen_num_t) + * \ingroup hardware_ticks + */ +typedef enum tick_gen_num_rp2350 { + TICK_PROC0 = 0, + TICK_PROC1 = 1, + TICK_TIMER0 = 2, + TICK_TIMER1 = 3, + TICK_WATCHDOG = 4, + TICK_RISCV = 5, + TICK_COUNT +} tick_gen_num_t; + +typedef struct { + _REG_(TICKS_PROC0_CTRL_OFFSET) // TICKS_PROC0_CTRL + // Controls the tick generator + // 0x00000002 [1] RUNNING (-) Is the tick generator running? + // 0x00000001 [0] ENABLE (0) start / stop tick generation + io_rw_32 ctrl; + + _REG_(TICKS_PROC0_CYCLES_OFFSET) // TICKS_PROC0_CYCLES + // 0x000001ff [8:0] PROC0_CYCLES (0x000) Total number of clk_tick cycles before the next tick + io_rw_32 cycles; + + _REG_(TICKS_PROC0_COUNT_OFFSET) // TICKS_PROC0_COUNT + // 0x000001ff [8:0] PROC0_COUNT (-) Count down timer: the remaining number clk_tick cycles... + io_ro_32 count; +} ticks_slice_hw_t; + +typedef struct { + ticks_slice_hw_t ticks[6]; +} ticks_hw_t; + +#define ticks_hw ((ticks_hw_t *)TICKS_BASE) +static_assert(sizeof (ticks_hw_t) == 0x0048, ""); + +#endif // _HARDWARE_STRUCTS_TICKS_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/timer.h b/lib/pico-sdk/rp2350/hardware/structs/timer.h new file mode 100644 index 000000000000..978dd56881ad --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/timer.h @@ -0,0 +1,127 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TIMER_H +#define _HARDWARE_STRUCTS_TIMER_H + +/** + * \file rp2350/timer.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/timer.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_timer +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/timer.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW + // Write to bits 63:32 of time always write timelw before timehw + // 0xffffffff [31:0] TIMEHW (0x00000000) + io_wo_32 timehw; + + _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW + // Write to bits 31:0 of time writes do not get copied to time until timehw is written + // 0xffffffff [31:0] TIMELW (0x00000000) + io_wo_32 timelw; + + _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR + // Read from bits 63:32 of time always read timelr before timehr + // 0xffffffff [31:0] TIMEHR (0x00000000) + io_ro_32 timehr; + + _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR + // Read from bits 31:0 of time + // 0xffffffff [31:0] TIMELR (0x00000000) + io_ro_32 timelr; + + // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes) + _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0 + // Arm alarm 0, and configure the time it will fire + // 0xffffffff [31:0] ALARM0 (0x00000000) + io_rw_32 alarm[4]; + + _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED + // Indicates the armed/disarmed status of each alarm + // 0x0000000f [3:0] ARMED (0x0) + io_rw_32 armed; + + _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH + // Raw read from bits 63:32 of time (no side effects) + // 0xffffffff [31:0] TIMERAWH (0x00000000) + io_ro_32 timerawh; + + _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL + // Raw read from bits 31:0 of time (no side effects) + // 0xffffffff [31:0] TIMERAWL (0x00000000) + io_ro_32 timerawl; + + _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE + // Set bits high to enable pause when the corresponding debug ports are active + // 0x00000004 [2] DBG1 (1) Pause when processor 1 is in debug mode + // 0x00000002 [1] DBG0 (1) Pause when processor 0 is in debug mode + io_rw_32 dbgpause; + + _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE + // Set high to pause the timer + // 0x00000001 [0] PAUSE (0) + io_rw_32 pause; + + _REG_(TIMER_LOCKED_OFFSET) // TIMER_LOCKED + // Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) + // 0x00000001 [0] LOCKED (0) + io_rw_32 locked; + + _REG_(TIMER_SOURCE_OFFSET) // TIMER_SOURCE + // Selects the source for the timer + // 0x00000001 [0] CLK_SYS (0) + io_rw_32 source; + + _REG_(TIMER_INTR_OFFSET) // TIMER_INTR + // Raw Interrupts + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_rw_32 intr; + + _REG_(TIMER_INTE_OFFSET) // TIMER_INTE + // Interrupt Enable + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_rw_32 inte; + + _REG_(TIMER_INTF_OFFSET) // TIMER_INTF + // Interrupt Force + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_rw_32 intf; + + _REG_(TIMER_INTS_OFFSET) // TIMER_INTS + // Interrupt status after masking & forcing + // 0x00000008 [3] ALARM_3 (0) + // 0x00000004 [2] ALARM_2 (0) + // 0x00000002 [1] ALARM_1 (0) + // 0x00000001 [0] ALARM_0 (0) + io_ro_32 ints; +} timer_hw_t; + +#define timer0_hw ((timer_hw_t *)TIMER0_BASE) +#define timer1_hw ((timer_hw_t *)TIMER1_BASE) +static_assert(sizeof (timer_hw_t) == 0x004c, ""); + +#endif // _HARDWARE_STRUCTS_TIMER_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/tmds_encode.h b/lib/pico-sdk/rp2350/hardware/structs/tmds_encode.h new file mode 100644 index 000000000000..c1213af1983b --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/tmds_encode.h @@ -0,0 +1,92 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TMDS_ENCODE_H +#define _HARDWARE_STRUCTS_TMDS_ENCODE_H + +/** + * \file rp2350/tmds_encode.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/sio.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/sio.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(SIO_TMDS_CTRL_OFFSET) // SIO_TMDS_CTRL + // Control register for TMDS encoder + // 0x10000000 [28] CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders + // 0x08000000 [27] PIX2_NOSHIFT (0) When encoding two pixels's worth of symbols in one cycle... + // 0x07000000 [26:24] PIX_SHIFT (0x0) Shift applied to the colour data register with each read... + // 0x00800000 [23] INTERLEAVE (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE + // 0x001c0000 [20:18] L2_NBITS (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,... + // 0x00038000 [17:15] L1_NBITS (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,... + // 0x00007000 [14:12] L0_NBITS (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,... + // 0x00000f00 [11:8] L2_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + // 0x000000f0 [7:4] L1_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + // 0x0000000f [3:0] L0_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... + io_rw_32 tmds_ctrl; + + _REG_(SIO_TMDS_WDATA_OFFSET) // SIO_TMDS_WDATA + // Write-only access to the TMDS colour data register + // 0xffffffff [31:0] TMDS_WDATA (0x00000000) + io_wo_32 tmds_wdata; + + _REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) // SIO_TMDS_PEEK_SINGLE + // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols) + // 0xffffffff [31:0] TMDS_PEEK_SINGLE (0x00000000) + io_ro_32 tmds_peek_single; + + _REG_(SIO_TMDS_POP_SINGLE_OFFSET) // SIO_TMDS_POP_SINGLE + // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value + // 0xffffffff [31:0] TMDS_POP_SINGLE (0x00000000) + io_ro_32 tmds_pop_single; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L0 + // Get lane 0 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L0 (0x00000000) + io_ro_32 tmds_peek_double_l0; + + _REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) // SIO_TMDS_POP_DOUBLE_L0 + // Get lane 0 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L0 (0x00000000) + io_ro_32 tmds_pop_double_l0; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L1 + // Get lane 1 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L1 (0x00000000) + io_ro_32 tmds_peek_double_l1; + + _REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) // SIO_TMDS_POP_DOUBLE_L1 + // Get lane 1 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L1 (0x00000000) + io_ro_32 tmds_pop_double_l1; + + _REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L2 + // Get lane 2 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L2 (0x00000000) + io_ro_32 tmds_peek_double_l2; + + _REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) // SIO_TMDS_POP_DOUBLE_L2 + // Get lane 2 of the encoding of two pixels' worth of colour data + // 0xffffffff [31:0] TMDS_POP_DOUBLE_L2 (0x00000000) + io_ro_32 tmds_pop_double_l2; +} tmds_encode_hw_t; + +#define tmds_encode_hw ((tmds_encode_hw_t *)(SIO_BASE + SIO_TMDS_CTRL_OFFSET)) +#define tmds_encode_ns_hw ((tmds_encode_hw_t *)(SIO_NONSEC_BASE + SIO_TMDS_CTRL_OFFSET)) +static_assert(sizeof (tmds_encode_hw_t) == 0x0028, ""); + +#endif // _HARDWARE_STRUCTS_TMDS_ENCODE_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/trng.h b/lib/pico-sdk/rp2350/hardware/structs/trng.h new file mode 100644 index 000000000000..5ae592961af0 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/trng.h @@ -0,0 +1,153 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_TRNG_H +#define _HARDWARE_STRUCTS_TRNG_H + +/** + * \file rp2350/trng.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/trng.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_trng +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/trng.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(TRNG_RNG_IMR_OFFSET) // TRNG_RNG_IMR + // Interrupt masking + // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED + // 0x00000008 [3] VN_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated + // 0x00000004 [2] CRNGT_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated + // 0x00000002 [1] AUTOCORR_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated + // 0x00000001 [0] EHR_VALID_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated + io_rw_32 rng_imr; + + _REG_(TRNG_RNG_ISR_OFFSET) // TRNG_RNG_ISR + // RNG status register + // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED + // 0x00000008 [3] VN_ERR (0) 1'b1 indicates Von Neuman error + // 0x00000004 [2] CRNGT_ERR (0) 1'b1 indicates CRNGT in the RNG test failed + // 0x00000002 [1] AUTOCORR_ERR (0) 1'b1 indicates Autocorrelation test failed four times in a row + // 0x00000001 [0] EHR_VALID (0) 1'b1 indicates that 192 bits have been collected in the... + io_ro_32 rng_isr; + + _REG_(TRNG_RNG_ICR_OFFSET) // TRNG_RNG_ICR + // Interrupt/status bit clear Register + // 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED + // 0x00000008 [3] VN_ERR (0) Write 1'b1 - clear corresponding bit in RNG_ISR + // 0x00000004 [2] CRNGT_ERR (0) Write 1'b1 - clear corresponding bit in RNG_ISR + // 0x00000002 [1] AUTOCORR_ERR (0) Cannot be cleared by SW! Only RNG reset clears this bit + // 0x00000001 [0] EHR_VALID (0) Write 1'b1 - clear corresponding bit in RNG_ISR + io_rw_32 rng_icr; + + _REG_(TRNG_TRNG_CONFIG_OFFSET) // TRNG_TRNG_CONFIG + // Selecting the inverter-chain length + // 0xfffffffc [31:2] RESERVED (0x00000000) RESERVED + // 0x00000003 [1:0] RND_SRC_SEL (0x0) Selects the number of inverters (out of four possible... + io_rw_32 trng_config; + + _REG_(TRNG_TRNG_VALID_OFFSET) // TRNG_TRNG_VALID + // 192 bit collection indication + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] EHR_VALID (0) 1'b1 indicates that collection of bits in the RNG is... + io_ro_32 trng_valid; + + // (Description copied from array index 0 register TRNG_EHR_DATA0 applies similarly to other array indexes) + _REG_(TRNG_EHR_DATA0_OFFSET) // TRNG_EHR_DATA0 + // RNG collected bits + // 0xffffffff [31:0] EHR_DATA0 (0x00000000) Bits [31:0] of Entropy Holding Register (EHR) - RNG... + io_ro_32 ehr_data[6]; + + _REG_(TRNG_RND_SOURCE_ENABLE_OFFSET) // TRNG_RND_SOURCE_ENABLE + // Enable signal for the random source + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] RND_SRC_EN (0) * 1'b1 - entropy source is enabled + io_rw_32 rnd_source_enable; + + _REG_(TRNG_SAMPLE_CNT1_OFFSET) // TRNG_SAMPLE_CNT1 + // Counts clocks between sampling of random bit + // 0xffffffff [31:0] SAMPLE_CNTR1 (0x0000ffff) Sets the number of rng_clk cycles between two... + io_rw_32 sample_cnt1; + + _REG_(TRNG_AUTOCORR_STATISTIC_OFFSET) // TRNG_AUTOCORR_STATISTIC + // Statistic about Autocorrelation test activations + // 0xffc00000 [31:22] RESERVED (0x000) RESERVED + // 0x003fc000 [21:14] AUTOCORR_FAILS (0x00) Count each time an autocorrelation test fails + // 0x00003fff [13:0] AUTOCORR_TRYS (0x0000) Count each time an autocorrelation test starts + io_rw_32 autocorr_statistic; + + _REG_(TRNG_TRNG_DEBUG_CONTROL_OFFSET) // TRNG_TRNG_DEBUG_CONTROL + // Debug register + // 0x00000008 [3] AUTO_CORRELATE_BYPASS (0) When set, the autocorrelation test in the TRNG module is bypassed + // 0x00000004 [2] TRNG_CRNGT_BYPASS (0) When set, the CRNGT test in the RNG is bypassed + // 0x00000002 [1] VNC_BYPASS (0) When set, the Von-Neuman balancer is bypassed (including... + // 0x00000001 [0] RESERVED (0) N/A + io_rw_32 trng_debug_control; + + uint32_t _pad0; + + _REG_(TRNG_TRNG_SW_RESET_OFFSET) // TRNG_TRNG_SW_RESET + // Generate internal SW reset within the RNG block + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] TRNG_SW_RESET (0) Writing 1'b1 to this register causes an internal RNG reset + io_rw_32 trng_sw_reset; + + uint32_t _pad1[28]; + + _REG_(TRNG_RNG_DEBUG_EN_INPUT_OFFSET) // TRNG_RNG_DEBUG_EN_INPUT + // Enable the RNG debug mode + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] RNG_DEBUG_EN (0) * 1'b1 - debug mode is enabled + io_rw_32 rng_debug_en_input; + + _REG_(TRNG_TRNG_BUSY_OFFSET) // TRNG_TRNG_BUSY + // RNG Busy indication + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] TRNG_BUSY (0) Reflects rng_busy status + io_ro_32 trng_busy; + + _REG_(TRNG_RST_BITS_COUNTER_OFFSET) // TRNG_RST_BITS_COUNTER + // Reset the counter of collected bits in the RNG + // 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED + // 0x00000001 [0] RST_BITS_COUNTER (0) Writing any value to this address will reset the bits... + io_rw_32 rst_bits_counter; + + _REG_(TRNG_RNG_VERSION_OFFSET) // TRNG_RNG_VERSION + // Displays the version settings of the TRNG + // 0xffffff00 [31:8] RESERVED (0x000000) RESERVED + // 0x00000080 [7] RNG_USE_5_SBOXES (0) * 1'b1 - 5 SBOX AES + // 0x00000040 [6] RESEEDING_EXISTS (0) * 1'b1 - Exists + // 0x00000020 [5] KAT_EXISTS (0) * 1'b1 - Exists + // 0x00000010 [4] PRNG_EXISTS (0) * 1'b1 - Exists + // 0x00000008 [3] TRNG_TESTS_BYPASS_EN (0) * 1'b1 - Exists + // 0x00000004 [2] AUTOCORR_EXISTS (0) * 1'b1 - Exists + // 0x00000002 [1] CRNGT_EXISTS (0) * 1'b1 - Exists + // 0x00000001 [0] EHR_WIDTH_192 (0) * 1'b1 - 192-bit EHR + io_ro_32 rng_version; + + uint32_t _pad2[7]; + + // (Description copied from array index 0 register TRNG_RNG_BIST_CNTR_0 applies similarly to other array indexes) + _REG_(TRNG_RNG_BIST_CNTR_0_OFFSET) // TRNG_RNG_BIST_CNTR_0 + // Collected BIST results + // 0xffc00000 [31:22] RESERVED (0x000) RESERVED + // 0x003fffff [21:0] ROSC_CNTR_VAL (0x000000) Reflects the results of RNG BIST counter + io_ro_32 rng_bist_cntr[3]; +} trng_hw_t; + +#define trng_hw ((trng_hw_t *)(TRNG_BASE + TRNG_RNG_IMR_OFFSET)) +static_assert(sizeof (trng_hw_t) == 0x00ec, ""); + +#endif // _HARDWARE_STRUCTS_TRNG_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/uart.h b/lib/pico-sdk/rp2350/hardware/structs/uart.h new file mode 100644 index 000000000000..47ff324e378d --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/uart.h @@ -0,0 +1,182 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_UART_H +#define _HARDWARE_STRUCTS_UART_H + +/** + * \file rp2350/uart.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/uart.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_uart +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/uart.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(UART_UARTDR_OFFSET) // UART_UARTDR + // Data Register, UARTDR + // 0x00000800 [11] OE (-) Overrun error + // 0x00000400 [10] BE (-) Break error + // 0x00000200 [9] PE (-) Parity error + // 0x00000100 [8] FE (-) Framing error + // 0x000000ff [7:0] DATA (-) Receive (read) data character + io_rw_32 dr; + + _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR + // Receive Status Register/Error Clear Register, UARTRSR/UARTECR + // 0x00000008 [3] OE (0) Overrun error + // 0x00000004 [2] BE (0) Break error + // 0x00000002 [1] PE (0) Parity error + // 0x00000001 [0] FE (0) Framing error + io_rw_32 rsr; + + uint32_t _pad0[4]; + + _REG_(UART_UARTFR_OFFSET) // UART_UARTFR + // Flag Register, UARTFR + // 0x00000100 [8] RI (-) Ring indicator + // 0x00000080 [7] TXFE (1) Transmit FIFO empty + // 0x00000040 [6] RXFF (0) Receive FIFO full + // 0x00000020 [5] TXFF (0) Transmit FIFO full + // 0x00000010 [4] RXFE (1) Receive FIFO empty + // 0x00000008 [3] BUSY (0) UART busy + // 0x00000004 [2] DCD (-) Data carrier detect + // 0x00000002 [1] DSR (-) Data set ready + // 0x00000001 [0] CTS (-) Clear to send + io_ro_32 fr; + + uint32_t _pad1; + + _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR + // IrDA Low-Power Counter Register, UARTILPR + // 0x000000ff [7:0] ILPDVSR (0x00) 8-bit low-power divisor value + io_rw_32 ilpr; + + _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD + // Integer Baud Rate Register, UARTIBRD + // 0x0000ffff [15:0] BAUD_DIVINT (0x0000) The integer baud rate divisor + io_rw_32 ibrd; + + _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD + // Fractional Baud Rate Register, UARTFBRD + // 0x0000003f [5:0] BAUD_DIVFRAC (0x00) The fractional baud rate divisor + io_rw_32 fbrd; + + _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H + // Line Control Register, UARTLCR_H + // 0x00000080 [7] SPS (0) Stick parity select + // 0x00000060 [6:5] WLEN (0x0) Word length + // 0x00000010 [4] FEN (0) Enable FIFOs: 0 = FIFOs are disabled (character mode)... + // 0x00000008 [3] STP2 (0) Two stop bits select + // 0x00000004 [2] EPS (0) Even parity select + // 0x00000002 [1] PEN (0) Parity enable: 0 = parity is disabled and no parity bit... + // 0x00000001 [0] BRK (0) Send break + io_rw_32 lcr_h; + + _REG_(UART_UARTCR_OFFSET) // UART_UARTCR + // Control Register, UARTCR + // 0x00008000 [15] CTSEN (0) CTS hardware flow control enable + // 0x00004000 [14] RTSEN (0) RTS hardware flow control enable + // 0x00002000 [13] OUT2 (0) This bit is the complement of the UART Out2 (nUARTOut2)... + // 0x00001000 [12] OUT1 (0) This bit is the complement of the UART Out1 (nUARTOut1)... + // 0x00000800 [11] RTS (0) Request to send + // 0x00000400 [10] DTR (0) Data transmit ready + // 0x00000200 [9] RXE (1) Receive enable + // 0x00000100 [8] TXE (1) Transmit enable + // 0x00000080 [7] LBE (0) Loopback enable + // 0x00000004 [2] SIRLP (0) SIR low-power IrDA mode + // 0x00000002 [1] SIREN (0) SIR enable: 0 = IrDA SIR ENDEC is disabled + // 0x00000001 [0] UARTEN (0) UART enable: 0 = UART is disabled + io_rw_32 cr; + + _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS + // Interrupt FIFO Level Select Register, UARTIFLS + // 0x00000038 [5:3] RXIFLSEL (0x2) Receive interrupt FIFO level select + // 0x00000007 [2:0] TXIFLSEL (0x2) Transmit interrupt FIFO level select + io_rw_32 ifls; + + _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC + // Interrupt Mask Set/Clear Register, UARTIMSC + // 0x00000400 [10] OEIM (0) Overrun error interrupt mask + // 0x00000200 [9] BEIM (0) Break error interrupt mask + // 0x00000100 [8] PEIM (0) Parity error interrupt mask + // 0x00000080 [7] FEIM (0) Framing error interrupt mask + // 0x00000040 [6] RTIM (0) Receive timeout interrupt mask + // 0x00000020 [5] TXIM (0) Transmit interrupt mask + // 0x00000010 [4] RXIM (0) Receive interrupt mask + // 0x00000008 [3] DSRMIM (0) nUARTDSR modem interrupt mask + // 0x00000004 [2] DCDMIM (0) nUARTDCD modem interrupt mask + // 0x00000002 [1] CTSMIM (0) nUARTCTS modem interrupt mask + // 0x00000001 [0] RIMIM (0) nUARTRI modem interrupt mask + io_rw_32 imsc; + + _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS + // Raw Interrupt Status Register, UARTRIS + // 0x00000400 [10] OERIS (0) Overrun error interrupt status + // 0x00000200 [9] BERIS (0) Break error interrupt status + // 0x00000100 [8] PERIS (0) Parity error interrupt status + // 0x00000080 [7] FERIS (0) Framing error interrupt status + // 0x00000040 [6] RTRIS (0) Receive timeout interrupt status + // 0x00000020 [5] TXRIS (0) Transmit interrupt status + // 0x00000010 [4] RXRIS (0) Receive interrupt status + // 0x00000008 [3] DSRRMIS (-) nUARTDSR modem interrupt status + // 0x00000004 [2] DCDRMIS (-) nUARTDCD modem interrupt status + // 0x00000002 [1] CTSRMIS (-) nUARTCTS modem interrupt status + // 0x00000001 [0] RIRMIS (-) nUARTRI modem interrupt status + io_ro_32 ris; + + _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS + // Masked Interrupt Status Register, UARTMIS + // 0x00000400 [10] OEMIS (0) Overrun error masked interrupt status + // 0x00000200 [9] BEMIS (0) Break error masked interrupt status + // 0x00000100 [8] PEMIS (0) Parity error masked interrupt status + // 0x00000080 [7] FEMIS (0) Framing error masked interrupt status + // 0x00000040 [6] RTMIS (0) Receive timeout masked interrupt status + // 0x00000020 [5] TXMIS (0) Transmit masked interrupt status + // 0x00000010 [4] RXMIS (0) Receive masked interrupt status + // 0x00000008 [3] DSRMMIS (-) nUARTDSR modem masked interrupt status + // 0x00000004 [2] DCDMMIS (-) nUARTDCD modem masked interrupt status + // 0x00000002 [1] CTSMMIS (-) nUARTCTS modem masked interrupt status + // 0x00000001 [0] RIMMIS (-) nUARTRI modem masked interrupt status + io_ro_32 mis; + + _REG_(UART_UARTICR_OFFSET) // UART_UARTICR + // Interrupt Clear Register, UARTICR + // 0x00000400 [10] OEIC (-) Overrun error interrupt clear + // 0x00000200 [9] BEIC (-) Break error interrupt clear + // 0x00000100 [8] PEIC (-) Parity error interrupt clear + // 0x00000080 [7] FEIC (-) Framing error interrupt clear + // 0x00000040 [6] RTIC (-) Receive timeout interrupt clear + // 0x00000020 [5] TXIC (-) Transmit interrupt clear + // 0x00000010 [4] RXIC (-) Receive interrupt clear + // 0x00000008 [3] DSRMIC (-) nUARTDSR modem interrupt clear + // 0x00000004 [2] DCDMIC (-) nUARTDCD modem interrupt clear + // 0x00000002 [1] CTSMIC (-) nUARTCTS modem interrupt clear + // 0x00000001 [0] RIMIC (-) nUARTRI modem interrupt clear + io_rw_32 icr; + + _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR + // DMA Control Register, UARTDMACR + // 0x00000004 [2] DMAONERR (0) DMA on error + // 0x00000002 [1] TXDMAE (0) Transmit DMA enable + // 0x00000001 [0] RXDMAE (0) Receive DMA enable + io_rw_32 dmacr; +} uart_hw_t; + +#define uart0_hw ((uart_hw_t *)UART0_BASE) +#define uart1_hw ((uart_hw_t *)UART1_BASE) +static_assert(sizeof (uart_hw_t) == 0x004c, ""); + +#endif // _HARDWARE_STRUCTS_UART_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/usb.h b/lib/pico-sdk/rp2350/hardware/structs/usb.h new file mode 100644 index 000000000000..1c6229bd3495 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/usb.h @@ -0,0 +1,602 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_USB_H +#define _HARDWARE_STRUCTS_USB_H + +/** + * \file rp2350/usb.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/usb.h" +#include "hardware/structs/usb_dpram.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_usb +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP + // Device address and endpoint control + // 0x000f0000 [19:16] ENDPOINT (0x0) Device endpoint to send data to + // 0x0000007f [6:0] ADDRESS (0x00) In device mode, the address that the device should respond to + io_rw_32 dev_addr_ctrl; + + // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes) + _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1 + // Interrupt endpoint 1 + // 0x04000000 [26] INTEP_PREAMBLE (0) Interrupt EP requires preamble (is a low speed device on... + // 0x02000000 [25] INTEP_DIR (0) Direction of the interrupt endpoint + // 0x000f0000 [19:16] ENDPOINT (0x0) Endpoint number of the interrupt endpoint + // 0x0000007f [6:0] ADDRESS (0x00) Device address + io_rw_32 int_ep_addr_ctrl[15]; + + _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL + // Main control register + // 0x80000000 [31] SIM_TIMING (0) Reduced timings for simulation + // 0x00000004 [2] PHY_ISO (1) Isolates USB phy after controller power-up + + // 0x00000002 [1] HOST_NDEVICE (0) Device mode = 0, Host mode = 1 + // 0x00000001 [0] CONTROLLER_EN (0) Enable controller + io_rw_32 main_ctrl; + + _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR + // Set the SOF (Start of Frame) frame number in the host controller + // 0x000007ff [10:0] COUNT (0x000) + io_wo_32 sof_wr; + + _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD + // Read the last SOF (Start of Frame) frame number seen + // 0x000007ff [10:0] COUNT (0x000) + io_ro_32 sof_rd; + + _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL + // SIE control register + // 0x80000000 [31] EP0_INT_STALL (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + // 0x40000000 [30] EP0_DOUBLE_BUF (0) Device: EP0 single buffered = 0, double buffered = 1 + // 0x20000000 [29] EP0_INT_1BUF (0) Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + // 0x10000000 [28] EP0_INT_2BUF (0) Device: Set bit in BUFF_STATUS for every 2 buffers... + // 0x08000000 [27] EP0_INT_NAK (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + // 0x04000000 [26] DIRECT_EN (0) Direct bus drive enable + // 0x02000000 [25] DIRECT_DP (0) Direct control of DP + // 0x01000000 [24] DIRECT_DM (0) Direct control of DM + // 0x00080000 [19] EP0_STOP_ON_SHORT_PACKET (0) Device: Stop EP0 on a short packet + // 0x00040000 [18] TRANSCEIVER_PD (0) Power down bus transceiver + // 0x00020000 [17] RPU_OPT (0) Device: Pull-up strength (0=1K2, 1=2k3) + // 0x00010000 [16] PULLUP_EN (0) Device: Enable pull up resistor + // 0x00008000 [15] PULLDOWN_EN (1) Host: Enable pull down resistors + // 0x00002000 [13] RESET_BUS (0) Host: Reset bus + // 0x00001000 [12] RESUME (0) Device: Remote wakeup + // 0x00000800 [11] VBUS_EN (0) Host: Enable VBUS + // 0x00000400 [10] KEEP_ALIVE_EN (0) Host: Enable keep alive packet (for low speed bus) + // 0x00000200 [9] SOF_EN (0) Host: Enable SOF generation (for full speed bus) + // 0x00000100 [8] SOF_SYNC (0) Host: Delay packet(s) until after SOF + // 0x00000040 [6] PREAMBLE_EN (0) Host: Preable enable for LS device on FS hub + // 0x00000010 [4] STOP_TRANS (0) Host: Stop transaction + // 0x00000008 [3] RECEIVE_DATA (0) Host: Receive transaction (IN to host) + // 0x00000004 [2] SEND_DATA (0) Host: Send transaction (OUT from host) + // 0x00000002 [1] SEND_SETUP (0) Host: Send Setup packet + // 0x00000001 [0] START_TRANS (0) Host: Start transaction + io_rw_32 sie_ctrl; + + _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS + // SIE status register + // 0x80000000 [31] DATA_SEQ_ERROR (0) Data Sequence Error + // 0x40000000 [30] ACK_REC (0) ACK received + // 0x20000000 [29] STALL_REC (0) Host: STALL received + // 0x10000000 [28] NAK_REC (0) Host: NAK received + // 0x08000000 [27] RX_TIMEOUT (0) RX timeout is raised by both the host and device if an... + // 0x04000000 [26] RX_OVERFLOW (0) RX overflow is raised by the Serial RX engine if the... + // 0x02000000 [25] BIT_STUFF_ERROR (0) Bit Stuff Error + // 0x01000000 [24] CRC_ERROR (0) CRC Error + // 0x00800000 [23] ENDPOINT_ERROR (0) An endpoint has encountered an error + // 0x00080000 [19] BUS_RESET (0) Device: bus reset received + // 0x00040000 [18] TRANS_COMPLETE (0) Transaction complete + // 0x00020000 [17] SETUP_REC (0) Device: Setup packet received + // 0x00010000 [16] CONNECTED (0) Device: connected + // 0x00001000 [12] RX_SHORT_PACKET (0) Device or Host has received a short packet + // 0x00000800 [11] RESUME (0) Host: Device has initiated a remote resume + // 0x00000400 [10] VBUS_OVER_CURR (0) VBUS over current detected + // 0x00000300 [9:8] SPEED (0x0) Host: device speed + // 0x00000010 [4] SUSPENDED (0) Bus in suspended state + // 0x0000000c [3:2] LINE_STATE (0x0) USB bus line state + // 0x00000001 [0] VBUS_DETECTED (0) Device: VBUS Detected + io_rw_32 sie_status; + + _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL + // interrupt endpoint control register + // 0x0000fffe [15:1] INT_EP_ACTIVE (0x0000) Host: Enable interrupt endpoint 1 -> 15 + io_rw_32 int_ep_ctrl; + + _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS + // Buffer status register + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 buf_status; + + _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE + // Which of the double buffers should be handled + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_ro_32 buf_cpu_should_handle; + + _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT + // Device only: Can be set to ignore the buffer control register for this endpoint in case you... + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 abort; + + _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE + // Device only: Used in conjunction with `EP_ABORT` + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 abort_done; + + _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM + // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register... + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 ep_stall_arm; + + _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL + // Used by the host controller + // 0xf0000000 [31:28] RETRY_COUNT_HI (0x0) Bits 9:6 of nak_retry count + // 0x08000000 [27] EPX_STOPPED_ON_NAK (0) EPX polling has stopped because a nak was received + // 0x04000000 [26] STOP_EPX_ON_NAK (0) Stop polling epx when a nak is received + // 0x03ff0000 [25:16] DELAY_FS (0x010) NAK polling interval for a full speed device + // 0x0000fc00 [15:10] RETRY_COUNT_LO (0x00) Bits 5:0 of nak_retry_count + // 0x000003ff [9:0] DELAY_LS (0x010) NAK polling interval for a low speed device + io_rw_32 nak_poll; + + _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK + // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set + // 0x80000000 [31] EP15_OUT (0) + // 0x40000000 [30] EP15_IN (0) + // 0x20000000 [29] EP14_OUT (0) + // 0x10000000 [28] EP14_IN (0) + // 0x08000000 [27] EP13_OUT (0) + // 0x04000000 [26] EP13_IN (0) + // 0x02000000 [25] EP12_OUT (0) + // 0x01000000 [24] EP12_IN (0) + // 0x00800000 [23] EP11_OUT (0) + // 0x00400000 [22] EP11_IN (0) + // 0x00200000 [21] EP10_OUT (0) + // 0x00100000 [20] EP10_IN (0) + // 0x00080000 [19] EP9_OUT (0) + // 0x00040000 [18] EP9_IN (0) + // 0x00020000 [17] EP8_OUT (0) + // 0x00010000 [16] EP8_IN (0) + // 0x00008000 [15] EP7_OUT (0) + // 0x00004000 [14] EP7_IN (0) + // 0x00002000 [13] EP6_OUT (0) + // 0x00001000 [12] EP6_IN (0) + // 0x00000800 [11] EP5_OUT (0) + // 0x00000400 [10] EP5_IN (0) + // 0x00000200 [9] EP4_OUT (0) + // 0x00000100 [8] EP4_IN (0) + // 0x00000080 [7] EP3_OUT (0) + // 0x00000040 [6] EP3_IN (0) + // 0x00000020 [5] EP2_OUT (0) + // 0x00000010 [4] EP2_IN (0) + // 0x00000008 [3] EP1_OUT (0) + // 0x00000004 [2] EP1_IN (0) + // 0x00000002 [1] EP0_OUT (0) + // 0x00000001 [0] EP0_IN (0) + io_rw_32 ep_nak_stall_status; + + _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING + // Where to connect the USB controller + // 0x80000000 [31] SWAP_DPDM (0) Swap the USB PHY DP and DM pins and all related controls... + // 0x00000010 [4] USBPHY_AS_GPIO (0) Use the usb DP and DM pins as GPIO pins instead of... + // 0x00000008 [3] SOFTCON (0) + // 0x00000004 [2] TO_DIGITAL_PAD (0) + // 0x00000002 [1] TO_EXTPHY (0) + // 0x00000001 [0] TO_PHY (1) + io_rw_32 muxing; + + _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR + // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO + // 0x00000020 [5] OVERCURR_DETECT_EN (0) + // 0x00000010 [4] OVERCURR_DETECT (0) + // 0x00000008 [3] VBUS_DETECT_OVERRIDE_EN (0) + // 0x00000004 [2] VBUS_DETECT (0) + // 0x00000002 [1] VBUS_EN_OVERRIDE_EN (0) + // 0x00000001 [0] VBUS_EN (0) + io_rw_32 pwr; + + _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT + // This register allows for direct control of the USB phy + // 0x02000000 [25] RX_DM_OVERRIDE (0) Override rx_dm value into controller + // 0x01000000 [24] RX_DP_OVERRIDE (0) Override rx_dp value into controller + // 0x00800000 [23] RX_DD_OVERRIDE (0) Override rx_dd value into controller + // 0x00400000 [22] DM_OVV (0) DM over voltage + // 0x00200000 [21] DP_OVV (0) DP over voltage + // 0x00100000 [20] DM_OVCN (0) DM overcurrent + // 0x00080000 [19] DP_OVCN (0) DP overcurrent + // 0x00040000 [18] RX_DM (0) DPM pin state + // 0x00020000 [17] RX_DP (0) DPP pin state + // 0x00010000 [16] RX_DD (0) Differential RX + // 0x00008000 [15] TX_DIFFMODE (0) TX_DIFFMODE=0: Single ended mode + + // 0x00004000 [14] TX_FSSLEW (0) TX_FSSLEW=0: Low speed slew rate + + // 0x00002000 [13] TX_PD (0) TX power down override (if override enable is set) + // 0x00001000 [12] RX_PD (0) RX power down override (if override enable is set) + // 0x00000800 [11] TX_DM (0) Output data + // 0x00000400 [10] TX_DP (0) Output data + // 0x00000200 [9] TX_DM_OE (0) Output enable + // 0x00000100 [8] TX_DP_OE (0) Output enable + // 0x00000040 [6] DM_PULLDN_EN (0) DM pull down enable + // 0x00000020 [5] DM_PULLUP_EN (0) DM pull up enable + // 0x00000010 [4] DM_PULLUP_HISEL (0) Enable the second DM pull up resistor + // 0x00000004 [2] DP_PULLDN_EN (0) DP pull down enable + // 0x00000002 [1] DP_PULLUP_EN (0) DP pull up enable + // 0x00000001 [0] DP_PULLUP_HISEL (0) Enable the second DP pull up resistor + io_rw_32 phy_direct; + + _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE + // Override enable for each control in usbphy_direct + // 0x00040000 [18] RX_DM_OVERRIDE_EN (0) + // 0x00020000 [17] RX_DP_OVERRIDE_EN (0) + // 0x00010000 [16] RX_DD_OVERRIDE_EN (0) + // 0x00008000 [15] TX_DIFFMODE_OVERRIDE_EN (0) + // 0x00001000 [12] DM_PULLUP_OVERRIDE_EN (0) + // 0x00000800 [11] TX_FSSLEW_OVERRIDE_EN (0) + // 0x00000400 [10] TX_PD_OVERRIDE_EN (0) + // 0x00000200 [9] RX_PD_OVERRIDE_EN (0) + // 0x00000100 [8] TX_DM_OVERRIDE_EN (0) + // 0x00000080 [7] TX_DP_OVERRIDE_EN (0) + // 0x00000040 [6] TX_DM_OE_OVERRIDE_EN (0) + // 0x00000020 [5] TX_DP_OE_OVERRIDE_EN (0) + // 0x00000010 [4] DM_PULLDN_EN_OVERRIDE_EN (0) + // 0x00000008 [3] DP_PULLDN_EN_OVERRIDE_EN (0) + // 0x00000004 [2] DP_PULLUP_EN_OVERRIDE_EN (0) + // 0x00000002 [1] DM_PULLUP_HISEL_OVERRIDE_EN (0) + // 0x00000001 [0] DP_PULLUP_HISEL_OVERRIDE_EN (0) + io_rw_32 phy_direct_override; + + _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM + // Used to adjust trim values of USB phy pull down resistors + // 0x00001f00 [12:8] DM_PULLDN_TRIM (0x1f) Value to drive to USB PHY + + // 0x0000001f [4:0] DP_PULLDN_TRIM (0x1f) Value to drive to USB PHY + + io_rw_32 phy_trim; + + _REG_(USB_LINESTATE_TUNING_OFFSET) // USB_LINESTATE_TUNING + // Used for debug only + // 0x00000f00 [11:8] SPARE_FIX (0x0) + // 0x00000080 [7] DEV_LS_WAKE_FIX (1) Device - exit suspend on any non-idle signalling, not... + // 0x00000040 [6] DEV_RX_ERR_QUIESCE (1) Device - suppress repeated errors until the device FSM... + // 0x00000020 [5] SIE_RX_CHATTER_SE0_FIX (1) RX - when recovering from line chatter or bitstuff... + // 0x00000010 [4] SIE_RX_BITSTUFF_FIX (1) RX - when a bitstuff error is signalled by rx_dasm,... + // 0x00000008 [3] DEV_BUFF_CONTROL_DOUBLE_READ_FIX (1) Device - the controller FSM performs two reads of the... + // 0x00000004 [2] MULTI_HUB_FIX (0) Host - increase inter-packet and turnaround timeouts to... + // 0x00000002 [1] LINESTATE_DELAY (0) Device/Host - add an extra 1-bit debounce of linestate sampling + // 0x00000001 [0] RCV_DELAY (0) Device - register the received data to account for hub... + io_rw_32 linestate_tuning; + + _REG_(USB_INTR_OFFSET) // USB_INTR + // Raw Interrupts + // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL + // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG + // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS + // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_ro_32 intr; + + _REG_(USB_INTE_OFFSET) // USB_INTE + // Interrupt Enable + // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL + // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG + // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS + // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_rw_32 inte; + + _REG_(USB_INTF_OFFSET) // USB_INTF + // Interrupt Force + // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL + // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG + // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS + // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_rw_32 intf; + + _REG_(USB_INTS_OFFSET) // USB_INTS + // Interrupt status after masking & forcing + // 0x00800000 [23] EPX_STOPPED_ON_NAK (0) Source: NAK_POLL + // 0x00400000 [22] DEV_SM_WATCHDOG_FIRED (0) Source: DEV_SM_WATCHDOG + // 0x00200000 [21] ENDPOINT_ERROR (0) Source: SIE_STATUS + // 0x00100000 [20] RX_SHORT_PACKET (0) Source: SIE_STATUS + // 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set + // 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set + // 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet + // 0x00010000 [16] SETUP_REQ (0) Device + // 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host + // 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes + // 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes + // 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS + // 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS + // 0x00000400 [10] STALL (0) Source: SIE_STATUS + // 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS + // 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS + // 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS + // 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS + // 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS + // 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set + // 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS + // 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame) + // 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host + // 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i + io_ro_32 ints; + + uint32_t _pad0[25]; + + _REG_(USB_SOF_TIMESTAMP_RAW_OFFSET) // USB_SOF_TIMESTAMP_RAW + // Device only + // 0x001fffff [20:0] SOF_TIMESTAMP_RAW (0x000000) + io_ro_32 sof_timestamp_raw; + + _REG_(USB_SOF_TIMESTAMP_LAST_OFFSET) // USB_SOF_TIMESTAMP_LAST + // Device only + // 0x001fffff [20:0] SOF_TIMESTAMP_LAST (0x000000) + io_ro_32 sof_timestamp_last; + + _REG_(USB_SM_STATE_OFFSET) // USB_SM_STATE + // 0x00000f00 [11:8] RX_DASM (0x0) + // 0x000000e0 [7:5] BC_STATE (0x0) + // 0x0000001f [4:0] STATE (0x00) + io_ro_32 sm_state; + + _REG_(USB_EP_TX_ERROR_OFFSET) // USB_EP_TX_ERROR + // TX error count for each endpoint + // 0xc0000000 [31:30] EP15 (0x0) + // 0x30000000 [29:28] EP14 (0x0) + // 0x0c000000 [27:26] EP13 (0x0) + // 0x03000000 [25:24] EP12 (0x0) + // 0x00c00000 [23:22] EP11 (0x0) + // 0x00300000 [21:20] EP10 (0x0) + // 0x000c0000 [19:18] EP9 (0x0) + // 0x00030000 [17:16] EP8 (0x0) + // 0x0000c000 [15:14] EP7 (0x0) + // 0x00003000 [13:12] EP6 (0x0) + // 0x00000c00 [11:10] EP5 (0x0) + // 0x00000300 [9:8] EP4 (0x0) + // 0x000000c0 [7:6] EP3 (0x0) + // 0x00000030 [5:4] EP2 (0x0) + // 0x0000000c [3:2] EP1 (0x0) + // 0x00000003 [1:0] EP0 (0x0) + io_rw_32 ep_tx_error; + + _REG_(USB_EP_RX_ERROR_OFFSET) // USB_EP_RX_ERROR + // RX error count for each endpoint + // 0x80000000 [31] EP15_SEQ (0) + // 0x40000000 [30] EP15_TRANSACTION (0) + // 0x20000000 [29] EP14_SEQ (0) + // 0x10000000 [28] EP14_TRANSACTION (0) + // 0x08000000 [27] EP13_SEQ (0) + // 0x04000000 [26] EP13_TRANSACTION (0) + // 0x02000000 [25] EP12_SEQ (0) + // 0x01000000 [24] EP12_TRANSACTION (0) + // 0x00800000 [23] EP11_SEQ (0) + // 0x00400000 [22] EP11_TRANSACTION (0) + // 0x00200000 [21] EP10_SEQ (0) + // 0x00100000 [20] EP10_TRANSACTION (0) + // 0x00080000 [19] EP9_SEQ (0) + // 0x00040000 [18] EP9_TRANSACTION (0) + // 0x00020000 [17] EP8_SEQ (0) + // 0x00010000 [16] EP8_TRANSACTION (0) + // 0x00008000 [15] EP7_SEQ (0) + // 0x00004000 [14] EP7_TRANSACTION (0) + // 0x00002000 [13] EP6_SEQ (0) + // 0x00001000 [12] EP6_TRANSACTION (0) + // 0x00000800 [11] EP5_SEQ (0) + // 0x00000400 [10] EP5_TRANSACTION (0) + // 0x00000200 [9] EP4_SEQ (0) + // 0x00000100 [8] EP4_TRANSACTION (0) + // 0x00000080 [7] EP3_SEQ (0) + // 0x00000040 [6] EP3_TRANSACTION (0) + // 0x00000020 [5] EP2_SEQ (0) + // 0x00000010 [4] EP2_TRANSACTION (0) + // 0x00000008 [3] EP1_SEQ (0) + // 0x00000004 [2] EP1_TRANSACTION (0) + // 0x00000002 [1] EP0_SEQ (0) + // 0x00000001 [0] EP0_TRANSACTION (0) + io_rw_32 ep_rx_error; + + _REG_(USB_DEV_SM_WATCHDOG_OFFSET) // USB_DEV_SM_WATCHDOG + // Watchdog that forces the device state machine to idle and raises an interrupt if the device... + // 0x00100000 [20] FIRED (0) + // 0x00080000 [19] RESET (0) Set to 1 to forcibly reset the device state machine on... + // 0x00040000 [18] ENABLE (0) + // 0x0003ffff [17:0] LIMIT (0x00000) + io_rw_32 dev_sm_watchdog; +} usb_hw_t; + +#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE) +static_assert(sizeof (usb_hw_t) == 0x0118, ""); + +#endif // _HARDWARE_STRUCTS_USB_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/usb_dpram.h b/lib/pico-sdk/rp2350/hardware/structs/usb_dpram.h new file mode 100644 index 000000000000..aaa4ec58b861 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/usb_dpram.h @@ -0,0 +1,128 @@ +/** + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _HARDWARE_STRUCTS_USB_DPRAM_H +#define _HARDWARE_STRUCTS_USB_DPRAM_H + +#include "hardware/address_mapped.h" +#include "hardware/regs/usb.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_usb +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/usb.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + + +// 0-15 +#define USB_NUM_ENDPOINTS 16 + +// allow user to restrict number of endpoints available to save RAN +#ifndef USB_MAX_ENDPOINTS +#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS +#endif + +// 1-15 +#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1) + +// Endpoint buffer control bits +#define USB_BUF_CTRL_FULL 0x00008000u +#define USB_BUF_CTRL_LAST 0x00004000u +#define USB_BUF_CTRL_DATA0_PID 0x00000000u +#define USB_BUF_CTRL_DATA1_PID 0x00002000u +#define USB_BUF_CTRL_SEL 0x00001000u +#define USB_BUF_CTRL_STALL 0x00000800u +#define USB_BUF_CTRL_AVAIL 0x00000400u +#define USB_BUF_CTRL_LEN_MASK 0x000003FFu +#define USB_BUF_CTRL_LEN_LSB 0 + +// ep_inout_ctrl bits +#define EP_CTRL_ENABLE_BITS (1u << 31u) +#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30) +#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29) +#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28) +#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16) +#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17) +#define EP_CTRL_BUFFER_TYPE_LSB 26u +#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u + +#define USB_DPRAM_SIZE 4096u + +// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb +// Allow user to claim some of the USB RAM for themselves +#ifndef USB_DPRAM_MAX +#define USB_DPRAM_MAX USB_DPRAM_SIZE +#endif + +// Define maximum packet sizes +#define USB_MAX_ISO_PACKET_SIZE 1023 +#define USB_MAX_PACKET_SIZE 64 + +typedef struct { + // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses + volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets + + // Starts at ep1 + struct usb_device_dpram_ep_ctrl { + io_rw_32 in; + io_rw_32 out; + } ep_ctrl[USB_NUM_ENDPOINTS - 1]; + + // Starts at ep0 + struct usb_device_dpram_ep_buf_ctrl { + io_rw_32 in; + io_rw_32 out; + } ep_buf_ctrl[USB_NUM_ENDPOINTS]; + + // EP0 buffers are fixed. Assumes single buffered mode for EP0 + uint8_t ep0_buf_a[0x40]; + uint8_t ep0_buf_b[0x40]; + + // Rest of DPRAM can be carved up as needed + uint8_t epx_data[USB_DPRAM_MAX - 0x180]; +} usb_device_dpram_t; + +static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, ""); +static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, ""); + +typedef struct { + // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses + volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets + + // Interrupt endpoint control 1 -> 15 + struct usb_host_dpram_ep_ctrl { + io_rw_32 ctrl; + io_rw_32 spare; + } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + io_rw_32 epx_buf_ctrl; + io_rw_32 _spare0; + + // Interrupt endpoint buffer control + struct usb_host_dpram_ep_buf_ctrl { + io_rw_32 ctrl; + io_rw_32 spare; + } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; + + io_rw_32 epx_ctrl; + + uint8_t _spare1[124]; + + // Should start at 0x180 + uint8_t epx_data[USB_DPRAM_MAX - 0x180]; +} usb_host_dpram_t; + +static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, ""); +static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, ""); + +#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE) +#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE) + +static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, ""); + +#endif // _HARDWARE_STRUCTS_USB_DPRAM_H \ No newline at end of file diff --git a/lib/pico-sdk/rp2350/hardware/structs/watchdog.h b/lib/pico-sdk/rp2350/hardware/structs/watchdog.h new file mode 100644 index 000000000000..19c7bfaeea92 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/watchdog.h @@ -0,0 +1,59 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_WATCHDOG_H +#define _HARDWARE_STRUCTS_WATCHDOG_H + +/** + * \file rp2350/watchdog.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/watchdog.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_watchdog +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL + // Watchdog control + + // 0x80000000 [31] TRIGGER (0) Trigger a watchdog reset + // 0x40000000 [30] ENABLE (0) When not enabled the watchdog timer is paused + // 0x04000000 [26] PAUSE_DBG1 (1) Pause the watchdog timer when processor 1 is in debug mode + // 0x02000000 [25] PAUSE_DBG0 (1) Pause the watchdog timer when processor 0 is in debug mode + // 0x01000000 [24] PAUSE_JTAG (1) Pause the watchdog timer when JTAG is accessing the bus fabric + // 0x00ffffff [23:0] TIME (0x000000) Indicates the time in usec before a watchdog reset will... + io_rw_32 ctrl; + + _REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD + // Load the watchdog timer + // 0x00ffffff [23:0] LOAD (0x000000) + io_wo_32 load; + + _REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON + // Logs the reason for the last reset + // 0x00000002 [1] FORCE (0) + // 0x00000001 [0] TIMER (0) + io_ro_32 reason; + + // (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes) + _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0 + // Scratch register + // 0xffffffff [31:0] SCRATCH0 (0x00000000) + io_rw_32 scratch[8]; +} watchdog_hw_t; + +#define watchdog_hw ((watchdog_hw_t *)WATCHDOG_BASE) +static_assert(sizeof (watchdog_hw_t) == 0x002c, ""); + +#endif // _HARDWARE_STRUCTS_WATCHDOG_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/xip.h b/lib/pico-sdk/rp2350/hardware/structs/xip.h new file mode 100644 index 000000000000..ee5cb2366832 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/xip.h @@ -0,0 +1,79 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XIP_H +#define _HARDWARE_STRUCTS_XIP_H + +/** + * \file rp2350/xip.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/xip.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_xip +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xip.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(XIP_CTRL_OFFSET) // XIP_CTRL + // Cache control register + // 0x00000800 [11] WRITABLE_M1 (0) If 1, enable writes to XIP memory window 1 (addresses... + // 0x00000400 [10] WRITABLE_M0 (0) If 1, enable writes to XIP memory window 0 (addresses... + // 0x00000200 [9] SPLIT_WAYS (0) When 1, route all cached+Secure accesses to way 0 of the... + // 0x00000100 [8] MAINT_NONSEC (0) When 0, Non-secure accesses to the cache maintenance... + // 0x00000080 [7] NO_UNTRANSLATED_NONSEC (1) When 1, Non-secure accesses to the uncached,... + // 0x00000040 [6] NO_UNTRANSLATED_SEC (0) When 1, Secure accesses to the uncached, untranslated... + // 0x00000020 [5] NO_UNCACHED_NONSEC (0) When 1, Non-secure accesses to the uncached window... + // 0x00000010 [4] NO_UNCACHED_SEC (0) When 1, Secure accesses to the uncached window... + // 0x00000008 [3] POWER_DOWN (0) When 1, the cache memories are powered down + // 0x00000002 [1] EN_NONSECURE (1) When 1, enable the cache for Non-secure accesses + // 0x00000001 [0] EN_SECURE (1) When 1, enable the cache for Secure accesses + io_rw_32 ctrl; + + uint32_t _pad0; + + _REG_(XIP_STAT_OFFSET) // XIP_STAT + // 0x00000004 [2] FIFO_FULL (0) When 1, indicates the XIP streaming FIFO is completely full + // 0x00000002 [1] FIFO_EMPTY (1) When 1, indicates the XIP streaming FIFO is completely empty + io_ro_32 stat; + + _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT + // Cache Hit counter + // 0xffffffff [31:0] CTR_HIT (0x00000000) A 32 bit saturating counter that increments upon each... + io_rw_32 ctr_hit; + + _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC + // Cache Access counter + // 0xffffffff [31:0] CTR_ACC (0x00000000) A 32 bit saturating counter that increments upon each... + io_rw_32 ctr_acc; + + _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR + // FIFO stream address + // 0xfffffffc [31:2] STREAM_ADDR (0x00000000) The address of the next word to be streamed from flash... + io_rw_32 stream_addr; + + _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR + // FIFO stream control + // 0x003fffff [21:0] STREAM_CTR (0x000000) Write a nonzero value to start a streaming read + io_rw_32 stream_ctr; + + _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO + // FIFO stream data + // 0xffffffff [31:0] STREAM_FIFO (0x00000000) Streamed data is buffered here, for retrieval by the system DMA + io_ro_32 stream_fifo; +} xip_ctrl_hw_t; + +#define xip_ctrl_hw ((xip_ctrl_hw_t *)XIP_CTRL_BASE) +static_assert(sizeof (xip_ctrl_hw_t) == 0x0020, ""); + +#endif // _HARDWARE_STRUCTS_XIP_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/xip_aux.h b/lib/pico-sdk/rp2350/hardware/structs/xip_aux.h new file mode 100644 index 000000000000..1e1caf8c7880 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/xip_aux.h @@ -0,0 +1,51 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XIP_AUX_H +#define _HARDWARE_STRUCTS_XIP_AUX_H + +/** + * \file rp2350/xip_aux.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/xip_aux.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_xip_aux +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xip_aux.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +typedef struct { + _REG_(XIP_AUX_STREAM_OFFSET) // XIP_AUX_STREAM + // Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) + // 0xffffffff [31:0] STREAM (0x00000000) + io_ro_32 stream; + + _REG_(XIP_AUX_QMI_DIRECT_TX_OFFSET) // XIP_AUX_QMI_DIRECT_TX + // Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) + // 0x00100000 [20] NOPUSH (0) Inhibit the RX FIFO push that would correspond to this... + // 0x00080000 [19] OE (0) Output enable (active-high) + // 0x00040000 [18] DWIDTH (0) Data width + // 0x00030000 [17:16] IWIDTH (0x0) Configure whether this FIFO record is transferred with... + // 0x0000ffff [15:0] DATA (0x0000) Data pushed here will be clocked out falling edges of... + io_wo_32 qmi_direct_tx; + + _REG_(XIP_AUX_QMI_DIRECT_RX_OFFSET) // XIP_AUX_QMI_DIRECT_RX + // Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) + // 0x0000ffff [15:0] QMI_DIRECT_RX (0x0000) With each byte clocked out on the serial interface, one... + io_ro_32 qmi_direct_rx; +} xip_aux_hw_t; + +#define xip_aux_hw ((xip_aux_hw_t *)XIP_AUX_BASE) +static_assert(sizeof (xip_aux_hw_t) == 0x000c, ""); + +#endif // _HARDWARE_STRUCTS_XIP_AUX_H + diff --git a/lib/pico-sdk/rp2350/hardware/structs/xip_ctrl.h b/lib/pico-sdk/rp2350/hardware/structs/xip_ctrl.h new file mode 100644 index 000000000000..c31569b60fd9 --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/xip_ctrl.h @@ -0,0 +1,11 @@ +/** + * Copyright (c) 2024 Raspberry Pi (Trading) Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +// Support old header for compatibility (and if included, support old variable name) +#include "hardware/structs/xip.h" +#define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS +#define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS +#define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS diff --git a/lib/pico-sdk/rp2350/hardware/structs/xosc.h b/lib/pico-sdk/rp2350/hardware/structs/xosc.h new file mode 100644 index 000000000000..dca0c05e8c6d --- /dev/null +++ b/lib/pico-sdk/rp2350/hardware/structs/xosc.h @@ -0,0 +1,64 @@ +// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT + +/** + * Copyright (c) 2024 Raspberry Pi Ltd. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _HARDWARE_STRUCTS_XOSC_H +#define _HARDWARE_STRUCTS_XOSC_H + +/** + * \file rp2350/xosc.h + */ + +#include "hardware/address_mapped.h" +#include "hardware/regs/xosc.h" + +// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_xosc +// +// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) +// _REG_(x) will link to the corresponding register in hardware/regs/xosc.h. +// +// Bit-field descriptions are of the form: +// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION + +/// \tag::xosc_hw[] +typedef struct { + _REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL + // Crystal Oscillator Control + // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to DISABLE and the... + // 0x00000fff [11:0] FREQ_RANGE (-) The 12-bit code is intended to give some protection... + io_rw_32 ctrl; + + _REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS + // Crystal Oscillator Status + // 0x80000000 [31] STABLE (0) Oscillator is running and stable + // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or... + // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and... + // 0x00000003 [1:0] FREQ_RANGE (-) The current frequency range setting + io_rw_32 status; + + _REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT + // Crystal Oscillator pause control + // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the XOSC + + io_rw_32 dormant; + + _REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP + // Controls the startup delay + // 0x00100000 [20] X4 (-) Multiplies the startup_delay by 4, just in case + // 0x00003fff [13:0] DELAY (-) in multiples of 256*xtal_period + io_rw_32 startup; + + _REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT + // A down counter running at the XOSC frequency which counts to zero and stops. + // 0x0000ffff [15:0] COUNT (0x0000) + io_rw_32 count; +} xosc_hw_t; +/// \end::xosc_hw[] + +#define xosc_hw ((xosc_hw_t *)XOSC_BASE) +static_assert(sizeof (xosc_hw_t) == 0x0014, ""); + +#endif // _HARDWARE_STRUCTS_XOSC_H + diff --git a/lib/rp2040/cmsis_include/RP2040.h b/lib/rp2040/cmsis_include/RP2040.h deleted file mode 100644 index a29b9e09537d..000000000000 --- a/lib/rp2040/cmsis_include/RP2040.h +++ /dev/null @@ -1,109 +0,0 @@ -/*************************************************************************//** - * @file RP2040.h - * @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for - * Device RP2040 - * @version V1.0.0 - * @date 5. May 2021 - *****************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CMSIS_RP2040_H_ -#define _CMSIS_RP2040_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ - -typedef enum -{ - /* ======================================= ARM Cortex-M0+ Specific Interrupt Numbers ======================================= */ - Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ - SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ - PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ - SysTick_IRQn = -1, /*!< -1 System Tick Timer */ - /* =========================================== RP2040 Specific Interrupt Numbers =========================================== */ - TIMER_IRQ_0_IRQn = 0, /*!< 0 TIMER_IRQ_0 */ - TIMER_IRQ_1_IRQn = 1, /*!< 1 TIMER_IRQ_1 */ - TIMER_IRQ_2_IRQn = 2, /*!< 2 TIMER_IRQ_2 */ - TIMER_IRQ_3_IRQn = 3, /*!< 3 TIMER_IRQ_3 */ - PWM_IRQ_WRAP_IRQn = 4, /*!< 4 PWM_IRQ_WRAP */ - USBCTRL_IRQ_IRQn = 5, /*!< 5 USBCTRL_IRQ */ - XIP_IRQ_IRQn = 6, /*!< 6 XIP_IRQ */ - PIO0_IRQ_0_IRQn = 7, /*!< 7 PIO0_IRQ_0 */ - PIO0_IRQ_1_IRQn = 8, /*!< 8 PIO0_IRQ_1 */ - PIO1_IRQ_0_IRQn = 9, /*!< 9 PIO1_IRQ_0 */ - PIO1_IRQ_1_IRQn = 10, /*!< 10 PIO1_IRQ_1 */ - DMA_IRQ_0_IRQn = 11, /*!< 11 DMA_IRQ_0 */ - DMA_IRQ_1_IRQn = 12, /*!< 12 DMA_IRQ_1 */ - IO_IRQ_BANK0_IRQn = 13, /*!< 13 IO_IRQ_BANK0 */ - IO_IRQ_QSPI_IRQn = 14, /*!< 14 IO_IRQ_QSPI */ - SIO_IRQ_PROC0_IRQn = 15, /*!< 15 SIO_IRQ_PROC0 */ - SIO_IRQ_PROC1_IRQn = 16, /*!< 16 SIO_IRQ_PROC1 */ - CLOCKS_IRQ_IRQn = 17, /*!< 17 CLOCKS_IRQ */ - SPI0_IRQ_IRQn = 18, /*!< 18 SPI0_IRQ */ - SPI1_IRQ_IRQn = 19, /*!< 19 SPI1_IRQ */ - UART0_IRQ_IRQn = 20, /*!< 20 UART0_IRQ */ - UART1_IRQ_IRQn = 21, /*!< 21 UART1_IRQ */ - ADC_IRQ_FIFO_IRQn = 22, /*!< 22 ADC_IRQ_FIFO */ - I2C0_IRQ_IRQn = 23, /*!< 23 I2C0_IRQ */ - I2C1_IRQ_IRQn = 24, /*!< 24 I2C1_IRQ */ - RTC_IRQ_IRQn = 25 /*!< 25 RTC_IRQ */ -} IRQn_Type; - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* ========================== Configuration of the ARM Cortex-M0+ Processor and Core Peripherals =========================== */ -#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ -#define __MPU_PRESENT 1 /*!< MPU present */ -#define __FPU_PRESENT 0 /*!< FPU present */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ -#include "system_RP2040.h" /*!< RP2040 System */ - -#ifndef __IM /*!< Fallback for older CMSIS versions */ -#define __IM __I -#endif -#ifndef __OM /*!< Fallback for older CMSIS versions */ -#define __OM __O -#endif -#ifndef __IOM /*!< Fallback for older CMSIS versions */ -#define __IOM __IO -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* _CMSIS_RP2040_H */ diff --git a/lib/rp2040/hardware/platform_defs.h b/lib/rp2040/hardware/platform_defs.h deleted file mode 100644 index 437594c903fc..000000000000 --- a/lib/rp2040/hardware/platform_defs.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_PLATFORM_DEFS_H -#define _HARDWARE_PLATFORM_DEFS_H - -// This header is included from C and assembler - only define macros - -#ifndef _u -#ifdef __ASSEMBLER__ -#define _u(x) x -#else -#define _u(x) x ## u -#endif -#endif - -#define NUM_CORES _u(2) -#define NUM_DMA_CHANNELS _u(12) -#define NUM_IRQS _u(32) -#define NUM_PIOS _u(2) -#define NUM_PIO_STATE_MACHINES _u(4) -#define NUM_PWM_SLICES _u(8) -#define NUM_SPIN_LOCKS _u(32) -#define NUM_UARTS _u(2) -#define NUM_I2CS _u(2) -#define NUM_SPIS _u(2) - -#define NUM_ADC_CHANNELS _u(5) - -#define NUM_BANK0_GPIOS _u(30) - -#define PIO_INSTRUCTION_COUNT _u(32) - -#define XOSC_MHZ _u(12) - -// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_standard_link -#ifndef PICO_STACK_SIZE -#define PICO_STACK_SIZE _u(0x800) -#endif - -// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_standard_link -#ifndef PICO_HEAP_SIZE -#define PICO_HEAP_SIZE _u(0x800) -#endif - -// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_runtime -#ifndef PICO_NO_RAM_VECTOR_TABLE -#define PICO_NO_RAM_VECTOR_TABLE 0 -#endif - -#endif - diff --git a/lib/rp2040/hardware/regs/dreq.h b/lib/rp2040/hardware/regs/dreq.h deleted file mode 100644 index 9de9dd5fde5e..000000000000 --- a/lib/rp2040/hardware/regs/dreq.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _DREQ_H_ -#define _DREQ_H_ - -#define DREQ_PIO0_TX0 0x0 -#define DREQ_PIO0_TX1 0x1 -#define DREQ_PIO0_TX2 0x2 -#define DREQ_PIO0_TX3 0x3 -#define DREQ_PIO0_RX0 0x4 -#define DREQ_PIO0_RX1 0x5 -#define DREQ_PIO0_RX2 0x6 -#define DREQ_PIO0_RX3 0x7 -#define DREQ_PIO1_TX0 0x8 -#define DREQ_PIO1_TX1 0x9 -#define DREQ_PIO1_TX2 0xa -#define DREQ_PIO1_TX3 0xb -#define DREQ_PIO1_RX0 0xc -#define DREQ_PIO1_RX1 0xd -#define DREQ_PIO1_RX2 0xe -#define DREQ_PIO1_RX3 0xf -#define DREQ_SPI0_TX 0x10 -#define DREQ_SPI0_RX 0x11 -#define DREQ_SPI1_TX 0x12 -#define DREQ_SPI1_RX 0x13 -#define DREQ_UART0_TX 0x14 -#define DREQ_UART0_RX 0x15 -#define DREQ_UART1_TX 0x16 -#define DREQ_UART1_RX 0x17 -#define DREQ_PWM_WRAP0 0x18 -#define DREQ_PWM_WRAP1 0x19 -#define DREQ_PWM_WRAP2 0x1a -#define DREQ_PWM_WRAP3 0x1b -#define DREQ_PWM_WRAP4 0x1c -#define DREQ_PWM_WRAP5 0x1d -#define DREQ_PWM_WRAP6 0x1e -#define DREQ_PWM_WRAP7 0x1f -#define DREQ_I2C0_TX 0x20 -#define DREQ_I2C0_RX 0x21 -#define DREQ_I2C1_TX 0x22 -#define DREQ_I2C1_RX 0x23 -#define DREQ_ADC 0x24 -#define DREQ_XIP_STREAM 0x25 -#define DREQ_XIP_SSITX 0x26 -#define DREQ_XIP_SSIRX 0x27 - -#endif // _DREQ_H_ diff --git a/lib/rp2040/hardware/regs/intctrl.h b/lib/rp2040/hardware/regs/intctrl.h deleted file mode 100644 index dec7e36eaf95..000000000000 --- a/lib/rp2040/hardware/regs/intctrl.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _INTCTRL_H_ -#define _INTCTRL_H_ - -#define TIMER_IRQ_0 0 -#define TIMER_IRQ_1 1 -#define TIMER_IRQ_2 2 -#define TIMER_IRQ_3 3 -#define PWM_IRQ_WRAP 4 -#define USBCTRL_IRQ 5 -#define XIP_IRQ 6 -#define PIO0_IRQ_0 7 -#define PIO0_IRQ_1 8 -#define PIO1_IRQ_0 9 -#define PIO1_IRQ_1 10 -#define DMA_IRQ_0 11 -#define DMA_IRQ_1 12 -#define IO_IRQ_BANK0 13 -#define IO_IRQ_QSPI 14 -#define SIO_IRQ_PROC0 15 -#define SIO_IRQ_PROC1 16 -#define CLOCKS_IRQ 17 -#define SPI0_IRQ 18 -#define SPI1_IRQ 19 -#define UART0_IRQ 20 -#define UART1_IRQ 21 -#define ADC_IRQ_FIFO 22 -#define I2C0_IRQ 23 -#define I2C1_IRQ 24 -#define RTC_IRQ 25 - -#define isr_timer_0 isr_irq0 -#define isr_timer_1 isr_irq1 -#define isr_timer_2 isr_irq2 -#define isr_timer_3 isr_irq3 -#define isr_pwm_wrap isr_irq4 -#define isr_usbctrl isr_irq5 -#define isr_xip isr_irq6 -#define isr_pio0_0 isr_irq7 -#define isr_pio0_1 isr_irq8 -#define isr_pio1_0 isr_irq9 -#define isr_pio1_1 isr_irq10 -#define isr_dma_0 isr_irq11 -#define isr_dma_1 isr_irq12 -#define isr_io_bank0 isr_irq13 -#define isr_io_qspi isr_irq14 -#define isr_sio_proc0 isr_irq15 -#define isr_sio_proc1 isr_irq16 -#define isr_clocks isr_irq17 -#define isr_spi0 isr_irq18 -#define isr_spi1 isr_irq19 -#define isr_uart0 isr_irq20 -#define isr_uart1 isr_irq21 -#define isr_adc_fifo isr_irq22 -#define isr_i2c0 isr_irq23 -#define isr_i2c1 isr_irq24 -#define isr_rtc isr_irq25 - -#endif // _INTCTRL_H_ diff --git a/lib/rp2040/hardware/structs/adc.h b/lib/rp2040/hardware/structs/adc.h deleted file mode 100644 index 559b5f177274..000000000000 --- a/lib/rp2040/hardware/structs/adc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_ADC_H -#define _HARDWARE_STRUCTS_ADC_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/adc.h" - -typedef struct { - io_rw_32 cs; - io_rw_32 result; - io_rw_32 fcs; - io_rw_32 fifo; - io_rw_32 div; - io_rw_32 intr; - io_rw_32 inte; - io_rw_32 intf; - io_rw_32 ints; -} adc_hw_t; - -check_hw_layout(adc_hw_t, ints, ADC_INTS_OFFSET); - -#define adc_hw ((adc_hw_t *const)ADC_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/bus_ctrl.h b/lib/rp2040/hardware/structs/bus_ctrl.h deleted file mode 100644 index ce95a7c19843..000000000000 --- a/lib/rp2040/hardware/structs/bus_ctrl.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_BUS_CTRL_H -#define _HARDWARE_STRUCTS_BUS_CTRL_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/busctrl.h" - -enum bus_ctrl_perf_counter { - arbiter_rom_perf_event_access = 19, - arbiter_rom_perf_event_access_contested = 18, - arbiter_xip_main_perf_event_access = 17, - arbiter_xip_main_perf_event_access_contested = 16, - arbiter_sram0_perf_event_access = 15, - arbiter_sram0_perf_event_access_contested = 14, - arbiter_sram1_perf_event_access = 13, - arbiter_sram1_perf_event_access_contested = 12, - arbiter_sram2_perf_event_access = 11, - arbiter_sram2_perf_event_access_contested = 10, - arbiter_sram3_perf_event_access = 9, - arbiter_sram3_perf_event_access_contested = 8, - arbiter_sram4_perf_event_access = 7, - arbiter_sram4_perf_event_access_contested = 6, - arbiter_sram5_perf_event_access = 5, - arbiter_sram5_perf_event_access_contested = 4, - arbiter_fastperi_perf_event_access = 3, - arbiter_fastperi_perf_event_access_contested = 2, - arbiter_apb_perf_event_access = 1, - arbiter_apb_perf_event_access_contested = 0 -}; - -typedef struct { - io_rw_32 priority; - io_ro_32 priority_ack; - struct { - io_rw_32 value; - io_rw_32 sel; - } counter[4]; -} bus_ctrl_hw_t; - -check_hw_layout(bus_ctrl_hw_t, counter[0].value, BUSCTRL_PERFCTR0_OFFSET); - -#define bus_ctrl_hw ((bus_ctrl_hw_t *const)BUSCTRL_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/clocks.h b/lib/rp2040/hardware/structs/clocks.h deleted file mode 100644 index 489876d16980..000000000000 --- a/lib/rp2040/hardware/structs/clocks.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_CLOCKS_H -#define _HARDWARE_STRUCTS_CLOCKS_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/clocks.h" - -/*! \brief Enumeration identifying a hardware clock - * \ingroup hardware_clocks - */ -/// \tag::clkenum[] -enum clock_index { - clk_gpout0 = 0, ///< GPIO Muxing 0 - clk_gpout1, ///< GPIO Muxing 1 - clk_gpout2, ///< GPIO Muxing 2 - clk_gpout3, ///< GPIO Muxing 3 - clk_ref, ///< Watchdog and timers reference clock - clk_sys, ///< Processors, bus fabric, memory, memory mapped registers - clk_peri, ///< Peripheral clock for UART and SPI - clk_usb, ///< USB clock - clk_adc, ///< ADC clock - clk_rtc, ///< Real time clock - CLK_COUNT -}; -/// \end::clkenum[] - -/// \tag::clock_hw[] -typedef struct { - io_rw_32 ctrl; - io_rw_32 div; - io_rw_32 selected; -} clock_hw_t; -/// \end::clock_hw[] - -typedef struct { - io_rw_32 ref_khz; - io_rw_32 min_khz; - io_rw_32 max_khz; - io_rw_32 delay; - io_rw_32 interval; - io_rw_32 src; - io_ro_32 status; - io_ro_32 result; -} fc_hw_t; - -typedef struct { - clock_hw_t clk[CLK_COUNT]; - struct { - io_rw_32 ctrl; - io_rw_32 status; - } resus; - fc_hw_t fc0; - io_rw_32 wake_en0; - io_rw_32 wake_en1; - io_rw_32 sleep_en0; - io_rw_32 sleep_en1; - io_rw_32 enabled0; - io_rw_32 enabled1; - io_rw_32 intr; - io_rw_32 inte; - io_rw_32 intf; - io_rw_32 ints; -} clocks_hw_t; - -#define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE) -#endif diff --git a/lib/rp2040/hardware/structs/dma.h b/lib/rp2040/hardware/structs/dma.h deleted file mode 100644 index 06cdf7927503..000000000000 --- a/lib/rp2040/hardware/structs/dma.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_DMA_H -#define _HARDWARE_STRUCTS_DMA_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/dma.h" - -typedef struct { - io_rw_32 read_addr; - io_rw_32 write_addr; - io_rw_32 transfer_count; - io_rw_32 ctrl_trig; - io_rw_32 al1_ctrl; - io_rw_32 al1_read_addr; - io_rw_32 al1_write_addr; - io_rw_32 al1_transfer_count_trig; - io_rw_32 al2_ctrl; - io_rw_32 al2_transfer_count; - io_rw_32 al2_read_addr; - io_rw_32 al2_write_addr_trig; - io_rw_32 al3_ctrl; - io_rw_32 al3_write_addr; - io_rw_32 al3_transfer_count; - io_rw_32 al3_read_addr_trig; -} dma_channel_hw_t; - -typedef struct { - dma_channel_hw_t ch[NUM_DMA_CHANNELS]; - uint32_t _pad0[16 * (16 - NUM_DMA_CHANNELS)]; - io_ro_32 intr; - io_rw_32 inte0; - io_rw_32 intf0; - io_rw_32 ints0; - uint32_t _pad1[1]; - io_rw_32 inte1; - io_rw_32 intf1; - io_rw_32 ints1; - io_rw_32 timer[4]; - io_wo_32 multi_channel_trigger; - io_rw_32 sniff_ctrl; - io_rw_32 sniff_data; - uint32_t _pad2[1]; - io_ro_32 fifo_levels; - io_wo_32 abort; -} dma_hw_t; - -typedef struct { - struct dma_debug_hw_channel { - io_ro_32 ctrdeq; - io_ro_32 tcr; - uint32_t pad[14]; - } ch[NUM_DMA_CHANNELS]; -} dma_debug_hw_t; - -#define dma_hw ((dma_hw_t *const)DMA_BASE) -#define dma_debug_hw ((dma_debug_hw_t *const)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET)) - -#endif diff --git a/lib/rp2040/hardware/structs/i2c.h b/lib/rp2040/hardware/structs/i2c.h deleted file mode 100644 index 1a58c50dd817..000000000000 --- a/lib/rp2040/hardware/structs/i2c.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_I2C_H -#define _HARDWARE_STRUCTS_I2C_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/i2c.h" - -typedef struct { - io_rw_32 con; - io_rw_32 tar; - io_rw_32 sar; - uint32_t _pad0; - io_rw_32 data_cmd; - io_rw_32 ss_scl_hcnt; - io_rw_32 ss_scl_lcnt; - io_rw_32 fs_scl_hcnt; - io_rw_32 fs_scl_lcnt; - uint32_t _pad1[2]; - io_rw_32 intr_stat; - io_rw_32 intr_mask; - io_rw_32 raw_intr_stat; - io_rw_32 rx_tl; - io_rw_32 tx_tl; - io_rw_32 clr_intr; - io_rw_32 clr_rx_under; - io_rw_32 clr_rx_over; - io_rw_32 clr_tx_over; - io_rw_32 clr_rd_req; - io_rw_32 clr_tx_abrt; - io_rw_32 clr_rx_done; - io_rw_32 clr_activity; - io_rw_32 clr_stop_det; - io_rw_32 clr_start_det; - io_rw_32 clr_gen_call; - io_rw_32 enable; - io_rw_32 status; - io_rw_32 txflr; - io_rw_32 rxflr; - io_rw_32 sda_hold; - io_rw_32 tx_abrt_source; - io_rw_32 slv_data_nack_only; - io_rw_32 dma_cr; - io_rw_32 dma_tdlr; - io_rw_32 dma_rdlr; - io_rw_32 sda_setup; - io_rw_32 ack_general_call; - io_rw_32 enable_status; - io_rw_32 fs_spklen; - uint32_t _pad2; - io_rw_32 clr_restart_det; -} i2c_hw_t; - -#define i2c0_hw ((i2c_hw_t *const)I2C0_BASE) -#define i2c1_hw ((i2c_hw_t *const)I2C1_BASE) - -// List of configuration constants for the Synopsys I2C hardware (you may see -// references to these in I2C register header; these are *fixed* values, -// set at hardware design time): - -// IC_ULTRA_FAST_MODE ................ 0x0 -// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 -// IC_UFM_SCL_LOW_COUNT .............. 0x0008 -// IC_UFM_SCL_HIGH_COUNT ............. 0x0006 -// IC_TX_TL .......................... 0x0 -// IC_TX_CMD_BLOCK ................... 0x1 -// IC_HAS_DMA ........................ 0x1 -// IC_HAS_ASYNC_FIFO ................. 0x0 -// IC_SMBUS_ARP ...................... 0x0 -// IC_FIRST_DATA_BYTE_STATUS ......... 0x1 -// IC_INTR_IO ........................ 0x1 -// IC_MASTER_MODE .................... 0x1 -// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 -// IC_INTR_POL ....................... 0x1 -// IC_OPTIONAL_SAR ................... 0x0 -// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 -// IC_DEFAULT_SLAVE_ADDR ............. 0x055 -// IC_DEFAULT_HS_SPKLEN .............. 0x1 -// IC_FS_SCL_HIGH_COUNT .............. 0x0006 -// IC_HS_SCL_LOW_COUNT ............... 0x0008 -// IC_DEVICE_ID_VALUE ................ 0x0 -// IC_10BITADDR_MASTER ............... 0x0 -// IC_CLK_FREQ_OPTIMIZATION .......... 0x0 -// IC_DEFAULT_FS_SPKLEN .............. 0x7 -// IC_ADD_ENCODED_PARAMS ............. 0x0 -// IC_DEFAULT_SDA_HOLD ............... 0x000001 -// IC_DEFAULT_SDA_SETUP .............. 0x64 -// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 -// IC_CLOCK_PERIOD ................... 100 -// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 -// IC_RESTART_EN ..................... 0x1 -// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 -// IC_BUS_CLEAR_FEATURE .............. 0x0 -// IC_CAP_LOADING .................... 100 -// IC_FS_SCL_LOW_COUNT ............... 0x000d -// APB_DATA_WIDTH .................... 32 -// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff -// IC_SLV_DATA_NACK_ONLY ............. 0x1 -// IC_10BITADDR_SLAVE ................ 0x0 -// IC_CLK_TYPE ....................... 0x0 -// IC_SMBUS_UDID_MSB ................. 0x0 -// IC_SMBUS_SUSPEND_ALERT ............ 0x0 -// IC_HS_SCL_HIGH_COUNT .............. 0x0006 -// IC_SLV_RESTART_DET_EN ............. 0x1 -// IC_SMBUS .......................... 0x0 -// IC_OPTIONAL_SAR_DEFAULT ........... 0x0 -// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 -// IC_USE_COUNTS ..................... 0x0 -// IC_RX_BUFFER_DEPTH ................ 16 -// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff -// IC_RX_FULL_HLD_BUS_EN ............. 0x1 -// IC_SLAVE_DISABLE .................. 0x1 -// IC_RX_TL .......................... 0x0 -// IC_DEVICE_ID ...................... 0x0 -// IC_HC_COUNT_VALUES ................ 0x0 -// I2C_DYNAMIC_TAR_UPDATE ............ 0 -// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff -// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff -// IC_HS_MASTER_CODE ................. 0x1 -// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff -// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff -// IC_SS_SCL_HIGH_COUNT .............. 0x0028 -// IC_SS_SCL_LOW_COUNT ............... 0x002f -// IC_MAX_SPEED_MODE ................. 0x2 -// IC_STAT_FOR_CLK_STRETCH ........... 0x0 -// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 -// IC_DEFAULT_UFM_SPKLEN ............. 0x1 -// IC_TX_BUFFER_DEPTH ................ 16 - -#endif diff --git a/lib/rp2040/hardware/structs/interp.h b/lib/rp2040/hardware/structs/interp.h deleted file mode 100644 index 683750733b66..000000000000 --- a/lib/rp2040/hardware/structs/interp.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_INTERP_H -#define _HARDWARE_STRUCTS_INTERP_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/sio.h" - -typedef struct { - io_rw_32 accum[2]; - io_rw_32 base[3]; - io_ro_32 pop[3]; - io_ro_32 peek[3]; - io_rw_32 ctrl[2]; - io_rw_32 add_raw[2]; - io_wo_32 base01; -} interp_hw_t; - -#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET)) -#define interp0_hw (&interp_hw_array[0]) -#define interp1_hw (&interp_hw_array[1]) - -#endif diff --git a/lib/rp2040/hardware/structs/iobank0.h b/lib/rp2040/hardware/structs/iobank0.h deleted file mode 100644 index b19800fa7d33..000000000000 --- a/lib/rp2040/hardware/structs/iobank0.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_IOBANK0_H -#define _HARDWARE_STRUCTS_IOBANK0_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/io_bank0.h" - -typedef struct { - io_rw_32 inte[4]; - io_rw_32 intf[4]; - io_rw_32 ints[4]; -} io_irq_ctrl_hw_t; - -/// \tag::iobank0_hw[] -typedef struct { - struct { - io_rw_32 status; - io_rw_32 ctrl; - } io[30]; - io_rw_32 intr[4]; - io_irq_ctrl_hw_t proc0_irq_ctrl; - io_irq_ctrl_hw_t proc1_irq_ctrl; - io_irq_ctrl_hw_t dormant_wake_irq_ctrl; -} iobank0_hw_t; -/// \end::iobank0_hw[] - -#define iobank0_hw ((iobank0_hw_t *const)IO_BANK0_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/ioqspi.h b/lib/rp2040/hardware/structs/ioqspi.h deleted file mode 100644 index 48d08a7c92b4..000000000000 --- a/lib/rp2040/hardware/structs/ioqspi.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_IOQSPI_H -#define _HARDWARE_STRUCTS_IOQSPI_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/io_qspi.h" - -typedef struct { - struct { - io_rw_32 status; - io_rw_32 ctrl; - } io[6]; -} ioqspi_hw_t; - -#define ioqspi_hw ((ioqspi_hw_t *const)IO_QSPI_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/mpu.h b/lib/rp2040/hardware/structs/mpu.h deleted file mode 100644 index 34e5c39e81fe..000000000000 --- a/lib/rp2040/hardware/structs/mpu.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_MPU_H -#define _HARDWARE_STRUCTS_MPU_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/m0plus.h" - -typedef struct { - io_ro_32 type; - io_rw_32 ctrl; - io_rw_32 rnr; - io_rw_32 rbar; - io_rw_32 rasr; -} mpu_hw_t; - -#define mpu_hw ((mpu_hw_t *const)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET)) - -#endif diff --git a/lib/rp2040/hardware/structs/pads_qspi.h b/lib/rp2040/hardware/structs/pads_qspi.h deleted file mode 100644 index 451d7ebc383c..000000000000 --- a/lib/rp2040/hardware/structs/pads_qspi.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H -#define _HARDWARE_STRUCTS_PADS_QSPI_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/pads_qspi.h" - -typedef struct { - io_rw_32 voltage_select; - io_rw_32 io[6]; -} pads_qspi_hw_t; - -#define pads_qspi_hw ((pads_qspi_hw_t *const)PADS_QSPI_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/padsbank0.h b/lib/rp2040/hardware/structs/padsbank0.h deleted file mode 100644 index f56dc4011507..000000000000 --- a/lib/rp2040/hardware/structs/padsbank0.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_PADSBANK0_H -#define _HARDWARE_STRUCTS_PADSBANK0_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/pads_bank0.h" - -typedef struct { - io_rw_32 voltage_select; - io_rw_32 io[30]; -} padsbank0_hw_t; - -#define padsbank0_hw ((padsbank0_hw_t *)PADS_BANK0_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/pio.h b/lib/rp2040/hardware/structs/pio.h deleted file mode 100644 index 176863bb4d8b..000000000000 --- a/lib/rp2040/hardware/structs/pio.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_PIO_H -#define _HARDWARE_STRUCTS_PIO_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/pio.h" - -typedef struct { - io_rw_32 ctrl; - io_ro_32 fstat; - io_rw_32 fdebug; - io_ro_32 flevel; - io_wo_32 txf[NUM_PIO_STATE_MACHINES]; - io_ro_32 rxf[NUM_PIO_STATE_MACHINES]; - io_rw_32 irq; - io_wo_32 irq_force; - io_rw_32 input_sync_bypass; - io_rw_32 dbg_padout; - io_rw_32 dbg_padoe; - io_rw_32 dbg_cfginfo; - io_wo_32 instr_mem[32]; - struct pio_sm_hw { - io_rw_32 clkdiv; - io_rw_32 execctrl; - io_rw_32 shiftctrl; - io_ro_32 addr; - io_rw_32 instr; - io_rw_32 pinctrl; - } sm[NUM_PIO_STATE_MACHINES]; - io_rw_32 intr; - io_rw_32 inte0; - io_rw_32 intf0; - io_ro_32 ints0; - io_rw_32 inte1; - io_rw_32 intf1; - io_ro_32 ints1; -} pio_hw_t; - -#define pio0_hw ((pio_hw_t *const)PIO0_BASE) -#define pio1_hw ((pio_hw_t *const)PIO1_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/pll.h b/lib/rp2040/hardware/structs/pll.h deleted file mode 100644 index 4d5b5b78ccb9..000000000000 --- a/lib/rp2040/hardware/structs/pll.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_PLL_H -#define _HARDWARE_STRUCTS_PLL_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/pll.h" - -/// \tag::pll_hw[] -typedef struct { - io_rw_32 cs; - io_rw_32 pwr; - io_rw_32 fbdiv_int; - io_rw_32 prim; -} pll_hw_t; - -#define pll_sys_hw ((pll_hw_t *const)PLL_SYS_BASE) -#define pll_usb_hw ((pll_hw_t *const)PLL_USB_BASE) -/// \end::pll_hw[] - -#endif diff --git a/lib/rp2040/hardware/structs/psm.h b/lib/rp2040/hardware/structs/psm.h deleted file mode 100644 index cc9fb97e07d9..000000000000 --- a/lib/rp2040/hardware/structs/psm.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_PSM_H -#define _HARDWARE_STRUCTS_PSM_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/psm.h" - -typedef struct { - io_rw_32 frce_on; - io_rw_32 frce_off; - io_rw_32 wdsel; - io_rw_32 done; -} psm_hw_t; - -#define psm_hw ((psm_hw_t *const)PSM_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/pwm.h b/lib/rp2040/hardware/structs/pwm.h deleted file mode 100644 index 549956109390..000000000000 --- a/lib/rp2040/hardware/structs/pwm.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_PWM_H -#define _HARDWARE_STRUCTS_PWM_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/pwm.h" - -typedef struct pwm_slice_hw { - io_rw_32 csr; - io_rw_32 div; - io_rw_32 ctr; - io_rw_32 cc; - io_rw_32 top; -} pwm_slice_hw_t; - -typedef struct { - pwm_slice_hw_t slice[NUM_PWM_SLICES]; - io_rw_32 en; - io_rw_32 intr; - io_rw_32 inte; - io_rw_32 intf; - io_rw_32 ints; -} pwm_hw_t; - -#define pwm_hw ((pwm_hw_t *const)PWM_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/resets.h b/lib/rp2040/hardware/structs/resets.h deleted file mode 100644 index a96ddebd7c75..000000000000 --- a/lib/rp2040/hardware/structs/resets.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_RESETS_H -#define _HARDWARE_STRUCTS_RESETS_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/resets.h" - -/// \tag::resets_hw[] -typedef struct { - io_rw_32 reset; - io_rw_32 wdsel; - io_rw_32 reset_done; -} resets_hw_t; - -#define resets_hw ((resets_hw_t *const)RESETS_BASE) -/// \end::resets_hw[] - -#endif diff --git a/lib/rp2040/hardware/structs/rosc.h b/lib/rp2040/hardware/structs/rosc.h deleted file mode 100644 index 10543937cf46..000000000000 --- a/lib/rp2040/hardware/structs/rosc.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_ROSC_H -#define _HARDWARE_STRUCTS_ROSC_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/rosc.h" - -typedef struct { - io_rw_32 ctrl; - io_rw_32 freqa; - io_rw_32 freqb; - io_rw_32 dormant; - io_rw_32 div; - io_rw_32 phase; - io_rw_32 status; - io_rw_32 randombit; - io_rw_32 count; - io_rw_32 dftx; -} rosc_hw_t; - -#define rosc_hw ((rosc_hw_t *const)ROSC_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/rtc.h b/lib/rp2040/hardware/structs/rtc.h deleted file mode 100644 index 276bd7a2428a..000000000000 --- a/lib/rp2040/hardware/structs/rtc.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_RTC_H -#define _HARDWARE_STRUCTS_RTC_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/rtc.h" - -typedef struct { - io_rw_32 clkdiv_m1; - io_rw_32 setup_0; - io_rw_32 setup_1; - io_rw_32 ctrl; - io_rw_32 irq_setup_0; - io_rw_32 irq_setup_1; - io_rw_32 rtc_1; - io_rw_32 rtc_0; - io_rw_32 intr; - io_rw_32 inte; - io_rw_32 intf; - io_rw_32 ints; -} rtc_hw_t; - -#define rtc_hw ((rtc_hw_t *const)RTC_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/scb.h b/lib/rp2040/hardware/structs/scb.h deleted file mode 100644 index b48a8725472b..000000000000 --- a/lib/rp2040/hardware/structs/scb.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_SCB_H -#define _HARDWARE_STRUCTS_SCB_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/m0plus.h" - -// SCB == System Control Block -typedef struct { - io_ro_32 cpuid; - io_rw_32 icsr; - io_rw_32 vtor; - io_rw_32 aircr; - io_rw_32 scr; - // ... -} armv6m_scb_t; - -#define scb_hw ((armv6m_scb_t *const)(PPB_BASE + M0PLUS_CPUID_OFFSET)) - -#endif diff --git a/lib/rp2040/hardware/structs/sio.h b/lib/rp2040/hardware/structs/sio.h deleted file mode 100644 index bc277afcae18..000000000000 --- a/lib/rp2040/hardware/structs/sio.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_SIO_H -#define _HARDWARE_STRUCTS_SIO_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/sio.h" -#include "hardware/structs/interp.h" - -typedef struct { - io_ro_32 cpuid; - io_ro_32 gpio_in; - io_ro_32 gpio_hi_in; - uint32_t _pad; - - io_rw_32 gpio_out; - io_wo_32 gpio_set; - io_wo_32 gpio_clr; - io_wo_32 gpio_togl; - - io_wo_32 gpio_oe; - io_wo_32 gpio_oe_set; - io_wo_32 gpio_oe_clr; - io_wo_32 gpio_oe_togl; - - io_rw_32 gpio_hi_out; - io_wo_32 gpio_hi_set; - io_wo_32 gpio_hi_clr; - io_wo_32 gpio_hi_togl; - - io_wo_32 gpio_hi_oe; - io_wo_32 gpio_hi_oe_set; - io_wo_32 gpio_hi_oe_clr; - io_wo_32 gpio_hi_oe_togl; - - io_rw_32 fifo_st; - io_wo_32 fifo_wr; - io_ro_32 fifo_rd; - io_ro_32 spinlock_st; - - io_rw_32 div_udividend; - io_rw_32 div_udivisor; - io_rw_32 div_sdividend; - io_rw_32 div_sdivisor; - - io_rw_32 div_quotient; - io_rw_32 div_remainder; - io_rw_32 div_csr; - - uint32_t _pad2; - - interp_hw_t interp[2]; -} sio_hw_t; - -#define sio_hw ((sio_hw_t *)SIO_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/spi.h b/lib/rp2040/hardware/structs/spi.h deleted file mode 100644 index 5b3b2bab5d55..000000000000 --- a/lib/rp2040/hardware/structs/spi.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_SPI_H -#define _HARDWARE_STRUCTS_SPI_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/spi.h" - -typedef struct { - io_rw_32 cr0; - io_rw_32 cr1; - io_rw_32 dr; - io_rw_32 sr; - io_rw_32 cpsr; - io_rw_32 imsc; - io_rw_32 ris; - io_rw_32 mis; - io_rw_32 icr; - io_rw_32 dmacr; -} spi_hw_t; - -#define spi0_hw ((spi_hw_t *const)SPI0_BASE) -#define spi1_hw ((spi_hw_t *const)SPI1_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/ssi.h b/lib/rp2040/hardware/structs/ssi.h deleted file mode 100644 index 80779fe6ba2d..000000000000 --- a/lib/rp2040/hardware/structs/ssi.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_SSI_H -#define _HARDWARE_STRUCTS_SSI_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/ssi.h" - -typedef struct { - io_rw_32 ctrlr0; - io_rw_32 ctrlr1; - io_rw_32 ssienr; - io_rw_32 mwcr; - io_rw_32 ser; - io_rw_32 baudr; - io_rw_32 txftlr; - io_rw_32 rxftlr; - io_rw_32 txflr; - io_rw_32 rxflr; - io_rw_32 sr; - io_rw_32 imr; - io_rw_32 isr; - io_rw_32 risr; - io_rw_32 txoicr; - io_rw_32 rxoicr; - io_rw_32 rxuicr; - io_rw_32 msticr; - io_rw_32 icr; - io_rw_32 dmacr; - io_rw_32 dmatdlr; - io_rw_32 dmardlr; - io_rw_32 idr; - io_rw_32 ssi_version_id; - io_rw_32 dr0; - uint32_t _pad[(0xf0 - 0x60) / 4 - 1]; - io_rw_32 rx_sample_dly; - io_rw_32 spi_ctrlr0; - io_rw_32 txd_drive_edge; -} ssi_hw_t; - -#define ssi_hw ((ssi_hw_t *const)XIP_SSI_BASE) -#endif diff --git a/lib/rp2040/hardware/structs/syscfg.h b/lib/rp2040/hardware/structs/syscfg.h deleted file mode 100644 index 0bfc7293c103..000000000000 --- a/lib/rp2040/hardware/structs/syscfg.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_SYSCFG_H -#define _HARDWARE_STRUCTS_SYSCFG_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/syscfg.h" - -typedef struct { - io_rw_32 proc0_nmi_mask; - io_rw_32 proc1_nmi_mask; - io_rw_32 proc_config; - io_rw_32 proc_in_sync_bypass; - io_rw_32 proc_in_sync_bypass_hi; - io_rw_32 dbgforce; - io_rw_32 mempowerdown; -} syscfg_hw_t; - -#define syscfg_hw ((syscfg_hw_t *const)SYSCFG_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/systick.h b/lib/rp2040/hardware/structs/systick.h deleted file mode 100644 index 24673fbc7529..000000000000 --- a/lib/rp2040/hardware/structs/systick.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_SYSTICK_H -#define _HARDWARE_STRUCTS_SYSTICK_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/m0plus.h" - -typedef struct { - io_rw_32 csr; - io_rw_32 rvr; - io_rw_32 cvr; - io_ro_32 calib; -} systick_hw_t; - -#define systick_hw ((systick_hw_t *const)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET)) - -#endif diff --git a/lib/rp2040/hardware/structs/timer.h b/lib/rp2040/hardware/structs/timer.h deleted file mode 100644 index e051a06970c3..000000000000 --- a/lib/rp2040/hardware/structs/timer.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_TIMER_H -#define _HARDWARE_STRUCTS_TIMER_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/timer.h" - -#define NUM_TIMERS 4 - -typedef struct { - io_wo_32 timehw; - io_wo_32 timelw; - io_ro_32 timehr; - io_ro_32 timelr; - io_rw_32 alarm[NUM_TIMERS]; - io_rw_32 armed; - io_ro_32 timerawh; - io_ro_32 timerawl; - io_rw_32 dbgpause; - io_rw_32 pause; - io_rw_32 intr; - io_rw_32 inte; - io_rw_32 intf; - io_ro_32 ints; -} timer_hw_t; - -#define timer_hw ((timer_hw_t *const)TIMER_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/uart.h b/lib/rp2040/hardware/structs/uart.h deleted file mode 100644 index 42fe8e88bf99..000000000000 --- a/lib/rp2040/hardware/structs/uart.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_UART_H -#define _HARDWARE_STRUCTS_UART_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/uart.h" - -typedef struct { - io_rw_32 dr; - io_rw_32 rsr; - uint32_t _pad0[4]; - io_rw_32 fr; - uint32_t _pad1; - io_rw_32 ilpr; - io_rw_32 ibrd; - io_rw_32 fbrd; - io_rw_32 lcr_h; - io_rw_32 cr; - io_rw_32 ifls; - io_rw_32 imsc; - io_rw_32 ris; - io_rw_32 mis; - io_rw_32 icr; - io_rw_32 dmacr; -} uart_hw_t; - -#define uart0_hw ((uart_hw_t *const)UART0_BASE) -#define uart1_hw ((uart_hw_t *const)UART1_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/vreg_and_chip_reset.h b/lib/rp2040/hardware/structs/vreg_and_chip_reset.h deleted file mode 100644 index 9956d6831525..000000000000 --- a/lib/rp2040/hardware/structs/vreg_and_chip_reset.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H -#define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/vreg_and_chip_reset.h" - -typedef struct { - io_rw_32 vreg; - io_rw_32 bod; - io_rw_32 chip_reset; -} vreg_and_chip_reset_hw_t; - -#define vreg_and_chip_reset_hw ((vreg_and_chip_reset_hw_t *const)VREG_AND_CHIP_RESET_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/watchdog.h b/lib/rp2040/hardware/structs/watchdog.h deleted file mode 100644 index 2cf05f19d1e6..000000000000 --- a/lib/rp2040/hardware/structs/watchdog.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_WATCHDOG_H -#define _HARDWARE_STRUCTS_WATCHDOG_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/watchdog.h" - -typedef struct { - io_rw_32 ctrl; - io_wo_32 load; - io_ro_32 reason; - io_rw_32 scratch[8]; - io_rw_32 tick; -} watchdog_hw_t; - -#define watchdog_hw ((watchdog_hw_t *const)WATCHDOG_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/xip_ctrl.h b/lib/rp2040/hardware/structs/xip_ctrl.h deleted file mode 100644 index bfa5b1c0cb4a..000000000000 --- a/lib/rp2040/hardware/structs/xip_ctrl.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _HARDWARE_STRUCTS_XIP_CTRL_H -#define _HARDWARE_STRUCTS_XIP_CTRL_H - -#include "hardware/address_mapped.h" -#include "hardware/regs/xip.h" - -typedef struct { - io_rw_32 ctrl; - io_rw_32 flush; - io_rw_32 stat; - io_rw_32 ctr_hit; - io_rw_32 ctr_acc; - io_rw_32 stream_addr; - io_rw_32 stream_ctr; - io_rw_32 stream_fifo; -} xip_ctrl_hw_t; - -#define XIP_STAT_FIFO_FULL 0x4u -#define XIP_STAT_FIFO_EMPTY 0x2u -#define XIP_STAT_FLUSH_RDY 0x1u - -#define xip_ctrl_hw ((xip_ctrl_hw_t *const)XIP_CTRL_BASE) - -#endif diff --git a/lib/rp2040/hardware/structs/xosc.h b/lib/rp2040/hardware/structs/xosc.h deleted file mode 100644 index 698e6a2ff2ca..000000000000 --- a/lib/rp2040/hardware/structs/xosc.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2020 Raspberry Pi (Trading) Ltd. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _HARDWARE_STRUCTS_XOSC_H -#define _HARDWARE_STRUCTS_XOSC_H - -#include "hardware/address_mapped.h" -#include "hardware/platform_defs.h" -#include "hardware/regs/xosc.h" - -/// \tag::xosc_hw[] -typedef struct { - io_rw_32 ctrl; - io_rw_32 status; - io_rw_32 dormant; - io_rw_32 startup; - io_rw_32 _reserved[3]; - io_rw_32 count; -} xosc_hw_t; - -#define xosc_hw ((xosc_hw_t *const)XOSC_BASE) -/// \end::xosc_hw[] - -#endif diff --git a/lib/rp2040/rp2040.patch b/lib/rp2040/rp2040.patch deleted file mode 100644 index bae9e6d1bc7f..000000000000 --- a/lib/rp2040/rp2040.patch +++ /dev/null @@ -1,41 +0,0 @@ -diff --git a/lib/rp2040/boot_stage2/boot2_generic_03h.S b/lib/rp2040/boot_stage2/boot2_generic_03h.S -index a10e66abd..cc7e4fbc7 100644 ---- a/lib/rp2040/boot_stage2/boot2_generic_03h.S -+++ b/lib/rp2040/boot_stage2/boot2_generic_03h.S -@@ -16,7 +16,7 @@ - // 4-byte checksum. Therefore code size cannot exceed 252 bytes. - // ---------------------------------------------------------------------------- - --#include "pico/asm_helper.S" -+//#include "pico/asm_helper.S" - #include "hardware/regs/addressmap.h" - #include "hardware/regs/ssi.h" - -diff --git a/lib/rp2040/boot_stage2/boot2_w25q080.S b/lib/rp2040/boot_stage2/boot2_w25q080.S -index ad3238e2..8fb3def4 100644 ---- a/lib/rp2040/boot_stage2/boot2_w25q080.S -+++ b/lib/rp2040/boot_stage2/boot2_w25q080.S -@@ -26,7 +26,7 @@ - // 4-byte checksum. Therefore code size cannot exceed 252 bytes. - // ---------------------------------------------------------------------------- - --#include "pico/asm_helper.S" -+//#include "pico/asm_helper.S" - #include "hardware/regs/addressmap.h" - #include "hardware/regs/ssi.h" - #include "hardware/regs/pads_qspi.h" -diff --git a/lib/rp2040/hardware/address_mapped.h b/lib/rp2040/hardware/address_mapped.h -index b58f1e50..d651f598 100644 ---- a/lib/rp2040/hardware/address_mapped.h -+++ b/lib/rp2040/hardware/address_mapped.h -@@ -7,7 +7,9 @@ - #ifndef _HARDWARE_ADDRESS_MAPPED_H - #define _HARDWARE_ADDRESS_MAPPED_H - --#include "pico.h" -+//#include "pico.h" -+#define __force_inline inline -+#define static_assert(a,b) - #include "hardware/regs/addressmap.h" - - /** \file address_mapped.h diff --git a/lib/rp2040_flash/Makefile b/lib/rp2040_flash/Makefile index d98a72d95b21..142ad3263396 100644 --- a/lib/rp2040_flash/Makefile +++ b/lib/rp2040_flash/Makefile @@ -1,10 +1,10 @@ CC=gcc -CFLAGS=-c -Wall -ggdb +CFLAGS=-c -Wall -ggdb -DHAS_LIBUSB LDFALGS= SOURCES=main.c picoboot_connection.c OBJECTS=$(SOURCES:.c=.o) LIBS=`pkg-config libusb-1.0 --libs` -INCLUDE_DIRS+=-I../rp2040/ `pkg-config libusb-1.0 --cflags` +INCLUDE_DIRS+=-I../pico-sdk/ `pkg-config libusb-1.0 --cflags` EXECUTABLE=rp2040_flash diff --git a/lib/rp2040_flash/addresses.h b/lib/rp2040_flash/addresses.h new file mode 100644 index 000000000000..d8926f069c5e --- /dev/null +++ b/lib/rp2040_flash/addresses.h @@ -0,0 +1,94 @@ +#ifndef _ADDRESSES_H +#define _ADDRESSES_H + +#define ROM_START 0x00000000 // same as ROM_BASE in addressmap.h +#define ROM_END_RP2040 0x00004000 +#define ROM_END_RP2350 0x00008000 +// todo amy based on what sort of elf (also this breaks RP2040 builds?) +#define FLASH_START 0x10000000 // same as XIP_MAIN_BASE in addressmap.h +#define FLASH_END_RP2040 0x11000000 // +32 MiB -- remainder has no external devices mapped +#define FLASH_END_RP2350 0x12000000 // +32 MiB -- remainder has no external devices mapped +// todo amy based on what sort of elf +#define XIP_SRAM_START_RP2040 0x15000000 +#define XIP_SRAM_END_RP2040 0x15004000 +#define XIP_SRAM_START_RP2350 0x13ffc000 // same as XIP_SRAM_BASE in addressmap.h +#define XIP_SRAM_END_RP2350 0x14000000 // same as XIP_SRAM_END in addressmap.h + +#define SRAM_START 0x20000000 // same as SRAM_BASE in addressmap.h +#define SRAM_END_RP2040 0x20042000 +#define SRAM_END_RP2350 0x20082000 +// todo amy no more banked alias +#define MAIN_RAM_BANKED_START 0x21000000 +#define MAIN_RAM_BANKED_END 0x21040000 + + +#ifdef __cplusplus + +#include +#include + +#ifdef _WIN32 +#undef IGNORE +#endif + +// Address ranges for RP2040/RP2350 +struct address_range { + enum type { + CONTENTS, // may have contents + NO_CONTENTS, // must be uninitialized + IGNORE // will be ignored + }; + address_range(uint32_t from, uint32_t to, type type) : from(from), to(to), type(type) {} + address_range() : address_range(0, 0, IGNORE) {} + uint32_t from; + uint32_t to; + type type; +}; + +typedef std::vector address_ranges; + + +const address_ranges rp2040_address_ranges_flash { + address_range(FLASH_START, FLASH_END_RP2040, address_range::type::CONTENTS), + address_range(SRAM_START, SRAM_END_RP2040, address_range::type::NO_CONTENTS), + address_range(MAIN_RAM_BANKED_START, MAIN_RAM_BANKED_END, address_range::type::NO_CONTENTS) +}; + +const address_ranges rp2040_address_ranges_ram { + address_range(SRAM_START, SRAM_END_RP2040, address_range::type::CONTENTS), + address_range(XIP_SRAM_START_RP2040, XIP_SRAM_END_RP2040, address_range::type::CONTENTS), + address_range(ROM_START, ROM_END_RP2040, address_range::type::IGNORE) // for now we ignore the bootrom if present +}; + +const address_ranges rp2350_address_ranges_flash { + address_range(FLASH_START, FLASH_END_RP2350, address_range::type::CONTENTS), + address_range(SRAM_START, SRAM_END_RP2350, address_range::type::NO_CONTENTS), + address_range(MAIN_RAM_BANKED_START, MAIN_RAM_BANKED_END, address_range::type::NO_CONTENTS) +}; + +const address_ranges rp2350_address_ranges_ram { + address_range(SRAM_START, SRAM_END_RP2350, address_range::type::CONTENTS), + address_range(XIP_SRAM_START_RP2350, XIP_SRAM_END_RP2350, address_range::type::CONTENTS), + address_range(ROM_START, ROM_END_RP2350, address_range::type::IGNORE) // for now we ignore the bootrom if present +}; + +static bool is_address_valid(const address_ranges& valid_ranges, uint32_t addr) { + for(const auto& range : valid_ranges) { + if (range.from <= addr && range.to > addr) { + return true; + } + } + return false; +} + +static bool is_address_initialized(const address_ranges& valid_ranges, uint32_t addr) { + for(const auto& range : valid_ranges) { + if (range.from <= addr && range.to > addr) { + return address_range::type::CONTENTS == range.type; + } + } + return false; +} + +#endif +#endif diff --git a/lib/rp2040_flash/main.c b/lib/rp2040_flash/main.c index e938eb35e796..780071308900 100644 --- a/lib/rp2040_flash/main.c +++ b/lib/rp2040_flash/main.c @@ -12,7 +12,7 @@ #include "picoboot_connection.h" #include "boot/uf2.h" -#define FLASH_MAX_SIZE (FLASH_END - FLASH_START) +#define FLASH_MAX_SIZE (FLASH_END_RP2350 - FLASH_START) #define FLASH_NUM_WRITE_BLOCKS (FLASH_MAX_SIZE / PAGE_SIZE) #define FLASH_NUM_ERASE_BLOCKS (FLASH_MAX_SIZE / FLASH_SECTOR_ERASE_SIZE) @@ -62,7 +62,7 @@ int load_flash_data(const char *filename, struct flash_data *target) { // Bounds and alignment checking if (block.target_addr != (block.target_addr & ~(PAGE_SIZE-1))) continue; - if (block.target_addr > FLASH_END - PAGE_SIZE) continue; + if (block.target_addr > FLASH_END_RP2350 - PAGE_SIZE) continue; if (block.target_addr < FLASH_START) continue; uint32_t offset = block.target_addr - FLASH_START; @@ -110,7 +110,7 @@ int report_error(libusb_device_handle *handle, const char *cmd) { return 1; }; -int picoboot_flash(libusb_device_handle *handle, struct flash_data *image) { +int picoboot_flash(libusb_device_handle *handle, struct flash_data *image, model_t model) { fprintf(stderr, "Resetting interface\n"); if (picoboot_reset(handle)) { return report_error(handle, "reset"); @@ -146,8 +146,18 @@ int picoboot_flash(libusb_device_handle *handle, struct flash_data *image) { } fprintf(stderr, "Rebooting device\n"); - if (picoboot_reboot(handle, 0, 0, 500)) { - return report_error(handle, "reboot"); + if (model == 2040) { + if (picoboot_reboot(handle, 0, 0, 500)) { + return report_error(handle, "reboot"); + } + } else { + struct picoboot_reboot2_cmd cmd = { + .dFlags = REBOOT2_FLAG_REBOOT_TYPE_NORMAL, + .dDelayMS = 500, + }; + if (picoboot_reboot2(handle, &cmd)) { + return report_error(handle, "reboot"); + } } return 0; @@ -204,12 +214,13 @@ int main(int argc, char *argv[]) { goto do_exit; } + model_t model; for (libusb_device **dev = devs; *dev; ++dev) { if (has_target) { if (target_bus != libusb_get_bus_number(*dev)) continue; if (target_address != libusb_get_device_address(*dev)) continue; } - enum picoboot_device_result res = picoboot_open_device(*dev, &handle); + enum picoboot_device_result res = picoboot_open_device(*dev, &handle, &model, -1, -1, ""); if (res == dr_vidpid_bootrom_ok) { break; } @@ -229,7 +240,7 @@ int main(int argc, char *argv[]) { libusb_get_bus_number(dev), libusb_get_device_address(dev)); fprintf(stderr, "Flashing...\n"); - rc = picoboot_flash(handle, image); + rc = picoboot_flash(handle, image, model); do_exit: if (handle) { diff --git a/lib/rp2040_flash/picoboot_connection.c b/lib/rp2040_flash/picoboot_connection.c index c0d2176937fe..7a519d1648d0 100644 --- a/lib/rp2040_flash/picoboot_connection.c +++ b/lib/rp2040_flash/picoboot_connection.c @@ -7,29 +7,32 @@ #include #include #include +#include #include "picoboot_connection.h" +#include "pico/bootrom_constants.h" -#if false && !defined(NDEBUG) -#define output(format,...) printf(format, __VA_ARGS__) +#if ENABLE_DEBUG_LOG +#include +#define output(...) printf(__VA_ARGS__) #else #define output(format,...) ((void)0) #endif static bool verbose; +static bool definitely_exclusive; +static enum { + XIP_UNKOWN, + XIP_ACTIVE, + XIP_INACTIVE, +} xip_state; // todo test sparse binary (well actually two range is this) -#define VENDOR_ID_RASPBERRY_PI 0x2e8au -#define PRODUCT_ID_RP2_USBBOOT 0x0003u -#define PRODUCT_ID_PICOPROBE 0x0004u -#define PRODUCT_ID_MICROPYTHON 0x0005u -#define PRODUCT_ID_STDIO_USB 0x000au - uint32_t crc32_for_byte(uint32_t remainder) { const uint32_t POLYNOMIAL = 0x4C11DB7; remainder <<= 24u; - for (uint bit = 8; bit > 0; bit--) { + for (unsigned int bit = 8; bit > 0; bit--) { if (remainder & 0x80000000) remainder = (remainder << 1) ^ POLYNOMIAL; else @@ -38,47 +41,64 @@ uint32_t crc32_for_byte(uint32_t remainder) { return remainder; } -uint32_t crc32_sw(const uint8_t *buf, uint count, uint32_t crc) { +uint32_t crc32_sw(const uint8_t *buf, unsigned int count, uint32_t crc) { static uint32_t table[0x100]; if (!table[1]) { - for (uint i = 0; i < count_of(table); i++) { + for (unsigned int i = 0; i < count_of(table); i++) { table[i] = crc32_for_byte(i); } } - for (uint i = 0; i < count; ++i) { + for (unsigned int i = 0; i < count; ++i) { crc = (crc << 8u) ^ table[(uint8_t) ((crc >> 24u) ^ buf[i])]; } return crc; } -uint interface; -uint out_ep; -uint in_ep; +unsigned int interface; +unsigned int out_ep; +unsigned int in_ep; -enum picoboot_device_result picoboot_open_device(libusb_device *device, libusb_device_handle **dev_handle) { +enum picoboot_device_result picoboot_open_device(libusb_device *device, libusb_device_handle **dev_handle, model_t *model, int vid, int pid, const char* ser) { struct libusb_device_descriptor desc; struct libusb_config_descriptor *config; + definitely_exclusive = false; *dev_handle = NULL; + *model = unknown; int ret = libusb_get_device_descriptor(device, &desc); + enum picoboot_device_result res = dr_vidpid_unknown; if (ret && verbose) { - output("Failed to read device descriptor"); + output("Failed to read device descriptor\n"); } if (!ret) { - if (desc.idVendor != VENDOR_ID_RASPBERRY_PI) { - return dr_vidpid_unknown; - } - switch (desc.idProduct) { - case PRODUCT_ID_MICROPYTHON: - return dr_vidpid_micropython; - case PRODUCT_ID_PICOPROBE: - return dr_vidpid_picoprobe; - case PRODUCT_ID_STDIO_USB: - return dr_vidpid_stdio_usb; - case PRODUCT_ID_RP2_USBBOOT: - break; - default: + if (pid >= 0) { + bool match_vid = (vid < 0 ? VENDOR_ID_RASPBERRY_PI : (unsigned int)vid) == desc.idVendor; + bool match_pid = pid == desc.idProduct; + if (!(match_vid && match_pid)) { return dr_vidpid_unknown; + } + } else if (vid != 0) { // ignore vid/pid filtering if no pid and vid == 0 + if (desc.idVendor != (vid < 0 ? VENDOR_ID_RASPBERRY_PI : (unsigned int)vid)) { + return dr_vidpid_unknown; + } + switch (desc.idProduct) { + case PRODUCT_ID_MICROPYTHON: + return dr_vidpid_micropython; + case PRODUCT_ID_PICOPROBE: + return dr_vidpid_picoprobe; + case PRODUCT_ID_RP2040_STDIO_USB: + case PRODUCT_ID_STDIO_USB: + res = dr_vidpid_stdio_usb; + break; + case PRODUCT_ID_RP2040_USBBOOT: + *model = rp2040; + break; + case PRODUCT_ID_RP2350_USBBOOT: + *model = rp2350; + break; + default: + return dr_vidpid_unknown; + } } ret = libusb_get_active_config_descriptor(device, &config); if (ret && verbose) { @@ -92,7 +112,29 @@ enum picoboot_device_result picoboot_open_device(libusb_device *device, libusb_d output("Failed to open device %d\n", ret); } if (ret) { - return dr_vidpid_bootrom_cant_connect; + if (vid == 0 || strlen(ser) != 0) { + // didn't check vid or ser, so treat as unknown + return dr_vidpid_unknown; + } else if (res != dr_vidpid_unknown) { + return res; + } else { + return dr_vidpid_bootrom_cant_connect; + } + } + } + + if (res == dr_vidpid_stdio_usb) { + if (strlen(ser) != 0) { + // Check USB serial number + char ser_str[128]; + libusb_get_string_descriptor_ascii(*dev_handle, desc.iSerialNumber, (unsigned char*)ser_str, sizeof(ser_str)); + if (strcmp(ser, ser_str)) { + return dr_vidpid_unknown; + } else { + return res; + } + } else { + return res; } } @@ -114,14 +156,48 @@ enum picoboot_device_result picoboot_open_device(libusb_device *device, libusb_d if (verbose) output("Failed to claim interface\n"); return dr_vidpid_bootrom_no_interface; } - - return dr_vidpid_bootrom_ok; } else { if (verbose) output("Did not find PICOBOOT interface\n"); return dr_vidpid_bootrom_no_interface; } } + if (!ret) { + if (*model == unknown) { + struct picoboot_get_info_cmd info_cmd; + info_cmd.bType = PICOBOOT_GET_INFO_SYS, + info_cmd.dParams[0] = (uint32_t) (SYS_INFO_CHIP_INFO); + uint32_t word_buf[64]; + // RP2040 doesn't have this function, so returns non-zero + int info_ret = picoboot_get_info(*dev_handle, &info_cmd, (uint8_t*)word_buf, sizeof(word_buf)); + if (info_ret) { + *model = rp2040; + } else { + *model = rp2350; + } + } + if (strlen(ser) != 0) { + if (*model == rp2040) { + // Check flash ID, as USB serial number is not unique + uint64_t ser_num = strtoull(ser, NULL, 16); + uint64_t id = 0; + int id_ret = picoboot_flash_id(*dev_handle, &id); + if (verbose) output("Flash ID %"PRIX64"\n", id); + if (id_ret || (ser_num != id)) { + return dr_vidpid_unknown; + } + } else { + // Check USB serial number + char ser_str[128]; + libusb_get_string_descriptor_ascii(*dev_handle, desc.iSerialNumber, (unsigned char*)ser_str, sizeof(ser_str)); + if (strcmp(ser, ser_str)) { + return dr_vidpid_unknown; + } + } + } + return dr_vidpid_bootrom_ok; + } + assert(ret); if (*dev_handle) { @@ -169,6 +245,7 @@ int picoboot_reset(libusb_device_handle *usb_device) { return ret; } if (verbose) output(" ...ok\n"); + definitely_exclusive = false; return 0; } @@ -198,7 +275,7 @@ int picoboot_cmd_status(libusb_device_handle *usb_device, struct picoboot_cmd_st int one_time_bulk_timeout; -int picoboot_cmd(libusb_device_handle *usb_device, struct picoboot_cmd *cmd, uint8_t *buffer, uint buf_size) { +int picoboot_cmd(libusb_device_handle *usb_device, struct picoboot_cmd *cmd, uint8_t *buffer, unsigned int buf_size) { int sent = 0; int ret; @@ -212,6 +289,10 @@ int picoboot_cmd(libusb_device_handle *usb_device, struct picoboot_cmd *cmd, uin return ret; } + int saved_xip_state = xip_state; + bool saved_exclusive = definitely_exclusive; + xip_state = XIP_UNKOWN; + definitely_exclusive = false; int timeout = 10000; if (one_time_bulk_timeout) { timeout = one_time_bulk_timeout; @@ -250,6 +331,42 @@ int picoboot_cmd(libusb_device_handle *usb_device, struct picoboot_cmd *cmd, uin if (verbose) output("zero length in\n"); ret = libusb_bulk_transfer(usb_device, in_ep, spoon, 1, &received, cmd->dTransferLength == 0 ? timeout : 3000); } + if (!ret) { + // do our defensive best to keep the xip_state up to date + switch (cmd->bCmdId) { + case PC_EXIT_XIP: + xip_state = XIP_INACTIVE; + break; + case PC_ENTER_CMD_XIP: + xip_state = XIP_ACTIVE; + break; + case PC_READ: + case PC_WRITE: + // whitelist PC_READ and PC_WRITE as not affecting xip state + xip_state = saved_xip_state; + break; + default: + xip_state = XIP_UNKOWN; + break; + } + // do our defensive best to keep the exclusive var up to date + switch (cmd->bCmdId) { + case PC_EXCLUSIVE_ACCESS: + definitely_exclusive = cmd->exclusive_cmd.bExclusive; + break; + case PC_ENTER_CMD_XIP: + case PC_EXIT_XIP: + case PC_READ: + case PC_WRITE: + // whitelist PC_READ and PC_WRITE as not affecting xip state + definitely_exclusive = saved_exclusive; + break; + default: + definitely_exclusive = false; + break; + } + } + return ret; } @@ -264,11 +381,16 @@ int picoboot_exclusive_access(libusb_device_handle *usb_device, uint8_t exclusiv } int picoboot_exit_xip(libusb_device_handle *usb_device) { + if (definitely_exclusive && xip_state == XIP_INACTIVE) { + if (verbose) output("Skipping EXIT_XIP"); + return 0; + } struct picoboot_cmd cmd; if (verbose) output("EXIT_XIP\n"); cmd.bCmdId = PC_EXIT_XIP; cmd.bCmdSize = 0; cmd.dTransferLength = 0; + xip_state = XIP_INACTIVE; return picoboot_cmd(usb_device, &cmd, NULL, 0); } @@ -278,12 +400,13 @@ int picoboot_enter_cmd_xip(libusb_device_handle *usb_device) { cmd.bCmdId = PC_ENTER_CMD_XIP; cmd.bCmdSize = 0; cmd.dTransferLength = 0; + xip_state = XIP_ACTIVE; return picoboot_cmd(usb_device, &cmd, NULL, 0); } int picoboot_reboot(libusb_device_handle *usb_device, uint32_t pc, uint32_t sp, uint32_t delay_ms) { struct picoboot_cmd cmd; - if (verbose) output("REBOOT %08x %08x %u\n", (uint) pc, (uint) sp, (uint) delay_ms); + if (verbose) output("REBOOT %08x %08x %u\n", (unsigned int) pc, (unsigned int) sp, (unsigned int) delay_ms); cmd.bCmdId = PC_REBOOT; cmd.bCmdSize = sizeof(cmd.reboot_cmd); cmd.dTransferLength = 0; @@ -293,11 +416,21 @@ int picoboot_reboot(libusb_device_handle *usb_device, uint32_t pc, uint32_t sp, return picoboot_cmd(usb_device, &cmd, NULL, 0); } +int picoboot_reboot2(libusb_device_handle *usb_device, struct picoboot_reboot2_cmd *reboot_cmd) { + struct picoboot_cmd cmd; + if (verbose) output("REBOOT %08x %08x %08x %u\n", (unsigned int)reboot_cmd->dFlags, (unsigned int) reboot_cmd->dParam0, (unsigned int) reboot_cmd->dParam1, (unsigned int) reboot_cmd->dDelayMS); + cmd.bCmdId = PC_REBOOT2; + cmd.bCmdSize = sizeof(cmd.reboot2_cmd); + cmd.reboot2_cmd = *reboot_cmd; + cmd.dTransferLength = 0; + return picoboot_cmd(usb_device, &cmd, NULL, 0); +} + int picoboot_exec(libusb_device_handle *usb_device, uint32_t addr) { struct picoboot_cmd cmd; // shouldn't be necessary any more // addr |= 1u; // Thumb bit - if (verbose) output("EXEC %08x\n", (uint) addr); + if (verbose) output("EXEC %08x\n", (unsigned int) addr); cmd.bCmdId = PC_EXEC; cmd.bCmdSize = sizeof(cmd.address_only_cmd); cmd.dTransferLength = 0; @@ -305,9 +438,22 @@ int picoboot_exec(libusb_device_handle *usb_device, uint32_t addr) { return picoboot_cmd(usb_device, &cmd, NULL, 0); } +// int picoboot_exec2(libusb_device_handle *usb_device, struct picoboot_exec2_cmd *exec2_cmd) { +// struct picoboot_cmd cmd; +// // shouldn't be necessary any more +// // addr |= 1u; // Thumb bit +// //if (verbose) output("EXEC2 %08x\n", (unsigned int) exec2_cmd->scan_base); +// cmd.bCmdId = PC_EXEC2; +// cmd.bCmdSize = sizeof(cmd.exec2_cmd); +// cmd.dTransferLength = 0; +// cmd.exec2_cmd = *exec2_cmd; +// return picoboot_cmd(usb_device, &cmd, NULL, 0); +// } // currently unused + + int picoboot_flash_erase(libusb_device_handle *usb_device, uint32_t addr, uint32_t len) { struct picoboot_cmd cmd; - if (verbose) output("FLASH_ERASE %08x+%08x\n", (uint) addr, (uint) len); + if (verbose) output("FLASH_ERASE %08x+%08x\n", (unsigned int) addr, (unsigned int) len); cmd.bCmdId = PC_FLASH_ERASE; cmd.bCmdSize = sizeof(cmd.range_cmd); cmd.range_cmd.dAddr = addr; @@ -318,7 +464,7 @@ int picoboot_flash_erase(libusb_device_handle *usb_device, uint32_t addr, uint32 int picoboot_vector(libusb_device_handle *usb_device, uint32_t addr) { struct picoboot_cmd cmd; - if (verbose) output("VECTOR %08x\n", (uint) addr); + if (verbose) output("VECTOR %08x\n", (unsigned int) addr); cmd.bCmdId = PC_VECTORIZE_FLASH; cmd.bCmdSize = sizeof(cmd.address_only_cmd); cmd.range_cmd.dAddr = addr; @@ -328,7 +474,7 @@ int picoboot_vector(libusb_device_handle *usb_device, uint32_t addr) { int picoboot_write(libusb_device_handle *usb_device, uint32_t addr, uint8_t *buffer, uint32_t len) { struct picoboot_cmd cmd; - if (verbose) output("WRITE %08x+%08x\n", (uint) addr, (uint) len); + if (verbose) output("WRITE %08x+%08x\n", (unsigned int) addr, (unsigned int) len); cmd.bCmdId = PC_WRITE; cmd.bCmdSize = sizeof(cmd.range_cmd); cmd.range_cmd.dAddr = addr; @@ -338,7 +484,7 @@ int picoboot_write(libusb_device_handle *usb_device, uint32_t addr, uint8_t *buf int picoboot_read(libusb_device_handle *usb_device, uint32_t addr, uint8_t *buffer, uint32_t len) { memset(buffer, 0xaa, len); - if (verbose) output("READ %08x+%08x\n", (uint) addr, (uint) len); + if (verbose) output("READ %08x+%08x\n", (unsigned int) addr, (unsigned int) len); struct picoboot_cmd cmd; cmd.bCmdId = PC_READ; cmd.bCmdSize = sizeof(cmd.range_cmd); @@ -357,8 +503,47 @@ int picoboot_read(libusb_device_handle *usb_device, uint32_t addr, uint8_t *buff return ret; } +int picoboot_otp_write(libusb_device_handle *usb_device, struct picoboot_otp_cmd *otp_cmd, uint8_t *buffer, uint32_t len) { + struct picoboot_cmd cmd; + if (verbose) output("OTP WRITE %04x+%08x ecc=%d\n", (unsigned int) otp_cmd->wRow, otp_cmd->wRowCount, otp_cmd->bEcc); + cmd.bCmdId = PC_OTP_WRITE; +#ifdef _MSC_VER + cmd.bCmdSize = 5; // for some reason with MSVC, and only with picoboot_otp_cmd, the size is 6 not 5?? +#else + cmd.bCmdSize = sizeof(cmd.otp_cmd); +#endif + cmd.otp_cmd = *otp_cmd; + cmd.dTransferLength = len; + one_time_bulk_timeout = 5000 + len * 5; + return picoboot_cmd(usb_device, &cmd, buffer, len); +} -#if 0 +int picoboot_otp_read(libusb_device_handle *usb_device, struct picoboot_otp_cmd *otp_cmd, uint8_t *buffer, uint32_t len) { + struct picoboot_cmd cmd; + if (verbose) output("OTP READ %04x+%08x ecc=%d\n", (unsigned int) otp_cmd->wRow, otp_cmd->wRowCount, otp_cmd->bEcc); + cmd.bCmdId = PC_OTP_READ; +#ifdef _MSC_VER + cmd.bCmdSize = 5; // for some reason with MSVC, and only with picoboot_otp_cmd, the size is 6 not 5?? +#else + cmd.bCmdSize = sizeof(cmd.otp_cmd); +#endif + cmd.otp_cmd = *otp_cmd; + cmd.dTransferLength = len; + return picoboot_cmd(usb_device, &cmd, buffer, len); +} + +int picoboot_get_info(libusb_device_handle *usb_device, struct picoboot_get_info_cmd *get_info_cmd, uint8_t *buffer, uint32_t len) { + if (verbose) output("GET_INFO\n"); + struct picoboot_cmd cmd; + cmd.bCmdId = PC_GET_INFO; + cmd.bCmdSize = sizeof(cmd.get_info_cmd); + cmd.get_info_cmd = *get_info_cmd; + cmd.dTransferLength = len; + int ret = picoboot_cmd(usb_device, &cmd, buffer, len); + return ret; +} + +#if 1 // Peek/poke via EXEC // 00000000 : @@ -376,6 +561,7 @@ static const size_t picoboot_poke_cmd_len = 8; static const uint8_t picoboot_poke_cmd[] = { 0x01, 0x48, 0x02, 0x49, 0x08, 0x60, 0x70, 0x47 }; +#define PICOBOOT_POKE_CMD_PROG_SIZE (size_t)(8 + 8) // 00000000 : // 0: 4802 ldr r0, [pc, #8] ; (c ) @@ -391,19 +577,53 @@ static const size_t picoboot_peek_cmd_len = 12; static const uint8_t picoboot_peek_cmd[] = { 0x02, 0x48, 0x00, 0x68, 0x79, 0x46, 0x48, 0x60, 0x70, 0x47, 0xc0, 0x46 }; +#define PICOBOOT_PEEK_CMD_PROG_SIZE (size_t)(12 + 4) + +// todo - compile this - currently taken from github PR #86 +static const size_t picoboot_flash_id_cmd_len = 152; +static const uint8_t picoboot_flash_id_cmd[] = { + // void flash_get_unique_id(void) + 0x02, 0xa0, 0x06, 0xa1, 0x00, 0x4a, 0x11, 0xe0, + // int buflen + 0x0d, 0x00, 0x00, 0x00, + // char txbuf[13] + 0x4b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // char rxbuf[13] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + // void flash_do_cmd(txbuf, rxbuf, buflen) + 0x80, 0x23, 0xf0, 0xb5, 0x17, 0x4e, 0x9b, 0x00, + 0x34, 0x68, 0x63, 0x40, 0xc0, 0x24, 0xa4, 0x00, + 0x23, 0x40, 0x15, 0x4c, 0x23, 0x60, 0xc0, 0x24, + 0x13, 0x00, 0x64, 0x05, 0x17, 0x00, 0x1f, 0x43, + 0x06, 0xd1, 0xc0, 0x23, 0x32, 0x68, 0x9b, 0x00, + 0x93, 0x43, 0x0f, 0x4a, 0x13, 0x60, 0xf0, 0xbd, + 0x08, 0x25, 0xa7, 0x6a, 0x3d, 0x40, 0xac, 0x46, + 0x02, 0x25, 0x2f, 0x42, 0x08, 0xd0, 0x00, 0x2a, + 0x06, 0xd0, 0x9f, 0x1a, 0x0d, 0x2f, 0x03, 0xd8, + 0x07, 0x78, 0x01, 0x3a, 0x27, 0x66, 0x01, 0x30, + 0x65, 0x46, 0x00, 0x2d, 0xe2, 0xd0, 0x00, 0x2b, + 0xe0, 0xd0, 0x27, 0x6e, 0x01, 0x3b, 0x0f, 0x70, + 0x01, 0x31, 0xdb, 0xe7, 0x0c, 0x80, 0x01, 0x40, + 0x0c, 0x90, 0x01, 0x40, +}; +#define PICOBOOT_FLASH_ID_CMD_PROG_SIZE (size_t)(152) // TODO better place for this e.g. the USB DPRAM location the controller has already put it in #define PEEK_POKE_CODE_LOC 0x20000000u +#define FLASH_ID_CODE_LOC 0x15000000 // XIP_SRAM_BASE on RP2040, as we're not using XIP so probably fine +#define FLASH_ID_UID_ADDR (FLASH_ID_CODE_LOC + 28 + 1 + 4) + int picoboot_poke(libusb_device_handle *usb_device, uint32_t addr, uint32_t data) { - const size_t prog_size = picoboot_poke_cmd_len + 8; - uint8_t prog[prog_size]; + uint8_t prog[PICOBOOT_POKE_CMD_PROG_SIZE]; output("POKE (D)%08x -> (A)%08x\n", data, addr); memcpy(prog, picoboot_poke_cmd, picoboot_poke_cmd_len); *(uint32_t *) (prog + picoboot_poke_cmd_len) = data; *(uint32_t *) (prog + picoboot_poke_cmd_len + 4) = addr; - int ret = picoboot_write(usb_device, PEEK_POKE_CODE_LOC, prog, prog_size); + int ret = picoboot_write(usb_device, PEEK_POKE_CODE_LOC, prog, PICOBOOT_POKE_CMD_PROG_SIZE); if (ret) return ret; return picoboot_exec(usb_device, PEEK_POKE_CODE_LOC); @@ -411,13 +631,12 @@ int picoboot_poke(libusb_device_handle *usb_device, uint32_t addr, uint32_t data // TODO haven't checked the store goes to the right address :) int picoboot_peek(libusb_device_handle *usb_device, uint32_t addr, uint32_t *data) { - const size_t prog_size = picoboot_peek_cmd_len + 4; - uint8_t prog[prog_size]; + uint8_t prog[PICOBOOT_PEEK_CMD_PROG_SIZE]; output("PEEK %08x\n", addr); memcpy(prog, picoboot_peek_cmd, picoboot_peek_cmd_len); *(uint32_t *) (prog + picoboot_peek_cmd_len) = addr; - int ret = picoboot_write(usb_device, PEEK_POKE_CODE_LOC, prog, prog_size); + int ret = picoboot_write(usb_device, PEEK_POKE_CODE_LOC, prog, PICOBOOT_PEEK_CMD_PROG_SIZE); if (ret) return ret; ret = picoboot_exec(usb_device, PEEK_POKE_CODE_LOC); @@ -425,4 +644,36 @@ int picoboot_peek(libusb_device_handle *usb_device, uint32_t addr, uint32_t *dat return ret; return picoboot_read(usb_device, PEEK_POKE_CODE_LOC + picoboot_peek_cmd_len, (uint8_t *) data, sizeof(uint32_t)); } -#endif + +int picoboot_flash_id(libusb_device_handle *usb_device, uint64_t *data) { + picoboot_exclusive_access(usb_device, 1); + uint8_t prog[PICOBOOT_FLASH_ID_CMD_PROG_SIZE]; + uint64_t id; + output("GET FLASH ID\n"); + memcpy(prog, picoboot_flash_id_cmd, picoboot_flash_id_cmd_len); + + // ensure XIP is exited before executing + int ret = picoboot_exit_xip(usb_device); + if (ret) + goto flash_id_return; + ret = picoboot_write(usb_device, FLASH_ID_CODE_LOC, prog, PICOBOOT_FLASH_ID_CMD_PROG_SIZE); + if (ret) + goto flash_id_return; + ret = picoboot_exec(usb_device, FLASH_ID_CODE_LOC); + if (ret) + goto flash_id_return; + ret = picoboot_read(usb_device, FLASH_ID_UID_ADDR, (uint8_t *) &id, sizeof(uint64_t)); + *data = (((id & 0x00000000000000FF) << 56) | + ((id & 0x000000000000FF00) << 40) | + ((id & 0x0000000000FF0000) << 24) | + ((id & 0x00000000FF000000) << 8) | + ((id & 0x000000FF00000000) >> 8) | + ((id & 0x0000FF0000000000) >> 24) | + ((id & 0x00FF000000000000) >> 40) | + ((id & 0xFF00000000000000) >> 56)); + +flash_id_return: + picoboot_exclusive_access(usb_device, 0); + return ret; +} +#endif \ No newline at end of file diff --git a/lib/rp2040_flash/picoboot_connection.h b/lib/rp2040_flash/picoboot_connection.h index ebdabfc93ef8..875c35c0fa89 100644 --- a/lib/rp2040_flash/picoboot_connection.h +++ b/lib/rp2040_flash/picoboot_connection.h @@ -10,9 +10,21 @@ // todo we should use fully encapsulate libusb #include +#if HAS_LIBUSB #include +#endif #include "boot/picoboot.h" +#include "addresses.h" + +#define VENDOR_ID_RASPBERRY_PI 0x2e8au +#define PRODUCT_ID_RP2040_USBBOOT 0x0003u +#define PRODUCT_ID_PICOPROBE 0x0004u +#define PRODUCT_ID_MICROPYTHON 0x0005u +#define PRODUCT_ID_STDIO_USB 0x0009u +#define PRODUCT_ID_RP2040_STDIO_USB 0x000au +#define PRODUCT_ID_RP2350_USBBOOT 0x000fu + #ifdef __cplusplus extern "C" { #endif @@ -28,7 +40,20 @@ enum picoboot_device_result { dr_vidpid_stdio_usb, }; -enum picoboot_device_result picoboot_open_device(libusb_device *device, libusb_device_handle **dev_handle); +typedef enum { + rp2040, + rp2350, + unknown +} model_t; + +typedef enum { + rp2350_a2, + rp2350_unknown +} rp2350_version_t; + +#if HAS_LIBUSB +// note that vid and pid are filters, unless both are specified in which case a device with that VID and PID is allowed for RP2350 +enum picoboot_device_result picoboot_open_device(libusb_device *device, libusb_device_handle **dev_handle, model_t *model, int vid, int pid, const char* ser); int picoboot_reset(libusb_device_handle *usb_device); int picoboot_cmd_status_verbose(libusb_device_handle *usb_device, struct picoboot_cmd_status *status, @@ -38,26 +63,20 @@ int picoboot_exclusive_access(libusb_device_handle *usb_device, uint8_t exclusiv int picoboot_enter_cmd_xip(libusb_device_handle *usb_device); int picoboot_exit_xip(libusb_device_handle *usb_device); int picoboot_reboot(libusb_device_handle *usb_device, uint32_t pc, uint32_t sp, uint32_t delay_ms); +int picoboot_reboot2(libusb_device_handle *usb_device, struct picoboot_reboot2_cmd *reboot_cmd); +int picoboot_get_info(libusb_device_handle *usb_device, struct picoboot_get_info_cmd *cmd, uint8_t *buffer, uint32_t len); int picoboot_exec(libusb_device_handle *usb_device, uint32_t addr); +// int picoboot_exec2(libusb_device_handle *usb_device, struct picoboot_exec2_cmd *exec2_cmd); // currently unused int picoboot_flash_erase(libusb_device_handle *usb_device, uint32_t addr, uint32_t len); int picoboot_vector(libusb_device_handle *usb_device, uint32_t addr); int picoboot_write(libusb_device_handle *usb_device, uint32_t addr, uint8_t *buffer, uint32_t len); int picoboot_read(libusb_device_handle *usb_device, uint32_t addr, uint8_t *buffer, uint32_t len); +int picoboot_otp_write(libusb_device_handle *usb_device, struct picoboot_otp_cmd *otp_cmd, uint8_t *buffer, uint32_t len); +int picoboot_otp_read(libusb_device_handle *usb_device, struct picoboot_otp_cmd *otp_cmd, uint8_t *buffer, uint32_t len); int picoboot_poke(libusb_device_handle *usb_device, uint32_t addr, uint32_t data); int picoboot_peek(libusb_device_handle *usb_device, uint32_t addr, uint32_t *data); - -#define ROM_START 0x00000000 -#define ROM_END 0x00004000 -#define FLASH_START 0x10000000 -#define FLASH_END 0x11000000 // this is maximum -#define XIP_SRAM_BASE 0x15000000 -#define XIP_SRAM_END 0x15004000 - -#define SRAM_START 0x20000000 -#define SRAM_END 0x20042000 - -#define SRAM_UNSTRIPED_START 0x21000000 -#define SRAM_UNSTRIPED_END 0x21040000 +int picoboot_flash_id(libusb_device_handle *usb_device, uint64_t *data); +#endif // we require 256 (as this is the page size supported by the device) #define LOG2_PAGE_SIZE 8u @@ -74,27 +93,44 @@ enum memory_type { }; // inclusive of ends -static inline enum memory_type get_memory_type(uint32_t addr) { - if (addr >= ROM_START && addr <= ROM_END) { - return rom; - } - if (addr >= FLASH_START && addr <= FLASH_END) { +static inline enum memory_type get_memory_type(uint32_t addr, model_t model) { + if (addr >= FLASH_START && addr <= FLASH_END_RP2040) { return flash; } - if (addr >= SRAM_START && addr <= SRAM_END) { + if (addr >= ROM_START && addr <= ROM_END_RP2040) { + return rom; + } + if (addr >= SRAM_START && addr <= SRAM_END_RP2040) { return sram; } - if (addr >= SRAM_UNSTRIPED_START && addr <= SRAM_UNSTRIPED_END) { + if (model == rp2350) { + if (addr >= FLASH_START && addr <= FLASH_END_RP2350) { + return flash; + } + if (addr >= ROM_START && addr <= ROM_END_RP2350) { + return rom; + } + if (addr >= SRAM_START && addr <= SRAM_END_RP2350) { + return sram; + } + } + if (addr >= MAIN_RAM_BANKED_START && addr <= MAIN_RAM_BANKED_END) { return sram_unstriped; } - if (addr >= XIP_SRAM_BASE && addr <= XIP_SRAM_END) { - return xip_sram; + if (model == rp2040) { + if (addr >= XIP_SRAM_START_RP2040 && addr <= XIP_SRAM_END_RP2040) { + return xip_sram; + } + } else if (model == rp2350) { + if (addr >= XIP_SRAM_START_RP2350 && addr <= XIP_SRAM_END_RP2350) { + return xip_sram; + } } return invalid; } -static inline bool is_transfer_aligned(uint32_t addr) { - enum memory_type t = get_memory_type(addr); +static inline bool is_transfer_aligned(uint32_t addr, model_t model) { + enum memory_type t = get_memory_type(addr, model); return t != invalid && !(t == flash && addr & (PAGE_SIZE-1)); } diff --git a/scripts/ci-install.sh b/scripts/ci-install.sh index f5a18612ffa8..470bab46bec0 100755 --- a/scripts/ci-install.sh +++ b/scripts/ci-install.sh @@ -20,6 +20,7 @@ PKGS="virtualenv python2-dev libffi-dev build-essential" PKGS="${PKGS} gcc-avr avr-libc" PKGS="${PKGS} libnewlib-arm-none-eabi gcc-arm-none-eabi binutils-arm-none-eabi" PKGS="${PKGS} pv libmpfr-dev libgmp-dev libmpc-dev texinfo bison flex" +sudo apt-get update sudo apt-get install ${PKGS} diff --git a/scripts/flash_usb.py b/scripts/flash_usb.py index 33c437602d20..e290f7f35911 100755 --- a/scripts/flash_usb.py +++ b/scripts/flash_usb.py @@ -198,7 +198,7 @@ def flash_picoboot(device, binfile, sudo): # We need one level up to get access to busnum/devnum files usbdir = os.path.dirname(devpath) enter_bootloader(device) - wait_path(usbdir) + wait_path(usbdir + "/busnum") with open(usbdir + "/busnum") as f: bus = f.read().strip() with open(usbdir + "/devnum") as f: @@ -321,7 +321,7 @@ def flash_stm32f4(options, binfile): If the device is already in bootloader mode it can be flashed with the following command: - make flash FLASH_DEVICE=2e8a:0003 + make flash FLASH_DEVICE=%s Alternatively, one can flash rp2040 boards like the Pico by manually entering bootloader mode(hold bootsel button during powerup), mount the @@ -330,13 +330,16 @@ def flash_stm32f4(options, binfile): """ def flash_rp2040(options, binfile): + rawdev = "2e8a:0003" + if options.mcutype == 'rp2350': + rawdev = "2e8a:000f" try: - if options.device.lower() == "2e8a:0003": + if options.device.lower() == rawdev: call_picoboot(None, None, binfile, options.sudo) else: flash_picoboot(options.device, binfile, options.sudo) except error as e: - sys.stderr.write(RP2040_HELP % (options.device, str(e))) + sys.stderr.write(RP2040_HELP % (options.device, str(e), rawdev)) sys.exit(-1) MCUTYPES = { @@ -347,7 +350,7 @@ def flash_rp2040(options, binfile): 'stm32f070': flash_stm32f4, 'stm32f072': flash_stm32f4, 'stm32g0b1': flash_stm32f4, 'stm32f7': flash_stm32f4, 'stm32h7': flash_stm32f4, 'stm32l4': flash_stm32f4, - 'stm32g4': flash_stm32f4, 'rp2040': flash_rp2040, + 'stm32g4': flash_stm32f4, 'rp2': flash_rp2040, } diff --git a/scripts/spi_flash/board_defs.py b/scripts/spi_flash/board_defs.py index 4f84d7229c8e..9924fefcd70e 100644 --- a/scripts/spi_flash/board_defs.py +++ b/scripts/spi_flash/board_defs.py @@ -31,6 +31,11 @@ 'spi_bus': "spi1", "cs_pin": "PA4" }, + 'btt-skr-mini-v3-b0': { + 'mcu': "stm32g0b0xx", + 'spi_bus': "spi1", + "cs_pin": "PA4" + }, 'flyboard-mini': { 'mcu': "stm32f103xe", 'spi_bus': "spi2", @@ -41,6 +46,7 @@ 'mcu': "stm32f103xe", 'spi_bus': "spi2", "cs_pin": "PA15", + "conversion_script": "scripts/update_mks_robin.py", "firmware_path": "Robin_e3.bin", "current_firmware_path": "Robin_e3.cur" }, @@ -128,6 +134,16 @@ 'mcu': "stm32g0b1xx", 'spi_bus': "spi1", "cs_pin": "PB8" + }, + 'chitu-v6': { + 'mcu': "stm32f103xe", + 'spi_bus': "swspi", + 'spi_pins': "PC8,PD2,PC12", + "cs_pin": "PC11", + #'sdio_bus': 'sdio', + "conversion_script": "scripts/update_chitu.py", + "firmware_path": "update.cbd", + 'skip_verify': True } } @@ -152,6 +168,7 @@ 'btt-skr-mini-e3-v1.2': BOARD_DEFS['btt-skr-mini'], 'btt-skr-mini-e3-v2': BOARD_DEFS['btt-skr-mini'], 'btt-skr-mini-e3-v3': BOARD_DEFS['btt-skr-mini-v3'], + 'btt-skr-mini-e3-v3-b0': BOARD_DEFS['btt-skr-mini-v3-b0'], 'btt-skr-mini-mz': BOARD_DEFS['btt-skr-mini'], 'btt-skr-e3-dip': BOARD_DEFS['btt-skr-mini'], 'btt002-v1': BOARD_DEFS['btt-skr-mini'], @@ -176,7 +193,8 @@ 'fysetc-s6-v1.2': BOARD_DEFS['fysetc-spider'], 'fysetc-s6-v2': BOARD_DEFS['fysetc-spider'], 'robin_v3': BOARD_DEFS['monster8'], - 'btt-skrat-v1.0': BOARD_DEFS['btt-skrat'] + 'btt-skrat-v1.0': BOARD_DEFS['btt-skrat'], + 'chitu-v6': BOARD_DEFS['chitu-v6'] } def list_boards(): diff --git a/scripts/spi_flash/spi_flash.py b/scripts/spi_flash/spi_flash.py index a3231b693219..cbe769e573f1 100644 --- a/scripts/spi_flash/spi_flash.py +++ b/scripts/spi_flash/spi_flash.py @@ -74,20 +74,19 @@ def translate_serial_to_tty(device): return ttyname, ttyname def check_need_convert(board_name, config): - if board_name.lower().startswith('mks-robin-e3'): - # we need to convert this file - robin_util = os.path.join( - fatfs_lib.KLIPPER_DIR, "scripts/update_mks_robin.py") - klipper_bin = config['klipper_bin_path'] - robin_bin = os.path.join( + conv_script = config.get("conversion_script") + if conv_script is None: + return + conv_util = os.path.join(fatfs_lib.KLIPPER_DIR, conv_script) + klipper_bin = config['klipper_bin_path'] + dest_bin = os.path.join( os.path.dirname(klipper_bin), os.path.basename(config['firmware_path'])) - cmd = "%s %s %s %s" % (sys.executable, robin_util, klipper_bin, - robin_bin) - output("Converting Klipper binary to MKS Robin format...") - os.system(cmd) - output_line("Done") - config['klipper_bin_path'] = robin_bin + cmd = "%s %s %s %s" % (sys.executable, conv_util, klipper_bin, dest_bin) + output("Converting Klipper binary to custom format...") + os.system(cmd) + output_line("Done") + config['klipper_bin_path'] = dest_bin ########################################################### diff --git a/scripts/whconsole.py b/scripts/whconsole.py index ba77ae9bba9c..5e76b3bcea61 100755 --- a/scripts/whconsole.py +++ b/scripts/whconsole.py @@ -38,25 +38,25 @@ def __init__(self, uds_filename): self.poll = select.poll() self.poll.register(sys.stdin, select.POLLIN | select.POLLHUP) self.poll.register(self.webhook_socket, select.POLLIN | select.POLLHUP) - self.kbd_data = self.socket_data = "" + self.kbd_data = self.socket_data = b"" def process_socket(self): data = self.webhook_socket.recv(4096) if not data: sys.stderr.write("Socket closed\n") sys.exit(0) - parts = data.split('\x03') + parts = data.split(b'\x03') parts[0] = self.socket_data + parts[0] self.socket_data = parts.pop() for line in parts: sys.stdout.write("GOT: %s\n" % (line,)) def process_kbd(self): data = os.read(self.kbd_fd, 4096) - parts = data.split('\n') + parts = data.split(b'\n') parts[0] = self.kbd_data + parts[0] self.kbd_data = parts.pop() for line in parts: line = line.strip() - if not line or line.startswith('#'): + if not line or line.startswith(b'#'): continue try: m = json.loads(line) @@ -65,7 +65,7 @@ def process_kbd(self): continue cm = json.dumps(m, separators=(',', ':')) sys.stdout.write("SEND: %s\n" % (cm,)) - self.webhook_socket.send("%s\x03" % (cm,)) + self.webhook_socket.send(cm.encode() + b"\x03") def run(self): while 1: res = self.poll.poll(1000.) diff --git a/src/Kconfig b/src/Kconfig index 7dcea3bab59d..ad326e729b2e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -13,17 +13,17 @@ choice config MACH_AVR bool "Atmega AVR" config MACH_ATSAM - bool "SAM3/SAM4/SAM E70 (Due and Duet)" + bool "SAM3/SAM4/SAM E70" config MACH_ATSAMD bool "SAMC21/SAMD21/SAMD51/SAME5x" config MACH_LPC176X - bool "LPC176x (Smoothieboard)" + bool "LPC176x" config MACH_STM32 bool "STMicroelectronics STM32" config MACH_HC32F460 bool "Huada Semiconductor HC32F460" - config MACH_RP2040 - bool "Raspberry Pi RP2040" + config MACH_RPXXXX + bool "Raspberry Pi RP2040/RP235x" config MACH_PRU bool "Beaglebone PRU" config MACH_AR100 @@ -102,12 +102,20 @@ config WANT_SENSORS default y config WANT_LIS2DW bool - depends on HAVE_GPIO_SPI + depends on HAVE_GPIO_SPI || HAVE_GPIO_I2C default y config WANT_LDC1612 bool depends on HAVE_GPIO_I2C default y +config WANT_HX71X + bool + depends on WANT_GPIO_BITBANGING + default y +config WANT_ADS1220 + bool + depends on HAVE_GPIO_SPI + default y config WANT_SOFTWARE_I2C bool depends on HAVE_GPIO && HAVE_GPIO_I2C @@ -118,7 +126,8 @@ config WANT_SOFTWARE_SPI default y config NEED_SENSOR_BULK bool - depends on WANT_SENSORS || WANT_LIS2DW || WANT_LDC1612 + depends on WANT_SENSORS || WANT_LIS2DW || WANT_LDC1612 || WANT_HX71X \ + || WANT_ADS1220 default y menu "Optional features (to reduce code size)" depends on HAVE_LIMITED_CODE_SIZE @@ -132,11 +141,17 @@ config WANT_SENSORS bool "Support external sensor devices" depends on HAVE_GPIO_I2C || HAVE_GPIO_SPI config WANT_LIS2DW - bool "Support lis2dw 3-axis accelerometer" - depends on HAVE_GPIO_SPI + bool "Support lis2dw and lis3dh 3-axis accelerometers" + depends on HAVE_GPIO_SPI || HAVE_GPIO_I2C config WANT_LDC1612 bool "Support ldc1612 eddy current sensor" depends on HAVE_GPIO_I2C +config WANT_HX71X + bool "Support HX711 and HX717 ADC chips" + depends on WANT_GPIO_BITBANGING +config WANT_ADS1220 + bool "Support ADS 1220 ADC chip" + depends on HAVE_GPIO_SPI config WANT_SOFTWARE_I2C bool "Support software based I2C \"bit-banging\"" depends on HAVE_GPIO && HAVE_GPIO_I2C diff --git a/src/Makefile b/src/Makefile index ed98172e4e8d..86c7407e687f 100644 --- a/src/Makefile +++ b/src/Makefile @@ -20,4 +20,6 @@ sensors-src-$(CONFIG_HAVE_GPIO_I2C) += sensor_mpu9250.c src-$(CONFIG_WANT_SENSORS) += $(sensors-src-y) src-$(CONFIG_WANT_LIS2DW) += sensor_lis2dw.c src-$(CONFIG_WANT_LDC1612) += sensor_ldc1612.c +src-$(CONFIG_WANT_HX71X) += sensor_hx71x.c +src-$(CONFIG_WANT_ADS1220) += sensor_ads1220.c src-$(CONFIG_NEED_SENSOR_BULK) += sensor_bulk.c diff --git a/src/ar100/gpio.h b/src/ar100/gpio.h index b5eea2f94186..2d29a7dcdd02 100644 --- a/src/ar100/gpio.h +++ b/src/ar100/gpio.h @@ -40,4 +40,8 @@ void spi_prepare(struct spi_config config); void spi_transfer(struct spi_config config, uint8_t receive_data , uint8_t len, uint8_t *data); +struct i2c_config { + void *cfg; +}; + #endif diff --git a/src/atsam/Kconfig b/src/atsam/Kconfig index 4a10a0f7d162..4c20c2440064 100644 --- a/src/atsam/Kconfig +++ b/src/atsam/Kconfig @@ -22,19 +22,19 @@ config BOARD_DIRECTORY choice prompt "Processor model" config MACH_SAM3X8E - bool "SAM3x8e (Arduino Due)" + bool "SAM3x8e" select MACH_SAM3X config MACH_SAM3X8C - bool "SAM3x8c (Printrboard G2)" + bool "SAM3x8c" select MACH_SAM3X config MACH_SAM4S8C - bool "SAM4s8c (Duet Maestro)" + bool "SAM4s8c" select MACH_SAM4S config MACH_SAM4E8E - bool "SAM4e8e (Duet Wifi/Eth)" + bool "SAM4e8e" select MACH_SAM4E config MACH_SAME70Q20B - bool "SAME70Q20B (Duet 3 6HC)" + bool "SAME70Q20B" select MACH_SAME70 endchoice @@ -70,6 +70,7 @@ config CLOCK_FREQ config FLASH_SIZE hex + default 0x20000 if MACH_SAME70 default 0x80000 config FLASH_BOOT_ADDRESS @@ -84,8 +85,7 @@ config RAM_START config RAM_SIZE hex default 0x18000 if MACH_SAM3X - default 0x20000 if MACH_SAM4 - default 0x40000 if MACH_SAME70 + default 0x20000 if MACH_SAM4 || MACH_SAME70 config STACK_SIZE int @@ -93,9 +93,25 @@ config STACK_SIZE config FLASH_APPLICATION_ADDRESS hex - default 0x400000 if MACH_SAM4 || MACH_SAME70 + default 0x0 if MACH_SAME70 + default 0x400000 if MACH_SAM4 default 0x80000 +config ARMCM_ITCM_FLASH_MIRROR_START + depends on MACH_SAME70 + hex + default 0x400000 + +config ARMCM_DTCM_START + depends on MACH_SAME70 + hex + default 0x20000000 + +config ARMCM_DTCM_SIZE + depends on MACH_SAME70 + hex + default 0x20000 + choice prompt "Communication interface" config ATSAM_USB diff --git a/src/atsam/Makefile b/src/atsam/Makefile index 3595d0cef40f..15bef326201d 100644 --- a/src/atsam/Makefile +++ b/src/atsam/Makefile @@ -20,9 +20,10 @@ CFLAGS-$(CONFIG_MACH_SAM4E) += -Ilib/sam4e/include CFLAGS-$(CONFIG_MACH_SAME70) += -Ilib/same70b/include CFLAGS += $(CFLAGS-y) -D__$(MCU)__ -mthumb -Ilib/cmsis-core -Ilib/fast-hash -CFLAGS_klipper.elf += -nostdlib -lgcc -lc_nano -CFLAGS_klipper.elf += -T $(OUT)src/generic/armcm_link.ld -$(OUT)klipper.elf: $(OUT)src/generic/armcm_link.ld +samlink-y := $(OUT)src/generic/armcm_link.ld +samlink-$(CONFIG_MACH_SAME70) := $(OUT)src/atsam/same70_link.ld +CFLAGS_klipper.elf += -nostdlib -lgcc -lc_nano -T $(samlink-y) +$(OUT)klipper.elf: $(samlink-y) # Add source files src-y += atsam/main.c atsam/gpio.c atsam/i2c.c atsam/spi.c diff --git a/src/atsam/fdcan.c b/src/atsam/fdcan.c index a536a7be1ed6..deeb607063c1 100644 --- a/src/atsam/fdcan.c +++ b/src/atsam/fdcan.c @@ -71,8 +71,8 @@ struct fdcan_msg_ram { struct fdcan_fifo TXFIFO[3]; }; -// Message ram is in regular memory -static struct fdcan_msg_ram MSG_RAM; +// Message ram is in DTCM - locate it there to avoid cache. +static struct fdcan_msg_ram MSG_RAM __section(".dtcm.bss"); /**************************************************************** diff --git a/src/atsam/gpio.h b/src/atsam/gpio.h index e9fc4c3ed040..638d02da4d10 100644 --- a/src/atsam/gpio.h +++ b/src/atsam/gpio.h @@ -50,8 +50,8 @@ struct i2c_config { }; struct i2c_config i2c_setup(uint32_t bus, uint32_t rate, uint8_t addr); -void i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); -void i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg - , uint8_t read_len, uint8_t *read); +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg + , uint8_t read_len, uint8_t *read); #endif // gpio.h diff --git a/src/atsam/i2c.c b/src/atsam/i2c.c index 0661727c274e..8c3dc8ad2428 100644 --- a/src/atsam/i2c.c +++ b/src/atsam/i2c.c @@ -10,6 +10,7 @@ #include "gpio.h" // i2c_setup #include "internal.h" // gpio_peripheral #include "sched.h" // sched_shutdown +#include "i2ccmds.h" // I2C_BUS_SUCCESS #if CONFIG_MACH_SAME70 #include "same70_i2c.h" // Fixes for upstream header changes @@ -126,7 +127,7 @@ i2c_setup(uint32_t bus, uint32_t rate, uint8_t addr) return (struct i2c_config){ .twi=p_twi, .addr=addr}; } -void +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write) { Twi *p_twi = config.twi; @@ -150,9 +151,11 @@ i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write) p_twi->TWI_CR = TWI_CR_STOP; while (!(p_twi->TWI_SR & TWI_SR_TXCOMP)) ; + + return I2C_BUS_SUCCESS; } -void +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg , uint8_t read_len, uint8_t *read) { @@ -192,4 +195,6 @@ i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg while (!(p_twi->TWI_SR & TWI_SR_TXCOMP)) ; (void)p_twi->TWI_SR; + + return I2C_BUS_SUCCESS; } diff --git a/src/atsam/sam3_usb.c b/src/atsam/sam3_usb.c index a76d7c751a56..a26a6961b8b7 100644 --- a/src/atsam/sam3_usb.c +++ b/src/atsam/sam3_usb.c @@ -32,6 +32,7 @@ usb_write_packet(uint32_t ep, const uint8_t *data, uint32_t len) uint8_t *dest = usb_fifo(ep); while (len--) *dest++ = *data++; + __DMB(); } static void diff --git a/src/atsam/same70_link.lds.S b/src/atsam/same70_link.lds.S new file mode 100644 index 000000000000..8dd5e1b3bdbd --- /dev/null +++ b/src/atsam/same70_link.lds.S @@ -0,0 +1,81 @@ +// Generic ARM Cortex-M linker script +// +// Copyright (C) 2019-2024 Kevin O'Connor +// Copyright (C) 2024 Luke Vuksta +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "autoconf.h" // CONFIG_FLASH_APPLICATION_ADDRESS + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +MEMORY +{ + rom (rx) : ORIGIN = CONFIG_FLASH_APPLICATION_ADDRESS , LENGTH = CONFIG_FLASH_SIZE + ram (rwx) : ORIGIN = CONFIG_RAM_START , LENGTH = CONFIG_RAM_SIZE + dtcm (rw) : ORIGIN = CONFIG_ARMCM_DTCM_START , LENGTH = CONFIG_ARMCM_DTCM_SIZE +} + +SECTIONS +{ + .text : AT (CONFIG_ARMCM_ITCM_FLASH_MIRROR_START) { + . = ALIGN(4); + _text_vectortable_start = .; + KEEP(*(.vector_table)) + _text_vectortable_end = .; + *(.text .text.*) + *(.ramfunc .ramfunc.*) + *(.rodata .rodata*) + } > rom + + _text_size = SIZEOF (.text); + . = CONFIG_ARMCM_ITCM_FLASH_MIRROR_START + _text_size; + . = ALIGN(4); + _data_flash = .; + + .data : AT (_data_flash) + { + . = ALIGN(4); + _data_start = .; + *(.data .data.*) + . = ALIGN(4); + _data_end = .; + } > ram + + .bss (NOLOAD) : + { + . = ALIGN(4); + _bss_start = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _bss_end = .; + } > ram + + _stack_start = CONFIG_RAM_START + CONFIG_RAM_SIZE - CONFIG_STACK_SIZE ; + .stack _stack_start (NOLOAD) : + { + . = . + CONFIG_STACK_SIZE; + _stack_end = .; + } > ram + + .dtcm_bss (NOLOAD) : + { + . = ALIGN(4); + _dtcm_bss_start = .; + *(.dtcm.bss) + . = ALIGN(4); + _dtcm_bss_end = .; + } > dtcm + + /DISCARD/ : { + // The .init/.fini sections are used by __libc_init_array(), but + // that isn't needed so no need to include them in the binary. + *(.init) + *(.fini) + // Don't include exception tables + *(.ARM.extab) + *(.ARM.exidx) + } +} diff --git a/src/atsam/same70_sysinit.c b/src/atsam/same70_sysinit.c index 4cb5f48cc2df..d2b6ecb4715c 100644 --- a/src/atsam/same70_sysinit.c +++ b/src/atsam/same70_sysinit.c @@ -1,5 +1,6 @@ // This code is from lib/sam4e/gcc/system_sam4e.c and modified for the SAM E70 +#include // memset #include "internal.h" /* Clock Settings (300MHz) */ @@ -9,13 +10,17 @@ | CKGR_PLLAR_PLLACOUNT(0x3fU) \ | CKGR_PLLAR_DIVA_BYPASS) #define SYS_BOARD_MCKR (PMC_MCKR_MDIV_PCK_DIV2 | PMC_MCKR_CSS_PLLA_CLK) +#define RST_PARAMS ((0xA5 << RSTC_CR_KEY_Pos) | RSTC_CR_PROCRST) +#define GPNVM_TCM_MASK ((1 << 7) | (1 << 8)) /* Key to unlock MOR register */ #define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) -uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_12MHZ; +extern uint32_t _text_size; +extern uint32_t _dtcm_bss_start, _dtcm_bss_end; -void SystemInit( void ) +void +SystemInit( void ) { /* Set FWS according to SYS_BOARD_MCKR configuration */ EFC->EEFC_FMR = EEFC_FMR_FWS(6) | EEFC_FMR_CLOE; @@ -66,12 +71,84 @@ void SystemInit( void ) { } - SystemCoreClock = CHIP_FREQ_CPU_MAX; - - // Configure PCK6 for TC use + /* Configure PCK6 for TC use */ PMC->PMC_PCK[6] = PMC_PCK_CSS_MCK | PMC_PCK_PRES(2); while ( !(PMC->PMC_SR & PMC_SR_PCKRDY6) ) { } PMC->PMC_SCER |= PMC_SCER_PCK6; + + /* Check Tightly Coupled Memory (TCM) bits. */ + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_GGPB); + while ((EFC->EEFC_FSR & EEFC_FSR_FRDY) == 0) + ; + if ((EFC->EEFC_FRR & GPNVM_TCM_MASK) != GPNVM_TCM_MASK) + { + /* Configure TCM sizes to 128KiB (set GPNVM7 and GPNVM8). */ + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_SGPB + | EEFC_FCR_FARG(7)); + while ((EFC->EEFC_FSR & EEFC_FSR_FRDY) == 0) + ; + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD| EEFC_FCR_FCMD_SGPB + | EEFC_FCR_FARG(8)); + while ((EFC->EEFC_FSR & EEFC_FSR_FRDY) == 0) + ; + /* Reboot required, but bits are set now and we will not + * return down this path. */ + __DSB(); + __ISB(); + RSTC->RSTC_CR = RST_PARAMS; + for (;;) + ; + } + + /* Clear Data Tightly Coupled Memory (DTCM) bss segment - this has to happen + * after we check that the DTCM is enabled. */ + memset(&_dtcm_bss_start, 0, (&_dtcm_bss_end - &_dtcm_bss_start) * 4); + + /* DMA copy flash to Instruction Tightly Coupled Memory (ITCM). Just use + * channel 0 since we have not done anything yet. */ + enable_pclock(ID_XDMAC); + /* Clear pending interrupts. */ + (void)REG_XDMAC_CIS0; + REG_XDMAC_CSA0 = CONFIG_ARMCM_ITCM_FLASH_MIRROR_START; + REG_XDMAC_CDA0 = CONFIG_FLASH_APPLICATION_ADDRESS; + REG_XDMAC_CUBC0 = XDMAC_CUBC_UBLEN((int)&_text_size); + + REG_XDMAC_CC0 = + XDMAC_CC_TYPE_MEM_TRAN | XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_WORD | + XDMAC_CC_SAM_INCREMENTED_AM | XDMAC_CC_DAM_INCREMENTED_AM | + XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF0; + + REG_XDMAC_CNDA0 = 0; + REG_XDMAC_CNDC0 = 0; + REG_XDMAC_CBC0 = 0; + REG_XDMAC_CDS_MSP0 = 0; + REG_XDMAC_CSUS0 = 0; + REG_XDMAC_CDUS0 = 0; + + REG_XDMAC_CIE0 = XDMAC_CIE_BIE; + + __DSB(); + __ISB(); + XDMAC->XDMAC_GE = XDMAC_GE_EN0; + while ( XDMAC->XDMAC_GS & XDMAC_GS_ST0 ) + ; + + while ( !(REG_XDMAC_CIS0 & XDMAC_CIS_BIS) ) + ; + + /* Enable ITCM. DTCM is enabled by default. */ + __DSB(); + __ISB(); + SCB->ITCMCR = (SCB_ITCMCR_EN_Msk | SCB_ITCMCR_RMW_Msk + | SCB_ITCMCR_RETEN_Msk); + __DSB(); + __ISB(); + + /* Use data cache rather than DTCM for two reasons: + * 1. It is hard to flash this device with GPNVM bits enabled. + * 2. It is about as fast. */ + SCB_EnableDCache(); } diff --git a/src/atsamd/Kconfig b/src/atsamd/Kconfig index 6ba0d7e6e6da..5711566a3de0 100644 --- a/src/atsamd/Kconfig +++ b/src/atsamd/Kconfig @@ -27,35 +27,38 @@ config BOARD_DIRECTORY choice prompt "Processor model" config MACH_SAMC21G18 - bool "SAMC21G18 (Duet 3 Toolboard 1LC)" + bool "SAMC21G18" select MACH_SAMC21 config MACH_SAMD21G18 - bool "SAMD21G18 (Arduino Zero)" + bool "SAMD21G18" select MACH_SAMD21 config MACH_SAMD21E18 - bool "SAMD21E18 (Adafruit Trinket M0)" + bool "SAMD21E18" select MACH_SAMD21 config MACH_SAMD21J18 - bool "SAMD21J18 (ReprapWorld Minitronics v2)" + bool "SAMD21J18" select MACH_SAMD21 config MACH_SAMD21E15 bool "SAMD21E15" select MACH_SAMD21 config MACH_SAMD51G19 - bool "SAMD51G19 (Adafruit ItsyBitsy M4)" + bool "SAMD51G19" select MACH_SAMD51 config MACH_SAMD51J19 - bool "SAMD51J19 (Adafruit Metro M4)" + bool "SAMD51J19" select MACH_SAMD51 config MACH_SAMD51N19 bool "SAMD51N19" select MACH_SAMD51 config MACH_SAMD51P20 - bool "SAMD51P20 (Adafruit Grand Central)" + bool "SAMD51P20" select MACH_SAMD51 config MACH_SAME51J19 bool "SAME51J19" select MACH_SAME51 + config MACH_SAME51N19 + bool "SAME51N19" + select MACH_SAME51 config MACH_SAME54P20 bool "SAME54P20" select MACH_SAME54 @@ -100,13 +103,14 @@ config MCU default "samd51n19a" if MACH_SAMD51N19 default "samd51p20a" if MACH_SAMD51P20 default "same51j19a" if MACH_SAME51J19 + default "same51n19a" if MACH_SAME51N19 default "same54p20a" if MACH_SAME54P20 config FLASH_SIZE hex default 0x8000 if MACH_SAMD21E15 default 0x40000 if MACH_SAMC21G18 || MACH_SAMD21G18 || MACH_SAMD21E18 || MACH_SAMD21J18 - default 0x80000 if MACH_SAMD51G19 || MACH_SAMD51J19 || MACH_SAMD51N19 || MACH_SAME51J19 + default 0x80000 if MACH_SAMD51G19 || MACH_SAMD51J19 || MACH_SAMD51N19 || MACH_SAME51J19 || MACH_SAME51N19 default 0x100000 if MACH_SAMD51P20 || MACH_SAME54P20 config FLASH_BOOT_ADDRESS @@ -121,7 +125,7 @@ config RAM_SIZE hex default 0x1000 if MACH_SAMD21E15 default 0x8000 if MACH_SAMC21G18 || MACH_SAMD21G18 || MACH_SAMD21E18 || MACH_SAMD21J18 - default 0x30000 if MACH_SAMD51G19 || MACH_SAMD51J19 || MACH_SAMD51N19 || MACH_SAME51J19 + default 0x30000 if MACH_SAMD51G19 || MACH_SAMD51J19 || MACH_SAMD51N19 || MACH_SAME51J19 || MACH_SAME51N19 default 0x40000 if MACH_SAMD51P20 || MACH_SAME54P20 config STACK_SIZE @@ -137,9 +141,9 @@ choice prompt "Bootloader offset" config SAMD_FLASH_START_2000 depends on MACH_SAMD21 - bool "8KiB bootloader (Arduino Zero)" + bool "8KiB bootloader" config SAMD_FLASH_START_4000 - bool "16KiB bootloader (Arduino M0, Duet 3 Bootloader)" + bool "16KiB bootloader" config SAMD_FLASH_START_0000 bool "No bootloader" endchoice diff --git a/src/atsamd/gpio.h b/src/atsamd/gpio.h index b8cb3e861d19..d29071dc6f77 100644 --- a/src/atsamd/gpio.h +++ b/src/atsamd/gpio.h @@ -51,8 +51,8 @@ struct i2c_config { }; struct i2c_config i2c_setup(uint32_t bus, uint32_t rate, uint8_t addr); -void i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); -void i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg - , uint8_t read_len, uint8_t *read); +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg + , uint8_t read_len, uint8_t *read); #endif // gpio.h diff --git a/src/atsamd/i2c.c b/src/atsamd/i2c.c index 3c316142ce5b..5897a7760d35 100644 --- a/src/atsamd/i2c.c +++ b/src/atsamd/i2c.c @@ -9,12 +9,14 @@ #include "command.h" // shutdown #include "gpio.h" // i2c_setup #include "sched.h" // sched_shutdown +#include "i2ccmds.h" // I2C_BUS_SUCCESS #define TIME_RISE 125ULL // 125 nanoseconds -#define I2C_FREQ 100000 +#define I2C_FREQ 100000 +#define I2C_FREQ_FAST 400000 static void -i2c_init(uint32_t bus, SercomI2cm *si) +i2c_init(uint32_t bus, uint32_t rate, SercomI2cm *si) { static uint8_t have_run_init; if (have_run_init & (1<CTRLA.reg = areg; uint32_t freq = sercom_get_pclock_frequency(bus); - uint32_t baud = (freq/I2C_FREQ - 10 - freq*TIME_RISE/1000000000) / 2; + uint32_t baud = 0; + if (rate < I2C_FREQ_FAST) { + baud = (freq/I2C_FREQ - 10 - freq*TIME_RISE/1000000000) / 2; + } else { + baud = (freq/I2C_FREQ_FAST - 10 - freq*TIME_RISE/1000000000) / 2; + } si->BAUD.reg = baud; si->CTRLA.reg = areg | SERCOM_I2CM_CTRLA_ENABLE; while (si->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) @@ -46,7 +53,7 @@ i2c_setup(uint32_t bus, uint32_t rate, uint8_t addr) Sercom *sercom = sercom_enable_pclock(bus); sercom_i2c_pins(bus); SercomI2cm *si = &sercom->I2CM; - i2c_init(bus, si); + i2c_init(bus, rate, si); return (struct i2c_config){ .si=si, .addr=addr<<1 }; } @@ -86,7 +93,7 @@ i2c_stop(SercomI2cm *si) si->CTRLB.reg = SERCOM_I2CM_CTRLB_CMD(3); } -void +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write) { SercomI2cm *si = (SercomI2cm *)config.si; @@ -94,9 +101,11 @@ i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write) while (write_len--) i2c_send_byte(si, *write++); i2c_stop(si); + + return I2C_BUS_SUCCESS; } -void +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg , uint8_t read_len, uint8_t *read) { @@ -143,4 +152,6 @@ i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg // read received data byte *read++ = si->DATA.reg; } + + return I2C_BUS_SUCCESS; } diff --git a/src/avr/gpio.h b/src/avr/gpio.h index 9d98ee709218..9f28a30acdad 100644 --- a/src/avr/gpio.h +++ b/src/avr/gpio.h @@ -50,8 +50,8 @@ struct i2c_config { }; struct i2c_config i2c_setup(uint32_t bus, uint32_t rate, uint8_t addr); -void i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); -void i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg , uint8_t read_len, uint8_t *read); #endif // gpio.h diff --git a/src/avr/i2c.c b/src/avr/i2c.c index 658a30a12187..e8febfba973d 100644 --- a/src/avr/i2c.c +++ b/src/avr/i2c.c @@ -11,6 +11,7 @@ #include "gpio.h" // i2c_setup #include "internal.h" // GPIO #include "sched.h" // sched_shutdown +#include "i2ccmds.h" // I2C_BUS_SUCCESS DECL_ENUMERATION("i2c_bus", "twi", 0); @@ -94,7 +95,7 @@ i2c_stop(uint32_t timeout) TWCR = (1<IPR); i++) + NVIC->IPR[i] = 0; +#else for (i = 0; i < ARRAY_SIZE(NVIC->IP); i++) NVIC->IP[i] = 0; +#endif // Disable SysTick interrupt SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk; @@ -70,7 +75,7 @@ reset_handler_stage_two(void) SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk | SCB_ICSR_PENDSTCLR_Msk; // Reset all system interrupt priorities -#if __CORTEX_M >= 7 +#if __CORTEX_M == 7 || __CORTEX_M == 33 for (i = 0; i < ARRAY_SIZE(SCB->SHPR); i++) SCB->SHPR[i] = 0; #else diff --git a/src/generic/armcm_irq.c b/src/generic/armcm_irq.c index c4909222cea7..329670a13026 100644 --- a/src/generic/armcm_irq.c +++ b/src/generic/armcm_irq.c @@ -38,7 +38,7 @@ irq_restore(irqstatus_t flag) void irq_wait(void) { - if (__CORTEX_M >= 7) + if (__CORTEX_M == 7) // Cortex-m7 may disable cpu counter on wfi, so use nop asm volatile("cpsie i\n nop\n cpsid i\n" ::: "memory"); else diff --git a/src/generic/armcm_reset.c b/src/generic/armcm_reset.c index fb9bf0b13a7d..2b41107184af 100644 --- a/src/generic/armcm_reset.c +++ b/src/generic/armcm_reset.c @@ -29,7 +29,7 @@ canboot_reset(uint64_t req_signature) return; irq_disable(); *req_sig = req_signature; -#if __CORTEX_M >= 7 +#if __CORTEX_M == 7 SCB_CleanDCache_by_Addr((void*)req_sig, sizeof(*req_sig)); #endif NVIC_SystemReset(); diff --git a/src/generic/armcm_timer.c b/src/generic/armcm_timer.c index ef38680a9e70..e77081804d65 100644 --- a/src/generic/armcm_timer.c +++ b/src/generic/armcm_timer.c @@ -137,7 +137,7 @@ timer_dispatch_many(void) // Check if there are too many repeat timers if (diff < (int32_t)(-timer_from_us(1000))) try_shutdown("Rescheduled timer in the past"); - if (sched_tasks_busy()) { + if (sched_check_set_tasks_busy()) { timer_repeat_until = now + TIMER_REPEAT_TICKS; return TIMER_DEFER_REPEAT_TICKS; } diff --git a/src/generic/gpio.h b/src/generic/gpio.h index cb104d00ddb3..9f86952d31a1 100644 --- a/src/generic/gpio.h +++ b/src/generic/gpio.h @@ -41,4 +41,8 @@ void spi_prepare(struct spi_config config); void spi_transfer(struct spi_config config, uint8_t receive_data , uint8_t len, uint8_t *data); +struct i2c_config { + uint32_t cfg; +}; + #endif // gpio.h diff --git a/src/generic/timer_irq.c b/src/generic/timer_irq.c index 40e9336b20c2..7c2e871bdf36 100644 --- a/src/generic/timer_irq.c +++ b/src/generic/timer_irq.c @@ -55,7 +55,7 @@ timer_dispatch_many(void) // Check if there are too many repeat timers if (diff < (int32_t)(-timer_from_us(1000))) try_shutdown("Rescheduled timer in the past"); - if (sched_tasks_busy()) { + if (sched_check_set_tasks_busy()) { timer_repeat_until = now + TIMER_REPEAT_TICKS; return now + TIMER_DEFER_REPEAT_TICKS; } diff --git a/src/hc32f460/gpio.h b/src/hc32f460/gpio.h index 5e88a234c8f1..3ac74d9ac983 100644 --- a/src/hc32f460/gpio.h +++ b/src/hc32f460/gpio.h @@ -55,8 +55,8 @@ struct i2c_config { }; struct i2c_config i2c_setup(uint32_t bus, uint32_t rate, uint8_t addr); -void i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); -void i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg - , uint8_t read_len, uint8_t *read); +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg + , uint8_t read_len, uint8_t *read); #endif // gpio.h diff --git a/src/i2c_software.c b/src/i2c_software.c index ed0efe536556..13acb7661cd6 100644 --- a/src/i2c_software.c +++ b/src/i2c_software.c @@ -11,7 +11,6 @@ #include "board/misc.h" // timer_read_time #include "basecmd.h" // oid_alloc #include "command.h" // DECL_COMMAND -#include "sched.h" // sched_shutdown #include "i2ccmds.h" // i2cdev_set_software_bus struct i2c_software { @@ -87,7 +86,7 @@ i2c_software_read_ack(struct i2c_software *is) return nack; } -static void +static int i2c_software_send_byte(struct i2c_software *is, uint8_t b) { for (uint_fast8_t i = 0; i < 8; i++) { @@ -104,8 +103,10 @@ i2c_software_send_byte(struct i2c_software *is, uint8_t b) } if (i2c_software_read_ack(is)) { - shutdown("soft_i2c NACK"); + return I2C_BUS_NACK; } + + return I2C_BUS_SUCCESS; } static uint8_t @@ -126,9 +127,10 @@ i2c_software_read_byte(struct i2c_software *is, uint8_t remaining) return b; } -static void +static int i2c_software_start(struct i2c_software *is, uint8_t addr) { + int ret; i2c_delay(is->ticks); gpio_in_reset(is->sda_in, 1); gpio_in_reset(is->scl_in, 1); @@ -137,7 +139,10 @@ i2c_software_start(struct i2c_software *is, uint8_t addr) i2c_delay(is->ticks); gpio_out_reset(is->scl_out, 0); - i2c_software_send_byte(is, addr); + ret = i2c_software_send_byte(is, addr); + if (ret == I2C_BUS_NACK) + return I2C_BUS_START_NACK; + return ret; } static void @@ -150,32 +155,52 @@ i2c_software_stop(struct i2c_software *is) gpio_in_reset(is->sda_in, 1); } -void +int i2c_software_write(struct i2c_software *is, uint8_t write_len, uint8_t *write) { - i2c_software_start(is, is->addr); - while (write_len--) - i2c_software_send_byte(is, *write++); + int ret = i2c_software_start(is, is->addr); + if (ret != I2C_BUS_SUCCESS) + goto out; + + while (write_len--) { + ret = i2c_software_send_byte(is, *write++); + if (ret != I2C_BUS_SUCCESS) + break; + } + +out: i2c_software_stop(is); + return ret; } -void +int i2c_software_read(struct i2c_software *is, uint8_t reg_len, uint8_t *reg , uint8_t read_len, uint8_t *read) { - uint8_t addr = is->addr | 0x01; - + int ret; if (reg_len) { // write the register - i2c_software_start(is, is->addr); - while(reg_len--) - i2c_software_send_byte(is, *reg++); + ret = i2c_software_start(is, is->addr); + if (ret != I2C_BUS_SUCCESS) + goto out; + while(reg_len--) { + ret = i2c_software_send_byte(is, *reg++); + if (ret != I2C_BUS_SUCCESS) + goto out; + } + } // start/re-start and read data - i2c_software_start(is, addr); + ret = i2c_software_start(is, is->addr | 0x01); + if (ret != I2C_BUS_SUCCESS) { + ret = I2C_BUS_START_READ_NACK; + goto out; + } while(read_len--) { *read = i2c_software_read_byte(is, read_len); read++; } +out: i2c_software_stop(is); + return ret; } diff --git a/src/i2c_software.h b/src/i2c_software.h index 9bd54f29af90..843ab461a87b 100644 --- a/src/i2c_software.h +++ b/src/i2c_software.h @@ -4,10 +4,10 @@ #include // uint8_t struct i2c_software *i2c_software_oid_lookup(uint8_t oid); -void i2c_software_write(struct i2c_software *sw_i2c - , uint8_t write_len, uint8_t *write); -void i2c_software_read(struct i2c_software *sw_i2c - , uint8_t reg_len, uint8_t *reg - , uint8_t read_len, uint8_t *read); +int i2c_software_write(struct i2c_software *sw_i2c + , uint8_t write_len, uint8_t *write); +int i2c_software_read(struct i2c_software *sw_i2c + , uint8_t reg_len, uint8_t *reg + , uint8_t read_len, uint8_t *read); #endif // i2c_software.h diff --git a/src/i2ccmds.c b/src/i2ccmds.c index 377a9537deaa..c51772f1da09 100644 --- a/src/i2ccmds.c +++ b/src/i2ccmds.c @@ -36,7 +36,7 @@ command_i2c_set_bus(uint32_t *args) { uint8_t addr = args[3] & 0x7f; struct i2cdev_s *i2c = i2cdev_oid_lookup(args[0]); - i2c->i2c_config = i2c_setup(args[1], args[2], addr); + i2c->i2c_hw = i2c_setup(args[1], args[2], addr); i2c->flags |= IF_HARDWARE; } DECL_COMMAND(command_i2c_set_bus, @@ -45,72 +45,64 @@ DECL_COMMAND(command_i2c_set_bus, void i2cdev_set_software_bus(struct i2cdev_s *i2c, struct i2c_software *is) { - i2c->i2c_software = is; + i2c->i2c_sw = is; i2c->flags |= IF_SOFTWARE; } -void -command_i2c_write(uint32_t *args) +void i2c_shutdown_on_err(int ret) +{ + switch (ret) { + case I2C_BUS_NACK: + shutdown("I2C NACK"); + case I2C_BUS_START_NACK: + shutdown("I2C START NACK"); + case I2C_BUS_START_READ_NACK: + shutdown("I2C START READ NACK"); + case I2C_BUS_TIMEOUT: + shutdown("I2C Timeout"); + } +} + +int i2c_dev_write(struct i2cdev_s *i2c, uint8_t write_len, uint8_t *data) { - uint8_t oid = args[0]; - struct i2cdev_s *i2c = oid_lookup(oid, command_config_i2c); - uint8_t data_len = args[1]; - uint8_t *data = command_decode_ptr(args[2]); uint_fast8_t flags = i2c->flags; if (CONFIG_WANT_SOFTWARE_I2C && flags & IF_SOFTWARE) - i2c_software_write(i2c->i2c_software, data_len, data); + return i2c_software_write(i2c->i2c_sw, write_len, data); else - i2c_write(i2c->i2c_config, data_len, data); + return i2c_write(i2c->i2c_hw, write_len, data); } -DECL_COMMAND(command_i2c_write, "i2c_write oid=%c data=%*s"); -void -command_i2c_read(uint32_t * args) +void command_i2c_write(uint32_t *args) { uint8_t oid = args[0]; struct i2cdev_s *i2c = oid_lookup(oid, command_config_i2c); - uint8_t reg_len = args[1]; - uint8_t *reg = command_decode_ptr(args[2]); - uint8_t data_len = args[3]; - uint8_t data[data_len]; + uint8_t data_len = args[1]; + uint8_t *data = command_decode_ptr(args[2]); + int ret = i2c_dev_write(i2c, data_len, data); + i2c_shutdown_on_err(ret); +} +DECL_COMMAND(command_i2c_write, "i2c_write oid=%c data=%*s"); + +int i2c_dev_read(struct i2cdev_s *i2c, uint8_t reg_len, uint8_t *reg + , uint8_t read_len, uint8_t *read) +{ uint_fast8_t flags = i2c->flags; if (CONFIG_WANT_SOFTWARE_I2C && flags & IF_SOFTWARE) - i2c_software_read(i2c->i2c_software, reg_len, reg, data_len, data); + return i2c_software_read(i2c->i2c_sw, reg_len, reg, read_len, read); else - i2c_read(i2c->i2c_config, reg_len, reg, data_len, data); - sendf("i2c_read_response oid=%c response=%*s", oid, data_len, data); + return i2c_read(i2c->i2c_hw, reg_len, reg, read_len, read); } -DECL_COMMAND(command_i2c_read, "i2c_read oid=%c reg=%*s read_len=%u"); -void -command_i2c_modify_bits(uint32_t *args) +void command_i2c_read(uint32_t *args) { uint8_t oid = args[0]; struct i2cdev_s *i2c = oid_lookup(oid, command_config_i2c); uint8_t reg_len = args[1]; uint8_t *reg = command_decode_ptr(args[2]); - uint32_t clear_set_len = args[3]; - if (clear_set_len % 2 != 0) - shutdown("i2c_modify_bits: Odd number of bits!"); - uint8_t data_len = clear_set_len/2; - uint8_t *clear_set = command_decode_ptr(args[4]); - uint8_t receive_data[reg_len + data_len]; - uint_fast8_t flags = i2c->flags; - memcpy(receive_data, reg, reg_len); - if (CONFIG_WANT_SOFTWARE_I2C && flags & IF_SOFTWARE) - i2c_software_read( - i2c->i2c_software, reg_len, reg, data_len, receive_data + reg_len); - else - i2c_read( - i2c->i2c_config, reg_len, reg, data_len, receive_data + reg_len); - for (int i = 0; i < data_len; i++) { - receive_data[reg_len + i] &= ~clear_set[i]; - receive_data[reg_len + i] |= clear_set[data_len + i]; - } - if (CONFIG_WANT_SOFTWARE_I2C && flags & IF_SOFTWARE) - i2c_software_write(i2c->i2c_software, reg_len + data_len, receive_data); - else - i2c_write(i2c->i2c_config, reg_len + data_len, receive_data); + uint8_t data_len = args[3]; + uint8_t data[data_len]; + int ret = i2c_dev_read(i2c, reg_len, reg, data_len, data); + i2c_shutdown_on_err(ret); + sendf("i2c_read_response oid=%c response=%*s", oid, data_len, data); } -DECL_COMMAND(command_i2c_modify_bits, - "i2c_modify_bits oid=%c reg=%*s clear_set_bits=%*s"); +DECL_COMMAND(command_i2c_read, "i2c_read oid=%c reg=%*s read_len=%u"); diff --git a/src/i2ccmds.h b/src/i2ccmds.h index 9ce54aa060b2..55c97b6b5af1 100644 --- a/src/i2ccmds.h +++ b/src/i2ccmds.h @@ -4,13 +4,28 @@ #include #include "board/gpio.h" // i2c_config +// I2C ERROR Codes +enum { + I2C_BUS_SUCCESS, + I2C_BUS_NACK, + I2C_BUS_TIMEOUT, + I2C_BUS_START_NACK, + I2C_BUS_START_READ_NACK, +}; + struct i2cdev_s { - struct i2c_config i2c_config; - struct i2c_software *i2c_software; + union { + struct i2c_config i2c_hw; + struct i2c_software *i2c_sw; + }; uint8_t flags; }; struct i2cdev_s *i2cdev_oid_lookup(uint8_t oid); void i2cdev_set_software_bus(struct i2cdev_s *i2c, struct i2c_software *is); +int i2c_dev_read(struct i2cdev_s *i2c, uint8_t reg_len, uint8_t *reg + , uint8_t read_len, uint8_t *read); +int i2c_dev_write(struct i2cdev_s *i2c, uint8_t write_len, uint8_t *data); +void i2c_shutdown_on_err(int ret); #endif diff --git a/src/linux/gpio.h b/src/linux/gpio.h index df9de752566e..d72007c2ce3b 100644 --- a/src/linux/gpio.h +++ b/src/linux/gpio.h @@ -49,8 +49,8 @@ struct i2c_config { }; struct i2c_config i2c_setup(uint32_t bus, uint32_t rate, uint8_t addr); -void i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); -void i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg , uint8_t read_len, uint8_t *read); #endif // gpio.h diff --git a/src/linux/i2c.c b/src/linux/i2c.c index b328dc56eaa6..a728752aa7c2 100644 --- a/src/linux/i2c.c +++ b/src/linux/i2c.c @@ -13,6 +13,7 @@ #include "command.h" // shutdown #include "internal.h" // report_errno #include "sched.h" // sched_shutdown +#include "i2ccmds.h" // I2C_BUS_SUCCESS DECL_ENUMERATION_RANGE("i2c_bus", "i2c.0", 0, 15); @@ -84,18 +85,28 @@ i2c_setup(uint32_t bus, uint32_t rate, uint8_t addr) return (struct i2c_config){.fd=fd, .addr=addr}; } -void +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *data) { - int ret = write(config.fd, data, write_len); - if (ret != write_len) { - if (ret < 0) - report_errno("write value i2c", ret); - try_shutdown("Unable write i2c device"); + struct i2c_rdwr_ioctl_data i2c_data; + struct i2c_msg msgs[1]; + msgs[0].addr = config.addr; + msgs[0].flags = 0x0; + msgs[0].len = write_len; + msgs[0].buf = data; + i2c_data.nmsgs = 1; + i2c_data.msgs = &msgs[0]; + + int ret = ioctl(config.fd, I2C_RDWR, &i2c_data); + + if (ret < 0) { + return I2C_BUS_NACK; } + + return I2C_BUS_SUCCESS; } -void +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg , uint8_t read_len, uint8_t *data) { @@ -121,7 +132,9 @@ i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg int ret = ioctl(config.fd, I2C_RDWR, &i2c_data); - if(ret < 0) { - try_shutdown("Unable to read i2c device"); + if (ret < 0) { + return I2C_BUS_NACK; } + + return I2C_BUS_SUCCESS; } diff --git a/src/linux/timer.c b/src/linux/timer.c index 21be01312460..8eda62a54ddc 100644 --- a/src/linux/timer.c +++ b/src/linux/timer.c @@ -152,7 +152,7 @@ timer_dispatch(void) // Check if there are too many repeat timers if (diff < (int32_t)(-timer_from_us(100000))) try_shutdown("Rescheduled timer in the past"); - if (sched_tasks_busy()) + if (sched_check_set_tasks_busy()) return; repeat_count = TIMER_IDLE_REPEAT_COUNT; } diff --git a/src/lpc176x/Kconfig b/src/lpc176x/Kconfig index 390a081f034a..ee7580301020 100644 --- a/src/lpc176x/Kconfig +++ b/src/lpc176x/Kconfig @@ -65,7 +65,7 @@ config STACK_SIZE choice prompt "Bootloader offset" config LPC_FLASH_START_4000 - bool "16KiB bootloader (Smoothieware bootloader)" + bool "16KiB bootloader" config LPC_FLASH_START_0000 bool "No bootloader" endchoice diff --git a/src/lpc176x/gpio.h b/src/lpc176x/gpio.h index e03afbb44910..c1507c64c265 100644 --- a/src/lpc176x/gpio.h +++ b/src/lpc176x/gpio.h @@ -51,8 +51,8 @@ struct i2c_config { }; struct i2c_config i2c_setup(uint32_t bus, uint32_t rate, uint8_t addr); -void i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); -void i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg - , uint8_t read_len, uint8_t *read); +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg + , uint8_t read_len, uint8_t *read); #endif // gpio.h diff --git a/src/lpc176x/i2c.c b/src/lpc176x/i2c.c index 7ed631af1f15..519dd504ca5a 100644 --- a/src/lpc176x/i2c.c +++ b/src/lpc176x/i2c.c @@ -9,6 +9,7 @@ #include "gpio.h" // i2c_setup #include "internal.h" // gpio_peripheral #include "sched.h" // sched_shutdown +#include "i2ccmds.h" // I2C_BUS_SUCCESS struct i2c_info { LPC_I2C_TypeDef *i2c; @@ -122,7 +123,7 @@ i2c_stop(LPC_I2C_TypeDef *i2c, uint32_t timeout) i2c_wait(i2c, IF_STOP, timeout); } -void +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write) { LPC_I2C_TypeDef *i2c = config.i2c; @@ -133,9 +134,11 @@ i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write) while (write_len--) i2c_send_byte(i2c, *write++, timeout); i2c_stop(i2c, timeout); + + return I2C_BUS_SUCCESS; } -void +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg , uint8_t read_len, uint8_t *read) { @@ -159,4 +162,6 @@ i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg read++; } i2c_stop(i2c, timeout); + + return I2C_BUS_SUCCESS; } diff --git a/src/rp2040/Kconfig b/src/rp2040/Kconfig index ec8a1af3205d..5ec7c918b96d 100644 --- a/src/rp2040/Kconfig +++ b/src/rp2040/Kconfig @@ -1,8 +1,8 @@ -# Kconfig settings for RP2040 processors +# Kconfig settings for RPxxxx processors -if MACH_RP2040 +if MACH_RPXXXX -config RP2040_SELECT +config RPXXXX_SELECT bool default y select HAVE_GPIO @@ -19,13 +19,27 @@ config BOARD_DIRECTORY string default "rp2040" +###################################################################### +# Chip selection +###################################################################### + +choice + prompt "Processor model" + config MACH_RP2040 + bool "rp2040" + config MACH_RP2350 + bool "rp2350" +endchoice + config MCU string - default "rp2040" + default "rp2040" if MACH_RP2040 + default "rp2350" if MACH_RP2350 config CLOCK_FREQ int - default 12000000 + default 12000000 if MACH_RP2040 + default 150000000 if MACH_RP2350 config FLASH_SIZE hex @@ -33,7 +47,8 @@ config FLASH_SIZE config FLASH_BOOT_ADDRESS hex - default 0x10000100 # Stage2 binary starts at 0x10000000 + default 0x10000100 if MACH_RP2040 # Stage2 binary starts at 0x10000000 + default 0x10000000 if MACH_RP2350 config RAM_START hex @@ -41,7 +56,8 @@ config RAM_START config RAM_SIZE hex - default 0x42000 + default 0x42000 if MACH_RP2040 + default 0x82000 if MACH_RP2350 config STACK_SIZE int @@ -54,22 +70,27 @@ config STACK_SIZE config RP2040_HAVE_STAGE2 bool -config RP2040_HAVE_BOOTLOADER +config RPXXXX_HAVE_BOOTLOADER bool - default y if !RP2040_HAVE_STAGE2 choice prompt "Bootloader offset" - config RP2040_FLASH_START_0100 + config RPXXXX_FLASH_START_0000 + bool "No bootloader" + depends on MACH_RP2350 + config RPXXXX_FLASH_START_0100 bool "No bootloader" + depends on MACH_RP2040 select RP2040_HAVE_STAGE2 - config RP2040_FLASH_START_4000 + config RPXXXX_FLASH_START_4000 bool "16KiB bootloader" + select RPXXXX_HAVE_BOOTLOADER endchoice config FLASH_APPLICATION_ADDRESS hex - default 0x10004000 if RP2040_FLASH_START_4000 - default 0x10000100 + default 0x10004000 if RPXXXX_FLASH_START_4000 + default 0x10000100 if RPXXXX_FLASH_START_0100 + default 0x10000000 if RPXXXX_FLASH_START_0000 choice prompt "Flash chip" if LOW_LEVEL_OPTIONS && RP2040_HAVE_STAGE2 @@ -95,48 +116,48 @@ config RP2040_STAGE2_CLKDIV ###################################################################### choice - prompt "Communication Interface" - config RP2040_USB - bool "USBSERIAL" - select USBSERIAL - config RP2040_SERIAL_UART0_PINS_0_1 - bool "UART0 on GPIO0/GPIO1" - select SERIAL - config RP2040_SERIAL_UART0_PINS_12_13 - bool "UART0 on GPIO12/GPIO13" if LOW_LEVEL_OPTIONS - select SERIAL - config RP2040_SERIAL_UART0_PINS_16_17 - bool "UART0 on GPIO16/GPIO17" if LOW_LEVEL_OPTIONS - select SERIAL - config RP2040_SERIAL_UART0_PINS_28_29 - bool "UART0 on GPIO28/GPIO29" if LOW_LEVEL_OPTIONS - select SERIAL - config RP2040_SERIAL_UART1_PINS_4_5 - bool "UART1 on GPIO4/GPIO5" if LOW_LEVEL_OPTIONS - select SERIAL - config RP2040_SERIAL_UART1_PINS_8_9 - bool "UART1 on GPIO8/GPIO9" if LOW_LEVEL_OPTIONS - select SERIAL - config RP2040_SERIAL_UART1_PINS_20_21 - bool "UART1 on GPIO20/GPIO21" if LOW_LEVEL_OPTIONS - select SERIAL - config RP2040_SERIAL_UART1_PINS_24_25 - bool "UART1 on GPIO24/GPIO25" if LOW_LEVEL_OPTIONS - select SERIAL - config RP2040_CANBUS - bool "CAN bus" - select CANSERIAL - config RP2040_USBCANBUS - bool "USB to CAN bus bridge" - select USBCANBUS + prompt "Communication Interface" + config RPXXXX_USB + bool "USBSERIAL" + select USBSERIAL + config RPXXXX_SERIAL_UART0_PINS_0_1 + bool "UART0 on GPIO0/GPIO1" + select SERIAL + config RPXXXX_SERIAL_UART0_PINS_12_13 + bool "UART0 on GPIO12/GPIO13" if LOW_LEVEL_OPTIONS + select SERIAL + config RPXXXX_SERIAL_UART0_PINS_16_17 + bool "UART0 on GPIO16/GPIO17" if LOW_LEVEL_OPTIONS + select SERIAL + config RPXXXX_SERIAL_UART0_PINS_28_29 + bool "UART0 on GPIO28/GPIO29" if LOW_LEVEL_OPTIONS + select SERIAL + config RPXXXX_SERIAL_UART1_PINS_4_5 + bool "UART1 on GPIO4/GPIO5" if LOW_LEVEL_OPTIONS + select SERIAL + config RPXXXX_SERIAL_UART1_PINS_8_9 + bool "UART1 on GPIO8/GPIO9" if LOW_LEVEL_OPTIONS + select SERIAL + config RPXXXX_SERIAL_UART1_PINS_20_21 + bool "UART1 on GPIO20/GPIO21" if LOW_LEVEL_OPTIONS + select SERIAL + config RPXXXX_SERIAL_UART1_PINS_24_25 + bool "UART1 on GPIO24/GPIO25" if LOW_LEVEL_OPTIONS + select SERIAL + config RPXXXX_CANBUS + bool "CAN bus" + select CANSERIAL + config RPXXXX_USBCANBUS + bool "USB to CAN bus bridge" + select USBCANBUS endchoice -config RP2040_CANBUS_GPIO_RX +config RPXXXX_CANBUS_GPIO_RX int "CAN RX gpio number" if CANBUS default 4 range 0 29 -config RP2040_CANBUS_GPIO_TX +config RPXXXX_CANBUS_GPIO_TX int "CAN TX gpio number" if CANBUS default 5 range 0 29 diff --git a/src/rp2040/Makefile b/src/rp2040/Makefile index b82503a39669..f7c38dabe49c 100644 --- a/src/rp2040/Makefile +++ b/src/rp2040/Makefile @@ -1,20 +1,26 @@ -# Additional RP2040 build rules +# Additional RPxxxx Raspberry Pi MCU build rules # Setup the toolchain CROSS_PREFIX=arm-none-eabi- -dirs-y += src/rp2040 src/generic lib/rp2040/elf2uf2 lib/fast-hash lib/can2040 +dirs-y += src/rp2040 src/generic lib/elf2uf2 lib/fast-hash lib/can2040 -CFLAGS += -mcpu=cortex-m0plus -mthumb -Ilib/cmsis-core -CFLAGS += -Ilib/rp2040 -Ilib/rp2040/cmsis_include -Ilib/fast-hash -Ilib/can2040 +MCU := $(shell echo $(CONFIG_MCU)) +MCU_UPPER := $(shell echo $(CONFIG_MCU) | tr a-z A-Z | tr X x) + +CFLAGS-$(CONFIG_MACH_RP2040) += -mcpu=cortex-m0plus +CFLAGS-$(CONFIG_MACH_RP2350) += -mcpu=cortex-m33 +CFLAGS += $(CFLAGS-y) -DPICO_$(MCU_UPPER) -mthumb -Ilib/cmsis-core +CFLAGS += -Ilib/pico-sdk/$(MCU) -Ilib/pico-sdk +CFLAGS += -Ilib/pico-sdk/$(MCU)/cmsis_include -Ilib/fast-hash -Ilib/can2040 # Add source files -src-y += rp2040/main.c rp2040/watchdog.c rp2040/gpio.c -src-y += rp2040/adc.c rp2040/timer.c rp2040/bootrom.c -src-y += generic/armcm_boot.c generic/armcm_irq.c generic/armcm_reset.c -src-y += generic/timer_irq.c generic/crc16_ccitt.c -src-$(CONFIG_USBSERIAL) += rp2040/usbserial.c generic/usb_cdc.c -src-$(CONFIG_USBSERIAL) += rp2040/chipid.c +src-y += rp2040/main.c rp2040/watchdog.c rp2040/gpio.c rp2040/adc.c +src-y += generic/armcm_boot.c generic/armcm_irq.c +src-y += generic/armcm_reset.c generic/crc16_ccitt.c +src-$(CONFIG_MACH_RP2040) += rp2040/timer.c generic/timer_irq.c rp2040/bootrom.c +src-$(CONFIG_MACH_RP2350) += generic/armcm_timer.c rp2040/rp2350_bootrom.c +src-$(CONFIG_USBSERIAL) += rp2040/usbserial.c generic/usb_cdc.c rp2040/chipid.c src-$(CONFIG_SERIAL) += rp2040/serial.c generic/serial_irq.c src-$(CONFIG_CANSERIAL) += rp2040/can.c rp2040/chipid.c ../lib/can2040/can2040.c src-$(CONFIG_CANSERIAL) += generic/canserial.c generic/canbus.c @@ -28,24 +34,24 @@ src-$(CONFIG_HAVE_GPIO_I2C) += rp2040/i2c.c # rp2040 stage2 building STAGE2_FILE := $(shell echo $(CONFIG_RP2040_STAGE2_FILE)) -$(OUT)stage2.o: lib/rp2040/boot_stage2/$(STAGE2_FILE) $(OUT)autoconf.h +$(OUT)stage2.o: lib/pico-sdk/$(MCU)/boot_stage2/$(STAGE2_FILE) $(OUT)autoconf.h @echo " Building rp2040 stage2 $@" - $(Q)$(CC) $(CFLAGS) -Ilib/rp2040/boot_stage2 -Ilib/rp2040/boot_stage2/asminclude -DPICO_FLASH_SPI_CLKDIV=$(CONFIG_RP2040_STAGE2_CLKDIV) -c $< -o $(OUT)stage2raw1.o - $(Q)$(LD) $(OUT)stage2raw1.o --script=lib/rp2040/boot_stage2/boot_stage2.ld -o $(OUT)stage2raw.o + $(Q)$(CC) $(CFLAGS) -Ilib/pico-sdk/$(MCU)/boot_stage2 -Ilib/pico-sdk/$(MCU)/boot_stage2/asminclude -DPICO_FLASH_SPI_CLKDIV=$(CONFIG_RP2040_STAGE2_CLKDIV) -c $< -o $(OUT)stage2raw1.o + $(Q)$(LD) $(OUT)stage2raw1.o --script=lib/pico-sdk/$(MCU)/boot_stage2/boot_stage2.ld -o $(OUT)stage2raw.o $(Q)$(OBJCOPY) -O binary $(OUT)stage2raw.o $(OUT)stage2raw.bin - $(Q)lib/rp2040/boot_stage2/pad_checksum -s 0xffffffff $(OUT)stage2raw.bin $(OUT)stage2.S + $(Q)lib/pico-sdk/$(MCU)/boot_stage2/pad_checksum -s 0xffffffff $(OUT)stage2raw.bin $(OUT)stage2.S $(Q)$(CC) $(CFLAGS) -c $(OUT)stage2.S -o $(OUT)stage2.o # Binary output file rules when using stage2 -$(OUT)lib/rp2040/elf2uf2/elf2uf2: lib/rp2040/elf2uf2/main.cpp +$(OUT)lib/elf2uf2/elf2uf2: lib/elf2uf2/main.cpp @echo " Building $@" - $(Q)g++ -g -O -Ilib/rp2040 $< -o $@ + $(Q)g++ -g -O -Ilib/pico-sdk $< -o $@ -$(OUT)klipper.uf2: $(OUT)klipper.elf $(OUT)lib/rp2040/elf2uf2/elf2uf2 +$(OUT)klipper.uf2: $(OUT)klipper.elf $(OUT)lib/elf2uf2/elf2uf2 @echo " Creating uf2 file $@" - $(Q)$(OUT)lib/rp2040/elf2uf2/elf2uf2 $< $@ + $(Q)$(OUT)lib/elf2uf2/elf2uf2 $< $@ -rptarget-$(CONFIG_RP2040_HAVE_STAGE2) := $(OUT)klipper.uf2 +rptarget-y := $(OUT)klipper.uf2 stage2-$(CONFIG_RP2040_HAVE_STAGE2) := $(OUT)stage2.o # rp2040 building when using a bootloader @@ -53,14 +59,14 @@ $(OUT)klipper.bin: $(OUT)klipper.elf @echo " Creating bin file $@" $(Q)$(OBJCOPY) -O binary $< $@ -rptarget-$(CONFIG_RP2040_HAVE_BOOTLOADER) := $(OUT)klipper.bin +rptarget-$(CONFIG_RPXXXX_HAVE_BOOTLOADER) := $(OUT)klipper.bin # Set klipper.elf linker rules target-y += $(rptarget-y) CFLAGS_klipper.elf += -nostdlib -lgcc -lc_nano -CFLAGS_klipper.elf += -T $(OUT)src/rp2040/rp2040_link.ld +CFLAGS_klipper.elf += -T $(OUT)src/rp2040/rpxxxx_link.ld OBJS_klipper.elf += $(stage2-y) -$(OUT)klipper.elf: $(stage2-y) $(OUT)src/rp2040/rp2040_link.ld +$(OUT)klipper.elf: $(stage2-y) $(OUT)src/rp2040/rpxxxx_link.ld # Flash rules lib/rp2040_flash/rp2040_flash: diff --git a/src/rp2040/bootrom.c b/src/rp2040/bootrom.c index 6e6c46e9d34a..e54bdcc2ca31 100644 --- a/src/rp2040/bootrom.c +++ b/src/rp2040/bootrom.c @@ -6,7 +6,10 @@ #include // uint16_t, uint32_t, uintptr_t #include // memcpy +#include "board/irq.h" // irq_disable, irq_enable #include "compiler.h" // noinline, __section +#include "hardware/structs/ioqspi.h" // ioqspi_hw +#include "hardware/structs/ssi.h" // ssi_hw #include "internal.h" // _ramfunc #define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8)) @@ -35,7 +38,7 @@ rom_func_lookup(uint32_t code) return fn(table, code); } -void _ramfunc +static void _ramfunc reset_to_usb_boot(uint32_t gpio_activity_pin_mask , uint32_t disable_interface_mask) { @@ -43,23 +46,129 @@ reset_to_usb_boot(uint32_t gpio_activity_pin_mask fn(gpio_activity_pin_mask, disable_interface_mask); } -void _ramfunc +static void _ramfunc connect_internal_flash(void) { void (*fn)(void) = rom_func_lookup(ROM_TABLE_CODE('I', 'F')); fn(); } -void _ramfunc +static void _ramfunc flash_exit_xip(void) { void (*fn)(void) = rom_func_lookup(ROM_TABLE_CODE('E', 'X')); fn(); } -void _ramfunc +static void _ramfunc flash_flush_cache(void) { void (*fn)(void) = rom_func_lookup(ROM_TABLE_CODE('F', 'C')); fn(); } + + +/**************************************************************** + * Reboot to USB rom bootloader + ****************************************************************/ + +void +bootrom_reboot_usb_bootloader(void) +{ + reset_to_usb_boot(0, 0); +} + + +/**************************************************************** + * Unique id reading + ****************************************************************/ + +// Functions for reading out the flash chip ID. Adapted from the official +// Pi SDK. + +static void _ramfunc +flash_cs_force(int high) +{ + uint32_t field_val = high ? + IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH : + IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW; + hw_write_masked(&ioqspi_hw->io[1].ctrl, + field_val << IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB, + IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS + ); +} + +// To re-enable XIP we need to call flash_enter_xip. It's available in the +// bootrom, but that version is a generic one that works for most devices and +// the tradeoff for that is enabling a low performance mode. +// Instead we copy out the boot2 XIP enabling stage, and save it in RAM +// so we can call it later on. + +#define BOOT2_SIZE 0x100 + +static uint8_t boot2_copy[BOOT2_SIZE] __aligned(16); + +static void +flash_enter_xip_prepare(void) +{ + void * volatile target = (void *)XIP_BASE; // Avoids warning + memcpy(boot2_copy, target, BOOT2_SIZE); + barrier(); +} + +static void _ramfunc +flash_enter_xip_perform(void) +{ + ((void (*)(void))boot2_copy+1)(); +} + +#define FLASH_RUID_CMD 0x4B +#define FLASH_RUID_DUMMY_BYTES 4 +#define FLASH_RUID_DATA_BYTES 8 +#define FLASH_RUID_TOTAL_BYTES (1+FLASH_RUID_DUMMY_BYTES+FLASH_RUID_DATA_BYTES) + +void _ramfunc +bootrom_read_unique_id(uint8_t *out, uint32_t maxlen) +{ + uint8_t txbuf[FLASH_RUID_TOTAL_BYTES] = {0}; + uint8_t rxbuf[FLASH_RUID_TOTAL_BYTES] = {0}; + + uint8_t *txptr = txbuf; + uint8_t *rxptr = rxbuf; + + int tx_remaining = FLASH_RUID_TOTAL_BYTES; + int rx_remaining = FLASH_RUID_TOTAL_BYTES; + + txbuf[0] = FLASH_RUID_CMD; + + // Set up flash so we can work with it without XIP getting in the way + flash_enter_xip_prepare(); + irq_disable(); + barrier(); + connect_internal_flash(); + flash_exit_xip(); + flash_cs_force(0); + + while (tx_remaining || rx_remaining) { + uint32_t flags = ssi_hw->sr; + int can_put = !!(flags & SSI_SR_TFNF_BITS); + int can_get = !!(flags & SSI_SR_RFNE_BITS); + if (can_put && tx_remaining) { + ssi_hw->dr0 = *txptr++; + tx_remaining--; + } + if (can_get && rx_remaining) { + *rxptr++ = (uint8_t)ssi_hw->dr0; + --rx_remaining; + } + } + + // Restore XIP + flash_cs_force(1); + flash_flush_cache(); + flash_enter_xip_perform(); + barrier(); + irq_enable(); + + memcpy(out, rxbuf+1+FLASH_RUID_DUMMY_BYTES, FLASH_RUID_DATA_BYTES); +} diff --git a/src/rp2040/can.c b/src/rp2040/can.c index 6cae2a7fb800..1f4c281ece4f 100644 --- a/src/rp2040/can.c +++ b/src/rp2040/can.c @@ -18,8 +18,8 @@ #include "internal.h" // DMA_IRQ_0_IRQn #include "sched.h" // DECL_INIT -#define GPIO_STR_CAN_RX "gpio" __stringify(CONFIG_RP2040_CANBUS_GPIO_RX) -#define GPIO_STR_CAN_TX "gpio" __stringify(CONFIG_RP2040_CANBUS_GPIO_TX) +#define GPIO_STR_CAN_RX "gpio" __stringify(CONFIG_RPXXXX_CANBUS_GPIO_RX) +#define GPIO_STR_CAN_TX "gpio" __stringify(CONFIG_RPXXXX_CANBUS_GPIO_TX) DECL_CONSTANT_STR("RESERVE_PINS_CAN", GPIO_STR_CAN_RX "," GPIO_STR_CAN_TX); static struct can2040 cbus; @@ -73,6 +73,6 @@ can_init(void) // Start canbus uint32_t pclk = get_pclock_frequency(RESETS_RESET_PIO0_RESET); can2040_start(&cbus, pclk, CONFIG_CANBUS_FREQUENCY - , CONFIG_RP2040_CANBUS_GPIO_RX, CONFIG_RP2040_CANBUS_GPIO_TX); + , CONFIG_RPXXXX_CANBUS_GPIO_RX, CONFIG_RPXXXX_CANBUS_GPIO_TX); } DECL_INIT(can_init); diff --git a/src/rp2040/chipid.c b/src/rp2040/chipid.c index 80182f6051f4..75d6e385f7ec 100644 --- a/src/rp2040/chipid.c +++ b/src/rp2040/chipid.c @@ -1,19 +1,15 @@ // Support for extracting the hardware chip id on rp2040 // -// Copyright (C) 2021 Lasse Dalegaard +// Copyright (C) 2019-2024 Kevin O'Connor // // This file may be distributed under the terms of the GNU GPLv3 license. -#include // memcpy #include "autoconf.h" // CONFIG_USB_SERIAL_NUMBER_CHIPID -#include "board/irq.h" // irq_disable, irq_enable #include "board/canserial.h" // canserial_set_uuid #include "generic/usb_cdc.h" // usb_fill_serial #include "generic/usbstd.h" // usb_string_descriptor +#include "internal.h" // bootrom_read_unique_id #include "sched.h" // DECL_INIT -#include "hardware/structs/ioqspi.h" // ioqspi_hw -#include "hardware/structs/ssi.h" // ssi_hw -#include "internal.h" #define CHIP_UID_LEN 8 @@ -28,104 +24,14 @@ usbserial_get_serialid(void) return &cdc_chipid.desc; } -// Functions for reading out the flash chip ID. Adapted from the official -// Pi SDK. - -static void _ramfunc -flash_cs_force(int high) -{ - uint32_t field_val = high ? - IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH : - IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW; - hw_write_masked(&ioqspi_hw->io[1].ctrl, - field_val << IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB, - IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS - ); -} - -// To re-enable XIP we need to call flash_enter_xip. It's available in the -// bootrom, but that version is a generic one that works for most devices and -// the tradeoff for that is enabling a low performance mode. -// Instead we copy out the boot2 XIP enabling stage, and save it in RAM -// so we can call it later on. - -#define BOOT2_SIZE 0x100 - -static uint8_t boot2_copy[BOOT2_SIZE] __aligned(16); - -static void -flash_enter_xip_prepare(void) -{ - void * volatile target = (void *)XIP_BASE; // Avoids warning - memcpy(boot2_copy, target, BOOT2_SIZE); - barrier(); -} - -static void _ramfunc -flash_enter_xip_perform(void) -{ - ((void (*)(void))boot2_copy+1)(); -} - -#define FLASH_RUID_CMD 0x4B -#define FLASH_RUID_DUMMY_BYTES 4 -#define FLASH_RUID_DATA_BYTES 8 -#define FLASH_RUID_TOTAL_BYTES (1+FLASH_RUID_DUMMY_BYTES+FLASH_RUID_DATA_BYTES) - -static void _ramfunc -read_unique_id(uint8_t *out) -{ - uint8_t txbuf[FLASH_RUID_TOTAL_BYTES] = {0}; - uint8_t rxbuf[FLASH_RUID_TOTAL_BYTES] = {0}; - - uint8_t *txptr = txbuf; - uint8_t *rxptr = rxbuf; - - int tx_remaining = FLASH_RUID_TOTAL_BYTES; - int rx_remaining = FLASH_RUID_TOTAL_BYTES; - - txbuf[0] = FLASH_RUID_CMD; - - // Set up flash so we can work with it without XIP getting in the way - flash_enter_xip_prepare(); - irq_disable(); - barrier(); - connect_internal_flash(); - flash_exit_xip(); - flash_cs_force(0); - - while (tx_remaining || rx_remaining) { - uint32_t flags = ssi_hw->sr; - int can_put = !!(flags & SSI_SR_TFNF_BITS); - int can_get = !!(flags & SSI_SR_RFNE_BITS); - if (can_put && tx_remaining) { - ssi_hw->dr0 = *txptr++; - tx_remaining--; - } - if (can_get && rx_remaining) { - *rxptr++ = (uint8_t)ssi_hw->dr0; - --rx_remaining; - } - } - - // Restore XIP - flash_cs_force(1); - flash_flush_cache(); - flash_enter_xip_perform(); - barrier(); - irq_enable(); - - memcpy(out, rxbuf+1+FLASH_RUID_DUMMY_BYTES, FLASH_RUID_DATA_BYTES); -} - void chipid_init(void) { if (!(CONFIG_USB_SERIAL_NUMBER_CHIPID || CONFIG_CANBUS)) return; - uint8_t data[8] = {0}; - read_unique_id(data); + uint8_t data[CHIP_UID_LEN] = {}; + bootrom_read_unique_id(data, sizeof(data)); if (CONFIG_USB_SERIAL_NUMBER_CHIPID) usb_fill_serial(&cdc_chipid.desc, ARRAY_SIZE(cdc_chipid.data), data); diff --git a/src/rp2040/gpio.h b/src/rp2040/gpio.h index ae6083780ce9..0dd393bfed42 100644 --- a/src/rp2040/gpio.h +++ b/src/rp2040/gpio.h @@ -50,8 +50,8 @@ struct i2c_config { }; struct i2c_config i2c_setup(uint32_t bus, uint32_t rate, uint8_t addr); -void i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); -void i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg - , uint8_t read_len, uint8_t *read); +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg + , uint8_t read_len, uint8_t *read); #endif // gpio.h diff --git a/src/rp2040/i2c.c b/src/rp2040/i2c.c index 8a32417badd4..8ec2bd7a6684 100644 --- a/src/rp2040/i2c.c +++ b/src/rp2040/i2c.c @@ -11,6 +11,7 @@ #include "internal.h" // pclock, gpio_peripheral #include "hardware/regs/resets.h" // RESETS_RESET_I2C*_BITS #include "hardware/structs/i2c.h" +#include "i2ccmds.h" // I2C_BUS_SUCCESS struct i2c_info { i2c_hw_t *i2c; @@ -132,8 +133,8 @@ i2c_stop(i2c_hw_t *i2c) i2c->enable = 0; } -static void -i2c_do_write(i2c_hw_t *i2c, uint8_t addr, uint8_t write_len, uint8_t *write +static int +i2c_do_write(i2c_hw_t *i2c, uint8_t write_len, uint8_t *write , uint8_t send_stop, uint32_t timeout) { for (int i = 0; i < write_len; i++) { @@ -143,7 +144,7 @@ i2c_do_write(i2c_hw_t *i2c, uint8_t addr, uint8_t write_len, uint8_t *write // Wait until there's a spot in the TX FIFO while (i2c->txflr == 16) { if (!timer_is_before(timer_read_time(), timeout)) - shutdown("i2c timeout"); + return I2C_BUS_TIMEOUT; } i2c->data_cmd = first << I2C_IC_DATA_CMD_RESTART_LSB @@ -152,24 +153,39 @@ i2c_do_write(i2c_hw_t *i2c, uint8_t addr, uint8_t write_len, uint8_t *write } if (!send_stop) - return; + return I2C_BUS_SUCCESS; // Drain the transmit buffer while (i2c->txflr != 0) { if (!timer_is_before(timer_read_time(), timeout)) - shutdown("i2c timeout"); + return I2C_BUS_TIMEOUT; + } + + if (i2c->raw_intr_stat & I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS) { + uint32_t abort_source = i2c->tx_abrt_source; + if (abort_source & I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS) + { + i2c->clr_tx_abrt; + return I2C_BUS_START_NACK; + } + if (abort_source & I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS) + { + i2c->clr_tx_abrt; + return I2C_BUS_NACK; + } } + return I2C_BUS_SUCCESS; } -static void -i2c_do_read(i2c_hw_t *i2c, uint8_t addr, uint8_t read_len, uint8_t *read +static int +i2c_do_read(i2c_hw_t *i2c, uint8_t read_len, uint8_t *read , uint32_t timeout) { int have_read = 0; int to_send = read_len; while (have_read < read_len) { if (!timer_is_before(timer_read_time(), timeout)) - shutdown("i2c timeout"); + return I2C_BUS_TIMEOUT; if (to_send > 0 && i2c->txflr < 16) { int first = to_send == read_len; @@ -186,30 +202,47 @@ i2c_do_read(i2c_hw_t *i2c, uint8_t addr, uint8_t read_len, uint8_t *read *read++ = i2c->data_cmd & 0xFF; have_read++; } + + if (i2c->raw_intr_stat & I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS) { + uint32_t abort_source = i2c->tx_abrt_source; + if (abort_source & I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS) { + i2c->clr_tx_abrt; + return I2C_BUS_START_READ_NACK; + } + } } + + return I2C_BUS_SUCCESS; } -void +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write) { i2c_hw_t *i2c = (i2c_hw_t*)config.i2c; uint32_t timeout = timer_read_time() + timer_from_us(5000); + int ret; i2c_start(i2c, config.addr); - i2c_do_write(i2c, config.addr, write_len, write, 1, timeout); + ret = i2c_do_write(i2c, write_len, write, 1, timeout); i2c_stop(i2c); + return ret; } -void +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg , uint8_t read_len, uint8_t *read) { i2c_hw_t *i2c = (i2c_hw_t*)config.i2c; uint32_t timeout = timer_read_time() + timer_from_us(5000); + int ret = I2C_BUS_SUCCESS; i2c_start(i2c, config.addr); if (reg_len != 0) - i2c_do_write(i2c, config.addr, reg_len, reg, 0, timeout); - i2c_do_read(i2c, config.addr, read_len, read, timeout); + ret = i2c_do_write(i2c, reg_len, reg, 0, timeout); + if (ret != I2C_BUS_SUCCESS) + goto out; + ret = i2c_do_read(i2c, read_len, read, timeout); +out: i2c_stop(i2c); + return ret; } diff --git a/src/rp2040/internal.h b/src/rp2040/internal.h index 8553278d5417..da5b0a5b115b 100644 --- a/src/rp2040/internal.h +++ b/src/rp2040/internal.h @@ -1,18 +1,21 @@ #ifndef __RP2040_INTERNAL_H #define __RP2040_INTERNAL_H -// Local definitions for rp2040 +// Local definitions for RPxxxx chips -#include "RP2040.h" +#include "autoconf.h" // CONFIG_MACH_RP2040 + +#if CONFIG_MACH_RP2040 + #include "RP2040.h" +#elif CONFIG_MACH_RP2350 + #include "RP2350.h" +#endif void enable_pclock(uint32_t reset_bit); int is_enabled_pclock(uint32_t reset_bit); uint32_t get_pclock_frequency(uint32_t reset_bit); void gpio_peripheral(uint32_t gpio, int func, int pull_up); -void reset_to_usb_boot(uint32_t gpio_activity_pin_mask - , uint32_t disable_interface_mask); -void connect_internal_flash(void); -void flash_exit_xip(void); -void flash_flush_cache(void); +void bootrom_reboot_usb_bootloader(void); +void bootrom_read_unique_id(uint8_t *out, uint32_t maxlen); // Force a function to run from ram #define UNIQSEC __FILE__ "." __stringify(__LINE__) diff --git a/src/rp2040/main.c b/src/rp2040/main.c index e7b64e5f0da2..144b8796bbb5 100644 --- a/src/rp2040/main.c +++ b/src/rp2040/main.c @@ -15,6 +15,10 @@ #include "internal.h" // enable_pclock #include "sched.h" // sched_main +#if !CONFIG_MACH_RP2040 +#include "hardware/structs/ticks.h" // ticks_hw +#endif + /**************************************************************** * Ram IRQ vector table @@ -24,7 +28,7 @@ static void enable_ram_vectortable(void) { - // Symbols created by rp2040_link.lds.S linker script + // Symbols created by rpxxxx_link.lds.S linker script extern uint32_t _ram_vectortable_start, _ram_vectortable_end; extern uint32_t _text_vectortable_start; @@ -45,8 +49,7 @@ bootloader_request(void) { watchdog_hw->ctrl = 0; try_request_canboot(); - // Use the bootrom-provided code to reset into BOOTSEL mode - reset_to_usb_boot(0, 0); + bootrom_reboot_usb_bootloader(); } @@ -55,7 +58,7 @@ bootloader_request(void) ****************************************************************/ #define FREQ_XOSC 12000000 -#define FREQ_SYS 125000000 +#define FREQ_SYS (CONFIG_MACH_RP2040 ? 125000000 : CONFIG_CLOCK_FREQ) #define FREQ_USB 48000000 void @@ -85,7 +88,7 @@ xosc_setup(void) xosc_hw->startup = DIV_ROUND_UP(FREQ_XOSC, 1000 * 256); // 1ms xosc_hw->ctrl = (XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ | (XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB)); - while(!(xosc_hw->status & XOSC_STATUS_STABLE_BITS)) + while (!(xosc_hw->status & XOSC_STATUS_STABLE_BITS)) ; } @@ -94,6 +97,10 @@ pll_setup(pll_hw_t *pll, uint32_t mul, uint32_t postdiv) { // Setup pll uint32_t refdiv = 1, fbdiv = mul, postdiv2 = 2, postdiv1 = postdiv/postdiv2; + if (postdiv1 > 0x07) { + postdiv1 >>= 1; + postdiv2 <<= 1; + } pll->cs = refdiv; pll->fbdiv_int = fbdiv; pll->pwr = PLL_PWR_DSMPD_BITS | PLL_PWR_POSTDIVPD_BITS; @@ -143,7 +150,7 @@ clock_setup(void) // Setup pll_usb enable_pclock(RESETS_RESET_PLL_USB_BITS); - pll_setup(pll_usb_hw, 40, 40*FREQ_XOSC/FREQ_USB); + pll_setup(pll_usb_hw, 80, 80*FREQ_XOSC/FREQ_USB); // Setup peripheral clocks clk_aux_setup(clk_peri, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS); @@ -155,7 +162,12 @@ clock_setup(void) cref->ctrl = CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC; while (!(cref->selected & (1 << 2))) ; +#if CONFIG_MACH_RP2040 watchdog_hw->tick = 1 | WATCHDOG_TICK_ENABLE_BITS; +#else + ticks_hw->ticks[TICK_WATCHDOG].cycles = 1; + ticks_hw->ticks[TICK_WATCHDOG].ctrl = TICKS_WATCHDOG_CTRL_ENABLE_BITS; +#endif // Enable GPIO control enable_pclock(RESETS_RESET_IO_BANK0_BITS | RESETS_RESET_PADS_BANK0_BITS); diff --git a/src/rp2040/rp2350_bootrom.c b/src/rp2040/rp2350_bootrom.c new file mode 100644 index 000000000000..257fb3d44d97 --- /dev/null +++ b/src/rp2040/rp2350_bootrom.c @@ -0,0 +1,59 @@ +// Code for interacting with bootrom on rp235x chips +// +// Copyright (C) 2024 Kevin O'Connor +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include // uint32_t +#include "boot/picoboot_constants.h" // REBOOT2_FLAG_REBOOT_TYPE_BOOTSEL +#include "hardware/address_mapped.h" // static_assert +#include "internal.h" // bootrom_read_unique_id +#include "pico/bootrom_constants.h" // RT_FLAG_FUNC_ARM_NONSEC + +static void * +rom_func_lookup(uint32_t code) +{ + typedef void *(*rom_table_lookup_fn)(uint32_t code, uint32_t mask); +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Warray-bounds" + rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) + (uintptr_t)*(uint16_t*)(BOOTROM_TABLE_LOOKUP_OFFSET); +#pragma GCC diagnostic pop + return rom_table_lookup(code, RT_FLAG_FUNC_ARM_SEC); +} + + +/**************************************************************** + * Reboot to USB rom bootloader + ****************************************************************/ + +void +bootrom_reboot_usb_bootloader(void) +{ + typedef int (*rom_reboot_fn)(uint32_t flags, uint32_t delay_ms + , uint32_t p0, uint32_t p1); + rom_reboot_fn func = rom_func_lookup(ROM_FUNC_REBOOT); + func(REBOOT2_FLAG_REBOOT_TYPE_BOOTSEL | REBOOT2_FLAG_NO_RETURN_ON_SUCCESS + , 10, 0, 0); +} + + +/**************************************************************** + * Unique id reading + ****************************************************************/ + +#define PICO_UNIQUE_BOARD_ID_SIZE_BYTES 8 + +void +bootrom_read_unique_id(uint8_t *out, uint32_t maxlen) +{ + typedef int (*rom_get_sys_info_fn)(uint8_t *out_buffer + , uint32_t out_buffer_word_size + , uint32_t flags); + rom_get_sys_info_fn func = rom_func_lookup(ROM_FUNC_GET_SYS_INFO); + uint8_t data[9 * 4]; + func(data, 9, SYS_INFO_CHIP_INFO); + int i; + for (i = 0; i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES; i++) + out[i] = data[PICO_UNIQUE_BOARD_ID_SIZE_BYTES - 1 + 2 * 4 - i]; +} diff --git a/src/rp2040/rp2040_link.lds.S b/src/rp2040/rpxxxx_link.lds.S similarity index 91% rename from src/rp2040/rp2040_link.lds.S rename to src/rp2040/rpxxxx_link.lds.S index abc5be6c5d2f..5cd556fe7ba4 100644 --- a/src/rp2040/rp2040_link.lds.S +++ b/src/rp2040/rpxxxx_link.lds.S @@ -42,6 +42,15 @@ SECTIONS KEEP(*(.vector_table)) _text_vectortable_end = .; *(.text.armcm_boot*) + +#if CONFIG_MACH_RP2350 + // The rp2350 needs an "image definition" for the internal ROM + LONG(0xffffded3) + LONG(0x10210142) + LONG(0x000001ff) + LONG(0x00000000) + LONG(0xab123579) +#endif } > rom :text_segment . = ALIGN(4); diff --git a/src/rp2040/serial.c b/src/rp2040/serial.c index 351a873e55bf..1c2369779c2d 100644 --- a/src/rp2040/serial.c +++ b/src/rp2040/serial.c @@ -18,44 +18,44 @@ // Dynamically select UART and IRQ based on configuration - #if CONFIG_RP2040_SERIAL_UART0_PINS_0_1 + #if CONFIG_RPXXXX_SERIAL_UART0_PINS_0_1 #define GPIO_Rx 1 #define GPIO_Tx 0 #define UARTx uart0_hw #define UARTx_IRQn UART0_IRQ_IRQn - #elif CONFIG_RP2040_SERIAL_UART0_PINS_12_13 + #elif CONFIG_RPXXXX_SERIAL_UART0_PINS_12_13 #define GPIO_Rx 13 #define GPIO_Tx 12 #define UARTx uart0_hw #define UARTx_IRQn UART0_IRQ_IRQn - #elif CONFIG_RP2040_SERIAL_UART0_PINS_16_17 + #elif CONFIG_RPXXXX_SERIAL_UART0_PINS_16_17 #define GPIO_Rx 17 #define GPIO_Tx 16 #define UARTx uart0_hw #define UARTx_IRQn UART0_IRQ_IRQn - #elif CONFIG_RP2040_SERIAL_UART0_PINS_28_29 + #elif CONFIG_RPXXXX_SERIAL_UART0_PINS_28_29 #define GPIO_Rx 29 #define GPIO_Tx 28 #define UARTx uart1_hw #define UARTx_IRQn UART1_IRQ_IRQn #define UARTx uart0_hw #define UARTx_IRQn UART0_IRQ_IRQn - #elif CONFIG_RP2040_SERIAL_UART1_PINS_4_5 + #elif CONFIG_RPXXXX_SERIAL_UART1_PINS_4_5 #define GPIO_Rx 5 #define GPIO_Tx 4 #define UARTx uart1_hw #define UARTx_IRQn UART1_IRQ_IRQn - #elif CONFIG_RP2040_SERIAL_UART1_PINS_8_9 + #elif CONFIG_RPXXXX_SERIAL_UART1_PINS_8_9 #define GPIO_Rx 9 #define GPIO_Tx 8 #define UARTx uart1_hw #define UARTx_IRQn UART1_IRQ_IRQn - #elif CONFIG_RP2040_SERIAL_UART1_PINS_20_21 + #elif CONFIG_RPXXXX_SERIAL_UART1_PINS_20_21 #define GPIO_Rx 20 #define GPIO_Tx 21 #define UARTx uart1_hw #define UARTx_IRQn UART1_IRQ_IRQn - #elif CONFIG_RP2040_SERIAL_UART1_PINS_24_25 + #elif CONFIG_RPXXXX_SERIAL_UART1_PINS_24_25 #define GPIO_Rx 24 #define GPIO_Tx 25 #define UARTx uart1_hw diff --git a/src/rp2040/usbserial.c b/src/rp2040/usbserial.c index 61d04d1891a5..b4d90b5ad672 100644 --- a/src/rp2040/usbserial.c +++ b/src/rp2040/usbserial.c @@ -1,6 +1,6 @@ // Hardware interface to USB on rp2040 // -// Copyright (C) 2021-2023 Kevin O'Connor +// Copyright (C) 2021-2024 Kevin O'Connor // // This file may be distributed under the terms of the GNU GPLv3 license. @@ -69,6 +69,29 @@ get_rx_count(uint32_t epb, uint32_t max_len) return c; } +// Memcpy using 8-bit read/write (system memcpy may make unaligned accesses) +static void +dpram_memcpy(void *dest, const void *src, size_t n) +{ + const uint8_t *s = src; + volatile uint8_t *d = dest; + while (n) { + *d++ = *s++; + n -= sizeof(*d); + } +} + +// Memset using only 8-bit writes (system memcpy may make unaligned accesses) +static void +dpram_memset(void *s, int c, size_t n) +{ + volatile uint8_t *p = s; + while (n) { + *p++ = c; + n -= sizeof(*p); + } +} + /**************************************************************** * Interface @@ -94,7 +117,7 @@ usb_read_bulk_out(void *data, uint_fast8_t max_len) barrier(); // Copy the packet to the given buffer uint32_t c = get_rx_count(epb, max_len); - memcpy(data, usb_buf_addr(ep, bufnum), c); + dpram_memcpy(data, usb_buf_addr(ep, bufnum), c); // Notify the USB hardware that the space is now available barrier(); *epbp = new_epb | USB_BUF_CTRL_AVAIL; @@ -120,7 +143,7 @@ usb_send_bulk_in(void *data, uint_fast8_t len) *epbp = new_epb; barrier(); // Copy the packet to the hw buffer - memcpy(usb_buf_addr(ep, bufnum), data, len); + dpram_memcpy(usb_buf_addr(ep, bufnum), data, len); // Inform the USB hardware of the available packet barrier(); *epbp = new_epb | USB_BUF_CTRL_AVAIL; @@ -140,7 +163,7 @@ usb_read_ep0_setup(void *data, uint_fast8_t max_len) | USB_BUF_CTRL_AVAIL | DPBUF_SIZE); usb_hw->sie_status = USB_SIE_STATUS_SETUP_REC_BITS; barrier(); - memcpy(data, (void*)usb_dpram->setup_packet, max_len); + dpram_memcpy(data, (void*)usb_dpram->setup_packet, max_len); barrier(); if (usb_hw->intr & USB_INTR_SETUP_REQ_BITS) { // Raced with next setup packet @@ -168,7 +191,7 @@ usb_read_ep0(void *data, uint_fast8_t max_len) barrier(); // Copy the packet to the given buffer uint32_t c = get_rx_count(epb, max_len); - memcpy(data, usb_buf_addr(ep, 0), c); + dpram_memcpy(data, usb_buf_addr(ep, 0), c); // Notify the USB hardware that the space is now available barrier(); *epbp = new_epb | USB_BUF_CTRL_AVAIL; @@ -193,7 +216,7 @@ usb_send_ep0(const void *data, uint_fast8_t len) *epbp = new_epb; barrier(); // Copy the packet to the hw buffer - memcpy(usb_buf_addr(ep, 0), data, len); + dpram_memcpy(usb_buf_addr(ep, 0), data, len); // Inform the USB hardware of the available packet barrier(); *epbp = new_epb | USB_BUF_CTRL_AVAIL; @@ -380,7 +403,7 @@ usbserial_init(void) enable_pclock(RESETS_RESET_USBCTRL_BITS); // Setup shared memory area - memset(usb_dpram, 0, sizeof(*usb_dpram)); + dpram_memset(usb_dpram, 0, sizeof(*usb_dpram)); endpoint_setup(); // Enable USB in device mode diff --git a/src/sched.c b/src/sched.c index 44cce558ee9e..51d159bc6e5c 100644 --- a/src/sched.c +++ b/src/sched.c @@ -1,6 +1,6 @@ // Basic scheduling functions and startup/shutdown code. // -// Copyright (C) 2016-2021 Kevin O'Connor +// Copyright (C) 2016-2024 Kevin O'Connor // // This file may be distributed under the terms of the GNU GPLv3 license. @@ -19,7 +19,7 @@ static struct timer periodic_timer, sentinel_timer, deleted_timer; static struct { struct timer *timer_list, *last_insert; - int8_t tasks_status; + int8_t tasks_status, tasks_busy; uint8_t shutdown_status, shutdown_reason; } SchedStatus = {.timer_list = &periodic_timer, .last_insert = &periodic_timer}; @@ -205,11 +205,15 @@ sched_wake_tasks(void) SchedStatus.tasks_status = TS_REQUESTED; } -// Check if tasks need to be run +// Check if tasks busy (called from low-level timer dispatch code) uint8_t -sched_tasks_busy(void) +sched_check_set_tasks_busy(void) { - return SchedStatus.tasks_status >= TS_REQUESTED; + // Return busy if tasks never idle between two consecutive calls + if (SchedStatus.tasks_busy >= TS_REQUESTED) + return 1; + SchedStatus.tasks_busy = SchedStatus.tasks_status; + return 0; } // Note that a task is ready to run @@ -243,7 +247,7 @@ run_tasks(void) irq_disable(); if (SchedStatus.tasks_status != TS_REQUESTED) { // Sleep processor (only run timers) until tasks woken - SchedStatus.tasks_status = TS_IDLE; + SchedStatus.tasks_status = SchedStatus.tasks_busy = TS_IDLE; do { irq_wait(); } while (SchedStatus.tasks_status != TS_REQUESTED); diff --git a/src/sched.h b/src/sched.h index 0a2bdc4bcab0..9ec96631eeb4 100644 --- a/src/sched.h +++ b/src/sched.h @@ -31,7 +31,7 @@ void sched_del_timer(struct timer *del); unsigned int sched_timer_dispatch(void); void sched_timer_reset(void); void sched_wake_tasks(void); -uint8_t sched_tasks_busy(void); +uint8_t sched_check_set_tasks_busy(void); void sched_wake_task(struct task_wake *w); uint8_t sched_check_wake(struct task_wake *w); uint8_t sched_is_shutdown(void); diff --git a/src/sensor_ads1220.c b/src/sensor_ads1220.c new file mode 100644 index 000000000000..ea33379a0b6d --- /dev/null +++ b/src/sensor_ads1220.c @@ -0,0 +1,163 @@ +// Support for ADS1220 ADC Chip +// +// Copyright (C) 2024 Gareth Farrington +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "board/irq.h" // irq_disable +#include "board/gpio.h" // gpio_out_write +#include "board/misc.h" // timer_read_time +#include "basecmd.h" // oid_alloc +#include "command.h" // DECL_COMMAND +#include "sched.h" // sched_add_timer +#include "sensor_bulk.h" // sensor_bulk_report +#include "spicmds.h" // spidev_transfer +#include + +struct ads1220_adc { + struct timer timer; + uint32_t rest_ticks; + struct gpio_in data_ready; + struct spidev_s *spi; + uint8_t pending_flag, data_count; + struct sensor_bulk sb; +}; + +// Flag types +enum { + FLAG_PENDING = 1 << 0 +}; + +#define BYTES_PER_SAMPLE 4 + +static struct task_wake wake_ads1220; + +/**************************************************************** + * ADS1220 Sensor Support + ****************************************************************/ + +int8_t +ads1220_is_data_ready(struct ads1220_adc *ads1220) { + return gpio_in_read(ads1220->data_ready) == 0; +} + +// Event handler that wakes wake_ads1220() periodically +static uint_fast8_t +ads1220_event(struct timer *timer) +{ + struct ads1220_adc *ads1220 = container_of(timer, struct ads1220_adc, + timer); + uint32_t rest_ticks = ads1220->rest_ticks; + if (ads1220->pending_flag) { + ads1220->sb.possible_overflows++; + rest_ticks *= 4; + } else if (ads1220_is_data_ready(ads1220)) { + ads1220->pending_flag = 1; + sched_wake_task(&wake_ads1220); + rest_ticks *= 8; + } + ads1220->timer.waketime += rest_ticks; + return SF_RESCHEDULE; +} + +// Add a measurement to the buffer +static void +add_sample(struct ads1220_adc *ads1220, uint8_t oid, uint_fast32_t counts) +{ + ads1220->sb.data[ads1220->sb.data_count] = counts; + ads1220->sb.data[ads1220->sb.data_count + 1] = counts >> 8; + ads1220->sb.data[ads1220->sb.data_count + 2] = counts >> 16; + ads1220->sb.data[ads1220->sb.data_count + 3] = counts >> 24; + ads1220->sb.data_count += BYTES_PER_SAMPLE; + + if ((ads1220->sb.data_count + BYTES_PER_SAMPLE) > + ARRAY_SIZE(ads1220->sb.data)) { + sensor_bulk_report(&ads1220->sb, oid); + } +} + +// ADS1220 ADC query +void +ads1220_read_adc(struct ads1220_adc *ads1220, uint8_t oid) +{ + uint8_t msg[3] = {0, 0, 0}; + spidev_transfer(ads1220->spi, 1, sizeof(msg), msg); + ads1220->pending_flag = 0; + barrier(); + + // create 24 bit int from bytes + uint32_t counts = ((uint32_t)msg[0] << 16) + | ((uint32_t)msg[1] << 8) + | ((uint32_t)msg[2]); + + // extend 2's complement 24 bits to 32bits + if (counts & 0x800000) + counts |= 0xFF000000; + + add_sample(ads1220, oid, counts); +} + +// Create an ads1220 sensor +void +command_config_ads1220(uint32_t *args) +{ + struct ads1220_adc *ads1220 = oid_alloc(args[0] + , command_config_ads1220, sizeof(*ads1220)); + ads1220->timer.func = ads1220_event; + ads1220->pending_flag = 0; + ads1220->spi = spidev_oid_lookup(args[1]); + ads1220->data_ready = gpio_in_setup(args[2], 0); +} +DECL_COMMAND(command_config_ads1220, "config_ads1220 oid=%c" + " spi_oid=%c data_ready_pin=%u"); + +// start/stop capturing ADC data +void +command_query_ads1220(uint32_t *args) +{ + uint8_t oid = args[0]; + struct ads1220_adc *ads1220 = oid_lookup(oid, command_config_ads1220); + sched_del_timer(&ads1220->timer); + ads1220->pending_flag = 0; + ads1220->rest_ticks = args[1]; + if (!ads1220->rest_ticks) { + // End measurements + return; + } + // Start new measurements + sensor_bulk_reset(&ads1220->sb); + irq_disable(); + ads1220->timer.waketime = timer_read_time() + ads1220->rest_ticks; + sched_add_timer(&ads1220->timer); + irq_enable(); +} +DECL_COMMAND(command_query_ads1220, "query_ads1220 oid=%c rest_ticks=%u"); + +void +command_query_ads1220_status(const uint32_t *args) +{ + uint8_t oid = args[0]; + struct ads1220_adc *ads1220 = oid_lookup(oid, command_config_ads1220); + irq_disable(); + const uint32_t start_t = timer_read_time(); + uint8_t is_data_ready = ads1220_is_data_ready(ads1220); + irq_enable(); + uint8_t pending_bytes = is_data_ready ? BYTES_PER_SAMPLE : 0; + sensor_bulk_status(&ads1220->sb, oid, start_t, 0, pending_bytes); +} +DECL_COMMAND(command_query_ads1220_status, "query_ads1220_status oid=%c"); + +// Background task that performs measurements +void +ads1220_capture_task(void) +{ + if (!sched_check_wake(&wake_ads1220)) + return; + uint8_t oid; + struct ads1220_adc *ads1220; + foreach_oid(oid, ads1220, command_config_ads1220) { + if (ads1220->pending_flag) + ads1220_read_adc(ads1220, oid); + } +} +DECL_TASK(ads1220_capture_task); diff --git a/src/sensor_hx71x.c b/src/sensor_hx71x.c new file mode 100644 index 000000000000..f20d880726fe --- /dev/null +++ b/src/sensor_hx71x.c @@ -0,0 +1,253 @@ +// Support for bit-banging commands to HX711 and HX717 ADC chips +// +// Copyright (C) 2024 Gareth Farrington +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "autoconf.h" // CONFIG_MACH_AVR +#include "board/gpio.h" // gpio_out_write +#include "board/irq.h" // irq_poll +#include "board/misc.h" // timer_read_time +#include "basecmd.h" // oid_alloc +#include "command.h" // DECL_COMMAND +#include "sched.h" // sched_add_timer +#include "sensor_bulk.h" // sensor_bulk_report +#include +#include + +struct hx71x_adc { + struct timer timer; + uint8_t gain_channel; // the gain+channel selection (1-4) + uint8_t flags; + uint32_t rest_ticks; + uint32_t last_error; + struct gpio_in dout; // pin used to receive data from the hx71x + struct gpio_out sclk; // pin used to generate clock for the hx71x + struct sensor_bulk sb; +}; + +enum { + HX_PENDING = 1<<0, HX_OVERFLOW = 1<<1, +}; + +#define BYTES_PER_SAMPLE 4 +#define SAMPLE_ERROR_DESYNC 1L << 31 +#define SAMPLE_ERROR_READ_TOO_LONG 1L << 30 + +static struct task_wake wake_hx71x; + + +/**************************************************************** + * Low-level bit-banging + ****************************************************************/ + +#define MIN_PULSE_TIME nsecs_to_ticks(200) + +static uint32_t +nsecs_to_ticks(uint32_t ns) +{ + return timer_from_us(ns * 1000) / 1000000; +} + +// Pause for 200ns +static void +hx71x_delay_noirq(void) +{ + if (CONFIG_MACH_AVR) { + // Optimize avr, as calculating time takes longer than needed delay + asm("nop\n nop"); + return; + } + uint32_t end = timer_read_time() + MIN_PULSE_TIME; + while (timer_is_before(timer_read_time(), end)) + ; +} + +// Pause for a minimum of 200ns +static void +hx71x_delay(void) +{ + if (CONFIG_MACH_AVR) + // Optimize avr, as calculating time takes longer than needed delay + return; + uint32_t end = timer_read_time() + MIN_PULSE_TIME; + while (timer_is_before(timer_read_time(), end)) + irq_poll(); +} + +// Read 'num_bits' from the sensor +static uint32_t +hx71x_raw_read(struct gpio_in dout, struct gpio_out sclk, int num_bits) +{ + uint32_t bits_read = 0; + while (num_bits--) { + irq_disable(); + gpio_out_toggle_noirq(sclk); + hx71x_delay_noirq(); + gpio_out_toggle_noirq(sclk); + uint_fast8_t bit = gpio_in_read(dout); + irq_enable(); + hx71x_delay(); + bits_read = (bits_read << 1) | bit; + } + return bits_read; +} + + +/**************************************************************** + * HX711 and HX717 Sensor Support + ****************************************************************/ + +// Check if data is ready +static uint_fast8_t +hx71x_is_data_ready(struct hx71x_adc *hx71x) +{ + return !gpio_in_read(hx71x->dout); +} + +// Event handler that wakes wake_hx71x() periodically +static uint_fast8_t +hx71x_event(struct timer *timer) +{ + struct hx71x_adc *hx71x = container_of(timer, struct hx71x_adc, timer); + uint32_t rest_ticks = hx71x->rest_ticks; + uint8_t flags = hx71x->flags; + if (flags & HX_PENDING) { + hx71x->sb.possible_overflows++; + hx71x->flags = HX_PENDING | HX_OVERFLOW; + rest_ticks *= 4; + } else if (hx71x_is_data_ready(hx71x)) { + // New sample pending + hx71x->flags = HX_PENDING; + sched_wake_task(&wake_hx71x); + rest_ticks *= 8; + } + hx71x->timer.waketime += rest_ticks; + return SF_RESCHEDULE; +} + +static void +add_sample(struct hx71x_adc *hx71x, uint8_t oid, uint32_t counts, + uint8_t force_flush) { + // Add measurement to buffer + hx71x->sb.data[hx71x->sb.data_count] = counts; + hx71x->sb.data[hx71x->sb.data_count + 1] = counts >> 8; + hx71x->sb.data[hx71x->sb.data_count + 2] = counts >> 16; + hx71x->sb.data[hx71x->sb.data_count + 3] = counts >> 24; + hx71x->sb.data_count += BYTES_PER_SAMPLE; + + if (hx71x->sb.data_count + BYTES_PER_SAMPLE > ARRAY_SIZE(hx71x->sb.data) + || force_flush) + sensor_bulk_report(&hx71x->sb, oid); +} + +// hx71x ADC query +static void +hx71x_read_adc(struct hx71x_adc *hx71x, uint8_t oid) +{ + // Read from sensor + uint_fast8_t gain_channel = hx71x->gain_channel; + uint32_t adc = hx71x_raw_read(hx71x->dout, hx71x->sclk, 24 + gain_channel); + + // Clear pending flag (and note if an overflow occurred) + irq_disable(); + uint8_t flags = hx71x->flags; + hx71x->flags = 0; + irq_enable(); + + // Extract report from raw data + uint32_t counts = adc >> gain_channel; + if (counts & 0x800000) + counts |= 0xFF000000; + + // Check for errors + uint_fast8_t extras_mask = (1 << gain_channel) - 1; + if ((adc & extras_mask) != extras_mask) { + // Transfer did not complete correctly + hx71x->last_error = SAMPLE_ERROR_DESYNC; + } else if (flags & HX_OVERFLOW) { + // Transfer took too long + hx71x->last_error = SAMPLE_ERROR_READ_TOO_LONG; + } + + // forever send errors until reset + if (hx71x->last_error != 0) { + counts = hx71x->last_error; + } + + // Add measurement to buffer + add_sample(hx71x, oid, counts, false); +} + +// Create a hx71x sensor +void +command_config_hx71x(uint32_t *args) +{ + struct hx71x_adc *hx71x = oid_alloc(args[0] + , command_config_hx71x, sizeof(*hx71x)); + hx71x->timer.func = hx71x_event; + uint8_t gain_channel = args[1]; + if (gain_channel < 1 || gain_channel > 4) { + shutdown("HX71x gain/channel out of range 1-4"); + } + hx71x->gain_channel = gain_channel; + hx71x->dout = gpio_in_setup(args[2], 1); + hx71x->sclk = gpio_out_setup(args[3], 0); + gpio_out_write(hx71x->sclk, 1); // put chip in power down state +} +DECL_COMMAND(command_config_hx71x, "config_hx71x oid=%c gain_channel=%c" + " dout_pin=%u sclk_pin=%u"); + +// start/stop capturing ADC data +void +command_query_hx71x(uint32_t *args) +{ + uint8_t oid = args[0]; + struct hx71x_adc *hx71x = oid_lookup(oid, command_config_hx71x); + sched_del_timer(&hx71x->timer); + hx71x->flags = 0; + hx71x->last_error = 0; + hx71x->rest_ticks = args[1]; + if (!hx71x->rest_ticks) { + // End measurements + gpio_out_write(hx71x->sclk, 1); // put chip in power down state + return; + } + // Start new measurements + gpio_out_write(hx71x->sclk, 0); // wake chip from power down + sensor_bulk_reset(&hx71x->sb); + irq_disable(); + hx71x->timer.waketime = timer_read_time() + hx71x->rest_ticks; + sched_add_timer(&hx71x->timer); + irq_enable(); +} +DECL_COMMAND(command_query_hx71x, "query_hx71x oid=%c rest_ticks=%u"); + +void +command_query_hx71x_status(const uint32_t *args) +{ + uint8_t oid = args[0]; + struct hx71x_adc *hx71x = oid_lookup(oid, command_config_hx71x); + irq_disable(); + const uint32_t start_t = timer_read_time(); + uint8_t is_data_ready = hx71x_is_data_ready(hx71x); + irq_enable(); + uint8_t pending_bytes = is_data_ready ? BYTES_PER_SAMPLE : 0; + sensor_bulk_status(&hx71x->sb, oid, start_t, 0, pending_bytes); +} +DECL_COMMAND(command_query_hx71x_status, "query_hx71x_status oid=%c"); + +// Background task that performs measurements +void +hx71x_capture_task(void) +{ + if (!sched_check_wake(&wake_hx71x)) + return; + uint8_t oid; + struct hx71x_adc *hx71x; + foreach_oid(oid, hx71x, command_config_hx71x) { + if (hx71x->flags) + hx71x_read_adc(hx71x, oid); + } +} +DECL_TASK(hx71x_capture_task); diff --git a/src/sensor_ldc1612.c b/src/sensor_ldc1612.c index 01cf3ee04597..8b67884f15c9 100644 --- a/src/sensor_ldc1612.c +++ b/src/sensor_ldc1612.c @@ -7,7 +7,6 @@ #include // memcpy #include "basecmd.h" // oid_alloc -#include "board/gpio.h" // i2c_read #include "board/irq.h" // irq_disable #include "board/misc.h" // timer_read_time #include "command.h" // DECL_COMMAND @@ -147,7 +146,8 @@ check_home(struct ldc1612 *ld, uint32_t data) static void read_reg(struct ldc1612 *ld, uint8_t reg, uint8_t *res) { - i2c_read(ld->i2c->i2c_config, sizeof(reg), ®, 2, res); + int ret = i2c_dev_read(ld->i2c, sizeof(reg), ®, 2, res); + i2c_shutdown_on_err(ret); } // Read the status register on the ldc1612 @@ -180,7 +180,10 @@ ldc1612_query(struct ldc1612 *ld, uint8_t oid) ld->sb.data_count += BYTES_PER_SAMPLE; // Check for endstop trigger - uint32_t data = (d[0] << 24L) | (d[1] << 16L) | (d[2] << 8) | d[3]; + uint32_t data = ((uint32_t)d[0] << 24) + | ((uint32_t)d[1] << 16) + | ((uint32_t)d[2] << 8) + | ((uint32_t)d[3]); check_home(ld, data); // Flush local buffer if needed diff --git a/src/sensor_lis2dw.c b/src/sensor_lis2dw.c index 83922003c31b..8a4a6a66444b 100644 --- a/src/sensor_lis2dw.c +++ b/src/sensor_lis2dw.c @@ -6,6 +6,8 @@ // This file may be distributed under the terms of the GNU GPLv3 license. #include // memcpy +#include "autoconf.h" // CONFIG_HAVE_GPIO_SPI +#include "board/gpio.h" // irq_disable #include "board/irq.h" // irq_disable #include "board/misc.h" // timer_read_time #include "basecmd.h" // oid_alloc @@ -13,9 +15,12 @@ #include "sched.h" // DECL_TASK #include "sensor_bulk.h" // sensor_bulk_report #include "spicmds.h" // spidev_transfer +#include "i2ccmds.h" // i2cdev_s #define LIS_AR_DATAX0 0x28 #define LIS_AM_READ 0x80 +#define LIS_MS_SPI 0x40 +#define LIS_MS_I2C 0x80 #define LIS_FIFO_SAMPLES 0x2F #define BYTES_PER_SAMPLE 6 @@ -23,8 +28,13 @@ struct lis2dw { struct timer timer; uint32_t rest_ticks; - struct spidev_s *spi; + union { + struct spidev_s *spi; + struct i2cdev_s *i2c; + }; + uint8_t bus_type; uint8_t flags; + uint8_t model; struct sensor_bulk sb; }; @@ -32,6 +42,20 @@ enum { LIS_PENDING = 1<<0, }; +enum { + SPI_SERIAL, I2C_SERIAL, +}; + +DECL_ENUMERATION("bus_oid_type", "spi", SPI_SERIAL); +DECL_ENUMERATION("bus_oid_type", "i2c", I2C_SERIAL); + +enum { + LIS2DW, LIS3DH, +}; + +DECL_ENUMERATION("lis_chip_type", "LIS2DW", LIS2DW); +DECL_ENUMERATION("lis_chip_type", "LIS3DH", LIS3DH); + static struct task_wake lis2dw_wake; // Event handler that wakes lis2dw_task() periodically @@ -50,9 +74,39 @@ command_config_lis2dw(uint32_t *args) struct lis2dw *ax = oid_alloc(args[0], command_config_lis2dw , sizeof(*ax)); ax->timer.func = lis2dw_event; - ax->spi = spidev_oid_lookup(args[1]); + + switch (args[2]) { + case SPI_SERIAL: + if (CONFIG_HAVE_GPIO_SPI) { + ax->spi = spidev_oid_lookup(args[1]); + ax->bus_type = SPI_SERIAL; + break; + } else { + shutdown("bus_type spi unsupported"); + } + case I2C_SERIAL: + if (CONFIG_HAVE_GPIO_I2C) { + ax->i2c = i2cdev_oid_lookup(args[1]); + ax->bus_type = I2C_SERIAL; + break; + } else { + shutdown("bus_type i2c unsupported"); + } + default: + shutdown("bus_type invalid"); + } + + switch (args[3]) { + case LIS2DW: + case LIS3DH: + ax->model = args[3]; + break; + default: + shutdown("model type invalid"); + } } -DECL_COMMAND(command_config_lis2dw, "config_lis2dw oid=%c spi_oid=%c"); +DECL_COMMAND(command_config_lis2dw, "config_lis2dw oid=%c" + " bus_oid=%c bus_oid_type=%c lis_chip_type=%c"); // Helper code to reschedule the lis2dw_event() timer static void @@ -68,25 +122,58 @@ lis2dw_reschedule_timer(struct lis2dw *ax) static void lis2dw_query(struct lis2dw *ax, uint8_t oid) { - uint8_t msg[7] = {0}; - uint8_t fifo[2] = {LIS_FIFO_SAMPLES| LIS_AM_READ , 0}; - uint8_t fifo_empty,fifo_ovrn = 0; - - msg[0] = LIS_AR_DATAX0 | LIS_AM_READ ; + uint8_t fifo_empty = 0; + uint8_t fifo_ovrn = 0; uint8_t *d = &ax->sb.data[ax->sb.data_count]; - spidev_transfer(ax->spi, 1, sizeof(msg), msg); + if (CONFIG_HAVE_GPIO_SPI && ax->bus_type == SPI_SERIAL) { + uint8_t msg[7] = {0}; + uint8_t fifo[2] = {LIS_FIFO_SAMPLES | LIS_AM_READ , 0}; + + msg[0] = LIS_AR_DATAX0 | LIS_AM_READ; + if (ax->model == LIS3DH) + msg[0] |= LIS_MS_SPI; + + spidev_transfer(ax->spi, 1, sizeof(msg), msg); - spidev_transfer(ax->spi, 1, sizeof(fifo), fifo); - fifo_empty = fifo[1]&0x3F; - fifo_ovrn = fifo[1]&0x40; + spidev_transfer(ax->spi, 1, sizeof(fifo), fifo); - d[0] = msg[1]; // x low bits - d[1] = msg[2]; // x high bits - d[2] = msg[3]; // y low bits - d[3] = msg[4]; // y high bits - d[4] = msg[5]; // z low bits - d[5] = msg[6]; // z high bits + if (ax->model == LIS3DH) + fifo_empty = fifo[1] & 0x20; + else + fifo_empty = fifo[1] & 0x3F; + + fifo_ovrn = fifo[1] & 0x40; + + for (uint32_t i = 0; i < BYTES_PER_SAMPLE; i++) + d[i] = msg[i + 1]; + } else if (CONFIG_HAVE_GPIO_I2C && ax->bus_type == I2C_SERIAL) { + uint8_t msg_reg[] = {LIS_AR_DATAX0}; + if (ax->model == LIS3DH) + msg_reg[0] |= LIS_MS_I2C; + uint8_t msg[6]; + uint8_t fifo_reg[1] = {LIS_FIFO_SAMPLES}; + uint8_t fifo[1]; + + int ret; + ret = i2c_dev_read(ax->i2c, sizeof(msg_reg), msg_reg + , sizeof(msg), msg); + i2c_shutdown_on_err(ret); + + ret = i2c_dev_read(ax->i2c, sizeof(fifo_reg), fifo_reg + , sizeof(fifo), fifo); + i2c_shutdown_on_err(ret); + + if (ax->model == LIS3DH) + fifo_empty = fifo[0] & 0x20; + else + fifo_empty = fifo[0] & 0x3F; + + fifo_ovrn = fifo[0] & 0x40; + + for (uint32_t i = 0; i < BYTES_PER_SAMPLE; i++) + d[i] = msg[i]; + } ax->sb.data_count += BYTES_PER_SAMPLE; if (ax->sb.data_count + BYTES_PER_SAMPLE > ARRAY_SIZE(ax->sb.data)) @@ -129,12 +216,32 @@ void command_query_lis2dw_status(uint32_t *args) { struct lis2dw *ax = oid_lookup(args[0], command_config_lis2dw); - uint8_t msg[2] = { LIS_FIFO_SAMPLES | LIS_AM_READ, 0x00 }; - uint32_t time1 = timer_read_time(); - spidev_transfer(ax->spi, 1, sizeof(msg), msg); - uint32_t time2 = timer_read_time(); + uint32_t time1 = 0; + uint32_t time2 = 0; + uint8_t status = 0; + + if (CONFIG_HAVE_GPIO_SPI && ax->bus_type == SPI_SERIAL) { + uint8_t msg[2] = { LIS_FIFO_SAMPLES | LIS_AM_READ, 0x00 }; + time1 = timer_read_time(); + spidev_transfer(ax->spi, 1, sizeof(msg), msg); + time2 = timer_read_time(); + status = msg[1]; + } else if (CONFIG_HAVE_GPIO_I2C && ax->bus_type == I2C_SERIAL) { + uint8_t fifo_reg[1] = {LIS_FIFO_SAMPLES}; + uint8_t fifo[1]; + + time1 = timer_read_time(); + int ret = i2c_dev_read(ax->i2c, sizeof(fifo_reg), fifo_reg + , sizeof(fifo), fifo); + time2 = timer_read_time(); + + i2c_shutdown_on_err(ret); + + status = fifo[0]; + } + sensor_bulk_status(&ax->sb, args[0], time1, time2-time1 - , (msg[1] & 0x1f) * BYTES_PER_SAMPLE); + , (status & 0x1f) * BYTES_PER_SAMPLE); } DECL_COMMAND(command_query_lis2dw_status, "query_lis2dw_status oid=%c"); diff --git a/src/sensor_mpu9250.c b/src/sensor_mpu9250.c index 23c029211f72..7476734c4f0a 100644 --- a/src/sensor_mpu9250.c +++ b/src/sensor_mpu9250.c @@ -13,7 +13,6 @@ #include "command.h" // DECL_COMMAND #include "sched.h" // DECL_TASK #include "sensor_bulk.h" // sensor_bulk_report -#include "board/gpio.h" // i2c_read #include "i2ccmds.h" // i2cdev_oid_lookup // Chip registers @@ -71,13 +70,21 @@ mp9250_reschedule_timer(struct mpu9250 *mp) irq_enable(); } +static void +read_mpu(struct i2cdev_s *i2c, uint8_t reg_len, uint8_t *reg + , uint8_t read_len, uint8_t *read) +{ + int ret = i2c_dev_read(i2c, reg_len, reg, read_len, read); + i2c_shutdown_on_err(ret); +} + // Reads the fifo byte count from the device. static uint16_t get_fifo_status(struct mpu9250 *mp) { uint8_t reg[] = {AR_FIFO_COUNT_H}; uint8_t msg[2]; - i2c_read(mp->i2c->i2c_config, sizeof(reg), reg, sizeof(msg), msg); + read_mpu(mp->i2c, sizeof(reg), reg, sizeof(msg), msg); uint16_t fifo_bytes = ((msg[0] & 0x1f) << 8) | msg[1]; if (fifo_bytes > mp->fifo_max) mp->fifo_max = fifo_bytes; @@ -95,8 +102,7 @@ mp9250_query(struct mpu9250 *mp, uint8_t oid) // If we have enough bytes to fill the buffer do it and send report if (mp->fifo_pkts_bytes >= BYTES_PER_BLOCK) { uint8_t reg = AR_FIFO; - i2c_read(mp->i2c->i2c_config, sizeof(reg), ® - , BYTES_PER_BLOCK, &mp->sb.data[0]); + read_mpu(mp->i2c, sizeof(reg), ®, BYTES_PER_BLOCK, &mp->sb.data[0]); mp->sb.data_count = BYTES_PER_BLOCK; mp->fifo_pkts_bytes -= BYTES_PER_BLOCK; sensor_bulk_report(&mp->sb, oid); @@ -144,8 +150,7 @@ command_query_mpu9250_status(uint32_t *args) // Detect if a FIFO overrun occurred uint8_t int_reg[] = {AR_INT_STATUS}; uint8_t int_msg; - i2c_read(mp->i2c->i2c_config, sizeof(int_reg), int_reg, sizeof(int_msg), - &int_msg); + read_mpu(mp->i2c, sizeof(int_reg), int_reg, sizeof(int_msg), &int_msg); if (int_msg & FIFO_OVERFLOW_INT) mp->sb.possible_overflows++; @@ -153,7 +158,7 @@ command_query_mpu9250_status(uint32_t *args) uint8_t reg[] = {AR_FIFO_COUNT_H}; uint8_t msg[2]; uint32_t time1 = timer_read_time(); - i2c_read(mp->i2c->i2c_config, sizeof(reg), reg, sizeof(msg), msg); + read_mpu(mp->i2c, sizeof(reg), reg, sizeof(msg), msg); uint32_t time2 = timer_read_time(); uint16_t fifo_bytes = ((msg[0] & 0x1f) << 8) | msg[1]; diff --git a/src/stm32/Kconfig b/src/stm32/Kconfig index 037e37bbe949..4112e8334c6d 100644 --- a/src/stm32/Kconfig +++ b/src/stm32/Kconfig @@ -416,6 +416,10 @@ choice bool "Serial (on USART3 PD9/PD8)" if LOW_LEVEL_OPTIONS depends on !MACH_STM32F0 && !MACH_STM32F401 select SERIAL + config STM32_SERIAL_USART3_ALT_PC11_PC10 + bool "Serial (on USART3 PC11/PC10)" if LOW_LEVEL_OPTIONS + depends on MACH_STM32G474 + select SERIAL config STM32_SERIAL_UART4 bool "Serial (on UART4 PA0/PA1)" depends on MACH_STM32H7 diff --git a/src/stm32/gpio.h b/src/stm32/gpio.h index 281e3a8db44c..78f567b8149e 100644 --- a/src/stm32/gpio.h +++ b/src/stm32/gpio.h @@ -51,8 +51,8 @@ struct i2c_config { }; struct i2c_config i2c_setup(uint32_t bus, uint32_t rate, uint8_t addr); -void i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); -void i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg - , uint8_t read_len, uint8_t *read); +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write); +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg + , uint8_t read_len, uint8_t *read); #endif // gpio.h diff --git a/src/stm32/i2c.c b/src/stm32/i2c.c index f5bbd01dd04a..441f611a89f8 100644 --- a/src/stm32/i2c.c +++ b/src/stm32/i2c.c @@ -11,6 +11,7 @@ #include "internal.h" // GPIO #include "sched.h" // sched_shutdown #include "board/irq.h" //irq_disable +#include "i2ccmds.h" // I2C_BUS_SUCCESS struct i2c_info { I2C_TypeDef *i2c; @@ -97,6 +98,8 @@ i2c_wait(I2C_TypeDef *i2c, uint32_t set, uint32_t clear, uint32_t timeout) uint32_t sr1 = i2c->SR1; if ((sr1 & set) == set && (sr1 & clear) == 0) return sr1; + if (sr1 & I2C_SR1_AF) + shutdown("I2C NACK error encountered"); if (!timer_is_before(timer_read_time(), timeout)) shutdown("i2c timeout"); } @@ -147,7 +150,7 @@ i2c_stop(I2C_TypeDef *i2c, uint32_t timeout) i2c_wait(i2c, 0, I2C_SR1_TXE, timeout); } -void +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write) { I2C_TypeDef *i2c = config.i2c; @@ -157,9 +160,11 @@ i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write) while (write_len--) i2c_send_byte(i2c, *write++, timeout); i2c_stop(i2c, timeout); + + return I2C_BUS_SUCCESS; } -void +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg , uint8_t read_len, uint8_t *read) { @@ -180,4 +185,6 @@ i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg read++; } i2c_wait(i2c, 0, I2C_SR1_RXNE, timeout); + + return I2C_BUS_SUCCESS; } diff --git a/src/stm32/stm32f0_i2c.c b/src/stm32/stm32f0_i2c.c index 597b48460eb7..ef12145f7de2 100644 --- a/src/stm32/stm32f0_i2c.c +++ b/src/stm32/stm32f0_i2c.c @@ -9,6 +9,7 @@ #include "gpio.h" // i2c_setup #include "internal.h" // GPIO #include "sched.h" // sched_shutdown +#include "i2ccmds.h" // I2C_BUS_SUCCESS struct i2c_info { I2C_TypeDef *i2c; @@ -148,57 +149,83 @@ i2c_setup(uint32_t bus, uint32_t rate, uint8_t addr) gpio_peripheral(ii->sda_pin, ii->function | GPIO_OPEN_DRAIN, 1); // Set 100Khz frequency and enable - i2c->TIMINGR = ((0xB << I2C_TIMINGR_PRESC_Pos) - | (0x13 << I2C_TIMINGR_SCLL_Pos) - | (0xF << I2C_TIMINGR_SCLH_Pos) - | (0x2 << I2C_TIMINGR_SDADEL_Pos) - | (0x4 << I2C_TIMINGR_SCLDEL_Pos)); + uint32_t nom_i2c_clock = 8000000; // 8mhz internal clock = 125ns ticks + uint32_t scll = 40; // 40 * 125ns = 5us + uint32_t sclh = 32; // 32 * 125ns = 4us + uint32_t sdadel = 4; // 4 * 125ns = 500ns + uint32_t scldel = 10; // 10 * 125ns = 1250ns + // Clamp the rate to 400Khz + if (rate >= 400000) { + scll = 10; // 10 * 125ns = 1250ns + sclh = 4; // 4 * 125 = 500ns + sdadel = 3; // 3 * 125 = 375ns + scldel = 4; // 4 * 125 = 500ns + } + + uint32_t pclk = get_pclock_frequency((uint32_t)i2c); + uint32_t presc = DIV_ROUND_UP(pclk, nom_i2c_clock); + i2c->TIMINGR = (((presc - 1) << I2C_TIMINGR_PRESC_Pos) + | ((scll - 1) << I2C_TIMINGR_SCLL_Pos) + | ((sclh - 1) << I2C_TIMINGR_SCLH_Pos) + | (sdadel << I2C_TIMINGR_SDADEL_Pos) + | ((scldel - 1) << I2C_TIMINGR_SCLDEL_Pos)); i2c->CR1 = I2C_CR1_PE; } return (struct i2c_config){ .i2c=i2c, .addr=addr<<1 }; } -static uint32_t +static int i2c_wait(I2C_TypeDef *i2c, uint32_t set, uint32_t timeout) { for (;;) { uint32_t isr = i2c->ISR; if (isr & set) - return isr; + return I2C_BUS_SUCCESS; + if (isr & I2C_ISR_NACKF) + return I2C_BUS_NACK; if (!timer_is_before(timer_read_time(), timeout)) - shutdown("i2c timeout"); + return I2C_BUS_TIMEOUT; } } -void +int i2c_write(struct i2c_config config, uint8_t write_len, uint8_t *write) { I2C_TypeDef *i2c = config.i2c; uint32_t timeout = timer_read_time() + timer_from_us(5000); + int ret = I2C_BUS_SUCCESS; // Send start and address i2c->CR2 = (I2C_CR2_START | config.addr | (write_len << I2C_CR2_NBYTES_Pos) | I2C_CR2_AUTOEND); while (write_len--) { - i2c_wait(i2c, I2C_ISR_TXIS, timeout); + ret = i2c_wait(i2c, I2C_ISR_TXIS, timeout); + if (ret != I2C_BUS_SUCCESS) + goto abrt; i2c->TXDR = *write++; } - i2c_wait(i2c, I2C_ISR_TXE, timeout); + return i2c_wait(i2c, I2C_ISR_TXE, timeout); +abrt: + i2c->CR2 |= I2C_CR2_STOP; + return ret; } -void +int i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg , uint8_t read_len, uint8_t *read) { I2C_TypeDef *i2c = config.i2c; uint32_t timeout = timer_read_time() + timer_from_us(5000); + int ret = I2C_BUS_SUCCESS; // Send start, address, reg i2c->CR2 = (I2C_CR2_START | config.addr | (reg_len << I2C_CR2_NBYTES_Pos)); while (reg_len--) { - i2c_wait(i2c, I2C_ISR_TXIS, timeout); + ret = i2c_wait(i2c, I2C_ISR_TXIS, timeout); + if (ret != I2C_BUS_SUCCESS) + goto abrt; i2c->TXDR = *reg++; } i2c_wait(i2c, I2C_ISR_TC, timeout); @@ -207,8 +234,13 @@ i2c_read(struct i2c_config config, uint8_t reg_len, uint8_t *reg i2c->CR2 = (I2C_CR2_START | I2C_CR2_RD_WRN | config.addr | (read_len << I2C_CR2_NBYTES_Pos) | I2C_CR2_AUTOEND); while (read_len--) { - i2c_wait(i2c, I2C_ISR_RXNE, timeout); + ret = i2c_wait(i2c, I2C_ISR_RXNE, timeout); + if (ret != I2C_BUS_SUCCESS) + goto abrt; *read++ = i2c->RXDR; } - i2c_wait(i2c, I2C_ISR_STOPF, timeout); + return i2c_wait(i2c, I2C_ISR_STOPF, timeout); +abrt: + i2c->CR2 |= I2C_CR2_STOP; + return ret; } diff --git a/src/stm32/stm32f0_serial.c b/src/stm32/stm32f0_serial.c index c987f149e561..964601b68b75 100644 --- a/src/stm32/stm32f0_serial.c +++ b/src/stm32/stm32f0_serial.c @@ -71,6 +71,14 @@ #define USARTx_FUNCTION GPIO_FUNCTION(CONFIG_MACH_STM32G0 ? 0 : 7) #define USARTx USART3 #define USARTx_IRQn USART3_IRQn +#elif CONFIG_STM32_SERIAL_USART3_ALT_PC11_PC10 + // Currently only supports STM32G474. + DECL_CONSTANT_STR("RESERVE_PINS_serial", "PC11,PC10"); + #define GPIO_Rx GPIO('C', 11) + #define GPIO_Tx GPIO('C', 10) + #define USARTx_FUNCTION GPIO_FUNCTION(7) + #define USARTx USART3 + #define USARTx_IRQn USART3_IRQn #elif CONFIG_STM32_SERIAL_UART4 DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA1,PA0"); #define GPIO_Rx GPIO('A', 1) diff --git a/src/stm32/stm32g4.c b/src/stm32/stm32g4.c index 1eed3ec188d6..6d6d1c0d3a81 100644 --- a/src/stm32/stm32g4.c +++ b/src/stm32/stm32g4.c @@ -12,7 +12,7 @@ #include "internal.h" // enable_pclock #include "sched.h" // sched_main -#define FREQ_PERIPH_DIV 1 +#define FREQ_PERIPH_DIV 2 #define FREQ_PERIPH (CONFIG_CLOCK_FREQ / FREQ_PERIPH_DIV) // Map a peripheral address to its enable bits @@ -104,7 +104,7 @@ enable_clock_stm32g4(void) RCC->CR |= RCC_CR_PLLON; // Enable 48Mhz USB clock using clock recovery - if (CONFIG_USBSERIAL) { + if (CONFIG_USB) { RCC->CRRCR |= RCC_CRRCR_HSI48ON; while (!(RCC->CRRCR & RCC_CRRCR_HSI48RDY)) ; @@ -142,7 +142,7 @@ clock_setup(void) RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN; // Switch system clock to PLL - RCC->CFGR = RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV1 | RCC_CFGR_PPRE2_DIV1 + RCC->CFGR = RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_SW_PLL; while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) ; diff --git a/src/stm32/stm32h7_adc.c b/src/stm32/stm32h7_adc.c index 3c217ca273c6..6740edd3e1ab 100644 --- a/src/stm32/stm32h7_adc.c +++ b/src/stm32/stm32h7_adc.c @@ -12,6 +12,8 @@ #include "internal.h" // GPIO #include "sched.h" // sched_shutdown +#define ADC_INVALID_PIN 0xFF + #define ADC_TEMPERATURE_PIN 0xfe DECL_ENUMERATION("pin", "ADC_TEMPERATURE", ADC_TEMPERATURE_PIN); @@ -24,8 +26,8 @@ DECL_CONSTANT("ADC_MAX", 4095); static const uint8_t adc_pins[] = { #if CONFIG_MACH_STM32H7 // ADC1 - 0, // PA0_C ADC12_INP0 - 0, // PA1_C ADC12_INP1 + ADC_INVALID_PIN, // PA0_C ADC12_INP0 + ADC_INVALID_PIN, // PA1_C ADC12_INP1 GPIO('F', 11), // ADC1_INP2 GPIO('A', 6), // ADC12_INP3 GPIO('C', 4), // ADC12_INP4 @@ -45,8 +47,8 @@ static const uint8_t adc_pins[] = { GPIO('A', 4), // ADC12_INP18 GPIO('A', 5), // ADC12_INP19 // ADC2 - 0, // PA0_C ADC12_INP0 - 0, // PA1_C ADC12_INP1 + ADC_INVALID_PIN, // PA0_C ADC12_INP0 + ADC_INVALID_PIN, // PA1_C ADC12_INP1 GPIO('F', 13), // ADC2_INP2 GPIO('A', 6), // ADC12_INP3 GPIO('C', 4), // ADC12_INP4 @@ -61,13 +63,13 @@ static const uint8_t adc_pins[] = { GPIO('C', 3), // ADC12_INP13 GPIO('A', 2), // ADC12_INP14 GPIO('A', 3), // ADC12_INP15 - 0, // dac_out1 - 0, // dac_out2 + ADC_INVALID_PIN, // dac_out1 + ADC_INVALID_PIN, // dac_out2 GPIO('A', 4), // ADC12_INP18 GPIO('A', 5), // ADC12_INP19 // ADC3 - 0, // PC2_C ADC3_INP0 - 0, // PC3_C ADC3_INP1 + ADC_INVALID_PIN, // PC2_C ADC3_INP0 + ADC_INVALID_PIN, // PC3_C ADC3_INP1 GPIO('F', 9) , // ADC3_INP2 GPIO('F', 7), // ADC3_INP3 GPIO('F', 5), // ADC3_INP4 @@ -85,14 +87,14 @@ static const uint8_t adc_pins[] = { GPIO('H', 5), // ADC3_INP16 #if CONFIG_MACH_STM32H723 ADC_TEMPERATURE_PIN, - 0, + ADC_INVALID_PIN, #else - 0, // Vbat/4 + ADC_INVALID_PIN, // Vbat/4 ADC_TEMPERATURE_PIN,// VSENSE #endif - 0, // VREFINT + ADC_INVALID_PIN, // VREFINT #elif CONFIG_MACH_STM32G4 - 0, // [0] vssa + ADC_INVALID_PIN, // [0] vssa GPIO('A', 0), // [1] GPIO('A', 1), // [2] GPIO('A', 2), // [3] @@ -105,14 +107,14 @@ static const uint8_t adc_pins[] = { GPIO('F', 0), // [10] GPIO('B', 12), // [11] GPIO('B', 1), // [12] - 0, // [13] opamp + ADC_INVALID_PIN, // [13] opamp GPIO('B', 11), // [14] GPIO('B', 0), // [15] ADC_TEMPERATURE_PIN, // [16] vtemp - 0, // [17] vbat/3 - 0, // [18] vref - 0, - 0, // [0] vssa ADC 2 + ADC_INVALID_PIN, // [17] vbat/3 + ADC_INVALID_PIN, // [18] vref + ADC_INVALID_PIN, + ADC_INVALID_PIN, // [0] vssa ADC 2 GPIO('A', 0), // [1] GPIO('A', 1), // [2] GPIO('A', 6), // [3] @@ -128,11 +130,11 @@ static const uint8_t adc_pins[] = { GPIO('A', 5), // [13] GPIO('B', 11), // [14] GPIO('B', 15), // [15] - 0, // [16] opamp + ADC_INVALID_PIN, // [16] opamp GPIO('A', 4), // [17] - 0, // [18] opamp + ADC_INVALID_PIN, // [18] opamp #else // stm32l4 - 0, // vref + ADC_INVALID_PIN, // vref GPIO('C', 0), // ADC12_IN1 .. 16 GPIO('C', 1), GPIO('C', 2), @@ -150,7 +152,7 @@ static const uint8_t adc_pins[] = { GPIO('B', 0), GPIO('B', 1), ADC_TEMPERATURE_PIN, // temp - 0, // vbat + ADC_INVALID_PIN, // vbat #endif }; diff --git a/src/stm32/stm32l4.c b/src/stm32/stm32l4.c index 7db15fff0ba2..ae099d6bc6a5 100644 --- a/src/stm32/stm32l4.c +++ b/src/stm32/stm32l4.c @@ -96,7 +96,7 @@ enable_clock_stm32l4(void) RCC->CR |= RCC_CR_PLLON; // Enable 48Mhz USB clock using clock recovery - if (CONFIG_USBSERIAL) { + if (CONFIG_USB) { RCC->CRRCR |= RCC_CRRCR_HSI48ON; while (!(RCC->CRRCR & RCC_CRRCR_HSI48RDY)) ; diff --git a/src/trsync.c b/src/trsync.c index 3bf7aa669afd..5625280a6b71 100644 --- a/src/trsync.c +++ b/src/trsync.c @@ -1,6 +1,6 @@ // Handling of synchronized "trigger" dispatch // -// Copyright (C) 2016-2021 Kevin O'Connor +// Copyright (C) 2016-2024 Kevin O'Connor // // This file may be distributed under the terms of the GNU GPLv3 license. @@ -23,13 +23,14 @@ enum { TSF_CAN_TRIGGER=1<<0, TSF_REPORT=1<<2 }; static struct task_wake trsync_wake; -// Activate a trigger (caller must disable IRQs) +// Activate a trigger void trsync_do_trigger(struct trsync *ts, uint8_t reason) { + irqstatus_t flag = irq_save(); uint8_t flags = ts->flags; if (!(flags & TSF_CAN_TRIGGER)) - return; + goto done; ts->trigger_reason = reason; ts->flags = (flags & ~TSF_CAN_TRIGGER) | TSF_REPORT; // Dispatch signals @@ -42,6 +43,8 @@ trsync_do_trigger(struct trsync *ts, uint8_t reason) func(tss, reason); } sched_wake_task(&trsync_wake); +done: + irq_restore(flag); } // Timeout handler diff --git a/test/configs/ar100.config b/test/configs/ar100.config index 6c9174824b5e..a1335176fb78 100644 --- a/test/configs/ar100.config +++ b/test/configs/ar100.config @@ -4,3 +4,5 @@ CONFIG_WANT_DISPLAYS=n CONFIG_WANT_SOFTWARE_I2C=n CONFIG_WANT_SOFTWARE_SPI=n CONFIG_WANT_LIS2DW=n +CONFIG_WANT_HX71X=n +CONFIG_WANT_ADS1220=n diff --git a/test/configs/rp2040.config b/test/configs/rp2040.config index 51fc122802c0..ed594e04deac 100644 --- a/test/configs/rp2040.config +++ b/test/configs/rp2040.config @@ -1,2 +1,2 @@ # Base config file for rp2040 boards -CONFIG_MACH_RP2040=y +CONFIG_MACH_RPXXXX=y diff --git a/test/configs/stm32f042.config b/test/configs/stm32f042.config index 12cc0922e45e..53cf1281e80b 100644 --- a/test/configs/stm32f042.config +++ b/test/configs/stm32f042.config @@ -4,3 +4,5 @@ CONFIG_MACH_STM32F042=y CONFIG_WANT_SOFTWARE_I2C=n CONFIG_WANT_LIS2DW=n CONFIG_WANT_LDC1612=n +CONFIG_WANT_HX71X=n +CONFIG_WANT_ADS1220=n diff --git a/test/klippy/dual_carriage.cfg b/test/klippy/dual_carriage.cfg index 9ae01c2bc1be..93c5744404f1 100644 --- a/test/klippy/dual_carriage.cfg +++ b/test/klippy/dual_carriage.cfg @@ -61,7 +61,7 @@ pid_Kd: 114 min_temp: 0 max_temp: 250 -[gcode_macro PARK_extruder0] +[gcode_macro PARK_extruder] gcode: G90 G1 X0 diff --git a/test/klippy/dual_carriage.test b/test/klippy/dual_carriage.test index 5b2f9e65d3ed..ed40c236e5b5 100644 --- a/test/klippy/dual_carriage.test +++ b/test/klippy/dual_carriage.test @@ -17,6 +17,18 @@ G1 X190 F6000 SET_DUAL_CARRIAGE CARRIAGE=0 G1 X20 F6000 +# Save dual carriage state +SAVE_DUAL_CARRIAGE_STATE + +G1 X50 F6000 + +# Go back to alternate carriage +SET_DUAL_CARRIAGE CARRIAGE=1 +G1 X170 F6000 + +# Restore dual carriage state +RESTORE_DUAL_CARRIAGE_STATE + # Test changing extruders G1 X5 T1 diff --git a/test/klippy/load_cell.cfg b/test/klippy/load_cell.cfg new file mode 100644 index 000000000000..fa599d10e366 --- /dev/null +++ b/test/klippy/load_cell.cfg @@ -0,0 +1,23 @@ +# Test config for load_cell +[mcu] +serial: /dev/ttyACM0 + +[printer] +kinematics: none +max_velocity: 300 +max_accel: 3000 + +[load_cell my_ads1220] +sensor_type: ads1220 +cs_pin: PA0 +data_ready_pin: PA1 + +[load_cell my_hx711] +sensor_type: hx711 +sclk_pin: PA2 +dout_pin: PA3 + +[load_cell my_hx717] +sensor_type: hx717 +sclk_pin: PA4 +dout_pin: PA5 diff --git a/test/klippy/load_cell.test b/test/klippy/load_cell.test new file mode 100644 index 000000000000..880f840aa388 --- /dev/null +++ b/test/klippy/load_cell.test @@ -0,0 +1,5 @@ +# Tests for loadcell sensors +DICTIONARY atmega2560.dict +CONFIG load_cell.cfg + +G4 P1000 diff --git a/test/klippy/printers.test b/test/klippy/printers.test index 9f7ab3c20f38..40a6118c0eeb 100644 --- a/test/klippy/printers.test +++ b/test/klippy/printers.test @@ -224,6 +224,7 @@ CONFIG ../../config/generic-bigtreetech-skr-2.cfg CONFIG ../../config/generic-flyboard.cfg CONFIG ../../config/generic-I3DBEEZ9.cfg CONFIG ../../config/generic-mellow-fly-cdy-v3.cfg +CONFIG ../../config/generic-mellow-fly-e3-v2.cfg CONFIG ../../config/generic-mellow-super-infinty-hv.cfg CONFIG ../../config/generic-mks-monster8.cfg CONFIG ../../config/generic-mks-robin-nano-v3.cfg