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KCU105_Rev1.0_02292016.xdc
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KCU105_Rev1.0_02292016.xdc
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#
# KCU105 RevD XDC
#
#Other net PACKAGE_PIN Y11 - SYSMON_DXN Bank 0 - DXN
#Other net PACKAGE_PIN U12 - SYSMON_VCC Bank 0 - VCCADC
#Other net PACKAGE_PIN U11 - SYSMON_AGND Bank 0 - GNDADC
#Other net PACKAGE_PIN Y12 - SYSMON_DXP Bank 0 - DXP
#Other net PACKAGE_PIN W12 - SYSMON_VREFP Bank 0 - VREFP
#Other net PACKAGE_PIN V11 - SYSMON_AGND Bank 0 - VREFN
#Other net PACKAGE_PIN V12 - SYSMON_VP_R Bank 0 - VP
#Other net PACKAGE_PIN W11 - SYSMON_VN_R Bank 0 - VN
#Other net PACKAGE_PIN K7 - 3N5500 Bank 0 - M0_0
#Other net PACKAGE_PIN L7 - 3N5497 Bank 0 - M1_0
#Other net PACKAGE_PIN V7 - FPGA_INIT_B Bank 0 - INIT_B_0
#Other net PACKAGE_PIN M7 - FPGA_M2 Bank 0 - M2_0
#Other net PACKAGE_PIN W7 - GND Bank 0 - CFGBVS_0
#Other net PACKAGE_PIN R7 - 3N2787 Bank 0 - PUDC_B_0
#Other net PACKAGE_PIN P7 - 3N3559 Bank 0 - POR_OVERRIDE
#Other net PACKAGE_PIN N7 - FPGA_DONE Bank 0 - DONE_0
#Other net PACKAGE_PIN T7 - FPGA_PROG_B Bank 0 - PROGRAM_B_0
#Other net PACKAGE_PIN U9 - FPGA_TDO_FMC_TDI Bank 0 - TDO_0
#Other net PACKAGE_PIN V9 - JTAG_TDI_FPGA_BUF Bank 0 - TDI_0
#Other net PACKAGE_PIN U7 - QSPI0_CS_B Bank 0 - RDWR_FCS_B_0
#Other net PACKAGE_PIN AA7 - QSPI0_IO2 Bank 0 - D02_0
#Other net PACKAGE_PIN AC7 - QSPI0_IO0 Bank 0 - D00_MOSI_0
#Other net PACKAGE_PIN Y7 - QSPI0_IO3 Bank 0 - D03_0
#Other net PACKAGE_PIN AB7 - QSPI0_IO1 Bank 0 - D01_DIN_0
#Other net PACKAGE_PIN W9 - FPGA_TMS_BUF Bank 0 - TMS_0
#Other net PACKAGE_PIN AA9 - FPGA_CCLK Bank 0 - CCLK_0
#Other net PACKAGE_PIN AC9 - FPGA_TCK_BUF Bank 0 - TCK_0
#Other net PACKAGE_PIN AD7 - FPGA_VBATT Bank 0 - VBATT
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L24P_T3U_N10_44
set_property PACKAGE_PIN AN23 [get_ports "DDR4_DQ25"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ25"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L24N_T3U_N11_44
set_property PACKAGE_PIN AP23 [get_ports "DDR4_DQ27"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ27"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_T3U_N12_44
set_property PACKAGE_PIN AM25 [get_ports "4N6824"]
set_property IOSTANDARD LVCMOSxx [get_ports "4N6824"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L23P_T3U_N8_44
set_property PACKAGE_PIN AP24 [get_ports "DDR4_DQ30"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ30"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L23N_T3U_N9_44
set_property PACKAGE_PIN AP25 [get_ports "DDR4_DQ28"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ28"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L22P_T3U_N6_DBC_AD0P_44
set_property PACKAGE_PIN AP20 [get_ports "DDR4_DQS3_T"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS3_T"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L22N_T3U_N7_DBC_AD0N_44
set_property PACKAGE_PIN AP21 [get_ports "DDR4_DQS3_C"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS3_C"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L21P_T3L_N4_AD8P_44
set_property PACKAGE_PIN AM24 [get_ports "DDR4_DQ24"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ24"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L21N_T3L_N5_AD8N_44
set_property PACKAGE_PIN AN24 [get_ports "DDR4_DQ26"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ26"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L20P_T3L_N2_AD1P_44
set_property PACKAGE_PIN AM22 [get_ports "DDR4_DQ31"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ31"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L20N_T3L_N3_AD1N_44
set_property PACKAGE_PIN AN22 [get_ports "DDR4_DQ29"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ29"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L19P_T3L_N0_DBC_AD9P_44
set_property PACKAGE_PIN AM21 [get_ports "DDR4_DM3"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM3"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L19N_T3L_N1_DBC_AD9N_44
set_property PACKAGE_PIN AN21 [get_ports "PMOD0_1_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_1_LS"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L18P_T2U_N10_AD2P_44
set_property PACKAGE_PIN AL24 [get_ports "DDR4_DQ21"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ21"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L18N_T2U_N11_AD2N_44
set_property PACKAGE_PIN AL25 [get_ports "DDR4_DQ17"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ17"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L17P_T2U_N8_AD10P_44
set_property PACKAGE_PIN AL22 [get_ports "DDR4_DQ16"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ16"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L17N_T2U_N9_AD10N_44
set_property PACKAGE_PIN AL23 [get_ports "DDR4_DQ23"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ23"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L16P_T2U_N6_QBC_AD3P_44
set_property PACKAGE_PIN AJ20 [get_ports "DDR4_DQS2_T"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS2_T"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L16N_T2U_N7_QBC_AD3N_44
set_property PACKAGE_PIN AK20 [get_ports "DDR4_DQS2_C"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS2_C"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L15P_T2L_N4_AD11P_44
set_property PACKAGE_PIN AL20 [get_ports "DDR4_DQ22"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ22"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L15N_T2L_N5_AD11N_44
set_property PACKAGE_PIN AM20 [get_ports "DDR4_DQ18"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ18"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L14P_T2L_N2_GC_44
set_property PACKAGE_PIN AK22 [get_ports "DDR4_DQ20"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ20"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L14N_T2L_N3_GC_44
set_property PACKAGE_PIN AK23 [get_ports "DDR4_DQ19"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ19"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_T2U_N12_44
set_property PACKAGE_PIN AK25 [get_ports "PMOD0_0_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_0_LS"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L13P_T2L_N0_GC_QBC_44
set_property PACKAGE_PIN AJ21 [get_ports "DDR4_DM2"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM2"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L13N_T2L_N1_GC_QBC_44
set_property PACKAGE_PIN AK21 [get_ports "4N7226"]
set_property IOSTANDARD LVCMOSxx [get_ports "4N7226"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L12P_T1U_N10_GC_44
set_property PACKAGE_PIN AH22 [get_ports "DDR4_DQ14"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ14"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L12N_T1U_N11_GC_44
set_property PACKAGE_PIN AH23 [get_ports "DDR4_DQ12"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ12"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_T1U_N12_VRP_44
set_property PACKAGE_PIN AF25 [get_ports "PMOD0_5_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_5_LS"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L11P_T1U_N8_GC_44
set_property PACKAGE_PIN AJ23 [get_ports "DDR4_DQ10"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ10"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L11N_T1U_N9_GC_44
set_property PACKAGE_PIN AJ24 [get_ports "DDR4_DQ8"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ8"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L10P_T1U_N6_QBC_AD4P_44
set_property PACKAGE_PIN AH24 [get_ports "DDR4_DQS1_T"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS1_T"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L10N_T1U_N7_QBC_AD4N_44
set_property PACKAGE_PIN AJ25 [get_ports "DDR4_DQS1_C"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS1_C"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L9P_T1L_N4_AD12P_44
set_property PACKAGE_PIN AG24 [get_ports "DDR4_DQ9"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ9"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L9N_T1L_N5_AD12N_44
set_property PACKAGE_PIN AG25 [get_ports "DDR4_DQ15"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ15"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L8P_T1L_N2_AD5P_44
set_property PACKAGE_PIN AF23 [get_ports "DDR4_DQ11"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ11"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L8N_T1L_N3_AD5N_44
set_property PACKAGE_PIN AF24 [get_ports "DDR4_DQ13"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ13"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L7P_T1L_N0_QBC_AD13P_44
set_property PACKAGE_PIN AE25 [get_ports "DDR4_DM1"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM1"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L7N_T1L_N1_QBC_AD13N_44
set_property PACKAGE_PIN AE26 [get_ports "PMOD0_4_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_4_LS"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L6P_T0U_N10_AD6P_44
set_property PACKAGE_PIN AF22 [get_ports "DDR4_DQ2"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ2"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L6N_T0U_N11_AD6N_44
set_property PACKAGE_PIN AG22 [get_ports "DDR4_DQ6"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ6"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L5P_T0U_N8_AD14P_44
set_property PACKAGE_PIN AE22 [get_ports "DDR4_DQ4"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ4"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L5N_T0U_N9_AD14N_44
set_property PACKAGE_PIN AE23 [get_ports "DDR4_DQ0"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ0"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L4P_T0U_N6_DBC_AD7P_44
set_property PACKAGE_PIN AG21 [get_ports "DDR4_DQS0_T"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS0_T"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L4N_T0U_N7_DBC_AD7N_44
set_property PACKAGE_PIN AH21 [get_ports "DDR4_DQS0_C"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS0_C"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L3P_T0L_N4_AD15P_44
set_property PACKAGE_PIN AD20 [get_ports "DDR4_DQ5"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ5"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L3N_T0L_N5_AD15N_44
set_property PACKAGE_PIN AE20 [get_ports "DDR4_DQ7"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ7"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L2P_T0L_N2_44
set_property PACKAGE_PIN AF20 [get_ports "DDR4_DQ3"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ3"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L2N_T0L_N3_44
set_property PACKAGE_PIN AG20 [get_ports "DDR4_DQ1"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ1"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_T0U_N12_44
set_property PACKAGE_PIN AD24 [get_ports "VRP_44"]
set_property IOSTANDARD LVCMOSxx [get_ports "VRP_44"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L1P_T0L_N0_DBC_44
set_property PACKAGE_PIN AD21 [get_ports "DDR4_DM0"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM0"]
# Bank 44 VCCO - VCC1V2_FPGA_3A - IO_L1N_T0L_N1_DBC_44
set_property PACKAGE_PIN AE21 [get_ports "PMOD0_6_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_6_LS"]
#Other net PACKAGE_PIN AD23 - 4N6160 Bank 44 - VREF_44
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L24P_T3U_N10_45
set_property PACKAGE_PIN AD16 [get_ports "DDR4_A14_WE_B"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A14_WE_B"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L24N_T3U_N11_45
set_property PACKAGE_PIN AD15 [get_ports "DDR4_CKE"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_CKE"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_T3U_N12_45
set_property PACKAGE_PIN AD14 [get_ports "4N6835"]
set_property IOSTANDARD LVCMOSxx [get_ports "4N6835"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L23P_T3U_N8_45
set_property PACKAGE_PIN AE17 [get_ports "DDR4_A0"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A0"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L23N_T3U_N9_45
set_property PACKAGE_PIN AF17 [get_ports "DDR4_BA0"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BA0"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L22P_T3U_N6_DBC_AD0P_45
set_property PACKAGE_PIN AE16 [get_ports "DDR4_CK_T"]
set_property IOSTANDARD DIFF_SSTL2_DCI [get_ports "DDR4_CK_T"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L22N_T3U_N7_DBC_AD0N_45
set_property PACKAGE_PIN AE15 [get_ports "DDR4_CK_C"]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "DDR4_CK_C"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L21P_T3L_N4_AD8P_45
set_property PACKAGE_PIN AE18 [get_ports "DDR4_A2"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A2"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L21N_T3L_N5_AD8N_45
set_property PACKAGE_PIN AF18 [get_ports "DDR4_A8"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A8"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L20P_T3L_N2_AD1P_45
set_property PACKAGE_PIN AF15 [get_ports "DDR4_A10"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A10"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L20N_T3L_N3_AD1N_45
set_property PACKAGE_PIN AF14 [get_ports "DDR4_A16_RAS_B"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A16_RAS_B"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L19P_T3L_N0_DBC_AD9P_45
set_property PACKAGE_PIN AD19 [get_ports "DDR4_A11"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A11"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L19N_T3L_N1_DBC_AD9N_45
set_property PACKAGE_PIN AD18 [get_ports "DDR4_PAR"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_PAR"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L18P_T2U_N10_AD2P_45
set_property PACKAGE_PIN AG15 [get_ports "DDR4_BG0"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BG0"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L18N_T2U_N11_AD2N_45
set_property PACKAGE_PIN AG14 [get_ports "DDR4_A15_CAS_B"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A15_CAS_B"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L17P_T2U_N8_AD10P_45
set_property PACKAGE_PIN AG19 [get_ports "DDR4_A13"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A13"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L17N_T2U_N9_AD10N_45
set_property PACKAGE_PIN AH19 [get_ports "DDR4_A9"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A9"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L16P_T2U_N6_QBC_AD3P_45
set_property PACKAGE_PIN AJ15 [get_ports "DDR4_A3"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A3"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L16N_T2U_N7_QBC_AD3N_45
set_property PACKAGE_PIN AJ14 [get_ports "DDR4_A12"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A12"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L15P_T2L_N4_AD11P_45
set_property PACKAGE_PIN AG17 [get_ports "DDR4_A7"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A7"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L15N_T2L_N5_AD11N_45
set_property PACKAGE_PIN AG16 [get_ports "DDR4_A4"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A4"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L14P_T2L_N2_GC_45
set_property PACKAGE_PIN AH16 [get_ports "DDR4_TEN"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_TEN"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L14N_T2L_N3_GC_45
set_property PACKAGE_PIN AJ16 [get_ports "DDR4_ALERT_B"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ALERT_B"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_T2U_N12_45
set_property PACKAGE_PIN AH14 [get_ports "DDR4_ACT_B"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ACT_B"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L13P_T2L_N0_GC_QBC_45
set_property PACKAGE_PIN AH18 [get_ports "PMOD0_2_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_2_LS"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L13N_T2L_N1_GC_QBC_45
set_property PACKAGE_PIN AH17 [get_ports "DDR4_A1"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A1"]
#
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L12P_T1U_N10_GC_45
set_property PACKAGE_PIN AK17 [get_ports "SYSCLK_300_P"]
set_property IOSTANDARD DIFF_SSTL12 [get_ports "SYSCLK_300_P"]
set_property ODT RTT_48 [get_ports "SYSCLK_300_P"]
#
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L12N_T1U_N11_GC_45
set_property PACKAGE_PIN AK16 [get_ports "SYSCLK_300_N"]
set_property IOSTANDARD DIFF_SSTL12 [get_ports "SYSCLK_300_N"]
set_property ODT RTT_48 [get_ports "SYSCLK_300_N"]
#
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_T1U_N12_VRP_45
set_property PACKAGE_PIN AJ19 [get_ports "4N8047"]
set_property IOSTANDARD LVCMOSxx [get_ports "4N8047"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L11P_T1U_N8_GC_45
set_property PACKAGE_PIN AJ18 [get_ports "DDR4_ODT"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ODT"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L11N_T1U_N9_GC_45
set_property PACKAGE_PIN AK18 [get_ports "DDR4_A6"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A6"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L10P_T1U_N6_QBC_AD4P_45
set_property PACKAGE_PIN AL18 [get_ports "DDR4_RESET_B"]
set_property IOSTANDARD LVCMOS12 [get_ports "DDR4_RESET_B"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L10N_T1U_N7_QBC_AD4N_45
set_property PACKAGE_PIN AL17 [get_ports "DDR4_A5"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A5"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L9P_T1L_N4_AD12P_45
set_property PACKAGE_PIN AK15 [get_ports "4N6914"]
set_property IOSTANDARD LVCMOSxx [get_ports "4N6914"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L9N_T1L_N5_AD12N_45
set_property PACKAGE_PIN AL15 [get_ports "DDR4_BA1"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BA1"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L8P_T1L_N2_AD5P_45
set_property PACKAGE_PIN AL19 [get_ports "DDR4_CS_B"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_CS_B"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L8N_T1L_N3_AD5N_45
set_property PACKAGE_PIN AM19 [get_ports "PMOD0_3_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_3_LS"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L7P_T1L_N0_QBC_AD13P_45
set_property PACKAGE_PIN AL14 [get_ports "PMOD1_0_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_0_LS"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L7N_T1L_N1_QBC_AD13N_45
set_property PACKAGE_PIN AM14 [get_ports "PMOD1_1_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_1_LS"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L6P_T0U_N10_AD6P_45
set_property PACKAGE_PIN AP16 [get_ports "PMOD1_2_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_2_LS"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L6N_T0U_N11_AD6N_45
set_property PACKAGE_PIN AP15 [get_ports "PMOD1_3_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_3_LS"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L5P_T0U_N8_AD14P_45
set_property PACKAGE_PIN AM16 [get_ports "PMOD1_4_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_4_LS"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L5N_T0U_N9_AD14N_45
set_property PACKAGE_PIN AM15 [get_ports "PMOD1_5_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_5_LS"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L4P_T0U_N6_DBC_AD7P_45
set_property PACKAGE_PIN AN18 [get_ports "PMOD1_6_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_6_LS"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L4N_T0U_N7_DBC_AD7N_45
set_property PACKAGE_PIN AN17 [get_ports "PMOD1_7_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD1_7_LS"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L3P_T0L_N4_AD15P_45
set_property PACKAGE_PIN AM17 [get_ports "PMOD0_7_LS"]
set_property IOSTANDARD LVCMOS12 [get_ports "PMOD0_7_LS"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L3N_T0L_N5_AD15N_45
set_property PACKAGE_PIN AN16 [get_ports "GPIO_DIP_SW0"]
set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW0"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L2P_T0L_N2_45
set_property PACKAGE_PIN AN19 [get_ports "GPIO_DIP_SW1"]
set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW1"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L2N_T0L_N3_45
set_property PACKAGE_PIN AP18 [get_ports "GPIO_DIP_SW2"]
set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW2"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_T0U_N12_45
set_property PACKAGE_PIN AP19 [get_ports "VRP_45"]
set_property IOSTANDARD LVCMOSxx [get_ports "VRP_45"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L1P_T0L_N0_DBC_45
set_property PACKAGE_PIN AN14 [get_ports "GPIO_DIP_SW3"]
set_property IOSTANDARD LVCMOS12 [get_ports "GPIO_DIP_SW3"]
# Bank 45 VCCO - VCC1V2_FPGA_3A - IO_L1N_T0L_N1_DBC_45
set_property PACKAGE_PIN AP14 [get_ports "4N7200"]
set_property IOSTANDARD LVCMOSxx [get_ports "4N7200"]
#Other net PACKAGE_PIN AF19 - 4N6273 Bank 45 - VREF_45
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L24P_T3U_N10_46
set_property PACKAGE_PIN AL34 [get_ports "DDR4_DQ62"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ62"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L24N_T3U_N11_46
set_property PACKAGE_PIN AM34 [get_ports "DDR4_DQ58"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ58"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_T3U_N12_46
set_property PACKAGE_PIN AK33 [get_ports "46N3480"]
set_property IOSTANDARD LVCMOSxx [get_ports "46N3480"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L23P_T3U_N8_46
set_property PACKAGE_PIN AM32 [get_ports "DDR4_DQ60"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ60"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L23N_T3U_N9_46
set_property PACKAGE_PIN AN32 [get_ports "DDR4_DQ63"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ63"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L22P_T3U_N6_DBC_AD0P_46
set_property PACKAGE_PIN AN34 [get_ports "DDR4_DQS7_T"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS7_T"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L22N_T3U_N7_DBC_AD0N_46
set_property PACKAGE_PIN AP34 [get_ports "DDR4_DQS7_C"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS7_C"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L21P_T3L_N4_AD8P_46
set_property PACKAGE_PIN AN31 [get_ports "DDR4_DQ61"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ61"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L21N_T3L_N5_AD8N_46
set_property PACKAGE_PIN AP31 [get_ports "DDR4_DQ59"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ59"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L20P_T3L_N2_AD1P_46
set_property PACKAGE_PIN AN33 [get_ports "DDR4_DQ56"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ56"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L20N_T3L_N3_AD1N_46
set_property PACKAGE_PIN AP33 [get_ports "DDR4_DQ57"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ57"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L19P_T3L_N0_DBC_AD9P_46
set_property PACKAGE_PIN AL32 [get_ports "DDR4_DM7"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM7"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L19N_T3L_N1_DBC_AD9N_46
set_property PACKAGE_PIN AL33 [get_ports "46N3671"]
set_property IOSTANDARD LVCMOSxx [get_ports "46N3671"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L18P_T2U_N10_AD2P_46
set_property PACKAGE_PIN AH34 [get_ports "DDR4_DQ54"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ54"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L18N_T2U_N11_AD2N_46
set_property PACKAGE_PIN AJ34 [get_ports "DDR4_DQ50"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ50"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L17P_T2U_N8_AD10P_46
set_property PACKAGE_PIN AH31 [get_ports "DDR4_DQ48"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ48"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L17N_T2U_N9_AD10N_46
set_property PACKAGE_PIN AH32 [get_ports "DDR4_DQ49"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ49"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L16P_T2U_N6_QBC_AD3P_46
set_property PACKAGE_PIN AH33 [get_ports "DDR4_DQS6_T"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS6_T"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L16N_T2U_N7_QBC_AD3N_46
set_property PACKAGE_PIN AJ33 [get_ports "DDR4_DQS6_C"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS6_C"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L15P_T2L_N4_AD11P_46
set_property PACKAGE_PIN AJ30 [get_ports "DDR4_DQ53"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ53"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L15N_T2L_N5_AD11N_46
set_property PACKAGE_PIN AJ31 [get_ports "DDR4_DQ52"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ52"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L14P_T2L_N2_GC_46
set_property PACKAGE_PIN AK31 [get_ports "DDR4_DQ51"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ51"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L14N_T2L_N3_GC_46
set_property PACKAGE_PIN AK32 [get_ports "DDR4_DQ55"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ55"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_T2U_N12_46
set_property PACKAGE_PIN AH29 [get_ports "46N4260"]
set_property IOSTANDARD LVCMOSxx [get_ports "46N4260"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L13P_T2L_N0_GC_QBC_46
set_property PACKAGE_PIN AJ29 [get_ports "DDR4_DM6"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM6"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L13N_T2L_N1_GC_QBC_46
set_property PACKAGE_PIN AK30 [get_ports "46N3668"]
set_property IOSTANDARD LVCMOSxx [get_ports "46N3668"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L12P_T1U_N10_GC_46
set_property PACKAGE_PIN AL30 [get_ports "DDR4_DQ40"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ40"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L12N_T1U_N11_GC_46
set_property PACKAGE_PIN AM30 [get_ports "DDR4_DQ42"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ42"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_T1U_N12_VRP_46
set_property PACKAGE_PIN AM31 [get_ports "46N4257"]
set_property IOSTANDARD LVCMOSxx [get_ports "46N4257"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L11P_T1U_N8_GC_46
set_property PACKAGE_PIN AL29 [get_ports "DDR4_DQ44"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ44"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L11N_T1U_N9_GC_46
set_property PACKAGE_PIN AM29 [get_ports "DDR4_DQ46"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ46"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L10P_T1U_N6_QBC_AD4P_46
set_property PACKAGE_PIN AN29 [get_ports "DDR4_DQS5_T"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS5_T"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L10N_T1U_N7_QBC_AD4N_46
set_property PACKAGE_PIN AP30 [get_ports "DDR4_DQS5_C"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS5_C"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L9P_T1L_N4_AD12P_46
set_property PACKAGE_PIN AN27 [get_ports "DDR4_DQ47"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ47"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L9N_T1L_N5_AD12N_46
set_property PACKAGE_PIN AN28 [get_ports "DDR4_DQ43"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ43"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L8P_T1L_N2_AD5P_46
set_property PACKAGE_PIN AP28 [get_ports "DDR4_DQ45"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ45"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L8N_T1L_N3_AD5N_46
set_property PACKAGE_PIN AP29 [get_ports "DDR4_DQ41"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ41"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L7P_T1L_N0_QBC_AD13P_46
set_property PACKAGE_PIN AN26 [get_ports "DDR4_DM5"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM5"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L7N_T1L_N1_QBC_AD13N_46
set_property PACKAGE_PIN AP26 [get_ports "46N3665"]
set_property IOSTANDARD LVCMOSxx [get_ports "46N3665"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L6P_T0U_N10_AD6P_46
set_property PACKAGE_PIN AJ28 [get_ports "DDR4_DQ36"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ36"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L6N_T0U_N11_AD6N_46
set_property PACKAGE_PIN AK28 [get_ports "DDR4_DQ34"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ34"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L5P_T0U_N8_AD14P_46
set_property PACKAGE_PIN AH27 [get_ports "DDR4_DQ37"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ37"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L5N_T0U_N9_AD14N_46
set_property PACKAGE_PIN AH28 [get_ports "DDR4_DQ32"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ32"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L4P_T0U_N6_DBC_AD7P_46
set_property PACKAGE_PIN AL27 [get_ports "DDR4_DQS4_T"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS4_T"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L4N_T0U_N7_DBC_AD7N_46
set_property PACKAGE_PIN AL28 [get_ports "DDR4_DQS4_C"]
set_property IOSTANDARD DIFF_POD12 [get_ports "DDR4_DQS4_C"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L3P_T0L_N4_AD15P_46
set_property PACKAGE_PIN AK26 [get_ports "DDR4_DQ33"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ33"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L3N_T0L_N5_AD15N_46
set_property PACKAGE_PIN AK27 [get_ports "DDR4_DQ38"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ38"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L2P_T0L_N2_46
set_property PACKAGE_PIN AM26 [get_ports "DDR4_DQ39"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ39"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L2N_T0L_N3_46
set_property PACKAGE_PIN AM27 [get_ports "DDR4_DQ35"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ35"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_T0U_N12_46
set_property PACKAGE_PIN AG26 [get_ports "VRP_46"]
set_property IOSTANDARD LVCMOSxx [get_ports "VRP_46"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L1P_T0L_N0_DBC_46
set_property PACKAGE_PIN AH26 [get_ports "DDR4_DM4"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM4"]
# Bank 46 VCCO - VCC1V2_FPGA_3A - IO_L1N_T0L_N1_DBC_46
set_property PACKAGE_PIN AJ26 [get_ports "46N3735"]
set_property IOSTANDARD LVCMOSxx [get_ports "46N3735"]
#Other net PACKAGE_PIN AG27 - 46N3019 Bank 46 - VREF_46
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L24P_T3U_N10_47
set_property PACKAGE_PIN V26 [get_ports "FMC_LPC_LA09_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA09_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L24N_T3U_N11_47
set_property PACKAGE_PIN W26 [get_ports "FMC_LPC_LA09_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA09_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_T3U_N12_47
set_property PACKAGE_PIN U29 [get_ports "5N3695"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N3695"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L23P_T3U_N8_47
set_property PACKAGE_PIN V29 [get_ports "FMC_LPC_LA06_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA06_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L23N_T3U_N9_47
set_property PACKAGE_PIN W29 [get_ports "FMC_LPC_LA06_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA06_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L22P_T3U_N6_DBC_AD0P_47
set_property PACKAGE_PIN U26 [get_ports "FMC_LPC_LA04_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA04_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L22N_T3U_N7_DBC_AD0N_47
set_property PACKAGE_PIN U27 [get_ports "FMC_LPC_LA04_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA04_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L21P_T3L_N4_AD8P_47
set_property PACKAGE_PIN W28 [get_ports "FMC_LPC_LA03_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA03_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L21N_T3L_N5_AD8N_47
set_property PACKAGE_PIN Y28 [get_ports "FMC_LPC_LA03_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA03_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L20P_T3L_N2_AD1P_47
set_property PACKAGE_PIN U24 [get_ports "FMC_LPC_LA08_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA08_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L20N_T3L_N3_AD1N_47
set_property PACKAGE_PIN U25 [get_ports "FMC_LPC_LA08_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA08_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L19P_T3L_N0_DBC_AD9P_47
set_property PACKAGE_PIN V27 [get_ports "FMC_LPC_LA05_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA05_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L19N_T3L_N1_DBC_AD9N_47
set_property PACKAGE_PIN V28 [get_ports "FMC_LPC_LA05_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA05_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L18P_T2U_N10_AD2P_47
set_property PACKAGE_PIN V21 [get_ports "FMC_LPC_LA11_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA11_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L18N_T2U_N11_AD2N_47
set_property PACKAGE_PIN W21 [get_ports "FMC_LPC_LA11_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA11_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L17P_T2U_N8_AD10P_47
set_property PACKAGE_PIN T22 [get_ports "FMC_LPC_LA10_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA10_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L17N_T2U_N9_AD10N_47
set_property PACKAGE_PIN T23 [get_ports "FMC_LPC_LA10_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA10_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L16P_T2U_N6_QBC_AD3P_47
set_property PACKAGE_PIN V22 [get_ports "FMC_LPC_LA07_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA07_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L16N_T2U_N7_QBC_AD3N_47
set_property PACKAGE_PIN V23 [get_ports "FMC_LPC_LA07_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA07_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L15P_T2L_N4_AD11P_47
set_property PACKAGE_PIN U21 [get_ports "FMC_LPC_LA14_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA14_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L15N_T2L_N5_AD11N_47
set_property PACKAGE_PIN U22 [get_ports "FMC_LPC_LA14_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA14_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L14P_T2L_N2_GC_47
set_property PACKAGE_PIN W25 [get_ports "FMC_LPC_LA01_CC_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA01_CC_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L14N_T2L_N3_GC_47
set_property PACKAGE_PIN Y25 [get_ports "FMC_LPC_LA01_CC_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA01_CC_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_T2U_N12_47
set_property PACKAGE_PIN Y21 [get_ports "ROTARY_INCA"]
set_property IOSTANDARD LVCMOS18 [get_ports "ROTARY_INCA"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L13P_T2L_N0_GC_QBC_47
set_property PACKAGE_PIN W23 [get_ports "FMC_LPC_LA00_CC_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA00_CC_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L13N_T2L_N1_GC_QBC_47
set_property PACKAGE_PIN W24 [get_ports "FMC_LPC_LA00_CC_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA00_CC_N"]
#
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L12P_T1U_N10_GC_47
set_property PACKAGE_PIN AA24 [get_ports "FMC_LPC_CLK0_M2C_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_CLK0_M2C_P"]
set_property DIFF_TERM TRUE [get_ports "FMC_LPC_CLK0_M2C_P"]
#
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L12N_T1U_N11_GC_47
set_property PACKAGE_PIN AA25 [get_ports "FMC_LPC_CLK0_M2C_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_CLK0_M2C_N"]
set_property DIFF_TERM TRUE [get_ports "FMC_LPC_CLK0_M2C_N"]
#
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_T1U_N12_VRP_47
set_property PACKAGE_PIN Y22 [get_ports "5N5033"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N5033"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L11P_T1U_N8_GC_47
set_property PACKAGE_PIN Y23 [get_ports "5N4122"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4122"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L11N_T1U_N9_GC_47
set_property PACKAGE_PIN AA23 [get_ports "5N4120"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4120"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L10P_T1U_N6_QBC_AD4P_47
set_property PACKAGE_PIN AB21 [get_ports "FMC_LPC_LA16_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA16_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L10N_T1U_N7_QBC_AD4N_47
set_property PACKAGE_PIN AC21 [get_ports "FMC_LPC_LA16_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA16_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L9P_T1L_N4_AD12P_47
set_property PACKAGE_PIN AA20 [get_ports "FMC_LPC_LA13_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA13_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L9N_T1L_N5_AD12N_47
set_property PACKAGE_PIN AB20 [get_ports "FMC_LPC_LA13_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA13_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L8P_T1L_N2_AD5P_47
set_property PACKAGE_PIN AC22 [get_ports "FMC_LPC_LA12_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA12_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L8N_T1L_N3_AD5N_47
set_property PACKAGE_PIN AC23 [get_ports "FMC_LPC_LA12_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA12_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L7P_T1L_N0_QBC_AD13P_47
set_property PACKAGE_PIN AA22 [get_ports "FMC_LPC_LA02_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA02_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L7N_T1L_N1_QBC_AD13N_47
set_property PACKAGE_PIN AB22 [get_ports "FMC_LPC_LA02_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA02_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L6P_T0U_N10_AD6P_47
set_property PACKAGE_PIN AB25 [get_ports "FMC_LPC_LA15_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA15_P"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L6N_T0U_N11_AD6N_47
set_property PACKAGE_PIN AB26 [get_ports "FMC_LPC_LA15_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA15_N"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L5P_T0U_N8_AD14P_47
set_property PACKAGE_PIN AA27 [get_ports "5N4116"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4116"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L5N_T0U_N9_AD14N_47
set_property PACKAGE_PIN AB27 [get_ports "5N4114"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4114"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L4P_T0U_N6_DBC_AD7P_47
set_property PACKAGE_PIN AC26 [get_ports "5N4109"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4109"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L4N_T0U_N7_DBC_AD7N_47
set_property PACKAGE_PIN AC27 [get_ports "5N4107"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4107"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L3P_T0L_N4_AD15P_47
set_property PACKAGE_PIN AB24 [get_ports "5N4105"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4105"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L3N_T0L_N5_AD15N_47
set_property PACKAGE_PIN AC24 [get_ports "5N4100"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4100"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L2P_T0L_N2_47
set_property PACKAGE_PIN AD25 [get_ports "5N4098"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4098"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L2N_T0L_N3_47
set_property PACKAGE_PIN AD26 [get_ports "ROTARY_INCB"]
set_property IOSTANDARD LVCMOS18 [get_ports "ROTARY_INCB"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_T0U_N12_47
set_property PACKAGE_PIN AA28 [get_ports "VRP_47"]
set_property IOSTANDARD LVCMOSxx [get_ports "VRP_47"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L1P_T0L_N0_DBC_47
set_property PACKAGE_PIN Y26 [get_ports "5N4093"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4093"]
# Bank 47 VCCO - VADJ_1V8_FPGA_10A - IO_L1N_T0L_N1_DBC_47
set_property PACKAGE_PIN Y27 [get_ports "5N4090"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4090"]
#Other net PACKAGE_PIN V24 - 5N4336 Bank 47 - VREF_47
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L24P_T3U_N10_48
set_property PACKAGE_PIN V31 [get_ports "FMC_LPC_LA28_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA28_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L24N_T3U_N11_48
set_property PACKAGE_PIN W31 [get_ports "FMC_LPC_LA28_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA28_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_T3U_N12_48
set_property PACKAGE_PIN V32 [get_ports "5N3527"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N3527"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L23P_T3U_N8_48
set_property PACKAGE_PIN U34 [get_ports "FMC_LPC_LA29_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA29_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L23N_T3U_N9_48
set_property PACKAGE_PIN V34 [get_ports "FMC_LPC_LA29_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA29_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L22P_T3U_N6_DBC_AD0P_48
set_property PACKAGE_PIN Y31 [get_ports "FMC_LPC_LA30_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA30_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L22N_T3U_N7_DBC_AD0N_48
set_property PACKAGE_PIN Y32 [get_ports "FMC_LPC_LA30_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA30_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L21P_T3L_N4_AD8P_48
set_property PACKAGE_PIN V33 [get_ports "FMC_LPC_LA31_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA31_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L21N_T3L_N5_AD8N_48
set_property PACKAGE_PIN W34 [get_ports "FMC_LPC_LA31_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA31_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L20P_T3L_N2_AD1P_48
set_property PACKAGE_PIN W30 [get_ports "FMC_LPC_LA32_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA32_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L20N_T3L_N3_AD1N_48
set_property PACKAGE_PIN Y30 [get_ports "FMC_LPC_LA32_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA32_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L19P_T3L_N0_DBC_AD9P_48
set_property PACKAGE_PIN W33 [get_ports "FMC_LPC_LA33_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA33_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L19N_T3L_N1_DBC_AD9N_48
set_property PACKAGE_PIN Y33 [get_ports "FMC_LPC_LA33_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA33_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L18P_T2U_N10_AD2P_48
set_property PACKAGE_PIN AC33 [get_ports "FMC_LPC_LA21_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA21_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L18N_T2U_N11_AD2N_48
set_property PACKAGE_PIN AD33 [get_ports "FMC_LPC_LA21_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA21_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L17P_T2U_N8_AD10P_48
set_property PACKAGE_PIN AA34 [get_ports "FMC_LPC_LA20_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA20_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L17N_T2U_N9_AD10N_48
set_property PACKAGE_PIN AB34 [get_ports "FMC_LPC_LA20_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA20_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L16P_T2U_N6_QBC_AD3P_48
set_property PACKAGE_PIN AA29 [get_ports "FMC_LPC_LA19_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA19_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L16N_T2U_N7_QBC_AD3N_48
set_property PACKAGE_PIN AB29 [get_ports "FMC_LPC_LA19_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA19_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L15P_T2L_N4_AD11P_48
set_property PACKAGE_PIN AC34 [get_ports "FMC_LPC_LA22_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA22_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L15N_T2L_N5_AD11N_48
set_property PACKAGE_PIN AD34 [get_ports "FMC_LPC_LA22_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA22_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L14P_T2L_N2_GC_48
set_property PACKAGE_PIN AB30 [get_ports "FMC_LPC_LA18_CC_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA18_CC_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L14N_T2L_N3_GC_48
set_property PACKAGE_PIN AB31 [get_ports "FMC_LPC_LA18_CC_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA18_CC_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_T2U_N12_48
set_property PACKAGE_PIN AA33 [get_ports "5N5055"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N5055"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L13P_T2L_N0_GC_QBC_48
set_property PACKAGE_PIN AA32 [get_ports "FMC_LPC_LA17_CC_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA17_CC_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L13N_T2L_N1_GC_QBC_48
set_property PACKAGE_PIN AB32 [get_ports "FMC_LPC_LA17_CC_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA17_CC_N"]
#
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L12P_T1U_N10_GC_48
set_property PACKAGE_PIN AC31 [get_ports "FMC_LPC_CLK1_M2C_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_CLK1_M2C_P"]
set_property DIFF_TERM TRUE [get_ports "FMC_LPC_CLK1_M2C_P"]
#
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L12N_T1U_N11_GC_48
set_property PACKAGE_PIN AC32 [get_ports "FMC_LPC_CLK1_M2C_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_CLK1_M2C_N"]
set_property DIFF_TERM TRUE [get_ports "FMC_LPC_CLK1_M2C_N"]
#
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_T1U_N12_VRP_48
set_property PACKAGE_PIN AE31 [get_ports "5N5047"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N5047"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L11P_T1U_N8_GC_48
set_property PACKAGE_PIN AD30 [get_ports "FMC_LPC_LA23_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA23_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L11N_T1U_N9_GC_48
set_property PACKAGE_PIN AD31 [get_ports "FMC_LPC_LA23_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA23_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L10P_T1U_N6_QBC_AD4P_48
set_property PACKAGE_PIN AE33 [get_ports "FMC_LPC_LA25_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA25_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L10N_T1U_N7_QBC_AD4N_48
set_property PACKAGE_PIN AF34 [get_ports "FMC_LPC_LA25_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA25_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L9P_T1L_N4_AD12P_48
set_property PACKAGE_PIN AE32 [get_ports "FMC_LPC_LA24_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA24_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L9N_T1L_N5_AD12N_48
set_property PACKAGE_PIN AF32 [get_ports "FMC_LPC_LA24_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA24_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L8P_T1L_N2_AD5P_48
set_property PACKAGE_PIN AF33 [get_ports "FMC_LPC_LA26_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA26_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L8N_T1L_N3_AD5N_48
set_property PACKAGE_PIN AG34 [get_ports "FMC_LPC_LA26_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA26_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L7P_T1L_N0_QBC_AD13P_48
set_property PACKAGE_PIN AG31 [get_ports "FMC_LPC_LA27_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA27_P"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L7N_T1L_N1_QBC_AD13N_48
set_property PACKAGE_PIN AG32 [get_ports "FMC_LPC_LA27_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_LPC_LA27_N"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L6P_T0U_N10_AD6P_48
set_property PACKAGE_PIN AF30 [get_ports "5N4159"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4159"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L6N_T0U_N11_AD6N_48
set_property PACKAGE_PIN AG30 [get_ports "5N4148"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4148"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L5P_T0U_N8_AD14P_48
set_property PACKAGE_PIN AD29 [get_ports "5N4146"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4146"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L5N_T0U_N9_AD14N_48
set_property PACKAGE_PIN AE30 [get_ports "5N4144"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4144"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L4P_T0U_N6_DBC_AD7P_48
set_property PACKAGE_PIN AF29 [get_ports "5N4139"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4139"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L4N_T0U_N7_DBC_AD7N_48
set_property PACKAGE_PIN AG29 [get_ports "5N4137"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4137"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L3P_T0L_N4_AD15P_48
set_property PACKAGE_PIN AC28 [get_ports "5N4135"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4135"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L3N_T0L_N5_AD15N_48
set_property PACKAGE_PIN AD28 [get_ports "5N4130"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4130"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L2P_T0L_N2_48
set_property PACKAGE_PIN AE28 [get_ports "5N4128"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4128"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L2N_T0L_N3_48
set_property PACKAGE_PIN AF28 [get_ports "ROTARY_PUSH"]
set_property IOSTANDARD LVCMOS18 [get_ports "ROTARY_PUSH"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_T0U_N12_48
set_property PACKAGE_PIN AC29 [get_ports "VRP_48"]
set_property IOSTANDARD LVCMOSxx [get_ports "VRP_48"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L1P_T0L_N0_DBC_48
set_property PACKAGE_PIN AE27 [get_ports "5N4156"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4156"]
# Bank 48 VCCO - VADJ_1V8_FPGA_10A - IO_L1N_T0L_N1_DBC_48
set_property PACKAGE_PIN AF27 [get_ports "5N4153"]
set_property IOSTANDARD LVCMOSxx [get_ports "5N4153"]
#Other net PACKAGE_PIN AA30 - 5N4450 Bank 48 - VREF_48
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L24P_T3U_N10_66
set_property PACKAGE_PIN D13 [get_ports "FMC_HPC_LA06_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA06_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L24N_T3U_N11_66
set_property PACKAGE_PIN C13 [get_ports "FMC_HPC_LA06_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA06_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_T3U_N12_66
set_property PACKAGE_PIN E12 [get_ports "7N4392"]
set_property IOSTANDARD LVCMOSxx [get_ports "7N4392"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L23P_T3U_N8_66
set_property PACKAGE_PIN A13 [get_ports "FMC_HPC_LA03_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA03_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L23N_T3U_N9_66
set_property PACKAGE_PIN A12 [get_ports "FMC_HPC_LA03_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA03_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L22P_T3U_N6_DBC_AD0P_66
set_property PACKAGE_PIN F13 [get_ports "SYSMON_AD0_R_P"]
set_property IOSTANDARD ANALOG [get_ports "SYSMON_AD0_R_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L22N_T3U_N7_DBC_AD0N_66
set_property PACKAGE_PIN E13 [get_ports "SYSMON_AD0_R_N"]
set_property IOSTANDARD ANALOG [get_ports "SYSMON_AD0_R_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L21P_T3L_N4_AD8P_66
set_property PACKAGE_PIN C11 [get_ports "SYSMON_AD8_R_P"]
set_property IOSTANDARD ANALOG [get_ports "SYSMON_AD8_R_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L21N_T3L_N5_AD8N_66
set_property PACKAGE_PIN B11 [get_ports "SYSMON_AD8_R_N"]
set_property IOSTANDARD ANALOG [get_ports "SYSMON_AD8_R_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L20P_T3L_N2_AD1P_66
set_property PACKAGE_PIN C12 [get_ports "7N6232"]
set_property IOSTANDARD LVCMOSxx [get_ports "7N6232"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L20N_T3L_N3_AD1N_66
set_property PACKAGE_PIN B12 [get_ports "7N6230"]
set_property IOSTANDARD LVCMOSxx [get_ports "7N6230"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L19P_T3L_N0_DBC_AD9P_66
set_property PACKAGE_PIN E11 [get_ports "7N6227"]
set_property IOSTANDARD LVCMOS12 [get_ports "7N6227"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L19N_T3L_N1_DBC_AD9N_66
set_property PACKAGE_PIN D11 [get_ports "7N6224"]
set_property IOSTANDARD LVCMOSxx [get_ports "7N6224"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L18P_T2U_N10_AD2P_66
set_property PACKAGE_PIN J13 [get_ports "SYSMON_AD2_R_P"]
set_property IOSTANDARD ANALOG [get_ports "SYSMON_AD2_R_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L18N_T2U_N11_AD2N_66
set_property PACKAGE_PIN H13 [get_ports "SYSMON_AD2_R_N"]
set_property IOSTANDARD ANALOG [get_ports "SYSMON_AD2_R_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L17P_T2U_N8_AD10P_66
set_property PACKAGE_PIN L12 [get_ports "FMC_HPC_LA04_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA04_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L17N_T2U_N9_AD10N_66
set_property PACKAGE_PIN K12 [get_ports "FMC_HPC_LA04_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA04_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L16P_T2U_N6_QBC_AD3P_66
set_property PACKAGE_PIN L13 [get_ports "FMC_HPC_LA05_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA05_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L16N_T2U_N7_QBC_AD3N_66
set_property PACKAGE_PIN K13 [get_ports "FMC_HPC_LA05_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA05_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L15P_T2L_N4_AD11P_66
set_property PACKAGE_PIN K11 [get_ports "FMC_HPC_LA11_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA11_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L15N_T2L_N5_AD11N_66
set_property PACKAGE_PIN J11 [get_ports "FMC_HPC_LA11_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA11_N"]
#
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L14P_T2L_N2_GC_66
set_property PACKAGE_PIN H12 [get_ports "FMC_HPC_CLK0_M2C_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_CLK0_M2C_P"]
set_property DIFF_TERM TRUE [get_ports "FMC_HPC_CLK0_M2C_P"]
#
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L14N_T2L_N3_GC_66
set_property PACKAGE_PIN G12 [get_ports "FMC_HPC_CLK0_M2C_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_CLK0_M2C_N"]
set_property DIFF_TERM TRUE [get_ports "FMC_HPC_CLK0_M2C_N"]
#
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_T2U_N12_66
set_property PACKAGE_PIN F12 [get_ports "SI570_CLK_SEL_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "SI570_CLK_SEL_LS"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L13P_T2L_N0_GC_QBC_66
set_property PACKAGE_PIN H11 [get_ports "FMC_HPC_LA00_CC_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA00_CC_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L13N_T2L_N1_GC_QBC_66
set_property PACKAGE_PIN G11 [get_ports "FMC_HPC_LA00_CC_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA00_CC_N"]
#
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L12P_T1U_N10_GC_66
set_property PACKAGE_PIN G10 [get_ports "CLK_125MHZ_P"]
set_property IOSTANDARD LVDS [get_ports "CLK_125MHZ_P"]
#
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L12N_T1U_N11_GC_66
set_property PACKAGE_PIN F10 [get_ports "CLK_125MHZ_N"]
set_property IOSTANDARD LVDS [get_ports "CLK_125MHZ_N"]
#
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_T1U_N12_VRP_66
set_property PACKAGE_PIN L9 [get_ports "7N6175"]
set_property IOSTANDARD LVCMOSxx [get_ports "7N6175"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L11P_T1U_N8_GC_66
set_property PACKAGE_PIN G9 [get_ports "FMC_HPC_LA01_CC_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA01_CC_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L11N_T1U_N9_GC_66
set_property PACKAGE_PIN F9 [get_ports "FMC_HPC_LA01_CC_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA01_CC_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L10P_T1U_N6_QBC_AD4P_66
set_property PACKAGE_PIN K10 [get_ports "FMC_HPC_LA02_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA02_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L10N_T1U_N7_QBC_AD4N_66
set_property PACKAGE_PIN J10 [get_ports "FMC_HPC_LA02_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA02_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L9P_T1L_N4_AD12P_66
set_property PACKAGE_PIN J8 [get_ports "FMC_HPC_LA08_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA08_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L9N_T1L_N5_AD12N_66
set_property PACKAGE_PIN H8 [get_ports "FMC_HPC_LA08_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA08_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L8P_T1L_N2_AD5P_66
set_property PACKAGE_PIN J9 [get_ports "FMC_HPC_LA09_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA09_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L8N_T1L_N3_AD5N_66
set_property PACKAGE_PIN H9 [get_ports "FMC_HPC_LA09_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA09_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L7P_T1L_N0_QBC_AD13P_66
set_property PACKAGE_PIN L8 [get_ports "FMC_HPC_LA10_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA10_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L7N_T1L_N1_QBC_AD13N_66
set_property PACKAGE_PIN K8 [get_ports "FMC_HPC_LA10_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA10_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L6P_T0U_N10_AD6P_66
set_property PACKAGE_PIN E10 [get_ports "FMC_HPC_LA12_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA12_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L6N_T0U_N11_AD6N_66
set_property PACKAGE_PIN D10 [get_ports "FMC_HPC_LA12_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA12_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L5P_T0U_N8_AD14P_66
set_property PACKAGE_PIN D9 [get_ports "FMC_HPC_LA13_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA13_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L5N_T0U_N9_AD14N_66
set_property PACKAGE_PIN C9 [get_ports "FMC_HPC_LA13_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA13_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L4P_T0U_N6_DBC_AD7P_66
set_property PACKAGE_PIN B10 [get_ports "FMC_HPC_LA14_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA14_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L4N_T0U_N7_DBC_AD7N_66
set_property PACKAGE_PIN A10 [get_ports "FMC_HPC_LA14_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA14_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L3P_T0L_N4_AD15P_66
set_property PACKAGE_PIN D8 [get_ports "FMC_HPC_LA15_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA15_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L3N_T0L_N5_AD15N_66
set_property PACKAGE_PIN C8 [get_ports "FMC_HPC_LA15_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA15_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L2P_T0L_N2_66
set_property PACKAGE_PIN B9 [get_ports "FMC_HPC_LA16_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA16_P"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_L2N_T0L_N3_66
set_property PACKAGE_PIN A9 [get_ports "FMC_HPC_LA16_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_LA16_N"]
# Bank 66 VCCO - VADJ_1V8_FPGA_10A - IO_T0U_N12_66
set_property PACKAGE_PIN A8 [get_ports "VRP_66"]
set_property IOSTANDARD LVCOMSxx [get_ports "VRP_66"]