From 19d32148611707fb71146b8215ca90a469d93b7d Mon Sep 17 00:00:00 2001
From: chunlin min <chunlin.min@microchip.com>
Date: Thu, 4 Jul 2024 14:13:26 -0400
Subject: [PATCH 1/4] use output reg instead of additional reg declaration

---
 techlibs/microchip/cells_sim.v | 20 ++++++--------------
 1 file changed, 6 insertions(+), 14 deletions(-)

diff --git a/techlibs/microchip/cells_sim.v b/techlibs/microchip/cells_sim.v
index de4038e0954..f3b55fe4c70 100644
--- a/techlibs/microchip/cells_sim.v
+++ b/techlibs/microchip/cells_sim.v
@@ -164,22 +164,18 @@ module MICROCHIP_SYNC_SET_DFF(
 	input CLK,
 	input Set,
 	input En,
-	output Q);
+	output reg Q);
 	parameter [0:0] INIT = 1'b0; // unused
 
-	reg q_ff;
-
 	always @(posedge CLK) begin
 		if (En == 1) begin
 			if (Set == 0)
-				q_ff <= 1;
+				Q <= 1;
 			else
-				q_ff <= D;
+				Q <= D;
 		end
 	end
 
-	assign Q = q_ff;
-
 	specify
 		$setup(D , posedge CLK &&& En && Set, 0); // neg setup not supported?
 		$setup(En, posedge CLK, 109);
@@ -195,22 +191,18 @@ module MICROCHIP_SYNC_RESET_DFF(
 	input CLK,
 	input Reset,
 	input En,
-	output Q);
+	output reg Q);
 	parameter [0:0] INIT = 1'b0; // unused
 
-	reg q_ff;
-
 	always @(posedge CLK) begin
 		if (En == 1) begin
 			if (Reset == 0) 
-				q_ff <= 0;
+				Q <= 0;
 			else
-				q_ff <= D;
+				Q <= D;
 		end
 	end
 
-	assign Q = q_ff;
-
 	specify
 		$setup(D , posedge CLK &&& En && Reset, 0); // neg setup not supported?
 		$setup(En, posedge CLK, 109);

From e3c4791e5ba446e484385be7385fca2a4cfa87d6 Mon Sep 17 00:00:00 2001
From: chunlin min <chunlin.min@microchip.com>
Date: Thu, 4 Jul 2024 14:16:52 -0400
Subject: [PATCH 2/4] move microchip tests from techlibs/microchip/tests to
 tests/arch/microchip

---
 .../tests => tests/arch/microchip}/Registers/Registers.v          | 0
 .../tests => tests/arch/microchip}/Registers/Registers.ys         | 0
 .../microchip/tests => tests/arch/microchip}/carryout/carryout.v  | 0
 .../microchip/tests => tests/arch/microchip}/carryout/carryout.ys | 0
 .../microchip/tests => tests/arch/microchip}/cascade/cascade.v    | 0
 .../microchip/tests => tests/arch/microchip}/cascade/cascade.ys   | 0
 .../microchip/tests => tests/arch/microchip}/dff_opt/dff_opt.v    | 0
 .../microchip/tests => tests/arch/microchip}/dff_opt/dff_opt.ys   | 0
 .../microchip/tests => tests/arch/microchip}/full_dsp/full_dsp.v  | 0
 .../microchip/tests => tests/arch/microchip}/full_dsp/full_dsp.ys | 0
 .../tests => tests/arch/microchip}/large_mult/large_mult.v        | 0
 .../tests => tests/arch/microchip}/large_mult/large_mult.ys       | 0
 {techlibs/microchip/tests => tests/arch/microchip}/mac/mac.v      | 0
 {techlibs/microchip/tests => tests/arch/microchip}/mac/mac.ys     | 0
 .../tests => tests/arch/microchip}/postAdd_mult/postAdd_mult.v    | 0
 .../tests => tests/arch/microchip}/postAdd_mult/postAdd_mult.ys   | 0
 .../tests => tests/arch/microchip}/post_adder/post_adder.v        | 0
 .../tests => tests/arch/microchip}/post_adder/post_adder.ys       | 0
 .../tests => tests/arch/microchip}/pre_adder_dsp/pre_adder_dsp.v  | 0
 .../tests => tests/arch/microchip}/pre_adder_dsp/pre_adder_dsp.ys | 0
 .../microchip/tests => tests/arch/microchip}/ram_SDP/ram_SDP.v    | 0
 .../microchip/tests => tests/arch/microchip}/ram_SDP/ram_SDP.ys   | 0
 .../microchip/tests => tests/arch/microchip}/ram_TDP/ram_TDP.v    | 0
 .../microchip/tests => tests/arch/microchip}/ram_TDP/ram_TDP.ys   | 0
 .../microchip/tests => tests/arch/microchip}/reduce/reduce.v      | 0
 .../microchip/tests => tests/arch/microchip}/reduce/reduce.ys     | 0
 {techlibs/microchip/tests => tests/arch/microchip}/reg_c/reg_c.v  | 0
 {techlibs/microchip/tests => tests/arch/microchip}/reg_c/reg_c.ys | 0
 .../microchip/tests => tests/arch/microchip}/reg_test/reg_test.v  | 0
 .../microchip/tests => tests/arch/microchip}/reg_test/reg_test.ys | 0
 .../tests => tests/arch/microchip}/signed_mult/signed_mult.v      | 0
 .../tests => tests/arch/microchip}/signed_mult/signed_mult.ys     | 0
 .../tests => tests/arch/microchip}/simple_ram/simple_ram.v        | 0
 .../tests => tests/arch/microchip}/simple_ram/simple_ram.ys       | 0
 .../tests => tests/arch/microchip}/unsigned_mult/unsigned_mult.v  | 0
 .../tests => tests/arch/microchip}/unsigned_mult/unsigned_mult.ys | 0
 .../microchip/tests => tests/arch/microchip}/uram_ar/uram_ar.v    | 0
 .../microchip/tests => tests/arch/microchip}/uram_ar/uram_ar.ys   | 0
 .../microchip/tests => tests/arch/microchip}/uram_sr/uram_sr.v    | 0
 .../microchip/tests => tests/arch/microchip}/uram_sr/uram_sr.ys   | 0
 .../microchip/tests => tests/arch/microchip}/widemux/widemux.v    | 0
 .../microchip/tests => tests/arch/microchip}/widemux/widemux.ys   | 0
 42 files changed, 0 insertions(+), 0 deletions(-)
 rename {techlibs/microchip/tests => tests/arch/microchip}/Registers/Registers.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/Registers/Registers.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/carryout/carryout.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/carryout/carryout.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/cascade/cascade.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/cascade/cascade.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/dff_opt/dff_opt.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/dff_opt/dff_opt.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/full_dsp/full_dsp.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/full_dsp/full_dsp.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/large_mult/large_mult.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/large_mult/large_mult.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/mac/mac.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/mac/mac.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/postAdd_mult/postAdd_mult.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/postAdd_mult/postAdd_mult.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/post_adder/post_adder.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/post_adder/post_adder.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/pre_adder_dsp/pre_adder_dsp.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/pre_adder_dsp/pre_adder_dsp.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/ram_SDP/ram_SDP.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/ram_SDP/ram_SDP.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/ram_TDP/ram_TDP.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/ram_TDP/ram_TDP.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/reduce/reduce.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/reduce/reduce.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/reg_c/reg_c.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/reg_c/reg_c.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/reg_test/reg_test.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/reg_test/reg_test.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/signed_mult/signed_mult.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/signed_mult/signed_mult.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/simple_ram/simple_ram.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/simple_ram/simple_ram.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/unsigned_mult/unsigned_mult.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/unsigned_mult/unsigned_mult.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/uram_ar/uram_ar.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/uram_ar/uram_ar.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/uram_sr/uram_sr.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/uram_sr/uram_sr.ys (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/widemux/widemux.v (100%)
 rename {techlibs/microchip/tests => tests/arch/microchip}/widemux/widemux.ys (100%)

diff --git a/techlibs/microchip/tests/Registers/Registers.v b/tests/arch/microchip/Registers/Registers.v
similarity index 100%
rename from techlibs/microchip/tests/Registers/Registers.v
rename to tests/arch/microchip/Registers/Registers.v
diff --git a/techlibs/microchip/tests/Registers/Registers.ys b/tests/arch/microchip/Registers/Registers.ys
similarity index 100%
rename from techlibs/microchip/tests/Registers/Registers.ys
rename to tests/arch/microchip/Registers/Registers.ys
diff --git a/techlibs/microchip/tests/carryout/carryout.v b/tests/arch/microchip/carryout/carryout.v
similarity index 100%
rename from techlibs/microchip/tests/carryout/carryout.v
rename to tests/arch/microchip/carryout/carryout.v
diff --git a/techlibs/microchip/tests/carryout/carryout.ys b/tests/arch/microchip/carryout/carryout.ys
similarity index 100%
rename from techlibs/microchip/tests/carryout/carryout.ys
rename to tests/arch/microchip/carryout/carryout.ys
diff --git a/techlibs/microchip/tests/cascade/cascade.v b/tests/arch/microchip/cascade/cascade.v
similarity index 100%
rename from techlibs/microchip/tests/cascade/cascade.v
rename to tests/arch/microchip/cascade/cascade.v
diff --git a/techlibs/microchip/tests/cascade/cascade.ys b/tests/arch/microchip/cascade/cascade.ys
similarity index 100%
rename from techlibs/microchip/tests/cascade/cascade.ys
rename to tests/arch/microchip/cascade/cascade.ys
diff --git a/techlibs/microchip/tests/dff_opt/dff_opt.v b/tests/arch/microchip/dff_opt/dff_opt.v
similarity index 100%
rename from techlibs/microchip/tests/dff_opt/dff_opt.v
rename to tests/arch/microchip/dff_opt/dff_opt.v
diff --git a/techlibs/microchip/tests/dff_opt/dff_opt.ys b/tests/arch/microchip/dff_opt/dff_opt.ys
similarity index 100%
rename from techlibs/microchip/tests/dff_opt/dff_opt.ys
rename to tests/arch/microchip/dff_opt/dff_opt.ys
diff --git a/techlibs/microchip/tests/full_dsp/full_dsp.v b/tests/arch/microchip/full_dsp/full_dsp.v
similarity index 100%
rename from techlibs/microchip/tests/full_dsp/full_dsp.v
rename to tests/arch/microchip/full_dsp/full_dsp.v
diff --git a/techlibs/microchip/tests/full_dsp/full_dsp.ys b/tests/arch/microchip/full_dsp/full_dsp.ys
similarity index 100%
rename from techlibs/microchip/tests/full_dsp/full_dsp.ys
rename to tests/arch/microchip/full_dsp/full_dsp.ys
diff --git a/techlibs/microchip/tests/large_mult/large_mult.v b/tests/arch/microchip/large_mult/large_mult.v
similarity index 100%
rename from techlibs/microchip/tests/large_mult/large_mult.v
rename to tests/arch/microchip/large_mult/large_mult.v
diff --git a/techlibs/microchip/tests/large_mult/large_mult.ys b/tests/arch/microchip/large_mult/large_mult.ys
similarity index 100%
rename from techlibs/microchip/tests/large_mult/large_mult.ys
rename to tests/arch/microchip/large_mult/large_mult.ys
diff --git a/techlibs/microchip/tests/mac/mac.v b/tests/arch/microchip/mac/mac.v
similarity index 100%
rename from techlibs/microchip/tests/mac/mac.v
rename to tests/arch/microchip/mac/mac.v
diff --git a/techlibs/microchip/tests/mac/mac.ys b/tests/arch/microchip/mac/mac.ys
similarity index 100%
rename from techlibs/microchip/tests/mac/mac.ys
rename to tests/arch/microchip/mac/mac.ys
diff --git a/techlibs/microchip/tests/postAdd_mult/postAdd_mult.v b/tests/arch/microchip/postAdd_mult/postAdd_mult.v
similarity index 100%
rename from techlibs/microchip/tests/postAdd_mult/postAdd_mult.v
rename to tests/arch/microchip/postAdd_mult/postAdd_mult.v
diff --git a/techlibs/microchip/tests/postAdd_mult/postAdd_mult.ys b/tests/arch/microchip/postAdd_mult/postAdd_mult.ys
similarity index 100%
rename from techlibs/microchip/tests/postAdd_mult/postAdd_mult.ys
rename to tests/arch/microchip/postAdd_mult/postAdd_mult.ys
diff --git a/techlibs/microchip/tests/post_adder/post_adder.v b/tests/arch/microchip/post_adder/post_adder.v
similarity index 100%
rename from techlibs/microchip/tests/post_adder/post_adder.v
rename to tests/arch/microchip/post_adder/post_adder.v
diff --git a/techlibs/microchip/tests/post_adder/post_adder.ys b/tests/arch/microchip/post_adder/post_adder.ys
similarity index 100%
rename from techlibs/microchip/tests/post_adder/post_adder.ys
rename to tests/arch/microchip/post_adder/post_adder.ys
diff --git a/techlibs/microchip/tests/pre_adder_dsp/pre_adder_dsp.v b/tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.v
similarity index 100%
rename from techlibs/microchip/tests/pre_adder_dsp/pre_adder_dsp.v
rename to tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.v
diff --git a/techlibs/microchip/tests/pre_adder_dsp/pre_adder_dsp.ys b/tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.ys
similarity index 100%
rename from techlibs/microchip/tests/pre_adder_dsp/pre_adder_dsp.ys
rename to tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.ys
diff --git a/techlibs/microchip/tests/ram_SDP/ram_SDP.v b/tests/arch/microchip/ram_SDP/ram_SDP.v
similarity index 100%
rename from techlibs/microchip/tests/ram_SDP/ram_SDP.v
rename to tests/arch/microchip/ram_SDP/ram_SDP.v
diff --git a/techlibs/microchip/tests/ram_SDP/ram_SDP.ys b/tests/arch/microchip/ram_SDP/ram_SDP.ys
similarity index 100%
rename from techlibs/microchip/tests/ram_SDP/ram_SDP.ys
rename to tests/arch/microchip/ram_SDP/ram_SDP.ys
diff --git a/techlibs/microchip/tests/ram_TDP/ram_TDP.v b/tests/arch/microchip/ram_TDP/ram_TDP.v
similarity index 100%
rename from techlibs/microchip/tests/ram_TDP/ram_TDP.v
rename to tests/arch/microchip/ram_TDP/ram_TDP.v
diff --git a/techlibs/microchip/tests/ram_TDP/ram_TDP.ys b/tests/arch/microchip/ram_TDP/ram_TDP.ys
similarity index 100%
rename from techlibs/microchip/tests/ram_TDP/ram_TDP.ys
rename to tests/arch/microchip/ram_TDP/ram_TDP.ys
diff --git a/techlibs/microchip/tests/reduce/reduce.v b/tests/arch/microchip/reduce/reduce.v
similarity index 100%
rename from techlibs/microchip/tests/reduce/reduce.v
rename to tests/arch/microchip/reduce/reduce.v
diff --git a/techlibs/microchip/tests/reduce/reduce.ys b/tests/arch/microchip/reduce/reduce.ys
similarity index 100%
rename from techlibs/microchip/tests/reduce/reduce.ys
rename to tests/arch/microchip/reduce/reduce.ys
diff --git a/techlibs/microchip/tests/reg_c/reg_c.v b/tests/arch/microchip/reg_c/reg_c.v
similarity index 100%
rename from techlibs/microchip/tests/reg_c/reg_c.v
rename to tests/arch/microchip/reg_c/reg_c.v
diff --git a/techlibs/microchip/tests/reg_c/reg_c.ys b/tests/arch/microchip/reg_c/reg_c.ys
similarity index 100%
rename from techlibs/microchip/tests/reg_c/reg_c.ys
rename to tests/arch/microchip/reg_c/reg_c.ys
diff --git a/techlibs/microchip/tests/reg_test/reg_test.v b/tests/arch/microchip/reg_test/reg_test.v
similarity index 100%
rename from techlibs/microchip/tests/reg_test/reg_test.v
rename to tests/arch/microchip/reg_test/reg_test.v
diff --git a/techlibs/microchip/tests/reg_test/reg_test.ys b/tests/arch/microchip/reg_test/reg_test.ys
similarity index 100%
rename from techlibs/microchip/tests/reg_test/reg_test.ys
rename to tests/arch/microchip/reg_test/reg_test.ys
diff --git a/techlibs/microchip/tests/signed_mult/signed_mult.v b/tests/arch/microchip/signed_mult/signed_mult.v
similarity index 100%
rename from techlibs/microchip/tests/signed_mult/signed_mult.v
rename to tests/arch/microchip/signed_mult/signed_mult.v
diff --git a/techlibs/microchip/tests/signed_mult/signed_mult.ys b/tests/arch/microchip/signed_mult/signed_mult.ys
similarity index 100%
rename from techlibs/microchip/tests/signed_mult/signed_mult.ys
rename to tests/arch/microchip/signed_mult/signed_mult.ys
diff --git a/techlibs/microchip/tests/simple_ram/simple_ram.v b/tests/arch/microchip/simple_ram/simple_ram.v
similarity index 100%
rename from techlibs/microchip/tests/simple_ram/simple_ram.v
rename to tests/arch/microchip/simple_ram/simple_ram.v
diff --git a/techlibs/microchip/tests/simple_ram/simple_ram.ys b/tests/arch/microchip/simple_ram/simple_ram.ys
similarity index 100%
rename from techlibs/microchip/tests/simple_ram/simple_ram.ys
rename to tests/arch/microchip/simple_ram/simple_ram.ys
diff --git a/techlibs/microchip/tests/unsigned_mult/unsigned_mult.v b/tests/arch/microchip/unsigned_mult/unsigned_mult.v
similarity index 100%
rename from techlibs/microchip/tests/unsigned_mult/unsigned_mult.v
rename to tests/arch/microchip/unsigned_mult/unsigned_mult.v
diff --git a/techlibs/microchip/tests/unsigned_mult/unsigned_mult.ys b/tests/arch/microchip/unsigned_mult/unsigned_mult.ys
similarity index 100%
rename from techlibs/microchip/tests/unsigned_mult/unsigned_mult.ys
rename to tests/arch/microchip/unsigned_mult/unsigned_mult.ys
diff --git a/techlibs/microchip/tests/uram_ar/uram_ar.v b/tests/arch/microchip/uram_ar/uram_ar.v
similarity index 100%
rename from techlibs/microchip/tests/uram_ar/uram_ar.v
rename to tests/arch/microchip/uram_ar/uram_ar.v
diff --git a/techlibs/microchip/tests/uram_ar/uram_ar.ys b/tests/arch/microchip/uram_ar/uram_ar.ys
similarity index 100%
rename from techlibs/microchip/tests/uram_ar/uram_ar.ys
rename to tests/arch/microchip/uram_ar/uram_ar.ys
diff --git a/techlibs/microchip/tests/uram_sr/uram_sr.v b/tests/arch/microchip/uram_sr/uram_sr.v
similarity index 100%
rename from techlibs/microchip/tests/uram_sr/uram_sr.v
rename to tests/arch/microchip/uram_sr/uram_sr.v
diff --git a/techlibs/microchip/tests/uram_sr/uram_sr.ys b/tests/arch/microchip/uram_sr/uram_sr.ys
similarity index 100%
rename from techlibs/microchip/tests/uram_sr/uram_sr.ys
rename to tests/arch/microchip/uram_sr/uram_sr.ys
diff --git a/techlibs/microchip/tests/widemux/widemux.v b/tests/arch/microchip/widemux/widemux.v
similarity index 100%
rename from techlibs/microchip/tests/widemux/widemux.v
rename to tests/arch/microchip/widemux/widemux.v
diff --git a/techlibs/microchip/tests/widemux/widemux.ys b/tests/arch/microchip/widemux/widemux.ys
similarity index 100%
rename from techlibs/microchip/tests/widemux/widemux.ys
rename to tests/arch/microchip/widemux/widemux.ys

From 8e7ec2d66091d3b657e2c58d4c4d113c7fb32067 Mon Sep 17 00:00:00 2001
From: chunlin min <chunlin.min@microchip.com>
Date: Thu, 4 Jul 2024 15:45:44 -0400
Subject: [PATCH 3/4] add assertions for synth_microchip tests

---
 techlibs/microchip/arith_map.v                |  6 +++---
 tests/arch/microchip/.gitignore               |  4 ++++
 .../microchip/{Registers => }/Registers.v     |  2 +-
 .../microchip/{Registers => }/Registers.ys    |  5 +++--
 .../arch/microchip/{carryout => }/carryout.v  |  0
 .../arch/microchip/{carryout => }/carryout.ys |  3 ++-
 tests/arch/microchip/{cascade => }/cascade.v  |  0
 tests/arch/microchip/{cascade => }/cascade.ys |  3 ++-
 tests/arch/microchip/{dff_opt => }/dff_opt.v  |  0
 tests/arch/microchip/{dff_opt => }/dff_opt.ys |  7 +++++--
 .../arch/microchip/{full_dsp => }/full_dsp.v  |  0
 .../arch/microchip/{full_dsp => }/full_dsp.ys |  3 ++-
 .../microchip/{large_mult => }/large_mult.v   |  0
 .../microchip/{large_mult => }/large_mult.ys  |  4 +++-
 tests/arch/microchip/{mac => }/mac.v          |  0
 tests/arch/microchip/{mac => }/mac.ys         |  4 ++--
 .../{postAdd_mult => }/postAdd_mult.v         |  0
 .../{postAdd_mult => }/postAdd_mult.ys        |  3 ++-
 .../microchip/{post_adder => }/post_adder.v   |  0
 .../microchip/{post_adder => }/post_adder.ys  |  6 ++++--
 .../{pre_adder_dsp => }/pre_adder_dsp.v       |  0
 .../{pre_adder_dsp => }/pre_adder_dsp.ys      |  3 ++-
 tests/arch/microchip/{ram_SDP => }/ram_SDP.v  |  0
 tests/arch/microchip/{ram_SDP => }/ram_SDP.ys |  5 ++++-
 tests/arch/microchip/{ram_TDP => }/ram_TDP.v  |  0
 tests/arch/microchip/{ram_TDP => }/ram_TDP.ys |  3 ++-
 tests/arch/microchip/{reduce => }/reduce.v    |  0
 tests/arch/microchip/{reduce => }/reduce.ys   |  4 +++-
 tests/arch/microchip/{reg_c => }/reg_c.v      |  0
 tests/arch/microchip/{reg_c => }/reg_c.ys     |  3 ++-
 .../arch/microchip/{reg_test => }/reg_test.v  |  0
 .../arch/microchip/{reg_test => }/reg_test.ys |  3 ++-
 tests/arch/microchip/run-test.sh              |  4 ++++
 .../microchip/{signed_mult => }/signed_mult.v |  0
 .../{signed_mult => }/signed_mult.ys          |  3 ++-
 .../microchip/{simple_ram => }/simple_ram.v   |  0
 .../microchip/{simple_ram => }/simple_ram.ys  |  3 ++-
 .../{unsigned_mult => }/unsigned_mult.v       |  0
 .../{unsigned_mult => }/unsigned_mult.ys      |  3 ++-
 tests/arch/microchip/{uram_ar => }/uram_ar.v  |  4 ++--
 tests/arch/microchip/{uram_ar => }/uram_ar.ys |  3 ++-
 tests/arch/microchip/{uram_sr => }/uram_sr.v  |  0
 tests/arch/microchip/{uram_sr => }/uram_sr.ys |  3 ++-
 tests/arch/microchip/{widemux => }/widemux.v  | 19 +------------------
 tests/arch/microchip/{widemux => }/widemux.ys |  3 ++-
 45 files changed, 67 insertions(+), 49 deletions(-)
 create mode 100644 tests/arch/microchip/.gitignore
 rename tests/arch/microchip/{Registers => }/Registers.v (98%)
 rename tests/arch/microchip/{Registers => }/Registers.ys (89%)
 rename tests/arch/microchip/{carryout => }/carryout.v (100%)
 rename tests/arch/microchip/{carryout => }/carryout.ys (92%)
 rename tests/arch/microchip/{cascade => }/cascade.v (100%)
 rename tests/arch/microchip/{cascade => }/cascade.ys (92%)
 rename tests/arch/microchip/{dff_opt => }/dff_opt.v (100%)
 rename tests/arch/microchip/{dff_opt => }/dff_opt.ys (86%)
 rename tests/arch/microchip/{full_dsp => }/full_dsp.v (100%)
 rename tests/arch/microchip/{full_dsp => }/full_dsp.ys (92%)
 rename tests/arch/microchip/{large_mult => }/large_mult.v (100%)
 rename tests/arch/microchip/{large_mult => }/large_mult.ys (92%)
 rename tests/arch/microchip/{mac => }/mac.v (100%)
 rename tests/arch/microchip/{mac => }/mac.ys (93%)
 rename tests/arch/microchip/{postAdd_mult => }/postAdd_mult.v (100%)
 rename tests/arch/microchip/{postAdd_mult => }/postAdd_mult.ys (92%)
 rename tests/arch/microchip/{post_adder => }/post_adder.v (100%)
 rename tests/arch/microchip/{post_adder => }/post_adder.ys (85%)
 rename tests/arch/microchip/{pre_adder_dsp => }/pre_adder_dsp.v (100%)
 rename tests/arch/microchip/{pre_adder_dsp => }/pre_adder_dsp.ys (92%)
 rename tests/arch/microchip/{ram_SDP => }/ram_SDP.v (100%)
 rename tests/arch/microchip/{ram_SDP => }/ram_SDP.ys (88%)
 rename tests/arch/microchip/{ram_TDP => }/ram_TDP.v (100%)
 rename tests/arch/microchip/{ram_TDP => }/ram_TDP.ys (92%)
 rename tests/arch/microchip/{reduce => }/reduce.v (100%)
 rename tests/arch/microchip/{reduce => }/reduce.ys (92%)
 rename tests/arch/microchip/{reg_c => }/reg_c.v (100%)
 rename tests/arch/microchip/{reg_c => }/reg_c.ys (92%)
 rename tests/arch/microchip/{reg_test => }/reg_test.v (100%)
 rename tests/arch/microchip/{reg_test => }/reg_test.ys (92%)
 create mode 100755 tests/arch/microchip/run-test.sh
 rename tests/arch/microchip/{signed_mult => }/signed_mult.v (100%)
 rename tests/arch/microchip/{signed_mult => }/signed_mult.ys (92%)
 rename tests/arch/microchip/{simple_ram => }/simple_ram.v (100%)
 rename tests/arch/microchip/{simple_ram => }/simple_ram.ys (92%)
 rename tests/arch/microchip/{unsigned_mult => }/unsigned_mult.v (100%)
 rename tests/arch/microchip/{unsigned_mult => }/unsigned_mult.ys (92%)
 rename tests/arch/microchip/{uram_ar => }/uram_ar.v (95%)
 rename tests/arch/microchip/{uram_ar => }/uram_ar.ys (92%)
 rename tests/arch/microchip/{uram_sr => }/uram_sr.v (100%)
 rename tests/arch/microchip/{uram_sr => }/uram_sr.ys (92%)
 rename tests/arch/microchip/{widemux => }/widemux.v (82%)
 rename tests/arch/microchip/{widemux => }/widemux.ys (93%)

diff --git a/techlibs/microchip/arith_map.v b/techlibs/microchip/arith_map.v
index c21f34f4427..6b105a1f3cc 100644
--- a/techlibs/microchip/arith_map.v
+++ b/techlibs/microchip/arith_map.v
@@ -31,9 +31,9 @@ endmodule
 
 (* techmap_celltype = "$reduce_xor" *)
 module \$__microchip_XOR8_ (A, Y);
-	parameter A_SIGNED = 0;
-	parameter A_WIDTH = 0;
-	parameter Y_WIDTH = 0;
+	parameter A_SIGNED = 1;
+	parameter A_WIDTH = 8;
+	parameter Y_WIDTH = 1;
 
 	input [A_WIDTH-1:0] A;
 	output [Y_WIDTH-1:0] Y;
diff --git a/tests/arch/microchip/.gitignore b/tests/arch/microchip/.gitignore
new file mode 100644
index 00000000000..9c0a77944a9
--- /dev/null
+++ b/tests/arch/microchip/.gitignore
@@ -0,0 +1,4 @@
+*.log
+/run-test.mk
+*.vm
+
diff --git a/tests/arch/microchip/Registers/Registers.v b/tests/arch/microchip/Registers.v
similarity index 98%
rename from tests/arch/microchip/Registers/Registers.v
rename to tests/arch/microchip/Registers.v
index b9a86d1d519..160c09cc736 100644
--- a/tests/arch/microchip/Registers/Registers.v
+++ b/tests/arch/microchip/Registers.v
@@ -21,7 +21,7 @@ module Registers(
 	input en,
 	input rst,
 	input D,
-	output Q
+	output reg Q
 );
 parameter LOAD_DATA = 1;
 
diff --git a/tests/arch/microchip/Registers/Registers.ys b/tests/arch/microchip/Registers.ys
similarity index 89%
rename from tests/arch/microchip/Registers/Registers.ys
rename to tests/arch/microchip/Registers.ys
index 7b1a1ed77a1..bbf7a6c912f 100644
--- a/tests/arch/microchip/Registers/Registers.ys
+++ b/tests/arch/microchip/Registers.ys
@@ -19,5 +19,6 @@ read_verilog Registers.v
 
 synth_microchip -top Registers -abc9 -family polarfire -noiopad
 
-# write final outputfile
-write_verilog -noexpr Registers.vm
+select -assert-count 1 t:SLE
+select -assert-count 1 t:CLKBUF
+select -assert-none t:SLE t:CLKBUF %% t:* %D
diff --git a/tests/arch/microchip/carryout/carryout.v b/tests/arch/microchip/carryout.v
similarity index 100%
rename from tests/arch/microchip/carryout/carryout.v
rename to tests/arch/microchip/carryout.v
diff --git a/tests/arch/microchip/carryout/carryout.ys b/tests/arch/microchip/carryout.ys
similarity index 92%
rename from tests/arch/microchip/carryout/carryout.ys
rename to tests/arch/microchip/carryout.ys
index 65d4d6709f2..7c79dfba38f 100644
--- a/tests/arch/microchip/carryout/carryout.ys
+++ b/tests/arch/microchip/carryout.ys
@@ -18,4 +18,5 @@ read_verilog carryout.v
 
 synth_microchip -top carryout -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr carryout.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/cascade/cascade.v b/tests/arch/microchip/cascade.v
similarity index 100%
rename from tests/arch/microchip/cascade/cascade.v
rename to tests/arch/microchip/cascade.v
diff --git a/tests/arch/microchip/cascade/cascade.ys b/tests/arch/microchip/cascade.ys
similarity index 92%
rename from tests/arch/microchip/cascade/cascade.ys
rename to tests/arch/microchip/cascade.ys
index a817c094553..7248c562594 100644
--- a/tests/arch/microchip/cascade/cascade.ys
+++ b/tests/arch/microchip/cascade.ys
@@ -18,4 +18,5 @@ read_verilog cascade.v
 
 synth_microchip -top cascade -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr cascade.vm
+select -assert-count 2 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/dff_opt/dff_opt.v b/tests/arch/microchip/dff_opt.v
similarity index 100%
rename from tests/arch/microchip/dff_opt/dff_opt.v
rename to tests/arch/microchip/dff_opt.v
diff --git a/tests/arch/microchip/dff_opt/dff_opt.ys b/tests/arch/microchip/dff_opt.ys
similarity index 86%
rename from tests/arch/microchip/dff_opt/dff_opt.ys
rename to tests/arch/microchip/dff_opt.ys
index 776081639f9..f159ad864f4 100644
--- a/tests/arch/microchip/dff_opt/dff_opt.ys
+++ b/tests/arch/microchip/dff_opt.ys
@@ -13,9 +13,12 @@
 # WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
 read_verilog dff_opt.v 
 
 synth_microchip -top dff_opt -abc9 -family polarfire -noiopad
 
-# write final outputfile
-write_verilog -noexpr dff_opt.vm
+select -assert-count 1 t:SLE
+select -assert-count 1 t:CFG4
+select -assert-count 1 t:CLKBUF
+select -assert-none t:SLE t:CFG4 t:CLKBUF %% t:* %D
\ No newline at end of file
diff --git a/tests/arch/microchip/full_dsp/full_dsp.v b/tests/arch/microchip/full_dsp.v
similarity index 100%
rename from tests/arch/microchip/full_dsp/full_dsp.v
rename to tests/arch/microchip/full_dsp.v
diff --git a/tests/arch/microchip/full_dsp/full_dsp.ys b/tests/arch/microchip/full_dsp.ys
similarity index 92%
rename from tests/arch/microchip/full_dsp/full_dsp.ys
rename to tests/arch/microchip/full_dsp.ys
index 67c66fa1989..9fce46a38bb 100644
--- a/tests/arch/microchip/full_dsp/full_dsp.ys
+++ b/tests/arch/microchip/full_dsp.ys
@@ -18,4 +18,5 @@ read_verilog full_dsp.v
 
 synth_microchip -top full_dsp -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr full_dsp.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/large_mult/large_mult.v b/tests/arch/microchip/large_mult.v
similarity index 100%
rename from tests/arch/microchip/large_mult/large_mult.v
rename to tests/arch/microchip/large_mult.v
diff --git a/tests/arch/microchip/large_mult/large_mult.ys b/tests/arch/microchip/large_mult.ys
similarity index 92%
rename from tests/arch/microchip/large_mult/large_mult.ys
rename to tests/arch/microchip/large_mult.ys
index ea3c80a0ddd..b76e5576af2 100644
--- a/tests/arch/microchip/large_mult/large_mult.ys
+++ b/tests/arch/microchip/large_mult.ys
@@ -18,4 +18,6 @@ read_verilog large_mult.v
 
 synth_microchip -top large_mult -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr large_mult.vm
+select -assert-count 2 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
+
diff --git a/tests/arch/microchip/mac/mac.v b/tests/arch/microchip/mac.v
similarity index 100%
rename from tests/arch/microchip/mac/mac.v
rename to tests/arch/microchip/mac.v
diff --git a/tests/arch/microchip/mac/mac.ys b/tests/arch/microchip/mac.ys
similarity index 93%
rename from tests/arch/microchip/mac/mac.ys
rename to tests/arch/microchip/mac.ys
index f8a0c45c5c1..69352354743 100644
--- a/tests/arch/microchip/mac/mac.ys
+++ b/tests/arch/microchip/mac.ys
@@ -20,5 +20,5 @@ read_verilog mac.v
 # run the synth flow, specifies top module and additional parameters
 synth_microchip -top mac -abc9 -family polarfire -noiopad
 
-# write final outputfile
-write_verilog -noexpr mac.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
\ No newline at end of file
diff --git a/tests/arch/microchip/postAdd_mult/postAdd_mult.v b/tests/arch/microchip/postAdd_mult.v
similarity index 100%
rename from tests/arch/microchip/postAdd_mult/postAdd_mult.v
rename to tests/arch/microchip/postAdd_mult.v
diff --git a/tests/arch/microchip/postAdd_mult/postAdd_mult.ys b/tests/arch/microchip/postAdd_mult.ys
similarity index 92%
rename from tests/arch/microchip/postAdd_mult/postAdd_mult.ys
rename to tests/arch/microchip/postAdd_mult.ys
index 54754bb7f5a..7d0a4bf0224 100644
--- a/tests/arch/microchip/postAdd_mult/postAdd_mult.ys
+++ b/tests/arch/microchip/postAdd_mult.ys
@@ -18,4 +18,5 @@ read_verilog postAdd_mult.v
 
 synth_microchip -top postAdd_mult -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr postAdd_mult.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/post_adder/post_adder.v b/tests/arch/microchip/post_adder.v
similarity index 100%
rename from tests/arch/microchip/post_adder/post_adder.v
rename to tests/arch/microchip/post_adder.v
diff --git a/tests/arch/microchip/post_adder/post_adder.ys b/tests/arch/microchip/post_adder.ys
similarity index 85%
rename from tests/arch/microchip/post_adder/post_adder.ys
rename to tests/arch/microchip/post_adder.ys
index 29f0e73f033..196215cac3e 100644
--- a/tests/arch/microchip/post_adder/post_adder.ys
+++ b/tests/arch/microchip/post_adder.ys
@@ -16,6 +16,8 @@
 
 read_verilog post_adder.v
 
-synth_microchip -top post_adder -abc9 -family polarfire
+synth_microchip -top post_adder -abc9 -family polarfire -noiopad
+
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
 
-write_verilog -noexpr post_adder.vm
diff --git a/tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.v b/tests/arch/microchip/pre_adder_dsp.v
similarity index 100%
rename from tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.v
rename to tests/arch/microchip/pre_adder_dsp.v
diff --git a/tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.ys b/tests/arch/microchip/pre_adder_dsp.ys
similarity index 92%
rename from tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.ys
rename to tests/arch/microchip/pre_adder_dsp.ys
index 1510f4ed61b..5aa87d432b4 100644
--- a/tests/arch/microchip/pre_adder_dsp/pre_adder_dsp.ys
+++ b/tests/arch/microchip/pre_adder_dsp.ys
@@ -18,4 +18,5 @@ read_verilog pre_adder_dsp.v
 
 synth_microchip -top pre_adder_dsp -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr pre_adder_dsp.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
\ No newline at end of file
diff --git a/tests/arch/microchip/ram_SDP/ram_SDP.v b/tests/arch/microchip/ram_SDP.v
similarity index 100%
rename from tests/arch/microchip/ram_SDP/ram_SDP.v
rename to tests/arch/microchip/ram_SDP.v
diff --git a/tests/arch/microchip/ram_SDP/ram_SDP.ys b/tests/arch/microchip/ram_SDP.ys
similarity index 88%
rename from tests/arch/microchip/ram_SDP/ram_SDP.ys
rename to tests/arch/microchip/ram_SDP.ys
index 0060c882db1..59f08705176 100644
--- a/tests/arch/microchip/ram_SDP/ram_SDP.ys
+++ b/tests/arch/microchip/ram_SDP.ys
@@ -18,4 +18,7 @@ read_verilog ram_SDP.v
 
 synth_microchip -top ram_SDP -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr ram_SDP.vm
+select -assert-count 1 t:RAM1K20
+select -assert-count 1 t:CFG1
+select -assert-none t:RAM1K20 t:CFG1 %% t:* %D
+
diff --git a/tests/arch/microchip/ram_TDP/ram_TDP.v b/tests/arch/microchip/ram_TDP.v
similarity index 100%
rename from tests/arch/microchip/ram_TDP/ram_TDP.v
rename to tests/arch/microchip/ram_TDP.v
diff --git a/tests/arch/microchip/ram_TDP/ram_TDP.ys b/tests/arch/microchip/ram_TDP.ys
similarity index 92%
rename from tests/arch/microchip/ram_TDP/ram_TDP.ys
rename to tests/arch/microchip/ram_TDP.ys
index 9fe5fdbe76a..9dab3cfdc2a 100644
--- a/tests/arch/microchip/ram_TDP/ram_TDP.ys
+++ b/tests/arch/microchip/ram_TDP.ys
@@ -18,4 +18,5 @@ read_verilog ram_TDP.v
 
 synth_microchip -top ram_TDP -abc9 -family polarfire -noiopad -debug_memory
 
-write_verilog -noexpr ram_TDP.vm
+select -assert-count 1 t:RAM1K20
+select -assert-none t:RAM1K20 %% t:* %D
diff --git a/tests/arch/microchip/reduce/reduce.v b/tests/arch/microchip/reduce.v
similarity index 100%
rename from tests/arch/microchip/reduce/reduce.v
rename to tests/arch/microchip/reduce.v
diff --git a/tests/arch/microchip/reduce/reduce.ys b/tests/arch/microchip/reduce.ys
similarity index 92%
rename from tests/arch/microchip/reduce/reduce.ys
rename to tests/arch/microchip/reduce.ys
index 3341f51a23f..789912f3225 100644
--- a/tests/arch/microchip/reduce/reduce.ys
+++ b/tests/arch/microchip/reduce.ys
@@ -18,4 +18,6 @@ read_verilog reduce.v
 
 synth_microchip -top reduce -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr reduce.vm
+select -assert-count 1 t:XOR8
+select -assert-none t:XOR8 %% t:* %D
+
diff --git a/tests/arch/microchip/reg_c/reg_c.v b/tests/arch/microchip/reg_c.v
similarity index 100%
rename from tests/arch/microchip/reg_c/reg_c.v
rename to tests/arch/microchip/reg_c.v
diff --git a/tests/arch/microchip/reg_c/reg_c.ys b/tests/arch/microchip/reg_c.ys
similarity index 92%
rename from tests/arch/microchip/reg_c/reg_c.ys
rename to tests/arch/microchip/reg_c.ys
index 0265be56f32..994e0811137 100644
--- a/tests/arch/microchip/reg_c/reg_c.ys
+++ b/tests/arch/microchip/reg_c.ys
@@ -18,4 +18,5 @@ read_verilog reg_c.v
 
 synth_microchip -top reg_c -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr reg_c.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/reg_test/reg_test.v b/tests/arch/microchip/reg_test.v
similarity index 100%
rename from tests/arch/microchip/reg_test/reg_test.v
rename to tests/arch/microchip/reg_test.v
diff --git a/tests/arch/microchip/reg_test/reg_test.ys b/tests/arch/microchip/reg_test.ys
similarity index 92%
rename from tests/arch/microchip/reg_test/reg_test.ys
rename to tests/arch/microchip/reg_test.ys
index 7bd44a99e7b..1b225b7bf64 100644
--- a/tests/arch/microchip/reg_test/reg_test.ys
+++ b/tests/arch/microchip/reg_test.ys
@@ -18,4 +18,5 @@ read_verilog reg_test.v
 
 synth_microchip -top reg_test -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr reg_test.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/run-test.sh b/tests/arch/microchip/run-test.sh
new file mode 100755
index 00000000000..4be4b70ae17
--- /dev/null
+++ b/tests/arch/microchip/run-test.sh
@@ -0,0 +1,4 @@
+#!/usr/bin/env bash
+set -eu
+source ../../gen-tests-makefile.sh
+run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'"
diff --git a/tests/arch/microchip/signed_mult/signed_mult.v b/tests/arch/microchip/signed_mult.v
similarity index 100%
rename from tests/arch/microchip/signed_mult/signed_mult.v
rename to tests/arch/microchip/signed_mult.v
diff --git a/tests/arch/microchip/signed_mult/signed_mult.ys b/tests/arch/microchip/signed_mult.ys
similarity index 92%
rename from tests/arch/microchip/signed_mult/signed_mult.ys
rename to tests/arch/microchip/signed_mult.ys
index 93588a5dd83..931052163c3 100755
--- a/tests/arch/microchip/signed_mult/signed_mult.ys
+++ b/tests/arch/microchip/signed_mult.ys
@@ -18,4 +18,5 @@ read_verilog signed_mult.v
 
 synth_microchip -top signed_mult -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr signed_mult.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/simple_ram/simple_ram.v b/tests/arch/microchip/simple_ram.v
similarity index 100%
rename from tests/arch/microchip/simple_ram/simple_ram.v
rename to tests/arch/microchip/simple_ram.v
diff --git a/tests/arch/microchip/simple_ram/simple_ram.ys b/tests/arch/microchip/simple_ram.ys
similarity index 92%
rename from tests/arch/microchip/simple_ram/simple_ram.ys
rename to tests/arch/microchip/simple_ram.ys
index 85975d25093..5ed8448ee27 100644
--- a/tests/arch/microchip/simple_ram/simple_ram.ys
+++ b/tests/arch/microchip/simple_ram.ys
@@ -18,4 +18,5 @@ read_verilog simple_ram.v
 
 synth_microchip -top simple_ram -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr simple_ram.vm
+select -assert-count 1 t:RAM1K20
+select -assert-none t:RAM1K20 %% t:* %D
diff --git a/tests/arch/microchip/unsigned_mult/unsigned_mult.v b/tests/arch/microchip/unsigned_mult.v
similarity index 100%
rename from tests/arch/microchip/unsigned_mult/unsigned_mult.v
rename to tests/arch/microchip/unsigned_mult.v
diff --git a/tests/arch/microchip/unsigned_mult/unsigned_mult.ys b/tests/arch/microchip/unsigned_mult.ys
similarity index 92%
rename from tests/arch/microchip/unsigned_mult/unsigned_mult.ys
rename to tests/arch/microchip/unsigned_mult.ys
index e588912eaba..9cc96c99811 100644
--- a/tests/arch/microchip/unsigned_mult/unsigned_mult.ys
+++ b/tests/arch/microchip/unsigned_mult.ys
@@ -18,4 +18,5 @@ read_verilog unsigned_mult.v
 
 synth_microchip -top unsigned_mult -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr unsigned_mult.vm
+select -assert-count 1 t:MACC_PA
+select -assert-none t:MACC_PA %% t:* %D
diff --git a/tests/arch/microchip/uram_ar/uram_ar.v b/tests/arch/microchip/uram_ar.v
similarity index 95%
rename from tests/arch/microchip/uram_ar/uram_ar.v
rename to tests/arch/microchip/uram_ar.v
index b3b542df634..c73ece07e31 100644
--- a/tests/arch/microchip/uram_ar/uram_ar.v
+++ b/tests/arch/microchip/uram_ar.v
@@ -17,9 +17,9 @@ OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */
 
 module uram_ar(data,waddr,we,clk,q);
-parameter d_width = 27;
+parameter d_width = 12;
 parameter addr_width = 2;
-parameter mem_depth = 4;
+parameter mem_depth = 12;
 input [d_width-1:0] data;
 input [addr_width-1:0] waddr;
 input we, clk;
diff --git a/tests/arch/microchip/uram_ar/uram_ar.ys b/tests/arch/microchip/uram_ar.ys
similarity index 92%
rename from tests/arch/microchip/uram_ar/uram_ar.ys
rename to tests/arch/microchip/uram_ar.ys
index cbaea647ff4..68e76897a31 100644
--- a/tests/arch/microchip/uram_ar/uram_ar.ys
+++ b/tests/arch/microchip/uram_ar.ys
@@ -18,4 +18,5 @@ read_verilog uram_ar.v
 
 synth_microchip -top uram_ar -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr uram_ar.vm
+select -assert-count 1 t:RAM64x12
+select -assert-none t:RAM64x12 %% t:* %D
diff --git a/tests/arch/microchip/uram_sr/uram_sr.v b/tests/arch/microchip/uram_sr.v
similarity index 100%
rename from tests/arch/microchip/uram_sr/uram_sr.v
rename to tests/arch/microchip/uram_sr.v
diff --git a/tests/arch/microchip/uram_sr/uram_sr.ys b/tests/arch/microchip/uram_sr.ys
similarity index 92%
rename from tests/arch/microchip/uram_sr/uram_sr.ys
rename to tests/arch/microchip/uram_sr.ys
index 7708fb39ff7..842d8362773 100644
--- a/tests/arch/microchip/uram_sr/uram_sr.ys
+++ b/tests/arch/microchip/uram_sr.ys
@@ -18,4 +18,5 @@ read_verilog uram_sr.v
 
 synth_microchip -top uram_sr -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr uram_sr.vm
+select -assert-count 1 t:RAM64x12
+select -assert-none t:RAM64x12 %% t:* %D
diff --git a/tests/arch/microchip/widemux/widemux.v b/tests/arch/microchip/widemux.v
similarity index 82%
rename from tests/arch/microchip/widemux/widemux.v
rename to tests/arch/microchip/widemux.v
index e25c7df16b5..74e3fd7fc58 100644
--- a/tests/arch/microchip/widemux/widemux.v
+++ b/tests/arch/microchip/widemux.v
@@ -23,25 +23,8 @@ module widemux(
 	output Y
 
 );
+assign Y = S1 ? (S0 ? data[3] : data[1]) : (S0 ? data[2] : data[0]);
 
-wire A, B;
-
-always @ (*) begin 
-		if (S0)begin
-		A = data[1];
-		B = data[3];
-		end else begin 
-		A = data[0];
-		B = data[2];
-	end
-
-	if (S1)begin
-		Y = A;
-	end else begin
-		Y = B;
-	end
-
-end
 endmodule
 
 
diff --git a/tests/arch/microchip/widemux/widemux.ys b/tests/arch/microchip/widemux.ys
similarity index 93%
rename from tests/arch/microchip/widemux/widemux.ys
rename to tests/arch/microchip/widemux.ys
index 8ef3a92308f..adb7e00bce3 100644
--- a/tests/arch/microchip/widemux/widemux.ys
+++ b/tests/arch/microchip/widemux.ys
@@ -18,4 +18,5 @@ read_verilog widemux.v
 
 synth_microchip -top widemux -abc9 -family polarfire -noiopad
 
-write_verilog -noexpr widemux.vm
+select -assert-count 1 t:MX4
+select -assert-none t:MX4 %% t:* %D
\ No newline at end of file

From 9de5602574cadc7a362134a9444a69646134e29b Mon Sep 17 00:00:00 2001
From: chunlin min <chunlin.min@microchip.com>
Date: Thu, 4 Jul 2024 15:54:59 -0400
Subject: [PATCH 4/4] ininclude microchip tests in makefile

---
 Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Makefile b/Makefile
index 313de44d56d..f40f0d6a515 100644
--- a/Makefile
+++ b/Makefile
@@ -863,6 +863,7 @@ endif
 	+cd tests/arch/quicklogic/pp3 && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/quicklogic/qlf_k6n10f && bash run-test.sh $(SEEDOPT)
 	+cd tests/arch/gatemate && bash run-test.sh $(SEEDOPT)
+	+cd tests/arch/microchip && bash run-test.sh $(SEEDOPT)
 	+cd tests/rpc && bash run-test.sh
 	+cd tests/memfile && bash run-test.sh
 	+cd tests/verilog && bash run-test.sh