- This repository holds various instructions for different basic modules in SystemVerilog.
- You need either Quartus Prime Lite, Vivado XLS or YoSYS.
- You can choose to use EDA playground for test benches
- Write your code, compile it, and generate RTL diagram.
- Upload your files and screenshot of RTL diagram in the folder
- All test bench writing is optional task, but it carries more points than the design
- This repository may update with more projects over the course of the hackathon, remember to sync fork and pull before starting to make changes
- Additionally feel free to suggest modules
- Self checking test-benches: 50 points
- Layered testbench: 500 points
- Simple testbenches: 25 points
- 16-Bit Priority Encoder
- 32-Bit Logic Shifter
- 32-Bit BCD Adder
- 32-Bit Prefix Adder
- 32-Bit Ripple Carry Adder
- 4-Bit Multiplier
- Decoder & Encoder
- 8-Bit ALU
- 8-Bit Comparator
- 8-Bit Barrel Shifter
- 8-Bit 7 Segment Decoder
- Mod-N Counter
- N-Bit ALU
- N-Bit Up/Down Counter
- Reduce 1s FSM
- Sequence Detector (01/10)
- Shift Register PISO
- Shift Register SIPO
- Shift Register SISO
- Traffic Light FSM
- Vending Machine FSM
- Parameterised RAM
- HDL ROM Module
- 4-Bit Hex Decoder