SweRV-EH1 implements non-blocking load path for load instructions without any dependency in next instructions. Processor jumps to next instruction while non-blocking load is being done. Results for non-blocking load are written back to gpr later.
Syncing non-block load result with it's respective PC and instruction could not be done due to irregular difference of cycle between them.
A separate log for nonblock log is generated by the tracer. Before Post-sim comparison, core log is updated using nonblock load log information via a postfix python script.
GPR can by updated either from writeback from i0 writeback, i1 writeback or from non-block load result. To trace this result, tracer signals were added at the writeback stage for enable, gpr address being written to and non-block load result. A separate nonblock load log is written to whenever nonblock load write enable is active. Log contains information regarding simulation time, cycle, gpr being written to and data being written back.
Purpose of the script nb_postfix.py is to find and replace the non-block load instruction in trace core log and update it with valid results.
The postfix script is called in sim.py to update the trace core log before csv generation. CSV is generated from core log for post-sim comparison.