From a5a03c66ba7d61c5869f585e6e031772a2dbe7d5 Mon Sep 17 00:00:00 2001 From: Paul Gardner-Stephen Date: Wed, 3 Apr 2024 20:03:44 +1030 Subject: [PATCH] fix buffered uart plumbing #798 --- src/vhdl/nexys4.vhdl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vhdl/nexys4.vhdl b/src/vhdl/nexys4.vhdl index 45973e4ff..153fbac41 100644 --- a/src/vhdl/nexys4.vhdl +++ b/src/vhdl/nexys4.vhdl @@ -581,8 +581,8 @@ begin uart_rx => jclo(1), uart_tx => jclo(2), - buffereduart_rx => jalo(1), - buffereduart_tx => jalo(2), + buffereduart_rx(0) => jalo(1), + buffereduart_tx(0) => jalo(2), -- buffereduart2_rx => jchi(9), -- buffereduart2_tx => jchi(10), buffereduart_ringindicate => (others => '0'),