I watched the lecture series for MIT 6.004 "Computation Structures", where they build a 32-bit computer called "Beta". My plan is to implement this computer on a NEXYS4 DDR board from DigilentInc.
The NEXYS4 DDR board is built around a Xilinx Artix-7 FPGA, specifically a XC7A100T with approx 100 K logic cells and 540 KB RAM. The FPGA is furthermore connected to a 128 MB DDR2 RAM.
The intent is to get a design working on the board, using the VGA output for debug purposes, e.g. showing the contents of all the registers.
I will start by implementing the unpipelined version. I need to come up with a plan for thoroughly testing my implementation. I also need to figure out how to write a compiler for the Beta CPU.
- The NEXYS4 DDR boaard is documented here.
- The MIT lecture series is here.
- The description of the Beta design.
- Course website.
- Lab material.
I will be keeping a log of my work, please see the file log.md