Skip to content

Commit d8388f3

Browse files
authored
feat(par): add mover functionality to parallel capabilities (#1427)
* - add exchange mover - split mover in provider,receiver parts * - add syncing of qpactual * fprettify * add synchronization of package mover iprmap for movers * modify makefile * add file to MSVS * Fix merge error * fprettify * fix: only add variables to mapper when exchange has a mvr * - add (parallel) exchange mover test - ncpus can now be set per simulation in testframework * - (this file has been renamed: test_gwf_exgmvr01.py * - add second exchange mover test (+parallel) - fix printing of MVR table with qavailable in parallel
1 parent d5e5927 commit d8388f3

20 files changed

+1340
-145
lines changed

autotest/framework.py

+34-11
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,17 @@
1010

1111
import flopy
1212
import numpy as np
13-
from common_regression import (COMPARE_PROGRAMS, adjust_htol,
14-
get_mf6_comparison, get_mf6_files,
15-
get_namefiles, get_rclose, get_regression_files,
16-
setup_mf6, setup_mf6_comparison)
13+
from common_regression import (
14+
COMPARE_PROGRAMS,
15+
adjust_htol,
16+
get_mf6_comparison,
17+
get_mf6_files,
18+
get_namefiles,
19+
get_rclose,
20+
get_regression_files,
21+
setup_mf6,
22+
setup_mf6_comparison,
23+
)
1724
from flopy.mbase import BaseModel
1825
from flopy.mf6 import MFSimulation
1926
from flopy.utils.compare import compare_heads
@@ -243,7 +250,7 @@ def __init__(
243250
self.build = build
244251
self.check = check
245252
self.parallel = parallel
246-
self.ncpus = ncpus
253+
self.ncpus = [ncpus] if isinstance(ncpus, int) else ncpus
247254
self.api_func = api_func
248255
self.compare = compare
249256
self.outp = None
@@ -526,6 +533,7 @@ def run_sim_or_model(
526533
workspace: Union[str, os.PathLike],
527534
target: Union[str, os.PathLike],
528535
xfail: bool = False,
536+
ncpus: int = 1,
529537
) -> Tuple[bool, List[str]]:
530538
"""
531539
Run a simulation or model with FloPy.
@@ -536,6 +544,8 @@ def run_sim_or_model(
536544
The target executable to use
537545
xfail : bool
538546
Whether to expect failure
547+
ncpus : int
548+
The number of CPUs for a parallel run
539549
"""
540550

541551
# make sure workspace exists
@@ -570,14 +580,12 @@ def run_sim_or_model(
570580
# via MF6 executable
571581
elif "mf6" in target.name:
572582
# parallel test if configured
573-
if self.parallel:
583+
if self.parallel and ncpus > 1:
574584
print(
575585
f"Parallel test {self.name} on {self.ncpus} processes"
576586
)
577587
try:
578-
success, buff = run_parallel(
579-
workspace, target, self.ncpus
580-
)
588+
success, buff = run_parallel(workspace, target, ncpus)
581589
except Exception:
582590
warn(
583591
"MODFLOW 6 parallel test",
@@ -687,19 +695,31 @@ def run(self):
687695
self.sims = sims
688696
nsims = len(sims)
689697
self.buffs = list(repeat(None, nsims))
698+
690699
assert len(self.xfail) in [
691700
1,
692701
nsims,
693702
], f"Invalid xfail: expected a single boolean or one for each model"
694703
if len(self.xfail) == 1 and nsims:
695704
self.xfail = list(repeat(self.xfail[0], nsims))
705+
706+
assert len(self.ncpus) in [
707+
1,
708+
nsims,
709+
], f"Invalid ncpus: expected a single integer or one for each model"
710+
if len(self.ncpus) == 1 and nsims:
711+
self.ncpus = list(repeat(self.ncpus[0], nsims))
712+
696713
write_input(*sims, overwrite=self.overwrite, verbose=self.verbose)
697714
else:
698715
self.sims = [MFSimulation.load(sim_ws=self.workspace)]
699716
self.buffs = [None]
700717
assert (
701718
len(self.xfail) == 1
702-
), f"Invalid xfail: expected a single boolean or one for each model"
719+
), f"Invalid xfail: expected a single boolean"
720+
assert (
721+
len(self.ncpus) == 1
722+
), f"Invalid ncpus: expected a single integer"
703723

704724
# run models/simulations
705725
for i, sim_or_model in enumerate(self.sims):
@@ -716,7 +736,10 @@ def run(self):
716736
else tgts.get(exe_path.stem, tgts["mf6"])
717737
)
718738
xfail = self.xfail[i]
719-
success, buff = self.run_sim_or_model(workspace, target, xfail)
739+
ncpus = self.ncpus[i]
740+
success, buff = self.run_sim_or_model(
741+
workspace, target, xfail, ncpus
742+
)
720743
self.buffs[i] = buff # store model output for assertions later
721744
assert success, (
722745
f"{'Simulation' if 'mf6' in str(target) else 'Model'} "

autotest/test_gwf_sfr01gwfgwf.py autotest/test_gwf_exgmvr01.py

+2-5
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
"""
22
Based on sft01 gwf model, but split into two gwf models test gwf-gwf and
3-
mvr. The single base model is split using the model splitter into two models.
4-
The single model is run as the regression model
3+
mvr. The single model is run as the regression model
54
65
The final split model look like:
76
@@ -18,9 +17,7 @@
1817

1918
from framework import TestFramework
2019

21-
# from flopy.mf6.utils import Mf6Splitter
22-
23-
cases = ["sfr01gwfgwf"]
20+
cases = ["gwf_exgmvr01"]
2421

2522
# properties for single model combination
2623
lx = 14.0

0 commit comments

Comments
 (0)