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ddr3_training.c
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/*******************************************************************************
Copyright (C) 2016 Marvell International Ltd.
This software file (the "File") is owned and distributed by Marvell
International Ltd. and/or its affiliates ("Marvell") under the following
alternative licensing terms. Once you have made an election to distribute the
File under one of the following license alternatives, please (i) delete this
introductory statement regarding license alternatives, (ii) delete the three
license alternatives that you have not elected to use and (iii) preserve the
Marvell copyright notice above.
********************************************************************************
Marvell Commercial License Option
If you received this File from Marvell and you have entered into a commercial
license agreement (a "Commercial License") with Marvell, the File is licensed
to you under the terms of the applicable Commercial License.
********************************************************************************
Marvell GPL License Option
This program is free software: you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation, either version 2 of the License, or any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
********************************************************************************
Marvell GNU General Public License FreeRTOS Exception
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File in accordance with the terms and conditions of the Lesser
General Public License Version 2.1 plus the following FreeRTOS exception.
An independent module is a module which is not derived from or based on
FreeRTOS.
Clause 1:
Linking FreeRTOS statically or dynamically with other modules is making a
combined work based on FreeRTOS. Thus, the terms and conditions of the GNU
General Public License cover the whole combination.
As a special exception, the copyright holder of FreeRTOS gives you permission
to link FreeRTOS with independent modules that communicate with FreeRTOS solely
through the FreeRTOS API interface, regardless of the license terms of these
independent modules, and to copy and distribute the resulting combined work
under terms of your choice, provided that:
1. Every copy of the combined work is accompanied by a written statement that
details to the recipient the version of FreeRTOS used and an offer by yourself
to provide the FreeRTOS source code (including any modifications you may have
made) should the recipient request it.
2. The combined work is not itself an RTOS, scheduler, kernel or related
product.
3. The independent modules add significant and primary functionality to
FreeRTOS and do not merely extend the existing functionality already present in
FreeRTOS.
Clause 2:
FreeRTOS may not be used for any competitive or comparative purpose, including
the publication of any form of run time or compile time metric, without the
express permission of Real Time Engineers Ltd. (this is the norm within the
industry and is intended to ensure information accuracy).
********************************************************************************
Marvell BSD License Option
If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Marvell nor the names of its contributors may be
used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#include "ddr3_init.h"
#include "mv_ddr_common.h"
#include "mv_ddr_training_db.h"
#include "mv_ddr_regs.h"
#if defined(A70X0) || defined(A80X0)
#include "mv_ddr_mrs.h"
#endif
#define GET_CS_FROM_MASK(mask) (cs_mask2_num[mask])
#define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num])
u32 window_mem_addr = 0;
u32 phy_reg0_val = 0;
u32 phy_reg1_val = 8;
u32 phy_reg2_val = 0;
u32 phy_reg3_val = PARAM_UNDEFINED;
enum mv_ddr_freq low_freq = MV_DDR_FREQ_LOW_FREQ;
enum mv_ddr_freq medium_freq;
u32 debug_dunit = 0;
u32 odt_additional = 1;
u32 *dq_map_table = NULL;
/* in case of ddr4 do not run ddr3_tip_write_additional_odt_setting function - mc odt always 'on'
* in ddr4 case the terminations are rttWR and rttPARK and the odt must be always 'on' 0x1498 = 0xf
*/
#if defined(CONFIG_DDR4)
u32 odt_config = 0;
#else
u32 odt_config = 1;
#endif
u32 nominal_avs;
u32 extension_avs;
u32 is_pll_before_init = 0, is_adll_calib_before_init = 1, is_dfs_in_init = 0;
u32 dfs_low_freq;
u32 g_rtt_nom_cs0, g_rtt_nom_cs1;
u8 calibration_update_control; /* 2 external only, 1 is internal only */
enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
enum auto_tune_stage training_stage = INIT_CONTROLLER;
u32 finger_test = 0, p_finger_start = 11, p_finger_end = 64,
n_finger_start = 11, n_finger_end = 64,
p_finger_step = 3, n_finger_step = 3;
u32 clamp_tbl[] = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 };
/* Initiate to 0xff, this variable is define by user in debug mode */
u32 mode_2t = 0xff;
u32 xsb_validate_type = 0;
u32 xsb_validation_base_address = 0xf000;
u32 first_active_if = 0;
u32 dfs_low_phy1 = 0x1f;
u32 multicast_id = 0;
int use_broadcast = 0;
struct hws_tip_freq_config_info *freq_info_table = NULL;
u8 is_cbe_required = 0;
u32 debug_mode = 0;
u32 delay_enable = 0;
int rl_mid_freq_wa = 0;
u32 effective_cs = 0;
u32 vref_init_val = 0x4;
u32 ck_delay = PARAM_UNDEFINED;
/* Design guidelines parameters */
u32 g_zpri_data = PARAM_UNDEFINED; /* controller data - P drive strength */
u32 g_znri_data = PARAM_UNDEFINED; /* controller data - N drive strength */
u32 g_zpri_ctrl = PARAM_UNDEFINED; /* controller C/A - P drive strength */
u32 g_znri_ctrl = PARAM_UNDEFINED; /* controller C/A - N drive strength */
u32 g_zpodt_data = PARAM_UNDEFINED; /* controller data - P ODT */
u32 g_znodt_data = PARAM_UNDEFINED; /* controller data - N ODT */
u32 g_zpodt_ctrl = PARAM_UNDEFINED; /* controller data - P ODT */
u32 g_znodt_ctrl = PARAM_UNDEFINED; /* controller data - N ODT */
u32 g_odt_config = PARAM_UNDEFINED;
u32 g_rtt_nom = PARAM_UNDEFINED;
u32 g_rtt_wr = PARAM_UNDEFINED;
u32 g_dic = PARAM_UNDEFINED;
u32 g_rtt_park = PARAM_UNDEFINED;
u32 mask_tune_func = (SET_MEDIUM_FREQ_MASK_BIT |
WRITE_LEVELING_MASK_BIT |
LOAD_PATTERN_2_MASK_BIT |
READ_LEVELING_MASK_BIT |
SET_TARGET_FREQ_MASK_BIT |
WRITE_LEVELING_TF_MASK_BIT |
#if defined(CONFIG_DDR4)
SW_READ_LEVELING_MASK_BIT |
#else /* CONFIG_DDR4 */
READ_LEVELING_TF_MASK_BIT |
#endif /* CONFIG_DDR4 */
CENTRALIZATION_RX_MASK_BIT |
CENTRALIZATION_TX_MASK_BIT);
static int ddr3_tip_ddr3_training_main_flow(u32 dev_num);
static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
u32 if_id, u32 cl_value, u32 cwl_value);
static int ddr3_tip_ddr3_auto_tune(u32 dev_num);
#ifdef ODT_TEST_SUPPORT
static int odt_test(u32 dev_num, enum hws_algo_type algo_type);
#endif
int adll_calibration(u32 dev_num, enum hws_access_type access_type,
u32 if_id, enum mv_ddr_freq frequency);
static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
u32 if_id, enum mv_ddr_freq frequency);
#if defined(CONFIG_DDR4)
static int ddr4_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
u32 if_id, enum mv_ddr_freq frequency);
#endif /* CONFIG_DDR4 */
static u8 mem_size_config[MV_DDR_DIE_CAP_LAST] = {
0x2, /* 512Mbit */
0x3, /* 1Gbit */
0x0, /* 2Gbit */
0x4, /* 4Gbit */
0x5, /* 8Gbit */
0x0, /* TODO: placeholder for 16-Mbit die capacity */
0x0, /* TODO: placeholder for 32-Mbit die capacity */
0x0, /* TODO: placeholder for 12-Mbit die capacity */
0x0 /* TODO: placeholder for 24-Mbit die capacity */
};
static u8 cs_mask2_num[] = { 0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 };
static struct reg_data odpg_default_value[] = {
{0x1034, 0x38000, MASK_ALL_BITS},
{0x1038, 0x0, MASK_ALL_BITS},
{0x10b0, 0x0, MASK_ALL_BITS},
{0x10b8, 0x0, MASK_ALL_BITS},
{0x10c0, 0x0, MASK_ALL_BITS},
{0x10f0, 0x0, MASK_ALL_BITS},
{0x10f4, 0x0, MASK_ALL_BITS},
{0x10f8, 0xff, MASK_ALL_BITS},
{0x10fc, 0xffff, MASK_ALL_BITS},
{0x1130, 0x0, MASK_ALL_BITS},
{0x1830, 0x2000000, MASK_ALL_BITS},
{0x14d0, 0x0, MASK_ALL_BITS},
{0x14d4, 0x0, MASK_ALL_BITS},
{0x14d8, 0x0, MASK_ALL_BITS},
{0x14dc, 0x0, MASK_ALL_BITS},
{0x1454, 0x0, MASK_ALL_BITS},
{0x1594, 0x0, MASK_ALL_BITS},
{0x1598, 0x0, MASK_ALL_BITS},
{0x159c, 0x0, MASK_ALL_BITS},
{0x15a0, 0x0, MASK_ALL_BITS},
{0x15a4, 0x0, MASK_ALL_BITS},
{0x15a8, 0x0, MASK_ALL_BITS},
{0x15ac, 0x0, MASK_ALL_BITS},
{0x1600, 0x0, MASK_ALL_BITS},
{0x1604, 0x0, MASK_ALL_BITS},
{0x1608, 0x0, MASK_ALL_BITS},
{0x160c, 0x0, MASK_ALL_BITS},
{0x1610, 0x0, MASK_ALL_BITS},
{0x1614, 0x0, MASK_ALL_BITS},
{0x1618, 0x0, MASK_ALL_BITS},
{0x1624, 0x0, MASK_ALL_BITS},
{0x1690, 0x0, MASK_ALL_BITS},
{0x1694, 0x0, MASK_ALL_BITS},
{0x1698, 0x0, MASK_ALL_BITS},
{0x169c, 0x0, MASK_ALL_BITS},
{0x14b8, 0x6f67, MASK_ALL_BITS},
{0x1630, 0x0, MASK_ALL_BITS},
{0x1634, 0x0, MASK_ALL_BITS},
{0x1638, 0x0, MASK_ALL_BITS},
{0x163c, 0x0, MASK_ALL_BITS},
{0x16b0, 0x0, MASK_ALL_BITS},
{0x16b4, 0x0, MASK_ALL_BITS},
{0x16b8, 0x0, MASK_ALL_BITS},
{0x16bc, 0x0, MASK_ALL_BITS},
{0x16c0, 0x0, MASK_ALL_BITS},
{0x16c4, 0x0, MASK_ALL_BITS},
{0x16c8, 0x0, MASK_ALL_BITS},
{0x16cc, 0x1, MASK_ALL_BITS},
{0x16f0, 0x1, MASK_ALL_BITS},
{0x16f4, 0x0, MASK_ALL_BITS},
{0x16f8, 0x0, MASK_ALL_BITS},
{0x16fc, 0x0, MASK_ALL_BITS}
};
/* MR cmd and addr definitions */
#if defined(CONFIG_DDR4)
struct mv_ddr_mr_data mr_data[] = {
{MRS0_CMD, DDR4_MR0_REG},
{MRS1_CMD, DDR4_MR1_REG},
{MRS2_CMD, DDR4_MR2_REG},
{MRS3_CMD, DDR4_MR3_REG},
{MRS4_CMD, DDR4_MR4_REG},
{MRS5_CMD, DDR4_MR5_REG},
{MRS6_CMD, DDR4_MR6_REG}
};
#else
struct mv_ddr_mr_data mr_data[] = {
{MRS0_CMD, MR0_REG},
{MRS1_CMD, MR1_REG},
{MRS2_CMD, MR2_REG},
{MRS3_CMD, MR3_REG}
};
#endif
/* inverse pads */
static int ddr3_tip_pad_inv(void)
{
u32 sphy, data;
u32 sphy_max = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
u32 ck_swap_ctrl_sphy;
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
for (sphy = 0; sphy < sphy_max; sphy++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy);
if (tm->interface_params[0].
as_bus_params[sphy].is_dqs_swap == 1) {
data = (INVERT_PAD << INV_PAD4_OFFS |
INVERT_PAD << INV_PAD5_OFFS);
/* dqs swap */
ddr3_tip_bus_read_modify_write(0, ACCESS_TYPE_UNICAST,
0, sphy,
DDR_PHY_DATA,
PHY_CTRL_PHY_REG,
data, data);
}
if (tm->interface_params[0].as_bus_params[sphy].
is_ck_swap == 1 && sphy == 0) {
/* TODO: move this code to per platform one */
#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
/* clock swap for both cs0 and cs1 */
data = (INVERT_PAD << INV_PAD2_OFFS |
INVERT_PAD << INV_PAD6_OFFS |
INVERT_PAD << INV_PAD4_OFFS |
INVERT_PAD << INV_PAD5_OFFS);
ck_swap_ctrl_sphy = CK_SWAP_CTRL_PHY_NUM;
ddr3_tip_bus_read_modify_write(0, ACCESS_TYPE_UNICAST,
0, ck_swap_ctrl_sphy,
DDR_PHY_CONTROL,
PHY_CTRL_PHY_REG,
data, data);
#elif defined(A70X0) || defined(A80X0)
/* clock swap for ck0 (cs0) */
data = (INVERT_PAD << INV_PAD4_OFFS |
INVERT_PAD << INV_PAD5_OFFS);
ck_swap_ctrl_sphy = CK0_SWAP_CTRL_PHY_NUM;
ddr3_tip_bus_read_modify_write(0, ACCESS_TYPE_UNICAST,
0, ck_swap_ctrl_sphy,
DDR_PHY_CONTROL,
PHY_CTRL_PHY_REG,
data, data);
/* clock swap for ck1 (cs1) */
#if defined(A70X0)
ck_swap_ctrl_sphy = CK1_A70X0_SWAP_CTRL_PHY_NUM;
#elif defined(A80X0)
ck_swap_ctrl_sphy = CK1_A80X0_SWAP_CTRL_PHY_NUM;
#else /* !A70X0 && !A80X0 */
#pragma message "unknown platform to define ddr clock swap control subphy"
#endif
ddr3_tip_bus_read_modify_write(0, ACCESS_TYPE_UNICAST,
0, ck_swap_ctrl_sphy,
DDR_PHY_CONTROL,
PHY_CTRL_PHY_REG,
data, data);
#else /* !CONFIG_ARMADA_38X && !CONFIG_ARMADA_39X && !A70X0 && !A80X0 */
#pragma message "unknown platform to configure ddr clock swap"
#endif
}
}
return MV_OK;
}
static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
/*
* Update global training parameters by data from user
*/
int ddr3_tip_tune_training_params(u32 dev_num,
struct tune_train_params *params)
{
if (params->ck_delay != PARAM_UNDEFINED)
ck_delay = params->ck_delay;
if (params->phy_reg3_val != PARAM_UNDEFINED)
phy_reg3_val = params->phy_reg3_val;
if (params->g_rtt_nom != PARAM_UNDEFINED)
g_rtt_nom = params->g_rtt_nom;
if (params->g_rtt_wr != PARAM_UNDEFINED)
g_rtt_wr = params->g_rtt_wr;
if (params->g_dic != PARAM_UNDEFINED)
g_dic = params->g_dic;
if (params->g_odt_config != PARAM_UNDEFINED)
g_odt_config = params->g_odt_config;
if (params->g_zpri_data != PARAM_UNDEFINED)
g_zpri_data = params->g_zpri_data;
if (params->g_znri_data != PARAM_UNDEFINED)
g_znri_data = params->g_znri_data;
if (params->g_zpri_ctrl != PARAM_UNDEFINED)
g_zpri_ctrl = params->g_zpri_ctrl;
if (params->g_znri_ctrl != PARAM_UNDEFINED)
g_znri_ctrl = params->g_znri_ctrl;
if (params->g_zpodt_data != PARAM_UNDEFINED)
g_zpodt_data = params->g_zpodt_data;
if (params->g_znodt_data != PARAM_UNDEFINED)
g_znodt_data = params->g_znodt_data;
if (params->g_zpodt_ctrl != PARAM_UNDEFINED)
g_zpodt_ctrl = params->g_zpodt_ctrl;
if (params->g_znodt_ctrl != PARAM_UNDEFINED)
g_znodt_ctrl = params->g_znodt_ctrl;
if (params->g_rtt_park != PARAM_UNDEFINED)
g_rtt_park = params->g_rtt_park;
#if defined(A70X0) || defined(A80X0)
g_rtt_nom = mv_ddr_rtt_nom_get();
if (g_rtt_nom != PARAM_UNDEFINED)
g_rtt_nom <<= MV_DDR_MR1_RTT_NOM_OFFS;
g_rtt_park = mv_ddr_rtt_park_get();
if (g_rtt_park != PARAM_UNDEFINED)
g_rtt_park <<= MV_DDR_MR5_RTT_PARK_OFFS;
g_rtt_wr = mv_ddr_rtt_wr_get();
if (g_rtt_wr != PARAM_UNDEFINED)
g_rtt_wr <<= MV_DDR_MR2_RTT_WR_OFFS;
g_dic = mv_ddr_dic_get();
if (g_dic != PARAM_UNDEFINED)
g_dic <<= MV_DDR_MR1_DIC_OFFS;
#endif
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("DGL parameters: 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n",
g_zpri_data, g_znri_data, g_zpri_ctrl, g_znri_ctrl, g_zpodt_data, g_znodt_data,
g_zpodt_ctrl, g_znodt_ctrl, g_rtt_nom, g_dic, g_odt_config, g_rtt_wr));
return MV_OK;
}
/*
* Configure CS
*/
int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable)
{
u32 data, addr_hi, data_high;
u32 mem_index;
u32 clk_enable;
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
if (tm->clk_enable & (1 << cs_num))
clk_enable = 1;
else
clk_enable = enable;
if (enable == 1) {
data = (tm->interface_params[if_id].bus_width ==
MV_DDR_DEV_WIDTH_8BIT) ? 0 : 1;
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id,
SDRAM_ADDR_CTRL_REG, (data << (cs_num * 4)),
0x3 << (cs_num * 4)));
mem_index = tm->interface_params[if_id].memory_size;
addr_hi = mem_size_config[mem_index] & 0x3;
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id,
SDRAM_ADDR_CTRL_REG,
(addr_hi << (2 + cs_num * 4)),
0x3 << (2 + cs_num * 4)));
data_high = (mem_size_config[mem_index] & 0x4) >> 2;
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id,
SDRAM_ADDR_CTRL_REG,
data_high << (20 + cs_num), 1 << (20 + cs_num)));
/* Enable Address Select Mode */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id,
SDRAM_ADDR_CTRL_REG, 1 << (16 + cs_num),
1 << (16 + cs_num)));
}
switch (cs_num) {
case 0:
case 1:
case 2:
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id,
DUNIT_CTRL_LOW_REG, (clk_enable << (cs_num + 11)),
1 << (cs_num + 11)));
break;
case 3:
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id,
DUNIT_CTRL_LOW_REG, (clk_enable << 15), 1 << 15));
break;
}
return MV_OK;
}
/*
* Init Controller Flow
*/
int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_prm)
{
u32 if_id;
u32 cs_num;
u32 t_ckclk = 0, t_wr = 0, t2t = 0;
u32 data_value = 0, cs_cnt = 0,
mem_mask = 0, bus_index = 0;
enum mv_ddr_speed_bin speed_bin_index = SPEED_BIN_DDR_2133N;
u32 cs_mask = 0;
u32 cl_value = 0, cwl_val = 0;
u32 bus_cnt = 0, adll_tap = 0;
enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
u32 data_read[MAX_INTERFACE_NUM];
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
enum mv_ddr_timing timing;
enum mv_ddr_freq freq = tm->interface_params[0].memory_freq;
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
("Init_controller, do_mrs_phy=%d, is_ctrl64_bit=%d\n",
init_cntr_prm->do_mrs_phy,
init_cntr_prm->is_ctrl64_bit));
if (init_cntr_prm->init_phy == 1) {
CHECK_STATUS(ddr3_tip_configure_phy(dev_num));
}
if (generic_init_controller == 1) {
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
("active IF %d\n", if_id));
mem_mask = 0;
for (bus_index = 0;
bus_index < octets_per_if_num;
bus_index++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_index);
mem_mask |=
tm->interface_params[if_id].
as_bus_params[bus_index].mirror_enable_bitmask;
}
if (mem_mask != 0) {
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_MULTICAST,
if_id, DUAL_DUNIT_CFG_REG, 0,
0x8));
}
speed_bin_index =
tm->interface_params[if_id].
speed_bin_index;
/* t_ckclk is external clock */
t_ckclk = (MEGA / mv_ddr_freq_get(freq));
if (MV_DDR_IS_HALF_BUS_DRAM_MODE(tm->bus_act_mask, octets_per_if_num))
data_value = (0x4000 | 0 | 0x1000000) & ~(1 << 26);
else
data_value = (0x4000 | 0x8000 | 0x1000000) & ~(1 << 26);
/* Interface Bus Width */
/* SRMode */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
SDRAM_CFG_REG, data_value,
0x100c000));
/* Interleave first command pre-charge enable (TBD) */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
SDRAM_OPEN_PAGES_CTRL_REG, (1 << 10),
(1 << 10)));
/* Reset divider_b assert -> de-assert */
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
SDRAM_CFG_REG,
0x0 << PUP_RST_DIVIDER_OFFS,
PUP_RST_DIVIDER_MASK << PUP_RST_DIVIDER_OFFS));
CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
SDRAM_CFG_REG,
0x1 << PUP_RST_DIVIDER_OFFS,
PUP_RST_DIVIDER_MASK << PUP_RST_DIVIDER_OFFS));
/* PHY configuration */
/*
* Postamble Length = 1.5cc, Addresscntl to clk skew
* \BD, Preamble length normal, parralal ADLL enable
*/
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
DRAM_PHY_CFG_REG, 0x28, 0x3e));
if (init_cntr_prm->is_ctrl64_bit) {
/* positive edge */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
DRAM_PHY_CFG_REG, 0x0,
0xff80));
}
/* calibration block disable */
/* Xbar Read buffer select (for Internal access) */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
MAIN_PADS_CAL_MACH_CTRL_REG, 0x1200c,
0x7dffe01c));
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
MAIN_PADS_CAL_MACH_CTRL_REG,
calibration_update_control << 3, 0x3 << 3));
/* Pad calibration control - enable */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
MAIN_PADS_CAL_MACH_CTRL_REG, 0x1, 0x1));
if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) < MV_TIP_REV_3) {
/* DDR3 rank ctrl \96 part of the generic code */
/* CS1 mirroring enable + w/a for JIRA DUNIT-14581 */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
DDR3_RANK_CTRL_REG, 0x27, MASK_ALL_BITS));
}
cs_mask = 0;
data_value = 0x7;
/*
* Address ctrl \96 Part of the Generic code
* The next configuration is done:
* 1) Memory Size
* 2) Bus_width
* 3) CS#
* 4) Page Number
* Per Dunit get from the Map_topology the parameters:
* Bus_width
*/
data_value =
(tm->interface_params[if_id].
bus_width == MV_DDR_DEV_WIDTH_8BIT) ? 0 : 1;
/* create merge cs mask for all cs available in dunit */
for (bus_cnt = 0;
bus_cnt < octets_per_if_num;
bus_cnt++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
cs_mask |=
tm->interface_params[if_id].
as_bus_params[bus_cnt].cs_bitmask;
}
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
("Init_controller IF %d cs_mask %d\n",
if_id, cs_mask));
/*
* Configure the next upon the Map Topology \96 If the
* Dunit is CS0 Configure CS0 if it is multi CS
* configure them both: The Bust_width it\92s the
* Memory Bus width \96 x8 or x16
*/
for (cs_cnt = 0; cs_cnt < MAX_CS_NUM; cs_cnt++) {
ddr3_tip_configure_cs(dev_num, if_id, cs_cnt,
((cs_mask & (1 << cs_cnt)) ? 1
: 0));
}
if (init_cntr_prm->do_mrs_phy) {
/*
* MR0 \96 Part of the Generic code
* The next configuration is done:
* 1) Burst Length
* 2) CAS Latency
* get for each dunit what is it Speed_bin &
* Target Frequency. From those both parameters
* get the appropriate Cas_l from the CL table
*/
cl_value =
tm->interface_params[if_id].
cas_l;
cwl_val =
tm->interface_params[if_id].
cas_wl;
DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
("cl_value 0x%x cwl_val 0x%x\n",
cl_value, cwl_val));
t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get
(speed_bin_index,
SPEED_BIN_TWR), t_ckclk);
data_value =
((cl_mask_table[cl_value] & 0x1) << 2) |
((cl_mask_table[cl_value] & 0xe) << 3);
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
MR0_REG, data_value,
(0x7 << 4) | (1 << 2)));
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
MR0_REG, twr_mask_table[t_wr] << 9,
0x7 << 9));
/*
* MR1: Set RTT and DIC Design GL values
* configured by user
*/
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_MULTICAST,
PARAM_NOT_CARE, MR1_REG,
g_dic | g_rtt_nom, 0x266));
/* MR2 - Part of the Generic code */
/*
* The next configuration is done:
* 1) SRT
* 2) CAS Write Latency
*/
data_value = (cwl_mask_table[cwl_val] << 3);
data_value |=
((tm->interface_params[if_id].
interface_temp ==
MV_DDR_TEMP_HIGH) ? (1 << 7) : 0);
data_value |= g_rtt_wr;
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
MR2_REG, data_value,
(0x7 << 3) | (0x1 << 7) | (0x3 <<
9)));
}
ddr3_tip_write_odt(dev_num, access_type, if_id,
cl_value, cwl_val);
ddr3_tip_set_timing(dev_num, access_type, if_id, freq);
if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) < MV_TIP_REV_3) {
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
DUNIT_CTRL_HIGH_REG, 0x1000119,
0x100017F));
} else {
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
DUNIT_CTRL_HIGH_REG, 0x600177 |
(init_cntr_prm->is_ctrl64_bit ?
CPU_INTERJECTION_ENA_SPLIT_ENA << CPU_INTERJECTION_ENA_OFFS :
CPU_INTERJECTION_ENA_SPLIT_DIS << CPU_INTERJECTION_ENA_OFFS),
0x1600177 | CPU_INTERJECTION_ENA_MASK <<
CPU_INTERJECTION_ENA_OFFS));
}
/* reset bit 7 */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
DUNIT_CTRL_HIGH_REG,
(init_cntr_prm->msys_init << 7), (1 << 7)));
timing = tm->interface_params[if_id].timing;
if (mode_2t != 0xff) {
t2t = mode_2t;
} else if (timing != MV_DDR_TIM_DEFAULT) {
t2t = (timing == MV_DDR_TIM_2T) ? 1 : 0;
} else {
/* calculate number of CS (per interface) */
cs_num = mv_ddr_cs_num_get();
t2t = (cs_num == 1) ? 0 : 1;
}
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
DUNIT_CTRL_LOW_REG, t2t << 3,
0x3 << 3));
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
DDR_TIMING_REG, 0x28 << 9, 0x3f << 9));
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
DDR_TIMING_REG, 0xa << 21, 0xff << 21));
/* move the block to ddr3_tip_set_timing - end */
/* AUTO_ZQC_TIMING */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
ZQC_CFG_REG, (AUTO_ZQC_TIMING | (2 << 20)),
0x3fffff));
CHECK_STATUS(ddr3_tip_if_read
(dev_num, access_type, if_id,
DRAM_PHY_CFG_REG, data_read, 0x30));
data_value =
(data_read[if_id] == 0) ? (1 << 11) : 0;
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
DUNIT_CTRL_HIGH_REG, data_value,
(1 << 11)));
/* Set Active control for ODT write transactions */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_MULTICAST,
PARAM_NOT_CARE, 0x1494, g_odt_config,
MASK_ALL_BITS));
if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) == MV_TIP_REV_3) {
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
0x14a8, 0x900, 0x900));
/* wa: controls control sub-phy outputs floating during self-refresh */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
0x16d0, 0, 0x8000));
}
}
}
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
CHECK_STATUS(ddr3_tip_rank_control(dev_num, if_id));
if (init_cntr_prm->do_mrs_phy)
ddr3_tip_pad_inv();
/* Pad calibration control - disable */
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
MAIN_PADS_CAL_MACH_CTRL_REG, 0x0, 0x1));
CHECK_STATUS(ddr3_tip_if_write
(dev_num, access_type, if_id,
MAIN_PADS_CAL_MACH_CTRL_REG,
calibration_update_control << 3, 0x3 << 3));
}
#if defined(CONFIG_DDR4)
/* dev_num, vref_en, pod_only */
CHECK_STATUS(mv_ddr4_mode_regs_init(dev_num));
CHECK_STATUS(mv_ddr4_sdram_config(dev_num));
#endif /* CONFIG_DDR4 */
if (delay_enable != 0) {
adll_tap = MEGA / (mv_ddr_freq_get(freq) * 64);
ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
}
return MV_OK;
}
/*
* Rank Control Flow
*/
static int ddr3_tip_rev2_rank_control(u32 dev_num, u32 if_id)
{
u32 data_value = 0, bus_cnt = 0;
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
for (bus_cnt = 0; bus_cnt < octets_per_if_num; bus_cnt++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
data_value |= tm->interface_params[if_id].as_bus_params[bus_cnt].
cs_bitmask;
if (tm->interface_params[if_id].as_bus_params[bus_cnt].
mirror_enable_bitmask == 1) {
/*
* Check mirror_enable_bitmask
* If it is enabled, CS + 4 bit in a word to be '1'
*/
if ((tm->interface_params[if_id].as_bus_params[bus_cnt].
cs_bitmask & 0x1) != 0) {
data_value |= tm->interface_params[if_id].
as_bus_params[bus_cnt].
mirror_enable_bitmask << 4;
}
if ((tm->interface_params[if_id].as_bus_params[bus_cnt].
cs_bitmask & 0x2) != 0) {
data_value |= tm->interface_params[if_id].
as_bus_params[bus_cnt].
mirror_enable_bitmask << 5;
}
if ((tm->interface_params[if_id].as_bus_params[bus_cnt].
cs_bitmask & 0x4) != 0) {
data_value |= tm->interface_params[if_id].
as_bus_params[bus_cnt].
mirror_enable_bitmask << 6;
}
if ((tm->interface_params[if_id].as_bus_params[bus_cnt].
cs_bitmask & 0x8) != 0) {
data_value |= tm->interface_params[if_id].
as_bus_params[bus_cnt].
mirror_enable_bitmask << 7;
}
}
}
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, DDR3_RANK_CTRL_REG,
data_value, 0xff));
return MV_OK;
}
static int ddr3_tip_rev3_rank_control(u32 dev_num, u32 if_id)
{
u32 data_value = 0, bus_cnt;
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
for (bus_cnt = 1; bus_cnt < octets_per_if_num; bus_cnt++) {
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
if ((tm->interface_params[if_id].
as_bus_params[0].cs_bitmask !=
tm->interface_params[if_id].
as_bus_params[bus_cnt].cs_bitmask) ||
(tm->interface_params[if_id].
as_bus_params[0].mirror_enable_bitmask !=
tm->interface_params[if_id].
as_bus_params[bus_cnt].mirror_enable_bitmask))
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("WARNING:Wrong configuration for pup #%d CS mask and CS mirroring for all pups should be the same\n",
bus_cnt));
}
data_value |= tm->interface_params[if_id].
as_bus_params[0].cs_bitmask;
data_value |= tm->interface_params[if_id].
as_bus_params[0].mirror_enable_bitmask << 4;
CHECK_STATUS(ddr3_tip_if_write
(dev_num, ACCESS_TYPE_UNICAST, if_id, DDR3_RANK_CTRL_REG,
data_value, 0xff));
return MV_OK;
}
static int ddr3_tip_rank_control(u32 dev_num, u32 if_id)
{
if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) == MV_TIP_REV_2)
return ddr3_tip_rev2_rank_control(dev_num, if_id);
else
return ddr3_tip_rev3_rank_control(dev_num, if_id);
}
/*
* Algorithm Parameters Validation
*/
int ddr3_tip_validate_algo_var(u32 value, u32 fail_value, char *var_name)
{
if (value == fail_value) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("Error: %s is not initialized (Algo Components Validation)\n",
var_name));
return 0;
}
return 1;
}
int ddr3_tip_validate_algo_ptr(void *ptr, void *fail_value, char *ptr_name)
{
if (ptr == fail_value) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("Error: %s is not initialized (Algo Components Validation)\n",
ptr_name));
return 0;
}
return 1;
}
int ddr3_tip_validate_algo_components(u8 dev_num)
{
int status = 1;
/* Check DGL parameters*/
status &= ddr3_tip_validate_algo_var(ck_delay, PARAM_UNDEFINED, "ck_delay");
status &= ddr3_tip_validate_algo_var(phy_reg3_val, PARAM_UNDEFINED, "phy_reg3_val");
status &= ddr3_tip_validate_algo_var(g_rtt_nom, PARAM_UNDEFINED, "g_rtt_nom");
status &= ddr3_tip_validate_algo_var(g_dic, PARAM_UNDEFINED, "g_dic");
status &= ddr3_tip_validate_algo_var(odt_config, PARAM_UNDEFINED, "odt_config");
status &= ddr3_tip_validate_algo_var(g_zpri_data, PARAM_UNDEFINED, "g_zpri_data");
status &= ddr3_tip_validate_algo_var(g_znri_data, PARAM_UNDEFINED, "g_znri_data");
status &= ddr3_tip_validate_algo_var(g_zpri_ctrl, PARAM_UNDEFINED, "g_zpri_ctrl");
status &= ddr3_tip_validate_algo_var(g_znri_ctrl, PARAM_UNDEFINED, "g_znri_ctrl");
status &= ddr3_tip_validate_algo_var(g_zpodt_data, PARAM_UNDEFINED, "g_zpodt_data");
status &= ddr3_tip_validate_algo_var(g_znodt_data, PARAM_UNDEFINED, "g_znodt_data");
status &= ddr3_tip_validate_algo_var(g_zpodt_ctrl, PARAM_UNDEFINED, "g_zpodt_ctrl");
status &= ddr3_tip_validate_algo_var(g_znodt_ctrl, PARAM_UNDEFINED, "g_znodt_ctrl");
/* Check functions pointers */
status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_dunit_mux_select_func,
NULL, "tip_dunit_mux_select_func");
status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_dunit_write,
NULL, "mv_ddr_dunit_write");
status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_dunit_read,
NULL, "mv_ddr_dunit_read");
status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_phy_write,
NULL, "mv_ddr_phy_write");
status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_phy_read,
NULL, "mv_ddr_phy_read");
status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_get_freq_config_info_func,
NULL, "tip_get_freq_config_info_func");