Patch to fix the Crypto design. Reduced clock frequency to 70Mhz, Cha…

…nged CoreAHBL version number and updated the hex file. Also added updated FPExpress project which reflects these changes.
Mi-V-Soft-RISC-V · Sep 10, 2024 · c510835 · c510835
1 parent e244d90
commit c510835
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diff --git a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG4_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG4_BaseDesign.job
diff --git a/Libero_Projects/import/components/cfg4/AHBL_bus.tcl b/Libero_Projects/import/components/cfg4/AHBL_bus.tcl
@@ -2,7 +2,7 @@
 # Family: PolarFire
 # Part Number: MPF300TS-1FCG1152I
 # Create and Configure the core component AHBL_bus
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:6.1.101} -download_core -component_name {AHBL_bus} -params {\
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -download_core -component_name {AHBL_bus} -params {\
 "HADDR_SHG_CFG:1"  \
 "M0_AHBSLOT0ENABLE:true"  \
 "M0_AHBSLOT1ENABLE:true"  \

diff --git a/Libero_Projects/import/components/cfg4/CCC_0.tcl b/Libero_Projects/import/components/cfg4/CCC_0.tcl
@@ -47,7 +47,7 @@ create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:*} -download_core -com
 "GL0_0_FABCLK_USED:true"  \
 "GL0_0_FREQ_SEL:false"  \
 "GL0_0_IS_USED:true"  \
-"GL0_0_OUT_FREQ:80"  \
+"GL0_0_OUT_FREQ:70"  \
 "GL0_0_PHASE_INDEX:0"  \
 "GL0_0_PHASE_SEL:false"  \
 "GL0_0_PLL_PHASE:0"  \